[Qemu-devel] [Bug 1087974] [PATCH 4/5] pixman: fix vnc tight png/jpeg support
This patch adds an x argument to qemu_pixman_linebuf_fill so it can
also be used to convert a partial scanline. Then fix tight + png/jpeg
encoding by passing in the x+y offset, so the data is read from the
correct screen location instead of the upper left corner.
Cc: 1087...@bugs.launchpad.net
Cc: qemu-sta...@nongnu.org
Reported-by: Tim Hardeneck thard...@suse.de
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/vga.c |2 +-
qemu-pixman.c |4 ++--
qemu-pixman.h |2 +-
ui/vnc-enc-tight.c |4 ++--
ui/vnc.c |2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/vga.c b/hw/vga.c
index 2b0200a..c266161 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -2413,7 +2413,7 @@ void ppm_save(const char *filename, struct DisplaySurface
*ds, Error **errp)
}
linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width);
for (y = 0; y height; y++) {
-qemu_pixman_linebuf_fill(linebuf, ds-image, width, y);
+qemu_pixman_linebuf_fill(linebuf, ds-image, width, 0, y);
clearerr(f);
ret = fwrite(pixman_image_get_data(linebuf), 1,
pixman_image_get_stride(linebuf), f);
diff --git a/qemu-pixman.c b/qemu-pixman.c
index 79e175b..e7263fb 100644
--- a/qemu-pixman.c
+++ b/qemu-pixman.c
@@ -52,10 +52,10 @@ pixman_image_t
*qemu_pixman_linebuf_create(pixman_format_code_t format,
}
void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb,
- int width, int y)
+ int width, int x, int y)
{
pixman_image_composite(PIXMAN_OP_SRC, fb, NULL, linebuf,
- 0, y, 0, 0, 0, 0, width, 1);
+ x, y, 0, 0, 0, 0, width, 1);
}
pixman_image_t *qemu_pixman_mirror_create(pixman_format_code_t format,
diff --git a/qemu-pixman.h b/qemu-pixman.h
index bee55eb..3c05c83 100644
--- a/qemu-pixman.h
+++ b/qemu-pixman.h
@@ -31,7 +31,7 @@ pixman_format_code_t qemu_pixman_get_format(PixelFormat *pf);
pixman_image_t *qemu_pixman_linebuf_create(pixman_format_code_t format,
int width);
void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb,
- int width, int y);
+ int width, int x, int y);
pixman_image_t *qemu_pixman_mirror_create(pixman_format_code_t format,
pixman_image_t *image);
void qemu_pixman_image_unref(pixman_image_t *image);
diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c
index 9ae4cab..62d0fde 100644
--- a/ui/vnc-enc-tight.c
+++ b/ui/vnc-enc-tight.c
@@ -1212,7 +1212,7 @@ static int send_jpeg_rect(VncState *vs, int x, int y, int
w, int h, int quality)
buf = (uint8_t *)pixman_image_get_data(linebuf);
row[0] = buf;
for (dy = 0; dy h; dy++) {
-qemu_pixman_linebuf_fill(linebuf, vs-vd-server, w, dy);
+qemu_pixman_linebuf_fill(linebuf, vs-vd-server, w, x, y + dy);
jpeg_write_scanlines(cinfo, row, 1);
}
qemu_pixman_image_unref(linebuf);
@@ -1356,7 +1356,7 @@ static int send_png_rect(VncState *vs, int x, int y, int
w, int h,
if (color_type == PNG_COLOR_TYPE_PALETTE) {
memcpy(buf, vs-tight.tight.buffer + (dy * w), w);
} else {
-qemu_pixman_linebuf_fill(linebuf, vs-vd-server, w, dy);
+qemu_pixman_linebuf_fill(linebuf, vs-vd-server, w, x, y + dy);
}
png_write_row(png_ptr, buf);
}
diff --git a/ui/vnc.c b/ui/vnc.c
index ba30362..04afcff 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -2569,7 +2569,7 @@ static int vnc_refresh_server_surface(VncDisplay *vd)
uint8_t *server_ptr;
if (vd-guest.format != VNC_SERVER_FB_FORMAT) {
-qemu_pixman_linebuf_fill(tmpbuf, vd-guest.fb, width, y);
+qemu_pixman_linebuf_fill(tmpbuf, vd-guest.fb, width, 0, y);
guest_ptr = (uint8_t *)pixman_image_get_data(tmpbuf);
} else {
guest_ptr = guest_row;
--
1.7.1
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1087974
Title:
[regression] vnc tight png produces garbled output
Status in QEMU:
New
Bug description:
VNC Tight PNG compression did work fine two or three month ago but don't
anymore. Now when Tight PNG is used parts of the desktop are shown but they are
scrambled together.
I have always tested this feature against QEMU git with noVNC by only
allowing Tight PNG compression.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1087974/+subscriptions
[Qemu-devel] [PATCH 0/5] pixman patch queue
Hi, Pixman patch queue, fixing vnc tight/png and tackeling build issues. cheers, Gerd Gerd Hoffmann (5): pixman: fix version check for PIXMAN_TYPE_BGRA Revert pixman: require 0.18.4 or newer pixman: update internal copy to pixman-0.28.2 pixman: fix vnc tight png/jpeg support console: clip update rectangle configure |4 ++-- console.h | 10 ++ hw/vga.c |2 +- pixman |2 +- qemu-pixman.c |6 +++--- qemu-pixman.h |2 +- ui/vnc-enc-tight.c |4 ++-- ui/vnc.c |2 +- 8 files changed, 21 insertions(+), 11 deletions(-)
[Qemu-devel] [PATCH 2/5] Revert pixman: require 0.18.4 or newer
This reverts commit 288fa40736e6eb63132d01aa6dc21ee831b796ae.
The only reason old pixman versions didn't work was the missing
PIXMAN_TYPE_BGRA, which is properly #ifdef'ed now. So we don't
have to require a minimum pixman version.
Conflicts:
configure
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
configure |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index 38b1cc6..ecdb33a 100755
--- a/configure
+++ b/configure
@@ -2127,7 +2127,7 @@ fi
# pixman support probe
if test $pixman = ; then
- if $pkg_config --atleast-version=0.18.4 pixman-1 /dev/null 21; then
+ if $pkg_config pixman-1 /dev/null 21; then
pixman=system
else
pixman=internal
@@ -2138,7 +2138,7 @@ if test $pixman = system; then
pixman_libs=`$pkg_config --libs pixman-1 2/dev/null`
else
if test ! -d ${source_path}/pixman/pixman; then
-echo ERROR: pixman not present (or older than 0.18.4). Your options:
+echo ERROR: pixman not present. Your options:
echo (1) Preferred: Install the pixman devel package (any recent
echo distro should have packages as Xorg needs pixman too).
echo (2) Fetch the pixman submodule, using:
--
1.7.1
[Qemu-devel] [PATCH 3/5] pixman: update internal copy to pixman-0.28.2
Some w64 fixes by Stefan Weil found their way into 0.28.2, so update the internal copy to that version to improve windows support. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- pixman |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/pixman b/pixman index 97336fa..a5e5179 16 --- a/pixman +++ b/pixman @@ -1 +1 @@ -Subproject commit 97336fad32acf802003855cd8bd6477fa49a12e3 +Subproject commit a5e5179b5624c99c812e9bf6e7b907e355a811e8 -- 1.7.1
Re: [Qemu-devel] [PATCH 3/3] qtest: add migrate-test
- Messaggio originale -
Da: Jason Baron jba...@redhat.com
A: qemu-devel@nongnu.org
Cc: aligu...@us.ibm.com, kw...@redhat.com, pbonz...@redhat.com,
quint...@redhat.com
Inviato: Giovedì, 13 dicembre 2012 23:02:22
Oggetto: [PATCH 3/3] qtest: add migrate-test
From: Jason Baron jba...@redhat.com
Tests a single 'pc' machine migration on the same host. Currently,
the test
fail for q35 since the ahci controller doesn't yet migrate. Will add
support
for q35 once the ahci support is accepted.
Would be nice to extend the test matrix to various machine versions,
but that
requires building multiple qemu binaries, which is a bit awkward in
the
context of qtest. Testing migration between different machine
versions with the
same binary doesn't seem too useful.
Signed-off-by: Jason Baron jba...@redhat.com
---
tests/Makefile |2 +
tests/migrate-test.c | 140
++
2 files changed, 142 insertions(+), 0 deletions(-)
create mode 100644 tests/migrate-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 30a101d..d50dff0 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -25,6 +25,7 @@ check-block-$(CONFIG_POSIX) +=
tests/qemu-iotests-quick.sh
check-qtest-i386-y = tests/fdc-test$(EXESUF)
check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/migrate-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
check-qtest-sparc-y = tests/m48t59-test$(EXESUF)
check-qtest-sparc64-y = tests/m48t59-test$(EXESUF)
@@ -78,6 +79,7 @@ tests/rtc-test$(EXESUF): tests/rtc-test.o
$(trace-obj-y) qstring.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o $(trace-obj-y)
tests/fdc-test$(EXESUF): tests/fdc-test.o tests/libqtest.o
$(trace-obj-y) qstring.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o tests/libqtest.o
$(trace-obj-y) qstring.o
+tests/migrate-test$(EXESUF): tests/migrate-test.o $(test-qapi-obj-y)
$(qom-obj-y)
# QTest rules
diff --git a/tests/migrate-test.c b/tests/migrate-test.c
new file mode 100644
index 000..c62d5af
--- /dev/null
+++ b/tests/migrate-test.c
@@ -0,0 +1,140 @@
+/*
+ * Migration tests
+ *
+ * Copyright Red Hat, Inc. 2012
+ *
+ * Authors:
+ * Jason Baron jba...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2
or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+#include libqtest.h
+
+#include glib.h
+#include stdio.h
+#include string.h
+#include stdlib.h
+#include unistd.h
+
+#include qjson.h
+#include error.h
+#include qemu/object.h
+#include qdict.h
+#include qbool.h
+
+#define migrate_assert(cond) \
+if (!(cond)) { \
+migrate_cleanup(); \
+fprintf(stderr, %s:%d %s\n, __FILE__, __LINE__, #cond); \
+abort(); \
+}\
+
+static QTestState *mach_a;
+static QTestState *mach_b;
+
+static void migrate_cleanup(void)
+{
+if (mach_a) {
+qtest_quit(mach_a);
+}
+if (mach_b) {
+qtest_quit(mach_b);
+}
+}
+
+static int expected_qobject(QObject *obj, qtype_code type)
+{
+if (!obj) {
+return 0;
+}
+return (qobject_type(obj) == type);
+}
+
+/*
+ * Return vals:
+ * 1: yes
+ * 0: no
+ * -1: retry
+ */
+static int is_running(QTestState *mch)
+{
+QString *resp = qstring_new();
+QObject *resp_obj;
+QObject *ret_obj;
+QObject *run_obj;
+int ret;
+
+resp = qstring_new();
+qtest_qmp_resp(mch, resp, { 'execute': 'query-status' },
NULL);
+
+resp_obj = qobject_from_json(qstring_get_str(resp));
+if (!expected_qobject(resp_obj, QTYPE_QDICT)) {
+ret = -1;
+goto out;
+}
+
+ret_obj = qdict_get(qobject_to_qdict(resp_obj), return);
+if (!expected_qobject(ret_obj, QTYPE_QDICT)) {
+ret = -1;
+goto out;
+}
+
+run_obj = qdict_get(qobject_to_qdict(ret_obj), running);
+if (!expected_qobject(run_obj, QTYPE_QBOOL)) {
+ret = -1;
+goto out;
+}
+ret = qbool_get_int(qobject_to_qbool(run_obj));
+
+out:
+qobject_decref(resp_obj);
+QDECREF(resp);
+return ret;
+}
+
+#define SLEEP_INTERVAL 2
+/* Abort after 2 minutes */
+#define SLEEP_MAX (60 * 2)
+
+static void migrate_a_to_b(void)
Do you think this function could be turned into a libqtest call?
It would take mach_a as an argument, add -incoming tcp:localhost:
to the command line of mach_a, use that to spawn mach_b, and
return mach_b as the return value (or perhaps change mach_a to
refer to the new machine).
The reason is that I can anticipate having many migration qtests,
at least one for every subsection we ever had to add.
Paolo
+{
+int a_run = 0;
+int b_run = 0;
+int iter = 0;
+
+/* is running on A ? */
+migrate_assert(is_running(mach_a));
+
+
Re: [Qemu-devel] [RFC PATCH] Allow building without graphics support
Hi, No, they are with prefix, just not in $PATH. I have more than one powerpc-linux-gnu toolchain and I don't want to mess with my $PATH constantly to choose between them. # ls -l /usr/bin/*-gcc -rwxr-xr-x. 2 root root 264112 Aug 23 2011 /usr/bin/i686-pc-mingw32-gcc -rwxr-xr-x. 2 root root 268216 Oct 18 18:24 /usr/bin/x86_64-redhat-linux-gcc I think the second part (pc / redhat) can be choosen pretty freely when building gcc, so you could name your cross compilers differently, then have them in PATH and pick by name instead of typing full paths. No, it's real name is /home/scott/fsl/tc/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu-gcc ./configure --cross-prefix=/home/scott/fsl/tc/gcc-4.5.55-eglibc-2.11.55/powerpc-linux-gnu/bin/powerpc-linux-gnu- make ? cheers, Gerd
Re: [Qemu-devel] [RFC PATCH] Allow building without graphics support
Hi,
Yes, I could manually install it, though then I get to deal with telling
the pixman build exactly where to install itself, and repeating the
process for each toolchain and multilib-variant thereof.
That part is easy too. You just need ${cross_prefix}-pkg-config.
A simple two-liner script which sets PKG_CONFIG_PATH, then calls
/usr/bin/pkg-config. That will not only work for pixman, but all
libraries detected via pkg-config by configure.
cheers,
Gerd
Re: [Qemu-devel] [PATCH] build: Use separate makefile for trace/
Yeah, make it oslib-obj-y += trace/ and get rid of trace-obj-y. Mmm, but according to Makefile.objs: oslib-obj-y is code depending on the OS (win32 vs posix) True... I'd like to simplify this jungle sooner or later though. We can keep trace-obj-y, but please do leave out qemu-timer-common.o I'm not sure how the subdir magic treats paths, but mapping all paths in final vars into their respective absolute path should simplify things. Difficult to do in make. :( Among many other things, AFAIR the linux kernel build system uses absolute paths, but I think it also uses make to get into each subdirectory (as opposed to QEMU), which I simplifies coding such a build system. We already use recursive make to compile each target. I think the current QEMU build system is a good balance between non-recursive and recursive make. I'm sure this has already been previously discussed to the point of extenuation, but what are the reasons for not using autotools? Autoconf - no point, but someone needs to do the work. Automake - the build system is just too different. Libtool - using it already. :) Ok, so it's not something against the suite per-se, but about porting work. The thing I like about automake is that it provides a clear set of vars to manage the per-dir builds, thanks to using a per-dir $(MAKE); but I'm not sure how the per-target build would be managed (except by having a separate configure+make for each of them). Yes, that would be it. Even an autoconf conversion probably would have to use separate configure scripts for the global project and for each target. This could also be provided by having the QEMU build infrastructure use $(MAKE) to enter into each directory, and having it produce an ar file (or a set of them) with a standard name as a result (using libtool). Doesn't need to use libtool. Static libraries are just fine. The problem is that ar doesn't work well with constructors, which we use for module.c. It is what QEMU used to use, but Andreas moved away a couple of years ago and I think it is an improvement. But I'm not sure how well would that work when building in Windows (is libtool available there?). Yes. Paolo
[Qemu-devel] [PATCH 2/3] chardev: fix QemuOpts lifecycle
qemu_chr_new_from_opts handles QemuOpts release now, so callers don't
have to worry. It will either be saved in CharDriverState, then
released in qemu_chr_delete, or in the error case released instantly.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
qemu-char.c | 15 ++-
qemu-char.h |1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index 5b91228..876714f 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2774,13 +2774,13 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
if (qemu_opts_id(opts) == NULL) {
error_setg(errp, chardev: no id specified\n);
-return NULL;
+goto err;
}
if (qemu_opt_get(opts, backend) == NULL) {
error_setg(errp, chardev: \%s\ missing backend\n,
qemu_opts_id(opts));
-return NULL;
+goto err;
}
for (i = 0; i ARRAY_SIZE(backend_table); i++) {
if (strcmp(backend_table[i].name, qemu_opt_get(opts, backend)) == 0)
@@ -2789,14 +2789,14 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
if (i == ARRAY_SIZE(backend_table)) {
error_setg(errp, chardev: backend \%s\ not found\n,
qemu_opt_get(opts, backend));
-return NULL;
+goto err;
}
chr = backend_table[i].open(opts);
if (!chr) {
error_setg(errp, chardev: opening backend \%s\ failed\n,
qemu_opt_get(opts, backend));
-return NULL;
+goto err;
}
if (!chr-filename)
@@ -2817,7 +2817,12 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
chr-avail_connections = 1;
}
chr-label = g_strdup(qemu_opts_id(opts));
+chr-opts = opts;
return chr;
+
+err:
+qemu_opts_del(opts);
+return NULL;
}
CharDriverState *qemu_chr_new(const char *label, const char *filename, void
(*init)(struct CharDriverState *s))
@@ -2843,7 +2848,6 @@ CharDriverState *qemu_chr_new(const char *label, const
char *filename, void (*in
if (chr qemu_opt_get_bool(opts, mux, 0)) {
monitor_init(chr, MONITOR_USE_READLINE);
}
-qemu_opts_del(opts);
return chr;
}
@@ -2875,6 +2879,7 @@ void qemu_chr_delete(CharDriverState *chr)
chr-chr_close(chr);
g_free(chr-filename);
g_free(chr-label);
+qemu_opts_del(chr-opts);
g_free(chr);
}
diff --git a/qemu-char.h b/qemu-char.h
index d7eed34..f984071 100644
--- a/qemu-char.h
+++ b/qemu-char.h
@@ -75,6 +75,7 @@ struct CharDriverState {
char *filename;
int opened;
int avail_connections;
+QemuOpts *opts;
QTAILQ_ENTRY(CharDriverState) next;
};
--
1.7.1
[Qemu-devel] [PATCH 1/3] chardev: add error reporting for qemu_chr_new_from_opts
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
qemu-char.c | 24 +++-
qemu-char.h |3 ++-
vl.c|9 ++---
3 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index 242b799..5b91228 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2766,19 +2766,20 @@ static const struct {
};
CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
-void (*init)(struct CharDriverState *s))
+void (*init)(struct CharDriverState *s),
+Error **errp)
{
CharDriverState *chr;
int i;
if (qemu_opts_id(opts) == NULL) {
-fprintf(stderr, chardev: no id specified\n);
+error_setg(errp, chardev: no id specified\n);
return NULL;
}
if (qemu_opt_get(opts, backend) == NULL) {
-fprintf(stderr, chardev: \%s\ missing backend\n,
-qemu_opts_id(opts));
+error_setg(errp, chardev: \%s\ missing backend\n,
+ qemu_opts_id(opts));
return NULL;
}
for (i = 0; i ARRAY_SIZE(backend_table); i++) {
@@ -2786,15 +2787,15 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
break;
}
if (i == ARRAY_SIZE(backend_table)) {
-fprintf(stderr, chardev: backend \%s\ not found\n,
-qemu_opt_get(opts, backend));
+error_setg(errp, chardev: backend \%s\ not found\n,
+ qemu_opt_get(opts, backend));
return NULL;
}
chr = backend_table[i].open(opts);
if (!chr) {
-fprintf(stderr, chardev: opening backend \%s\ failed\n,
-qemu_opt_get(opts, backend));
+error_setg(errp, chardev: opening backend \%s\ failed\n,
+ qemu_opt_get(opts, backend));
return NULL;
}
@@ -2824,6 +2825,7 @@ CharDriverState *qemu_chr_new(const char *label, const
char *filename, void (*in
const char *p;
CharDriverState *chr;
QemuOpts *opts;
+Error *err = NULL;
if (strstart(filename, chardev:, p)) {
return qemu_chr_find(p);
@@ -2833,7 +2835,11 @@ CharDriverState *qemu_chr_new(const char *label, const
char *filename, void (*in
if (!opts)
return NULL;
-chr = qemu_chr_new_from_opts(opts, init);
+chr = qemu_chr_new_from_opts(opts, init, err);
+if (error_is_set(err)) {
+fprintf(stderr, %s\n, error_get_pretty(err));
+error_free(err);
+}
if (chr qemu_opt_get_bool(opts, mux, 0)) {
monitor_init(chr, MONITOR_USE_READLINE);
}
diff --git a/qemu-char.h b/qemu-char.h
index a121e04..d7eed34 100644
--- a/qemu-char.h
+++ b/qemu-char.h
@@ -89,7 +89,8 @@ struct CharDriverState {
* Returns: a new character backend
*/
CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
-void (*init)(struct CharDriverState *s));
+void (*init)(struct CharDriverState *s),
+Error **errp);
/**
* @qemu_chr_new:
diff --git a/vl.c b/vl.c
index a3ab384..353817a 100644
--- a/vl.c
+++ b/vl.c
@@ -2057,11 +2057,14 @@ static int device_init_func(QemuOpts *opts, void
*opaque)
static int chardev_init_func(QemuOpts *opts, void *opaque)
{
-CharDriverState *chr;
+Error *local_err = NULL;
-chr = qemu_chr_new_from_opts(opts, NULL);
-if (!chr)
+qemu_chr_new_from_opts(opts, NULL, local_err);
+if (error_is_set(local_err)) {
+fprintf(stderr, %s\n, error_get_pretty(local_err));
+error_free(local_err);
return -1;
+}
return 0;
}
--
1.7.1
[Qemu-devel] [PATCH 3/3] chardev: add hotplug support.
This patch adds chardev_add_file, chardev_add_tty and chardev_remove
monitor commands.
chardev_add_file and chardev_add_tty expect an id and a path, they
create a file/tty chardev.
chardev_del just takes an id argument and zaps the chardev specified.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hmp-commands.hx | 44 +++
hmp.c| 29
hmp.h|3 ++
qapi-schema.json | 43 ++
qemu-char.c | 41 +
qemu-char.h |2 +
qmp-commands.hx | 76 ++
7 files changed, 238 insertions(+), 0 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 010b8c9..82a855a 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1485,6 +1485,50 @@ passed since 1970, i.e. unix epoch.
ETEXI
{
+.name = chardev_add_file,
+.args_type = id:s,path:s,
+.params = id path ,
+.help = add file chardev,
+.mhandler.cmd = hmp_chardev_add_file,
+},
+
+STEXI
+@item chardev_add_file id path
+@findex chardev_add_file
+
+ETEXI
+
+{
+.name = chardev_add_tty,
+.args_type = id:s,path:s,
+.params = id path ,
+.help = add tty chardev,
+.mhandler.cmd = hmp_chardev_add_tty,
+},
+
+STEXI
+@item chardev_add_tty id path
+@findex chardev_add_tty
+
+ETEXI
+
+{
+.name = chardev_remove,
+.args_type = id:s,
+.params = id,
+.help = remove chardev,
+.mhandler.cmd = hmp_chardev_remove,
+},
+
+STEXI
+@item chardev_remove id
+@findex chardev_remove
+
+Removes the chardev @var{id}.
+
+ETEXI
+
+{
.name = info,
.args_type = item:s?,
.params = [subcommand],
diff --git a/hmp.c b/hmp.c
index 180ba2b..8780e7c 100644
--- a/hmp.c
+++ b/hmp.c
@@ -1335,3 +1335,32 @@ void hmp_nbd_server_stop(Monitor *mon, const QDict
*qdict)
qmp_nbd_server_stop(errp);
hmp_handle_error(mon, errp);
}
+
+static void hmp_chardev_add_path(Monitor *mon, const QDict *qdict,
+ const char *backend)
+{
+const char *id = qdict_get_str(qdict, args);
+const char *path = qdict_get_str(qdict, path);
+Error *local_err = NULL;
+
+qmp_chardev_add_path(id, path, backend, local_err);
+hmp_handle_error(mon, local_err);
+}
+
+void hmp_chardev_add_file(Monitor *mon, const QDict *qdict)
+{
+hmp_chardev_add_path(mon, qdict, file);
+}
+
+void hmp_chardev_add_tty(Monitor *mon, const QDict *qdict)
+{
+hmp_chardev_add_path(mon, qdict, tty);
+}
+
+void hmp_chardev_remove(Monitor *mon, const QDict *qdict)
+{
+Error *local_err = NULL;
+
+qmp_chardev_remove(qdict_get_str(qdict, id), local_err);
+hmp_handle_error(mon, local_err);
+}
diff --git a/hmp.h b/hmp.h
index 0ab03be..8cd50d1 100644
--- a/hmp.h
+++ b/hmp.h
@@ -80,5 +80,8 @@ void hmp_screen_dump(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_start(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_add(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_stop(Monitor *mon, const QDict *qdict);
+void hmp_chardev_add_file(Monitor *mon, const QDict *qdict);
+void hmp_chardev_add_tty(Monitor *mon, const QDict *qdict);
+void hmp_chardev_remove(Monitor *mon, const QDict *qdict);
#endif
diff --git a/qapi-schema.json b/qapi-schema.json
index 5dfa052..34c0e58 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -3017,3 +3017,46 @@
# Since: 1.3.0
##
{ 'command': 'nbd-server-stop' }
+
+##
+# @chardev-add-file:
+#
+# Add a file chardev
+#
+# @id: the chardev's ID, must be unique
+# @path: file path
+#
+# Returns: Nothing on success
+#
+# Since: 1.3.0
+##
+{ 'command': 'chardev-add-file', 'data': {'id' : 'str',
+ 'path' : 'str' } }
+
+##
+# @chardev-add-tty:
+#
+# Add a terminal chardev
+#
+# @id: the chardev's ID, must be unique
+# @path: device path
+#
+# Returns: Nothing on success
+#
+# Since: 1.3.0
+##
+{ 'command': 'chardev-add-tty', 'data': {'id' : 'str',
+ 'path' : 'str' } }
+
+##
+# @chardev-remove:
+#
+# Remove a chardev
+#
+# @id: the chardev's ID, must exist and not be in use
+#
+# Returns: Nothing on success
+#
+# Since: 1.3.0
+##
+{ 'command': 'chardev-remove', 'data': {'id': 'str'} }
diff --git a/qemu-char.c b/qemu-char.c
index 876714f..169743b 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2922,3 +2922,44 @@ CharDriverState *qemu_char_get_next_serial(void)
return serial_hds[next_serial++];
}
+void qmp_chardev_add_path(const char *id, const char *path,
+ const char *backend, Error **errp)
+{
+QemuOpts *opts;
+
+opts = qemu_opts_create(qemu_find_opts(chardev), id, 1, errp);
+if (error_is_set(errp)) {
+return;
+}
+
+qemu_opt_set(opts, path, path);
+qemu_opt_set(opts,
[Qemu-devel] [PATCH RESENT 0/3] chardev hotplug patch series
Hi, Got stuck in discussions 1.3 freeze. Resending series to resume merge effort, almost unmodified, only rebased trivial conflicts resolved. please review comment, Gerd Gerd Hoffmann (3): chardev: add error reporting for qemu_chr_new_from_opts chardev: fix QemuOpts lifecycle chardev: add hotplug support. hmp-commands.hx | 44 + hmp.c| 29 +++ hmp.h|3 ++ qapi-schema.json | 43 + qemu-char.c | 80 - qemu-char.h |6 +++- qmp-commands.hx | 76 +++ vl.c |9 -- 8 files changed, 272 insertions(+), 18 deletions(-)
Re: [Qemu-devel] [PATCH 3/3] target-i386: replace cpuid_*features fields with a feature word array
On Wed, 12 Dec 2012 20:22:26 -0200 Eduardo Habkost ehabk...@redhat.com wrote: This replaces the feature-bit fields on both X86CPU and x86_def_t structs with an array. With this, we will be able to simplify code that simply does the same operation on all feature words (e.g. kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), and CPU feature-bit property lookup/registration). do you have a patch that simplifies kvm_check_features_against_host() using this? -- 1.7.11.7 -- Regards, Igor
Re: [Qemu-devel] [PATCH 1/3] target-i386: add EXT2_PPRO_FEATURES #define
On Wed, 12 Dec 2012 20:22:24 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
Instead of repeating the (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES)
expression everywhere, use EXT2_PPRO_FEATURES.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
Reviewed-by: Igor Mammedov imamm...@redhat.com
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 546c86a..a2ee8bb 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -303,6 +303,7 @@ typedef struct x86_def_t {
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
CPUID_PAE | CPUID_SEP | CPUID_APIC)
+#define EXT2_PPRO_FEATURES (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES)
#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
@@ -350,7 +351,7 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
-.ext2_features = (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) |
+.ext2_features = EXT2_PPRO_FEATURES |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
@@ -370,7 +371,7 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_PSE36 | CPUID_VME | CPUID_HT,
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
CPUID_EXT_POPCNT,
-.ext2_features = (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) |
+.ext2_features = EXT2_PPRO_FEATURES |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
@@ -421,7 +422,7 @@ static x86_def_t builtin_x86_defs[] = {
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
-.ext2_features = (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) |
+.ext2_features = EXT2_PPRO_FEATURES |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG,
CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
@@ -456,7 +457,7 @@ static x86_def_t builtin_x86_defs[] = {
.features = PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
.ext_features = CPUID_EXT_SSE3,
-.ext2_features = PPRO_FEATURES CPUID_EXT2_AMD_ALIASES,
+.ext2_features = EXT2_PPRO_FEATURES,
.ext3_features = 0,
.xlevel = 0x8008,
.model_id = Common 32-bit KVM processor
@@ -538,7 +539,7 @@ static x86_def_t builtin_x86_defs[] = {
.stepping = 3,
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
CPUID_MCA,
-.ext2_features = (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) |
+.ext2_features = EXT2_PPRO_FEATURES |
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
.xlevel = 0x8008,
},
@@ -558,7 +559,7 @@ static x86_def_t builtin_x86_defs[] = {
/* Some CPUs got no CPUID_SEP */
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3
|
CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
-.ext2_features = (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) |
+.ext2_features = EXT2_PPRO_FEATURES |
CPUID_EXT2_NX,
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x800A,
--
1.7.11.7
--
Regards,
Igor
Re: [Qemu-devel] [PATCH 1/2] pixman: require 0.16.4 as minimum version
On 14.12.2012, at 08:54, Gerd Hoffmann kra...@redhat.com wrote: Hi, If you send me a fix for 6e72719e721a40fe1224701ca10edc1caf0cd708 I'll go revert 288fa40736e6eb63132d01aa6dc21ee831b796ae 6e72719 is perfectly sane, because it brings consistency into the file. Now both users of PIXMAN_TYPE_BGRA are guarded by the same #ifdef. Both users? Hello? Its two *different* types: PIXMAN_TYPE_RGBA and PIXMAN_TYPE_BGRA. And, yes, they have been added in different versions. So guarding them with the *same* #ifdef is wrong. Ugh :(. Sorry then. #ifdef PIXMAN_TYPE_BGRA It's a enum, not a #define, so this isn't going to fly. In my old versions it's a define... Alex cheers, Gerd
[Qemu-devel] [PATCH] qemu-char: inheriting ptys and imporve output from -serial pty
When controlling a qemu instance from another program, it's hard to know which serial port or monitor device is redirected to which pty. With more than one device using pty a lot of guesswork is involved. $ ./x86_64-softmmu/qemu-system-x86_64 -serial pty -serial pty -monitor pty char device redirected to /dev/pts/5 char device redirected to /dev/pts/6 char device redirected to /dev/pts/7 Although we can find out what everything else is connected to by the info chardev with -monitor stdio in the command line, It'd be very useful to be able to have qemu inherit pseudo-tty file descriptors so they could just be specified on the command line like: $ ./x86_64-softmmu/qemu-system-x86_64 -serial pty -serial pty -monitor pty char device compat_monitor0 redirected to /dev/pts/5 char device serial0 redirected to /dev/pts/6 char device serial1 redirected to /dev/pts/7 Referred link: https://bugs.launchpad.net/qemu/+bug/938552 Reported-by: Craig Ringer ring...@gmail.com Signed-off-by: Lei Li li...@linux.vnet.ibm.com --- qemu-char.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/qemu-char.c b/qemu-char.c index 242b799..2b0f5f4 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -981,6 +981,7 @@ static CharDriverState *qemu_chr_open_pty(QemuOpts *opts) CharDriverState *chr; PtyCharDriver *s; struct termios tty; +char *label; int master_fd, slave_fd, len; #if defined(__OpenBSD__) || defined(__DragonFly__) char pty_name[PATH_MAX]; @@ -1006,7 +1007,8 @@ static CharDriverState *qemu_chr_open_pty(QemuOpts *opts) chr-filename = g_malloc(len); snprintf(chr-filename, len, pty:%s, q_ptsname(master_fd)); qemu_opt_set(opts, path, q_ptsname(master_fd)); -fprintf(stderr, char device redirected to %s\n, q_ptsname(master_fd)); +label = g_strdup(qemu_opts_id(opts)); +fprintf(stderr, char device %s redirected to %s\n, label, q_ptsname(master_fd)); s = g_malloc0(sizeof(PtyCharDriver)); chr-opaque = s; -- 1.7.7.6
Re: [Qemu-devel] [PATCH v13 0/7] libqblock qemu block layer library
v13: Moved another function into stubs, added xml rule in tests/makefile, little changes in patch 4, 6, 7. Wenchao Xia (7): Hi Paolo, Do you think a rebase of the libqblock is needed? It have been quite a time without comments. -- Best Regards Wenchao Xia
Re: [Qemu-devel] [PATCH v13 0/7] libqblock qemu block layer library
Il 14/12/2012 11:06, Wenchao Xia ha scritto: Hi Paolo, Do you think a rebase of the libqblock is needed? It have been quite a time without comments. I was hoping that other people would jump in. :) Paolo
Re: [Qemu-devel] [PATCH 2/2] target-i386: make cpu_x86_create() get Error argument
On Wed, 12 Dec 2012 16:16:23 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
Instead of forcing the caller to guess what went wrong while creating
the CPU object, return error information in a Error argument.
Also, as cpu_x86_create() won't print error messages itself anymore,
change cpu_x86_init() to print any error returned by cpu_x86_create()
or cpu_x86_realize().
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu.c| 8 ++--
target-i386/cpu.h| 2 +-
target-i386/helper.c | 21 ++---
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b242bf1..fba872d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1542,7 +1542,7 @@ static void filter_features_for_kvm(X86CPU *cpu)
/* Create and initialize a X86CPU object, based on the full CPU model string
* (that may include +feature,-feature,feature=xxx feature strings)
*/
-X86CPU *cpu_x86_create(const char *cpu_model)
+X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
{
X86CPU *cpu;
CPUX86State *env;
@@ -1559,12 +1559,14 @@ X86CPU *cpu_x86_create(const char *cpu_model)
model_pieces = g_strsplit(cpu_model, ,, 2);
if (!model_pieces[0]) {
+error_setg(errp, invalid CPU model string: %s, cpu_model);
goto error;
}
name = model_pieces[0];
features = model_pieces[1];
if (cpu_x86_find_by_name(def, name) 0) {
+error_setg(errp, CPU model not found: %s, name);
goto error;
}
@@ -1575,13 +1577,15 @@ X86CPU *cpu_x86_create(const char *cpu_model)
def-svm_features,
def-cpuid_7_0_ebx_features);
if (cpu_x86_parse_featurestr(def, features) 0) {
+error_setg(errp, Error parsing feature string: %s,
+ features ? features : (none));
It could be simplified, it shouldn't get here if features == NULL
goto error;
}
cpudef_2_x86_cpu(cpu, def, error);
if (error) {
-fprintf(stderr, %s\n, error_get_pretty(error));
+error_propagate(errp, error);
Why do it here but not above?
error_free(error);
goto error;
}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
[...]
X86CPU *cpu_x86_init(const char *cpu_model)
{
-X86CPU *cpu;
+X86CPU *cpu = NULL;
Error *error = NULL;
-cpu = cpu_x86_create(cpu_model);
-if (!cpu) {
-return NULL;
+cpu = cpu_x86_create(cpu_model, error);
+if (error) {
+goto error;
}
x86_cpu_realize(OBJECT(cpu), error);
if x86_cpu_realize() behave as visit* functions, i.e. return early if
error has been already set, error check goto could be removed here
and above and consolidated at function exit.
if (error) {
-error_free(error);
-object_delete(OBJECT(cpu));
-return NULL;
+goto error;
}
return cpu;
+
+error:
+if (cpu) {
+object_delete(OBJECT(cpu));
+}
+error_report(%s, error_get_pretty(error));
+error_free(error);
+return NULL;
}
#if !defined(CONFIG_USER_ONLY)
--
1.7.11.7
--
Regards,
Igor
Re: [Qemu-devel] [PATCH 1/2] target-i386: move CPU object creation to cpu.c
On Wed, 12 Dec 2012 16:16:22 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
As we will need to create the CPU object after splitting the CPU model
string (because we're going to use different subclasses for each CPU
model), move the CPU object creation to cpu_x86_register(), and at the
same time rename cpu_x86_register() to cpu_x86_create().
This will also simplify the CPU creation code to a trivial
cpu_x86_create()+cpu_x86_realize() sequence. This will be useful for
code that have to set additional properties before cpu_x86_realize() is
called (e.g. the PC CPU initialization code, that needs to set APIC IDs
depending on the CPU cores/threads topology).
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu.c| 16 +---
target-i386/cpu.h| 2 +-
target-i386/helper.c | 9 ++---
3 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 3b9bbfe..b242bf1 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1539,13 +1539,22 @@ static void filter_features_for_kvm(X86CPU *cpu)
}
#endif
-int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
+/* Create and initialize a X86CPU object, based on the full CPU model string
+ * (that may include +feature,-feature,feature=xxx feature strings)
feature format of cpu_model string misses just 'feature'
+ */
+X86CPU *cpu_x86_create(const char *cpu_model)
{
+X86CPU *cpu;
+CPUX86State *env;
x86_def_t def1, *def = def1;
Error *error = NULL;
char *name, *features;
gchar **model_pieces;
+cpu = X86_CPU(object_new(TYPE_X86_CPU));
Could we put this after cpu_x86_parse_featurestr(), it's really not needed
before it now and eventually we would like to move it there anyway.
+env = cpu-env;
+env-cpu_model_str = cpu_model;
+
memset(def, 0, sizeof(*def));
model_pieces = g_strsplit(cpu_model, ,, 2);
@@ -1578,10 +1587,11 @@ int cpu_x86_register(X86CPU *cpu, const char
*cpu_model)
}
g_strfreev(model_pieces);
-return 0;
+return cpu;
error:
+object_delete(OBJECT(cpu));
g_strfreev(model_pieces);
-return -1;
+return NULL;
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 386c4f6..3ebaae9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -980,7 +980,7 @@ int cpu_x86_signal_handler(int host_signum, void *pinfo,
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx);
-int cpu_x86_register(X86CPU *cpu, const char *cpu_model);
+X86CPU *cpu_x86_create(const char *cpu_model);
void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index bf206cf..23af4a8 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1243,15 +1243,10 @@ int cpu_x86_get_descr_debug(CPUX86State *env,
unsigned int selector,
X86CPU *cpu_x86_init(const char *cpu_model)
{
X86CPU *cpu;
-CPUX86State *env;
Error *error = NULL;
-cpu = X86_CPU(object_new(TYPE_X86_CPU));
-env = cpu-env;
-env-cpu_model_str = cpu_model;
-
-if (cpu_x86_register(cpu, cpu_model) 0) {
-object_delete(OBJECT(cpu));
+cpu = cpu_x86_create(cpu_model);
+if (!cpu) {
return NULL;
}
--
1.7.11.7
--
Regards,
Igor
[Qemu-devel] [PATCH v2 1/7] tmp105: Create API for TMP105 temperature sensor
From: Alex Horn alex.h...@cs.ox.ac.uk
* Define enum for TMP105 registers
* Move tmp105_set() from I2C to TMP105 header
* Document units and range of temperature as preconditions
Signed-off-by: Alex Horn alex.h...@cs.ox.ac.uk
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/i2c.h|3 ---
hw/tmp105.c | 17 ---
hw/tmp105.h | 67 +++
3 Dateien geändert, 76 Zeilen hinzugefügt(+), 11 Zeilen entfernt(-)
create mode 100644 hw/tmp105.h
diff --git a/hw/i2c.h b/hw/i2c.h
index 0f5682b..883b5c5 100644
--- a/hw/i2c.h
+++ b/hw/i2c.h
@@ -73,9 +73,6 @@ void *wm8750_dac_buffer(void *opaque, int samples);
void wm8750_dac_commit(void *opaque);
void wm8750_set_bclk_in(void *opaque, int new_hz);
-/* tmp105.c */
-void tmp105_set(I2CSlave *i2c, int temp);
-
/* lm832x.c */
void lm832x_key_event(DeviceState *dev, int key, int state);
diff --git a/hw/tmp105.c b/hw/tmp105.c
index 8e8dbd9..9c67e64 100644
--- a/hw/tmp105.c
+++ b/hw/tmp105.c
@@ -20,6 +20,7 @@
#include hw.h
#include i2c.h
+#include tmp105.h
typedef struct {
I2CSlave i2c;
@@ -92,22 +93,22 @@ static void tmp105_read(TMP105State *s)
}
switch (s-pointer 3) {
-case 0:/* Temperature */
+case TMP105_REG_TEMPERATURE:
s-buf[s-len ++] = (((uint16_t) s-temperature) 8);
s-buf[s-len ++] = (((uint16_t) s-temperature) 0)
(0xf0 ((~s-config 5) 3)); /* R */
break;
-case 1:/* Configuration */
+case TMP105_REG_CONFIG:
s-buf[s-len ++] = s-config;
break;
-case 2:/* T_LOW */
+case TMP105_REG_T_LOW:
s-buf[s-len ++] = ((uint16_t) s-limit[0]) 8;
s-buf[s-len ++] = ((uint16_t) s-limit[0]) 0;
break;
-case 3:/* T_HIGH */
+case TMP105_REG_T_HIGH:
s-buf[s-len ++] = ((uint16_t) s-limit[1]) 8;
s-buf[s-len ++] = ((uint16_t) s-limit[1]) 0;
break;
@@ -117,10 +118,10 @@ static void tmp105_read(TMP105State *s)
static void tmp105_write(TMP105State *s)
{
switch (s-pointer 3) {
-case 0:/* Temperature */
+case TMP105_REG_TEMPERATURE:
break;
-case 1:/* Configuration */
+case TMP105_REG_CONFIG:
if (s-buf[0] ~s-config (1 0)) /* SD */
printf(%s: TMP105 shutdown\n, __FUNCTION__);
s-config = s-buf[0];
@@ -128,8 +129,8 @@ static void tmp105_write(TMP105State *s)
tmp105_alarm_update(s);
break;
-case 2:/* T_LOW */
-case 3:/* T_HIGH */
+case TMP105_REG_T_LOW:
+case TMP105_REG_T_HIGH:
if (s-len = 3)
s-limit[s-pointer 1] = (int16_t)
uint16_t) s-buf[0]) 8) | s-buf[1]);
diff --git a/hw/tmp105.h b/hw/tmp105.h
new file mode 100644
index 000..51eff4b
--- /dev/null
+++ b/hw/tmp105.h
@@ -0,0 +1,67 @@
+/*
+ * Texas Instruments TMP105 Temperature Sensor
+ *
+ * Browse the data sheet:
+ *
+ *http://www.ti.com/lit/gpn/tmp105
+ *
+ * Copyright (C) 2012 Alex Horn alex.h...@cs.ox.ac.uk
+ * Copyright (C) 2008-2012 Andrzej Zaborowski balr...@gmail.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+#ifndef QEMU_TMP105_H
+#define QEMU_TMP105_H
+
+#include i2c.h
+
+/**
+ * TMP105Reg:
+ * @TMP105_REG_TEMPERATURE: Temperature register
+ * @TMP105_REG_CONFIG: Configuration register
+ * @TMP105_REG_T_LOW: Low temperature register (also known as T_hyst)
+ * @TMP105_REG_T_HIGH: High temperature register (also known as T_OS)
+ *
+ * The following temperature sensors are
+ * compatible with the TMP105 registers:
+ * - adt75
+ * - ds1775
+ * - ds75
+ * - lm75
+ * - lm75a
+ * - max6625
+ * - max6626
+ * - mcp980x
+ * - stds75
+ * - tcn75
+ * - tmp100
+ * - tmp101
+ * - tmp105
+ * - tmp175
+ * - tmp275
+ * - tmp75
+ **/
+typedef enum TMP105Reg {
+TMP105_REG_TEMPERATURE = 0,
+TMP105_REG_CONFIG,
+TMP105_REG_T_LOW,
+TMP105_REG_T_HIGH,
+} TMP105Reg;
+
+/**
+ * tmp105_set:
+ * @i2c: dispatcher to TMP105 hardware model
+ * @temp: temperature with 0.001 centigrades units in the range -40 C to +125 C
+ *
+ * Sets the temperature of the TMP105 hardware model.
+ *
+ * Bits 5 and 6 (value 32 and 64) in the register indexed by TMP105_REG_CONFIG
+ * determine the precision of the temperature. See Table 8 in the data sheet.
+ *
+ * @see_also: I2C_SLAVE macro
+ * @see_also: http://www.ti.com/lit/gpn/tmp105
+ */
+void tmp105_set(I2CSlave *i2c, int temp);
+
+#endif
--
1.7.10.4
Re: [Qemu-devel] [PATCH RFC] PowerPC: Added uapi directory into linux-header
On 14.12.2012, at 12:04, Bharat Bhushan wrote: This is corrently done for powerpc. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com Jan, could you please check if this is correct? --- configure |1 + scripts/update-linux-headers.sh |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/configure b/configure index 780b19a..bdc2d5e 100755 --- a/configure +++ b/configure @@ -3701,6 +3701,7 @@ if test $linux = yes ; then # For non-KVM architectures we will not have asm headers if [ -e $source_path/linux-headers/asm-$linux_arch ]; then symlink $source_path/linux-headers/asm-$linux_arch linux-headers/asm + symlink $source_path/linux-headers/uapi/asm-$linux_arch linux-headers/uapi/asm fi fi diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 4c7b566..9f6bf25 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -48,6 +48,11 @@ for arch in $ARCHLIST; do rm -rf $output/linux-headers/asm-$arch mkdir -p $output/linux-headers/asm-$arch +if [ $arch = powerpc ]; then This looks bogus. There shouldn't be any powerpc specifics anywhere in this file. Alex + rm -rf $output/linux-headers/uapi/asm-$arch/* +cp $linux/arch/$arch/include/uapi/asm/epapr_hcalls.h $output/linux-headers/uapi/asm-$arch/ +fi + for header in kvm.h kvm_para.h; do cp $tmpdir/include/asm/$header $output/linux-headers/asm-$arch done -- 1.7.0.4
Re: [Qemu-devel] [PATCH 1/3] target-i386: add EXT2_PPRO_FEATURES #define
Am 12.12.2012 23:22, schrieb Eduardo Habkost: Instead of repeating the (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) expression everywhere, use EXT2_PPRO_FEATURES. Signed-off-by: Eduardo Habkost ehabk...@redhat.com Technically this patch looks fine. My dislike for these defines aside, I have doubts about the semantics: This is masking out AMD_ALIASES (whatever that is exactly I still need to look up) - doesn't that rather call for EXT2_PPRO_INTEL_FEATURES or so? (But then again the Pentium Pro was an Intel chip so AMD sounds confusing...) Or does no AMD model actually inherit those AMD aliases? This at least deserves a mention in the commit message (no need to resend then). Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH v2 5/7] tmp105: Fix I2C protocol bug
An early length postincrement in the TMP105's I2C TX path led to
transfers of more than one byte to place the second byte in the third
byte's place within the buffer and the third byte to get discarded.
Fix this by explictly incrementing the length after the checks but
before the callback is called, which again checks the length.
Adjust the Coding Style while at it.
Signed-off-by: Alex Horn alex.h...@cs.ox.ac.uk
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/tmp105.c |9 ++---
1 Datei geändert, 6 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)
diff --git a/hw/tmp105.c b/hw/tmp105.c
index 9c67e64..ff9f28b 100644
--- a/hw/tmp105.c
+++ b/hw/tmp105.c
@@ -153,11 +153,14 @@ static int tmp105_tx(I2CSlave *i2c, uint8_t data)
{
TMP105State *s = (TMP105State *) i2c;
-if (!s-len ++)
+if (s-len == 0) {
s-pointer = data;
-else {
-if (s-len = 2)
+s-len++;
+} else {
+if (s-len = 2) {
s-buf[s-len - 1] = data;
+}
+s-len++;
tmp105_write(s);
}
--
1.7.10.4
Re: [Qemu-devel] [PATCH v6 03/12] dataplane: add host memory mapping code
On Wed, Dec 12, 2012 at 4:49 PM, Michael S. Tsirkin m...@redhat.com wrote: On Wed, Dec 12, 2012 at 04:34:21PM +0100, Stefan Hajnoczi wrote: On Tue, Dec 11, 2012 at 08:09:56PM +0200, Michael S. Tsirkin wrote: On Tue, Dec 11, 2012 at 10:32:28AM -0600, Anthony Liguori wrote: Michael S. Tsirkin m...@redhat.com writes: On Tue, Dec 11, 2012 at 04:27:49PM +0100, Stefan Hajnoczi wrote: On Tue, Dec 11, 2012 at 3:13 PM, Michael S. Tsirkin m...@redhat.com wrote: On Mon, Dec 10, 2012 at 02:09:36PM +0100, Stefan Hajnoczi wrote: The data plane thread needs to map guest physical addresses to host pointers. Normally this is done with cpu_physical_memory_map() but the function assumes the global mutex is held. The data plane thread does not touch the global mutex and therefore needs a thread-safe memory mapping mechanism. Hostmem registers a MemoryListener similar to how vhost collects and pushes memory region information into the kernel. There is a fine-grained lock on the regions list which is held during lookup and when installing a new regions list. Can we export and reuse the vhost code for this? I think you will find this advantageous when you add migration support down the line. And if you find it necessary to use MemoryListener e.g. for performance reasons, then vhost will likely benefit too. It's technically possible and not hard to do but it prevents integrating deeper with core QEMU as the memory API becomes thread-safe. There are two ways to implement dirty logging: 1. The vhost log approach which syncs dirty information periodically. 2. A cheap thread-safe way to mark dirty outside the global mutex, i.e. a thread-safe memory_region_set_dirty(). You don't normally want to dirty the whole region, you want to do this to individual pages. If we can get thread-safe guest memory load/store in QEMU then #2 is included. We can switch to using hw/virtio.c instead of hw/dataplane/vring.c, we get dirty logging for free, we can drop hostmem.c completely, etc. Stefan So why not reuse existing code? If you drop it later it won't matter what you used ... Let's not lose sight of the forest for the trees here... This whole series is not reusing existing code. That's really the whole point. The point is to take the code (duplication and all) and then do all of the refactoring to use common code in the tree itself. If we want to put this in a hw/staging/ directory, that's fine by me too. Regards, Anthony Liguori Yes I agree. I think lack of handling for cross regin descriptors bothers me a bit more. The two things you've mentioned both aren't handled by hw/virtio.c: 1. Issue: Indirect descriptors have no alignment restrictions and can cross regions. hw/virtio.c uses vring_desc_flags() and other accessor functions, which do lduw_phys() - there is no memory region boundary checking here. Since addresses are aligned this one is fine I think. 2. Issue: Virtio buffers can cross memory region boundaries. hw/virtio.c maps buffers 1:1 using virtqueue_map_sg() and exits if mapping fails. It does not split buffers if they cross a memory region. These are definitely ugly corner cases but hw/virtio.c is proof that we're not hitting them in practice. Stefan Yes, this one seems ugly. Maybe add a TODO? OK let's assume we want to put it in staging/ I worry about the virtio-blk changes being isolated. Can you put ifdef CONFIG_VIRTIO_BLK_DATA_PLANE around them all to avoid dependency on that header completely if configured out? Okay, I'll move the #ifdefs. I like the stubs in the header file because it reduces the amount of #ifdefs, but this is easy to change. Stefan
[Qemu-devel] [PATCH RFC] PowerPC: Added uapi directory into linux-header
This is corrently done for powerpc. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- configure |1 + scripts/update-linux-headers.sh |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/configure b/configure index 780b19a..bdc2d5e 100755 --- a/configure +++ b/configure @@ -3701,6 +3701,7 @@ if test $linux = yes ; then # For non-KVM architectures we will not have asm headers if [ -e $source_path/linux-headers/asm-$linux_arch ]; then symlink $source_path/linux-headers/asm-$linux_arch linux-headers/asm + symlink $source_path/linux-headers/uapi/asm-$linux_arch linux-headers/uapi/asm fi fi diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 4c7b566..9f6bf25 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -48,6 +48,11 @@ for arch in $ARCHLIST; do rm -rf $output/linux-headers/asm-$arch mkdir -p $output/linux-headers/asm-$arch +if [ $arch = powerpc ]; then + rm -rf $output/linux-headers/uapi/asm-$arch/* +cp $linux/arch/$arch/include/uapi/asm/epapr_hcalls.h $output/linux-headers/uapi/asm-$arch/ +fi + for header in kvm.h kvm_para.h; do cp $tmpdir/include/asm/$header $output/linux-headers/asm-$arch done -- 1.7.0.4
Re: [Qemu-devel] [PATCH 2/4] virtio: add wrapper for saving/restoring virtqueue elements
Il 10/12/2012 15:29, Anthony Liguori ha scritto:
Putting raw structures on the wire is bad news. Add a wrapper and use it.
Note that in virtio-serial-bus, we were mapping both the in and out vectors as
writable. This is a bug that is fixed by this change. I checked the revision
history, it has been there since the code was first added and does not appear
to be intentional.
Signed-off-by: Anthony Liguori aligu...@us.ibm.com
---
hw/virtio-blk.c| 9 ++---
hw/virtio-serial-bus.c | 10 ++
hw/virtio.c| 13 +
hw/virtio.h| 4
4 files changed, 21 insertions(+), 15 deletions(-)
virtio-scsi is missing; see virtio_scsi_load_request and
virtio_scsi_save_request.
Paolo
diff --git a/hw/virtio-blk.c b/hw/virtio-blk.c
index e25cc96..7ab174f 100644
--- a/hw/virtio-blk.c
+++ b/hw/virtio-blk.c
@@ -555,7 +555,7 @@ static void virtio_blk_save(QEMUFile *f, void *opaque)
while (req) {
qemu_put_sbyte(f, 1);
-qemu_put_buffer(f, (unsigned char*)req-elem, sizeof(req-elem));
+virtio_put_virt_queue_element(f, req-elem);
req = req-next;
}
qemu_put_sbyte(f, 0);
@@ -576,14 +576,9 @@ static int virtio_blk_load(QEMUFile *f, void *opaque,
int version_id)
while (qemu_get_sbyte(f)) {
VirtIOBlockReq *req = virtio_blk_alloc_request(s);
-qemu_get_buffer(f, (unsigned char*)req-elem, sizeof(req-elem));
+virtio_get_virt_queue_element(f, req-elem);
req-next = s-rq;
s-rq = req;
-
-virtqueue_map_sg(req-elem.in_sg, req-elem.in_addr,
-req-elem.in_num, 1);
-virtqueue_map_sg(req-elem.out_sg, req-elem.out_addr,
-req-elem.out_num, 0);
}
return 0;
diff --git a/hw/virtio-serial-bus.c b/hw/virtio-serial-bus.c
index 155da58..aa1ded0 100644
--- a/hw/virtio-serial-bus.c
+++ b/hw/virtio-serial-bus.c
@@ -629,8 +629,7 @@ static void virtio_serial_save(QEMUFile *f, void *opaque)
qemu_put_be32s(f, port-iov_idx);
qemu_put_be64s(f, port-iov_offset);
-qemu_put_buffer(f, (unsigned char *)port-elem,
-sizeof(port-elem));
+virtio_put_virt_queue_element(f, port-elem);
}
}
}
@@ -731,12 +730,7 @@ static int virtio_serial_load(QEMUFile *f, void *opaque,
int version_id)
qemu_get_be32s(f, port-iov_idx);
qemu_get_be64s(f, port-iov_offset);
-qemu_get_buffer(f, (unsigned char *)port-elem,
-sizeof(port-elem));
-virtqueue_map_sg(port-elem.in_sg, port-elem.in_addr,
- port-elem.in_num, 1);
-virtqueue_map_sg(port-elem.out_sg, port-elem.out_addr,
- port-elem.out_num, 1);
+virtio_get_virt_queue_element(f, port-elem);
/*
* Port was throttled on source machine. Let's
diff --git a/hw/virtio.c b/hw/virtio.c
index f40a8c5..8eb8f69 100644
--- a/hw/virtio.c
+++ b/hw/virtio.c
@@ -875,6 +875,19 @@ int virtio_load(VirtIODevice *vdev, QEMUFile *f)
return 0;
}
+void virtio_put_virt_queue_element(QEMUFile *f, const VirtQueueElement *elem)
+{
+qemu_put_buffer(f, (unsigned char*)elem, sizeof(*elem));
+}
+
+void virtio_get_virt_queue_element(QEMUFile *f, VirtQueueElement *elem)
+{
+qemu_get_buffer(f, (unsigned char *)elem, sizeof(*elem));
+
+virtqueue_map_sg(elem-in_sg, elem-in_addr, elem-in_num, 1);
+virtqueue_map_sg(elem-out_sg, elem-out_addr, elem-out_num, 0);
+}
+
void virtio_cleanup(VirtIODevice *vdev)
{
qemu_del_vm_change_state_handler(vdev-vmstate);
diff --git a/hw/virtio.h b/hw/virtio.h
index 7c17f7b..4af8239 100644
--- a/hw/virtio.h
+++ b/hw/virtio.h
@@ -159,6 +159,10 @@ void virtio_save(VirtIODevice *vdev, QEMUFile *f);
int virtio_load(VirtIODevice *vdev, QEMUFile *f);
+void virtio_put_virt_queue_element(QEMUFile *f, const VirtQueueElement
*elem);
+
+void virtio_get_virt_queue_element(QEMUFile *f, VirtQueueElement *elem);
+
void virtio_cleanup(VirtIODevice *vdev);
void virtio_notify_config(VirtIODevice *vdev);
[Qemu-devel] [PATCH v2 6/7] tmp105: QOM'ify
Introduce TYPE_ constant and cast macro.
Move the state struct to the new header to allow for future embedding.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/tmp105.c | 38 +-
hw/tmp105.h | 27 +++
2 Dateien geändert, 40 Zeilen hinzugefügt(+), 25 Zeilen entfernt(-)
diff --git a/hw/tmp105.c b/hw/tmp105.c
index ff9f28b..a16f538 100644
--- a/hw/tmp105.c
+++ b/hw/tmp105.c
@@ -22,20 +22,6 @@
#include i2c.h
#include tmp105.h
-typedef struct {
-I2CSlave i2c;
-uint8_t len;
-uint8_t buf[2];
-qemu_irq pin;
-
-uint8_t pointer;
-uint8_t config;
-int16_t temperature;
-int16_t limit[2];
-int faults;
-uint8_t alarm;
-} TMP105State;
-
static void tmp105_interrupt_update(TMP105State *s)
{
qemu_set_irq(s-pin, s-alarm ^ ((~s-config 2) 1)); /* POL */
@@ -68,7 +54,7 @@ static void tmp105_alarm_update(TMP105State *s)
/* Units are 0.001 centigrades relative to 0 C. */
void tmp105_set(I2CSlave *i2c, int temp)
{
-TMP105State *s = (TMP105State *) i2c;
+TMP105State *s = TMP105(i2c);
if (temp = 128000 || temp -128000) {
fprintf(stderr, %s: values is out of range (%i.%03i C)\n,
@@ -141,17 +127,18 @@ static void tmp105_write(TMP105State *s)
static int tmp105_rx(I2CSlave *i2c)
{
-TMP105State *s = (TMP105State *) i2c;
+TMP105State *s = TMP105(i2c);
-if (s-len 2)
+if (s-len 2) {
return s-buf[s-len ++];
-else
+} else {
return 0xff;
+}
}
static int tmp105_tx(I2CSlave *i2c, uint8_t data)
{
-TMP105State *s = (TMP105State *) i2c;
+TMP105State *s = TMP105(i2c);
if (s-len == 0) {
s-pointer = data;
@@ -169,10 +156,11 @@ static int tmp105_tx(I2CSlave *i2c, uint8_t data)
static void tmp105_event(I2CSlave *i2c, enum i2c_event event)
{
-TMP105State *s = (TMP105State *) i2c;
+TMP105State *s = TMP105(i2c);
-if (event == I2C_START_RECV)
+if (event == I2C_START_RECV) {
tmp105_read(s);
+}
s-len = 0;
}
@@ -208,7 +196,7 @@ static const VMStateDescription vmstate_tmp105 = {
static void tmp105_reset(I2CSlave *i2c)
{
-TMP105State *s = (TMP105State *) i2c;
+TMP105State *s = TMP105(i2c);
s-temperature = 0;
s-pointer = 0;
@@ -221,7 +209,7 @@ static void tmp105_reset(I2CSlave *i2c)
static int tmp105_init(I2CSlave *i2c)
{
-TMP105State *s = FROM_I2C_SLAVE(TMP105State, i2c);
+TMP105State *s = TMP105(i2c);
qdev_init_gpio_out(i2c-qdev, s-pin, 1);
@@ -242,8 +230,8 @@ static void tmp105_class_init(ObjectClass *klass, void
*data)
dc-vmsd = vmstate_tmp105;
}
-static TypeInfo tmp105_info = {
-.name = tmp105,
+static const TypeInfo tmp105_info = {
+.name = TYPE_TMP105,
.parent= TYPE_I2C_SLAVE,
.instance_size = sizeof(TMP105State),
.class_init= tmp105_class_init,
diff --git a/hw/tmp105.h b/hw/tmp105.h
index 982d1c9..c21396f 100644
--- a/hw/tmp105.h
+++ b/hw/tmp105.h
@@ -17,6 +17,33 @@
#include i2c.h
#include tmp105_regs.h
+#define TYPE_TMP105 tmp105
+#define TMP105(obj) OBJECT_CHECK(TMP105State, (obj), TYPE_TMP105)
+
+/**
+ * TMP105State:
+ * @config: Bits 5 and 6 (value 32 and 64) determine the precision of the
+ * temperature. See Table 8 in the data sheet.
+ *
+ * @see_also: http://www.ti.com/lit/gpn/tmp105
+ */
+typedef struct TMP105State {
+/* private */
+I2CSlave i2c;
+/* public */
+
+uint8_t len;
+uint8_t buf[2];
+qemu_irq pin;
+
+uint8_t pointer;
+uint8_t config;
+int16_t temperature;
+int16_t limit[2];
+int faults;
+uint8_t alarm;
+} TMP105State;
+
/**
* tmp105_set:
* @i2c: dispatcher to TMP105 hardware model
--
1.7.10.4
Re: [Qemu-devel] [PATCH 3/4] virtio: modify savevm to have a stable wire format
Il 14/12/2012 01:57, Rusty Russell ha scritto: With the new code we only need the head from that structure. We also need to do again all validation of the elements if we fetch it back from the data. Sometimes the parsed data is saved elsewhere (e.g. in a SCSIRequest struct that is serialized by the SCSI subsystem) and that data may be inconsistent with whatever you read from guest memory. It's a can of worms. I'm certainly in favor of cleaning up the savevm format and probably leaving the existing load/save functions as-is for legacy purposes. I'll leave that as an exercise for someone else though :-) What is the rule about new versions? Can we introduce a new save version at any time, or only at major qemu version changes? Any time, but we provide a backwards-compatible loader for older versions. Paolo
[Qemu-devel] [PATCH v2 7/7] tmp105: Add temperature QOM property
This obsoletes tmp105_set() and allows for better error handling.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/tmp105.c | 39 ---
hw/tmp105.h | 15 ---
2 Dateien geändert, 32 Zeilen hinzugefügt(+), 22 Zeilen entfernt(-)
diff --git a/hw/tmp105.c b/hw/tmp105.c
index a16f538..34c7d24 100644
--- a/hw/tmp105.c
+++ b/hw/tmp105.c
@@ -21,6 +21,7 @@
#include hw.h
#include i2c.h
#include tmp105.h
+#include qapi/qapi-visit-core.h
static void tmp105_interrupt_update(TMP105State *s)
{
@@ -51,18 +52,34 @@ static void tmp105_alarm_update(TMP105State *s)
tmp105_interrupt_update(s);
}
+static void tmp105_get_temperature(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+TMP105State *s = TMP105(obj);
+int64_t value = s-temperature;
+
+visit_type_int(v, value, name, errp);
+}
+
/* Units are 0.001 centigrades relative to 0 C. */
-void tmp105_set(I2CSlave *i2c, int temp)
+static void tmp105_set_temperature(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
{
-TMP105State *s = TMP105(i2c);
+TMP105State *s = TMP105(obj);
-if (temp = 128000 || temp -128000) {
-fprintf(stderr, %s: values is out of range (%i.%03i C)\n,
-__FUNCTION__, temp / 1000, temp % 1000);
-exit(-1);
+int64_t value;
+
+visit_type_int(v, value, name, errp);
+if (error_is_set(errp)) {
+return;
+}
+if (value = 128000 || value -128000) {
+error_setg(errp, value % PRId64 .%03 PRIu64 °C is out of range,
+ value / 1000, value % 1000);
+return;
}
-s-temperature = ((int16_t) (temp * 0x800 / 128000)) 4;
+s-temperature = ((int16_t) (value * 0x800 / 128000)) 4;
tmp105_alarm_update(s);
}
@@ -218,6 +235,13 @@ static int tmp105_init(I2CSlave *i2c)
return 0;
}
+static void tmp105_initfn(Object *obj)
+{
+object_property_add(obj, temperature, int,
+tmp105_get_temperature,
+tmp105_set_temperature, NULL, NULL, NULL);
+}
+
static void tmp105_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -234,6 +258,7 @@ static const TypeInfo tmp105_info = {
.name = TYPE_TMP105,
.parent= TYPE_I2C_SLAVE,
.instance_size = sizeof(TMP105State),
+.instance_init = tmp105_initfn,
.class_init= tmp105_class_init,
};
diff --git a/hw/tmp105.h b/hw/tmp105.h
index c21396f..d218919 100644
--- a/hw/tmp105.h
+++ b/hw/tmp105.h
@@ -44,19 +44,4 @@ typedef struct TMP105State {
uint8_t alarm;
} TMP105State;
-/**
- * tmp105_set:
- * @i2c: dispatcher to TMP105 hardware model
- * @temp: temperature with 0.001 centigrades units in the range -40 C to +125 C
- *
- * Sets the temperature of the TMP105 hardware model.
- *
- * Bits 5 and 6 (value 32 and 64) in the register indexed by TMP105_REG_CONFIG
- * determine the precision of the temperature. See Table 8 in the data sheet.
- *
- * @see_also: I2C_SLAVE macro
- * @see_also: http://www.ti.com/lit/gpn/tmp105
- */
-void tmp105_set(I2CSlave *i2c, int temp);
-
#endif
--
1.7.10.4
[Qemu-devel] [PATCH v2 3/7] tmp105: Split out I2C message constants from header
Allows value sharing with qtest.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/tmp105.h | 34 +-
hw/tmp105_regs.h | 50 ++
2 Dateien geändert, 51 Zeilen hinzugefügt(+), 33 Zeilen entfernt(-)
create mode 100644 hw/tmp105_regs.h
diff --git a/hw/tmp105.h b/hw/tmp105.h
index 51eff4b..982d1c9 100644
--- a/hw/tmp105.h
+++ b/hw/tmp105.h
@@ -15,39 +15,7 @@
#define QEMU_TMP105_H
#include i2c.h
-
-/**
- * TMP105Reg:
- * @TMP105_REG_TEMPERATURE: Temperature register
- * @TMP105_REG_CONFIG: Configuration register
- * @TMP105_REG_T_LOW: Low temperature register (also known as T_hyst)
- * @TMP105_REG_T_HIGH: High temperature register (also known as T_OS)
- *
- * The following temperature sensors are
- * compatible with the TMP105 registers:
- * - adt75
- * - ds1775
- * - ds75
- * - lm75
- * - lm75a
- * - max6625
- * - max6626
- * - mcp980x
- * - stds75
- * - tcn75
- * - tmp100
- * - tmp101
- * - tmp105
- * - tmp175
- * - tmp275
- * - tmp75
- **/
-typedef enum TMP105Reg {
-TMP105_REG_TEMPERATURE = 0,
-TMP105_REG_CONFIG,
-TMP105_REG_T_LOW,
-TMP105_REG_T_HIGH,
-} TMP105Reg;
+#include tmp105_regs.h
/**
* tmp105_set:
diff --git a/hw/tmp105_regs.h b/hw/tmp105_regs.h
new file mode 100644
index 000..9b55aba
--- /dev/null
+++ b/hw/tmp105_regs.h
@@ -0,0 +1,50 @@
+/*
+ * Texas Instruments TMP105 Temperature Sensor I2C messages
+ *
+ * Browse the data sheet:
+ *
+ *http://www.ti.com/lit/gpn/tmp105
+ *
+ * Copyright (C) 2012 Alex Horn alex.h...@cs.ox.ac.uk
+ * Copyright (C) 2008-2012 Andrzej Zaborowski balr...@gmail.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+#ifndef QEMU_TMP105_MSGS_H
+#define QEMU_TMP105_MSGS_H
+
+/**
+ * TMP105Reg:
+ * @TMP105_REG_TEMPERATURE: Temperature register
+ * @TMP105_REG_CONFIG: Configuration register
+ * @TMP105_REG_T_LOW: Low temperature register (also known as T_hyst)
+ * @TMP105_REG_T_HIGH: High temperature register (also known as T_OS)
+ *
+ * The following temperature sensors are
+ * compatible with the TMP105 registers:
+ * - adt75
+ * - ds1775
+ * - ds75
+ * - lm75
+ * - lm75a
+ * - max6625
+ * - max6626
+ * - mcp980x
+ * - stds75
+ * - tcn75
+ * - tmp100
+ * - tmp101
+ * - tmp105
+ * - tmp175
+ * - tmp275
+ * - tmp75
+ **/
+typedef enum TMP105Reg {
+TMP105_REG_TEMPERATURE = 0,
+TMP105_REG_CONFIG,
+TMP105_REG_T_LOW,
+TMP105_REG_T_HIGH,
+} TMP105Reg;
+
+#endif
--
1.7.10.4
Re: [Qemu-devel] [PATCH RFC] PowerPC: Added uapi directory into linux-header
On 14 December 2012 11:04, Bharat Bhushan r65...@freescale.com wrote: This is corrently done for powerpc. This commit message is a bit cryptic. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- configure |1 + scripts/update-linux-headers.sh |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/configure b/configure index 780b19a..bdc2d5e 100755 --- a/configure +++ b/configure @@ -3701,6 +3701,7 @@ if test $linux = yes ; then # For non-KVM architectures we will not have asm headers if [ -e $source_path/linux-headers/asm-$linux_arch ]; then symlink $source_path/linux-headers/asm-$linux_arch linux-headers/asm + symlink $source_path/linux-headers/uapi/asm-$linux_arch linux-headers/uapi/asm fi This creates a broken symlink if you run it on an arch that doesn't have a uapi directory: cam-vm-266:precise:qemu$ file linux-headers/uapi/asm linux-headers/uapi/asm: broken symbolic link to `/home/petmay01/linaro/qemu-from-laptop/qemu/linux-headers/uapi/asm-x86' Shouldn't it go in its own if [ -e $source_path/linux-headers/uapi/asm-$linux_arch ] guard ? fi diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 4c7b566..9f6bf25 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -48,6 +48,11 @@ for arch in $ARCHLIST; do rm -rf $output/linux-headers/asm-$arch mkdir -p $output/linux-headers/asm-$arch +if [ $arch = powerpc ]; then + rm -rf $output/linux-headers/uapi/asm-$arch/* +cp $linux/arch/$arch/include/uapi/asm/epapr_hcalls.h $output/linux-headers/uapi/asm-$arch/ +fi (1) This doesn't seem to be doing the mkdir of $output/linux-headers/uapi/asm-$arch/ anywhere. (2) The setup of the uapi/ subdirectory shouldn't be inside an if [ $arch = powerpc ] guard, so it can work on all archs with a uapi/. You want to rm-and-mkdir the uapi/ directory if $linux/arch/$arch/include/uapi/ exists. (3) it would be neater to put the copy this ppc specific header file code at the bottom of the for loop next to the existing copy this x86 specific header file code. -- PMM
[Qemu-devel] [PATCH v2 4/7] tests: Add tmp105 qtest test case
Exercise all four commands of the TMP105, testing for an issue in the
I2C TX path.
The test case uses the N800's OMAP I2C and is the first for ARM.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
tests/Makefile |2 ++
tests/tmp105-test.c | 76 +++
2 Dateien geändert, 78 Zeilen hinzugefügt(+)
create mode 100644 tests/tmp105-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 1ec41cb..a4e8ad3 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -28,6 +28,7 @@ check-qtest-i386-y += tests/rtc-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
check-qtest-sparc-y = tests/m48t59-test$(EXESUF)
check-qtest-sparc64-y = tests/m48t59-test$(EXESUF)
+check-qtest-arm-y = tests/tmp105-test$(EXESUF)
GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h
tests/test-qmp-commands.h
@@ -78,6 +79,7 @@ tests/rtc-test$(EXESUF): tests/rtc-test.o $(trace-obj-y)
tests/m48t59-test$(EXESUF): tests/m48t59-test.o $(trace-obj-y)
tests/fdc-test$(EXESUF): tests/fdc-test.o tests/libqtest.o $(trace-obj-y)
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o tests/libqtest.o $(trace-obj-y)
+tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(trace-obj-y)
# QTest rules
diff --git a/tests/tmp105-test.c b/tests/tmp105-test.c
new file mode 100644
index 000..a6ad213
--- /dev/null
+++ b/tests/tmp105-test.c
@@ -0,0 +1,76 @@
+/*
+ * QTest testcase for the TMP105 temperature sensor
+ *
+ * Copyright (c) 2012 Andreas Färber
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include libqtest.h
+#include libi2c.h
+#include hw/tmp105_regs.h
+
+#include glib.h
+
+#define OMAP2_I2C_1_BASE 0x4807
+
+#define N8X0_ADDR 0x48
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static void send_and_receive(void)
+{
+uint8_t cmd[3];
+uint8_t resp[2];
+
+cmd[0] = TMP105_REG_TEMPERATURE;
+i2c_send(i2c, addr, cmd, 1);
+i2c_recv(i2c, addr, resp, 2);
+g_assert_cmpuint(((uint16_t)resp[0] 8) | resp[1], ==, 0);
+
+cmd[0] = TMP105_REG_CONFIG;
+cmd[1] = 0x0; /* matches the reset value */
+i2c_send(i2c, addr, cmd, 2);
+i2c_recv(i2c, addr, resp, 1);
+g_assert_cmphex(resp[0], ==, cmd[1]);
+
+cmd[0] = TMP105_REG_T_LOW;
+cmd[1] = 0x12;
+cmd[2] = 0x34;
+i2c_send(i2c, addr, cmd, 3);
+i2c_recv(i2c, addr, resp, 2);
+g_assert_cmphex(resp[0], ==, cmd[1]);
+g_assert_cmphex(resp[1], ==, cmd[2]);
+
+cmd[0] = TMP105_REG_T_HIGH;
+cmd[1] = 0x42;
+cmd[2] = 0x31;
+i2c_send(i2c, addr, cmd, 3);
+i2c_recv(i2c, addr, resp, 2);
+g_assert_cmphex(resp[0], ==, cmd[1]);
+g_assert_cmphex(resp[1], ==, cmd[2]);
+}
+
+int main(int argc, char **argv)
+{
+QTestState *s = NULL;
+int ret;
+
+g_test_init(argc, argv, NULL);
+
+s = qtest_start(-display none -machine n800);
+i2c = omap_i2c_create(OMAP2_I2C_1_BASE);
+addr = N8X0_ADDR;
+
+qtest_add_func(/tmp105/tx-rx, send_and_receive);
+
+ret = g_test_run();
+
+if (s) {
+qtest_quit(s);
+}
+g_free(i2c);
+
+return ret;
+}
--
1.7.10.4
Re: [Qemu-devel] [PATCH 1/2] cutils:change strtosz_suffix_unit function
liguang lig.f...@cn.fujitsu.com writes:
if value to be translated is larger than INT64_MAX,
this function will not be convenient for caller to
be aware of it, so change a little for this.
Signed-off-by: liguang lig.f...@cn.fujitsu.com
---
cutils.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/cutils.c b/cutils.c
index 4f0692f..da05c9e 100644
--- a/cutils.c
+++ b/cutils.c
/*
* Convert string to bytes, allowing either B/b for bytes, K/k for KB,
* M/m for MB, G/g for GB or T/t for TB. End pointer will be returned
* in *end, if not NULL. Return -1 on error.
*/
@@ -219,7 +219,7 @@ static int64_t suffix_mul(char suffix, int64_t unit)
int64_t strtosz_suffix_unit(const char *nptr, char **end,
const char default_suffix, int64_t unit)
{
-int64_t retval = -1;
+int64_t retval = EINVAL;
char *endptr;
unsigned char c;
int mul_required = 0;
@@ -246,6 +246,7 @@ int64_t strtosz_suffix_unit(const char *nptr, char **end,
goto fail;
}
if ((val * mul = INT64_MAX) || val 0) {
+retval = ERANGE;
goto fail;
}
retval = val * mul;
Your error codes aren't negative, and you failed to update the function
comment!
Re: [Qemu-devel] [PATCH 1/3] target-i386: add EXT2_PPRO_FEATURES #define
On Fri, Dec 14, 2012 at 12:44:43PM +0100, Andreas Färber wrote: Am 12.12.2012 23:22, schrieb Eduardo Habkost: Instead of repeating the (PPRO_FEATURES CPUID_EXT2_AMD_ALIASES) expression everywhere, use EXT2_PPRO_FEATURES. Signed-off-by: Eduardo Habkost ehabk...@redhat.com Technically this patch looks fine. My dislike for these defines aside, I have doubts about the semantics: This is masking out AMD_ALIASES (whatever that is exactly I still need to look up) - doesn't that rather call for EXT2_PPRO_INTEL_FEATURES or so? (But then again the Pentium Pro was an Intel chip so AMD sounds confusing...) Or does no AMD model actually inherit those AMD aliases? This at least deserves a mention in the commit message (no need to resend then). The code is not masking out AMD_ALIASES, it is is the opposite: it's keeping only the AMD_ALIASES bits. CPUID_EXT2_AMD_ALIASES are the bits in cpuid_ext2_features that have to be directly duplicated from cpuid_features, but only on AMD CPUs. Intel CPUs don't have those bit aliases. Anyway, you have a point: I think the #define could be named PPRO_EXT2_FEATURES_AMD instead, to make it clear that those bits make sense only on AMD CPU models. Also: on the models that actually have vendor=AMD, we can probably remove those bits entirely from the table, as we now have code that makes sure the feature aliases on cpuid_ext2_features are consistent with cpuid_features. But we still have a few exceptions that have vendor=Intel (kvm64, kvm32, and n270), that have to be (carefully) fixed later. The main reason I sent this change was to make it easier to automatically line-wrap the feature lists in the code to 80-columns on patch 3/3. I think I will reorder and send the feature-array patch first, and fix the CPUID_EXT2_AMD_ALIASES mess later. -- Eduardo
[Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14
Hi Blue / Aurelien, This is my current patch queue for ppc. Please pull. Alex The following changes since commit 1c97e303d4ea80a2691334b0febe87a50660f99d: Anthony Liguori (1): Merge remote-tracking branch 'afaerber/qom-cpu' into staging are available in the git repository at: git://repo.or.cz/qemu/agraf.git ppc-for-upstream Alexander Graf (27): openpic: Remove unused code mpic: Unify numbering scheme openpic: update to proper memory api openpic: combine mpic and openpic src handlers openpic: Convert subregions to memory api openpic: combine mpic and openpic irq raise functions openpic: merge mpic and openpic timer handling openpic: combine openpic and mpic reset functions openpic: unify memory api subregions openpic: remove unused type variable openpic: convert simple reg operations to builtin bitops openpic: rename openpic_t to OpenPICState openpic: remove irq_out openpic: convert to qdev openpic: make brr1 model specific openpic: add Shared MSI support PPC: e500: Add MSI support PPC: e500: Declare pci bridge as bridge MSI-X: Fix endianness openpic: fix minor coding style issues openpic: Accelerate pending irq search PPC: E500: PCI: Make first slot qdev settable PPC: E500: PCI: Make IRQ calculation more generic PPC: E500: Generate dt pci irq map dynamically PPC: E500: Move PCI slot information into params PPC: E500plat: Make a lot of PCI slots available PPC: e500: pci: Export slot2irq calculation Ben Herrenschmidt (2): pseries: Use #define for XICS base irq number pseries: Allow RTAS tokens without a qemu handler Bharat Bhushan (2): e500: Adding CCSR memory region Adding BAR0 for e500 PCI controller David Gibson (8): pseries: Fix incorrect initialization of interrupt controller pseries: Add tracepoints to the XICS interrupt controller pseries: Split xics irq configuration from state information pseries: Implement PAPR NVRAM pseries: Update SLOF for NVRAM support pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs target-ppc: Don't use hwaddr to represent hardware state pseries: Increase default NVRAM size Michael Ellerman (1): pseries: Return the token when we register an RTAS call hw/msix.c|6 +- hw/openpic.c | 1397 ++ hw/openpic.h |7 +- hw/ppc/Makefile.objs |2 +- hw/ppc/e500-ccsr.h | 17 + hw/ppc/e500.c| 205 ++-- hw/ppc/e500.h|2 + hw/ppc/e500plat.c|3 + hw/ppc/mpc8544ds.c |2 + hw/ppc_newworld.c| 25 +- hw/ppce500_pci.c | 58 ++- hw/ppce500_pci.h |9 + hw/spapr.c | 35 ++- hw/spapr.h |4 +- hw/spapr_iommu.c |6 + hw/spapr_nvram.c | 196 +++ hw/spapr_rtas.c |6 +- hw/xics.c| 47 ++- hw/xics.h|1 + pc-bios/README |2 +- pc-bios/slof.bin | Bin 878640 - 880832 bytes qemu-config.c|4 + roms/SLOF|2 +- target-ppc/cpu.h |2 +- trace-events | 13 + 25 files changed, 1043 insertions(+), 1008 deletions(-) create mode 100644 hw/ppc/e500-ccsr.h create mode 100644 hw/ppce500_pci.h create mode 100644 hw/spapr_nvram.c
[Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available
The ppce500 machine doesn't have to stick to hardware limitations,
as it's defined as being fully device tree based.
Thus we can change the initial PCI slot ID to 0x1 which gives us a
whopping 31 PCI devices we can support with this machine now!
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500plat.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 9365213..2992bd9 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -14,6 +14,7 @@
#include e500.h
#include ../boards.h
#include device_tree.h
+#include hw/pci.h
static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
{
@@ -40,8 +41,8 @@ static void e500plat_init(QEMUMachineInitArgs *args)
.kernel_cmdline = kernel_cmdline,
.initrd_filename = initrd_filename,
.cpu_model = cpu_model,
-.pci_first_slot = 0x11,
-.pci_nr_slots = 2,
+.pci_first_slot = 0x1,
+.pci_nr_slots = PCI_SLOT_MAX - 1,
.fixup_devtree = e500plat_fixup_devtree,
};
--
1.6.0.2
[Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions
The only difference between the openpic and mpic memory api subregion
descriptors is the endianness. Unify them as openpic accessors with explicit
endianness markers in their names.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 108 ++
1 files changed, 56 insertions(+), 52 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index e94529b..623c807 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -867,7 +867,7 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr,
unsigned len)
return openpic_cpu_read_internal(opaque, addr, (addr 0x1f000) 12);
}
-static const MemoryRegionOps openpic_glb_ops = {
+static const MemoryRegionOps openpic_glb_ops_le = {
.write = openpic_gbl_write,
.read = openpic_gbl_read,
.endianness = DEVICE_LITTLE_ENDIAN,
@@ -877,7 +877,17 @@ static const MemoryRegionOps openpic_glb_ops = {
},
};
-static const MemoryRegionOps openpic_tmr_ops = {
+static const MemoryRegionOps openpic_glb_ops_be = {
+.write = openpic_gbl_write,
+.read = openpic_gbl_read,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static const MemoryRegionOps openpic_tmr_ops_le = {
.write = openpic_timer_write,
.read = openpic_timer_read,
.endianness = DEVICE_LITTLE_ENDIAN,
@@ -887,7 +897,17 @@ static const MemoryRegionOps openpic_tmr_ops = {
},
};
-static const MemoryRegionOps openpic_cpu_ops = {
+static const MemoryRegionOps openpic_tmr_ops_be = {
+.write = openpic_timer_write,
+.read = openpic_timer_read,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static const MemoryRegionOps openpic_cpu_ops_le = {
.write = openpic_cpu_write,
.read = openpic_cpu_read,
.endianness = DEVICE_LITTLE_ENDIAN,
@@ -897,7 +917,17 @@ static const MemoryRegionOps openpic_cpu_ops = {
},
};
-static const MemoryRegionOps openpic_src_ops = {
+static const MemoryRegionOps openpic_cpu_ops_be = {
+.write = openpic_cpu_write,
+.read = openpic_cpu_read,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static const MemoryRegionOps openpic_src_ops_le = {
.write = openpic_src_write,
.read = openpic_src_read,
.endianness = DEVICE_LITTLE_ENDIAN,
@@ -907,6 +937,16 @@ static const MemoryRegionOps openpic_src_ops = {
},
};
+static const MemoryRegionOps openpic_src_ops_be = {
+.write = openpic_src_write,
+.read = openpic_src_read,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
{
unsigned int i;
@@ -1026,10 +1066,14 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int
nb_cpus,
hwaddr start_addr;
ram_addr_t size;
} const list[] = {
-{glb, openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
-{tmr, openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
-{src, openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
-{cpu, openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
+{glb, openpic_glb_ops_le, OPENPIC_GLB_REG_START,
+ OPENPIC_GLB_REG_SIZE},
+{tmr, openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
+ OPENPIC_TMR_REG_SIZE},
+{src, openpic_src_ops_le, OPENPIC_SRC_REG_START,
+ OPENPIC_SRC_REG_SIZE},
+{cpu, openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
+ OPENPIC_CPU_REG_SIZE},
};
/* XXX: for now, only one CPU is supported */
@@ -1086,46 +1130,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
return qemu_allocate_irqs(openpic_set_irq, opp, opp-max_irq);
}
-static const MemoryRegionOps mpic_glb_ops = {
-.write = openpic_gbl_write,
-.read = openpic_gbl_read,
-.endianness = DEVICE_BIG_ENDIAN,
-.impl = {
-.min_access_size = 4,
-.max_access_size = 4,
-},
-};
-
-static const MemoryRegionOps mpic_tmr_ops = {
-.write = openpic_timer_write,
-.read = openpic_timer_read,
-.endianness = DEVICE_BIG_ENDIAN,
-.impl = {
-.min_access_size = 4,
-.max_access_size = 4,
-},
-};
-
-static const MemoryRegionOps mpic_cpu_ops = {
-.write = openpic_cpu_write,
-.read = openpic_cpu_read,
-.endianness = DEVICE_BIG_ENDIAN,
-.impl = {
-.min_access_size = 4,
-.max_access_size = 4,
-},
-};
-
-static const MemoryRegionOps mpic_irq_ops = {
-.write = openpic_src_write,
-.read = openpic_src_read,
-.endianness = DEVICE_BIG_ENDIAN,
-.impl = {
-
[Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions
The openpic and mpic reset handlers are almost identical. Combine
them and extract the differences into state variables.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 103 +++--
1 files changed, 42 insertions(+), 61 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 80016a2..e94529b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -53,7 +53,6 @@
#define MAX_IPI 4
#define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
#define VID 0x03 /* MPIC version ID */
-#define VENI0x /* Vendor ID */
enum {
IRQ_IPVP = 0,
@@ -125,6 +124,14 @@ enum {
#define FSL_BRR1_IPMJ (0x00 8) /* 8 bit IP major number */
#define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
+#define FREP_NIRQ_SHIFT 16
+#define FREP_NCPU_SHIFT8
+#define FREP_VID_SHIFT 0
+
+#define VID_REVISION_1_2 2
+
+#define VENI_GENERIC 0x /* Generic Vendor ID */
+
enum mpic_ide_bits {
IDR_EP = 31,
IDR_CI0 = 30,
@@ -208,6 +215,13 @@ typedef struct openpic_t {
/* Behavior control */
uint32_t flags;
+uint32_t nb_irqs;
+uint32_t vid;
+uint32_t veni; /* Vendor identification register */
+uint32_t spve_mask;
+uint32_t tifr_reset;
+uint32_t ipvp_reset;
+uint32_t ide_reset;
/* Sub-regions */
MemoryRegion sub_io_mem[7];
@@ -215,8 +229,6 @@ typedef struct openpic_t {
/* Global registers */
uint32_t frep; /* Feature reporting register */
uint32_t glbc; /* Global configuration register */
-uint32_t micr; /* MPIC interrupt configuration register */
-uint32_t veni; /* Vendor identification register */
uint32_t pint; /* Processor initialization register */
uint32_t spve; /* Spurious vector register */
uint32_t tifr; /* Timer frequency reporting register */
@@ -235,7 +247,6 @@ typedef struct openpic_t {
int max_irq;
int irq_ipi0;
int irq_tim0;
-void (*reset) (void *);
} openpic_t;
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
@@ -412,17 +423,17 @@ static void openpic_reset (void *opaque)
opp-glbc = 0x8000;
/* Initialise controller registers */
-opp-frep = ((OPENPIC_EXT_IRQ - 1) 16) | ((MAX_CPU - 1) 8) | VID;
-opp-veni = VENI;
+opp-frep = ((opp-nb_irqs -1) FREP_NIRQ_SHIFT) |
+((opp-nb_cpus -1) FREP_NCPU_SHIFT) |
+(opp-vid FREP_VID_SHIFT);
+
opp-pint = 0x;
-opp-spve = 0x00FF;
-opp-tifr = 0x003F7A00;
-/* ? */
-opp-micr = 0x;
+opp-spve = -1 opp-spve_mask;
+opp-tifr = opp-tifr_reset;
/* Initialise IRQ sources */
for (i = 0; i opp-max_irq; i++) {
-opp-src[i].ipvp = 0xA000;
-opp-src[i].ide = 0x;
+opp-src[i].ipvp = opp-ipvp_reset;
+opp-src[i].ide = opp-ide_reset;
}
/* Initialise IRQ destinations */
for (i = 0; i MAX_CPU; i++) {
@@ -499,9 +510,9 @@ static void openpic_gbl_write(void *opaque, hwaddr addr,
uint64_t val,
case 0x1000: /* FREP */
break;
case 0x1020: /* GLBC */
-if (val 0x8000 opp-reset)
-opp-reset(opp);
-opp-glbc = val ~0x8000;
+if (val 0x8000) {
+openpic_reset(opp);
+}
break;
case 0x1080: /* VENI */
break;
@@ -530,7 +541,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr,
uint64_t val,
}
break;
case 0x10E0: /* SPVE */
-opp-spve = val 0x00FF;
+opp-spve = val opp-spve_mask;
break;
default:
break;
@@ -912,9 +923,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
openpic_t *opp = (openpic_t *)opaque;
unsigned int i;
-qemu_put_be32s(f, opp-frep);
qemu_put_be32s(f, opp-glbc);
-qemu_put_be32s(f, opp-micr);
qemu_put_be32s(f, opp-veni);
qemu_put_be32s(f, opp-pint);
qemu_put_be32s(f, opp-spve);
@@ -964,9 +973,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
if (version_id != 1)
return -EINVAL;
-qemu_get_be32s(f, opp-frep);
qemu_get_be32s(f, opp-glbc);
-qemu_get_be32s(f, opp-micr);
qemu_get_be32s(f, opp-veni);
qemu_get_be32s(f, opp-pint);
qemu_get_be32s(f, opp-spve);
@@ -1043,6 +1050,11 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
//isu_base = 0xFFFC;
opp-nb_cpus = nb_cpus;
+opp-nb_irqs = OPENPIC_EXT_IRQ;
+opp-vid = VID;
+opp-veni = VENI_GENERIC;
+opp-spve_mask = 0xFF;
+opp-tifr_reset = 0x003F7A00;
opp-max_irq = OPENPIC_MAX_IRQ;
opp-irq_ipi0 = OPENPIC_IRQ_IPI0;
opp-irq_tim0 = OPENPIC_IRQ_TIM0;
@@ -1068,51 +1080,12 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int
nb_cpus,
openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
-opp-reset = openpic_reset;
-
if (pmem)
[Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state
From: David Gibson da...@gibson.dropbear.id.au
The hwaddr type is somewhat vaguely defined as being able to contain bus
addresses on the widest possible bus in the system. For that reason it's
discouraged for representing specific pieces of persistent hardware state,
which should instead use an explicit width type that matches the bits
available in real hardware. In particular, because of the possibility that
the size of hwaddr might change if different buses are added to the target
in future, it's not suitable for use in vm state descriptions for savevm
and migration.
This patch purges such unwise uses of hwaddr from the ppc target code,
which turns out to be just one. The ppcemb_tlb_t struct, used on a number
of embedded ppc models to represent a TLB entry contains a hwaddr for the
real address field. This patch changes it to be a fixed uint64_t which is
suitable enough for all machine types which use this structure.
Other uses of hwaddr in CPUPPCState turn out not to be problematic:
htab_base and htab_mask are just used for the convenience of the TCG code;
the underlying machine state is the SDR1 register, which is stored with
a suitable type already. Likewise the mpic_cpu_base field is only used
internally and does not represent fundamental hardware state which needs to
be saved.
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5f1dc8b..742d4f8 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -355,7 +355,7 @@ struct ppc6xx_tlb_t {
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
struct ppcemb_tlb_t {
-hwaddr RPN;
+uint64_t RPN;
target_ulong EPN;
target_ulong PID;
target_ulong size;
--
1.6.0.2
[Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge
The new PCI host bridge device needs to identify itself as PCI host bridge. Declare it as such. Signed-off-by: Alexander Graf ag...@suse.de --- hw/ppce500_pci.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 54c72b4..e534341 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -330,9 +330,15 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d) PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), /e500-ccsr)); +pci_config_set_class(d-config, PCI_CLASS_BRIDGE_PCI); +d-config[PCI_HEADER_TYPE] = +(d-config[PCI_HEADER_TYPE] PCI_HEADER_TYPE_MULTI_FUNCTION) | +PCI_HEADER_TYPE_BRIDGE; + memory_region_init_alias(b-bar0, e500-pci-bar0, ccsr-ccsr_space, 0, int128_get64(ccsr-ccsr_space.size)); pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, b-bar0); + return 0; } -- 1.6.0.2
[Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific
Now that we can properly distinguish between openpic model differences,
let's move brr1 out of the raven code path.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 591b291..5bf16ea 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -206,6 +206,7 @@ typedef struct OpenPICState {
uint32_t tifr_reset;
uint32_t ipvp_reset;
uint32_t ide_reset;
+uint32_t brr1;
/* Sub-regions */
MemoryRegion sub_io_mem[7];
@@ -784,7 +785,7 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
hwaddr addr,
addr = 0xFF0;
switch (addr) {
case 0x00: /* Block Revision Register1 (BRR1) */
-retval = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
+retval = opp-brr1;
break;
case 0x80: /* PCTP */
retval = dst-pctp;
@@ -1082,6 +1083,7 @@ static int openpic_init(SysBusDevice *dev)
opp-max_irq = FSL_MPIC_20_MAX_IRQ;
opp-irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
opp-irq_tim0 = FSL_MPIC_20_TMR_IRQ;
+opp-brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
list = list_be;
break;
case OPENPIC_MODEL_RAVEN:
@@ -1095,6 +1097,7 @@ static int openpic_init(SysBusDevice *dev)
opp-max_irq = RAVEN_MAX_IRQ;
opp-irq_ipi0 = RAVEN_IPI_IRQ;
opp-irq_tim0 = RAVEN_TMR_IRQ;
+opp-brr1 = -1;
list = list_le;
/* Only UP supported today */
--
1.6.0.2
[Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic
The IRQ line calculation is more or less hardcoded today. Instead, let's
write it as an algorithmic function that theoretically allows an arbitrary
number of PCI slots.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_pci.c | 13 +++--
1 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 4cd4edc..561a776 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -253,17 +253,10 @@ static const MemoryRegionOps e500_pci_reg_ops = {
static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
-int devno = pci_dev-devfn 3, ret = 0;
+int devno = pci_dev-devfn 3;
+int ret;
-switch (devno) {
-/* Two PCI slot */
-case 0x11:
-case 0x12:
-ret = (irq_num + devno - 0x10) % 4;
-break;
-default:
-printf(Error:%s:unknown dev number\n, __func__);
-}
+ret = (irq_num + devno) % 4;
pci_debug(%s: devfn %x irq %d - %d devno:%x\n, __func__,
pci_dev-devfn, irq_num, ret, devno);
--
1.6.0.2
[Qemu-devel] [PATCH 28/40] PPC: e500: Add MSI support
Now that our interrupt controller supports MSIs, let's expose that feature
to the guest through the device tree!
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500.c | 23 +++
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index fa9b8ed..1034f93 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,7 @@
#define MPC8544_CCSRBAR_BASE 0xE000ULL
#define MPC8544_CCSRBAR_SIZE 0x0010ULL
#define MPC8544_MPIC_REGS_OFFSET 0x4ULL
+#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
#define MPC8544_PCI_REGS_OFFSET0x8000ULL
@@ -127,8 +128,10 @@ static int ppce500_load_device_tree(CPUPPCState *env,
char soc[128];
char mpic[128];
uint32_t mpic_ph;
+uint32_t msi_ph;
char gutil[128];
char pci[128];
+char msi[128];
uint32_t pci_map[7 * 8];
uint32_t pci_ranges[14] =
{
@@ -300,6 +303,25 @@ static int ppce500_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_cells(fdt, gutil, reg, MPC8544_UTIL_OFFSET, 0x1000);
qemu_devtree_setprop(fdt, gutil, fsl,has-rstcr, NULL, 0);
+snprintf(msi, sizeof(msi), /%s/msi@%llx, soc, MPC8544_MSI_REGS_OFFSET);
+qemu_devtree_add_subnode(fdt, msi);
+qemu_devtree_setprop_string(fdt, msi, compatible, fsl,mpic-msi);
+qemu_devtree_setprop_cells(fdt, msi, reg, MPC8544_MSI_REGS_OFFSET,
0x200);
+msi_ph = qemu_devtree_alloc_phandle(fdt);
+qemu_devtree_setprop_cells(fdt, msi, msi-available-ranges, 0x0, 0x100);
+qemu_devtree_setprop_phandle(fdt, msi, interrupt-parent, mpic);
+qemu_devtree_setprop_cells(fdt, msi, interrupts,
+0xe0, 0x0,
+0xe1, 0x0,
+0xe2, 0x0,
+0xe3, 0x0,
+0xe4, 0x0,
+0xe5, 0x0,
+0xe6, 0x0,
+0xe7, 0x0);
+qemu_devtree_setprop_cell(fdt, msi, phandle, msi_ph);
+qemu_devtree_setprop_cell(fdt, msi, linux,phandle, msi_ph);
+
snprintf(pci, sizeof(pci), /pci@%llx, MPC8544_PCI_REGS_BASE);
qemu_devtree_add_subnode(fdt, pci);
qemu_devtree_setprop_cell(fdt, pci, cell-index, 0);
@@ -315,6 +337,7 @@ static int ppce500_load_device_tree(CPUPPCState *env,
for (i = 0; i 14; i++) {
pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
}
+qemu_devtree_setprop_cell(fdt, pci, fsl,msi, msi_ph);
qemu_devtree_setprop(fdt, pci, ranges, pci_ranges, sizeof(pci_ranges));
qemu_devtree_setprop_cells(fdt, pci, reg, MPC8544_PCI_REGS_BASE 32,
MPC8544_PCI_REGS_BASE, 0, 0x1000);
--
1.6.0.2
[Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number
From: Ben Herrenschmidt b...@kernel.crashing.org Currently the lowest real irq number for the XICS irq controller (as opposed to numbers reserved for IPIs and other special purposes) is hard coded as 16 in two places - in xics_system_init() and in spapr.c. As well as being generally bad practice, we're going to need to change this number soon to fit in with the in-kernel XICS implementation. This patch adds a #define for this number to avoid future breakage. Signed-off-by: Michael Ellerman mich...@ellerman.id.au Signed-off-by: Ben Herrenschmidt b...@kernel.crashing.org Signed-off-by: David Gibson da...@gibson.dropbear.id.au Signed-off-by: Alexander Graf ag...@suse.de --- hw/spapr.c |2 +- hw/xics.c |2 +- hw/xics.h |1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index ad3f0ea..eafee03 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -801,7 +801,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) /* Set up Interrupt Controller */ spapr-icp = xics_system_init(XICS_IRQS); -spapr-next_irq = 16; +spapr-next_irq = XICS_IRQ_BASE; /* Set up EPOW events infrastructure */ spapr_events_init(spapr); diff --git a/hw/xics.c b/hw/xics.c index edf5833..b8887cd 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -549,7 +549,7 @@ struct icp_state *xics_system_init(int nr_irqs) ics = g_malloc0(sizeof(*ics)); ics-nr_irqs = nr_irqs; -ics-offset = 16; +ics-offset = XICS_IRQ_BASE; ics-irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state)); icp-ics = ics; diff --git a/hw/xics.h b/hw/xics.h index 6817268..c3bf008 100644 --- a/hw/xics.h +++ b/hw/xics.h @@ -28,6 +28,7 @@ #define __XICS_H__ #define XICS_IPI0x2 +#define XICS_IRQ_BASE 0x10 struct icp_state; -- 1.6.0.2
[Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler
From: Ben Herrenschmidt b...@kernel.crashing.org
Kernel-based RTAS calls will not have a qemu handler, but will
still be registered in qemu in order to be assigned a token
number and appear in the device-tree.
Let's test for the name being NULL rather than the handler
when deciding to skip an entry while building the device-tree
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/spapr_rtas.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index 45294e8..e618c2d 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -301,7 +301,7 @@ int spapr_rtas_device_tree_setup(void *fdt, hwaddr
rtas_addr,
for (i = 0; i TOKEN_MAX; i++) {
struct rtas_call *call = rtas_table[i];
-if (!call-fn) {
+if (!call-name) {
continue;
}
--
1.6.0.2
Re: [Qemu-devel] [PATCH 3/3] chardev: add hotplug support.
Il 14/12/2012 10:38, Gerd Hoffmann ha scritto:
This patch adds chardev_add_file, chardev_add_tty and chardev_remove
monitor commands.
chardev_add_file and chardev_add_tty expect an id and a path, they
create a file/tty chardev.
I'd rather avoid introducing this interface. Using multiple commands is
different from all previous examples, both HMP and QMP (including recent
ones such as the NBD server). It is also hard to extend, for example
file descriptor passing is hard to retrofit.
Perhaps you can define a QAPI union and slowly build it up? Something
that ultimately can become this:
{ 'enum': 'ChardevFileMode', 'data':
# pty = console under Windows
# serial = tty under POSIX
[ 'file', 'pipe', 'parport', 'pty', 'serial' ] }
{ 'enum: 'ChardevFileSource', 'data':
[ 'path', 'fd' ] }
{ 'type': 'ChardevFile',
'data': {'source': 'string', 'source-type': 'ChardevFileSource',
'mode': 'ChardevFileMode'}}
{ 'type': 'ChardevVC',
'data': {'width': 'int', 'height': 'int', '*characters': 'bool'}}
{ 'type': 'ChardevSocket',
'data': {'addr': 'SocketAddress', '*server': 'bool',
'*wait': 'bool', '*nodelay': 'bool', '*telnet': 'bool'} }
# For future extensibility...
{ 'ChardevDummy', 'data': {} }
{ 'union': 'ChardevBackend', 'data': {
'socket': 'ChardevSocket',
'udp': 'UDPSocketAddress',
'file': 'ChardevFile',
'null': 'ChardevDummy',
'msmouse': 'ChardevDummy',
'braille': 'ChardevDummy',
'stdio': 'ChardevDummy',
'vc': 'ChardevVC',
# Solely for HMP usage.
'legacy': 'str'
}
{ 'command': 'chardev-add', 'data': {
'backend': 'ChardevBackend', 'id': 'str', '*mux': 'bool' } }
A simple conversion from this to QemuOpts should be easy, later the
backends can move to taking a ChardevBackend *.
Paolo
chardev_del just takes an id argument and zaps the chardev specified.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hmp-commands.hx | 44 +++
hmp.c| 29
hmp.h|3 ++
qapi-schema.json | 43 ++
qemu-char.c | 41 +
qemu-char.h |2 +
qmp-commands.hx | 76
++
7 files changed, 238 insertions(+), 0 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 010b8c9..82a855a 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1485,6 +1485,50 @@ passed since 1970, i.e. unix epoch.
ETEXI
{
+.name = chardev_add_file,
+.args_type = id:s,path:s,
+.params = id path ,
+.help = add file chardev,
+.mhandler.cmd = hmp_chardev_add_file,
+},
+
+STEXI
+@item chardev_add_file id path
+@findex chardev_add_file
+
+ETEXI
+
+{
+.name = chardev_add_tty,
+.args_type = id:s,path:s,
+.params = id path ,
+.help = add tty chardev,
+.mhandler.cmd = hmp_chardev_add_tty,
+},
+
+STEXI
+@item chardev_add_tty id path
+@findex chardev_add_tty
+
+ETEXI
+
+{
+.name = chardev_remove,
+.args_type = id:s,
+.params = id,
+.help = remove chardev,
+.mhandler.cmd = hmp_chardev_remove,
+},
+
+STEXI
+@item chardev_remove id
+@findex chardev_remove
+
+Removes the chardev @var{id}.
+
+ETEXI
+
+{
.name = info,
.args_type = item:s?,
.params = [subcommand],
diff --git a/hmp.c b/hmp.c
index 180ba2b..8780e7c 100644
--- a/hmp.c
+++ b/hmp.c
@@ -1335,3 +1335,32 @@ void hmp_nbd_server_stop(Monitor *mon, const QDict
*qdict)
qmp_nbd_server_stop(errp);
hmp_handle_error(mon, errp);
}
+
+static void hmp_chardev_add_path(Monitor *mon, const QDict *qdict,
+ const char *backend)
+{
+const char *id = qdict_get_str(qdict, args);
+const char *path = qdict_get_str(qdict, path);
+Error *local_err = NULL;
+
+qmp_chardev_add_path(id, path, backend, local_err);
+hmp_handle_error(mon, local_err);
+}
+
+void hmp_chardev_add_file(Monitor *mon, const QDict *qdict)
+{
+hmp_chardev_add_path(mon, qdict, file);
+}
+
+void hmp_chardev_add_tty(Monitor *mon, const QDict *qdict)
+{
+hmp_chardev_add_path(mon, qdict, tty);
+}
+
+void hmp_chardev_remove(Monitor *mon, const QDict *qdict)
+{
+Error *local_err = NULL;
+
+qmp_chardev_remove(qdict_get_str(qdict, id), local_err);
+hmp_handle_error(mon, local_err);
+}
diff --git a/hmp.h b/hmp.h
index 0ab03be..8cd50d1 100644
--- a/hmp.h
+++ b/hmp.h
@@ -80,5 +80,8 @@ void hmp_screen_dump(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_start(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_add(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_stop(Monitor *mon, const QDict *qdict);
+void hmp_chardev_add_file(Monitor *mon, const QDict
Re: [Qemu-devel] [PATCH 2/2] qemu-img:report size overflow error message
liguang lig.f...@cn.fujitsu.com writes:
qemu-img will complain when qcow or qcow2
size overflow for 64 bits, report the right
message in this condition.
before change:
qemu-img: Invalid image size specified! You may use k, M, G or T suffixes for
qemu-img: kilobytes, megabytes, gigabytes and terabytes.
after change:
qemu-img: Image size must be less than 8 exabytes!
Signed-off-by: liguang lig.f...@cn.fujitsu.com
---
qemu-img.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index e29e01b..1c3af67 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -346,13 +346,18 @@ static int img_create(int argc, char **argv)
int64_t sval;
char *end;
sval = strtosz_suffix(argv[optind++], end, STRTOSZ_DEFSUFFIX_B);
-if (sval 0 || *end) {
+if (sval == EINVAL || *end) {
error_report(Invalid image size specified! You may use k, M, G
or
T suffixes for );
error_report(kilobytes, megabytes, gigabytes and terabytes.);
ret = -1;
goto out;
}
+if (sval == ERANGE) {
+error_report(Image size must be less than 8 exabytes!);
+ret = -1;
+goto out;
+}
img_size = (uint64_t)sval;
}
If strtosz_suffix() ever acquires additional error codes, this caller
will fail to detect the failure. Try something like
if (sval 0 || *end) {
if (sval == -ERANGE) {
error_report(Image size must be less than 8 exabytes!);
} else {
error_report(Invalid image size specified!
You may use k, M, G or T suffixes for);
error_report(kilobytes, megabytes, gigabytes and terabytes.);
}
ret = -1;
goto out;
}
To be pedantically correct, 8 exabytes should be 8 Exbibytes or 8
EiB.
[Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api
The openpic controller is currently using one big region and does
subregion dispatching manually. Move this to the memory api.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 106 +
1 files changed, 61 insertions(+), 45 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index b671d9d..2a3b56a 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -79,6 +79,15 @@ enum {
#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First
mailbox IRQ */
#endif
+#define OPENPIC_GLB_REG_START0x0
+#define OPENPIC_GLB_REG_SIZE 0x10F0
+#define OPENPIC_TMR_REG_START0x10F0
+#define OPENPIC_TMR_REG_SIZE 0x220
+#define OPENPIC_SRC_REG_START0x1
+#define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
+#define OPENPIC_CPU_REG_START0x2
+#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
+
/* MPIC */
#define MPIC_MAX_CPU 1
#define MPIC_MAX_EXT 12
@@ -842,53 +851,39 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr
addr, unsigned len)
return openpic_cpu_read_internal(opaque, addr, (addr 0x1f000) 12);
}
-static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned len)
-{
-openpic_t *opp = opaque;
-
-DPRINTF(%s: offset %08x val: %08x\n, __func__, (int)addr, val);
-if (addr 0x1100) {
-/* Global registers */
-openpic_gbl_write(opp, addr, val, len);
-} else if (addr 0x1) {
-/* Timers registers */
-openpic_timer_write(opp, addr, val, len);
-} else if (addr 0x2) {
-/* Source registers */
-openpic_src_write(opp, addr, val, len);
-} else {
-/* CPU registers */
-openpic_cpu_write(opp, addr, val, len);
-}
-}
-
-static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
-{
-openpic_t *opp = opaque;
-uint32_t retval;
+static const MemoryRegionOps openpic_glb_ops = {
+.write = openpic_gbl_write,
+.read = openpic_gbl_read,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
-DPRINTF(%s: offset %08x\n, __func__, (int)addr);
-if (addr 0x1100) {
-/* Global registers */
-retval = openpic_gbl_read(opp, addr, len);
-} else if (addr 0x1) {
-/* Timers registers */
-retval = openpic_timer_read(opp, addr, len);
-} else if (addr 0x2) {
-/* Source registers */
-retval = openpic_src_read(opp, addr, len);
-} else {
-/* CPU registers */
-retval = openpic_cpu_read(opp, addr, len);
-}
+static const MemoryRegionOps openpic_tmr_ops = {
+.write = openpic_timer_write,
+.read = openpic_timer_read,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
-return retval;
-}
+static const MemoryRegionOps openpic_cpu_ops = {
+.write = openpic_cpu_write,
+.read = openpic_cpu_read,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
-static const MemoryRegionOps openpic_ops = {
-.read = openpic_read,
-.write = openpic_write,
+static const MemoryRegionOps openpic_src_ops = {
+.write = openpic_src_write,
+.read = openpic_src_read,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
@@ -1009,12 +1004,33 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int
nb_cpus,
{
openpic_t *opp;
int i, m;
+struct {
+const char *name;
+MemoryRegionOps const *ops;
+hwaddr start_addr;
+ram_addr_t size;
+} const list[] = {
+{glb, openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
+{tmr, openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
+{src, openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
+{cpu, openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
+};
/* XXX: for now, only one CPU is supported */
if (nb_cpus != 1)
return NULL;
opp = g_malloc0(sizeof(openpic_t));
-memory_region_init_io(opp-mem, openpic_ops, opp, openpic, 0x4);
+
+memory_region_init(opp-mem, openpic, 0x4);
+
+for (i = 0; i ARRAY_SIZE(list); i++) {
+
+memory_region_init_io(opp-sub_io_mem[i], list[i].ops, opp,
+ list[i].name, list[i].size);
+
+memory_region_add_subregion(opp-mem, list[i].start_addr,
+opp-sub_io_mem[i]);
+}
//isu_base = 0xFFFC;
opp-nb_cpus = nb_cpus;
--
1.6.0.2
[Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller
From: David Gibson da...@gibson.dropbear.id.au
This patch adds tracing / debugging calls to the XICS interrupt controller
implementation used on the pseries machine.
Signed-off-by: Ben Herrenschmidt b...@kernel.crashing.org
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/xics.c| 23 ---
trace-events | 13 +
2 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/hw/xics.c b/hw/xics.c
index b8887cd..33f99c7 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -26,6 +26,7 @@
*/
#include hw.h
+#include trace.h
#include hw/spapr.h
#include hw/xics.h
@@ -66,6 +67,8 @@ static void icp_check_ipi(struct icp_state *icp, int server)
return;
}
+trace_xics_icp_check_ipi(server, ss-mfrr);
+
if (XISR(ss)) {
ics_reject(icp-ics, XISR(ss));
}
@@ -120,11 +123,13 @@ static void icp_set_mfrr(struct icp_state *icp, int
server, uint8_t mfrr)
static uint32_t icp_accept(struct icp_server_state *ss)
{
-uint32_t xirr;
+uint32_t xirr = ss-xirr;
qemu_irq_lower(ss-output);
-xirr = ss-xirr;
ss-xirr = ss-pending_priority 24;
+
+trace_xics_icp_accept(xirr, ss-xirr);
+
return xirr;
}
@@ -134,6 +139,7 @@ static void icp_eoi(struct icp_state *icp, int server,
uint32_t xirr)
/* Send EOI - ICS */
ss-xirr = (ss-xirr ~CPPR_MASK) | (xirr CPPR_MASK);
+trace_xics_icp_eoi(server, xirr, ss-xirr);
ics_eoi(icp-ics, xirr XISR_MASK);
if (!XISR(ss)) {
icp_resend(icp, server);
@@ -144,6 +150,8 @@ static void icp_irq(struct icp_state *icp, int server, int
nr, uint8_t priority)
{
struct icp_server_state *ss = icp-ss + server;
+trace_xics_icp_irq(server, nr, priority);
+
if ((priority = CPPR(ss))
|| (XISR(ss) (ss-pending_priority = priority))) {
ics_reject(icp-ics, nr);
@@ -153,6 +161,7 @@ static void icp_irq(struct icp_state *icp, int server, int
nr, uint8_t priority)
}
ss-xirr = (ss-xirr ~XISR_MASK) | (nr XISR_MASK);
ss-pending_priority = priority;
+trace_xics_icp_raise(ss-xirr, ss-pending_priority);
qemu_irq_raise(ss-output);
}
}
@@ -217,10 +226,12 @@ static void set_irq_msi(struct ics_state *ics, int srcno,
int val)
{
struct ics_irq_state *irq = ics-irqs + srcno;
+trace_xics_set_irq_msi(srcno, srcno + ics-offset);
+
if (val) {
if (irq-priority == 0xff) {
irq-status |= XICS_STATUS_MASKED_PENDING;
-/* masked pending */ ;
+trace_xics_masked_pending();
} else {
icp_irq(ics-icp, irq-server, srcno + ics-offset, irq-priority);
}
@@ -231,6 +242,7 @@ static void set_irq_lsi(struct ics_state *ics, int srcno,
int val)
{
struct ics_irq_state *irq = ics-irqs + srcno;
+trace_xics_set_irq_lsi(srcno, srcno + ics-offset);
if (val) {
irq-status |= XICS_STATUS_ASSERTED;
} else {
@@ -279,6 +291,8 @@ static void ics_write_xive(struct ics_state *ics, int nr,
int server,
irq-priority = priority;
irq-saved_priority = saved_priority;
+trace_xics_ics_write_xive(nr, srcno, server, priority);
+
if (irq-lsi) {
write_xive_lsi(ics, srcno);
} else {
@@ -290,6 +304,7 @@ static void ics_reject(struct ics_state *ics, int nr)
{
struct ics_irq_state *irq = ics-irqs + nr - ics-offset;
+trace_xics_ics_reject(nr, nr - ics-offset);
irq-status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
irq-status = ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
}
@@ -315,6 +330,8 @@ static void ics_eoi(struct ics_state *ics, int nr)
int srcno = nr - ics-offset;
struct ics_irq_state *irq = ics-irqs + srcno;
+trace_xics_ics_eoi(nr);
+
if (irq-lsi) {
irq-status = ~XICS_STATUS_SENT;
}
diff --git a/trace-events b/trace-events
index 6c6cbf1..6cb450a 100644
--- a/trace-events
+++ b/trace-events
@@ -1022,3 +1022,16 @@ spapr_pci_rtas_ibm_change_msi(unsigned func, unsigned
req) func %u, requested %
spapr_pci_rtas_ibm_query_interrupt_source_number(unsigned ioa, unsigned intr)
queries for #%u, IRQ%u
spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq)
@%PRIx64=%PRIx64 IRQ %u
spapr_pci_lsi_set(const char *busname, int pin, uint32_t irq) %s PIN%d IRQ %u
+
+# hw/xics.c
+xics_icp_check_ipi(int server, uint8_t mfrr) CPU %d can take IPI mfrr=%#x
+xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) icp_accept: XIRR
%#PRIx32-%#PRIx32
+xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) icp_eoi: server %d
given XIRR %#PRIx32 new XIRR %#PRIx32
+xics_icp_irq(int server, int nr, uint8_t priority) cpu %d trying to deliver
irq %#PRIx32 priority %#x
+xics_icp_raise(uint32_t xirr, uint8_t pending_priority) raising IRQ new
XIRR=%#x new pending priority=%#x
+xics_set_irq_msi(int srcno, int nr) set_irq_msi: srcno %d [irq %#x]
Re: [Qemu-devel] [PATCH 3/3] target-i386: replace cpuid_*features fields with a feature word array
On Fri, Dec 14, 2012 at 10:38:50AM +0100, Igor Mammedov wrote: On Wed, 12 Dec 2012 20:22:26 -0200 Eduardo Habkost ehabk...@redhat.com wrote: This replaces the feature-bit fields on both X86CPU and x86_def_t structs with an array. With this, we will be able to simplify code that simply does the same operation on all feature words (e.g. kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), and CPU feature-bit property lookup/registration). do you have a patch that simplifies kvm_check_features_against_host() using this? I have a very old one, based on an older (and more complex) version of this series: https://github.com/ehabkost/qemu-hacks/commit/eb01d374baecf6df26fd6f0d0bb23f2e1547f499 It's in the work/cpuid-refactor-v0.22-2012-08-31 branch in my git repository. That branch also has some patches to merge kvm_check_features_against_host() and filter_features_for_kvm() (because the purpose of kvm_check_features_against_host() is simply to check if anything is going to be filtered out by filter_features_for_kvm()). If people are happy with the approach in this series, I plan to write and submit cleanups for kvm_cpu_fill_host(), kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), and the cpudef - CPU feature copying code. There's so much code that could be cleaned up using the array, that I am afraid that it would cause too much conflicts in the CPU properties work. So I can wait until the CPU properties series are submitted before making the cleanups, if necessary. -- Eduardo
[Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller
From: David Gibson da...@gibson.dropbear.id.au
Currently in the reset code for the XICS interrupt controller, we
initialize the pending_priority field to 0 (most favored, by XICS
convention). This is incorrect, since there is no pending interrupt, it
should be set to least favored - 0xff. At the moment our XICS
implementation doesn't get hurt by this edge case, but it does confuse the
upcoming kernel XICS implementation.
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/xics.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/xics.c b/hw/xics.c
index 1da3106..edf5833 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -495,7 +495,7 @@ static void xics_reset(void *opaque)
for (i = 0; i icp-nr_servers; i++) {
icp-ss[i].xirr = 0;
-icp-ss[i].pending_priority = 0;
+icp-ss[i].pending_priority = 0xff;
icp-ss[i].mfrr = 0xff;
/* Make all outputs are deasserted */
qemu_set_irq(icp-ss[i].output, 0);
--
1.6.0.2
[Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call
From: Michael Ellerman mich...@ellerman.id.au
The kernel will soon be able to service some RTAS calls. However the
choice of tokens will still be up to userspace. To support this have
spapr_rtas_register() return the token that is allocated for an
RTAS call, that allows the calling code to tell the kernel what the
token value is.
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/spapr.h |2 +-
hw/spapr_rtas.c |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/spapr.h b/hw/spapr.h
index efe7f57..971a50a 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -320,7 +320,7 @@ static inline void rtas_st(target_ulong phys, int n,
uint32_t val)
typedef void (*spapr_rtas_fn)(sPAPREnvironment *spapr, uint32_t token,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets);
-void spapr_rtas_register(const char *name, spapr_rtas_fn fn);
+int spapr_rtas_register(const char *name, spapr_rtas_fn fn);
target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
uint32_t token, uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets);
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index 6d5c48a..45294e8 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -242,7 +242,7 @@ target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
return H_PARAMETER;
}
-void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
+int spapr_rtas_register(const char *name, spapr_rtas_fn fn)
{
int i;
@@ -258,7 +258,7 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
rtas_next-name = name;
rtas_next-fn = fn;
-rtas_next++;
+return (rtas_next++ - rtas_table) + TOKEN_BASE;
}
int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
--
1.6.0.2
Re: [Qemu-devel] [PATCH 4/6] openpic: don't crash on a register access without a CPU context
On 14.12.2012, at 03:12, Scott Wood wrote:
If we access a register via the QEMU memory inspection commands (e.g.
xp) rather than from guest code, we won't have a CPU context.
Gracefully fail to access the register in that case, rather than
crashing.
Can't we set cpu_single_env in the debug memory access case? I'm not sure this
is the only device with that problem, and by always having cpu_single_env
available we would completely get rid of the whole bug category.
Alex
Signed-off-by: Scott Wood scottw...@freescale.com
---
hw/openpic.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 8c3f04d..c57a168 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -161,7 +161,11 @@ static inline int test_bit(uint32_t *field, int bit)
static int get_current_cpu(void)
{
- return cpu_single_env-cpu_index;
+if (!cpu_single_env) {
+return -1;
+}
+
+return cpu_single_env-cpu_index;
}
static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
@@ -797,6 +801,11 @@ static void openpic_cpu_write_internal(void *opaque,
hwaddr addr,
DPRINTF(%s: cpu %d addr TARGET_FMT_plx = %08x\n, __func__, idx,
addr, val);
+
+if (idx 0) {
+return;
+}
+
if (addr 0xF)
return;
dst = opp-dst[idx];
@@ -862,6 +871,11 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
hwaddr addr,
DPRINTF(%s: cpu %d addr TARGET_FMT_plx \n, __func__, idx, addr);
retval = 0x;
+
+if (idx 0) {
+return retval;
+}
+
if (addr 0xF)
return retval;
dst = opp-dst[idx];
--
1.7.9.5
[Qemu-devel] [Bug 1087974] Re: [regression] vnc tight png produces garbled output
The patch does fix the issue for me, thanks. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1087974 Title: [regression] vnc tight png produces garbled output Status in QEMU: New Bug description: VNC Tight PNG compression did work fine two or three month ago but don't anymore. Now when Tight PNG is used parts of the desktop are shown but they are scrambled together. I have always tested this feature against QEMU git with noVNC by only allowing Tight PNG compression. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1087974/+subscriptions
Re: [Qemu-devel] [PATCH 06/30] migration: stop all cpus correctly
Paolo Bonzini pbonz...@redhat.com wrote:
Il 12/11/2012 12:44, Paolo Bonzini ha scritto:
@@ -339,7 +351,11 @@ void migrate_fd_put_ready(MigrationState *s)
DPRINTF(done iterating\n);
start_time = qemu_get_clock_ms(rt_clock);
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
-vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
+if (old_vm_running) {
+vm_stop(RUN_STATE_FINISH_MIGRATE);
+} else {
+vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
+}
if (qemu_savevm_state_complete(s-file) 0) {
migrate_fd_error(s);
This hunk also seems to be useless nowadays.
it is needed for when we are migrating in suspended state. We need to
fix it some other way, but it needs to remaing for now.
Re: [Qemu-devel] [PATCH 2/2] target-i386: make cpu_x86_create() get Error argument
On Fri, Dec 14, 2012 at 11:18:18AM +0100, Igor Mammedov wrote:
On Wed, 12 Dec 2012 16:16:23 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
Instead of forcing the caller to guess what went wrong while creating
the CPU object, return error information in a Error argument.
Also, as cpu_x86_create() won't print error messages itself anymore,
change cpu_x86_init() to print any error returned by cpu_x86_create()
or cpu_x86_realize().
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu.c| 8 ++--
target-i386/cpu.h| 2 +-
target-i386/helper.c | 21 ++---
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b242bf1..fba872d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1542,7 +1542,7 @@ static void filter_features_for_kvm(X86CPU *cpu)
/* Create and initialize a X86CPU object, based on the full CPU model
string
* (that may include +feature,-feature,feature=xxx feature strings)
*/
-X86CPU *cpu_x86_create(const char *cpu_model)
+X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
{
X86CPU *cpu;
CPUX86State *env;
@@ -1559,12 +1559,14 @@ X86CPU *cpu_x86_create(const char *cpu_model)
model_pieces = g_strsplit(cpu_model, ,, 2);
if (!model_pieces[0]) {
+error_setg(errp, invalid CPU model string: %s, cpu_model);
goto error;
}
name = model_pieces[0];
features = model_pieces[1];
if (cpu_x86_find_by_name(def, name) 0) {
+error_setg(errp, CPU model not found: %s, name);
goto error;
}
@@ -1575,13 +1577,15 @@ X86CPU *cpu_x86_create(const char *cpu_model)
def-svm_features,
def-cpuid_7_0_ebx_features);
if (cpu_x86_parse_featurestr(def, features) 0) {
+error_setg(errp, Error parsing feature string: %s,
+ features ? features : (none));
It could be simplified, it shouldn't get here if features == NULL
It could be something like:
if (features cpu_x86_parse_featurestr(def, features) 0) {
...
}
Both options are reasonable to me.
goto error;
}
cpudef_2_x86_cpu(cpu, def, error);
if (error) {
-fprintf(stderr, %s\n, error_get_pretty(error));
+error_propagate(errp, error);
Why do it here but not above?
Because the other functions called above don't get an Error object
(yet). :-)
error_free(error);
goto error;
}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
[...]
X86CPU *cpu_x86_init(const char *cpu_model)
{
-X86CPU *cpu;
+X86CPU *cpu = NULL;
Error *error = NULL;
-cpu = cpu_x86_create(cpu_model);
-if (!cpu) {
-return NULL;
+cpu = cpu_x86_create(cpu_model, error);
+if (error) {
+goto error;
}
x86_cpu_realize(OBJECT(cpu), error);
if x86_cpu_realize() behave as visit* functions, i.e. return early if
error has been already set, error check goto could be removed here
and above and consolidated at function exit.
I'm not sure I want to use that coding style. Expecting every function
to abort in the beginning if Error is set sounds fragile, to me. I would
even expect the maintainers to complain if I wrote the code that way (as
I never saw that style being used in any code except the visitors).
The visitors seem to be different because they are called from
automatically-generated QAPI code, that can't know if errors in a give
visit should abort the rest of the process, or not.
if (error) {
-error_free(error);
-object_delete(OBJECT(cpu));
-return NULL;
+goto error;
}
return cpu;
+
+error:
+if (cpu) {
+object_delete(OBJECT(cpu));
+}
+error_report(%s, error_get_pretty(error));
+error_free(error);
+return NULL;
}
#if !defined(CONFIG_USER_ONLY)
--
1.7.11.7
--
Regards,
Igor
--
Eduardo
Re: [Qemu-devel] [PATCH 0/6] openpic: first batch of cleanups and minor fixes
On 14.12.2012, at 03:11, Scott Wood wrote: There'll be more to come, but here's an initial set of cleanups and fixes for openpic. Thanks, applied all except for 4/6 to ppc-next. Alex This is based on the ppc-mpic-cleanup branch in git://repo.or.cz/qemu/agraf.git Scott Wood (6): openpic: symbolicize some magic numbers openpic: remove pcsr (CPU sensitivity register) openpic: support large vectors on FSL mpic openpic: don't crash on a register access without a CPU context openpic: BRR1 is not a CPU-specific register. openpic: s/opp-nb_irqs -1/opp-nb_cpus - 1/ hw/openpic.c | 102 +- 1 file changed, 59 insertions(+), 43 deletions(-) -- 1.7.9.5
[Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size
From: David Gibson da...@gibson.dropbear.id.au
If no image file for NVRAM is specified, the pseries machine currently
creates a 16K non-persistent NVRAM by default. This basically works, but
is not large enough for current firmware and guest kernels to create all
the NVRAM partitions they would like to. Increasing the default size to
64K addresses this and stops the guest generating error messages.
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/spapr_nvram.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/spapr_nvram.c b/hw/spapr_nvram.c
index 641de48..512bb8d 100644
--- a/hw/spapr_nvram.c
+++ b/hw/spapr_nvram.c
@@ -37,7 +37,7 @@ typedef struct sPAPRNVRAM {
} sPAPRNVRAM;
#define MIN_NVRAM_SIZE 8192
-#define DEFAULT_NVRAM_SIZE 16384
+#define DEFAULT_NVRAM_SIZE 65536
#define MAX_NVRAM_SIZE (UINT16_MAX * 16)
static void rtas_nvram_fetch(sPAPREnvironment *spapr,
--
1.6.0.2
[Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information
From: David Gibson da...@gibson.dropbear.id.au
Currently the XICS irq controller code has a per-irq state structure which
amongst other things includes whether the interrupt is level or message
triggered - this is configured by the platform code, and is not directly
visible to the guest. This leads to a slightly awkward construct at reset
time where we need to reset everything in the state structure _except_ the
lsi/msi flag, which needs to retain the information given at platform init
time.
More importantly this flag will make matching the qemu state to the KVM
state for the upcoming in-kernel XICS implementation more awkward. This
patch, therefore, removes this flag from the per-irq state structure,
instead adding a parallel array giving the lsi/msi configuration per irq.
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/xics.c | 20
1 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/hw/xics.c b/hw/xics.c
index 33f99c7..55899ce 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -179,13 +179,13 @@ struct ics_irq_state {
#define XICS_STATUS_REJECTED 0x4
#define XICS_STATUS_MASKED_PENDING 0x8
uint8_t status;
-bool lsi;
};
struct ics_state {
int nr_irqs;
int offset;
qemu_irq *qirqs;
+bool *islsi;
struct ics_irq_state *irqs;
struct icp_state *icp;
};
@@ -254,9 +254,8 @@ static void set_irq_lsi(struct ics_state *ics, int srcno,
int val)
static void ics_set_irq(void *opaque, int srcno, int val)
{
struct ics_state *ics = (struct ics_state *)opaque;
-struct ics_irq_state *irq = ics-irqs + srcno;
-if (irq-lsi) {
+if (ics-islsi[srcno]) {
set_irq_lsi(ics, srcno, val);
} else {
set_irq_msi(ics, srcno, val);
@@ -293,7 +292,7 @@ static void ics_write_xive(struct ics_state *ics, int nr,
int server,
trace_xics_ics_write_xive(nr, srcno, server, priority);
-if (irq-lsi) {
+if (ics-islsi[srcno]) {
write_xive_lsi(ics, srcno);
} else {
write_xive_msi(ics, srcno);
@@ -314,10 +313,8 @@ static void ics_resend(struct ics_state *ics)
int i;
for (i = 0; i ics-nr_irqs; i++) {
-struct ics_irq_state *irq = ics-irqs + i;
-
/* FIXME: filter by server#? */
-if (irq-lsi) {
+if (ics-islsi[i]) {
resend_lsi(ics, i);
} else {
resend_msi(ics, i);
@@ -332,7 +329,7 @@ static void ics_eoi(struct ics_state *ics, int nr)
trace_xics_ics_eoi(nr);
-if (irq-lsi) {
+if (ics-islsi[srcno]) {
irq-status = ~XICS_STATUS_SENT;
}
}
@@ -354,7 +351,7 @@ void xics_set_irq_type(struct icp_state *icp, int irq, bool
lsi)
{
assert(ics_valid_irq(icp-ics, irq));
-icp-ics-irqs[irq - icp-ics-offset].lsi = lsi;
+icp-ics-islsi[irq - icp-ics-offset] = lsi;
}
static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
@@ -518,10 +515,8 @@ static void xics_reset(void *opaque)
qemu_set_irq(icp-ss[i].output, 0);
}
+memset(ics-irqs, 0, sizeof(struct ics_irq_state) * ics-nr_irqs);
for (i = 0; i ics-nr_irqs; i++) {
-/* Reset everything *except* the type */
-ics-irqs[i].server = 0;
-ics-irqs[i].status = 0;
ics-irqs[i].priority = 0xff;
ics-irqs[i].saved_priority = 0xff;
}
@@ -568,6 +563,7 @@ struct icp_state *xics_system_init(int nr_irqs)
ics-nr_irqs = nr_irqs;
ics-offset = XICS_IRQ_BASE;
ics-irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
+ics-islsi = g_malloc0(nr_irqs * sizeof(bool));
icp-ics = ics;
ics-icp = icp;
--
1.6.0.2
Re: [Qemu-devel] [PATCH 07/14] migration: make writes blocking
Paolo Bonzini pbonz...@redhat.com wrote: Il 21/09/2012 16:08, Juan Quintela ha scritto: -s-fd = inet_connect(host_port, false, in_progress, errp); +s-fd = inet_connect(host_port, true, in_progress, errp); This makes the connect operation blocking. Does this mean that Orit's patches for non-blocking connect are not useful anymore? Or should we instead leave this as is, and later call socket_set_block? fixed calling set-block. Easier that way. Later, Juan.
[Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops
The openpic code has its own bitmap code to access bits inside of a
bitmap. However, that is overkill when we simply want to check for a
bit inside of a uint32_t.
So instead, let's use normal bit masks and C builtin shifts and ands.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 67 +++--
1 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 91e87b7..d2038d8 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -132,13 +132,12 @@ enum {
#define VENI_GENERIC 0x /* Generic Vendor ID */
-enum mpic_ide_bits {
-IDR_EP = 31,
-IDR_CI0 = 30,
-IDR_CI1 = 29,
-IDR_P1 = 1,
-IDR_P0 = 0,
-};
+#define IDR_EP_SHIFT 31
+#define IDR_EP_MASK (1 IDR_EP_SHIFT)
+#define IDR_CI0_SHIFT 30
+#define IDR_CI1_SHIFT 29
+#define IDR_P1_SHIFT 1
+#define IDR_P0_SHIFT 0
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
@@ -181,13 +180,17 @@ typedef struct IRQ_src_t {
int pending;/* TRUE if IRQ is pending */
} IRQ_src_t;
-enum IPVP_bits {
-IPVP_MASK = 31,
-IPVP_ACTIVITY = 30,
-IPVP_MODE = 29,
-IPVP_POLARITY = 23,
-IPVP_SENSE= 22,
-};
+#define IPVP_MASK_SHIFT 31
+#define IPVP_MASK_MASK(1 IPVP_MASK_SHIFT)
+#define IPVP_ACTIVITY_SHIFT 30
+#define IPVP_ACTIVITY_MASK(1 IPVP_ACTIVITY_SHIFT)
+#define IPVP_MODE_SHIFT 29
+#define IPVP_MODE_MASK(1 IPVP_MODE_SHIFT)
+#define IPVP_POLARITY_SHIFT 23
+#define IPVP_POLARITY_MASK(1 IPVP_POLARITY_SHIFT)
+#define IPVP_SENSE_SHIFT 22
+#define IPVP_SENSE_MASK (1 IPVP_SENSE_SHIFT)
+
#define IPVP_PRIORITY_MASK (0x1F 16)
#define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) IPVP_PRIORITY_MASK) 16))
#define IPVP_VECTOR_MASK ((1 VECTOR_BITS) - 1)
@@ -310,7 +313,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int
n_IRQ)
__func__, n_IRQ, n_CPU);
return;
}
-set_bit(src-ipvp, IPVP_ACTIVITY);
+src-ipvp |= IPVP_ACTIVITY_MASK;
IRQ_setbit(dst-raised, n_IRQ);
if (priority dst-raised.priority) {
/* An higher priority IRQ is already raised */
@@ -343,7 +346,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
DPRINTF(%s: IRQ %d is not pending\n, __func__, n_IRQ);
return;
}
-if (test_bit(src-ipvp, IPVP_MASK)) {
+if (src-ipvp IPVP_MASK_MASK) {
/* Interrupt source is disabled */
DPRINTF(%s: IRQ %d is disabled\n, __func__, n_IRQ);
return;
@@ -353,7 +356,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
DPRINTF(%s: IRQ %d has 0 priority\n, __func__, n_IRQ);
return;
}
-if (test_bit(src-ipvp, IPVP_ACTIVITY)) {
+if (src-ipvp IPVP_ACTIVITY_MASK) {
/* IRQ already active */
DPRINTF(%s: IRQ %d is already active\n, __func__, n_IRQ);
return;
@@ -367,18 +370,19 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
if (src-ide == (1 src-last_cpu)) {
/* Only one CPU is allowed to receive this IRQ */
IRQ_local_pipe(opp, src-last_cpu, n_IRQ);
-} else if (!test_bit(src-ipvp, IPVP_MODE)) {
+} else if (!(src-ipvp IPVP_MODE_MASK)) {
/* Directed delivery mode */
for (i = 0; i opp-nb_cpus; i++) {
-if (test_bit(src-ide, i))
+if (src-ide (1 i)) {
IRQ_local_pipe(opp, i, n_IRQ);
+}
}
} else {
/* Distributed delivery mode */
for (i = src-last_cpu + 1; i != src-last_cpu; i++) {
if (i == opp-nb_cpus)
i = 0;
-if (test_bit(src-ide, i)) {
+if (src-ide (1 i)) {
IRQ_local_pipe(opp, i, n_IRQ);
src-last_cpu = i;
break;
@@ -395,11 +399,12 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int
level)
src = opp-src[n_IRQ];
DPRINTF(openpic: set irq %d = %d ipvp=%08x\n,
n_IRQ, level, src-ipvp);
-if (test_bit(src-ipvp, IPVP_SENSE)) {
+if (src-ipvp IPVP_SENSE_MASK) {
/* level-sensitive irq */
src-pending = level;
-if (!level)
-reset_bit(src-ipvp, IPVP_ACTIVITY);
+if (!level) {
+src-ipvp = ~IPVP_ACTIVITY_MASK;
+}
} else {
/* edge-sensitive irq */
if (level)
@@ -810,13 +815,13 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
hwaddr addr,
retval = IPVP_VECTOR(opp-spve);
} else {
src = opp-src[n_IRQ];
-if (!test_bit(src-ipvp, IPVP_ACTIVITY) ||
+if (!(src-ipvp IPVP_ACTIVITY_MASK) ||
!(IPVP_PRIORITY(src-ipvp) dst-pctp)) {
/* - Spurious level-sensitive IRQ
* - Priorities has been changed
* and the
Re: [Qemu-devel] [PATCH 09/14] migration: take finer locking
Paolo Bonzini pbonz...@redhat.com wrote:
Il 21/09/2012 16:08, Juan Quintela ha scritto:
Instead of locking the whole migration_thread inside loop, just lock
migration_fd_put_notify, that is what interacts with the rest of the
world.
Wrong commit message: just lock migrate_fd_put_ready.
Fixed.
@@ -305,8 +305,10 @@ void migrate_fd_put_ready(MigrationState *s)
int ret;
static bool first_time = true;
+qemu_mutex_lock_iothread();
if (s-state != MIG_STATE_ACTIVE) {
DPRINTF(put_ready returning because of non-active state\n);
+qemu_mutex_unlock_iothread();
Please use a goto instead.
return;
}
if (first_time) {
@@ -316,6 +318,7 @@ void migrate_fd_put_ready(MigrationState *s)
if (ret 0) {
DPRINTF(failed, %d\n, ret);
migrate_fd_error(s);
+qemu_mutex_unlock_iothread();
Same here.
Don't work. The last branch of the code drops the lock before the end.
Code is:
lock()
while() {
if (foo) {
...
unlock()
break;
}
if (bar) {
...
unlock()
break;
}
unlock()
... /* this is the interesting bit */
}
/* more stuff needed both sides */
adding a goto would not help making things clearer.
return;
}
}
@@ -351,6 +354,8 @@ void migrate_fd_put_ready(MigrationState *s)
}
}
}
+qemu_mutex_unlock_iothread();
+
}
static void migrate_fd_cancel(MigrationState *s)
Re: [Qemu-devel] [PATCH 1/2] target-i386: move CPU object creation to cpu.c
On Fri, Dec 14, 2012 at 11:26:55AM +0100, Igor Mammedov wrote:
On Wed, 12 Dec 2012 16:16:22 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
As we will need to create the CPU object after splitting the CPU model
string (because we're going to use different subclasses for each CPU
model), move the CPU object creation to cpu_x86_register(), and at the
same time rename cpu_x86_register() to cpu_x86_create().
This will also simplify the CPU creation code to a trivial
cpu_x86_create()+cpu_x86_realize() sequence. This will be useful for
code that have to set additional properties before cpu_x86_realize() is
called (e.g. the PC CPU initialization code, that needs to set APIC IDs
depending on the CPU cores/threads topology).
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu.c| 16 +---
target-i386/cpu.h| 2 +-
target-i386/helper.c | 9 ++---
3 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 3b9bbfe..b242bf1 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1539,13 +1539,22 @@ static void filter_features_for_kvm(X86CPU *cpu)
}
#endif
-int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
+/* Create and initialize a X86CPU object, based on the full CPU model
string
+ * (that may include +feature,-feature,feature=xxx feature strings)
feature format of cpu_model string misses just 'feature'
Thanks. I'll change it.
+ */
+X86CPU *cpu_x86_create(const char *cpu_model)
{
+X86CPU *cpu;
+CPUX86State *env;
x86_def_t def1, *def = def1;
Error *error = NULL;
char *name, *features;
gchar **model_pieces;
+cpu = X86_CPU(object_new(TYPE_X86_CPU));
Could we put this after cpu_x86_parse_featurestr(), it's really not needed
before it now and eventually we would like to move it there anyway.
I believe we want to call cpu_x86_parse_featurestr() _after_ the CPU
object is created, don't we? Because one day the feature string is going
be used to set properties in the CPU object.
But we can move object_new() after g_strsplit() (because evantually the
CPU object creation is going to use the first part of cpu_model to
lookup the class name).
+env = cpu-env;
+env-cpu_model_str = cpu_model;
+
memset(def, 0, sizeof(*def));
model_pieces = g_strsplit(cpu_model, ,, 2);
@@ -1578,10 +1587,11 @@ int cpu_x86_register(X86CPU *cpu, const char
*cpu_model)
}
g_strfreev(model_pieces);
-return 0;
+return cpu;
error:
+object_delete(OBJECT(cpu));
g_strfreev(model_pieces);
-return -1;
+return NULL;
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 386c4f6..3ebaae9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -980,7 +980,7 @@ int cpu_x86_signal_handler(int host_signum, void *pinfo,
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx);
-int cpu_x86_register(X86CPU *cpu, const char *cpu_model);
+X86CPU *cpu_x86_create(const char *cpu_model);
void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t
*edx);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index bf206cf..23af4a8 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1243,15 +1243,10 @@ int cpu_x86_get_descr_debug(CPUX86State *env,
unsigned int selector,
X86CPU *cpu_x86_init(const char *cpu_model)
{
X86CPU *cpu;
-CPUX86State *env;
Error *error = NULL;
-cpu = X86_CPU(object_new(TYPE_X86_CPU));
-env = cpu-env;
-env-cpu_model_str = cpu_model;
-
-if (cpu_x86_register(cpu, cpu_model) 0) {
-object_delete(OBJECT(cpu));
+cpu = cpu_x86_create(cpu_model);
+if (!cpu) {
return NULL;
}
--
1.7.11.7
--
Regards,
Igor
--
Eduardo
[Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness
The MSI-X vector tables are usually stored in little endian in memory,
so let's mark the accessors as such.
This fixes MSI-X on e500 for me.
Signed-off-by: Alexander Graf ag...@suse.de
Acked-by: Michael S. Tsirkin m...@redhat.com
---
hw/msix.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index 136ef09..b57ae60 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -180,8 +180,7 @@ static void msix_table_mmio_write(void *opaque, hwaddr addr,
static const MemoryRegionOps msix_table_mmio_ops = {
.read = msix_table_mmio_read,
.write = msix_table_mmio_write,
-/* TODO: MSIX should be LITTLE_ENDIAN. */
-.endianness = DEVICE_NATIVE_ENDIAN,
+.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@@ -198,8 +197,7 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr
addr,
static const MemoryRegionOps msix_pba_mmio_ops = {
.read = msix_pba_mmio_read,
-/* TODO: MSIX should be LITTLE_ENDIAN. */
-.endianness = DEVICE_NATIVE_ENDIAN,
+.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
--
1.6.0.2
[Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support
The OpenPIC allows MSI access through shared MSI registers. Implement
them for the MPC8544 MPIC, so we can support MSIs.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 150 ++
1 files changed, 130 insertions(+), 20 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 5bf16ea..4bea1e7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -38,6 +38,7 @@
#include pci.h
#include openpic.h
#include sysbus.h
+#include msi.h
//#define DEBUG_OPENPIC
@@ -52,6 +53,7 @@
#define MAX_TMR 4
#define VECTOR_BITS 8
#define MAX_IPI 4
+#define MAX_MSI 8
#define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
#define VID 0x03 /* MPIC version ID */
@@ -63,6 +65,8 @@
#define OPENPIC_GLB_REG_SIZE 0x10F0
#define OPENPIC_TMR_REG_START0x10F0
#define OPENPIC_TMR_REG_SIZE 0x220
+#define OPENPIC_MSI_REG_START0x1600
+#define OPENPIC_MSI_REG_SIZE 0x200
#define OPENPIC_SRC_REG_START0x1
#define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
#define OPENPIC_CPU_REG_START0x2
@@ -127,6 +131,12 @@
#define IDR_P1_SHIFT 1
#define IDR_P0_SHIFT 0
+#define MSIIR_OFFSET 0x140
+#define MSIIR_SRS_SHIFT29
+#define MSIIR_SRS_MASK (0x7 MSIIR_SRS_SHIFT)
+#define MSIIR_IBS_SHIFT24
+#define MSIIR_IBS_MASK (0x1f MSIIR_IBS_SHIFT)
+
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
@@ -209,7 +219,7 @@ typedef struct OpenPICState {
uint32_t brr1;
/* Sub-regions */
-MemoryRegion sub_io_mem[7];
+MemoryRegion sub_io_mem[5];
/* Global registers */
uint32_t frep; /* Feature reporting register */
@@ -227,9 +237,14 @@ typedef struct OpenPICState {
uint32_t ticc; /* Global timer current count register */
uint32_t tibc; /* Global timer base count register */
} timers[MAX_TMR];
+/* Shared MSI registers */
+struct {
+uint32_t msir; /* Shared Message Signaled Interrupt Register */
+} msi[MAX_MSI];
uint32_t max_irq;
uint32_t irq_ipi0;
uint32_t irq_tim0;
+uint32_t irq_msi;
} OpenPICState;
static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
@@ -704,6 +719,68 @@ static uint64_t openpic_src_read(void *opaque, uint64_t
addr, unsigned len)
return retval;
}
+static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+OpenPICState *opp = opaque;
+int idx = opp-irq_msi;
+int srs, ibs;
+
+DPRINTF(%s: addr TARGET_FMT_plx = %08x\n, __func__, addr, val);
+if (addr 0xF) {
+return;
+}
+
+switch (addr) {
+case MSIIR_OFFSET:
+srs = val MSIIR_SRS_SHIFT;
+idx += srs;
+ibs = (val MSIIR_IBS_MASK) MSIIR_IBS_SHIFT;
+opp-msi[srs].msir |= 1 ibs;
+openpic_set_irq(opp, idx, 1);
+break;
+default:
+/* most registers are read-only, thus ignored */
+break;
+}
+}
+
+static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
+{
+OpenPICState *opp = opaque;
+uint64_t r = 0;
+int i, srs;
+
+DPRINTF(%s: addr TARGET_FMT_plx \n, __func__, addr);
+if (addr 0xF) {
+return -1;
+}
+
+srs = addr 4;
+
+switch (addr) {
+case 0x00:
+case 0x10:
+case 0x20:
+case 0x30:
+case 0x40:
+case 0x50:
+case 0x60:
+case 0x70: /* MSIRs */
+r = opp-msi[srs].msir;
+/* Clear on read */
+opp-msi[srs].msir = 0;
+break;
+case 0x120: /* MSISR */
+for (i = 0; i MAX_MSI; i++) {
+r |= (opp-msi[i].msir ? 1 : 0) i;
+}
+break;
+}
+
+return r;
+}
+
static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx)
{
@@ -932,6 +1009,26 @@ static const MemoryRegionOps openpic_src_ops_be = {
},
};
+static const MemoryRegionOps openpic_msi_ops_le = {
+.read = openpic_msi_read,
+.write = openpic_msi_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static const MemoryRegionOps openpic_msi_ops_be = {
+.read = openpic_msi_read,
+.write = openpic_msi_write,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
{
unsigned int i;
@@ -1039,6 +1136,7 @@ static void openpic_irq_raise(OpenPICState *opp, int
n_CPU, IRQ_src_t *src)
struct memreg {
const char *name;
MemoryRegionOps const *ops;
+bool map;
hwaddr start_addr;
ram_addr_t size;
};
@@ -1047,27 +1145,31 @@ static int openpic_init(SysBusDevice *dev)
{
OpenPICState
[Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params
We have a params struct that allows us to expose differences between
e500 machine models. Include PCI slot information there, so we can have
different machines with different PCI slot topology.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500.c |4 +++-
hw/ppc/e500.h |2 ++
hw/ppc/e500plat.c |2 ++
hw/ppc/mpc8544ds.c |2 ++
4 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index ebb6d96..564f654 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -339,7 +339,8 @@ static int ppce500_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_cells(fdt, pci, interrupt-map-mask, 0xf800, 0x0,
0x0, 0x7);
pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
- 0x11, 2, len);
+ params-pci_first_slot, params-pci_nr_slots,
+ len);
qemu_devtree_setprop(fdt, pci, interrupt-map, pci_map, len);
qemu_devtree_setprop_phandle(fdt, pci, interrupt-parent, mpic);
qemu_devtree_setprop_cells(fdt, pci, interrupts, 24, 2);
@@ -569,6 +570,7 @@ void ppce500_init(PPCE500Params *params)
/* PCI */
dev = qdev_create(NULL, e500-pcihost);
+qdev_prop_set_uint32(dev, first_slot, params-pci_first_slot);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 7ae87f4..f5ff273 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -9,6 +9,8 @@ typedef struct PPCE500Params {
const char *kernel_cmdline;
const char *initrd_filename;
const char *cpu_model;
+int pci_first_slot;
+int pci_nr_slots;
/* e500-specific params */
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 4cfb940..9365213 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -40,6 +40,8 @@ static void e500plat_init(QEMUMachineInitArgs *args)
.kernel_cmdline = kernel_cmdline,
.initrd_filename = initrd_filename,
.cpu_model = cpu_model,
+.pci_first_slot = 0x11,
+.pci_nr_slots = 2,
.fixup_devtree = e500plat_fixup_devtree,
};
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index e651661..7e1761d 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -40,6 +40,8 @@ static void mpc8544ds_init(QEMUMachineInitArgs *args)
.kernel_cmdline = kernel_cmdline,
.initrd_filename = initrd_filename,
.cpu_model = cpu_model,
+.pci_first_slot = 0x11,
+.pci_nr_slots = 2,
.fixup_devtree = mpc8544ds_fixup_devtree,
};
--
1.6.0.2
[Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs
From: David Gibson da...@gibson.dropbear.id.au
The PAPR specification requires that every bus or device mediated by the
IOMMU have a unique Logical IO Bus Number (LIOBN). This patch adds a check
to enforce this, which will help catch errors in configuration earlier.
Signed-off-by: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/spapr_iommu.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/spapr_iommu.c b/hw/spapr_iommu.c
index 02d78cc..3011b25 100644
--- a/hw/spapr_iommu.c
+++ b/hw/spapr_iommu.c
@@ -120,6 +120,12 @@ DMAContext *spapr_tce_new_dma_context(uint32_t liobn,
size_t window_size)
{
sPAPRTCETable *tcet;
+if (spapr_tce_find_by_liobn(liobn)) {
+fprintf(stderr, Attempted to create TCE table with duplicate
+ LIOBN 0x%x\n, liobn);
+return NULL;
+}
+
if (!window_size) {
return NULL;
}
--
1.6.0.2
Re: [Qemu-devel] [BUG] qemu-1.1.2 [FIXED-BY] qcow2: Fix avail_sectors in cluster allocation code
Hello Kevin, On Wednesday 12 December 2012 18:29:48 Philipp Hahn wrote: I just re-run my git bisect run ~/bisect.sh case, but it again arrived at that patch. I just queued another run for tonight so make sure the test is reliable: The run from last night again arrived at the refecenced patch. Ideally we would find a sequence of qemu-io commands to reliably reproduce this. First thing worth trying would be running the current qemu-iotests suite on the old versions. If we don't find it this way, I guess we need to catch it with code review. I'm not sure if I can get to it this week, and starting next week I'll be on vacation, so any help with finding a reproducer would be appreciated. I took a closer look at what gets corrupted; I've attached my notes. Please notice that the partitions are not alignd properly. If you would like to look at the full qcow2_alloc_clusters_offset trace, I can provide you with a link to the trace file. BYtE Philipp -- Philipp Hahn Open Source Software Engineer h...@univention.de Univention GmbHbe open. fon: +49 421 22 232- 0 Mary-Somerville-Str.1 D-28359 Bremen fax: +49 421 22 232-99 http://www.univention.de/ # FILE=/var/cache/apt/archives/liblqr-1-0_0.4.1-1.3.201104131631_amd64.deb # debugfs /dev/vg_ucs/rootfs -R stat $FILE debugfs 1.41.12 (17-May-2010) Inode: 1385717 Type: regularMode: 0644 Flags: 0x0 Generation: 2854262870Version: 0x User: 0 Group: 0 Size: 38884 File ACL: 0Directory ACL: 0 Links: 1 Blockcount: 80 Fragment: Address: 0Number: 0Size: 0 ctime: 0x50979ae9 -- Mon Nov 5 11:54:33 2012 atime: 0x50979b0d -- Mon Nov 5 11:55:09 2012 mtime: 0x4de1dbce -- Sun May 29 07:38:22 2011 Size of extra inode fields: 4 BLOCKS: (0-9):5728401-5728410 TOTAL: 10 # BSIZE=4096 # BOFFSET=0 # dd bs=$BSIZE count=1 if=$FILE skip=$BOFFSET 2/dev/null | md5sum 065b19ba6e9153dcc88003ea06076f9f - # BLOCK=5728401 # dd bs=$BSIZE count=1 if=/dev/vg_ucs/rootfs skip=$BLOCK 2/dev/null | md5sum 065b19ba6e9153dcc88003ea06076f9f - # dmsetup table vg_ucs-rootfs: 0 97910784 linear 254:3 384 # LV_SOFFSET=384 # dd bs=512c count=8 if=/dev/vda3 skip=$((BLOCK*8+LV_SOFFSET)) 2/dev/null | md5sum 065b19ba6e9153dcc88003ea06076f9f - # fdisk -l -u /dev/vda /dev/vda3 4739175 10485625450058540 8e Linux LVM # PART_SOFFSET=4739175 # dd bs=512c count=8 if=/dev/vda skip=$((BLOCK*8+LV_SOFFSET+PART_SOFFSET)) 2/dev/null | md5sum 065b19ba6e9153dcc88003ea06076f9f - # debugfs /dev/vg_ucs/rootfs -R icheck $(seq 5728387 5728403 | tr '\n' ' ') debugfs 1.41.12 (17-May-2010) Block Inode number 5728387 1385715 5728388 1385715 5728389 1385715 5728390 1385715 5728391 1385715 5728392 1385715 5728393 1385715 5728394 1385715 5728395 1385715 5728396 1385715 5728397 1385716 5728398 1385716 5728399 1385716 5728400 1385716 5728401 1385717 5728402 1385717 5728403 1385717 # debugfs /dev/vg_ucs/rootfs -R ncheck 1385715 1385716 1385717 debugfs 1.41.12 (17-May-2010) Inode Pathname 1385715 /var/cache/apt/archives/libhtml-template-perl_2.9-2.7.201104290220_all.deb 1385717 /var/cache/apt/archives/liblqr-1-0_0.4.1-1.3.201104131631_amd64.deb 1385716 /var/cache/apt/archives/libio-socket-inet6-perl_2.65-1.1.3.201104291113_all.deb # md5sum /var/cache/apt/archives/libhtml-template-perl_2.9-2.7.201104290220_all.deb /var/cache/apt/archives/liblqr-1-0_0.4.1-1.3.201104131631_amd64.deb /var/cache/apt/archives/libio-socket-inet6-perl_2.65-1.1.3.201104291113_all.deb 123f4c338bd875825d5d762e8bb48b2a /var/cache/apt/archives/libhtml-template-perl_2.9-2.7.201104290220_all.deb eadbf53d7313df2560f4741fbe982008 /var/cache/apt/archives/liblqr-1-0_0.4.1-1.3.201104131631_amd64.deb d0c7bf2d62c125409e00e459ac94277a /var/cache/apt/archives/libio-socket-inet6-perl_2.65-1.1.3.201104291113_all.deb # apt-cache show libhtml-template-perl liblqr-1-0 libio-socket-inet6-perl | egrep 'MD5sum|Package' Package: libhtml-template-perl MD5sum: 123f4c338bd875825d5d762e8bb48b2a Package: liblqr-1-0 MD5sum: 94ccb97b38bedef97072fdcc7bce1872 Package: libio-socket-inet6-perl MD5sum: 8f04f2da2a7d2eefb9e77bf87a0b8972 # IMAGE=/var/lib/libvirt/images/stefan_UCS-3.0-2-13.3-Kolab-Slave.qcow2 # BLOCK=5728401 BSIZE=4096 BOFFSET=0 LV_SOFFSET=384 PART_SOFFSET=4739175 # OFFSET=$((BLOCK*BSIZE + LV_SOFFSET*512 + PART_SOFFSET*512)) # echo $((OFFSET 16 13)) $(((OFFSET 16) ((1 13) - 1))) $(((OFFSET 0) ((1 16) - 1))) 48 1836 56832 # qemu-io -c read -v $OFFSET $BSIZE $IMAGE | sed -ne 's/^\([0-9a-f]\+:\) /\1/p' | xxd -r -seek -$OFFSET | md5sum 065b19ba6e9153dcc88003ea06076f9f - # qcow2.py -r -s $IMAGE --read $OFFSET $BSIZE | xxd -r | md5sum l1=0x30 l2=0x72c c=0xde00 065b19ba6e9153dcc88003ea06076f9f - # qcow2.py -r -s $IMAGE | egrep L1\[$((0x30))\]|L2\[$((0x72c))\]|cluster_bits| size|l1_size : + cluster_bits=16 (64 KiB)
Re: [Qemu-devel] [PATCH 3/3] chardev: add hotplug support.
On 12/14/2012 05:17 AM, Paolo Bonzini wrote:
Il 14/12/2012 10:38, Gerd Hoffmann ha scritto:
This patch adds chardev_add_file, chardev_add_tty and chardev_remove
monitor commands.
chardev_add_file and chardev_add_tty expect an id and a path, they
create a file/tty chardev.
I'd rather avoid introducing this interface. Using multiple commands is
different from all previous examples, both HMP and QMP (including recent
ones such as the NBD server). It is also hard to extend, for example
file descriptor passing is hard to retrofit.
File descriptor passing via magic /dev/fdset/nnn should probably already
work. That said, a single command that uses a QAPI union, rather than
one command per source type, would be nicer from the UI perspective, and
it is the QMP UI perspective that libvirt is concerned about.
Perhaps you can define a QAPI union and slowly build it up? Something
that ultimately can become this:
{ 'enum': 'ChardevFileMode', 'data':
# pty = console under Windows
# serial = tty under POSIX
[ 'file', 'pipe', 'parport', 'pty', 'serial' ] }
{ 'enum: 'ChardevFileSource', 'data':
[ 'path', 'fd' ] }
{ 'type': 'ChardevFile',
'data': {'source': 'string', 'source-type': 'ChardevFileSource',
'mode': 'ChardevFileMode'}}
{ 'type': 'ChardevVC',
'data': {'width': 'int', 'height': 'int', '*characters': 'bool'}}
{ 'type': 'ChardevSocket',
'data': {'addr': 'SocketAddress', '*server': 'bool',
'*wait': 'bool', '*nodelay': 'bool', '*telnet': 'bool'} }
# For future extensibility...
{ 'ChardevDummy', 'data': {} }
{ 'union': 'ChardevBackend', 'data': {
'socket': 'ChardevSocket',
'udp': 'UDPSocketAddress',
'file': 'ChardevFile',
'null': 'ChardevDummy',
'msmouse': 'ChardevDummy',
'braille': 'ChardevDummy',
'stdio': 'ChardevDummy',
'vc': 'ChardevVC',
# Solely for HMP usage.
'legacy': 'str'
}
{ 'command': 'chardev-add', 'data': {
'backend': 'ChardevBackend', 'id': 'str', '*mux': 'bool' } }
Yes, this looks nicer.
--
Eric Blake eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org
signature.asc
Description: OpenPGP digital signature
[Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically
Today we're hardcoding the PCI interrupt map in the e500 machine file.
Instead, let's write it dynamically so that different machine types
can have different slot properties.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500.c | 51 +++
1 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 1034f93..ebb6d96 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -66,25 +66,33 @@ struct boot_info
uint32_t entry;
};
-static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
+static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
+int nr_slots, int *len)
{
-int i;
-const uint32_t tmp[] = {
- /* IDSEL 0x11 J17 Slot 1 */
- 0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1,
- 0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1,
- 0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1,
- 0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
-
- /* IDSEL 0x12 J16 Slot 2 */
- 0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1,
- 0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1,
- 0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1,
- 0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
- };
-for (i = 0; i (7 * 8); i++) {
-pci_map[i] = cpu_to_be32(tmp[i]);
+int i = 0;
+int slot;
+int pci_irq;
+int last_slot = first_slot + nr_slots;
+uint32_t *pci_map;
+
+*len = nr_slots * 4 * 7 * sizeof(uint32_t);
+pci_map = g_malloc(*len);
+
+for (slot = first_slot; slot last_slot; slot++) {
+for (pci_irq = 0; pci_irq 4; pci_irq++) {
+pci_map[i++] = cpu_to_be32(slot 11);
+pci_map[i++] = cpu_to_be32(0x0);
+pci_map[i++] = cpu_to_be32(0x0);
+pci_map[i++] = cpu_to_be32(pci_irq + 1);
+pci_map[i++] = cpu_to_be32(mpic);
+pci_map[i++] = cpu_to_be32(((pci_irq + slot) % 4) + 1);
+pci_map[i++] = cpu_to_be32(0x1);
+}
}
+
+assert((i * sizeof(uint32_t)) == *len);
+
+return pci_map;
}
static void dt_serial_create(void *fdt, unsigned long long offset,
@@ -132,7 +140,8 @@ static int ppce500_load_device_tree(CPUPPCState *env,
char gutil[128];
char pci[128];
char msi[128];
-uint32_t pci_map[7 * 8];
+uint32_t *pci_map = NULL;
+int len;
uint32_t pci_ranges[14] =
{
0x200, 0x0, 0xc000,
@@ -329,8 +338,9 @@ static int ppce500_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_string(fdt, pci, device_type, pci);
qemu_devtree_setprop_cells(fdt, pci, interrupt-map-mask, 0xf800, 0x0,
0x0, 0x7);
-pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
-qemu_devtree_setprop(fdt, pci, interrupt-map, pci_map, sizeof(pci_map));
+pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
+ 0x11, 2, len);
+qemu_devtree_setprop(fdt, pci, interrupt-map, pci_map, len);
qemu_devtree_setprop_phandle(fdt, pci, interrupt-parent, mpic);
qemu_devtree_setprop_cells(fdt, pci, interrupts, 24, 2);
qemu_devtree_setprop_cells(fdt, pci, bus-range, 0, 255);
@@ -364,6 +374,7 @@ done:
ret = fdt_size;
out:
+g_free(pci_map);
return ret;
}
--
1.6.0.2
[Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues
This patch removes all remaining occurences of spaces before function
parameter indicating parenthesis.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 4bea1e7..25d5cd7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -140,17 +140,17 @@
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
-static inline void set_bit (uint32_t *field, int bit)
+static inline void set_bit(uint32_t *field, int bit)
{
field[bit 5] |= 1 (bit 0x1F);
}
-static inline void reset_bit (uint32_t *field, int bit)
+static inline void reset_bit(uint32_t *field, int bit)
{
field[bit 5] = ~(1 (bit 0x1F));
}
-static inline int test_bit (uint32_t *field, int bit)
+static inline int test_bit(uint32_t *field, int bit)
{
return (field[bit 5] 1 (bit 0x1F)) != 0;
}
@@ -249,17 +249,17 @@ typedef struct OpenPICState {
static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
-static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
+static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
{
set_bit(q-queue, n_IRQ);
}
-static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
+static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
{
reset_bit(q-queue, n_IRQ);
}
-static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
+static inline int IRQ_testbit(IRQ_queue_t *q, int n_IRQ)
{
return test_bit(q-queue, n_IRQ);
}
--
1.6.0.2
[Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState
Rename the openpic_t struct to OpenPICState, so it adheres better to
the current coding style rules.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 68 +-
1 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index d2038d8..d5c2705 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -204,7 +204,7 @@ typedef struct IRQ_dst_t {
qemu_irq *irqs;
} IRQ_dst_t;
-typedef struct openpic_t {
+typedef struct OpenPICState {
PCIDevice pci_dev;
MemoryRegion mem;
@@ -242,9 +242,9 @@ typedef struct openpic_t {
int max_irq;
int irq_ipi0;
int irq_tim0;
-} openpic_t;
+} OpenPICState;
-static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
+static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
@@ -261,7 +261,7 @@ static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
return test_bit(q-queue, n_IRQ);
}
-static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
+static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
{
int next, i;
int priority;
@@ -282,7 +282,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
q-priority = priority;
}
-static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
+static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
{
if (q-next == -1) {
/* XXX: optimize */
@@ -292,7 +292,7 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
return q-next;
}
-static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
+static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
{
IRQ_dst_t *dst;
IRQ_src_t *src;
@@ -334,7 +334,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int
n_IRQ)
}
/* update pic state because registers for n_IRQ have changed value */
-static void openpic_update_irq(openpic_t *opp, int n_IRQ)
+static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
{
IRQ_src_t *src;
int i;
@@ -393,7 +393,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
static void openpic_set_irq(void *opaque, int n_IRQ, int level)
{
-openpic_t *opp = opaque;
+OpenPICState *opp = opaque;
IRQ_src_t *src;
src = opp-src[n_IRQ];
@@ -415,7 +415,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int
level)
static void openpic_reset (void *opaque)
{
-openpic_t *opp = (openpic_t *)opaque;
+OpenPICState *opp = (OpenPICState *)opaque;
int i;
opp-glbc = 0x8000;
@@ -450,17 +450,17 @@ static void openpic_reset (void *opaque)
opp-glbc = 0x;
}
-static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
+static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ)
{
return opp-src[n_IRQ].ide;
}
-static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
+static inline uint32_t read_IRQreg_ipvp(OpenPICState *opp, int n_IRQ)
{
return opp-src[n_IRQ].ipvp;
}
-static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
+static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val)
{
uint32_t tmp;
@@ -470,7 +470,7 @@ static inline void write_IRQreg_ide(openpic_t *opp, int
n_IRQ, uint32_t val)
DPRINTF(Set IDE %d to 0x%08x\n, n_IRQ, opp-src[n_IRQ].ide);
}
-static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
+static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t
val)
{
/* NOTE: not fully accurate for special IRQs, but simple and sufficient */
/* ACTIVITY bit is read-only */
@@ -484,7 +484,7 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int
n_IRQ, uint32_t val)
static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
-openpic_t *opp = opaque;
+OpenPICState *opp = opaque;
IRQ_dst_t *dst;
int idx;
@@ -547,7 +547,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr,
uint64_t val,
static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
{
-openpic_t *opp = opaque;
+OpenPICState *opp = opaque;
uint32_t retval;
DPRINTF(%s: addr TARGET_FMT_plx \n, __func__, addr);
@@ -599,10 +599,10 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr
addr, unsigned len)
return retval;
}
-static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
-openpic_t *opp = opaque;
+OpenPICState *opp = opaque;
int idx;
DPRINTF(%s: addr %08x = %08x\n, __func__, addr, val);
@@ -635,9 +635,9 @@ static void openpic_timer_write(void *opaque, hwaddr addr,
uint64_t val,
}
}
-static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
+static
[Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers
The MPIC source irq handler suddenly became identical to the standard
OpenPIC source irq handler. Combine them into the same function.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 52 +---
1 files changed, 5 insertions(+), 47 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 1d714f4..b671d9d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -100,8 +100,8 @@ enum {
#define MPIC_GLB_REG_SIZE 0x10F0
#define MPIC_TMR_REG_START0x10F0
#define MPIC_TMR_REG_SIZE 0x220
-#define MPIC_IRQ_REG_START0x1
-#define MPIC_IRQ_REG_SIZE (MAX_SRC * 0x20)
+#define MPIC_SRC_REG_START0x1
+#define MPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
#define MPIC_CPU_REG_START0x2
#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
@@ -1169,48 +1169,6 @@ static uint64_t mpic_timer_read(void *opaque, hwaddr
addr, unsigned len)
return retval;
}
-static void mpic_src_irq_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned len)
-{
-openpic_t *mpp = opaque;
-int idx = addr / 0x20;
-
-DPRINTF(%s: addr TARGET_FMT_plx = %08 PRIx64 \n,
-__func__, addr, val);
-if (addr 0xF)
-return;
-
-if (addr 0x10) {
-/* EXDE / IFEDE / IEEDE */
-write_IRQreg_ide(mpp, idx, val);
-} else {
-/* EXVP / IFEVP / IEEVP */
-write_IRQreg_ipvp(mpp, idx, val);
-}
-}
-
-static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
-{
-openpic_t *mpp = opaque;
-uint32_t retval;
-int idx = addr / 0x20;
-
-DPRINTF(%s: addr TARGET_FMT_plx \n, __func__, addr);
-if (addr 0xF)
-return -1;
-
-if (addr 0x10) {
-/* EXDE / IFEDE / IEEDE */
-retval = read_IRQreg_ide(mpp, idx);
-} else {
-/* EXVP / IFEVP / IEEVP */
-retval = read_IRQreg_ipvp(mpp, idx);
-}
-DPRINTF(%s: = %08x\n, __func__, retval);
-
-return retval;
-}
-
static const MemoryRegionOps mpic_glb_ops = {
.write = openpic_gbl_write,
.read = openpic_gbl_read,
@@ -1242,8 +1200,8 @@ static const MemoryRegionOps mpic_cpu_ops = {
};
static const MemoryRegionOps mpic_irq_ops = {
-.write = mpic_src_irq_write,
-.read = mpic_src_irq_read,
+.write = openpic_src_write,
+.read = openpic_src_read,
.endianness = DEVICE_BIG_ENDIAN,
.impl = {
.min_access_size = 4,
@@ -1264,7 +1222,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr
base,
} const list[] = {
{glb, mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
{tmr, mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
-{irq, mpic_irq_ops, MPIC_IRQ_REG_START, MPIC_IRQ_REG_SIZE},
+{src, mpic_irq_ops, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
{cpu, mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
};
--
1.6.0.2
[Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation
We need the calculation method to get from a PCI slot ID to its respective
interrupt line twice. Once in the internal map function and once when
assembling the device tree.
So let's extract the calculation to a separate function that can be called
by both users.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500.c|5 -
hw/ppce500_pci.c |3 ++-
hw/ppce500_pci.h |9 +
3 files changed, 15 insertions(+), 2 deletions(-)
create mode 100644 hw/ppce500_pci.h
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 564f654..af6b671 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -34,6 +34,7 @@
#include hw/sysbus.h
#include exec-memory.h
#include host-utils.h
+#include hw/ppce500_pci.h
#define BINARY_DEVICE_TREE_FILEmpc8544ds.dtb
#define UIMAGE_LOAD_BASE 0
@@ -72,6 +73,7 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int
first_slot,
int i = 0;
int slot;
int pci_irq;
+int host_irq;
int last_slot = first_slot + nr_slots;
uint32_t *pci_map;
@@ -85,7 +87,8 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int
first_slot,
pci_map[i++] = cpu_to_be32(0x0);
pci_map[i++] = cpu_to_be32(pci_irq + 1);
pci_map[i++] = cpu_to_be32(mpic);
-pci_map[i++] = cpu_to_be32(((pci_irq + slot) % 4) + 1);
+host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
+pci_map[i++] = cpu_to_be32(host_irq + 1);
pci_map[i++] = cpu_to_be32(0x1);
}
}
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 561a776..09e3507 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -19,6 +19,7 @@
#include pci.h
#include pci_host.h
#include bswap.h
+#include ppce500_pci.h
#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
@@ -256,7 +257,7 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int
irq_num)
int devno = pci_dev-devfn 3;
int ret;
-ret = (irq_num + devno) % 4;
+ret = ppce500_pci_map_irq_slot(devno, irq_num);
pci_debug(%s: devfn %x irq %d - %d devno:%x\n, __func__,
pci_dev-devfn, irq_num, ret, devno);
diff --git a/hw/ppce500_pci.h b/hw/ppce500_pci.h
new file mode 100644
index 000..61f773e
--- /dev/null
+++ b/hw/ppce500_pci.h
@@ -0,0 +1,9 @@
+#ifndef PPCE500_PCI_H
+#define PPCE500_PCI_H
+
+static inline int ppce500_pci_map_irq_slot(int devno, int irq_num)
+{
+return (devno + irq_num) % 4;
+}
+
+#endif
--
1.6.0.2
Re: [Qemu-devel] [PATCH 3/3] chardev: add hotplug support.
Hi,
{ 'enum': 'ChardevFileMode', 'data':
# pty = console under Windows
# serial = tty under POSIX
[ 'file', 'pipe', 'parport', 'pty', 'serial' ] }
Hmm, why this enum? I'd stay close to -chardev, i.e. specify the type
by backend name.
{ 'enum: 'ChardevFileSource', 'data':
[ 'path', 'fd' ] }
I guess I'd just create a new backend type for file descriptor passing
instead of fitting that into all the existing ones.
{ 'union': 'ChardevBackend', 'data': {
This union thing is new, isn't it?
Makes sense to use that indeed.
'socket': 'ChardevSocket',
'udp': 'UDPSocketAddress',
'file': 'ChardevFile',
'null': 'ChardevDummy',
'msmouse': 'ChardevDummy',
'braille': 'ChardevDummy',
'stdio': 'ChardevDummy',
'vc': 'ChardevVC',
I doubt we need them all hotpluggable.
cheers,
Gerd
From 6ea61630245d8ff9f87ed56b825dcc5f8d1f6e6d Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann kra...@redhat.com
Date: Thu, 11 Oct 2012 14:53:00 +0200
Subject: [PATCH] chardev: add hotplug support.
This patch adds chardev_add and chardev_remove monitor commands.
chardev_add expects a backend struct filled in and creates the chardev
from that. For now only file and tty backends are supported.
chardev_del just takes an id argument and zaps the chardev specified.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hmp-commands.hx | 30 ++
hmp.c| 19 +++
hmp.h|2 ++
qapi-schema.json | 31 +++
qemu-char.c | 46 ++
qemu-char.h |2 ++
qmp-commands.hx | 50 ++
7 files changed, 180 insertions(+), 0 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 010b8c9..9a0b2eb 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1485,6 +1485,36 @@ passed since 1970, i.e. unix epoch.
ETEXI
{
+.name = chardev_add,
+.args_type = id:s,backend:s,arg1:s,
+.params = id backend arg,
+.help = add chardev,
+.mhandler.cmd = hmp_chardev_add,
+},
+
+STEXI
+@item chardev_add id backend arg
+@findex chardev_add
+
+ETEXI
+
+{
+.name = chardev_remove,
+.args_type = id:s,
+.params = id,
+.help = remove chardev,
+.mhandler.cmd = hmp_chardev_remove,
+},
+
+STEXI
+@item chardev_remove id
+@findex chardev_remove
+
+Removes the chardev @var{id}.
+
+ETEXI
+
+{
.name = info,
.args_type = item:s?,
.params = [subcommand],
diff --git a/hmp.c b/hmp.c
index 180ba2b..c65f4f7 100644
--- a/hmp.c
+++ b/hmp.c
@@ -1335,3 +1335,22 @@ void hmp_nbd_server_stop(Monitor *mon, const QDict
*qdict)
qmp_nbd_server_stop(errp);
hmp_handle_error(mon, errp);
}
+
+void hmp_chardev_add(Monitor *mon, const QDict *qdict)
+{
+const char *id = qdict_get_str(qdict, id);
+const char *backend = qdict_get_str(qdict, backend);
+const char *path= qdict_get_str(qdict, arg1);
+Error *local_err = NULL;
+
+qmp_chardev_add_path(id, path, backend, local_err);
+hmp_handle_error(mon, local_err);
+}
+
+void hmp_chardev_remove(Monitor *mon, const QDict *qdict)
+{
+Error *local_err = NULL;
+
+qmp_chardev_remove(qdict_get_str(qdict, id), local_err);
+hmp_handle_error(mon, local_err);
+}
diff --git a/hmp.h b/hmp.h
index 0ab03be..e67e482 100644
--- a/hmp.h
+++ b/hmp.h
@@ -80,5 +80,7 @@ void hmp_screen_dump(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_start(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_add(Monitor *mon, const QDict *qdict);
void hmp_nbd_server_stop(Monitor *mon, const QDict *qdict);
+void hmp_chardev_add(Monitor *mon, const QDict *qdict);
+void hmp_chardev_remove(Monitor *mon, const QDict *qdict);
#endif
diff --git a/qapi-schema.json b/qapi-schema.json
index 5dfa052..7349757 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -3017,3 +3017,34 @@
# Since: 1.3.0
##
{ 'command': 'nbd-server-stop' }
+
+##
+# @chardev-add:
+#
+# Add a file chardev
+#
+# @id: the chardev's ID, must be unique
+# @backend: backend type and parameters
+#
+# Returns: Nothing on success
+#
+# Since: 1.3.0
+##
+{ 'type': 'ChardevFile', 'data': { 'path': 'str' } }
+{ 'union': 'ChardevBackend', 'data': { 'file': 'ChardevFile',
+ 'tty': 'ChardevFile' } }
+{ 'command': 'chardev-add', 'data': {'id' : 'str',
+ 'backend' : 'ChardevBackend' } }
+
+##
+# @chardev-remove:
+#
+# Remove a chardev
+#
+# @id: the chardev's ID, must exist and not be in use
+#
+# Returns: Nothing on success
+#
+# Since: 1.3.0
+##
+{ 'command': 'chardev-remove', 'data': {'id': 'str'} }
diff --git a/qemu-char.c b/qemu-char.c
index 876714f..bf7fdb6 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2922,3 +2922,49 @@ CharDriverState *qemu_char_get_next_serial(void)
[Qemu-devel] [PATCH 24/40] openpic: remove irq_out
The current openpic emulation contains half-ready code for bypass mode.
Remove it, so that when someone wants to finish it they can start from a
clean state.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c |8 ++--
hw/openpic.h |4 ++--
hw/ppc/e500.c |2 +-
hw/ppc_newworld.c |2 +-
4 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index d5c2705..5116b3e 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -237,8 +237,6 @@ typedef struct OpenPICState {
uint32_t ticc; /* Global timer current count register */
uint32_t tibc; /* Global timer base count register */
} timers[MAX_TMR];
-/* IRQ out is used when in bypass mode (not implemented) */
-qemu_irq irq_out;
int max_irq;
int irq_ipi0;
int irq_tim0;
@@ -1051,7 +1049,7 @@ static void openpic_irq_raise(OpenPICState *opp, int
n_CPU, IRQ_src_t *src)
}
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-qemu_irq **irqs, qemu_irq irq_out)
+qemu_irq **irqs)
{
OpenPICState *opp;
int i;
@@ -1100,7 +1098,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
for (i = 0; i nb_cpus; i++)
opp-dst[i].irqs = irqs[i];
-opp-irq_out = irq_out;
register_savevm(opp-pci_dev.qdev, openpic, 0, 2,
openpic_save, openpic_load, opp);
@@ -1113,7 +1110,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
}
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
- int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
+ int nb_cpus, qemu_irq **irqs)
{
OpenPICState*mpp;
int i;
@@ -1159,7 +1156,6 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr
base,
for (i = 0; i nb_cpus; i++)
mpp-dst[i].irqs = irqs[i];
-mpp-irq_out = irq_out;
/* Enable critical interrupt support */
mpp-flags |= OPENPIC_FLAG_IDE_CRIT;
diff --git a/hw/openpic.h b/hw/openpic.h
index 1232d10..8a68f20 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -15,7 +15,7 @@ enum {
#define OPENPIC_FLAG_IDE_CRIT(1 0)
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-qemu_irq **irqs, qemu_irq irq_out);
+qemu_irq **irqs);
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
- int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
+ int nb_cpus, qemu_irq **irqs);
#endif /* __OPENPIC_H__ */
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index f3e97d8..3f6d58c 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -493,7 +493,7 @@ void ppce500_init(PPCE500Params *params)
/* MPIC */
mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
- smp_cpus, irqs, NULL);
+ smp_cpus, irqs);
if (!mpic) {
cpu_abort(env, MPIC failed to initialize\n);
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 664747e..b9c2cd8 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -320,7 +320,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
exit(1);
}
}
-pic = openpic_init(pic_mem, smp_cpus, openpic_irqs, NULL);
+pic = openpic_init(pic_mem, smp_cpus, openpic_irqs);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
--
1.6.0.2
[Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical,
just that the MPIC one can also raise critical interrupts.
Combine those two and check for critical raise capability during runtime.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 34 --
hw/openpic.h |3 +++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 2a3b56a..d709e36 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -207,6 +207,9 @@ typedef struct openpic_t {
PCIDevice pci_dev;
MemoryRegion mem;
+/* Behavior control */
+uint32_t flags;
+
/* Sub-regions */
MemoryRegion sub_io_mem[7];
@@ -234,9 +237,10 @@ typedef struct openpic_t {
int irq_ipi0;
int irq_tim0;
void (*reset) (void *);
-void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
+static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
+
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q-queue, n_IRQ);
@@ -321,7 +325,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int
n_IRQ)
return;
}
DPRINTF(Raise OpenPIC INT output cpu %d irq %d\n, n_CPU, n_IRQ);
-opp-irq_raise(opp, n_CPU, src);
+openpic_irq_raise(opp, n_CPU, src);
}
/* update pic state because registers for n_IRQ have changed value */
@@ -753,7 +757,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr
addr,
IPVP_PRIORITY(src-ipvp) dst-servicing.priority)) {
DPRINTF(Raise OpenPIC INT output cpu %d irq %d\n,
idx, n_IRQ);
-opp-irq_raise(opp, idx, src);
+openpic_irq_raise(opp, idx, src);
}
break;
default:
@@ -996,7 +1000,13 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
{
-qemu_irq_raise(opp-dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+int n_ci = IDR_CI0 - n_CPU;
+
+if ((opp-flags OPENPIC_FLAG_IDE_CRIT) test_bit(src-ide, n_ci)) {
+qemu_irq_raise(opp-dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
+} else {
+qemu_irq_raise(opp-dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+}
}
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
@@ -1059,7 +1069,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
-opp-irq_raise = openpic_irq_raise;
opp-reset = openpic_reset;
if (pmem)
@@ -1068,18 +1077,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
return qemu_allocate_irqs(openpic_set_irq, opp, opp-max_irq);
}
-static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
-{
-int n_ci = IDR_CI0 - n_CPU;
-
-if(test_bit(src-ide, n_ci)) {
-qemu_irq_raise(mpp-dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
-}
-else {
-qemu_irq_raise(mpp-dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
-}
-}
-
static void mpic_reset (void *opaque)
{
openpic_t *mpp = (openpic_t *)opaque;
@@ -1265,7 +1262,8 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr
base,
mpp-dst[i].irqs = irqs[i];
mpp-irq_out = irq_out;
-mpp-irq_raise = mpic_irq_raise;
+/* Enable critical interrupt support */
+mpp-flags |= OPENPIC_FLAG_IDE_CRIT;
mpp-reset = mpic_reset;
register_savevm(NULL, mpic, 0, 2, openpic_save, openpic_load, mpp);
diff --git a/hw/openpic.h b/hw/openpic.h
index f50a1e4..1232d10 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -11,6 +11,9 @@ enum {
OPENPIC_OUTPUT_NB,
};
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDE_CRIT(1 0)
+
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
--
1.6.0.2
[Qemu-devel] [PATCH 14/40] openpic: update to proper memory api
The openpic code was still using the old mmio memory api. Convert it to
be a generic memory api user and clean up some code that becomes redundant
that way.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 138 --
1 files changed, 48 insertions(+), 90 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 122ce76..1d714f4 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -461,7 +461,8 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int
n_IRQ, uint32_t val)
opp-src[n_IRQ].ipvp);
}
-static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
+static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
@@ -527,7 +528,7 @@ static void openpic_gbl_write (void *opaque, hwaddr addr,
uint32_t val)
}
}
-static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
+static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -584,7 +585,8 @@ static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
return retval;
}
-static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+unsigned len)
{
openpic_t *opp = opaque;
int idx;
@@ -615,7 +617,7 @@ static void openpic_timer_write (void *opaque, uint32_t
addr, uint32_t val)
}
}
-static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
+static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -648,7 +650,8 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t
addr)
return retval;
}
-static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
int idx;
@@ -667,7 +670,7 @@ static void openpic_src_write (void *opaque, uint32_t addr,
uint32_t val)
}
}
-static uint32_t openpic_src_read (void *opaque, uint32_t addr)
+static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -749,7 +752,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr
addr,
}
}
-static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
+static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_cpu_write_internal(opaque, addr, val, (addr 0x1f000) 12);
}
@@ -833,96 +837,63 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
hwaddr addr,
return retval;
}
-static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
+static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
{
return openpic_cpu_read_internal(opaque, addr, (addr 0x1f000) 12);
}
-static void openpic_buggy_write (void *opaque,
- hwaddr addr, uint32_t val)
-{
-printf(Invalid OPENPIC write access !\n);
-}
-
-static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
-{
-printf(Invalid OPENPIC read access !\n);
-
-return -1;
-}
-
-static void openpic_writel (void *opaque,
-hwaddr addr, uint32_t val)
+static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
-addr = 0x3;
DPRINTF(%s: offset %08x val: %08x\n, __func__, (int)addr, val);
if (addr 0x1100) {
/* Global registers */
-openpic_gbl_write(opp, addr, val);
+openpic_gbl_write(opp, addr, val, len);
} else if (addr 0x1) {
/* Timers registers */
-openpic_timer_write(opp, addr, val);
+openpic_timer_write(opp, addr, val, len);
} else if (addr 0x2) {
/* Source registers */
-openpic_src_write(opp, addr, val);
+openpic_src_write(opp, addr, val, len);
} else {
/* CPU registers */
-openpic_cpu_write(opp, addr, val);
+openpic_cpu_write(opp, addr, val, len);
}
}
-static uint32_t openpic_readl (void *opaque,hwaddr addr)
+static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
-addr = 0x3;
DPRINTF(%s: offset %08x\n, __func__, (int)addr);
if (addr 0x1100) {
/* Global registers */
-retval = openpic_gbl_read(opp, addr);
+retval = openpic_gbl_read(opp, addr, len);
} else if (addr 0x1) {
/* Timers registers */
-retval = openpic_timer_read(opp, addr);
+retval = openpic_timer_read(opp, addr, len);
} else if (addr
[Qemu-devel] [PATCH 25/40] openpic: convert to qdev
This patch converts the OpenPIC device to qdev. Along the way it
renames the openpic target to raven and the mpic target to
fsl_mpic_20, to better reflect the actual models they implement.
This way we have a generic OpenPIC device now that can handle
different flavors of the OpenPIC specification.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 278 ++---
hw/openpic.h |8 +-
hw/ppc/e500.c | 24 -
hw/ppc_newworld.c | 25 +-
4 files changed, 180 insertions(+), 155 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 5116b3e..591b291 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -37,6 +37,7 @@
#include ppc_mac.h
#include pci.h
#include openpic.h
+#include sysbus.h
//#define DEBUG_OPENPIC
@@ -54,30 +55,10 @@
#define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
#define VID 0x03 /* MPIC version ID */
-enum {
-IRQ_IPVP = 0,
-IRQ_IDE,
-};
-
-/* OpenPIC */
-#define OPENPIC_MAX_CPU 2
-#define OPENPIC_MAX_IRQ 64
-#define OPENPIC_EXT_IRQ 48
-#define OPENPIC_MAX_TMR MAX_TMR
-#define OPENPIC_MAX_IPI MAX_IPI
-
-/* Interrupt definitions */
-#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
-#define OPENPIC_IRQ_ERR(OPENPIC_EXT_IRQ + 1) /* Error IRQ */
-#define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
-#if OPENPIC_MAX_IPI 0
-#define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI
IRQ */
-#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU *
OPENPIC_MAX_IPI)) /* First doorbell IRQ */
-#else
-#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First
doorbell IRQ */
-#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First
mailbox IRQ */
-#endif
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDE_CRIT (1 0)
+/* OpenPIC address map */
#define OPENPIC_GLB_REG_START0x0
#define OPENPIC_GLB_REG_SIZE 0x10F0
#define OPENPIC_TMR_REG_START0x10F0
@@ -87,31 +68,37 @@ enum {
#define OPENPIC_CPU_REG_START0x2
#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
-/* MPIC */
-#define MPIC_MAX_CPU 1
-#define MPIC_MAX_EXT 12
-#define MPIC_MAX_INT 64
-#define MPIC_MAX_IRQ MAX_IRQ
+/* Raven */
+#define RAVEN_MAX_CPU 2
+#define RAVEN_MAX_EXT 48
+#define RAVEN_MAX_IRQ 64
+#define RAVEN_MAX_TMR MAX_TMR
+#define RAVEN_MAX_IPI MAX_IPI
+
+/* Interrupt definitions */
+#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
+#define RAVEN_ERR_IRQ(RAVEN_MAX_EXT + 1) /* Error IRQ */
+#define RAVEN_TMR_IRQ(RAVEN_MAX_EXT + 2) /* First timer IRQ */
+#define RAVEN_IPI_IRQ(RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
+/* First doorbell IRQ */
+#define RAVEN_DBL_IRQ(RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
+
+/* FSL_MPIC_20 */
+#define FSL_MPIC_20_MAX_CPU 1
+#define FSL_MPIC_20_MAX_EXT 12
+#define FSL_MPIC_20_MAX_INT 64
+#define FSL_MPIC_20_MAX_IRQ MAX_IRQ
/* Interrupt definitions */
/* IRQs, accessible through the IRQ region */
-#define MPIC_EXT_IRQ 0x00
-#define MPIC_INT_IRQ 0x10
-#define MPIC_MSG_IRQ 0xb0
-#define MPIC_MSI_IRQ 0xe0
+#define FSL_MPIC_20_EXT_IRQ 0x00
+#define FSL_MPIC_20_INT_IRQ 0x10
+#define FSL_MPIC_20_MSG_IRQ 0xb0
+#define FSL_MPIC_20_MSI_IRQ 0xe0
/* These are available through separate regions, but
for simplicity's sake mapped into the same number space */
-#define MPIC_TMR_IRQ 0x100
-#define MPIC_IPI_IRQ 0x104
-
-#define MPIC_GLB_REG_START0x0
-#define MPIC_GLB_REG_SIZE 0x10F0
-#define MPIC_TMR_REG_START0x10F0
-#define MPIC_TMR_REG_SIZE 0x220
-#define MPIC_SRC_REG_START0x1
-#define MPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
-#define MPIC_CPU_REG_START0x2
-#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
+#define FSL_MPIC_20_TMR_IRQ 0x100
+#define FSL_MPIC_20_IPI_IRQ 0x104
/*
* Block Revision Register1 (BRR1): QEMU does not fully emulate
@@ -129,6 +116,7 @@ enum {
#define FREP_VID_SHIFT 0
#define VID_REVISION_1_2 2
+#define VID_REVISION_1_3 3
#define VENI_GENERIC 0x /* Generic Vendor ID */
@@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
} IRQ_dst_t;
typedef struct OpenPICState {
-PCIDevice pci_dev;
+SysBusDevice busdev;
MemoryRegion mem;
/* Behavior control */
+uint32_t model;
uint32_t flags;
uint32_t nb_irqs;
uint32_t vid;
@@ -231,15 +220,15 @@ typedef struct OpenPICState {
IRQ_src_t src[MAX_IRQ];
/* Local registers per output pin */
IRQ_dst_t dst[MAX_CPU];
-int nb_cpus;
+uint32_t nb_cpus;
/* Timer registers */
struct {
uint32_t ticc; /* Global timer current count register */
uint32_t tibc; /* Global timer base count
Re: [Qemu-devel] [PATCH] define qemukvm-1.2 machine type
Paolo Bonzini pbonz...@redhat.com writes: I think distros that used to ship qemu-kvm should just change the default just like for the acpi_piix4.c change. Maybe we could provide a --with-qemu-kvm-compat configure flag to them? I like this. I think that defeats the purpose of a single binary. I think it would be better for the distros to have a qemu-kvm script that was: /usr/libexec/qemu-kvm: #!/bin/sh qemu-system-x86_64 -enable-qemu-kvm-compat $@ That would be even better. I proposed a configure flag because I understood (maybe incorrectly) that Paolo proposed a build-time default change. Yes, that's what I was thinking. The problem is that Fedora did ship a qemu-system-x86_64 binary that disabled the qemu-kvm options (including using TCG by default), but it still had a qemu-kvm-compatible migration format. Can you be more specific? What's different in the migration format? Regards, Anthony Liguori Paolo
[Qemu-devel] [PATCH 12/40] openpic: Remove unused code
The openpic code had a few WIP bits left that nobody reanimated within
the last few years. Remove that code.
Signed-off-by: Alexander Graf ag...@suse.de
Acked-by: Hervé Poussineau hpous...@reactos.org
---
hw/openpic.c | 163 --
1 files changed, 0 insertions(+), 163 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 8b3784a..b30c853 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -46,27 +46,8 @@
#define DPRINTF(fmt, ...) do { } while (0)
#endif
-#define USE_MPCxxx /* Intel model is broken, for now */
-
-#if defined (USE_INTEL_GW80314)
-/* Intel GW80314 I/O Companion chip */
-
-#define MAX_CPU 4
-#define MAX_IRQ32
-#define MAX_DBL 4
-#define MAX_MBX 4
-#define MAX_TMR 4
-#define VECTOR_BITS 8
-#define MAX_IPI 4
-
-#define VID (0x)
-
-#elif defined(USE_MPCxxx)
-
#define MAX_CPU15
#define MAX_IRQ 128
-#define MAX_DBL 0
-#define MAX_MBX 0
#define MAX_TMR 4
#define VECTOR_BITS 8
#define MAX_IPI 4
@@ -149,12 +130,6 @@ enum mpic_ide_bits {
IDR_P0 = 0,
};
-#else
-#error Please select which OpenPic implementation is to be emulated
-#endif
-
-#define OPENPIC_PAGE_SIZE 4096
-
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
@@ -250,19 +225,6 @@ typedef struct openpic_t {
uint32_t ticc; /* Global timer current count register */
uint32_t tibc; /* Global timer base count register */
} timers[MAX_TMR];
-#if MAX_DBL 0
-/* Doorbell registers */
-uint32_t dar;/* Doorbell activate register */
-struct {
-uint32_t dmr;/* Doorbell messaging register */
-} doorbells[MAX_DBL];
-#endif
-#if MAX_MBX 0
-/* Mailbox registers */
-struct {
-uint32_t mbr;/* Mailbox register */
-} mailboxes[MAX_MAILBOXES];
-#endif
/* IRQ out is used when in bypass mode (not implemented) */
qemu_irq irq_out;
int max_irq;
@@ -470,19 +432,6 @@ static void openpic_reset (void *opaque)
opp-timers[i].ticc = 0x;
opp-timers[i].tibc = 0x8000;
}
-/* Initialise doorbells */
-#if MAX_DBL 0
-opp-dar = 0x;
-for (i = 0; i MAX_DBL; i++) {
-opp-doorbells[i].dmr = 0x;
-}
-#endif
-/* Initialise mailboxes */
-#if MAX_MBX 0
-for (i = 0; i MAX_MBX; i++) { /* ? */
-opp-mailboxes[i].mbr = 0x;
-}
-#endif
/* Go out of RESET state */
opp-glbc = 0x;
}
@@ -518,84 +467,6 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int
n_IRQ, uint32_t val)
opp-src[n_IRQ].ipvp);
}
-#if 0 // Code provision for Intel model
-#if MAX_DBL 0
-static uint32_t read_doorbell_register (openpic_t *opp,
-int n_dbl, uint32_t offset)
-{
-uint32_t retval;
-
-switch (offset) {
-case DBL_IPVP_OFFSET:
-retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
-break;
-case DBL_IDE_OFFSET:
-retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
-break;
-case DBL_DMR_OFFSET:
-retval = opp-doorbells[n_dbl].dmr;
-break;
-}
-
-return retval;
-}
-
-static void write_doorbell_register (penpic_t *opp, int n_dbl,
- uint32_t offset, uint32_t value)
-{
-switch (offset) {
-case DBL_IVPR_OFFSET:
-write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
-break;
-case DBL_IDE_OFFSET:
-write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
-break;
-case DBL_DMR_OFFSET:
-opp-doorbells[n_dbl].dmr = value;
-break;
-}
-}
-#endif
-
-#if MAX_MBX 0
-static uint32_t read_mailbox_register (openpic_t *opp,
- int n_mbx, uint32_t offset)
-{
-uint32_t retval;
-
-switch (offset) {
-case MBX_MBR_OFFSET:
-retval = opp-mailboxes[n_mbx].mbr;
-break;
-case MBX_IVPR_OFFSET:
-retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx);
-break;
-case MBX_DMR_OFFSET:
-retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx);
-break;
-}
-
-return retval;
-}
-
-static void write_mailbox_register (openpic_t *opp, int n_mbx,
-uint32_t address, uint32_t value)
-{
-switch (offset) {
-case MBX_MBR_OFFSET:
-opp-mailboxes[n_mbx].mbr = value;
-break;
-case MBX_IVPR_OFFSET:
-write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value);
-break;
-case MBX_DMR_OFFSET:
-write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value);
-break;
-}
-}
-#endif
-#endif /* 0 : Code provision for Intel model */
-
static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
{
openpic_t *opp = opaque;
@@ -841,7 +712,6 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr
addr,
dst = opp-dst[idx];
addr = 0xFF0;
switch (addr) {
-#if MAX_IPI 0
Re: [Qemu-devel] [PATCH 1/2] add visitor for parsing int[KMGT] input string
On Wed, 12 Dec 2012 16:16:42 -0200
Eduardo Habkost ehabk...@redhat.com wrote:
On Mon, Dec 10, 2012 at 10:33:06PM +0100, Igor Mammedov wrote:
Caller of visit_type_suffixed_int() have to specify
value of 'K' suffix using suffix_factor argument.
Example of selecting suffix_factor value:
* Kbytes: 1024
* Khz: 1000
Signed-off-by: Igor Mammedov imamm...@redhat.com
Reviewed-by: Eduardo Habkost ehabk...@redhat.com
I wonder if we could later introduce a visit_type_frequency() function
that simply calls visit_type_suffixed_int(). This would allow us to use
a 'frequency' type on QAPI, like the existing 'size' type we already
have.
I suggest having explicitly distinct types on QAPI because the 'size'
type probably won't abort (and maybe it _can't_ abort, to keep
compatibility) in case it finds a 100MB string. Likewise, the
It won't accept MB with current code, but we could probably pass
something like custom suffix table {KHz = 1000, MHz=100, ...} instead
of unit for variables that accept frequency, and a corresponding table for
sizes and whatever else if needed. Than we could use only
visit_type_suffixed_int() and avoid creating an extra boiler code for every
kind of units that might be needed in future.
'frequency' type wouldn't abort in case it finds a 100MHz string.
With separate types, we could also make the 'frequency' type _not_
accept 100B as a valid string (strtosz_suffix_unit() accepts B as a
valid suffix, today).
---
v3:
- Fix errp check. Spotted-By: Andreas Färber afaer...@suse.de
- s/type_unit_suffixed_int/type_suffixed_int/
- use 'suffix_factor' instead of 'unit'
- document visit_type_suffixed_int()
- add comment on current impl. limitation
v2:
- convert type_freq to type_unit_suffixed_int.
- provide qapi_dealloc_type_unit_suffixed_int() impl.
---
qapi/qapi-dealloc-visitor.c | 8
qapi/qapi-visit-core.c | 35 +++
qapi/qapi-visit-core.h | 4
qapi/string-input-visitor.c | 25 +
4 files changed, 72 insertions(+)
[...]
--
Eduardo
--
Regards,
Igor
[Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable
Today the first slot id in our e500 pci implementation is hardcoded to
0x11. Keep it there as default, but allow users to change the default to
a different id.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppce500_pci.c |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index e534341..4cd4edc 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -87,6 +87,7 @@ struct PPCE500PCIState {
struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
uint32_t gasket_time;
qemu_irq irq[4];
+uint32_t first_slot;
/* mmio maps */
MemoryRegion container;
MemoryRegion iomem;
@@ -361,7 +362,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
mpc85xx_pci_map_irq, s-irq, address_space_mem,
- s-pio, PCI_DEVFN(0x11, 0), 4);
+ s-pio, PCI_DEVFN(s-first_slot, 0), 4);
h-bus = b;
pci_create_simple(b, 0, e500-host-bridge);
@@ -401,12 +402,18 @@ static const TypeInfo e500_host_bridge_info = {
.class_init= e500_host_bridge_class_init,
};
+static Property pcihost_properties[] = {
+DEFINE_PROP_UINT32(first_slot, PPCE500PCIState, first_slot, 0x11),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void e500_pcihost_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k-init = e500_pcihost_initfn;
+dc-props = pcihost_properties;
dc-vmsd = vmstate_ppce500_pci;
}
--
1.6.0.2
[Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller
From: Bharat Bhushan r65...@freescale.com
PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt generation 2) Allow CCSR registers access when configured
as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.
What I observed is that when guest read the size of BAR0 of host controller
configuration header (TYPE1 header) then it always reads it as 0. When
looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
device registering BAR0. I do not find any other controller also doing so
may they do not use BAR0.
There are two issues when BAR0 is not there (which I can think of):
1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
when reading the size of BAR0, it should give size as per real h/w.
2) Do we need this BAR0 inbound address translation?
When BAR0 is of non-zero size then it will be configured for PCI
address space to local address(CCSR) space translation on inbound access.
The primary use case is for MSI interrupt generation. The device is
configured with an address offsets in PCI address space, which will be
translated to MSI interrupt generation MPIC registers. Currently I do
not understand the MSI interrupt generation mechanism in QEMU and also
IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
But this BAR0 will be used when using MSI on e500.
I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
but i do not see these being used for address translation.
So far that works because pci address space and local address space are 1:1
mapped. BAR0 inbound translation + ATMU translation will complete the address
translation of inbound traffic.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
[agraf: fix double variable assignment w/o read]
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/e500-ccsr.h | 17
hw/ppc/e500.c | 55 +++
hw/ppce500_pci.c | 29 ++-
3 files changed, 91 insertions(+), 10 deletions(-)
create mode 100644 hw/ppc/e500-ccsr.h
diff --git a/hw/ppc/e500-ccsr.h b/hw/ppc/e500-ccsr.h
new file mode 100644
index 000..f20f51b
--- /dev/null
+++ b/hw/ppc/e500-ccsr.h
@@ -0,0 +1,17 @@
+#ifndef E500_CCSR_H
+#define E500_CCSR_H
+
+#include ../sysbus.h
+
+typedef struct PPCE500CCSRState {
+/* private */
+SysBusDevice parent;
+/* public */
+
+MemoryRegion ccsr_space;
+} PPCE500CCSRState;
+
+#define TYPE_CCSR e500-ccsr
+#define CCSR(obj) OBJECT_CHECK(PPCE500CCSRState, (obj), TYPE_CCSR)
+
+#endif /* E500_CCSR_H */
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 8538933..47e2d41 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -17,6 +17,7 @@
#include config.h
#include qemu-common.h
#include e500.h
+#include e500-ccsr.h
#include net.h
#include hw/hw.h
#include hw/serial.h
@@ -422,8 +423,9 @@ void ppce500_init(PPCE500Params *params)
qemu_irq **irqs, *mpic;
DeviceState *dev;
CPUPPCState *firstenv = NULL;
-MemoryRegion *ccsr;
+MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
+PPCE500CCSRState *ccsr;
/* Setup CPUs */
if (params-cpu_model == NULL) {
@@ -480,12 +482,17 @@ void ppce500_init(PPCE500Params *params)
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
-ccsr = g_malloc0(sizeof(MemoryRegion));
-memory_region_init(ccsr, e500-ccsr, MPC8544_CCSRBAR_SIZE);
-memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, ccsr);
+dev = qdev_create(NULL, e500-ccsr);
+object_property_add_child(qdev_get_machine(), e500-ccsr,
+ OBJECT(dev), NULL);
+qdev_init_nofail(dev);
+ccsr = CCSR(dev);
+ccsr_addr_space = ccsr-ccsr_space;
+memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
+ccsr_addr_space);
/* MPIC */
-mpic = mpic_init(ccsr, MPC8544_MPIC_REGS_OFFSET,
+mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
smp_cpus, irqs, NULL);
if (!mpic) {
@@ -494,13 +501,13 @@ void ppce500_init(PPCE500Params *params)
/* Serial */
if (serial_hds[0]) {
-serial_mm_init(ccsr, MPC8544_SERIAL0_REGS_OFFSET,
+serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
0, mpic[12+26], 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
-serial_mm_init(ccsr, MPC8544_SERIAL1_REGS_OFFSET,
+serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
0, mpic[12+26], 399193,
serial_hds[1], DEVICE_BIG_ENDIAN);
}
@@
[Qemu-devel] [PATCH 19/26] usb: Add an usb_device_ep_stopped USBDevice method
Some usb devices (host or network redirection) can benefit from knowing when
the guest stops using an endpoint. Redirection may involve submitting packets
independently from the guest (in combination with a fifo buffer between the
redirection code and the guest), to ensure that buffers of the real usb device
are timely emptied. This is done for example for isoc traffic and for interrupt
input endpoints. But when the (re)submission of packets is done by the device
code, then how does it know when to stop this?
For isoc endpoints this is handled by detecting a set interface (change alt
setting) command, which works well for isoc endpoints. But for interrupt
endpoints currently the redirection code never stops receiving data from
the device, which is less then ideal.
However the controller emulation is aware when a guest looses interest, as
then the qh for the endpoint gets unlinked (ehci, ohci, uhci) or the endpoint
is explicitly stopped (xhci). This patch adds a new ep_stopped USBDevice
method and modifies the hcd code to call this on queue unlink / ep stop.
This makes it possible for the redirection code to properly stop receiving
interrupt input (*) data when the guest no longer has interest in it.
*) And in the future also buffered bulk input.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb.h | 8
hw/usb/bus.c | 8
hw/usb/hcd-ehci.c | 19 ++-
hw/usb/hcd-ohci.c | 30 ++
hw/usb/hcd-uhci.c | 1 +
hw/usb/hcd-xhci.c | 7 +++
6 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/hw/usb.h b/hw/usb.h
index 268e653..21caa54 100644
--- a/hw/usb.h
+++ b/hw/usb.h
@@ -307,6 +307,12 @@ typedef struct USBDeviceClass {
*/
void (*flush_ep_queue)(USBDevice *dev, USBEndpoint *ep);
+/*
+ * Called by the hcd to let the device know the queue for an endpoint
+ * has been unlinked / stopped. Optional may be NULL.
+ */
+void (*ep_stopped)(USBDevice *dev, USBEndpoint *ep);
+
const char *product_desc;
const USBDesc *usb_desc;
} USBDeviceClass;
@@ -539,6 +545,8 @@ void usb_device_set_interface(USBDevice *dev, int interface,
void usb_device_flush_ep_queue(USBDevice *dev, USBEndpoint *ep);
+void usb_device_ep_stopped(USBDevice *dev, USBEndpoint *ep);
+
const char *usb_device_get_product_desc(USBDevice *dev);
const USBDesc *usb_device_get_usb_desc(USBDevice *dev);
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
index 8264c24..da69ec6 100644
--- a/hw/usb/bus.c
+++ b/hw/usb/bus.c
@@ -189,6 +189,14 @@ void usb_device_flush_ep_queue(USBDevice *dev, USBEndpoint
*ep)
}
}
+void usb_device_ep_stopped(USBDevice *dev, USBEndpoint *ep)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass-ep_stopped) {
+klass-ep_stopped(dev, ep);
+}
+}
+
static int usb_qdev_init(DeviceState *qdev)
{
USBDevice *dev = USB_DEVICE(qdev);
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 36165b0..bf9b2b9 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -622,6 +622,17 @@ static EHCIQueue *ehci_alloc_queue(EHCIState *ehci,
uint32_t addr, int async)
return q;
}
+static void ehci_queue_stopped(EHCIQueue *q)
+{
+int endp = get_field(q-qh.epchar, QH_EPCHAR_EP);
+
+if (!q-last_pid || !q-dev) {
+return;
+}
+
+usb_device_ep_stopped(q-dev, usb_ep_get(q-dev, q-last_pid, endp));
+}
+
static int ehci_cancel_queue(EHCIQueue *q)
{
EHCIPacket *p;
@@ -629,7 +640,7 @@ static int ehci_cancel_queue(EHCIQueue *q)
p = QTAILQ_FIRST(q-packets);
if (p == NULL) {
-return 0;
+goto leave;
}
trace_usb_ehci_queue_action(q, cancel);
@@ -637,6 +648,9 @@ static int ehci_cancel_queue(EHCIQueue *q)
ehci_free_packet(p);
packets++;
} while ((p = QTAILQ_FIRST(q-packets)) != NULL);
+
+leave:
+ehci_queue_stopped(q);
return packets;
}
@@ -1386,6 +1400,9 @@ static int ehci_execute(EHCIPacket *p, const char *action)
return -1;
}
+if (!ehci_verify_pid(p-queue, p-qtd)) {
+ehci_queue_stopped(p-queue); /* Mark the ep in the prev dir stopped */
+}
p-pid = ehci_get_pid(p-qtd);
p-queue-last_pid = p-pid;
endp = get_field(p-queue-qh.epchar, QH_EPCHAR_EP);
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index e16a2ec..05e183d 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -430,6 +430,23 @@ static USBDevice *ohci_find_device(OHCIState *ohci,
uint8_t addr)
return NULL;
}
+static void ohci_stop_endpoints(OHCIState *ohci)
+{
+USBDevice *dev;
+int i, j;
+
+for (i = 0; i ohci-num_ports; i++) {
+dev = ohci-rhport[i].port.dev;
+if (dev dev-attached) {
+usb_device_ep_stopped(dev, dev-ep_ctl);
+for (j = 0; j USB_MAX_ENDPOINTS; j++) {
+usb_device_ep_stopped(dev, dev-ep_in[j]);
+usb_device_ep_stopped(dev, dev-ep_out[j]);
+}
+
[Qemu-devel] [PATCH 14/26] uhci: Add a QH_VALID define
Rather then using the magic 32 value in various places.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/hcd-uhci.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index 1e32549..11ccdc8 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -75,6 +75,9 @@
#define FRAME_MAX_LOOPS 256
+/* Must be large enough to handle 10 frame delay for initial isoc requests */
+#define QH_VALID 32
+
#define NB_PORTS 2
enum {
@@ -206,9 +209,7 @@ static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t
qh_addr, UHCI_TD *td,
queue-ep = ep;
QTAILQ_INIT(queue-asyncs);
QTAILQ_INSERT_HEAD(s-queues, queue, next);
-/* valid needs to be large enough to handle 10 frame delay
- * for initial isochronous requests */
-queue-valid = 32;
+queue-valid = QH_VALID;
trace_usb_uhci_queue_add(queue-token);
return queue;
}
@@ -854,7 +855,7 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q,
uint32_t qh_addr,
}
if (q) {
-q-valid = 32;
+q-valid = QH_VALID;
}
/* Is active ? */
--
1.8.0.1
[Qemu-devel] [PATCH 10/26] ehci: Further speedup rescanning if async schedule after raising an interrupt
I tried lowering the time between raising an interrupt and rescanning the
async schedule to see if the guest has queued a new transfer before, but
that did not have any positive effect. I now believe the cause for this is
that lowering this time made it more likely to hit the 1 ms interrupt
threshold penalty for the next packet, as described in my
ehci: Use uframe precision for interrupt threshold checking commit.
Now that we do interrupt threshold handling with uframe precision, futher
lowering this time from .5 to .25 ms gives an extra 15% improvement in speed
(MB/s) reading from a simple USB-2.0 thumb-drive.
While at it also properly set the int_req_by_async flag for short packet
completions.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/hcd-ehci.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index ef3ab97..c4d77bc 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -1341,6 +1341,9 @@ static void ehci_execute_complete(EHCIQueue *q)
if (tbytes) {
/* 4.15.1.2 must raise int on a short input packet */
ehci_raise_irq(q-ehci, USBSTS_INT);
+if (q-async) {
+q-ehci-int_req_by_async = true;
+}
}
} else {
tbytes = 0;
@@ -2337,7 +2340,7 @@ static void ehci_frame_timer(void *opaque)
/* If we've raised int, we speed up the timer, so that we quickly
* notice any new packets queued up in response */
if (ehci-int_req_by_async (ehci-usbsts USBSTS_INT)) {
-expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2);
+expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 4);
ehci-int_req_by_async = false;
} else {
expire_time = t_now + (get_ticks_per_sec()
--
1.8.0.1
[Qemu-devel] [PATCH 21/26] usbredir: Add USBEP2I and I2USBEP helper macros
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/redirect.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index 4cf8780..7b2cd8c 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -43,6 +43,11 @@
#define NO_INTERFACE_INFO 255 /* Valid interface_count always = 32 */
#define EP2I(ep_address) (((ep_address 0x80) 3) | (ep_address 0x0f))
#define I2EP(i) (((i 0x10) 3) | (i 0x0f))
+#define USBEP2I(usb_ep) (((usb_ep)-pid == USB_TOKEN_IN) ? \
+ ((usb_ep)-nr | 0x10) : ((usb_ep)-nr))
+#define I2USBEP(d, i) (usb_ep_get((d)-dev, \
+ ((i) 0x10) ? USB_TOKEN_IN : USB_TOKEN_OUT, \
+ (i) 0x0f))
typedef struct USBRedirDevice USBRedirDevice;
@@ -1373,11 +1378,10 @@ static void usbredir_set_pipeline(USBRedirDevice *dev,
struct USBEndpoint *uep)
static void usbredir_setup_usb_eps(USBRedirDevice *dev)
{
struct USBEndpoint *usb_ep;
-int i, pid;
+int i;
for (i = 0; i MAX_ENDPOINTS; i++) {
-pid = (i 0x10) ? USB_TOKEN_IN : USB_TOKEN_OUT;
-usb_ep = usb_ep_get(dev-dev, pid, i 0x0f);
+usb_ep = I2USBEP(dev, i);
usb_ep-type = dev-endpoint[i].type;
usb_ep-ifnum = dev-endpoint[i].interface;
usb_ep-max_packet_size = dev-endpoint[i].max_packet_size;
--
1.8.0.1
[Qemu-devel] [PATCH 20/26] usbredir: Add an usbredir_stop_ep helper function
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/redirect.c | 41 +++--
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index a4d324f..4cf8780 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -761,6 +761,23 @@ static void usbredir_flush_ep_queue(USBDevice *dev,
USBEndpoint *ep)
}
}
+static void usbredir_stop_ep(USBRedirDevice *dev, int i)
+{
+uint8_t ep = I2EP(i);
+
+switch (dev-endpoint[i].type) {
+case USB_ENDPOINT_XFER_ISOC:
+usbredir_stop_iso_stream(dev, ep);
+break;
+case USB_ENDPOINT_XFER_INT:
+if (ep USB_DIR_IN) {
+usbredir_stop_interrupt_receiving(dev, ep);
+}
+break;
+}
+usbredir_free_bufpq(dev, ep);
+}
+
static void usbredir_set_config(USBRedirDevice *dev, USBPacket *p,
int config)
{
@@ -770,17 +787,7 @@ static void usbredir_set_config(USBRedirDevice *dev,
USBPacket *p,
DPRINTF(set config %d id %PRIu64\n, config, p-id);
for (i = 0; i MAX_ENDPOINTS; i++) {
-switch (dev-endpoint[i].type) {
-case USB_ENDPOINT_XFER_ISOC:
-usbredir_stop_iso_stream(dev, I2EP(i));
-break;
-case USB_ENDPOINT_XFER_INT:
-if (i 0x10) {
-usbredir_stop_interrupt_receiving(dev, I2EP(i));
-}
-break;
-}
-usbredir_free_bufpq(dev, I2EP(i));
+usbredir_stop_ep(dev, i);
}
set_config.configuration = config;
@@ -808,17 +815,7 @@ static void usbredir_set_interface(USBRedirDevice *dev,
USBPacket *p,
for (i = 0; i MAX_ENDPOINTS; i++) {
if (dev-endpoint[i].interface == interface) {
-switch (dev-endpoint[i].type) {
-case USB_ENDPOINT_XFER_ISOC:
-usbredir_stop_iso_stream(dev, I2EP(i));
-break;
-case USB_ENDPOINT_XFER_INT:
-if (i 0x10) {
-usbredir_stop_interrupt_receiving(dev, I2EP(i));
-}
-break;
-}
-usbredir_free_bufpq(dev, I2EP(i));
+usbredir_stop_ep(dev, i);
}
}
--
1.8.0.1
[Qemu-devel] [PATCH 15/26] uhci: Limit amount of frames processed in one go
Before this patch uhci would process an unlimited amount of frames when
behind on schedule, by setting the timer to a time already past, causing the
timer subsys to immediately recall the frame_timer function gain.
This would cause invalid cancellations of bulk queues when the catching up
processed more then 32 frames at a moment when the bulk qh was temporarily
unlinked (which the Linux uhci driver does).
This patch fixes this by processing maximum 16 frames in one go, and always
setting the timer one ms later, making the code behave more like the ehci
code.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/hcd-uhci.c | 43 +++
1 file changed, 27 insertions(+), 16 deletions(-)
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index 11ccdc8..2a5d4cc 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -78,6 +78,8 @@
/* Must be large enough to handle 10 frame delay for initial isoc requests */
#define QH_VALID 32
+#define MAX_FRAMES_PER_TICK(QH_VALID / 2)
+
#define NB_PORTS 2
enum {
@@ -500,7 +502,7 @@ static void uhci_ioport_writew(void *opaque, uint32_t addr,
uint32_t val)
trace_usb_uhci_schedule_start();
s-expire_time = qemu_get_clock_ns(vm_clock) +
(get_ticks_per_sec() / FRAME_TIMER_FREQ);
-qemu_mod_timer(s-frame_timer, qemu_get_clock_ns(vm_clock));
+qemu_mod_timer(s-frame_timer, s-expire_time);
s-status = ~UHCI_STS_HCHALTED;
} else if (!(val UHCI_CMD_RS)) {
s-status |= UHCI_STS_HCHALTED;
@@ -1176,10 +1178,10 @@ static void uhci_bh(void *opaque)
static void uhci_frame_timer(void *opaque)
{
UHCIState *s = opaque;
+uint64_t t_now, t_last_run;
+int i, frames;
+const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ;
-/* prepare the timer for the next frame */
-s-expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
-s-frame_bytes = 0;
s-completions_only = false;
qemu_bh_cancel(s-bh);
@@ -1193,20 +1195,29 @@ static void uhci_frame_timer(void *opaque)
return;
}
-/* Process the current frame */
-trace_usb_uhci_frame_start(s-frnum);
-
-uhci_async_validate_begin(s);
-
-uhci_process_frame(s);
+/* We still store expire_time in our state, for migration */
+t_last_run = s-expire_time - frame_t;
+t_now = qemu_get_clock_ns(vm_clock);
-uhci_async_validate_end(s);
+/* Process up to MAX_FRAMES_PER_TICK frames */
+frames = (t_now - t_last_run) / frame_t;
+if (frames MAX_FRAMES_PER_TICK) {
+frames = MAX_FRAMES_PER_TICK;
+}
-/* The uhci spec says frnum reflects the frame currently being processed,
- * and the guest must look at frnum - 1 on interrupt, so inc frnum now */
-s-frnum = (s-frnum + 1) 0x7ff;
+for (i = 0; i frames; i++) {
+s-frame_bytes = 0;
+trace_usb_uhci_frame_start(s-frnum);
+uhci_async_validate_begin(s);
+uhci_process_frame(s);
+uhci_async_validate_end(s);
+/* The spec says frnum is the frame currently being processed, and
+ * the guest must look at frnum - 1 on interrupt, so inc frnum now */
+s-frnum = (s-frnum + 1) 0x7ff;
+s-expire_time += frame_t;
+}
-/* Complete the previous frame */
+/* Complete the previous frame(s) */
if (s-pending_int_mask) {
s-status2 |= s-pending_int_mask;
s-status |= UHCI_STS_USBINT;
@@ -1214,7 +1225,7 @@ static void uhci_frame_timer(void *opaque)
}
s-pending_int_mask = 0;
-qemu_mod_timer(s-frame_timer, s-expire_time);
+qemu_mod_timer(s-frame_timer, t_now + frame_t);
}
static const MemoryRegionPortio uhci_portio[] = {
--
1.8.0.1
[Qemu-devel] [PATCH 22/26] usbredir: Add ep_stopped USBDevice method
To ensure that interrupt receiving is properly stopped when the guest is
no longer interested in an interrupt endpoint.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/redirect.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index 7b2cd8c..ed2f427 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -783,6 +783,14 @@ static void usbredir_stop_ep(USBRedirDevice *dev, int i)
usbredir_free_bufpq(dev, ep);
}
+static void usbredir_ep_stopped(USBDevice *udev, USBEndpoint *uep)
+{
+USBRedirDevice *dev = DO_UPCAST(USBRedirDevice, dev, udev);
+
+usbredir_stop_ep(dev, USBEP2I(uep));
+usbredirparser_do_write(dev-parser);
+}
+
static void usbredir_set_config(USBRedirDevice *dev, USBPacket *p,
int config)
{
@@ -2017,6 +2025,7 @@ static void usbredir_class_initfn(ObjectClass *klass,
void *data)
uc-handle_data= usbredir_handle_data;
uc-handle_control = usbredir_handle_control;
uc-flush_ep_queue = usbredir_flush_ep_queue;
+uc-ep_stopped = usbredir_ep_stopped;
dc-vmsd = usbredir_vmstate;
dc-props = usbredir_properties;
}
--
1.8.0.1
[Qemu-devel] [PATCH 23/26] usbredir: Verify we have 32 bits bulk length cap when redirecting to xhci
The xhci-hcd may submit bulk transfers 65535 bytes even when not using
bulk-in pipeling, so usbredir can only be used in combination with an xhci
hcd if the client has the 32 bits bulk length capability.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/redirect.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index ed2f427..f4715f3 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -989,6 +989,8 @@ static void usbredir_do_attach(void *opaque)
usbredirparser_peer_has_cap(dev-parser,
usb_redir_cap_ep_info_max_packet_size)
usbredirparser_peer_has_cap(dev-parser,
+usb_redir_cap_32bits_bulk_length)
+usbredirparser_peer_has_cap(dev-parser,
usb_redir_cap_64bits_ids))) {
ERROR(usb-redir-host lacks capabilities needed for use with XHCI\n);
usbredir_reject_device(dev);
--
1.8.0.1
[Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling
The openpic and mpic timer handling code is basically the same.
Merge them.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 131 ++
1 files changed, 31 insertions(+), 100 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index d709e36..80016a2 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -195,7 +195,6 @@ enum IPVP_bits {
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) IPVP_VECTOR_MASK)
typedef struct IRQ_dst_t {
-uint32_t tfrr;
uint32_t pctp; /* CPU current task priority */
uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
@@ -533,9 +532,6 @@ static void openpic_gbl_write(void *opaque, hwaddr addr,
uint64_t val,
case 0x10E0: /* SPVE */
opp-spve = val 0x00FF;
break;
-case 0x10F0: /* TIFR */
-opp-tifr = val;
-break;
default:
break;
}
@@ -587,9 +583,6 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr,
unsigned len)
case 0x10E0: /* SPVE */
retval = opp-spve;
break;
-case 0x10F0: /* TIFR */
-retval = opp-tifr;
-break;
default:
break;
}
@@ -607,24 +600,28 @@ static void openpic_timer_write(void *opaque, hwaddr
addr, uint64_t val,
DPRINTF(%s: addr %08x = %08x\n, __func__, addr, val);
if (addr 0xF)
return;
-addr -= 0x10;
-addr = 0x;
-idx = (addr 0xFFF0) 6;
+idx = (addr 6) 0x3;
addr = addr 0x30;
-switch (addr) {
-case 0x00: /* TICC */
+
+if (addr == 0x0) {
+/* TIFR (TFRR) */
+opp-tifr = val;
+return;
+}
+switch (addr 0x30) {
+case 0x00: /* TICC (GTCCR) */
break;
-case 0x10: /* TIBC */
+case 0x10: /* TIBC (GTBCR) */
if ((opp-timers[idx].ticc 0x8000) != 0
(val 0x8000) == 0
(opp-timers[idx].tibc 0x8000) != 0)
opp-timers[idx].ticc = ~0x8000;
opp-timers[idx].tibc = val;
break;
-case 0x20: /* TIVP */
+case 0x20: /* TIVP (GTIVPR) */
write_IRQreg_ipvp(opp, opp-irq_tim0 + idx, val);
break;
-case 0x30: /* TIDE */
+case 0x30: /* TIDE (GTIDR) */
write_IRQreg_ide(opp, opp-irq_tim0 + idx, val);
break;
}
@@ -633,31 +630,35 @@ static void openpic_timer_write(void *opaque, hwaddr
addr, uint64_t val,
static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
-uint32_t retval;
+uint32_t retval = -1;
int idx;
DPRINTF(%s: addr %08x\n, __func__, addr);
-retval = 0x;
-if (addr 0xF)
-return retval;
-addr -= 0x10;
-addr = 0x;
-idx = (addr 0xFFF0) 6;
-addr = addr 0x30;
-switch (addr) {
-case 0x00: /* TICC */
+if (addr 0xF) {
+goto out;
+}
+idx = (addr 6) 0x3;
+if (addr == 0x0) {
+/* TIFR (TFRR) */
+retval = opp-tifr;
+goto out;
+}
+switch (addr 0x30) {
+case 0x00: /* TICC (GTCCR) */
retval = opp-timers[idx].ticc;
break;
-case 0x10: /* TIBC */
+case 0x10: /* TIBC (GTBCR) */
retval = opp-timers[idx].tibc;
break;
-case 0x20: /* TIPV */
+case 0x20: /* TIPV (TIPV) */
retval = read_IRQreg_ipvp(opp, opp-irq_tim0 + idx);
break;
-case 0x30: /* TIDE */
+case 0x30: /* TIDE (TIDR) */
retval = read_IRQreg_ide(opp, opp-irq_tim0 + idx);
break;
}
+
+out:
DPRINTF(%s: = %08x\n, __func__, retval);
return retval;
@@ -930,7 +931,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
qemu_put_sbe32s(f, opp-nb_cpus);
for (i = 0; i opp-nb_cpus; i++) {
-qemu_put_be32s(f, opp-dst[i].tfrr);
qemu_put_be32s(f, opp-dst[i].pctp);
qemu_put_be32s(f, opp-dst[i].pcsr);
openpic_save_IRQ_queue(f, opp-dst[i].raised);
@@ -983,7 +983,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
qemu_get_sbe32s(f, opp-nb_cpus);
for (i = 0; i opp-nb_cpus; i++) {
-qemu_get_be32s(f, opp-dst[i].tfrr);
qemu_get_be32s(f, opp-dst[i].pctp);
qemu_get_be32s(f, opp-dst[i].pcsr);
openpic_load_IRQ_queue(f, opp-dst[i].raised);
@@ -1100,7 +1099,6 @@ static void mpic_reset (void *opaque)
/* Initialise IRQ destinations */
for (i = 0; i MAX_CPU; i++) {
mpp-dst[i].pctp = 0x000F;
-mpp-dst[i].tfrr = 0x;
memset(mpp-dst[i].raised, 0, sizeof(IRQ_queue_t));
mpp-dst[i].raised.next = -1;
memset(mpp-dst[i].servicing, 0, sizeof(IRQ_queue_t));
@@ -1115,73 +1113,6 @@ static void mpic_reset (void *opaque)
mpp-glbc = 0x;
}
-static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned len)
-{
-openpic_t *mpp = opaque;
-int idx, cpu;
-
-DPRINTF(%s:
[Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search
When we're done with one interrupt, we need to search for the next pending
interrupt in the queue. This search has grown quite big now that we have
more than 256 possible irq lines.
So let's memorize how many interrupts we have pending in our bitmaps, so
that we can always bail out in the usual case - the one where we're all done.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 25d5cd7..3cbcea8 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -169,6 +169,7 @@ typedef struct IRQ_queue_t {
uint32_t queue[BF_WIDTH(MAX_IRQ)];
int next;
int priority;
+int pending;/* nr of pending bits in queue */
} IRQ_queue_t;
typedef struct IRQ_src_t {
@@ -251,11 +252,13 @@ static void openpic_irq_raise(OpenPICState *opp, int
n_CPU, IRQ_src_t *src);
static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
{
+q-pending++;
set_bit(q-queue, n_IRQ);
}
static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
{
+q-pending--;
reset_bit(q-queue, n_IRQ);
}
@@ -271,6 +274,12 @@ static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
next = -1;
priority = -1;
+
+if (!q-pending) {
+/* IRQ bitmap is empty */
+goto out;
+}
+
for (i = 0; i opp-max_irq; i++) {
if (IRQ_testbit(q, i)) {
DPRINTF(IRQ_check: irq %d set ipvp_pr=%d pr=%d\n,
@@ -281,6 +290,8 @@ static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
}
}
}
+
+out:
q-next = next;
q-priority = priority;
}
--
1.6.0.2
[Qemu-devel] [PATCH 21/40] openpic: remove unused type variable
The openpic source irqs are carrying around a type indicator that
is never accessed by anything. Remove it.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 27 ++-
1 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 623c807..91e87b7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -168,13 +168,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
hwaddr addr,
static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx);
-enum {
-IRQ_EXTERNAL = 0x01,
-IRQ_INTERNAL = 0x02,
-IRQ_TIMER= 0x04,
-IRQ_SPECIAL = 0x08,
-};
-
typedef struct IRQ_queue_t {
uint32_t queue[BF_WIDTH(MAX_IRQ)];
int next;
@@ -184,7 +177,6 @@ typedef struct IRQ_queue_t {
typedef struct IRQ_src_t {
uint32_t ipvp; /* IRQ vector/priority register */
uint32_t ide; /* IRQ destination register */
-int type;
int last_cpu;
int pending;/* TRUE if IRQ is pending */
} IRQ_src_t;
@@ -972,7 +964,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
for (i = 0; i opp-max_irq; i++) {
qemu_put_be32s(f, opp-src[i].ipvp);
qemu_put_be32s(f, opp-src[i].ide);
-qemu_put_sbe32s(f, opp-src[i].type);
qemu_put_sbe32s(f, opp-src[i].last_cpu);
qemu_put_sbe32s(f, opp-src[i].pending);
}
@@ -1022,7 +1013,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
for (i = 0; i opp-max_irq; i++) {
qemu_get_be32s(f, opp-src[i].ipvp);
qemu_get_be32s(f, opp-src[i].ide);
-qemu_get_sbe32s(f, opp-src[i].type);
qemu_get_sbe32s(f, opp-src[i].last_cpu);
qemu_get_sbe32s(f, opp-src[i].pending);
}
@@ -1059,7 +1049,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *opp;
-int i, m;
+int i;
struct {
const char *name;
MemoryRegionOps const *ops;
@@ -1102,20 +1092,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
opp-max_irq = OPENPIC_MAX_IRQ;
opp-irq_ipi0 = OPENPIC_IRQ_IPI0;
opp-irq_tim0 = OPENPIC_IRQ_TIM0;
-/* Set IRQ types */
-for (i = 0; i OPENPIC_EXT_IRQ; i++) {
-opp-src[i].type = IRQ_EXTERNAL;
-}
-for (; i OPENPIC_IRQ_TIM0; i++) {
-opp-src[i].type = IRQ_SPECIAL;
-}
-m = OPENPIC_IRQ_IPI0;
-for (; i m; i++) {
-opp-src[i].type = IRQ_TIMER;
-}
-for (; i OPENPIC_MAX_IRQ; i++) {
-opp-src[i].type = IRQ_INTERNAL;
-}
+
for (i = 0; i nb_cpus; i++)
opp-dst[i].irqs = irqs[i];
opp-irq_out = irq_out;
--
1.6.0.2
Re: [Qemu-devel] [PATCH RFC] PowerPC: Added uapi directory into linux-header
-Original Message- From: Alexander Graf [mailto:ag...@suse.de] Sent: Friday, December 14, 2012 5:06 PM To: Bhushan Bharat-R65777 Cc: qemu-devel qemu-devel; qemu-...@nongnu.org List; Bhushan Bharat-R65777; Jan Kiszka Subject: Re: [PATCH RFC] PowerPC: Added uapi directory into linux-header On 14.12.2012, at 12:04, Bharat Bhushan wrote: This is corrently done for powerpc. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com Jan, could you please check if this is correct? --- configure |1 + scripts/update-linux-headers.sh |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/configure b/configure index 780b19a..bdc2d5e 100755 --- a/configure +++ b/configure @@ -3701,6 +3701,7 @@ if test $linux = yes ; then # For non-KVM architectures we will not have asm headers if [ -e $source_path/linux-headers/asm-$linux_arch ]; then symlink $source_path/linux-headers/asm-$linux_arch linux-headers/asm + symlink $source_path/linux-headers/uapi/asm-$linux_arch + linux-headers/uapi/asm fi fi diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 4c7b566..9f6bf25 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -48,6 +48,11 @@ for arch in $ARCHLIST; do rm -rf $output/linux-headers/asm-$arch mkdir -p $output/linux-headers/asm-$arch +if [ $arch = powerpc ]; then This looks bogus. There shouldn't be any powerpc specifics anywhere in this file. This file have x86 specific also, why ? -Bharat Alex + rm -rf $output/linux-headers/uapi/asm-$arch/* +cp $linux/arch/$arch/include/uapi/asm/epapr_hcalls.h $output/linux-headers/uapi/asm-$arch/ +fi + for header in kvm.h kvm_para.h; do cp $tmpdir/include/asm/$header $output/linux-headers/asm-$arch done -- 1.7.0.4
[Qemu-devel] [PATCH 01/26] ehci: Add a ehci_writeback_async_complete_packet helper function
Also drop the warning printf, which was there mainly because this was an
untested code path (as the previous bug fixes to it show), but that no
longer is the case now :)
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/hcd-ehci.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 7536837..218b1d7 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -438,6 +438,22 @@ static inline bool ehci_periodic_enabled(EHCIState *s)
return ehci_enabled(s) (s-usbcmd USBCMD_PSE);
}
+/* Finish executing and writeback a packet outside of the regular
+ fetchqh - fetchqtd - execute - writeback cycle */
+static void ehci_writeback_async_complete_packet(EHCIPacket *p)
+{
+EHCIQueue *q = p-queue;
+int state;
+
+state = ehci_get_state(q-ehci, q-async);
+ehci_state_executing(q);
+ehci_state_writeback(q); /* Frees the packet! */
+if (!(q-qh.token QTD_TOKEN_HALT)) {
+ehci_state_advqueue(q);
+}
+ehci_set_state(q-ehci, q-async, state);
+}
+
/* packet management */
static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
@@ -455,17 +471,7 @@ static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
static void ehci_free_packet(EHCIPacket *p)
{
if (p-async == EHCI_ASYNC_FINISHED) {
-EHCIQueue *q = p-queue;
-int state = ehci_get_state(q-ehci, q-async);
-/* This is a normal, but rare condition (cancel racing completion) */
-fprintf(stderr, EHCI: Warning packet completed but not processed\n);
-ehci_state_executing(q);
-ehci_state_writeback(q);
-if (!(q-qh.token QTD_TOKEN_HALT)) {
-ehci_state_advqueue(q);
-}
-ehci_set_state(q-ehci, q-async, state);
-/* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
+ehci_writeback_async_complete_packet(p);
return;
}
trace_usb_ehci_packet_action(p-queue, p, free);
--
1.8.0.1
[Qemu-devel] [PATCH 02/26] ehci: Add ehci_verify_qh and ehci_verify_qtd helper functions
Signed-off-by: Hans de Goede hdego...@redhat.com
---
hw/usb/hcd-ehci.c | 51 +++
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 218b1d7..0d31597 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -438,6 +438,36 @@ static inline bool ehci_periodic_enabled(EHCIState *s)
return ehci_enabled(s) (s-usbcmd USBCMD_PSE);
}
+static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh)
+{
+uint32_t devaddr = get_field(qh-epchar, QH_EPCHAR_DEVADDR);
+uint32_t endp= get_field(qh-epchar, QH_EPCHAR_EP);
+if ((devaddr != get_field(q-qh.epchar, QH_EPCHAR_DEVADDR)) ||
+(endp!= get_field(q-qh.epchar, QH_EPCHAR_EP)) ||
+(qh-current_qtd != q-qh.current_qtd) ||
+(q-async qh-next_qtd != q-qh.next_qtd) ||
+(memcmp(qh-altnext_qtd, q-qh.altnext_qtd,
+ 7 * sizeof(uint32_t)) != 0) ||
+(q-dev != NULL q-dev-addr != devaddr)) {
+return false;
+} else {
+return true;
+}
+}
+
+static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd)
+{
+if (p-qtdaddr != p-queue-qtdaddr ||
+(p-queue-async !NLPTR_TBIT(p-qtd.next)
+(p-qtd.next != qtd-next)) ||
+(!NLPTR_TBIT(p-qtd.altnext) (p-qtd.altnext != qtd-altnext)) ||
+p-qtd.bufptr[0] != qtd-bufptr[0]) {
+return false;
+} else {
+return true;
+}
+}
+
/* Finish executing and writeback a packet outside of the regular
fetchqh - fetchqtd - execute - writeback cycle */
static void ehci_writeback_async_complete_packet(EHCIPacket *p)
@@ -1557,8 +1587,8 @@ out:
static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
{
+uint32_t entry;
EHCIPacket *p;
-uint32_t entry, devaddr, endp;
EHCIQueue *q;
EHCIqh qh;
@@ -1588,15 +1618,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci,
int async)
* The overlay area of the qh should never be changed by the guest,
* except when idle, in which case the reset is a nop.
*/
-devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR);
-endp= get_field(qh.epchar, QH_EPCHAR_EP);
-if ((devaddr != get_field(q-qh.epchar, QH_EPCHAR_DEVADDR)) ||
-(endp!= get_field(q-qh.epchar, QH_EPCHAR_EP)) ||
-(qh.current_qtd != q-qh.current_qtd) ||
-(q-async qh.next_qtd != q-qh.next_qtd) ||
-(memcmp(qh.altnext_qtd, q-qh.altnext_qtd,
- 7 * sizeof(uint32_t)) != 0) ||
-(q-dev != NULL q-dev-addr != devaddr)) {
+if (!ehci_verify_qh(q, qh)) {
if (ehci_reset_queue(q) 0) {
ehci_trace_guest_bug(ehci, guest updated active QH);
}
@@ -1610,7 +1632,8 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int
async)
}
if (q-dev == NULL) {
-q-dev = ehci_find_device(q-ehci, devaddr);
+q-dev = ehci_find_device(q-ehci,
+ get_field(q-qh.epchar, QH_EPCHAR_DEVADDR));
}
if (p p-async == EHCI_ASYNC_FINISHED) {
@@ -1768,11 +1791,7 @@ static int ehci_state_fetchqtd(EHCIQueue *q)
p = QTAILQ_FIRST(q-packets);
if (p != NULL) {
-if (p-qtdaddr != q-qtdaddr ||
-(q-async !NLPTR_TBIT(p-qtd.next)
-(p-qtd.next != qtd.next)) ||
-(!NLPTR_TBIT(p-qtd.altnext) (p-qtd.altnext != qtd.altnext)) ||
-p-qtd.bufptr[0] != qtd.bufptr[0]) {
+if (!ehci_verify_qtd(p, qtd)) {
ehci_cancel_queue(q);
ehci_trace_guest_bug(q-ehci, guest updated active QH or qTD);
p = NULL;
--
1.8.0.1
Re: [Qemu-devel] [PATCH v4 0/6] hw/ds1338.c
On 12/13/2012 03:09 PM, Peter Maydell wrote: I certainly will send further patches. As you noticed I am new to git. Thanks for your patience and advice.
