[Qemu-devel] GSoC Idea: Motorola DSP56k

[Niel van der Westhuizen]

Hey,

So I've been hacking away on an Xbox target in qemu (
https://github.com/espes/xqemu). The Xbox APU contains a Motorola DSP56362
core, and there's API and tooling for applications to generate and load
custom "effects" consisting of DSP code, so a reasonable emulation of it
seems to be required. I imagine it makes sense to implement it as a TCG
frontend, but I do not know how annoying it would be to get it wired up as
a component of a device and executing alongside x86...

I'll probably be lazilly looking at this over the next few months, but if
the idea is fleshed out and a mentor is available I could probably submit
it as a Summer of Code proposal and if accepted be forced to be a lot more
productive.

Thoughts?

Thanks,
Niel

[Qemu-devel] [PATCH] tcg: fix deposit_i64 op on 32-bit targets

[Aurelien Jarno]

On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +
deposit_i32, care should be taken to not overwrite the low part of
the second argument before the deposit when it is the same the
destination.

This fixes the shld instruction in qemu-system-x86_64, which in turns
fixes booting "system rescue CD version 2.8.0" on this target.

Reported-by: Michael S. Tsirkin 
Cc: Richard Henderson 
Cc: Paolo Bonzini 
Signed-off-by: Aurelien Jarno 
---
 tcg/tcg-op.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d70b2eb..94f6043 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2188,9 +2188,9 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, 
TCGv_i64 arg1,
 
 #if TCG_TARGET_REG_BITS == 32
 if (ofs >= 32) {
-tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
 TCGV_LOW(arg2), ofs - 32, len);
+tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
 return;
 }
 if (ofs + len <= 32) {
-- 
1.7.10.4

[Qemu-devel] xen-unstable qemu-upstream: pci-passthrough timing issues due to commit 0f7b2864d0d0c3ef2801f9214d8c510c80a220d1 when vnc enabled

[Sander Eikelenboom]

Hi Gerd,

Using qemu-upstream with pci-passthrough on xen-unstable previously worked fine.
Since commit 0f7b2864d0d0c3ef2801f9214d8c510c80a220d1 (bisected) i see what i 
think are timing issues (video device is reporting buffer underruns).

Since that commit changes vnc code, i have disabled vnc (was default enabled, 
but i did not use it).
Disabling vnc by using vnc=0 and nographic make thinks work like before.

--
Sander

Re: [Qemu-devel] [PATCH 0/1 V4] virtio-net: dynamic network offloads configuration

[Dmitry Fleytman]

Spec patch already inside.

Sent from my iPad

On Apr 20, 2013, at 8:04 PM, "Michael S. Tsirkin"  wrote:

> On Fri, Apr 19, 2013 at 10:10:01AM +0300, Dmitry Fleytman wrote:
>> Hello All,
>> 
>> Any news regarding this patch?
>> 
>> Thanks,
>> Dmitry
> 
> Rusty could you comment on the spec change soon please?
> If you pick it up I think we can include the feature in QEMU 1.5.
> 
>> On Sun, Apr 7, 2013 at 9:34 AM, Dmitry Fleytman  wrote:
>> 
>>From: Dmitry Fleytman 
>> 
>>This patch implements recently accepted by virtio-spec
>>dynamic offloads configuration feature.
>>See commit message for details.
>> 
>>V4 changes:
>>  1. Feature definitions re-used for command bitmask
>>  2. Command data made uint64
>>  3. Commit messsages fixed
>> 
>>Reported-by: Rusty Russell ru...@rustcorp.com.au
>> 
>>V3 changes:
>>  1. Compat macro added
>>  2. Feature name beautification
>> 
>>V2 changes:
>>  1. _GUEST_ added to command and feature names
>>  2. Live migration logic fixed
>> 
>>Reported-by: Michael S. Tsirkin 
>> 
>>One of recently introduced Windows features (RSC)
>>requires network driver to be able to enable and disable
>>HW LRO offload on the fly without device reinitialization.
>> 
>>Current Virtio specification doesn't support this requirement.
>>The solution proposed by following spec patch is to add
>>a new control command for this purpose.
>> 
>>The same solution may be used in Linux driver for ethtool interface
>>implementation.
>> 
>>--
>>1.8.1.4
>> 
>> 
>> 

Re: [Qemu-devel] [PATCH] i386 ROR r8/r16 instruction fix

[Aurelien Jarno]

On Mon, Apr 15, 2013 at 10:59:15AM +0400, Pavel Dovgaluk wrote:
> Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the 
> TB.
> 
> Signed-off-by: Pavel Dovgalyuk 
> ---
>  target-i386/translate.c |1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 233f24f..40f891d 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -1775,6 +1775,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int 
> op1, int is_right)
>  if (is_right) {
>  tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
>  tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
> +tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
>  } else {
>  tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
>  tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);

Thanks, applied.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

[Qemu-devel] [PATCH v2 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms

[Aurelien Jarno]

Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.

For that the helper is changed to handle 64-bit input values and mask with
up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit
marked as invalid anymore. Instead this is checked in the helper, which
therefore needs to access to the insns/insns_flags2. They are added in
the DisasContext struct. Finally change all accesses to the opcode fields
through extract helpers, prefixed with FP for consistency.

Signed-off-by: Aurelien Jarno 
---
 target-ppc/fpu_helper.c |   17 +++--
 target-ppc/translate.c  |   46 ++
 2 files changed, 41 insertions(+), 22 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 2f0db4e..e159615 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -430,20 +430,17 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 
 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 {
-/*
- * We use only the 32 LSB of the incoming fpr
- */
-uint32_t prev, new;
+target_ulong prev, new;
 int i;
 
 prev = env->fpscr;
-new = (uint32_t)arg;
-new &= ~0x6000;
-new |= prev & 0x6000;
-for (i = 0; i < 8; i++) {
+new = (target_ulong)arg;
+new &= ~0x6000LL;
+new |= prev & 0x6000LL;
+for (i = 0; i < sizeof(target_ulong) * 2; i++) {
 if (mask & (1 << i)) {
-env->fpscr &= ~(0xF << (4 * i));
-env->fpscr |= new & (0xF << (4 * i));
+env->fpscr &= ~(0xFLL << (4 * i));
+env->fpscr |= new & (0xFLL << (4 * i));
 }
 }
 /* Update VX and FEX */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 81c23fa..ef1bda4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -202,6 +202,8 @@ typedef struct DisasContext {
 int spe_enabled;
 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
 int singlestep_enabled;
+uint64_t insns_flags;
+uint64_t insns_flags2;
 } DisasContext;
 
 /* True when active word size < size of target_long.  */
@@ -423,9 +425,14 @@ EXTRACT_HELPER(ME, 1, 5);
 EXTRACT_HELPER(TO, 21, 5);
 
 EXTRACT_HELPER(CRM, 12, 8);
-EXTRACT_HELPER(FM, 17, 8);
 EXTRACT_HELPER(SR, 16, 4);
+
+/* mtfsf/mtfsfi */
+EXTRACT_HELPER(FPBF, 19, 3);
 EXTRACT_HELPER(FPIMM, 12, 4);
+EXTRACT_HELPER(FPL, 21, 1);
+EXTRACT_HELPER(FPFLM, 17, 8);
+EXTRACT_HELPER(FPW, 16, 1);
 
 /***Jump target decoding   ***/
 /* Displacement */
@@ -2355,19 +2362,27 @@ static void gen_mtfsb1(DisasContext *ctx)
 static void gen_mtfsf(DisasContext *ctx)
 {
 TCGv_i32 t0;
-int L = ctx->opcode & 0x0200;
+int flm, l, w;
 
 if (unlikely(!ctx->fpu_enabled)) {
 gen_exception(ctx, POWERPC_EXCP_FPU);
 return;
 }
+flm = FPFLM(ctx->opcode);
+l = FPL(ctx->opcode);
+w = FPW(ctx->opcode);
+if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+return;
+}
 /* NIP cannot be restored if the memory exception comes from an helper */
 gen_update_nip(ctx, ctx->nip - 4);
 gen_reset_fpstatus();
-if (L)
-t0 = tcg_const_i32(0xff);
-else
-t0 = tcg_const_i32(FM(ctx->opcode));
+if (l) {
+t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0x : 0xff);
+} else {
+t0 = tcg_const_i32(flm << (w * 8));
+}
 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
 tcg_temp_free_i32(t0);
 if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -2381,7 +2396,7 @@ static void gen_mtfsf(DisasContext *ctx)
 /* mtfsfi */
 static void gen_mtfsfi(DisasContext *ctx)
 {
-int bf, sh;
+int bf, sh, w;
 TCGv_i64 t0;
 TCGv_i32 t1;
 
@@ -2389,12 +2404,17 @@ static void gen_mtfsfi(DisasContext *ctx)
 gen_exception(ctx, POWERPC_EXCP_FPU);
 return;
 }
-bf = crbD(ctx->opcode) >> 2;
-sh = 7 - bf;
+w = FPW(ctx->opcode);
+bf = FPBF(ctx->opcode);
+if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+return;
+}
+sh = (8 * w) + 7 - bf;
 /* NIP cannot be restored if the memory exception comes from an helper */
 gen_update_nip(ctx, ctx->nip - 4);
 gen_reset_fpstatus();
-t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
+t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
 t1 = tcg_const_i32(1 << sh);
 gen_helper_store_fpscr(cpu_env, t0, t1);
 tcg_temp_free_i64(t0);
@@ -8677,8 +8697,8 @@ GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, 
PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOA

[Qemu-devel] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions

[Aurelien Jarno]

qemu-system-ppc64 -M pseries clamis to emulate a POWER7 CPU,
corresponding to an ISA 2.06 compliant CPU, while QEMU emulates
something like an ISA 2.04 CPU.

Given that glibc and GCC start to use some instructions like cmpb and
fcpsgn, this starts to be problematic.

This patches series improves the PPC emulation by bringing it to an
ISA 2.05 CPU (if we except DFP and VSX), at least from the
non-privledged point of view.

Changes v1 -> v2:
- Use (1ULL << 63) instead of (1LL << 63) to access the bit sign
- Improve description of load/store doubleword pair instructions

Aurelien Jarno (10):
  target-ppc: optimize fabs, fnabs, fneg
  disas: Disassemble all ppc insns for the guest
  target-ppc: add instruction flags for Book I 2.05
  target-ppc: emulate cmpb instruction
  target-ppc: emulate prtyw and prtyd instructions
  target-ppc: emulate fcpsgn instruction
  target-ppc: emulate lfiwax instruction
  target-ppc: emulate load doubleword pair instructions
  target-ppc: emulate store doubleword pair instructions
  target-ppc: add support for extended mtfsf/mtfsfi forms

 disas.c |1 +
 target-ppc/cpu.h|4 +-
 target-ppc/fpu_helper.c |   48 ++--
 target-ppc/helper.h |4 +-
 target-ppc/int_helper.c |   15 +++
 target-ppc/translate.c  |  260 +++
 target-ppc/translate_init.c |2 +-
 7 files changed, 268 insertions(+), 66 deletions(-)

-- 
1.7.10.4

[Qemu-devel] [PATCH v2 02/10] disas: Disassemble all ppc insns for the guest

[Aurelien Jarno]

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 disas.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/disas.c b/disas.c
index 67103e0..e51127e 100644
--- a/disas.c
+++ b/disas.c
@@ -227,6 +227,7 @@ void target_disas(FILE *out, CPUArchState *env, 
target_ulong code,
 s.info.mach = bfd_mach_ppc;
 #endif
 }
+s.info.disassembler_options = (char *)"any";
 print_insn = print_insn_ppc;
 #elif defined(TARGET_M68K)
 print_insn = print_insn_m68k;
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 01/10] target-ppc: optimize fabs, fnabs, fneg

[Aurelien Jarno]

fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.

Signed-off-by: Aurelien Jarno 
---
 target-ppc/fpu_helper.c |   31 ---
 target-ppc/helper.h |3 ---
 target-ppc/translate.c  |   40 ++--
 3 files changed, 34 insertions(+), 40 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 9e779ea..2f0db4e 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -595,37 +595,6 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, 
uint64_t arg2)
 return farg1.ll;
 }
 
-/* fabs */
-uint64_t helper_fabs(CPUPPCState *env, uint64_t arg)
-{
-CPU_DoubleU farg;
-
-farg.ll = arg;
-farg.d = float64_abs(farg.d);
-return farg.ll;
-}
-
-/* fnabs */
-uint64_t helper_fnabs(CPUPPCState *env, uint64_t arg)
-{
-CPU_DoubleU farg;
-
-farg.ll = arg;
-farg.d = float64_abs(farg.d);
-farg.d = float64_chs(farg.d);
-return farg.ll;
-}
-
-/* fneg */
-uint64_t helper_fneg(CPUPPCState *env, uint64_t arg)
-{
-CPU_DoubleU farg;
-
-farg.ll = arg;
-farg.d = float64_chs(farg.d);
-return farg.ll;
-}
-
 /* fctiw - fctiw. */
 uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
 {
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d33ee66..07397b2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -80,9 +80,6 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
 DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
 DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
 DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64)
-DEF_HELPER_2(fabs, i64, env, i64)
-DEF_HELPER_2(fnabs, i64, env, i64)
-DEF_HELPER_2(fneg, i64, env, i64)
 DEF_HELPER_2(fsqrt, i64, env, i64)
 DEF_HELPER_2(fre, i64, env, i64)
 DEF_HELPER_2(fres, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5e741d1..2ceb02f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2161,7 +2161,16 @@ static void gen_fcmpu(DisasContext *ctx)
 /*** Floating-point move   ***/
 /* fabs */
 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
+static void gen_fabs(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+ ~(1ULL << 63));
+gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
 
 /* fmr  - fmr. */
 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
@@ -2177,10 +2186,29 @@ static void gen_fmr(DisasContext *ctx)
 
 /* fnabs */
 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
+static void gen_fnabs(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+1ULL << 63);
+gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
 /* fneg */
 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
+static void gen_fneg(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+ 1ULL << 63);
+gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
 
 /***  Floating-Point status & ctrl register***/
 
@@ -8476,7 +8504,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, 
PPC_FLOAT_FSQRT),
 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x0061, PPC_FLOAT),
 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x0061, PPC_FLOAT),
+GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F, PPC_FLOAT),
 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F, PPC_FLOAT),
+GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F, PPC_FLOAT),
+GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F, PPC_FLOAT),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
@@ -8833,9 +8864,6 @@ GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
 
 #undef GEN_LD
 #undef GEN_LDU
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno 
---
 target-ppc/translate.c |   48 
 1 file changed, 48 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8298e1f..690fb45 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3293,6 +3293,52 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
  /* lfs lfsu lfsux lfsx */
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
 
+/* lfdp */
+static void gen_lfdp(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_FLOAT);
+EA = tcg_temp_new();
+gen_addr_imm_index(ctx, EA, 0);   \
+if (unlikely(ctx->le_mode)) {
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+} else {
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+}
+tcg_temp_free(EA);
+}
+
+/* lfdpx */
+static void gen_lfdpx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_FLOAT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+if (unlikely(ctx->le_mode)) {
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+} else {
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+}
+tcg_temp_free(EA);
+}
+
 /* lfiwax */
 static void gen_lfiwax(DisasContext *ctx)
 {
@@ -9023,6 +9069,8 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x0001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x0023, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x0021, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_STF
 #undef GEN_STUF
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/translate.c |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 977f9ef..4b1896f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2253,6 +2253,19 @@ static void gen_fneg(DisasContext *ctx)
 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
 }
 
+/* fcpsgn: PowerPC 2.05 specification */
+/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
+static void gen_fcpsgn(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+cpu_fpr[rB(ctx->opcode)], 0, 63);
+gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
 /***  Floating-Point status & ctrl register***/
 
 /* mcrfs */
@@ -8554,6 +8567,7 @@ GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F, 
PPC_FLOAT),
 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F, PPC_FLOAT),
 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F, PPC_FLOAT),
 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F, PPC_FLOAT),
+GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05

[Aurelien Jarno]

.. and enable it on POWER7 CPU.

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/cpu.h|4 +++-
 target-ppc/translate_init.c |2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 42c36e2..8b0b651 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1870,8 +1870,10 @@ enum {
 PPC2_PRCNTL= 0x0008ULL,
 /* Byte-reversed, indexed, double-word load and store*/
 PPC2_DBRX  = 0x0010ULL,
+/* Book I 2.05 PowerPC specification */
+PPC2_ISA205= 0x0020ULL,
 
-#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
 };
 
 /*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 781170f..14f6599 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7014,7 +7014,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
-pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
 pcc->msr_mask = 0x8204FF36ULL;
 pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 04/10] target-ppc: emulate cmpb instruction

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/helper.h |1 +
 target-ppc/int_helper.c |   15 +++
 target-ppc/translate.c  |8 
 3 files changed, 24 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 07397b2..56814b5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -36,6 +36,7 @@ DEF_HELPER_3(mulldo, i64, env, i64, i64)
 DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_3(sraw, tl, env, tl, tl)
 #if defined(TARGET_PPC64)
 DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 54eca9b..e50bdd2 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -53,6 +53,21 @@ target_ulong helper_cntlzd(target_ulong t)
 }
 #endif
 
+target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
+{
+target_ulong mask = 0xff;
+target_ulong ra = 0;
+int i;
+
+for (i = 0; i < sizeof(target_ulong); i++) {
+if ((rs & mask) == (rb & mask)) {
+ra |= mask;
+}
+mask <<= 8;
+}
+return ra;
+}
+
 /* shift right arithmetic helper */
 target_ulong helper_sraw(CPUPPCState *env, target_ulong value,
  target_ulong shift)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2ceb02f..6bee6db 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -739,6 +739,13 @@ static void gen_isel(DisasContext *ctx)
 tcg_temp_free_i32(t0);
 }
 
+/* cmpb: PowerPC 2.05 specification */
+static void gen_cmpb(DisasContext *ctx)
+{
+gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
+cpu_gpr[rB(ctx->opcode)]);
+}
+
 /***   Integer arithmetic  ***/
 
 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
@@ -8454,6 +8461,7 @@ GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x0040, 
PPC_INTEGER),
 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x0040, PPC_INTEGER),
 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x0040, PPC_INTEGER),
 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x0040, PPC_INTEGER),
+GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x0001, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x0001, PPC_ISEL),
 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x, PPC_INTEGER),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x, PPC_INTEGER),
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/translate.c |   18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4b1896f..8298e1f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2526,7 +2526,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv 
arg1, TCGv arg2)
 }
 }
 
-#if defined(TARGET_PPC64)
 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
 {
 if (unlikely(ctx->le_mode)) {
@@ -2536,7 +2535,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv 
arg1, TCGv arg2)
 } else
 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
 }
-#endif
 
 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
@@ -3295,6 +3293,21 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
  /* lfs lfsu lfsux lfsx */
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
 
+/* lfiwax */
+static void gen_lfiwax(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_FLOAT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_ld32s(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+tcg_temp_free(EA);
+}
+
 /*** Floating-point store  ***/
 #define GEN_STF(name, stop, opc, type)\
 static void glue(gen_, name)(DisasContext *ctx)
   \
@@ -9009,6 +9022,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
 
 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
+GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x0001, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_STF
 #undef GEN_STUF
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instructions

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/translate.c |   38 ++
 1 file changed, 38 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6bee6db..977f9ef 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
 }
 #endif
 
+/* prtyw: PowerPC 2.05 specification */
+static void gen_prtyw(DisasContext *ctx)
+{
+TCGv ra = cpu_gpr[rA(ctx->opcode)];
+TCGv rs = cpu_gpr[rS(ctx->opcode)];
+TCGv t0 = tcg_temp_new();
+tcg_gen_shri_tl(t0, rs, 16);
+tcg_gen_xor_tl(ra, rs, t0);
+tcg_gen_shri_tl(t0, ra, 8);
+tcg_gen_xor_tl(ra, ra, t0);
+#if defined(TARGET_PPC64)
+tcg_gen_andi_tl(ra, ra, 0x10001);
+#else
+tcg_gen_andi_tl(ra, ra, 1);
+#endif
+tcg_temp_free(t0);
+}
+
+#if defined(TARGET_PPC64)
+/* prtyd: PowerPC 2.05 specification */
+static void gen_prtyd(DisasContext *ctx)
+{
+TCGv ra = cpu_gpr[rA(ctx->opcode)];
+TCGv rs = cpu_gpr[rS(ctx->opcode)];
+TCGv t0 = tcg_temp_new();
+tcg_gen_shri_tl(t0, rs, 32);
+tcg_gen_xor_tl(ra, rs, t0);
+tcg_gen_shri_tl(t0, ra, 16);
+tcg_gen_xor_tl(ra, ra, t0);
+tcg_gen_shri_tl(t0, ra, 8);
+tcg_gen_xor_tl(ra, ra, t0);
+tcg_gen_andi_tl(ra, ra, 1);
+tcg_temp_free(t0);
+}
+#endif
+
 #if defined(TARGET_PPC64)
 /* extsw & extsw. */
 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -8489,9 +8525,11 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x, 
PPC_INTEGER),
 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x, PPC_INTEGER),
 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0xF801, PPC_POPCNTB),
 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0xF801, PPC_POPCNTWD),
+GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0xF801, PPC_NONE, PPC2_ISA205),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0xF801, PPC_POPCNTWD),
 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x, PPC_64B),
+GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0xF801, PPC_NONE, PPC2_ISA205),
 #endif
 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x, PPC_INTEGER),
 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x, PPC_INTEGER),
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 09/10] target-ppc: emulate store doubleword pair instructions

[Aurelien Jarno]

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno 
---
 target-ppc/translate.c |   48 
 1 file changed, 48 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 690fb45..81c23fa 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3447,6 +3447,52 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
 /* stfs stfsu stfsux stfsx */
 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
 
+/* stfdp */
+static void gen_stfdp(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_FLOAT);
+EA = tcg_temp_new();
+gen_addr_imm_index(ctx, EA, 0);   \
+if (unlikely(ctx->le_mode)) {
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+} else {
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+}
+tcg_temp_free(EA);
+}
+
+/* stfdpx */
+static void gen_stfdpx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_FLOAT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+if (unlikely(ctx->le_mode)) {
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+} else {
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+tcg_gen_addi_tl(EA, EA, 8);
+gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+}
+tcg_temp_free(EA);
+}
+
 /* Optional: */
 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv 
arg2)
 {
@@ -9094,6 +9140,8 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
+GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x0023, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x0021, PPC_NONE, PPC2_ISA205),
 
 #undef GEN_CRLOGIC
 #define GEN_CRLOGIC(name, tcg_op, opc)\
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 6/6] qemu-file: do not use stdio for qemu_fdopen

[Blue Swirl]

On Wed, Apr 17, 2013 at 9:46 AM, Paolo Bonzini  wrote:
> This uses system calls directly for Unix file descriptors, so that the
> efficient writev_buffer can be used.  Pay attention to the possibility
> of partial writes in writev.
>
> Reviewed-by: Juan Quintela 
> Reviewed-by: Orit Wassermann 
> Signed-off-by: Paolo Bonzini 
> ---
>  savevm.c | 101 
> ---
>  1 file changed, 90 insertions(+), 11 deletions(-)
>
> diff --git a/savevm.c b/savevm.c
> index ffabbff..31dcce9 100644
> --- a/savevm.c
> +++ b/savevm.c
> @@ -356,9 +356,94 @@ static const QEMUFileOps stdio_file_write_ops = {
>  .close =  stdio_fclose
>  };
>
> +static ssize_t unix_writev_buffer(void *opaque, struct iovec *iov, int 
> iovcnt,
> +  int64_t pos)
> +{
> +QEMUFileSocket *s = opaque;
> +ssize_t len, offset;
> +ssize_t size = iov_size(iov, iovcnt);
> +ssize_t total = 0;
> +
> +assert(iovcnt > 0);
> +offset = 0;
> +while (size > 0) {
> +/* Find the next start position; skip all full-sized vector elements 
>  */
> +while (offset >= iov[0].iov_len) {
> +offset -= iov[0].iov_len;
> +iov++, iovcnt--;
> +}
> +
> +/* skip `offset' bytes from the (now) first element, undo it on exit 
> */
> +assert(iovcnt > 0);
> +iov[0].iov_base += offset;
> +iov[0].iov_len -= offset;
> +
> +do {
> +len = writev(s->fd, iov, iovcnt);

This breaks mingw32 build:
  LINK  i386-softmmu/qemu-system-i386.exe
savevm.o: In function `unix_writev_buffer':
/src/qemu/savevm.c:382: undefined reference to `_writev'
collect2: error: ld returned 1 exit status

> +} while (len == -1 && errno == EINTR);
> +if (len == -1) {
> +return -errno;
> +}
> +
> +/* Undo the changes above */
> +iov[0].iov_base -= offset;
> +iov[0].iov_len += offset;
> +
> +/* Prepare for the next iteration */
> +offset += len;
> +total += len;
> +size -= len;
> +}
> +
> +return total;
> +}
> +
> +static int unix_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
> +{
> +QEMUFileSocket *s = opaque;
> +ssize_t len;
> +
> +for (;;) {
> +len = read(s->fd, buf, size);
> +if (len != -1) {
> +break;
> +}
> +if (errno == EAGAIN) {
> +yield_until_fd_readable(s->fd);
> +} else if (errno != EINTR) {
> +break;
> +}
> +}
> +
> +if (len == -1) {
> +len = -errno;
> +}
> +return len;
> +}
> +
> +static int unix_close(void *opaque)
> +{
> +QEMUFileSocket *s = opaque;
> +close(s->fd);
> +g_free(s);
> +return 0;
> +}
> +
> +static const QEMUFileOps unix_read_ops = {
> +.get_fd = socket_get_fd,
> +.get_buffer = unix_get_buffer,
> +.close =  unix_close
> +};
> +
> +static const QEMUFileOps unix_write_ops = {
> +.get_fd = socket_get_fd,
> +.writev_buffer = unix_writev_buffer,
> +.close =  unix_close
> +};
> +
>  QEMUFile *qemu_fdopen(int fd, const char *mode)
>  {
> -QEMUFileStdio *s;
> +QEMUFileSocket *s;
>
>  if (mode == NULL ||
> (mode[0] != 'r' && mode[0] != 'w') ||
> @@ -367,21 +452,15 @@ QEMUFile *qemu_fdopen(int fd, const char *mode)
>  return NULL;
>  }
>
> -s = g_malloc0(sizeof(QEMUFileStdio));
> -s->stdio_file = fdopen(fd, mode);
> -if (!s->stdio_file)
> -goto fail;
> +s = g_malloc0(sizeof(QEMUFileSocket));
> +s->fd = fd;
>
>  if(mode[0] == 'r') {
> -s->file = qemu_fopen_ops(s, &stdio_file_read_ops);
> +s->file = qemu_fopen_ops(s, &unix_read_ops);
>  } else {
> -s->file = qemu_fopen_ops(s, &stdio_file_write_ops);
> +s->file = qemu_fopen_ops(s, &unix_write_ops);
>  }
>  return s->file;
> -
> -fail:
> -g_free(s);
> -return NULL;
>  }
>
>  static const QEMUFileOps socket_read_ops = {
> --
> 1.8.1.4
>
>

Re: [Qemu-devel] [PATCH v5 3/3] configure/Make: Build libfdt from submodule DTC

[Blue Swirl]

On Thu, Apr 18, 2013 at 4:47 AM,   wrote:
> From: Peter Crosthwaite 
>
> Configure to use the DTC submodule to build libfdt when no system libfdt
> is found. Prompt to install the DTC submodule if --enable-fdt is set but
> no DTC can be found.
>
> DTC has no out-of-tree build capability, so the configure will symlink
> the Makefile and scripts directory in the out of tree build directory
> and pass in all the needed DTC arguments to make out of tree build happen.
> Ideally we fix the DTC make to support out of tree, but did it this way to
> avoid commits to DTC.
>
> Signed-off-by: David Holsgrove 
> Signed-off-by: Peter Crosthwaite 
> Reviewed-by: Peter Maydell 
> ---
> changed from v4:
> Use error_exit fn (PMM review)
> changed from v3:
> Rebased against recent devls.
> Fixed some cosmetics.
> changed from v2:
> Fixed quoting of Make arguments (PMM review)
> Fixed comment styling and typos (PMM review)
>
>  Makefile  |   10 ++
>  configure |   31 ++-
>  2 files changed, 36 insertions(+), 5 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 67f19f2..88375dc 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -145,6 +145,15 @@ pixman/Makefile: $(SRC_PATH)/pixman/configure
>  $(SRC_PATH)/pixman/configure:
> (cd $(SRC_PATH)/pixman; autoreconf -v --install)
>
> +DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" 
> LIBFDT_srcdir=$(SRC_PATH)/dtc/libfdt
> +DTC_CFLAGS=$(CFLAGS) $(extra_cflags) -I$(BUILD_DIR)/dtc -I$(SRC_PATH)/dtc 
> -I$(SRC_PATH)/dtc/libfdt

This is not entirely correct, I get these errors:
mingw32:
 CC libfdt/fdt.o
cc1: warnings being treated as errors
/src/qemu/dtc/libfdt/fdt.c:1: warning: -fPIC ignored for target (all
code is position independent)

Other flags, including -fPIC, is missing for Clang:
 LD libfdt/libfdt-1.3.0.so
/usr/bin/ld: libfdt/fdt.o: relocation R_X86_64_32S against `.rodata'
can not be used when making a shared object; recompile with -fPIC

My build script also passes additional CFLAGS to both.

Perhaps the fix is to use QEMU_CFLAGS instead of (or in addition to)
CFLAGS above for DTC_CFLAGS? Or add -fPIC as with pixman?

> +
> +subdir-dtc:dtc/libfdt dtc/tests
> +   $(call quiet-command,$(MAKE) $(DTC_MAKE_ARGS) 
> CPPFLAGS="$(DTC_CFLAGS)" LDFLAGS="$(LDFLAGS)" ARFLAGS="$(ARFLAGS)" CC="$(CC)" 
> AR="$(AR)" LD="$(LD)" $(SUBDIR_MAKEFLAGS) libfdt,)
> +
> +dtc/%:
> +   mkdir -p $@
> +
>  $(SUBDIR_RULES): libqemuutil.a libqemustub.a $(common-obj-y)
>
>  ROMSUBDIR_RULES=$(patsubst %,romsubdir-%, $(ROMS))
> @@ -262,6 +271,7 @@ distclean: clean
> rm -rf $$d || exit 1 ; \
>  done
> if test -f pixman/config.log; then make -C pixman distclean; fi
> +   if test -f dtc/version_gen.h; then make $(DTC_MAKE_ARGS) clean; fi
>
>  KEYMAPS=da en-gb  et  fr fr-ch  is  lt  modifiers  no  pt-br  sv \
>  ar  de en-us  fi  fr-be  hr it  lv  nl pl  ru th \
> diff --git a/configure b/configure
> index d5f1516..7546799 100755
> --- a/configure
> +++ b/configure
> @@ -2496,17 +2496,34 @@ if test "$fdt" != "no" ; then
>  int main(void) { return 0; }
>  EOF
>if compile_prog "" "$fdt_libs" ; then
> +# system DTC is good - use it
>  fdt=yes
> -libs_softmmu="$libs_softmmu $fdt_libs"
> -  else
> -if test "$fdt" = "yes" ; then
> -  feature_not_found "fdt"
> +  elif test -d ${source_path}/dtc/libfdt ; then
> +# have submodule DTC - use it
> +fdt=yes
> +dtc_internal="yes"
> +mkdir -p dtc
> +if [ "$source_path" != `pwd` ] ; then
> +   symlink "$source_path/dtc/Makefile" "dtc/Makefile"
> +   symlink "$source_path/dtc/scripts" "dtc/scripts"
>  fi
> +fdt_cflags="-I\$(SRC_PATH)/dtc/libfdt"
> +fdt_libs="-L\$(BUILD_DIR)/dtc/libfdt $fdt_libs"
> +  elif test "$fdt" = "yes" ; then
> +# have neither and want - prompt for system/submodule install
> +error_exit "ERROR: DTC not present. Your options:" \
> +"  (1) Preferred: Install the DTC devel package" \
> +"  (2) Fetch the DTC submodule, using:" \
> +"  git submodule update --init dtc"
> +  else
> +# don't have and don't want
>  fdt_libs=
>  fdt=no
>fi
>  fi
>
> +libs_softmmu="$libs_softmmu $fdt_libs"
> +
>  ##
>  # GLX probe, used by milkymist-tmu2
>  if test "$glx" != "no" ; then
> @@ -3452,7 +3469,7 @@ if test "$cpu" = "ppc64" -a "$targetos" != "Darwin" ; 
> then
>  fi
>
>  # add pixman flags after all config tests are done
> -QEMU_CFLAGS="$QEMU_CFLAGS $pixman_cflags"
> +QEMU_CFLAGS="$QEMU_CFLAGS $pixman_cflags $fdt_cflags"
>  libs_softmmu="$libs_softmmu $pixman_libs"
>
>  echo "Install prefix$prefix"
> @@ -4515,6 +4532,10 @@ if [ "$pixman" = "internal" ]; then
>echo "config-host.h: subdir-pixman" >> $config_host_mak
>  fi
>
> +if [ "$dtc_internal" = "yes" ]; then
> +  echo "config-host.h: subdir-dtc" >> $config_host_mak
> +fi
> +
>  # build tree in object directory in case 

Re: [Qemu-devel] [PATCH v3 0/2] Drop support for qdev taddr properties

[Blue Swirl]

Thanks, applied all.


On Sat, Apr 20, 2013 at 1:48 PM, Peter Maydell  wrote:
> There is currently only one user of the qdev taddr (target addr,
> now hwaddr) property code, and that user is wrong anyway, since the
> property it's trying to set isn't actually a taddr property.
> Fix the erroneous use in sm501 and drop all the taddr property code.
>
> The justification for dropping the support is that a device should
> generally not be exposing properties whose width (conceptually)
> depends on the target CPU type. (This is the same rationale for
> not supporting hwaddr fields in migration state.) Instead the
> device should expose either a 32 bit or 64 bit property, depending
> on what the actual hardware does.
>
> Changes v2->v3:
>  * rebased and fixed trivial textual conflict in xilinx_axidma.c
> Changes v1->v2:
>  * no functional changes, just rebased since Paolo's moved
>everything around and the old patches won't apply
>
> Peter Maydell (2):
>   hw/sm501: Use correct setter for sysbus-ohci dma-address property
>   qdev: Drop taddr properties
>
>  hw/block/fdc.c  |1 -
>  hw/core/Makefile.objs   |1 -
>  hw/core/qdev-addr.c |   78 
> ---
>  hw/display/sm501.c  |3 +-
>  hw/display/tcx.c|1 -
>  hw/dma/xilinx_axidma.c  |1 -
>  hw/lm32/milkymist-hw.h  |1 -
>  hw/net/milkymist-minimac2.c |1 -
>  hw/sparc/sun4m.c|1 -
>  include/hw/qdev-addr.h  |   10 --
>  10 files changed, 1 insertion(+), 97 deletions(-)
>  delete mode 100644 hw/core/qdev-addr.c
>  delete mode 100644 include/hw/qdev-addr.h
>
> --
> 1.7.9.5
>

Re: [Qemu-devel] [PATCH 0/1 V4] virtio-net: dynamic network offloads configuration

[Michael S. Tsirkin]

On Fri, Apr 19, 2013 at 10:10:01AM +0300, Dmitry Fleytman wrote:
> Hello All,
> 
> Any news regarding this patch?
> 
> Thanks,
> Dmitry
> 

Rusty could you comment on the spec change soon please?
If you pick it up I think we can include the feature in QEMU 1.5.

> On Sun, Apr 7, 2013 at 9:34 AM, Dmitry Fleytman  wrote:
> 
> From: Dmitry Fleytman 
> 
> This patch implements recently accepted by virtio-spec
> dynamic offloads configuration feature.
> See commit message for details.
> 
> V4 changes:
>   1. Feature definitions re-used for command bitmask
>   2. Command data made uint64
>   3. Commit messsages fixed
> 
> Reported-by: Rusty Russell ru...@rustcorp.com.au
> 
> V3 changes:
>   1. Compat macro added
>   2. Feature name beautification
> 
> V2 changes:
>   1. _GUEST_ added to command and feature names
>   2. Live migration logic fixed
> 
> Reported-by: Michael S. Tsirkin 
> 
> One of recently introduced Windows features (RSC)
> requires network driver to be able to enable and disable
> HW LRO offload on the fly without device reinitialization.
> 
> Current Virtio specification doesn't support this requirement.
> The solution proposed by following spec patch is to add
> a new control command for this purpose.
> 
> The same solution may be used in Linux driver for ethtool interface
> implementation.
>
> --
> 1.8.1.4
> 
> 
> 

Re: [Qemu-devel] [PULL v4 07/11] rdma: introduce capability for chunk registration

[Michael S. Tsirkin]

On Thu, Apr 18, 2013 at 04:07:24PM -0600, Eric Blake wrote:
> On 04/17/2013 05:07 PM, mrhi...@linux.vnet.ibm.com wrote:
> > From: "Michael R. Hines" 
> > 
> > This capability allows you to disable dynamic chunk registration
> > for better throughput on high-performance links.
> > 
> > It is enabled by default.
> > 
> > Signed-off-by: Michael R. Hines 
> > ---
> >  migration.c  |   10 ++
> >  qapi-schema.json |8 +++-
> >  2 files changed, 17 insertions(+), 1 deletion(-)
> 
> >  #
> > +# @x-chunk-register-destination: (since 1.5) RDMA option which controls 
> > whether
> > +#  or not the entire VM memory footprint is mlock() on demand or 
> > all at once.
> > +#  Refer to docs/rdma.txt for more advice on when to take 
> > advantage option.
> 
> s/take advantage/use this/
> 
> > +#  Enabled by default, and will be renamed to 
> > 'chunk-register-destination' 
> > +#  after experimental testing is complete.
> 
> I wouldn't promise a rename - after all, testing may prove that we can
> settle on enough heuristics to set this appropriately without needing a
> user option, even for the workloads where it makes a difference.  Thus,
> I think better wording might be:
> 
> Enabled by default.  Experimental: may be renamed or removed after
> further testing is complete.
> 
> Sorry for not thinking about this earlier, but typically you want a
> capability bit to default to 0 - it's much easier to assume that a bit
> not present behaves the same as a bit that is present and 0.  Or put
> another way, a older management app that asks for all enabled
> capabilities on a newer qemu has an easier time ignoring 0 bits that it
> doesn't recognize (oh, some new feature I don't know about, but it isn't
> on, so it can't hurt) than it does ignoring 1 bits (oh, a feature I
> don't recognize, but it's enabled - will it mess up my migration?).
> Since this is a bool, I would much rather can we rename the capability
> to express the opposite sense, and default it to 0.  I'm not even sure
> from your description here whether 'true' means 'mlock() on demand' or
> 'all at once', just that I'm supposed to read rdma.txt to decide if I
> want to move away from the default.
> 
> /me reads patch 11 again... and wonders why the docs came last instead
> of first in the series...
> 
> I guess the opposite sense could be named 'x-rdma-pin-all'; default
> false means to do chunk registration and release,

chunk release only happens after migration is complete unfortunately.
This means that eventually all initialized memory is pinned, regardless
of the setting (this is fixable but there's no plan to fix this, at this
point). So pin-all might be misleading to some.

I agree 'chunk' is unnecessarily low level though.
The only difference ATM is pinning of uninitialized memory so I think a
better name would be 'x-rdma-pin-uninitialized' or some such.

> true means to pin all
> memory up front.
> 
> -- 
> Eric Blake   eblake redhat com+1-919-301-3266
> Libvirt virtualization library http://libvirt.org
> 

Re: [Qemu-devel] [PATCH] tcg: Remove temp_buf

[Richard Henderson]

On 04/20/2013 03:46 AM, Blue Swirl wrote:

On Fri, Apr 19, 2013 at 12:18 PM, Andreas Färber  wrote:

Am 19.04.2013 14:11, schrieb Andreas Färber:

Hi,

Am 19.04.2013 10:27, schrieb Richard Henderson:

All targets have been converted to allocating space for temporaries
on the stack.  No need to allocate space within the CPU_COMMON block.

Signed-off-by: Richard Henderson 
---
This depends on my tcg-arm patch set that's still outstanding.

My tree still has exactly one user in tcg/arm/, so once that disappears
feel free to add my Reviewed-by. Thanks for helping clean this up!

One question...



r~
---
  include/exec/cpu-defs.h | 2 --
  1 file changed, 2 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d8c64e9..41f5b32 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -152,8 +152,6 @@ typedef struct CPUWatchpoint {
   memory was accessed */ \
  CPU_COMMON_TLB  \
  struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];   \
-/* buffer for temporaries in the code generator */  \
-long temp_buf[CPU_TEMP_BUF_NLONGS]; \

Could CPU_TEMP_BUF_NLONGS be removed, too?

More precisely, seeing that all targets actually still use it despite in
most cases not actually accessing temp_buf, can you rename it to
TCG_TEMP_STACK_NLONGS and move it to some TCG header as a follow-up please?

Much like this patch?

http://lists.nongnu.org/archive/html/qemu-devel/2011-05/msg03086.html


Yes, that would be the one...


r~

Re: [Qemu-devel] [PATCH] monitor: intervally send down events to guest in hold time

[Eric Blake]

On 04/18/2013 10:44 PM, Amos Kong wrote:
> (qemu) sendkey a 1000
> 
> Current design is that qemu only send one down event to guest,
> and delay sometime, then send one up event. In this case, only
> key can be identified by guest.
> 
> This patch changed qemu to intervally send down events to guest
> in the hold time, the interval is 100ms.

I don't like this.  When you hold a key for a long time on bare metal,
there is only one down and one up event; if the console displays
multiple copies of the character being typed, it is because the console
does the repeats itself.  If the user wants multiple down and up events,
they should send multiple events, not rely on one command to send
multiple presses.

> 
> (qemu) sendkey a 1000
> 
> qemu will send 9 down events, 1 up event to guest, we can see
> 9 'a' in guest screen.


I'm inclined to NACK this unless you can give better explanation why
send-key should behave differently than bare metal.  If anything, the
behavior being complained about is a "feature" of the console of the
guest being tested, not something where we should change how the
hardware behaves.

-- 
Eric Blake   eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org



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Re: [Qemu-devel] xen-unstable qemu-upstream: libxl: error: libxl_qmp.c:440:qmp_next: timeout, libxl_qmp.c:705:libxl__qmp_initialize: Failed to connect to QMP

[Sander Eikelenboom]

Friday, April 19, 2013, 7:15:59 PM, you wrote:

> Il 19/04/2013 19:11, Sander Eikelenboom ha scritto:
>> BTW, is there a relation with the "main-loop: WARNING: I/O thread spun for 
>> 1000 iterations" ?
>> I'm still seeing that one popping up in the log.

> If you want to try to up the count to 1 or 10 it would be nice.

> If it doesn't disappear with 10 it's definitely a bug.

It's somewhere between 1 and 5

> Paolo

Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation

[Jan Kiszka]

On 2013-04-16 09:42, Gerd Hoffmann wrote:
> On 04/10/13 10:31, Jan Kiszka wrote:
>> On 2013-04-03 13:50, Gerd Hoffmann wrote:
>>>   Hi,
>>>
> No, it is not, and yes, this is where the inconsistency comes 
> from.  We read wred+wgreen+wblue directly from the surface 
> whereas depth is cached in the vmware vga state struct.  Patch 
> attached.  Not fully tested yet.

 Unfortunately, this doesn't change the picture (except for the 
 expected "vmsvga_value_read: Bad register 1c"). The 0x315 
 workaround does indeed work.
>>>
>>> Hmm, the patch fixes it for me (boot vesafb with 800x600 or 1024x768 @
>>> 16bpp, Xorg starts successfully) ...
>>>
>>> Can I get a full X server log?
>>
>> Here is the one without the patch (it no longer applies). If you want me
>> to rerun with that patch, please provide an update.
> 
> Pushed latest pixman bits (including vmware fixes) to
>git://git.kraxel.org/qemu rebase/pixman
> 
> Should be working fine again.

Yep, works again.

Thanks,
Jan




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[Qemu-devel] [PATCH v3 2/2] qdev: Drop taddr properties

[Peter Maydell]

Drop all the infrastructure for taddr properties (ie ones which
are 'hwaddr' sized). These are now unused, and any further desired
use would be rather questionable since device properties shouldn't
generally depend on a type that is conceptually variable based on
the target CPU. 32 or 64 bit integer properties should be used instead
as appropriate for the specific device.

Signed-off-by: Peter Maydell 
---
 hw/block/fdc.c  |1 -
 hw/core/Makefile.objs   |1 -
 hw/core/qdev-addr.c |   78 ---
 hw/display/sm501.c  |1 -
 hw/display/tcx.c|1 -
 hw/dma/xilinx_axidma.c  |1 -
 hw/lm32/milkymist-hw.h  |1 -
 hw/net/milkymist-minimac2.c |1 -
 hw/sparc/sun4m.c|1 -
 include/hw/qdev-addr.h  |   10 --
 10 files changed, 96 deletions(-)
 delete mode 100644 hw/core/qdev-addr.c
 delete mode 100644 include/hw/qdev-addr.h

diff --git a/hw/block/fdc.c b/hw/block/fdc.c
index 1ed874f..f1f1fd7 100644
--- a/hw/block/fdc.c
+++ b/hw/block/fdc.c
@@ -33,7 +33,6 @@
 #include "qemu/timer.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
-#include "hw/qdev-addr.h"
 #include "sysemu/blockdev.h"
 #include "sysemu/sysemu.h"
 #include "qemu/log.h"
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 94109f3..950146c 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -9,6 +9,5 @@ common-obj-$(CONFIG_PTIMER) += ptimer.o
 common-obj-$(CONFIG_SOFTMMU) += sysbus.o
 common-obj-$(CONFIG_SOFTMMU) += null-machine.o
 common-obj-$(CONFIG_SOFTMMU) += loader.o
-common-obj-$(CONFIG_SOFTMMU) += qdev-addr.o
 common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
 
diff --git a/hw/core/qdev-addr.c b/hw/core/qdev-addr.c
deleted file mode 100644
index 80a38bb..000
--- a/hw/core/qdev-addr.c
+++ /dev/null
@@ -1,78 +0,0 @@
-#include "hw/qdev.h"
-#include "hw/qdev-addr.h"
-#include "exec/hwaddr.h"
-#include "qapi/qmp/qerror.h"
-#include "qapi/visitor.h"
-
-/* --- target physical address --- */
-
-static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
-{
-hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
-
-*ptr = strtoull(str, NULL, 16);
-return 0;
-}
-
-static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t 
len)
-{
-hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
-return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
-}
-
-static void get_taddr(Object *obj, Visitor *v, void *opaque,
-  const char *name, Error **errp)
-{
-DeviceState *dev = DEVICE(obj);
-Property *prop = opaque;
-hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
-int64_t value;
-
-value = *ptr;
-visit_type_int64(v, &value, name, errp);
-}
-
-static void set_taddr(Object *obj, Visitor *v, void *opaque,
-  const char *name, Error **errp)
-{
-DeviceState *dev = DEVICE(obj);
-Property *prop = opaque;
-hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
-Error *local_err = NULL;
-int64_t value;
-
-if (dev->realized) {
-qdev_prop_set_after_realize(dev, name, errp);
-return;
-}
-
-visit_type_int64(v, &value, name, &local_err);
-if (local_err) {
-error_propagate(errp, local_err);
-return;
-}
-if ((uint64_t)value <= (uint64_t) ~(hwaddr)0) {
-*ptr = value;
-} else {
-error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
-  dev->id?:"", name, value, (uint64_t) 0,
-  (uint64_t) ~(hwaddr)0);
-}
-}
-
-
-PropertyInfo qdev_prop_taddr = {
-.name  = "taddr",
-.parse = parse_taddr,
-.print = print_taddr,
-.get   = get_taddr,
-.set   = set_taddr,
-};
-
-void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value)
-{
-Error *errp = NULL;
-object_property_set_int(OBJECT(dev), value, name, &errp);
-assert(!errp);
-
-}
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index fc5e539..916816f 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -28,7 +28,6 @@
 #include "ui/console.h"
 #include "hw/devices.h"
 #include "hw/sysbus.h"
-#include "hw/qdev-addr.h"
 #include "qemu/range.h"
 #include "ui/pixel_ops.h"
 
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 77c7191..d7465c6 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -26,7 +26,6 @@
 #include "ui/console.h"
 #include "ui/pixel_ops.h"
 #include "hw/sysbus.h"
-#include "hw/qdev-addr.h"
 
 #define MAXX 1024
 #define MAXY 768
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index bc62664..3a3ef8a 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -26,7 +26,6 @@
 #include "qemu/timer.h"
 #include "hw/ptimer.h"
 #include "qemu/log.h"
-#include "hw/qdev-addr.h"
 #include "qapi/qmp/qerror.h"
 
 #include "hw/stream.h"
diff --git a/hw/lm32/milkymist-hw.h b/hw/lm32/milkymist-hw.h
index 4e86c4e..5317ce6 100644
--- a/hw/lm32/milkymist-hw.h
+++ b/hw/lm32/milkymist-hw.h
@@ -2,7 +2,6 @@
 

[Qemu-devel] [PATCH v3 1/2] hw/sm501: Use correct setter for sysbus-ohci dma-address property

[Peter Maydell]

The sysbus-ohci dma-address property is declared as a HEX64
property, not a TADDR, so use the correct setter for it.

Signed-off-by: Peter Maydell 
Acked-by: Andreas Färber 
Tested-by: Aurelien Jarno 
---
 hw/display/sm501.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index f0e6d70..fc5e539 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1434,7 +1434,7 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t 
base,
 /* bridge to usb host emulation module */
 dev = qdev_create(NULL, "sysbus-ohci");
 qdev_prop_set_uint32(dev, "num-ports", 2);
-qdev_prop_set_taddr(dev, "dma-offset", base);
+qdev_prop_set_uint64(dev, "dma-offset", base);
 qdev_init_nofail(dev);
 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
 base + MMIO_BASE_OFFSET + SM501_USB_HOST);
-- 
1.7.9.5

[Qemu-devel] [PATCH v3 0/2] Drop support for qdev taddr properties

[Peter Maydell]

There is currently only one user of the qdev taddr (target addr,
now hwaddr) property code, and that user is wrong anyway, since the
property it's trying to set isn't actually a taddr property.
Fix the erroneous use in sm501 and drop all the taddr property code.

The justification for dropping the support is that a device should
generally not be exposing properties whose width (conceptually)
depends on the target CPU type. (This is the same rationale for
not supporting hwaddr fields in migration state.) Instead the
device should expose either a 32 bit or 64 bit property, depending
on what the actual hardware does.

Changes v2->v3:
 * rebased and fixed trivial textual conflict in xilinx_axidma.c
Changes v1->v2:
 * no functional changes, just rebased since Paolo's moved
   everything around and the old patches won't apply

Peter Maydell (2):
  hw/sm501: Use correct setter for sysbus-ohci dma-address property
  qdev: Drop taddr properties

 hw/block/fdc.c  |1 -
 hw/core/Makefile.objs   |1 -
 hw/core/qdev-addr.c |   78 ---
 hw/display/sm501.c  |3 +-
 hw/display/tcx.c|1 -
 hw/dma/xilinx_axidma.c  |1 -
 hw/lm32/milkymist-hw.h  |1 -
 hw/net/milkymist-minimac2.c |1 -
 hw/sparc/sun4m.c|1 -
 include/hw/qdev-addr.h  |   10 --
 10 files changed, 1 insertion(+), 97 deletions(-)
 delete mode 100644 hw/core/qdev-addr.c
 delete mode 100644 include/hw/qdev-addr.h

-- 
1.7.9.5

Re: [Qemu-devel] [PATCH v2 2/2] qdev: Drop taddr properties

[Blue Swirl]

Patch does not apply, please rebase:

Applying: qdev: Drop taddr properties
error: patch failed: hw/display/sm501.c:28
error: hw/display/sm501.c: patch does not apply
error: patch failed: hw/dma/xilinx_axidma.c:26
error: hw/dma/xilinx_axidma.c: patch does not apply
Patch failed at 0002 qdev: Drop taddr properties

On Tue, Apr 9, 2013 at 11:27 AM, Peter Maydell  wrote:
> Drop all the infrastructure for taddr properties (ie ones which
> are 'hwaddr' sized). These are now unused, and any further desired
> use would be rather questionable since device properties shouldn't
> generally depend on a type that is conceptually variable based on
> the target CPU. 32 or 64 bit integer properties should be used instead
> as appropriate for the specific device.
>
> Signed-off-by: Peter Maydell 
> ---
>  hw/block/fdc.c  |1 -
>  hw/core/Makefile.objs   |1 -
>  hw/core/qdev-addr.c |   78 
> ---
>  hw/display/sm501.c  |1 -
>  hw/display/tcx.c|1 -
>  hw/dma/xilinx_axidma.c  |1 -
>  hw/lm32/milkymist-hw.h  |1 -
>  hw/net/milkymist-minimac2.c |1 -
>  hw/sparc/sun4m.c|1 -
>  include/hw/qdev-addr.h  |   10 --
>  10 files changed, 96 deletions(-)
>  delete mode 100644 hw/core/qdev-addr.c
>  delete mode 100644 include/hw/qdev-addr.h
>
> diff --git a/hw/block/fdc.c b/hw/block/fdc.c
> index 1ed874f..f1f1fd7 100644
> --- a/hw/block/fdc.c
> +++ b/hw/block/fdc.c
> @@ -33,7 +33,6 @@
>  #include "qemu/timer.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
> -#include "hw/qdev-addr.h"
>  #include "sysemu/blockdev.h"
>  #include "sysemu/sysemu.h"
>  #include "qemu/log.h"
> diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
> index 94109f3..950146c 100644
> --- a/hw/core/Makefile.objs
> +++ b/hw/core/Makefile.objs
> @@ -9,6 +9,5 @@ common-obj-$(CONFIG_PTIMER) += ptimer.o
>  common-obj-$(CONFIG_SOFTMMU) += sysbus.o
>  common-obj-$(CONFIG_SOFTMMU) += null-machine.o
>  common-obj-$(CONFIG_SOFTMMU) += loader.o
> -common-obj-$(CONFIG_SOFTMMU) += qdev-addr.o
>  common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
>
> diff --git a/hw/core/qdev-addr.c b/hw/core/qdev-addr.c
> deleted file mode 100644
> index 80a38bb..000
> --- a/hw/core/qdev-addr.c
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -#include "hw/qdev.h"
> -#include "hw/qdev-addr.h"
> -#include "exec/hwaddr.h"
> -#include "qapi/qmp/qerror.h"
> -#include "qapi/visitor.h"
> -
> -/* --- target physical address --- */
> -
> -static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
> -{
> -hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
> -
> -*ptr = strtoull(str, NULL, 16);
> -return 0;
> -}
> -
> -static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t 
> len)
> -{
> -hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
> -return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
> -}
> -
> -static void get_taddr(Object *obj, Visitor *v, void *opaque,
> -  const char *name, Error **errp)
> -{
> -DeviceState *dev = DEVICE(obj);
> -Property *prop = opaque;
> -hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
> -int64_t value;
> -
> -value = *ptr;
> -visit_type_int64(v, &value, name, errp);
> -}
> -
> -static void set_taddr(Object *obj, Visitor *v, void *opaque,
> -  const char *name, Error **errp)
> -{
> -DeviceState *dev = DEVICE(obj);
> -Property *prop = opaque;
> -hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
> -Error *local_err = NULL;
> -int64_t value;
> -
> -if (dev->realized) {
> -qdev_prop_set_after_realize(dev, name, errp);
> -return;
> -}
> -
> -visit_type_int64(v, &value, name, &local_err);
> -if (local_err) {
> -error_propagate(errp, local_err);
> -return;
> -}
> -if ((uint64_t)value <= (uint64_t) ~(hwaddr)0) {
> -*ptr = value;
> -} else {
> -error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
> -  dev->id?:"", name, value, (uint64_t) 0,
> -  (uint64_t) ~(hwaddr)0);
> -}
> -}
> -
> -
> -PropertyInfo qdev_prop_taddr = {
> -.name  = "taddr",
> -.parse = parse_taddr,
> -.print = print_taddr,
> -.get   = get_taddr,
> -.set   = set_taddr,
> -};
> -
> -void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value)
> -{
> -Error *errp = NULL;
> -object_property_set_int(OBJECT(dev), value, name, &errp);
> -assert(!errp);
> -
> -}
> diff --git a/hw/display/sm501.c b/hw/display/sm501.c
> index 3840bce..09a819e 100644
> --- a/hw/display/sm501.c
> +++ b/hw/display/sm501.c
> @@ -28,7 +28,6 @@
>  #include "ui/console.h"
>  #include "hw/arm/devices.h"
>  #include "hw/sysbus.h"
> -#include "hw/qdev-addr.h"
>  #include "qemu/range.h"
>  #include "ui/pixel_ops.h"
>
> diff --git a/hw/display/tcx.c b/hw/display/tcx.c
> index c44068e..55abaee 100644
> --- a/hw/display/tcx.c
> +++ b

Re: [Qemu-devel] [PULL 00/11] arm-devs queue

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 2:57 PM, Peter Maydell  wrote:
> arm-devs queue pullreq; this is just the versatile-pci
> cleanup (which has been on the list for some time now).
> Please pull.
>
> thanks
> -- PMM
>
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git arm-devs.next
>
> for you to fetch changes up to af9277e69df688ebb8b7edecc45f0f85ea51:
>
>   hw/versatile_pci: Drop unnecessary vpb_pci_config_addr() (2013-04-19 
> 11:15:21 +0100)
>
> 
> Peter Maydell (11):
>   versatile_pci: Fix hardcoded tabs
>   versatile_pci: Expose PCI I/O region on Versatile PB
>   versatile_pci: Update to realize and instance init functions
>   versatile_pci: Change to subclassing TYPE_PCI_HOST_BRIDGE
>   versatile_pci: Use separate PCI I/O space rather than system I/O space
>   versatile_pci: Put the host bridge PCI device at slot 29
>   versatile_pci: Implement the correct PCI IRQ mapping
>   versatile_pci: Implement the PCI controller's control registers
>   arm/realview: Fix mapping of PCI regions
>   versatile_pci: Expose PCI memory space to system
>   hw/versatile_pci: Drop unnecessary vpb_pci_config_addr()
>
>  hw/arm/realview.c   |   22 +--
>  hw/arm/versatilepb.c|   11 +-
>  hw/pci-host/versatile.c |  399 
> +--
>  3 files changed, 371 insertions(+), 61 deletions(-)
>

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 3:06 PM, Peter Maydell  wrote:
> target-arm pullreq, containing a fix for a dumb SRS bug I
> introduced, and the update to migration to use vmstate
> (both of which have been on the list since before freeze).
> Please pull.
>
> thanks
> -- PMM
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
>
> for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:
>
>   target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)
>
> 
> Juan Quintela (1):
>   target-arm: port ARM CPU save/load to use VMState
>
> Peter Chubb (1):
>   target-arm: Reinsert missing return statement in ARM mode SRS decode
>
> Peter Maydell (2):
>   target-arm: Add some missing CPU state fields to VMState
>   target-arm: Correctly restore FPSCR
>
>  target-arm/cpu-qom.h   |4 +
>  target-arm/cpu.c   |1 +
>  target-arm/cpu.h   |2 -
>  target-arm/machine.c   |  430 
> 
>  target-arm/translate.c |1 +
>  5 files changed, 222 insertions(+), 216 deletions(-)

Re: [Qemu-devel] [PULL] [PATCH 0/3] linux-user pending patches

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 1:59 PM,   wrote:
> From: Riku Voipio 
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/rikuvoipio/qemu.git linux-user-for-upstream
>
> for you to fetch changes up to 03903ffcfb5a7c75e52da97d00eb9d0bb0660f28:
>
>   linux-user: fix setgroups/getgroups for non-UID16 archs (2013-04-19 
> 10:48:51 +0300)
>
> 
> Andreas Schwab (2):
>   linux-user: fix undefined shift in copy_to_user_fdset
>   linux-user: fix setgroups/getgroups for non-UID16 archs
>
> Petar Jovanovic (1):
>   linux-user: change do_semop to return target errno when unsuccessful
>
>  linux-user/syscall.c |   12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
>
> --
> 1.7.10.4
>
>

Re: [Qemu-devel] [Qemu-ppc] Is FW_CFG_PPC_CPUFREQ deprecated?

[Mark Cave-Ayland]

On 19/04/13 16:31, Alexander Graf wrote:


Hi everyone,

Has FW_CFG_PPC_CPUFREQ been removed from QEMU for some reason? I noticed that 
the value always comes back as 0 in OpenBIOS, and it looks as if the 
FW_CFG_PPC_CPUFREQ constant (FW_CFG_ARCH_LOCAL + 0x4) has been removed from 
hw/ppc.h?


In fact, it simply never got introduced :)


Yes - I see now from the archives that there was disagreement as to how 
to obtain the CPU frequency to pass to OpenBIOS, and while the 
FW_CFG_PPC_CPUFREQ value was removed from the final QEMU commit, it 
still remains in the related OpenBIOS commit.


Well at least it explains why when booting an PPC OS in QEMU/OpenBIOS 
all the CPU speeds appear as 0MHz ;)



ATB,

Mark.

Re: [Qemu-devel] [PATCH] tcg: Remove temp_buf

[Blue Swirl]

On Fri, Apr 19, 2013 at 12:18 PM, Andreas Färber  wrote:
> Am 19.04.2013 14:11, schrieb Andreas Färber:
>> Hi,
>>
>> Am 19.04.2013 10:27, schrieb Richard Henderson:
>>> All targets have been converted to allocating space for temporaries
>>> on the stack.  No need to allocate space within the CPU_COMMON block.
>>>
>>> Signed-off-by: Richard Henderson 
>>> ---
>>> This depends on my tcg-arm patch set that's still outstanding.
>>
>> My tree still has exactly one user in tcg/arm/, so once that disappears
>> feel free to add my Reviewed-by. Thanks for helping clean this up!
>>
>> One question...
>>
>>>
>>>
>>> r~
>>> ---
>>>  include/exec/cpu-defs.h | 2 --
>>>  1 file changed, 2 deletions(-)
>>>
>>> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
>>> index d8c64e9..41f5b32 100644
>>> --- a/include/exec/cpu-defs.h
>>> +++ b/include/exec/cpu-defs.h
>>> @@ -152,8 +152,6 @@ typedef struct CPUWatchpoint {
>>>   memory was accessed */ \
>>>  CPU_COMMON_TLB  \
>>>  struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];   \
>>> -/* buffer for temporaries in the code generator */  \
>>> -long temp_buf[CPU_TEMP_BUF_NLONGS]; \
>>
>> Could CPU_TEMP_BUF_NLONGS be removed, too?
>
> More precisely, seeing that all targets actually still use it despite in
> most cases not actually accessing temp_buf, can you rename it to
> TCG_TEMP_STACK_NLONGS and move it to some TCG header as a follow-up please?

Much like this patch?

http://lists.nongnu.org/archive/html/qemu-devel/2011-05/msg03086.html

>
> Andreas
>
>>>  \
>>>  int64_t icount_extra; /* Instructions until next timer event.  */   \
>>>  /* Number of cycles left, with interrupt flag in high bit.  \
>>>
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
>

Re: [Qemu-devel] [RFC v2 3/7] m48t59: register a QOM type for each nvram type we support

[Blue Swirl]

On Sat, Apr 20, 2013 at 9:56 AM, Artyom Tarasenko  wrote:
> On Sat, Apr 20, 2013 at 11:34 AM, Blue Swirl  wrote:
>> On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko  
>> wrote:
>>> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau  
>>> wrote:
 As m48t59 devices can only be created with m48t59_init() or 
 m48t59_init_isa(),
 we know exactly which nvram types are required. Register only those three
 types.
 Remove .model and .size properties as they can be infered from nvram name.
 Remove .io_base ISA address port as m48t59_init_isa() is always called 
 with ioport 0x74.
>>>
>>> While this it indeed how it's currently called, this is wrong for the
>>> sun4u emulation.
>>> The isa (ebus) variant of the sun4u m48t59_init_isa() should be called
>>> with a mem_base, not io_base.
>>
>> Why? I don't see much difference between EBUS and ISA and with the
>> memory API, the difference between PIO and MMIO is almost nonexistent
>> anyway.
>
> Can you elaborate? Do you mean we just need to change the io_base?

Why wouldn't that work?

>> But it should be possible to change the base to match real HW, whatever it 
>> is:
>> http://git.kernel.org/cgit/linux/kernel/git/davem/prtconfs.git/tree/ultra5#n273
>
> Yes, I know where it is supposed to be, I'm just asking how to achieve
> this best with our current tooling.
>
>> So NACK for the original patch.
>>
>>> Do you think it should be implemented as another device type?
>>>
>>>
 Signed-off-by: Hervé Poussineau 
 ---
  hw/timer/m48t59.c |  187 
 -
  1 file changed, 126 insertions(+), 61 deletions(-)

 diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
 index 41022f2..29ec462 100644
 --- a/hw/timer/m48t59.c
 +++ b/hw/timer/m48t59.c
 @@ -43,6 +43,13 @@
   * PPC platform there is also a nvram lock function.
   */

 +typedef struct M48txxInfo {
 +const char *isa_name;
 +const char *sysbus_name;
 +uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
 +uint32_t size;
 +} M48txxInfo;
 +
  /*
   * Chipset docs:
   * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
 @@ -54,7 +61,6 @@ struct M48t59State {
  /* Hardware parameters */
  qemu_irq IRQ;
  MemoryRegion iomem;
 -uint32_t io_base;
  uint32_t size;
  /* RTC management */
  time_t   time_offset;
 @@ -78,12 +84,39 @@ typedef struct M48t59ISAState {
  MemoryRegion io;
  } M48t59ISAState;

 +typedef struct M48txxISADeviceClass {
 +ISADeviceClass parent_class;
 +M48txxInfo info;
 +} M48txxISADeviceClass;
 +
  typedef struct M48t59SysBusState {
  SysBusDevice busdev;
  M48t59State state;
  MemoryRegion io;
  } M48t59SysBusState;

 +typedef struct M48txxSysBusDeviceClass {
 +SysBusDeviceClass parent_class;
 +M48txxInfo info;
 +} M48txxSysBusDeviceClass;
 +
 +static M48txxInfo m48txx_info[] = {
 +{
 +.sysbus_name = "m48t02",
 +.model = 2,
 +.size = 0x800,
 +},{
 +.sysbus_name = "m48t08",
 +.model = 8,
 +.size = 0x2000,
 +},{
 +.isa_name = "m48t59_isa",
 +.model = 59,
 +.size = 0x2000,
 +}
 +};
 +
 +
  /* Fake timer functions */

  /* Alarm management */
 @@ -640,25 +673,34 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr 
 mem_base,
  SysBusDevice *s;
  M48t59SysBusState *d;
  M48t59State *state;
 +int i;

 -dev = qdev_create(NULL, "m48t59");
 -qdev_prop_set_uint32(dev, "model", model);
 -qdev_prop_set_uint32(dev, "size", size);
 -qdev_prop_set_uint32(dev, "io_base", io_base);
 -qdev_init_nofail(dev);
 -s = SYS_BUS_DEVICE(dev);
 -d = FROM_SYSBUS(M48t59SysBusState, s);
 -state = &d->state;
 -sysbus_connect_irq(s, 0, IRQ);
 -memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4);
 -if (io_base != 0) {
 -memory_region_add_subregion(get_system_io(), io_base, &d->io);
 -}
 -if (mem_base != 0) {
 -sysbus_mmio_map(s, 0, mem_base);
 +for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 +if (!m48txx_info[i].sysbus_name ||
 +m48txx_info[i].size != size ||
 +m48txx_info[i].model != model) {
 +continue;
 +}
 +
 +dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
 +qdev_init_nofail(dev);
 +s = SYS_BUS_DEVICE(dev);
 +d = FROM_SYSBUS(M48t59SysBusState, s);
 +state = &d->state;
 +sysbus_connect_irq(s, 0, IRQ);
 +memory_region_init_io(&d->io, &m48t59_io_ops, stat

Re: [Qemu-devel] Target-agnostic virtio?

[Blue Swirl]

On Wed, Apr 17, 2013 at 2:15 AM, Rob Landley  wrote:
> On 04/14/2013 04:38:23 AM, Artyom Tarasenko wrote:
>>
>> On Sat, Apr 13, 2013 at 7:03 PM, Rob Landley  wrote:
>> > On 03/26/2013 02:34:50 AM, Artyom Tarasenko wrote:
>> >>
>> >> On Tue, Mar 26, 2013 at 1:52 AM, Rob Landley  wrote:
>> >> > Can the virtio things (serial, network, block, virtfs) be used on
>> >> > arbitrary
>> >> > targets yet? I.E. Can I use a virtio network device on arm, mips,
>> >> > powerpc,
>> >> > sparc...
>> >>
>> >> Yes. Moreover, for sparc64 the virtio network is currently the only
>> >> way to have a network under Linux guest (and a virtio block is the
>> >> only to have a disk under Linux guest).
>>
>> >
>> >
>> > Do you have an example kernel .config and qemu command line showing how
>> > to
>> > use virtio for those? (Or a working sparc64 image you can point me to?)
>>
>> Yes. Will send it to you as I get to my home machine. Can you make them
>> available on your site?
>
>
> I plan to add a sparc64 target built from source to Aboriginal Linux.
>
> For a lot of the 64-bit targets, actual 64 bit userspace support is
> strangely lacking. For ppc64 they say to use ppc32, and I've been told that
> about sparc64 as well. I don't know if this is an optimization or a
> requirement. I have a 32 bit image, I'd like to test the 64 bit codepaths as
> well...

It's a sort of optimization, the pointers are smaller. OpenBSD/sparc64
takes a different approach, every binary is 64 bits. Would it be hard
to make Aboriginal *BSD? ;-)

>
>
>> I have a Debian Wheezy RC1 / SPARC64 How-To, it would be nice to link to
>> the .config and kernel, so people would be able to install it just by
>> a few clicks.
>
>
> I have http://landley.net/aboriginal/about.html
>
> Rob
>

Re: [Qemu-devel] [RFC v2 3/7] m48t59: register a QOM type for each nvram type we support

[Artyom Tarasenko]

On Sat, Apr 20, 2013 at 11:34 AM, Blue Swirl  wrote:
> On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko  wrote:
>> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau  
>> wrote:
>>> As m48t59 devices can only be created with m48t59_init() or 
>>> m48t59_init_isa(),
>>> we know exactly which nvram types are required. Register only those three
>>> types.
>>> Remove .model and .size properties as they can be infered from nvram name.
>>> Remove .io_base ISA address port as m48t59_init_isa() is always called with 
>>> ioport 0x74.
>>
>> While this it indeed how it's currently called, this is wrong for the
>> sun4u emulation.
>> The isa (ebus) variant of the sun4u m48t59_init_isa() should be called
>> with a mem_base, not io_base.
>
> Why? I don't see much difference between EBUS and ISA and with the
> memory API, the difference between PIO and MMIO is almost nonexistent
> anyway.

Can you elaborate? Do you mean we just need to change the io_base?

> But it should be possible to change the base to match real HW, whatever it is:
> http://git.kernel.org/cgit/linux/kernel/git/davem/prtconfs.git/tree/ultra5#n273

Yes, I know where it is supposed to be, I'm just asking how to achieve
this best with our current tooling.

> So NACK for the original patch.
>
>> Do you think it should be implemented as another device type?
>>
>>
>>> Signed-off-by: Hervé Poussineau 
>>> ---
>>>  hw/timer/m48t59.c |  187 
>>> -
>>>  1 file changed, 126 insertions(+), 61 deletions(-)
>>>
>>> diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
>>> index 41022f2..29ec462 100644
>>> --- a/hw/timer/m48t59.c
>>> +++ b/hw/timer/m48t59.c
>>> @@ -43,6 +43,13 @@
>>>   * PPC platform there is also a nvram lock function.
>>>   */
>>>
>>> +typedef struct M48txxInfo {
>>> +const char *isa_name;
>>> +const char *sysbus_name;
>>> +uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
>>> +uint32_t size;
>>> +} M48txxInfo;
>>> +
>>>  /*
>>>   * Chipset docs:
>>>   * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
>>> @@ -54,7 +61,6 @@ struct M48t59State {
>>>  /* Hardware parameters */
>>>  qemu_irq IRQ;
>>>  MemoryRegion iomem;
>>> -uint32_t io_base;
>>>  uint32_t size;
>>>  /* RTC management */
>>>  time_t   time_offset;
>>> @@ -78,12 +84,39 @@ typedef struct M48t59ISAState {
>>>  MemoryRegion io;
>>>  } M48t59ISAState;
>>>
>>> +typedef struct M48txxISADeviceClass {
>>> +ISADeviceClass parent_class;
>>> +M48txxInfo info;
>>> +} M48txxISADeviceClass;
>>> +
>>>  typedef struct M48t59SysBusState {
>>>  SysBusDevice busdev;
>>>  M48t59State state;
>>>  MemoryRegion io;
>>>  } M48t59SysBusState;
>>>
>>> +typedef struct M48txxSysBusDeviceClass {
>>> +SysBusDeviceClass parent_class;
>>> +M48txxInfo info;
>>> +} M48txxSysBusDeviceClass;
>>> +
>>> +static M48txxInfo m48txx_info[] = {
>>> +{
>>> +.sysbus_name = "m48t02",
>>> +.model = 2,
>>> +.size = 0x800,
>>> +},{
>>> +.sysbus_name = "m48t08",
>>> +.model = 8,
>>> +.size = 0x2000,
>>> +},{
>>> +.isa_name = "m48t59_isa",
>>> +.model = 59,
>>> +.size = 0x2000,
>>> +}
>>> +};
>>> +
>>> +
>>>  /* Fake timer functions */
>>>
>>>  /* Alarm management */
>>> @@ -640,25 +673,34 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr 
>>> mem_base,
>>>  SysBusDevice *s;
>>>  M48t59SysBusState *d;
>>>  M48t59State *state;
>>> +int i;
>>>
>>> -dev = qdev_create(NULL, "m48t59");
>>> -qdev_prop_set_uint32(dev, "model", model);
>>> -qdev_prop_set_uint32(dev, "size", size);
>>> -qdev_prop_set_uint32(dev, "io_base", io_base);
>>> -qdev_init_nofail(dev);
>>> -s = SYS_BUS_DEVICE(dev);
>>> -d = FROM_SYSBUS(M48t59SysBusState, s);
>>> -state = &d->state;
>>> -sysbus_connect_irq(s, 0, IRQ);
>>> -memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4);
>>> -if (io_base != 0) {
>>> -memory_region_add_subregion(get_system_io(), io_base, &d->io);
>>> -}
>>> -if (mem_base != 0) {
>>> -sysbus_mmio_map(s, 0, mem_base);
>>> +for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
>>> +if (!m48txx_info[i].sysbus_name ||
>>> +m48txx_info[i].size != size ||
>>> +m48txx_info[i].model != model) {
>>> +continue;
>>> +}
>>> +
>>> +dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
>>> +qdev_init_nofail(dev);
>>> +s = SYS_BUS_DEVICE(dev);
>>> +d = FROM_SYSBUS(M48t59SysBusState, s);
>>> +state = &d->state;
>>> +sysbus_connect_irq(s, 0, IRQ);
>>> +memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4);
>>> +if (io_base != 0) {
>>> +memory_region_add_subregion(get_system_io(), io_base, &d->io);
>>> +}
>>> +if (mem_base != 0) {
>>> +sysbus_mmio_map(s, 0, mem_base);
>>> +  

Re: [Qemu-devel] [RFC v2 3/7] m48t59: register a QOM type for each nvram type we support

[Blue Swirl]

On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko  wrote:
> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau  
> wrote:
>> As m48t59 devices can only be created with m48t59_init() or 
>> m48t59_init_isa(),
>> we know exactly which nvram types are required. Register only those three
>> types.
>> Remove .model and .size properties as they can be infered from nvram name.
>> Remove .io_base ISA address port as m48t59_init_isa() is always called with 
>> ioport 0x74.
>
> While this it indeed how it's currently called, this is wrong for the
> sun4u emulation.
> The isa (ebus) variant of the sun4u m48t59_init_isa() should be called
> with a mem_base, not io_base.

Why? I don't see much difference between EBUS and ISA and with the
memory API, the difference between PIO and MMIO is almost nonexistent
anyway.

But it should be possible to change the base to match real HW, whatever it is:
http://git.kernel.org/cgit/linux/kernel/git/davem/prtconfs.git/tree/ultra5#n273

So NACK for the original patch.

> Do you think it should be implemented as another device type?
>
>
>> Signed-off-by: Hervé Poussineau 
>> ---
>>  hw/timer/m48t59.c |  187 
>> -
>>  1 file changed, 126 insertions(+), 61 deletions(-)
>>
>> diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
>> index 41022f2..29ec462 100644
>> --- a/hw/timer/m48t59.c
>> +++ b/hw/timer/m48t59.c
>> @@ -43,6 +43,13 @@
>>   * PPC platform there is also a nvram lock function.
>>   */
>>
>> +typedef struct M48txxInfo {
>> +const char *isa_name;
>> +const char *sysbus_name;
>> +uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
>> +uint32_t size;
>> +} M48txxInfo;
>> +
>>  /*
>>   * Chipset docs:
>>   * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
>> @@ -54,7 +61,6 @@ struct M48t59State {
>>  /* Hardware parameters */
>>  qemu_irq IRQ;
>>  MemoryRegion iomem;
>> -uint32_t io_base;
>>  uint32_t size;
>>  /* RTC management */
>>  time_t   time_offset;
>> @@ -78,12 +84,39 @@ typedef struct M48t59ISAState {
>>  MemoryRegion io;
>>  } M48t59ISAState;
>>
>> +typedef struct M48txxISADeviceClass {
>> +ISADeviceClass parent_class;
>> +M48txxInfo info;
>> +} M48txxISADeviceClass;
>> +
>>  typedef struct M48t59SysBusState {
>>  SysBusDevice busdev;
>>  M48t59State state;
>>  MemoryRegion io;
>>  } M48t59SysBusState;
>>
>> +typedef struct M48txxSysBusDeviceClass {
>> +SysBusDeviceClass parent_class;
>> +M48txxInfo info;
>> +} M48txxSysBusDeviceClass;
>> +
>> +static M48txxInfo m48txx_info[] = {
>> +{
>> +.sysbus_name = "m48t02",
>> +.model = 2,
>> +.size = 0x800,
>> +},{
>> +.sysbus_name = "m48t08",
>> +.model = 8,
>> +.size = 0x2000,
>> +},{
>> +.isa_name = "m48t59_isa",
>> +.model = 59,
>> +.size = 0x2000,
>> +}
>> +};
>> +
>> +
>>  /* Fake timer functions */
>>
>>  /* Alarm management */
>> @@ -640,25 +673,34 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>>  SysBusDevice *s;
>>  M48t59SysBusState *d;
>>  M48t59State *state;
>> +int i;
>>
>> -dev = qdev_create(NULL, "m48t59");
>> -qdev_prop_set_uint32(dev, "model", model);
>> -qdev_prop_set_uint32(dev, "size", size);
>> -qdev_prop_set_uint32(dev, "io_base", io_base);
>> -qdev_init_nofail(dev);
>> -s = SYS_BUS_DEVICE(dev);
>> -d = FROM_SYSBUS(M48t59SysBusState, s);
>> -state = &d->state;
>> -sysbus_connect_irq(s, 0, IRQ);
>> -memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4);
>> -if (io_base != 0) {
>> -memory_region_add_subregion(get_system_io(), io_base, &d->io);
>> -}
>> -if (mem_base != 0) {
>> -sysbus_mmio_map(s, 0, mem_base);
>> +for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
>> +if (!m48txx_info[i].sysbus_name ||
>> +m48txx_info[i].size != size ||
>> +m48txx_info[i].model != model) {
>> +continue;
>> +}
>> +
>> +dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
>> +qdev_init_nofail(dev);
>> +s = SYS_BUS_DEVICE(dev);
>> +d = FROM_SYSBUS(M48t59SysBusState, s);
>> +state = &d->state;
>> +sysbus_connect_irq(s, 0, IRQ);
>> +memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4);
>> +if (io_base != 0) {
>> +memory_region_add_subregion(get_system_io(), io_base, &d->io);
>> +}
>> +if (mem_base != 0) {
>> +sysbus_mmio_map(s, 0, mem_base);
>> +}
>> +
>> +return state;
>>  }
>>
>> -return state;
>> +assert(false);
>> +return NULL;
>>  }
>>
>>  M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
>> @@ -667,16 +709,27 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t 
>> io_base, uint16_t size,
>>  M48t59ISAState *d;
>>  ISADevice *dev;
>>  M48t59State