Re: [Qemu-devel] [PATCH] Update MAINTAINERS
Il 02/10/2013 19:53, Andreas Färber ha scritto: LSI53C895A -M: Paul Brook p...@codesourcery.com -S: Odd Fixes +S: Orphan F: hw/scsi/lsi53c895a.c SSI CC'ing Paolo as SCSI maintainer. I definitely don't object to this, but it's also fine to just remove the whole stanza. Paolo
Re: [Qemu-devel] cache=writeback and migrations over shared storage
On Thu, Sep 26, 2013 at 09:31:00AM +0200, Stefan Hajnoczi wrote: Hi Filippos, Late response but this may help start the discussion... Cache consistency during migration was discussed a lot on the mailing list. You might be able to find threads from about 2 years ago that discuss this in detail. Here is what I remember: During migration the QEMU process on the destination host must be started. When QEMU starts up it opens the image file and reads the first sector (for disk geometry and image format probing). At this point the destination would populate its page cache while the source is still running the guest. We're in trouble because the destination host has stale pages in its page cache. Hence the recommendation to use cache=none. There are a few things to look at if you are really eager to use cache=writeback: 1. Can you avoid geometry probing? I think by setting the geometry options on the -drive you can skip probing. See hw/block/hd-geometry.c. 2. Can you avoid format probing? Use -drive format=raw to skip format probing. 3. Make sure to use raw image files. Do not use a format since that would require reading a header and metadata before migration handover. 4. Check if ioctl(BLKFLSBUF) can be used. Unfortunately it requires CAP_SYS_ADMIN so the QEMU process cannot issue it when running without privileges. Perhaps an external tool like libvirt could issue it, but that's tricky since live migration handover is a delicate operation - it's important to avoided dependencies between multiple processes to keep guest downtime low and avoid possibility of failures. So you might be able to get away with cache=writeback *if* you carefully study the code and double-check with strace that the destination QEMU processes does not access the image file before handover has completed. Stefan Hi Stefan, Thanx for your response. You've been really helpful. I believe it should be possible to use writeback cache, if we address the problems you pointed out. I 'll give it a try by providing disk geometry and by using the raw drive format. I don't thing I need to use ioctl(BLKFLSBUF). As far as I can tell by looking briefly the kernel code, I see that it flushes the dirty pages of the device and invalidates the now clean pages. Since a) the source QEMU process flushes all block devices before handing control over to the destination process and b) we remove the block device after the migration, this should happen automatically. To be extra sure about this, I 'll run a modified qemu version to pause execution of the source hypervisor after the vm is stopped in the source and right before it hands control to the destination. I believe that this window exists after: vm_stop_force_state(RUN_STATE_FINISH_MIGRATE); and right before: qemu_savevm_state_complete(s-file); in the migration_thread in migration.c . I 'll be strace-ing the destination to make sure there are no reads issued on the block device. Plus our custom storage layer allows us to monitor all I/O requests that are performed to the block device, so we have another layer that ensures that no data were read from the storage. Kind Regards, -- Filippos philipg...@grnet.gr
Re: [Qemu-devel] [Qemu-trivial] [PATCH] migration: Fix compiler warning ('caps' may be used uninitialized)
Il 02/10/2013 22:24, Stefan Weil ha scritto:
Am 02.10.2013 21:02, schrieb Michael Tokarev:
MigrationCapabilityStatusList *qmp_query_migrate_capabilities(Error **errp)
{
MigrationCapabilityStatusList *head = NULL;
MigrationCapabilityStatusList *prev = NULL;
MigrationState *s = migrate_get_current();
MigrationCapability i;
for (i = 0; i MIGRATION_CAPABILITY_MAX; i++) {
MigrationCapabilityStatusList *caps =
g_new(MigrationCapabilityStatusList, 1);
if (prev == NULL) {
head = caps;
} else {
prev-next = caps;
prev = caps;
}
caps-value = g_new(MigrationCapabilityStatus, 1);
caps-value-capability = i;
caps-value-state = s-enabled_capabilities[i];
}
return head;
}
I dislike having head initialized to NULL.
Which one do we take? Any correct solution which fixes the compiler
warning is fine for me (although I prefer g_new instead of g_malloc as
you might have guessed). :-)
Mine uses g_new0 so it should work for you as well? :)
Paolo
Re: [Qemu-devel] 82574/82571 emulation?
Il 02/10/2013 22:36, akepner ha scritto: Hi qemu-devel; We're using qemu to emulate a platform that uses Intel 82574, and 82571 based NICs (which use the e1000e driver). AFAICT, an emulation of 82574/82571 devices is not available in qemu. Couple of questions: 1) is someone already working on a 82574/82571 emulation? (and if so, can you point me to a repo?) 2) would a 82574/82571 emulation be welcome into upstream qemu? There's no one working that I know of, but it would definitely be welcome. Paolo (This'd be the first intended-for-upstream qemu work I've done, so any other advice, or pointers that you have would be appreciated.) Thanks.
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
Il 03/10/2013 06:03, Lei Li ha scritto: Hi Paolo, When debugging the code, I realized that this problem might still exist. In the incoming part, it will qemu_fopen_pipe() in unix_accept_incoming_migration first to enable the load_hook callback, the check action of this RAM_SAVE_FLAG_HOOK flags would lead to 8 bytes taken. Turns out, it will break normal unix migration (without unix-page-flipping), because no matter normal unix migration or unix-page-flipping migration, the incoming side has to check this 8-byes flags first to decide whether the load_hook is called, and normal unix migration did not send this 8-byte flags. Why is the load_hook callback being called at all without page flipping? Without page flipping, the before_iterate and save_page hook will return immediately (or depending on your code they may never be called), so the RAM_SAVE_FLAG_HOOK will never be written to the Unix socket. I wonder if I didn't understand your suggestion correctly? Perhaps you want to discuss this tomorrow morning on #qemu? Paolo
[Qemu-devel] [PULL 1/2] target-openrisc: Correct handling of page faults.
From: Sebastian Macke sebast...@macke.de
The result of (rw 0) is always zero and therefore a logic false.
The whole comparison will therefore never be executed, it is a obvious bug,
we should use !(rw 1) here.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 57f5616..323a173 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
}
}
-if ((rw 0) ((right PAGE_READ) == 0)) {
+if (!(rw 1) ((right PAGE_READ) == 0)) {
return TLBRET_BADADDR;
}
if ((rw 1) ((right PAGE_WRITE) == 0)) {
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. This patch set correct two problems. The first one corrects one obvious bug concerning the handling of page faults while reading from a page. The second part removes a non-conforming behavior for the first page of the memory. Sebastian have tested this patch with the newest Linux kernel and compared the output with or1ksim. The following changes since commit a684f3cf9b9b9c3cb82be87aafc463de8974610c: Merge remote-tracking branch 'kraxel/seabios-1.7.3.2' into staging (2013-09-30 17:15:27 -0500) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 6ef8263ead779e1eecfaf1e0388f4c3941ea7ec3: target-openrisc: Removes a non-conforming behavior for the first page of the memory (2013-10-03 16:24:44 +0800) Sebastian Macke (2): target-openrisc: Correct handling of page faults. target-openrisc: Removes a non-conforming behavior for the first page of the memory target-openrisc/mmu.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-)
[Qemu-devel] [PULL 2/2] target-openrisc: Removes a non-conforming behavior for the first page of the memory
From: Sebastian Macke sebast...@macke.de
Where *software* leaves 0x - 0x2000 unmapped, the hardware should
still allow for this area to be mapped.
Signed-off-by: Sebastian Macke sebast...@macke.de
Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
Reviewed-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 323a173..22d7cbe 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
{
int ret = TLBRET_MATCH;
-/* [0x--0x2000]: unmapped */
-if (address 0x2000 (cpu-env.sr SR_SM)) {
-*physical = address;
-*prot = PAGE_READ | PAGE_WRITE;
-return ret;
-}
-
if (rw == 2) {/* ITLB */
*physical = 0;
ret = cpu-env.tlb-cpu_openrisc_map_address_code(cpu, physical,
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH 2/2] .gitmodules: use upstream SeaBIOS repo to fix submodule init
From: Alex Bennée a...@bennee.com Currently master is broken as the wanted commit doesn't exist in qemu's mirror of SeaBIOS. --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index d7e3f3c..d5d5417 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = git://git.qemu.org/vgabios.git/ [submodule roms/seabios] path = roms/seabios - url = git://git.qemu.org/seabios.git/ + url = git://git.seabios.org/seabios.git [submodule roms/SLOF] path = roms/SLOF url = git://git.qemu.org/SLOF.git -- 1.8.4
[Qemu-devel] [PATCH 1/2] .travis.yml: basic compile and check recipes
From: Alex Bennée a...@bennee.com
This adds a build matrix definition for travis-ci.org continuous
integration service. It is usable on any public repository hosted on
GitHub. Once you have created an account signed into Travis you can
enable it on selected projects via travis-ci.org/profile. Alternatively
you can configure the service hooks on GitHub via the repository
Settings tab,then Service Hooks and selecting Travis.
Once setup Travis will automatically test every push as well as any pull
requests submitted to that repository.
The build matrix is currently split by target architecture (see TARGETS
environment variable) because a full build of QEMU can take some time.
This way you get quick feedback for any obvious errors. The additional
environment variables exist to allow additional builds to tweak the
environment. These are:
EXTRA_CONFIG - extra terms passed to configure
EXTRA_PKGS - extra dev packages to install
TEST_CMD - default make check, can be overridden
I've confined the additional stuff to x86/x86_64 for convenience.
As Travis supports clang the main builds are done twice (once for gcc
and once for clang). However clang is disabled for the debug/trace
builds for the purposes of brevity.
Other wrinkles:
* The lttng user-space tracing back-end is disabled
(it is currently horribly broken)
* The ftrace back-end doesn't run make check
(it requires a mounted debugfs to work)
* There are two debug enabled build (with and without TCG interpreter)
Signed-off-by: Alex Bennée a...@bennee.com
Reviewed-by: Stefan Hajnoczi stefa...@redhat.com
---
.travis.yml | 69 +
1 file changed, 69 insertions(+)
create mode 100644 .travis.yml
diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 000..15d36b1
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,69 @@
+language: c
+compiler:
+ - gcc
+ - clang
+env:
+ global:
+- TEST_CMD=make check
+- EXTRA_CONFIG=
+# Development packages, EXTRA_PKGS saved for additional builds
+- CORE_PKGS=libusb-1.0-0-dev libiscsi-dev librados-dev libncurses5-dev
+- NET_PKGS=libseccomp-dev libgnutls-dev libssh2-1-dev
libspice-server-dev libspice-protocol-dev libnss3-dev
+- GUI_PKGS=libgtk-3-dev libvte-2.90-dev libsdl1.2-dev libpng12-dev
libpixman-1-dev
+- EXTRA_PKGS=
+ matrix:
+ - TARGETS=alpha-softmmu,alpha-linux-user
+ - TARGETS=arm-softmmu,arm-linux-user
+ - TARGETS=cris-softmmu
+ - TARGETS=i386-softmmu,x86_64-softmmu
+ - TARGETS=lm32-softmmu
+ - TARGETS=m68k-softmmu
+ - TARGETS=microblaze-softmmu,microblazeel-softmmu
+ - TARGETS=mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu
+ - TARGETS=moxie-softmmu
+ - TARGETS=or32-softmmu,
+ - TARGETS=ppc-softmmu,ppc64-softmmu,ppcemb-softmmu
+ - TARGETS=s390x-softmmu
+ - TARGETS=sh4-softmmu,sh4eb-softmmu
+ - TARGETS=sparc-softmmu,sparc64-softmmu
+ - TARGETS=unicore32-softmmu
+ - TARGETS=xtensa-softmmu,xtensaeb-softmmu
+before_install:
+ - git submodule update --init --recursive
+ - sudo apt-get update -qq
+ - sudo apt-get install -qq ${CORE_PKGS} ${NET_PKGS} ${GUI_PKGS} ${EXTRA_PKGS}
+script: ./configure --target-list=${TARGETS} ${EXTRA_CONFIG} make
${TEST_CMD}
+matrix:
+ # We manually include a number of additional build for non-standard bits
+ include:
+# Debug related options
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-debug
+ compiler: gcc
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-debug --enable-tcg-interpreter
+ compiler: gcc
+# Currently configure doesn't force --disable-pie
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-gprof --enable-gcov --disable-pie
+ compiler: gcc
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_PKGS=sparse
+ EXTRA_CONFIG=--enable-sparse
+ compiler: gcc
+# All the trace backends (apart from dtrace)
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-trace-backend=stderr
+ compiler: gcc
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-trace-backend=simple
+ compiler: gcc
+- env: TARGETS=i386-softmmu,x86_64-softmmu
+ EXTRA_CONFIG=--enable-trace-backend=ftrace
+ TEST_CMD=
+ compiler: gcc
+# This disabled make check for the ftrace backend which needs more setting
up
+# Currently broken on 12.04 due to mis-packaged liburcu and changed API,
will be pulled.
+#- env: TARGETS=i386-softmmu,x86_64-softmmu
+# EXTRA_PKGS=liblttng-ust-dev liburcu-dev
+# EXTRA_CONFIG=--enable-trace-backend=ust
--
1.8.4
[Qemu-devel] [PATCH v4 0/0] .travis.yml: basic compile and check recipies and minor fixes
Hi, While testing after Peter's review comments Travis detected a regression in the tree due to the updating of SeaBIOS (also found by a bunch of others in the following days) which I take to be a good indication of the usefulness of these tests. v4: - split debug build for with/without TCG interpreter - add simple patch to use SeaBIOS upstream repo - I've left ust commented out, there are patches to remove/replace it pending on the mailing list. Alex Bennée (2): .travis.yml: basic compile and check recipes .gitmodules: use upstream SeaBIOS repo to fix submodule init .gitmodules | 2 +- .travis.yml | 69 + 2 files changed, 70 insertions(+), 1 deletion(-)
Re: [Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote: Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. As this is a pull request, the patches in it need your Signed-off-by, not just Reviewed-by. thanks -- PMM
Re: [Qemu-devel] [PATCH 2/2] .gitmodules: use upstream SeaBIOS repo to fix submodule init
On 3 October 2013 17:58, alex.ben...@linaro.org wrote: From: Alex Bennée a...@bennee.com Currently master is broken as the wanted commit doesn't exist in qemu's mirror of SeaBIOS. --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index d7e3f3c..d5d5417 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = git://git.qemu.org/vgabios.git/ [submodule roms/seabios] path = roms/seabios - url = git://git.qemu.org/seabios.git/ + url = git://git.seabios.org/seabios.git This is wrong. QEMU's submodules should all point to git.qemu.org. Among other things our release source tarballs pull in the sources and it's a good way to ensure it's all consistent and we definitely have version controlled copies of the sources we release under our control rather than just in an external repo. What should actually happen is that Anthony should fix his workflow to ensure that he doesn't commit patches which update submodules without also updating the qemu.org mirrors of the external repos :-) -- PMM
Re: [Qemu-devel] [PATCH 2/2] .gitmodules: use upstream SeaBIOS repo to fix submodule init
peter.mayd...@linaro.org writes: On 3 October 2013 17:58, alex.ben...@linaro.org wrote: From: Alex Bennée a...@bennee.com Currently master is broken as the wanted commit doesn't exist in qemu's mirror of SeaBIOS. snip This is wrong. QEMU's submodules should all point to git.qemu.org. Among other things our release source tarballs pull in the sources and it's a good way to ensure it's all consistent and we definitely have version controlled copies of the sources we release under our control rather than just in an external repo. Fair enough, I'll drop the patch. What should actually happen is that Anthony should fix his workflow to ensure that he doesn't commit patches which update submodules without also updating the qemu.org mirrors of the external repos :-) Of course once this is merged it will flag up the problem right away (even sooner if the pull request is a github one ;-) -- Alex Bennée
[Qemu-devel] [PATCH] target-arm: Implement ARMv8 VSEL instruction.
This adds support for the VSEL floating point selection instruction
which was added in ARMv8. It is based on the previous patch[1] from
Mans Rullgard, but attempts to addres the feedback given on that patch.
[1] http://lists.nongnu.org/archive/html/qemu-devel/2013-06/msg03117.html
Signed-off-by: Will Newton will.new...@linaro.org
---
target-arm/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..7bfd606 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2617,6 +2617,114 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s,
TCGv_i32 addr, int size)
return tmp;
}
+static int disas_v8vfp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
+{
+uint32_t rd, rn, rm, dp = (insn 8) 1;
+
+if (!s-vfp_enabled)
+ return 1;
+
+if (dp) {
+VFP_DREG_D(rd, insn);
+VFP_DREG_N(rn, insn);
+VFP_DREG_M(rm, insn);
+} else {
+rd = VFP_SREG_D(insn);
+rn = VFP_SREG_N(insn);
+rm = VFP_SREG_M(insn);
+}
+
+if (((insn 23) 1) == 0) {
+/* vsel */
+uint32_t cc = (insn 20) 3;
+ TCGv_i32 tmp, zero;
+
+ zero = tcg_const_tl(0);
+
+ if (dp) {
+ TCGv_i64 ftmp1, ftmp2, ftmp3;
+
+ ftmp1 = tcg_temp_new_i64();
+ ftmp2 = tcg_temp_new_i64();
+ ftmp3 = tcg_temp_new_i64();
+ tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+ tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+ switch (cc) {
+ case 0: /* eq: Z */
+ tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ ftmp1, ftmp2);
+ break;
+ case 1: /* vs: V */
+ tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ ftmp1, ftmp2);
+ break;
+ case 2: /* ge: N == V - N ^ V == 0 */
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ ftmp1, ftmp2);
+ tcg_temp_free_i32(tmp);
+ break;
+ case 3: /* gt: !Z N == V */
+ tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ ftmp1, ftmp2);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ ftmp3, ftmp2);
+ tcg_temp_free_i32(tmp);
+ break;
+ }
+ tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+ tcg_temp_free_i64(ftmp1);
+ tcg_temp_free_i64(ftmp2);
+ tcg_temp_free_i64(ftmp3);
+ } else {
+ TCGv_i32 ftmp1, ftmp2, ftmp3;
+
+ ftmp1 = tcg_temp_new_i32();
+ ftmp2 = tcg_temp_new_i32();
+ ftmp3 = tcg_temp_new_i32();
+ tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+ tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+ switch (cc) {
+ case 0: /* eq: Z */
+ tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ ftmp1, ftmp2);
+ break;
+ case 1: /* vs: V */
+ tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ ftmp1, ftmp2);
+ break;
+ case 2: /* ge: N == V - N ^ V == 0 */
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ ftmp1, ftmp2);
+ tcg_temp_free_i32(tmp);
+ break;
+ case 3: /* gt: !Z N == V */
+ tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ ftmp1, ftmp2);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ ftmp3, ftmp2);
+ tcg_temp_free_i32(tmp);
+ break;
+ }
+ tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+ tcg_temp_free_i32(ftmp1);
+ tcg_temp_free_i32(ftmp2);
+ tcg_temp_free_i32(ftmp3);
+ }
+
+return 0;
+}
+
+return 1;
+}
+
/* Disassemble a VFP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
@@ -6756,6 +6864,13 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
goto illegal_op;
return;
Re: [Qemu-devel] [PATCH v3 uq/master 2/2] x86: cpuid: reconstruct leaf 0Dh data
On Wed, 2 Oct 2013 17:54:57 +0200
Paolo Bonzini pbonz...@redhat.com wrote:
The data in leaf 0Dh depends on information from other feature bits.
Instead of passing it blindly from the host, compute it based on
whether these feature bits are enabled.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-i386/cpu.c | 65
---
1 file changed, 48 insertions(+), 17 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ac83106..1addb18 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -328,6 +328,15 @@ X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
};
#undef REGISTER
+typedef struct ExtSaveArea {
+uint32_t feature, bits;
+uint32_t offset, size;
+} ExtSaveArea;
+
+static const ExtSaveArea ext_save_areas[] = {
+[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
+.offset = 0x100, .size = 0x240 },
+};
const char *get_register_name_32(unsigned int reg)
{
@@ -2169,29 +2178,51 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = 0;
}
break;
-case 0xD:
+case 0xD: {
+KVMState *s = cs-kvm_state;
+uint64_t kvm_mask;
+int i;
+
/* Processor Extended State */
-if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE)) {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE) ||
!kvm_enabled()) {
break;
}
-if (kvm_enabled()) {
-KVMState *s = cs-kvm_state;
+kvm_mask =
+kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
+((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) 32);
calling kvm_arch_get_supported_cpuid() without kvm_enabled() guard
could regress TCG mode on non KVM host:
kvm_arch_get_supported_cpuid - get_supported_cpuid - try_get_cpuid -
r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
...
if (r 0) {
if (r == -E2BIG) {
g_free(cpuid);
return NULL;
} else {
fprintf(stderr, KVM_GET_SUPPORTED_CPUID failed: %s\n,
strerror(-r));
exit(1);
^ guest suddenly dies
-*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
-*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
-*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
-*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
-} else {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+if (count == 0) {
+*ecx = 0x240;
+for (i = 2; i ARRAY_SIZE(ext_save_areas); i++) {
+const ExtSaveArea *esa = ext_save_areas[i];
+if ((env-features[esa-feature] esa-bits) == esa-bits
+(kvm_mask (1 i)) != 0) {
+if (i 32) {
+*eax |= 1 i;
+} else {
+*edx |= 1 (i - 32);
+}
+*ecx = MAX(*ecx, esa-offset + esa-size);
+}
+}
+*eax |= kvm_mask (XSTATE_FP | XSTATE_SSE);
+*ebx = *ecx;
+} else if (count == 1) {
+*eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
+} else if (count ARRAY_SIZE(ext_save_areas)) {
+const ExtSaveArea *esa = ext_save_areas[count];
+if ((env-features[esa-feature] esa-bits) == esa-bits
+(kvm_mask (1 count)) != 0) {
+*eax = esa-offset;
+*ebx = esa-size;
+}
}
break;
+}
case 0x8000:
*eax = env-cpuid_xlevel;
*ebx = env-cpuid_vendor1;
Re: [Qemu-devel] [PATCH v3 uq/master 2/2] x86: cpuid: reconstruct leaf 0Dh data
On Thu, Oct 03, 2013 at 11:59:24AM +0200, Igor Mammedov wrote:
On Wed, 2 Oct 2013 17:54:57 +0200
Paolo Bonzini pbonz...@redhat.com wrote:
The data in leaf 0Dh depends on information from other feature bits.
Instead of passing it blindly from the host, compute it based on
whether these feature bits are enabled.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-i386/cpu.c | 65
---
1 file changed, 48 insertions(+), 17 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ac83106..1addb18 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -328,6 +328,15 @@ X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
};
#undef REGISTER
+typedef struct ExtSaveArea {
+uint32_t feature, bits;
+uint32_t offset, size;
+} ExtSaveArea;
+
+static const ExtSaveArea ext_save_areas[] = {
+[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
+.offset = 0x100, .size = 0x240 },
+};
const char *get_register_name_32(unsigned int reg)
{
@@ -2169,29 +2178,51 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t
index, uint32_t count,
*edx = 0;
}
break;
-case 0xD:
+case 0xD: {
+KVMState *s = cs-kvm_state;
+uint64_t kvm_mask;
+int i;
+
/* Processor Extended State */
-if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE)) {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE) ||
!kvm_enabled()) {
break;
}
-if (kvm_enabled()) {
-KVMState *s = cs-kvm_state;
+kvm_mask =
+kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
+((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX)
32);
calling kvm_arch_get_supported_cpuid() without kvm_enabled() guard
could regress TCG mode on non KVM host:
But there is kvm_enabled() guard above.
kvm_arch_get_supported_cpuid - get_supported_cpuid - try_get_cpuid -
r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
...
if (r 0) {
if (r == -E2BIG) {
g_free(cpuid);
return NULL;
} else {
fprintf(stderr, KVM_GET_SUPPORTED_CPUID failed: %s\n,
strerror(-r));
exit(1);
^ guest suddenly dies
-*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
-*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
-*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
-*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
-} else {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+if (count == 0) {
+*ecx = 0x240;
+for (i = 2; i ARRAY_SIZE(ext_save_areas); i++) {
+const ExtSaveArea *esa = ext_save_areas[i];
+if ((env-features[esa-feature] esa-bits) == esa-bits
+(kvm_mask (1 i)) != 0) {
+if (i 32) {
+*eax |= 1 i;
+} else {
+*edx |= 1 (i - 32);
+}
+*ecx = MAX(*ecx, esa-offset + esa-size);
+}
+}
+*eax |= kvm_mask (XSTATE_FP | XSTATE_SSE);
+*ebx = *ecx;
+} else if (count == 1) {
+*eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
+} else if (count ARRAY_SIZE(ext_save_areas)) {
+const ExtSaveArea *esa = ext_save_areas[count];
+if ((env-features[esa-feature] esa-bits) == esa-bits
+(kvm_mask (1 count)) != 0) {
+*eax = esa-offset;
+*ebx = esa-size;
+}
}
break;
+}
case 0x8000:
*eax = env-cpuid_xlevel;
*ebx = env-cpuid_vendor1;
--
Gleb.
Re: [Qemu-devel] [PATCH v3 uq/master 2/2] x86: cpuid: reconstruct leaf 0Dh data
On Thu, 3 Oct 2013 13:01:54 +0300
Gleb Natapov g...@redhat.com wrote:
On Thu, Oct 03, 2013 at 11:59:24AM +0200, Igor Mammedov wrote:
On Wed, 2 Oct 2013 17:54:57 +0200
Paolo Bonzini pbonz...@redhat.com wrote:
The data in leaf 0Dh depends on information from other feature bits.
Instead of passing it blindly from the host, compute it based on
whether these feature bits are enabled.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-i386/cpu.c | 65
---
1 file changed, 48 insertions(+), 17 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ac83106..1addb18 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -328,6 +328,15 @@ X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
};
#undef REGISTER
+typedef struct ExtSaveArea {
+uint32_t feature, bits;
+uint32_t offset, size;
+} ExtSaveArea;
+
+static const ExtSaveArea ext_save_areas[] = {
+[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
+.offset = 0x100, .size = 0x240 },
+};
const char *get_register_name_32(unsigned int reg)
{
@@ -2169,29 +2178,51 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t
index, uint32_t count,
*edx = 0;
}
break;
-case 0xD:
+case 0xD: {
+KVMState *s = cs-kvm_state;
+uint64_t kvm_mask;
+int i;
+
/* Processor Extended State */
-if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE)) {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+if (!(env-features[FEAT_1_ECX] CPUID_EXT_XSAVE) ||
!kvm_enabled()) {
break;
}
-if (kvm_enabled()) {
-KVMState *s = cs-kvm_state;
+kvm_mask =
+kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
+((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX)
32);
calling kvm_arch_get_supported_cpuid() without kvm_enabled() guard
could regress TCG mode on non KVM host:
But there is kvm_enabled() guard above.
Ah, I'm sorry for noise. I've not noticed it in previous hunk.
kvm_arch_get_supported_cpuid - get_supported_cpuid - try_get_cpuid -
r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
...
if (r 0) {
if (r == -E2BIG) {
g_free(cpuid);
return NULL;
} else {
fprintf(stderr, KVM_GET_SUPPORTED_CPUID failed: %s\n,
strerror(-r));
exit(1);
^ guest suddenly dies
-*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
-*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
-*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
-*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
-} else {
-*eax = 0;
-*ebx = 0;
-*ecx = 0;
-*edx = 0;
+if (count == 0) {
+*ecx = 0x240;
+for (i = 2; i ARRAY_SIZE(ext_save_areas); i++) {
+const ExtSaveArea *esa = ext_save_areas[i];
+if ((env-features[esa-feature] esa-bits) ==
esa-bits
+(kvm_mask (1 i)) != 0) {
+if (i 32) {
+*eax |= 1 i;
+} else {
+*edx |= 1 (i - 32);
+}
+*ecx = MAX(*ecx, esa-offset + esa-size);
+}
+}
+*eax |= kvm_mask (XSTATE_FP | XSTATE_SSE);
+*ebx = *ecx;
+} else if (count == 1) {
+*eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
+} else if (count ARRAY_SIZE(ext_save_areas)) {
+const ExtSaveArea *esa = ext_save_areas[count];
+if ((env-features[esa-feature] esa-bits) == esa-bits
+(kvm_mask (1 count)) != 0) {
+*eax = esa-offset;
+*ebx = esa-size;
+}
}
break;
+}
case 0x8000:
*eax = env-cpuid_xlevel;
*ebx = env-cpuid_vendor1;
--
Gleb.
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
On 10/03/2013 04:23 PM, Paolo Bonzini wrote:
Il 03/10/2013 06:03, Lei Li ha scritto:
Hi Paolo,
When debugging the code, I realized that this problem might still
exist. In the incoming part, it will qemu_fopen_pipe() in
unix_accept_incoming_migration first to enable the load_hook
callback, the check action of this RAM_SAVE_FLAG_HOOK flags would
lead to 8 bytes taken. Turns out, it will break normal unix
migration (without unix-page-flipping), because no matter normal unix
migration or unix-page-flipping migration, the incoming side has to
check this 8-byes flags first to decide whether the load_hook is
called, and normal unix migration did not send this 8-byte flags.
Why is the load_hook callback being called at all without page flipping?
Without page flipping, the before_iterate and save_page hook will
return immediately (or depending on your code they may never be called),
so the RAM_SAVE_FLAG_HOOK will never be written to the Unix socket.
The load_hook callback is only be called if the RAM_SAVE_FLAG_HOOK is received.
To check this flags, it means there would be a check action first in
unix_accept_incoming_migration(), like:
f = qemu_fopen_pipe(c, rb);
flags = qemu_get_be64(f);
if (flags == RAM_SAVE_FLAG_HOOK) {
load_hook();
...
}
Otherwise, the incoming side has no idea whether the special 8-bytes record
(RAM_SAVE_FLAG_HOOK) is sent.
In unix-page-flipping migration, it is OK. Without page flipping, since the
RAM_SAVE_FLAG_HOOK is not be written to the Unix socket, but the incoming
side will still check it, that will lead to the unexpected 8-bytes taken.
If the logic and the way to deal with it above is correct according to your
suggestion, how about:
1) Use another Unix socket to deal with this flags and pipe fd passing.
or 2) Use a new prefix URI for the incoming.
I wonder if I didn't understand your suggestion correctly?
Perhaps you want to discuss this tomorrow morning on #qemu?
I joined the #qemu channel just now, seems you were not there.
I guess it's your lunch time right now. :)
Paolo
--
Lei
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
Il 03/10/2013 12:28, Lei Li ha scritto:
The load_hook callback is only be called if the RAM_SAVE_FLAG_HOOK is
received.
To check this flags, it means there would be a check action first in
unix_accept_incoming_migration(), like:
f = qemu_fopen_pipe(c, rb);
flags = qemu_get_be64(f);
if (flags == RAM_SAVE_FLAG_HOOK) {
load_hook();
...
}
Otherwise, the incoming side has no idea whether the special 8-bytes record
(RAM_SAVE_FLAG_HOOK) is sent.
No, ram_load is taking care of checking for RAM_SAVE_FLAG_HOOK. If
before_iterate writes the 8 bytes (followed by passing the fd for the
pipe's read-side via SCM_RIGHTS), ram_load will call load_hook before it
loads any page and load_hook will fetch the fd.
Subsequent calls to load_hook will match data written by the sender's
save_page hook (so they contain a RAM address, with the 4k page data
sent on the pipe).
Paolo
Re: [Qemu-devel] [PATCH] target-arm: Implement ARMv8 VSEL instruction.
will.new...@linaro.org writes:
snip
@@ -6756,6 +6864,13 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
goto illegal_op;
return;
}
+ if ((insn 0x0f800e50) == 0x0e000a00) {
+ /* ARMv8 VFP. */
+ ARCH(8);
+
+ if (disas_v8vfp_insn(env, s, insn))
+ goto illegal_op;
+ }
if (((insn 0x0f30f000) == 0x0510f000) ||
((insn 0x0f30f010) == 0x0710f000)) {
if ((insn (1 22)) == 0) {
@@ -8768,6 +8883,12 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
insn = (insn 0xe2ff) | ((insn (1 28)) 4) | (1
28);
if (disas_neon_data_insn(env, s, insn))
goto illegal_op;
+ } else if ((insn 0x0f800e50) == 0x0e000a00) {
+ /* ARMv8 VFP. */
+ ARCH(8);
+
+ if (disas_v8vfp_insn(env, s, insn))
+ goto illegal_op;
} else {
if (insn (1 28))
goto illegal_op;
I wonder is there a better way to deal with these masks for checking
instruction type? I only mention it because the same constant is used
twice and should it ever be changed there is a risk of one being missed
(although conceivably thumb encoding could be different?).
I appreciate the disassembler code is already a mass of magic constants
so it's not a major thing for me.
Cheers,
--
Alex Bennée
Re: [Qemu-devel] [PULL 8/8] tcg-arm: Move the tlb addend load earlier
r...@twiddle.net writes: There are free scheduling slots between the sequence of comparison instructions. This requires changing the register in use to avoid conflict with those compares. Signed-off-by: Richard Henderson r...@twiddle.net snip Looks good to me. Reviewed-by: Alex Bennée a...@bennee.com -- Alex Bennée
[Qemu-devel] Qemu -gdb stdio option for mingw32 ?
Hi, Does QEMU support gdb connection through stdio/pipe in mingw32 ? Thanks, -Bilal
Re: [Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
Hi Peter, On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote: Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. As this is a pull request, the patches in it need your Signed-off-by, not just Reviewed-by. Thank you for mention. thanks -- PMM Regards, Jia
Re: [Qemu-devel] [Xen-devel] [RFC PATCH] vga: Start supporting resolution not multiple of 16 correctly.
Il 25/09/2013 18:12, Pasi Kärkkäinen ha scritto:
On Sun, Jul 28, 2013 at 05:56:01PM +0100, Frediano Ziglio wrote:
2013/7/23 Gerd Hoffmann [1]kra...@redhat.com
 Hi,
Tested-by: Fabio Fantoni [2]fabio.fant...@m2r.biz
I tested it for a long time with spice on xen (because qxl will be
fully
working only after adding SSE support on hvm domUs). It works, I think
it is good to add this and the respective vgabios patch on upstream.
     case VBE_DISPI_INDEX_XRES:
- Â Â Â Â Â Â if ((val = VBE_DISPI_MAX_XRES) ((val 7) ==
0)) {
+ Â Â Â Â Â Â if ((val = VBE_DISPI_MAX_XRES) ((val 1) ==
0)) {
         s-vbe_regs[s-vbe_index] = val;
       }
       break;
It's not that simple. Â With 32bit depths common today it will work
fine,
but for lower depths (especially those lower than 8bit) this will give
you broken scanline alignment.
cheers,
 Gerd
In the card I tested the scanline is keep aligned but for this reason is
not directly computed by maxx * bits but is something bigger.
Hmm.. so is an update needed for this patch? It'd be nice to get this patch in!
Ping
Some statistics for evidence the importance to add support for 1366x768
and other resolutions:
http://www.rapidtables.com/web/dev/screen-resolution-statistics.htm
http://www.geek.com/chips/most-popular-screen-resolution-increases-to-1366-x-768-1482311/
-- Pasi
Frediano
___
Xen-devel mailing list
xen-de...@lists.xen.org
http://lists.xen.org/xen-devel
Re: [Qemu-devel] [PATCH] target-arm: Implement ARMv8 VSEL instruction.
On 3 October 2013 20:31, Alex Bennée alex.ben...@linaro.org wrote:
will.new...@linaro.org writes:
snip
@@ -6756,6 +6864,13 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
goto illegal_op;
return;
}
+ if ((insn 0x0f800e50) == 0x0e000a00) {
+ /* ARMv8 VFP. */
+ ARCH(8);
+
+ if (disas_v8vfp_insn(env, s, insn))
+ goto illegal_op;
+ }
if (((insn 0x0f30f000) == 0x0510f000) ||
((insn 0x0f30f010) == 0x0710f000)) {
if ((insn (1 22)) == 0) {
@@ -8768,6 +8883,12 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
insn = (insn 0xe2ff) | ((insn (1 28)) 4) | (1
28);
if (disas_neon_data_insn(env, s, insn))
goto illegal_op;
+ } else if ((insn 0x0f800e50) == 0x0e000a00) {
+ /* ARMv8 VFP. */
+ ARCH(8);
+
+ if (disas_v8vfp_insn(env, s, insn))
+ goto illegal_op;
} else {
if (insn (1 28))
goto illegal_op;
I wonder is there a better way to deal with these masks for checking
instruction type? I only mention it because the same constant is used
twice and should it ever be changed there is a risk of one being missed
(although conceivably thumb encoding could be different?).
The v8 ARM ARM actually integrates this new instruction into the
decode tables for the existing VFP insns (it's an entry in table F5-16
'three register data floating point instructions'), which makes me wonder
if we should put the decode into the existing disas_vfp_insn()...
-- PMM
Re: [Qemu-devel] [PULL 4/8] tcg-arm: Use QEMU_BUILD_BUG_ON to verifyconstraints on tlbb
r...@twiddle.net writes: One of the two constraints we already checked via #if, but the tlb offset distance was only checked at runtime. Signed-off-by: Richard Henderson r...@twiddle.net snip Reviewed-by: Alex Bennée a...@bennee.com -- Alex Bennée
[Qemu-devel] [Bug 1234179] Re: QEMU segfaults during Windows 7 unattended install
Good point, I've just changed the configure line to include --enable- debug. About the relation of the crash with the top commit, We can't ensure it was because of this top commit, could be other patches that were applied from one day to another. We only test qemu.git once a day, we don't have enough resources to test commit per commit. Also, this crash apparently is not 100% reproducible. Today's jobs did not have it, for instance. I guess we don't have enough information about the crash, given that I did not enable debug symbols. I'm fine with closing this issue, if I see it again, I can reopen it and hopefully this time we'll have a more useful bt full report. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1234179 Title: QEMU segfaults during Windows 7 unattended install Status in QEMU: New Bug description: During today's automated qemu.git testing, a segmentation fault while installing Windows 7 SP1 happened. qemu.git top commit: 10/02 01:30:24 INFO | git:0150| git commit ID is a684f3cf9b9b9c3cb82be87aafc463de8974610c (tag v1.4.0-4237-ga684f3c) commit a684f3cf9b9b9c3cb82be87aafc463de8974610c Merge: 349cd52 1cf9412 Author: Anthony Liguori anth...@codemonkey.ws Date: Mon Sep 30 17:15:27 2013 -0500 Merge remote-tracking branch 'kraxel/seabios-1.7.3.2' into staging # By Gerd Hoffmann # Via Gerd Hoffmann * kraxel/seabios-1.7.3.2: update seabios from 1.7.2.2 to 1.7.3.2 Message-id: 1380533055-24960-1-git-send-email-kra...@redhat.com We have the core file saved in our test servers, we can make arrangements to transfer it if there's someone interested in investigating further. The framework saved the 'bt full' of the core file, that was missing some debug info: [Thread debugging using libthread_db enabled] Using host libthread_db library /lib64/libthread_db.so.1. Core was generated by `/usr/local/autotest/tests/virt/qemu/qemu -S -name virt-tests-vm1 -M pc -nodefau'. Program terminated with signal 11, Segmentation fault. #0 0x7ffc8fb86cf0 in pixman_image_get_data () from /lib64/libpixman-1.so.0 #0 0x7ffc8fb86cf0 in pixman_image_get_data () from /lib64/libpixman-1.so.0 No symbol table info available. #1 0x7ffc9165b05c in ?? () No symbol table info available. #2 0x7ffc9382b540 in ?? () No symbol table info available. #3 0x7ffc8f359a8d in clock_gettime () from /lib64/libc.so.6 No symbol table info available. #4 0x7ffc9382b5a8 in ?? () No symbol table info available. #5 0x00019382b4c0 in ?? () No symbol table info available. #6 0x in ?? () No symbol table info available. Extra info: Commits for the submodules: 10/02 01:30:29 DEBUG|base_utils:0134| [stdout] Submodule path 'dtc': checked out 'bc895d6d09695d05ceb8b52486ffe861d6cfbdde' 10/02 01:30:51 DEBUG|base_utils:0134| [stdout] Submodule path 'pixman': checked out '97336fad32acf802003855cd8bd6477fa49a12e3' 10/02 01:30:58 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/SLOF': checked out '8cfdfc43f4c4c8c8dfa4b7cf16f7c19c84eee812' 10/02 01:31:16 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/ipxe': checked out '09c5109b8585178172c7608de8d52e9d9af0b680' 10/02 01:31:20 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/openbios': checked out '0f3d51ef22ec9166beb3ed434d253029ed7cfe84' 10/02 01:31:21 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/qemu-palcode': checked out 'c87a92639b28ac42bc8f6c67443543b405dc479b' 10/02 01:31:27 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/seabios': checked out 'ece025f5980bae88fa677bc9c0d24d2e580e205d' 10/02 01:31:28 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/sgabios': checked out '23d474943dcd55d0550a3d20b3d30e9040a4f15b' 10/02 01:31:31 DEBUG|base_utils:0134| [stdout] Submodule path 'roms/vgabios': checked out '19ea12c230ded95928ecaef0db47a82231c2e485' Configure options: 10/02 01:31:32 DEBUG|base_utils:0099| Running '/usr/local/autotest/tmp/virt/src/qemu/configure --target-list=x86_64-softmmu --disable-strip --prefix=/usr/local/autotest/tests/virt/qemu/install_root' 10/02 01:31:35 DEBUG|env_proces:0829| (address cache) DHCP lease OK: 00:30:48:c5:d6:e2 -- 10.16.72.38 10/02 01:31:40 DEBUG|base_utils:0134| [stdout] Install prefix /usr/local/autotest/tests/virt/qemu/install_root 10/02 01:31:40 DEBUG|base_utils:0134| [stdout] BIOS directory /usr/local/autotest/tests/virt/qemu/install_root/share/qemu 10/02 01:31:40 DEBUG|base_utils:0134| [stdout] binary directory /usr/local/autotest/tests/virt/qemu/install_root/bin 10/02 01:31:40 DEBUG|base_utils:0134| [stdout] library directory /usr/local/autotest/tests/virt/qemu/install_root/lib 10/02 01:31:40 DEBUG|base_utils:0134| [stdout] libexec directory /usr/local/autotest/tests/virt/qemu/install_root/libexec
[Qemu-devel] Emulation of Sp805 watch dog timer
Hi, I need to test the ARM's sp805 based watch dog timer from the qemu. But the model SP805 is not present in the qemu-1.5.93 source. Is there any possibility to add the SP805 based watch dog timer module to the Qemu. Please any one guide me. Thanks balaji
[Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
This adds support for the VSEL floating point selection instruction
which was added in ARMv8. It is based on the previous patch[1] from
Mans Rullgard, but attempts to address the feedback given on that patch.
[1] http://lists.nongnu.org/archive/html/qemu-devel/2013-06/msg03117.html
Signed-off-by: Will Newton will.new...@linaro.org
---
target-arm/translate.c | 105 +
1 file changed, 105 insertions(+)
Changes in v2:
- Integrate vsel decoding into disas_vfp_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5e49334 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2880,6 +2880,98 @@ static int disas_vfp_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
rm = VFP_SREG_M(insn);
}
+if ((insn 0x0f800e50) == 0x0e000a00) {
+/* vsel */
+uint32_t cc = (insn 20) 3;
+TCGv_i32 tmp, zero;
+
+/* ARMv8 VFP. */
+if (!arm_feature(env, ARM_FEATURE_V8))
+return 1;
+
+zero = tcg_const_tl(0);
+
+if (dp) {
+TCGv_i64 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i64();
+ftmp2 = tcg_temp_new_i64();
+ftmp3 = tcg_temp_new_i64();
+tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+tcg_temp_free_i64(ftmp1);
+tcg_temp_free_i64(ftmp2);
+tcg_temp_free_i64(ftmp3);
+} else {
+TCGv_i32 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i32();
+ftmp2 = tcg_temp_new_i32();
+ftmp3 = tcg_temp_new_i32();
+tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 3 October 2013 21:51, Will Newton will.new...@linaro.org wrote:
This adds support for the VSEL floating point selection instruction
which was added in ARMv8. It is based on the previous patch[1] from
Mans Rullgard, but attempts to address the feedback given on that patch.
[1] http://lists.nongnu.org/archive/html/qemu-devel/2013-06/msg03117.html
This sort of commentary about previous patch versions should go below
the '---', not in the commit message.
Signed-off-by: Will Newton will.new...@linaro.org
---
target-arm/translate.c | 105
+
1 file changed, 105 insertions(+)
Changes in v2:
- Integrate vsel decoding into disas_vfp_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5e49334 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2880,6 +2880,98 @@ static int disas_vfp_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
rm = VFP_SREG_M(insn);
}
+if ((insn 0x0f800e50) == 0x0e000a00) {
+/* vsel */
+uint32_t cc = (insn 20) 3;
+TCGv_i32 tmp, zero;
+
+/* ARMv8 VFP. */
+if (!arm_feature(env, ARM_FEATURE_V8))
+return 1;
scripts/checkpatch.pl will tell you that omitting the braces
is a coding style violation.
+
+zero = tcg_const_tl(0);
+
+if (dp) {
+TCGv_i64 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i64();
+ftmp2 = tcg_temp_new_i64();
+ftmp3 = tcg_temp_new_i64();
+tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+tcg_temp_free_i64(ftmp1);
+tcg_temp_free_i64(ftmp2);
+tcg_temp_free_i64(ftmp3);
+} else {
+TCGv_i32 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i32();
+ftmp2 = tcg_temp_new_i32();
+ftmp3 = tcg_temp_new_i32();
+tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+
[Qemu-devel] [PATCH v7 02/26] qom: cleanup struct Error references
now that a typedef for struct Error is available, use it in qom/object.h to match coding style rules. Reviewed-by: Paolo Bonzini pbonz...@redhat.com Reviewed-by: Gerd Hoffmann kra...@redhat.com Tested-by: Gerd Hoffmann kra...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/qom/object.h | 50 +- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/include/qom/object.h b/include/qom/object.h index d9a0063..6c1e7d3 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -301,7 +301,7 @@ typedef void (ObjectPropertyAccessor)(Object *obj, struct Visitor *v, void *opaque, const char *name, - struct Error **errp); + Error **errp); /** * ObjectPropertyRelease: @@ -790,9 +790,9 @@ void object_property_add(Object *obj, const char *name, const char *type, ObjectPropertyAccessor *get, ObjectPropertyAccessor *set, ObjectPropertyRelease *release, - void *opaque, struct Error **errp); + void *opaque, Error **errp); -void object_property_del(Object *obj, const char *name, struct Error **errp); +void object_property_del(Object *obj, const char *name, Error **errp); /** * object_property_find: @@ -803,7 +803,7 @@ void object_property_del(Object *obj, const char *name, struct Error **errp); * Look up a property for an object and return its #ObjectProperty if found. */ ObjectProperty *object_property_find(Object *obj, const char *name, - struct Error **errp); + Error **errp); void object_unparent(Object *obj); @@ -818,7 +818,7 @@ void object_unparent(Object *obj); * Reads a property from a object. */ void object_property_get(Object *obj, struct Visitor *v, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_str: @@ -829,7 +829,7 @@ void object_property_get(Object *obj, struct Visitor *v, const char *name, * Writes a string value to a property. */ void object_property_set_str(Object *obj, const char *value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_str: @@ -842,7 +842,7 @@ void object_property_set_str(Object *obj, const char *value, * The caller should free the string. */ char *object_property_get_str(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_link: @@ -853,7 +853,7 @@ char *object_property_get_str(Object *obj, const char *name, * Writes an object's canonical path to a property. */ void object_property_set_link(Object *obj, Object *value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_link: @@ -866,7 +866,7 @@ void object_property_set_link(Object *obj, Object *value, * string or not a valid object path). */ Object *object_property_get_link(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_bool: @@ -877,7 +877,7 @@ Object *object_property_get_link(Object *obj, const char *name, * Writes a bool value to a property. */ void object_property_set_bool(Object *obj, bool value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_bool: @@ -889,7 +889,7 @@ void object_property_set_bool(Object *obj, bool value, * an error occurs (including when the property value is not a bool). */ bool object_property_get_bool(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_int: @@ -900,7 +900,7 @@ bool object_property_get_bool(Object *obj, const char *name, * Writes an integer value to a property. */ void object_property_set_int(Object *obj, int64_t value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_int: @@ -912,7 +912,7 @@ void object_property_set_int(Object *obj, int64_t value, * an error occurs (including when the property value is not an integer). */ int64_t object_property_get_int(Object *obj, const char *name, -struct Error **errp); +Error **errp);
[Qemu-devel] [PATCH v7 00/26] qemu: generate acpi tables for the guest
This code can also be found here: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi While this patch still uses info not available in QOM, I think it's reasonable to merge it and then refactor as QOM properties cover more ground. In particular, merging this patchset blocks other projects so I think its preferable to merge now and not wait for all required QOM properties to materialize. I added QOM properties in ich/piix where I knew how to do this. If you already reviewed v5 then the only patches that changed are: i386: define pc guest info i386: ACPI table generation code from seabios Gerd, Laszlo, I kept you Reviewed-by and Tested-by tags on these patches to ensure your contribution is recongnized, if you don't like this pls let me know. Or better yet re-ack this version :) Patches 1-3 are QOM patches really. Included here for completeness. Igor suggested dropping patches 1-2 and including error.h directly. I included his patch and dropped mine. I hope that's ok. If everything's in order, I intend to merge this through my tree. Please review, and comment. Changes from v6: - removed all complex table patching and migration code we now only migrate a single byte patched/non patched all tables are simply regenerated on access, rewriting old data in particular this fixed a bug that Igor noticed: cpu online status is now updated correctly - removed bitmask of found cpus - use QOM to calculate it Changes from v5: - update generated files to fix build on systems without iasl - fix mcfg failure reported by Gerd Changes from v4: - address comments by Paolo: rename loader interface reuse macro for hpet name better struct names move internal headers to hw/i386/ - fix typos resulting in bugs reported by Gerd Changes from v3: - reworked code to use QOM properties some info isn't yet available in QOM, use old-style APIs and lookups by type - address comments by Gerd: tables are now updated on guest access after pci configuration Changes from v2 repost: - address comment by Anthony - convert to use APIs implemented using QOM - address comment by Anthony - avoid tricky pointer path, use GArray from glib instead - Address lots of comments by Hu Tao and Laszlo Ersek Changes from v2: - added missing patches to make it actually build Changes from v1 RFC: - added code to address cross version compatibility - rebased to latest bits - updated seabios code to latest bits (added pvpanic device) This patchset moves all generation of ACPI tables from guest BIOS to the hypervisor. Although ACPI tables come from a system BIOS on real hw, it makes sense that the ACPI tables are coupled with the virtual machine, since they have to abstract the x86 machine to the OS's. This is widely desired as a way to avoid the churn and proliferation of QEMU-specific interfaces associated with ACPI tables in bios code. There's a bit of code duplication where we already declare similar acpi structures in qemu. I think it's best to do it in this order: port code directly, and apply cleanups and reduce duplication that results, on top. This way it's much easier to see that we don't introduce regressions. In particular, I booted a guest on qemu with and without the change, and verified that ACPI tables are unchanged except for trivial pointer address changes, and the SSDT P_BLK change in the last patch. Such binary compatibility makes it easier to be confident that this change won't break things. Igor Mammedov (1): cleanup object.h: include error.h directly Michael S. Tsirkin (25): qom: cleanup struct Error references qom: add pointer to int property helpers pci: fix up w64 size calculation helper fw_cfg: interface to trigger callback on read loader: support for unmapped ROM blobs pcie_host: expose UNMAPPED macro pcie_host: expose address format q35: use macro for MCFG property name q35: expose mmcfg size as a property i386: add ACPI table files from seabios acpi: add rules to compile ASL source acpi: pre-compiled ASL files acpi: ssdt pcihp: updat generated file loader: use file path size from fw_cfg.h i386: add bios linker/loader loader: allow adding ROMs in done callbacks i386: define pc guest info acpi/piix: add macros for acpi property names piix: APIs for pc guest info ich9: APIs for pc guest info pvpanic: add API to access io port hpet: add API to find it i386: ACPI table generation code from seabios ssdt: fix PBLK length ssdt-proc: update generated file configure |9 +- hw/i386/acpi-build.h|9 + hw/i386/acpi-defs.h | 331 ++ hw/i386/bios-linker-loader.h| 27 + hw/lm32/lm32_hwsetup.h |2 +- include/hw/acpi/ich9.h |2 + include/hw/acpi/piix4.h |8 + include/hw/i386/ich9.h |2 + include/hw/i386/pc.h| 22 + include/hw/loader.h |8 +-
[Qemu-devel] [PATCH v7 01/26] cleanup object.h: include error.h directly
From: Igor Mammedov imamm...@redhat.com qapi/error.h is simple enough to be included in qom/object.h direcly and prepares qom/object.h to use Error typedef. Signed-off-by: Igor Mammedov imamm...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qom/object.h b/include/qom/object.h index 1a7b71a..d9a0063 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -18,9 +18,9 @@ #include stdint.h #include stdbool.h #include qemu/queue.h +#include qapi/error.h struct Visitor; -struct Error; struct TypeImpl; typedef struct TypeImpl *Type; -- MST
[Qemu-devel] [PATCH v7 08/26] pcie_host: expose address format
Callers pass in the address so it's helpful for them to be able to decode it. Reviewed-by: Gerd Hoffmann kra...@redhat.com Tested-by: Gerd Hoffmann kra...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/hw/pci/pcie_host.h | 21 + hw/pci/pcie_host.c | 21 - 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index bac3c67..da0f275 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -54,4 +54,25 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, hwaddr addr, uint32_t size); +/* + * PCI express ECAM (Enhanced Configuration Address Mapping) format. + * AKA mmcfg address + * bit 20 - 28: bus number + * bit 15 - 19: device number + * bit 12 - 14: function number + * bit 0 - 11: offset in configuration space of a given device + */ +#define PCIE_MMCFG_SIZE_MAX (1ULL 28) +#define PCIE_MMCFG_SIZE_MIN (1ULL 20) +#define PCIE_MMCFG_BUS_BIT 20 +#define PCIE_MMCFG_BUS_MASK 0x1ff +#define PCIE_MMCFG_DEVFN_BIT12 +#define PCIE_MMCFG_DEVFN_MASK 0xff +#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff +#define PCIE_MMCFG_BUS(addr)(((addr) PCIE_MMCFG_BUS_BIT) \ + PCIE_MMCFG_BUS_MASK) +#define PCIE_MMCFG_DEVFN(addr) (((addr) PCIE_MMCFG_DEVFN_BIT) \ + PCIE_MMCFG_DEVFN_MASK) +#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) PCIE_MMCFG_CONFOFFSET_MASK) + #endif /* PCIE_HOST_H */ diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 410ac08..c6e1b57 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -24,27 +24,6 @@ #include hw/pci/pcie_host.h #include exec/address-spaces.h -/* - * PCI express mmcfig address - * bit 20 - 28: bus number - * bit 15 - 19: device number - * bit 12 - 14: function number - * bit 0 - 11: offset in configuration space of a given device - */ -#define PCIE_MMCFG_SIZE_MAX (1ULL 28) -#define PCIE_MMCFG_SIZE_MIN (1ULL 20) -#define PCIE_MMCFG_BUS_BIT 20 -#define PCIE_MMCFG_BUS_MASK 0x1ff -#define PCIE_MMCFG_DEVFN_BIT12 -#define PCIE_MMCFG_DEVFN_MASK 0xff -#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff -#define PCIE_MMCFG_BUS(addr)(((addr) PCIE_MMCFG_BUS_BIT) \ - PCIE_MMCFG_BUS_MASK) -#define PCIE_MMCFG_DEVFN(addr) (((addr) PCIE_MMCFG_DEVFN_BIT) \ - PCIE_MMCFG_DEVFN_MASK) -#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) PCIE_MMCFG_CONFOFFSET_MASK) - - /* a helper function to get a PCIDevice for a given mmconfig address */ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, uint32_t mmcfg_addr) -- MST
[Qemu-devel] [PATCH v7 03/26] qom: add pointer to int property helpers
Make it easy to add read-only helpers for simple
integer properties in memory.
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/qom/object.h | 21 ++
qom/object.c | 60
2 files changed, 81 insertions(+)
diff --git a/include/qom/object.h b/include/qom/object.h
index 6c1e7d3..d02172a 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -795,6 +795,27 @@ void object_property_add(Object *obj, const char *name,
const char *type,
void object_property_del(Object *obj, const char *name, Error **errp);
/**
+ * object_property_add_uint8_ptr:
+ * object_property_add_uint16_ptr:
+ * object_property_add_uint32_ptr:
+ * object_property_add_uint64_ptr:
+ * @obj: the object to add a property to
+ * @name: the name of the property
+ * @v: pointer to value
+ *
+ * Add an integer property in memory. This function will add a
+ * property of the appropriate type.
+ */
+void object_property_add_uint8_ptr(Object *obj, const char *name,
+ const uint8_t *v, Error **errp);
+void object_property_add_uint16_ptr(Object *obj, const char *name,
+const uint16_t *v, Error **errp);
+void object_property_add_uint32_ptr(Object *obj, const char *name,
+const uint32_t *v, Error **errp);
+void object_property_add_uint64_ptr(Object *obj, const char *name,
+const uint64_t *v, Error **Errp);
+
+/**
* object_property_find:
* @obj: the object
* @name: the name of the property
diff --git a/qom/object.c b/qom/object.c
index e90e382..b617f26 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1344,6 +1344,66 @@ static char *qdev_get_type(Object *obj, Error **errp)
return g_strdup(object_get_typename(obj));
}
+static void property_get_uint8_ptr(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+uint8_t value = *(uint8_t *)opaque;
+visit_type_uint8(v, value, name, errp);
+}
+
+static void property_get_uint16_ptr(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+uint16_t value = *(uint16_t *)opaque;
+visit_type_uint16(v, value, name, errp);
+}
+
+static void property_get_uint32_ptr(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+uint32_t value = *(uint32_t *)opaque;
+visit_type_uint32(v, value, name, errp);
+}
+
+static void property_get_uint64_ptr(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+uint64_t value = *(uint64_t *)opaque;
+visit_type_uint64(v, value, name, errp);
+}
+
+void object_property_add_uint8_ptr(Object *obj, const char *name,
+ const uint8_t *v, Error **errp)
+{
+object_property_add(obj, name, uint8, property_get_uint8_ptr,
+NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint16_ptr(Object *obj, const char *name,
+const uint16_t *v, Error **errp)
+{
+object_property_add(obj, name, uint16, property_get_uint16_ptr,
+NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint32_ptr(Object *obj, const char *name,
+const uint32_t *v, Error **errp)
+{
+object_property_add(obj, name, uint32, property_get_uint32_ptr,
+NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint64_ptr(Object *obj, const char *name,
+const uint64_t *v, Error **errp)
+{
+object_property_add(obj, name, uint64, property_get_uint64_ptr,
+NULL, NULL, (void *)v, errp);
+}
+
static void object_instance_init(Object *obj)
{
object_property_add_str(obj, type, qdev_get_type, NULL, NULL);
--
MST
[Qemu-devel] [PATCH v7 05/26] fw_cfg: interface to trigger callback on read
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/nvram/fw_cfg.h | 4
hw/nvram/fw_cfg.c | 33 -
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index f60dd67..2ab0fc2 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -60,6 +60,7 @@ typedef struct FWCfgFiles {
} FWCfgFiles;
typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
+typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset);
void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len);
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value);
@@ -70,6 +71,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
void *callback_opaque, void *data, size_t len);
void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
size_t len);
+void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
+ FWCfgReadCallback callback, void
*callback_opaque,
+ void *data, size_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
hwaddr crl_addr, hwaddr data_addr);
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index d0820e5..f5dc3ea 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -42,6 +42,7 @@ typedef struct FWCfgEntry {
uint8_t *data;
void *callback_opaque;
FWCfgCallback callback;
+FWCfgReadCallback read_callback;
} FWCfgEntry;
struct FWCfgState {
@@ -249,8 +250,12 @@ static uint8_t fw_cfg_read(FWCfgState *s)
if (s-cur_entry == FW_CFG_INVALID || !e-data || s-cur_offset = e-len)
ret = 0;
-else
+else {
+if (e-read_callback) {
+e-read_callback(e-callback_opaque, s-cur_offset);
+}
ret = e-data[s-cur_offset++];
+}
trace_fw_cfg_read(s, ret);
return ret;
@@ -381,7 +386,10 @@ static const VMStateDescription vmstate_fw_cfg = {
}
};
-void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
+ FWCfgReadCallback callback,
+ void *callback_opaque,
+ void *data, size_t len)
{
int arch = !!(key FW_CFG_ARCH_LOCAL);
@@ -391,6 +399,13 @@ void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void
*data, size_t len)
s-entries[arch][key].data = data;
s-entries[arch][key].len = (uint32_t)len;
+s-entries[arch][key].read_callback = callback;
+s-entries[arch][key].callback_opaque = callback_opaque;
+}
+
+void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+{
+fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len);
}
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
@@ -444,8 +459,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
s-entries[arch][key].callback = callback;
}
-void fw_cfg_add_file(FWCfgState *s, const char *filename,
- void *data, size_t len)
+void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
+ FWCfgReadCallback callback, void
*callback_opaque,
+ void *data, size_t len)
{
int i, index;
size_t dsize;
@@ -459,7 +475,8 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename,
index = be32_to_cpu(s-files-count);
assert(index FW_CFG_FILE_SLOTS);
-fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len);
+fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
+ callback, callback_opaque, data, len);
pstrcpy(s-files-f[index].name, sizeof(s-files-f[index].name),
filename);
@@ -477,6 +494,12 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename,
s-files-count = cpu_to_be32(index+1);
}
+void fw_cfg_add_file(FWCfgState *s, const char *filename,
+ void *data, size_t len)
+{
+fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
+}
+
static void fw_cfg_machine_ready(struct Notifier *n, void *data)
{
size_t len;
--
MST
[Qemu-devel] [PATCH v7 04/26] pci: fix up w64 size calculation helper
BAR base was calculated incorrectly.
Use existing pci_bar_address to get it right.
Tested-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/pci/pci.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 00554a0..c3fdff4 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2264,7 +2264,7 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev,
void *opaque)
Range *range = opaque;
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
uint16_t cmd = pci_get_word(dev-config + PCI_COMMAND);
-int r;
+int i;
if (!(cmd PCI_COMMAND_MEMORY)) {
return;
@@ -2283,17 +2283,21 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev,
void *opaque)
range_extend(range, pref_range);
}
}
-for (r = 0; r PCI_NUM_REGIONS; ++r) {
-PCIIORegion *region = dev-io_regions[r];
+for (i = 0; i PCI_NUM_REGIONS; ++i) {
+PCIIORegion *r = dev-io_regions[i];
Range region_range;
-if (!region-size ||
-(region-type PCI_BASE_ADDRESS_SPACE_IO) ||
-!(region-type PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+if (!r-size ||
+(r-type PCI_BASE_ADDRESS_SPACE_IO) ||
+!(r-type PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+continue;
+}
+region_range.begin = pci_bar_address(dev, i, r-type, r-size);
+region_range.end = region_range.begin + r-size;
+
+if (region_range.begin == PCI_BAR_UNMAPPED) {
continue;
}
-region_range.begin = pci_get_quad(dev-config + pci_bar(dev, r));
-region_range.end = region_range.begin + region-size;
region_range.begin = MAX(region_range.begin, 0x1ULL 32);
--
MST
[Qemu-devel] [PATCH v7 10/26] q35: expose mmcfg size as a property
Address is already exposed, expose size for symmetry.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 1 +
hw/pci-host/q35.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 33d75bd..acca45e 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -29,6 +29,7 @@
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
#define PCIE_HOST_MCFG_BASE MCFG
+#define PCIE_HOST_MCFG_SIZE mcfg_size
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index e46f286..a051b58 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj,
Visitor *v,
visit_type_uint64(v, w64.end, name, errp);
}
+static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
+void *opaque, const char *name,
+Error **errp)
+{
+PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
+uint32_t value = e-size;
+
+visit_type_uint32(v, value, name, errp);
+}
+
static Property mch_props[] = {
DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
@@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj)
q35_host_get_pci_hole64_end,
NULL, NULL, NULL, NULL);
+object_property_add(obj, PCIE_HOST_MCFG_SIZE, int,
+q35_host_get_mmcfg_size,
+NULL, NULL, NULL, NULL);
+
/* Leave enough space for the biggest MCFG BAR */
/* TODO: this matches current bios behaviour, but
* it's not a power of two, which means an MTRR
--
MST
[Qemu-devel] [PATCH v7 07/26] pcie_host: expose UNMAPPED macro
Make it possible to test unmapped status through QMP.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 3 +++
hw/pci/pcie_host.c | 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 1228e36..bac3c67 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,9 @@
#define PCIE_HOST_BRIDGE(obj) \
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
+#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
+
struct PCIExpressHost {
PCIHostState pci;
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index b70e5ad..410ac08 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -104,9 +104,6 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
-
int pcie_host_init(PCIExpressHost *e)
{
e-base_addr = PCIE_BASE_ADDR_UNMAPPED;
--
MST
[Qemu-devel] [PATCH v7 09/26] q35: use macro for MCFG property name
Useful to make it accessible through QOM.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 2 ++
hw/pci-host/q35.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index da0f275..33d75bd 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,8 @@
#define PCIE_HOST_BRIDGE(obj) \
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+#define PCIE_HOST_MCFG_BASE MCFG
+
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 23dbeea..e46f286 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -110,7 +110,7 @@ static void q35_host_get_pci_hole64_end(Object *obj,
Visitor *v,
}
static Property mch_props[] = {
-DEFINE_PROP_UINT64(MCFG, Q35PCIHost, parent_obj.base_addr,
+DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
--
MST
[Qemu-devel] [PATCH v7 17/26] loader: allow adding ROMs in done callbacks
Don't abort if machine done callbacks add ROMs.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/loader.h | 1 +
hw/core/loader.c| 6 +-
vl.c| 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index e0c576b..58eca98 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -46,6 +46,7 @@ void *rom_add_blob(const char *name, const void *blob, size_t
len,
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
+void rom_load_done(void);
void rom_set_fw(FWCfgState *f);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
void *rom_ptr(hwaddr addr);
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 060729f..60d2ebd 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -812,10 +812,14 @@ int rom_load_all(void)
memory_region_unref(section.mr);
}
qemu_register_reset(rom_reset, NULL);
-roms_loaded = 1;
return 0;
}
+void rom_load_done(void)
+{
+roms_loaded = 1;
+}
+
void rom_set_fw(FWCfgState *f)
{
fw_cfg = f;
diff --git a/vl.c b/vl.c
index fb8006e..46c29c4 100644
--- a/vl.c
+++ b/vl.c
@@ -4339,6 +4339,9 @@ int main(int argc, char **argv, char **envp)
qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
qemu_run_machine_init_done_notifiers();
+/* Done notifiers can load ROMs */
+rom_load_done();
+
qemu_system_reset(VMRESET_SILENT);
if (loadvm) {
if (load_vmstate(loadvm) 0) {
--
MST
[Qemu-devel] [PATCH v7 06/26] loader: support for unmapped ROM blobs
Support ROM blobs not mapped into guest memory:
same as ROM files really but use caller's buffer.
Support incoking callback on access and
return memory pointer making it easier
for caller to update memory if necessary.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Reviewed-by: Laszlo Ersek ler...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/lm32/lm32_hwsetup.h | 2 +-
include/hw/loader.h| 7 ---
hw/core/loader.c | 23 ---
3 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h
index 3449bd8..9fd5e69 100644
--- a/hw/lm32/lm32_hwsetup.h
+++ b/hw/lm32/lm32_hwsetup.h
@@ -73,7 +73,7 @@ static inline void hwsetup_free(HWSetup *hw)
static inline void hwsetup_create_rom(HWSetup *hw,
hwaddr base)
{
-rom_add_blob(hwsetup, hw-data, TARGET_PAGE_SIZE, base);
+rom_add_blob(hwsetup, hw-data, TARGET_PAGE_SIZE, base, NULL, NULL,
NULL);
}
static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 6145736..e0c576b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -40,8 +40,9 @@ extern bool rom_file_in_ram;
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex);
-int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr);
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+ hwaddr addr, const char *fw_file_name,
+ FWCfgReadCallback fw_callback, void *callback_opaque);
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
@@ -53,7 +54,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
#define rom_add_file_fixed(_f, _a, _i) \
rom_add_file(_f, NULL, _a, _i)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
-rom_add_blob(_f, _b, _l, _a)
+(rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) ? 0 : -1)
#define PC_ROM_MIN_VGA 0xc
#define PC_ROM_MIN_OPTION 0xc8000
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 7b3d3ee..449bd4c 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -700,10 +700,12 @@ err:
return -1;
}
-int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr)
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+ hwaddr addr, const char *fw_file_name,
+ FWCfgReadCallback fw_callback, void *callback_opaque)
{
Rom *rom;
+void *data = NULL;
rom = g_malloc0(sizeof(*rom));
rom-name = g_strdup(name);
@@ -713,7 +715,22 @@ int rom_add_blob(const char *name, const void *blob,
size_t len,
rom-data = g_malloc0(rom-datasize);
memcpy(rom-data, blob, len);
rom_insert(rom);
-return 0;
+if (fw_file_name fw_cfg) {
+char devpath[100];
+
+snprintf(devpath, sizeof(devpath), /rom@%s, fw_file_name);
+
+if (rom_file_in_ram) {
+data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
+} else {
+data = rom-data;
+}
+
+fw_cfg_add_file_callback(fw_cfg, fw_file_name,
+ fw_callback, callback_opaque,
+ data, rom-romsize);
+}
+return data;
}
/* This function is specific for elf program because we don't need to allocate
--
MST
[Qemu-devel] [PATCH v7 22/26] pvpanic: add API to access io port
Add API to find pvpanic device and get its io port.
Will be used to fill in guest info structure.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 1 +
hw/misc/pvpanic.c| 13 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 95857be..e3ee0a8 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory,
/* pvpanic.c */
void pvpanic_init(ISABus *bus);
+uint16_t pvpanic_port(void);
/* e820 types */
#define E820_RAM1
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index b64e3bb..226e298 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -117,8 +117,19 @@ void pvpanic_init(ISABus *bus)
isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE);
}
+#define PVPANIC_IOPORT_PROP ioport
+
+uint16_t pvpanic_port(void)
+{
+Object *o = object_resolve_path_type(, TYPE_ISA_PVPANIC_DEVICE, NULL);
+if (!o) {
+return 0;
+}
+return object_property_get_int(o, PVPANIC_IOPORT_PROP, NULL);
+}
+
static Property pvpanic_isa_properties[] = {
-DEFINE_PROP_UINT16(ioport, PVPanicState, ioport, 0x505),
+DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
DEFINE_PROP_END_OF_LIST(),
};
--
MST
[Qemu-devel] [PATCH v7 18/26] i386: define pc guest info
This defines a structure that will be used to fill in acpi tables
where relevant properties are not yet available using QOM.
Reviewed-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 9 +
hw/i386/pc.c | 31 +++
2 files changed, 40 insertions(+)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9b2ddc4..085a621 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -9,6 +9,9 @@
#include hw/i386/ioapic.h
#include qemu/range.h
+#include qemu/bitmap.h
+#include sysemu/sysemu.h
+#include hw/pci/pci.h
/* PC-style peripherals (also used by other machines). */
@@ -20,6 +23,12 @@ typedef struct PcPciInfo {
struct PcGuestInfo {
bool has_pci_info;
bool isapc_ram_fw;
+hwaddr ram_size;
+unsigned apic_id_limit;
+bool apic_xrupt_override;
+uint64_t numa_nodes;
+uint64_t *node_mem;
+uint64_t *node_cpu;
FWCfgState *fw_cfg;
};
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0c313fe..dbae9da 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1028,6 +1028,23 @@ static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
fw_cfg_add_file(guest_info-fw_cfg, etc/pci-info, info, sizeof *info);
}
+static void pc_set_cpu_guest_info(CPUState *cpu, PcGuestInfo *guest_info)
+{
+CPUClass *klass = CPU_GET_CLASS(cpu);
+uint64_t apic_id = klass-get_arch_id(cpu);
+int j;
+
+assert(apic_id guest_info-apic_id_limit);
+
+for (j = 0; j guest_info-numa_nodes; j++) {
+assert(cpu-cpu_index max_cpus);
+if (test_bit(cpu-cpu_index, node_cpumask[j])) {
+guest_info-node_cpu[apic_id] = cpu_to_le64(j);
+break;
+}
+}
+}
+
typedef struct PcGuestInfoState {
PcGuestInfo info;
Notifier machine_done;
@@ -1047,6 +1064,20 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
{
PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
PcGuestInfo *guest_info = guest_info_state-info;
+CPUState *cpu;
+
+guest_info-ram_size = below_4g_mem_size + above_4g_mem_size;
+guest_info-apic_id_limit = pc_apic_id_limit(max_cpus);
+guest_info-apic_xrupt_override = kvm_allows_irq0_override();
+guest_info-numa_nodes = nb_numa_nodes;
+guest_info-node_mem = g_memdup(node_mem, guest_info-numa_nodes *
+sizeof *guest_info-node_mem);
+guest_info-node_cpu = g_malloc0(guest_info-apic_id_limit *
+ sizeof *guest_info-node_cpu);
+
+CPU_FOREACH(cpu) {
+pc_set_cpu_guest_info(cpu, guest_info);
+}
guest_info_state-machine_done.notify = pc_guest_info_machine_done;
qemu_add_machine_init_done_notifier(guest_info_state-machine_done);
--
MST
[Qemu-devel] [PATCH v7 15/26] loader: use file path size from fw_cfg.h
Avoid a bit of code duplication, make
max file path constant reusable.
Suggested-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/nvram/fw_cfg.h | 4 +++-
hw/core/loader.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 2ab0fc2..72b1549 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -46,12 +46,14 @@
#define FW_CFG_INVALID 0x
+#define FW_CFG_MAX_FILE_PATH56
+
#ifndef NO_QEMU_PROTOS
typedef struct FWCfgFile {
uint32_t size;/* file size */
uint16_t select; /* write this to 0x510 to read it */
uint16_t reserved;
-char name[56];
+char name[FW_CFG_MAX_FILE_PATH];
} FWCfgFile;
typedef struct FWCfgFiles {
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 449bd4c..060729f 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -663,7 +663,7 @@ int rom_add_file(const char *file, const char *fw_dir,
rom_insert(rom);
if (rom-fw_file fw_cfg) {
const char *basename;
-char fw_file_name[56];
+char fw_file_name[FW_CFG_MAX_FILE_PATH];
void *data;
basename = strrchr(rom-fw_file, '/');
--
MST
[Qemu-devel] [PATCH v7 14/26] acpi: ssdt pcihp: updat generated file
update generated file, not sure what changed
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-pcihp.hex.generated | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
index 0d32a27..b3c2cd5 100644
--- a/hw/i386/ssdt-pcihp.hex.generated
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -17,7 +17,7 @@ static unsigned char ssdp_pcihp_aml[] = {
0x0,
0x0,
0x1,
-0x77,
+0x76,
0x42,
0x58,
0x50,
@@ -40,9 +40,9 @@ static unsigned char ssdp_pcihp_aml[] = {
0x4e,
0x54,
0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
0x20,
0x10,
0x33,
--
MST
[Qemu-devel] [PATCH v7 23/26] hpet: add API to find it
Add API to find HPET using QOM.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/timer/hpet.h | 2 ++
hw/timer/hpet.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
index 757f79f..ab44bd3 100644
--- a/include/hw/timer/hpet.h
+++ b/include/hw/timer/hpet.h
@@ -71,4 +71,6 @@ struct hpet_fw_config
} QEMU_PACKED;
extern struct hpet_fw_config hpet_cfg;
+
+bool hpet_find(void);
#endif
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index fcd22ae..2eb75ea 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -757,6 +757,11 @@ static void hpet_device_class_init(ObjectClass *klass,
void *data)
dc-props = hpet_device_properties;
}
+bool hpet_find(void)
+{
+return object_resolve_path_type(, TYPE_HPET, NULL);
+}
+
static const TypeInfo hpet_device_info = {
.name = TYPE_HPET,
.parent= TYPE_SYS_BUS_DEVICE,
--
MST
[Qemu-devel] [PATCH v7 19/26] acpi/piix: add macros for acpi property names
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 10 ++
hw/acpi/piix4.c | 6 +++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 085a621..5aefc5b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -20,6 +20,16 @@ typedef struct PcPciInfo {
Range w64;
} PcPciInfo;
+#define ACPI_PM_PROP_S3_DISABLED disable_s3
+#define ACPI_PM_PROP_S4_DISABLED disable_s4
+#define ACPI_PM_PROP_S4_VAL s4_val
+#define ACPI_PM_PROP_SCI_INT sci_int
+#define ACPI_PM_PROP_ACPI_ENABLE_CMD acpi_enable_cmd
+#define ACPI_PM_PROP_ACPI_DISABLE_CMD acpi_disable_cmd
+#define ACPI_PM_PROP_PM_IO_BASE pm_io_base
+#define ACPI_PM_PROP_GPE0_BLK gpe0_blk
+#define ACPI_PM_PROP_GPE0_BLK_LEN gpe0_blk_len
+
struct PcGuestInfo {
bool has_pci_info;
bool isapc_ram_fw;
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index b46bd5e..4b8c1da 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -489,9 +489,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
smb_io_base,
static Property piix4_pm_properties[] = {
DEFINE_PROP_UINT32(smb_io_base, PIIX4PMState, smb_io_base, 0),
-DEFINE_PROP_UINT8(disable_s3, PIIX4PMState, disable_s3, 0),
-DEFINE_PROP_UINT8(disable_s4, PIIX4PMState, disable_s4, 0),
-DEFINE_PROP_UINT8(s4_val, PIIX4PMState, s4_val, 2),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
DEFINE_PROP_END_OF_LIST(),
};
--
MST
[Qemu-devel] [PATCH v7 25/26] ssdt: fix PBLK length
We don't really support CPU throttling, so supply 0 PBLK length.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-proc.dsl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/ssdt-proc.dsl b/hw/i386/ssdt-proc.dsl
index 58333c7..8229bfd 100644
--- a/hw/i386/ssdt-proc.dsl
+++ b/hw/i386/ssdt-proc.dsl
@@ -37,7 +37,7 @@ DefinitionBlock (ssdt-proc.aml, SSDT, 0x01, BXPC,
BXSSDT, 0x1)
ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
-Processor(CPAA, 0xAA, 0xb010, 0x06) {
+Processor(CPAA, 0xAA, 0x, 0x0) {
ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
Name(ID, 0xAA)
/*
--
MST
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
On 10/03/2013 06:34 PM, Paolo Bonzini wrote:
Il 03/10/2013 12:28, Lei Li ha scritto:
The load_hook callback is only be called if the RAM_SAVE_FLAG_HOOK is
received.
To check this flags, it means there would be a check action first in
unix_accept_incoming_migration(), like:
f = qemu_fopen_pipe(c, rb);
flags = qemu_get_be64(f);
if (flags == RAM_SAVE_FLAG_HOOK) {
load_hook();
...
}
Otherwise, the incoming side has no idea whether the special 8-bytes record
(RAM_SAVE_FLAG_HOOK) is sent.
No, ram_load is taking care of checking for RAM_SAVE_FLAG_HOOK. If
before_iterate writes the 8 bytes (followed by passing the fd for the
pipe's read-side via SCM_RIGHTS), ram_load will call load_hook before it
loads any page and load_hook will fetch the fd.
If let ram_load take care of checking for RAM_SAVE_FLAG_HOOK, then in
unix_accept_incoming_migration(), how to decide which QEMUFile should
be opened? Since there would be two types of QEMUFile, one is the original
QEMUFile opened by qemu_fopen_socket() for normal Unix migration, the
other is opened by qemu_fopen_pipe() for unix-page-flipping migration.
Or, were you suggesting replace this qemu_fopen_socket() with the
qemu_fopen_pipe(), which also contain the copy of the QEMUFile code for
Unix sockets?
Subsequent calls to load_hook will match data written by the sender's
save_page hook (so they contain a RAM address, with the 4k page data
sent on the pipe).
Paolo
--
Lei
[Qemu-devel] [PATCH v7 21/26] ich9: APIs for pc guest info
This adds APIs that will be used to fill in
acpi tables, implemented using QOM,
to various ich9 components.
Some information is still missing in QOM,
so we fall back on lookups by type instead.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/acpi/ich9.h| 2 ++
include/hw/i386/ich9.h| 2 ++
include/hw/pci-host/q35.h | 2 ++
hw/acpi/ich9.c| 24
hw/isa/lpc_ich9.c | 40
hw/pci-host/q35.c | 10 ++
6 files changed, 80 insertions(+)
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index b1fe71f..82fcf9f 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp);
+
#endif /* HW_ACPI_ICH9_H */
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index c5f637b..4a68b35 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -66,6 +66,8 @@ typedef struct ICH9LPCState {
qemu_irq *ioapic;
} ICH9LPCState;
+Object *ich9_lpc_find(void);
+
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL ((ms_bit) + 1)) - 1) ~((1ULL ls_bit) - 1)))
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 6eb7ab6..f9db770 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -156,4 +156,6 @@ typedef struct Q35PCIHost {
#define MCH_PCIE_DEV 1
#define MCH_PCIE_FUNC 0
+uint64_t mch_mcfg_base(void);
+
#endif /* HW_Q35_H */
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 3fb443d..7e0429e 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -24,6 +24,7 @@
* GNU GPL, version 2 or (at your option) any later version.
*/
#include hw/hw.h
+#include qapi/visitor.h
#include hw/i386/pc.h
#include hw/pci/pci.h
#include qemu/timer.h
@@ -228,3 +229,26 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
pm-powerdown_notifier.notify = pm_powerdown_req;
qemu_register_powerdown_notifier(pm-powerdown_notifier);
}
+
+static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+ICH9LPCPMRegs *pm = opaque;
+uint32_t value = pm-pm_io_base + ICH9_PMIO_GPE0_STS;
+
+visit_type_uint32(v, value, name, errp);
+}
+
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
+{
+static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
+
+object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
+ pm-pm_io_base, errp);
+object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, uint32,
+ich9_pm_get_gpe0_blk,
+NULL, NULL, pm, NULL);
+object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
+ gpe0_len, errp);
+}
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 5633d08..19b2198 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -29,6 +29,7 @@
*/
#include qemu-common.h
#include hw/hw.h
+#include qapi/visitor.h
#include qemu/range.h
#include hw/isa/isa.h
#include hw/sysbus.h
@@ -525,6 +526,43 @@ static const MemoryRegionOps ich9_rst_cnt_ops = {
.endianness = DEVICE_LITTLE_ENDIAN
};
+Object *ich9_lpc_find(void)
+{
+bool ambig;
+Object *o = object_resolve_path_type(, TYPE_ICH9_LPC_DEVICE, ambig);
+
+if (ambig) {
+return NULL;
+}
+return o;
+}
+
+static void ich9_lpc_get_sci_int(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
+uint32_t value = ich9_lpc_sci_irq(lpc);
+
+visit_type_uint32(v, value, name, errp);
+}
+
+static void ich9_lpc_add_properties(ICH9LPCState *lpc)
+{
+static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
+static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+
+object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, uint32,
+ich9_lpc_get_sci_int,
+NULL, NULL, NULL, NULL);
+object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+ acpi_enable_cmd, NULL);
+object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+ acpi_disable_cmd, NULL);
+
+ich9_pm_add_properties(OBJECT(lpc), lpc-pm, NULL);
+}
+
static int ich9_lpc_initfn(PCIDevice *d)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
@@ -552,6 +590,8 @@ static int ich9_lpc_initfn(PCIDevice *d)
[Qemu-devel] [PATCH v7 16/26] i386: add bios linker/loader
This adds a dynamic bios linker/loader.
This will be used by acpi table generation
code to:
- load each table in the appropriate memory segment
- link tables to each other
- fix up checksums after said linking
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/bios-linker-loader.h | 27
hw/i386/bios-linker-loader.c | 158 +++
hw/i386/Makefile.objs| 1 +
3 files changed, 186 insertions(+)
create mode 100644 hw/i386/bios-linker-loader.h
create mode 100644 hw/i386/bios-linker-loader.c
diff --git a/hw/i386/bios-linker-loader.h b/hw/i386/bios-linker-loader.h
new file mode 100644
index 000..498c0af
--- /dev/null
+++ b/hw/i386/bios-linker-loader.h
@@ -0,0 +1,27 @@
+#ifndef BIOS_LINKER_LOADER_H
+#define BIOS_LINKER_LOADER_H
+
+#include glib.h
+#include stdbool.h
+#include inttypes.h
+
+GArray *bios_linker_loader_init(void);
+
+void bios_linker_loader_alloc(GArray *linker,
+ const char *file,
+ uint32_t alloc_align,
+ bool alloc_fseg);
+
+void bios_linker_loader_add_checksum(GArray *linker, const char *file,
+ void *table,
+ void *start, unsigned size,
+ uint8_t *checksum);
+
+void bios_linker_loader_add_pointer(GArray *linker,
+const char *dest_file,
+const char *src_file,
+GArray *table, void *pointer,
+uint8_t pointer_size);
+
+void *bios_linker_loader_cleanup(GArray *linker);
+#endif
diff --git a/hw/i386/bios-linker-loader.c b/hw/i386/bios-linker-loader.c
new file mode 100644
index 000..0833853
--- /dev/null
+++ b/hw/i386/bios-linker-loader.c
@@ -0,0 +1,158 @@
+/* Dynamic linker/loader of ACPI tables
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin m...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+
+#include bios-linker-loader.h
+#include hw/nvram/fw_cfg.h
+
+#include string.h
+#include assert.h
+#include qemu/bswap.h
+
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+struct BiosLinkerLoaderEntry {
+uint32_t command;
+union {
+/*
+ * COMMAND_ALLOCATE - allocate a table from @alloc.file
+ * subject to @alloc.align alignment (must be power of 2)
+ * and @alloc.zone (can be HIGH or FSEG) requirements.
+ *
+ * Must appear exactly once for each file, and before
+ * this file is referenced by any other command.
+ */
+struct {
+char file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t align;
+uint8_t zone;
+} alloc;
+
+/*
+ * COMMAND_ADD_POINTER - patch the table (originating from
+ * @dest_file) at @pointer.offset, by adding a pointer to the table
+ * originating from @src_file. 1,2,4 or 8 byte unsigned
+ * addition is used depending on @pointer.size.
+ */
+struct {
+char dest_file[BIOS_LINKER_LOADER_FILESZ];
+char src_file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t offset;
+uint8_t size;
+} pointer;
+
+/*
+ * COMMAND_ADD_CHECKSUM - calculate checksum of the range specified by
+ * @cksum_start and @cksum_length fields,
+ * and then add the value at @cksum.offset.
+ * Checksum simply sums -X for each byte X in the range
+ * using 8-bit math.
+ */
+struct {
+char file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t offset;
+uint32_t start;
+uint32_t length;
+} cksum;
+
+/* padding */
+char pad[124];
+};
+} QEMU_PACKED;
+typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
+
+enum {
+BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
+BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
+BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+GArray *bios_linker_loader_init(void)
+{
+return
[Qemu-devel] [PATCH v7 26/26] ssdt-proc: update generated file
Update generated ssdt proc hex file (used for systems
lacking IASL) after P_BLK length change.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-proc.hex.generated | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
index a28172e..bb9920d 100644
--- a/hw/i386/ssdt-proc.hex.generated
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -11,7 +11,7 @@ static unsigned char ssdp_proc_aml[] = {
0x0,
0x0,
0x1,
-0xb3,
+0xb8,
0x42,
0x58,
0x50,
@@ -34,9 +34,9 @@ static unsigned char ssdp_proc_aml[] = {
0x4e,
0x54,
0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
0x20,
0x5b,
0x83,
@@ -51,7 +51,7 @@ static unsigned char ssdp_proc_aml[] = {
0xb0,
0x0,
0x0,
-0x6,
+0x0,
0x8,
0x49,
0x44,
--
MST
Re: [Qemu-devel] [PATCH] qemu-char: Fix potential out of bounds accessto local arrayss
s...@weilnetz.de writes: Latest gcc-4.8 supports a new option -fsanitize=address which activates an AddressSanitizer. This AddressSanitizer stops the QEMU system emulation very early because two character arrays of size 8 are potentially written with 9 bytes. Commit 6ea314d91439741e95772dfbab98b4135e04bebb added the code. There is no obvious reason why width or height could need 8 characters, so reduce it to 7 characters which together with the terminating '\0' fit into the arrays. Cc: qemu-stable qemu-sta...@nongnu.org Signed-off-by: Stefan Weil s...@weilnetz.de snip Reviewed-by: Alex Bennée a...@bennee.com -- Alex Bennée
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
Il 03/10/2013 15:29, Lei Li ha scritto:
On 10/03/2013 06:34 PM, Paolo Bonzini wrote:
Il 03/10/2013 12:28, Lei Li ha scritto:
The load_hook callback is only be called if the RAM_SAVE_FLAG_HOOK is
received.
To check this flags, it means there would be a check action first in
unix_accept_incoming_migration(), like:
f = qemu_fopen_pipe(c, rb);
flags = qemu_get_be64(f);
if (flags == RAM_SAVE_FLAG_HOOK) {
load_hook();
...
}
Otherwise, the incoming side has no idea whether the special 8-bytes
record
(RAM_SAVE_FLAG_HOOK) is sent.
No, ram_load is taking care of checking for RAM_SAVE_FLAG_HOOK. If
before_iterate writes the 8 bytes (followed by passing the fd for the
pipe's read-side via SCM_RIGHTS), ram_load will call load_hook before it
loads any page and load_hook will fetch the fd.
If let ram_load take care of checking for RAM_SAVE_FLAG_HOOK, then in
unix_accept_incoming_migration(), how to decide which QEMUFile should
be opened? Since there would be two types of QEMUFile, one is the original
QEMUFile opened by qemu_fopen_socket() for normal Unix migration, the
other is opened by qemu_fopen_pipe() for unix-page-flipping migration.
Or, were you suggesting replace this qemu_fopen_socket() with the
qemu_fopen_pipe(), which also contain the copy of the QEMUFile code for
Unix sockets?
Yes (though I'd call it qemu_fopen_socket_local() or something like that).
On the incoming side, if non-page-flipping was enabled you will use the
normal RAM loading code, if page-flipping was enabled you will get
load_hook calls.
Paolo
Subsequent calls to load_hook will match data written by the sender's
save_page hook (so they contain a RAM address, with the 4k page data
sent on the pipe).
Paolo
[Qemu-devel] [PATCH v7 20/26] piix: APIs for pc guest info
This adds APIs that will be used to fill in guest acpi tables.
Some required information is still lacking in QOM, so we
fall back on lookups by type and returning explicit types.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/acpi/piix4.h | 8
include/hw/i386/pc.h| 1 +
hw/acpi/piix4.c | 44
hw/pci-host/piix.c | 8
4 files changed, 57 insertions(+), 4 deletions(-)
create mode 100644 include/hw/acpi/piix4.h
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
new file mode 100644
index 000..65e6fd7
--- /dev/null
+++ b/include/hw/acpi/piix4.h
@@ -0,0 +1,8 @@
+#ifndef HW_ACPI_PIIX4_H
+#define HW_ACPI_PIIX4_H
+
+#include qemu/typedefs.h
+
+Object *piix4_pm_find(void);
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 5aefc5b..95857be 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -192,6 +192,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int
*piix_devfn,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
+PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 4b8c1da..3bcd890 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -29,6 +29,7 @@
#include exec/ioport.h
#include hw/nvram/fw_cfg.h
#include exec/address-spaces.h
+#include hw/acpi/piix4.h
//#define DEBUG
@@ -69,6 +70,8 @@ typedef struct PIIX4PMState {
/* public */
MemoryRegion io;
+uint32_t io_base;
+
MemoryRegion io_gpe;
MemoryRegion io_pci;
MemoryRegion io_cpu;
@@ -152,14 +155,13 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
static void pm_io_space_update(PIIX4PMState *s)
{
PCIDevice *d = PCI_DEVICE(s);
-uint32_t pm_io_base;
-pm_io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x40));
-pm_io_base = 0xffc0;
+s-io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x40));
+s-io_base = 0xffc0;
memory_region_transaction_begin();
memory_region_set_enabled(s-io, d-config[0x80] 1);
-memory_region_set_address(s-io, pm_io_base);
+memory_region_set_address(s-io, s-io_base);
memory_region_transaction_commit();
}
@@ -407,6 +409,28 @@ static void piix4_pm_machine_ready(Notifier *n, void
*opaque)
(memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
}
+static void piix4_pm_add_propeties(PIIX4PMState *s)
+{
+static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
+static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
+static const uint32_t gpe0_blk = GPE_BASE;
+static const uint32_t gpe0_blk_len = GPE_LEN;
+static const uint16_t sci_int = 9;
+
+object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+ acpi_enable_cmd, NULL);
+object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+ acpi_disable_cmd, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
+ gpe0_blk, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
+ gpe0_blk_len, NULL);
+object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
+ sci_int, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
+ s-io_base, NULL);
+}
+
static int piix4_pm_initfn(PCIDevice *dev)
{
PIIX4PMState *s = PIIX4_PM(dev);
@@ -456,9 +480,21 @@ static int piix4_pm_initfn(PCIDevice *dev)
piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev-bus, s);
+piix4_pm_add_propeties(s);
return 0;
}
+Object *piix4_pm_find(void)
+{
+bool ambig;
+Object *o = object_resolve_path_type(, TYPE_PIIX4_PM, ambig);
+
+if (ambig || !o) {
+return NULL;
+}
+return o;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int kvm_enabled, FWCfgState *fw_cfg)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index c041149..bad3953 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -416,6 +416,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
return b;
}
+PCIBus *find_i440fx(void)
+{
+PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path(/machine/i440fx,
NULL),
+ TYPE_PCI_HOST_BRIDGE);
+return s ? s-bus : NULL;
+}
+
/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
--
MST
[Qemu-devel] [PATCH v7 12/26] acpi: add rules to compile ASL source
Detect presence of IASL compiler and use it
to process ASL source. If not there, use pre-compiled
files in-tree. Add script to update the in-tree files.
Note: distros are known to silently update iasl
so detect correct iasl flags for the installed version on each run as
opposed to at configure time.
Reviewed-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
configure | 9 -
hw/i386/Makefile.objs | 22 ++
scripts/update-acpi.sh | 4
3 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 scripts/update-acpi.sh
diff --git a/configure b/configure
index 2b83936..15405e1 100755
--- a/configure
+++ b/configure
@@ -119,6 +119,7 @@ path_of() {
# default parameters
source_path=`dirname $0`
cpu=
+iasl=iasl
interp_prefix=/usr/gnemul/qemu-%M
static=no
cross_prefix=
@@ -257,6 +258,8 @@ for opt do
;;
--cxx=*) CXX=$optarg
;;
+ --iasl=*) iasl=$optarg
+ ;;
--source-path=*) source_path=$optarg
;;
--cpu=*) cpu=$optarg
@@ -1055,6 +1058,7 @@ echo Advanced options (experts only):
echo --source-path=PATH path of source code [$source_path]
echo --cross-prefix=PREFIXuse PREFIX for compile tools [$cross_prefix]
echo --cc=CC use C compiler CC [$cc]
+echo --iasl=IASL use ACPI compiler IASL [$iasl]
echo --host-cc=CC use C compiler CC [$host_cc] for code run at
echobuild time
echo --cxx=CXXuse C++ compiler CXX [$cxx]
@@ -4239,6 +4243,9 @@ else
fi
echo PYTHON=$python $config_host_mak
echo CC=$cc $config_host_mak
+if $iasl -h /dev/null 21; then
+ echo IASL=$iasl $config_host_mak
+fi
echo CC_I386=$cc_i386 $config_host_mak
echo HOST_CC=$host_cc $config_host_mak
echo CXX=$cxx $config_host_mak
@@ -4691,7 +4698,7 @@ for rom in seabios vgabios ; do
echo BCC=bcc $config_mak
echo CPP=$cpp $config_mak
echo OBJCOPY=objcopy $config_mak
-echo IASL=iasl $config_mak
+echo IASL=$iasl $config_mak
echo LD=$ld $config_mak
done
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 45e6165..f950707 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -5,3 +5,25 @@ obj-y += pc_sysfw.o
obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
obj-y += kvmvapic.o
+
+iasl-option=$(shell if test -z `$(1) $(2) 21 /dev/null` \
+; then echo $(2); else echo $(3); fi ;)
+
+ifdef IASL
+#IASL Present. Generate hex files from .dsl
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl
$(SRC_PATH)/scripts/acpi_extract_preprocess.py
$(SRC_PATH)/scripts/acpi_extract.py
+ $(call quiet-command, cpp -P $ -o $*.dsl.i.orig, CPP
$(TARGET_DIR)$*.dsl.i.orig)
+ $(call quiet-command, $(PYTHON)
$(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig $*.dsl.i,
ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i)
+ $(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l
-tc -p $* $*.dsl.i $(if $(V), , /dev/null) 21 , IASL
$(TARGET_DIR)$*.dsl.i)
+ $(call quiet-command, $(SRC_PATH)/scripts/acpi_extract.py $*.lst
$*.off, ACPI_EXTRACT $(TARGET_DIR)$*.off)
+ $(call quiet-command, cat $*.off $@, CAT $(TARGET_DIR)$@)
+else
+#IASL Not present. Restore pre-generated hex files.
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.hex.generated
+ $(call quiet-command, cp -f $ $@, CP $(TARGET_DIR)$@)
+endif
+
+.PHONY: cleanhex
+cleanhex:
+ rm -f hw/i386/*hex
+clean: cleanhex
diff --git a/scripts/update-acpi.sh b/scripts/update-acpi.sh
new file mode 100644
index 000..b5f05ff
--- /dev/null
+++ b/scripts/update-acpi.sh
@@ -0,0 +1,4 @@
+cd x86_64-softmmu
+for file in hw/i386/*.hex; do
+cp -f $file ../$file.generated
+done
--
MST
[Qemu-devel] [PATCH 1/3] portio: Allow to mark portio lists as coalesced MMIO flushing
From: Jan Kiszka jan.kis...@siemens.com
This will enable us to remove all remaining explicit calls of
qemu_flush_coalesced_mmio_buffer in IO handlers.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/exec/ioport.h | 2 ++
ioport.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/include/exec/ioport.h b/include/exec/ioport.h
index b3848be..3bd6722 100644
--- a/include/exec/ioport.h
+++ b/include/exec/ioport.h
@@ -64,11 +64,13 @@ typedef struct PortioList {
struct MemoryRegion **regions;
void *opaque;
const char *name;
+bool flush_coalesced_mmio;
} PortioList;
void portio_list_init(PortioList *piolist, Object *owner,
const struct MemoryRegionPortio *callbacks,
void *opaque, const char *name);
+void portio_list_set_flush_coalesced(PortioList *piolist);
void portio_list_destroy(PortioList *piolist);
void portio_list_add(PortioList *piolist,
struct MemoryRegion *address_space,
diff --git a/ioport.c b/ioport.c
index 707cce8..3d91e79 100644
--- a/ioport.c
+++ b/ioport.c
@@ -139,6 +139,12 @@ void portio_list_init(PortioList *piolist,
piolist-opaque = opaque;
piolist-owner = owner;
piolist-name = name;
+piolist-flush_coalesced_mmio = false;
+}
+
+void portio_list_set_flush_coalesced(PortioList *piolist)
+{
+piolist-flush_coalesced_mmio = true;
}
void portio_list_destroy(PortioList *piolist)
@@ -231,6 +237,9 @@ static void portio_list_add_1(PortioList *piolist,
*/
memory_region_init_io(mrpio-mr, piolist-owner, portio_ops, mrpio,
piolist-name, off_high - off_low);
+if (piolist-flush_coalesced_mmio) {
+memory_region_set_flush_coalesced(mrpio-mr);
+}
memory_region_add_subregion(piolist-address_space,
start + off_low, mrpio-mr);
piolist-regions[piolist-nr] = mrpio-mr;
--
1.8.3.1
[Qemu-devel] [PATCH 2/3] cirrus: Mark vga io region as coalesced MMIO flushing
From: Jan Kiszka jan.kis...@siemens.com
This allows to remove the explicit qemu_flush_coalesced_mmio_buffer
calls - the memory core will invoke them now.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/display/cirrus_vga.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index dbd1f4a..e4c345f 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -2447,7 +2447,6 @@ static uint64_t cirrus_vga_ioport_read(void *opaque,
hwaddr addr,
VGACommonState *s = c-vga;
int val, index;
-qemu_flush_coalesced_mmio_buffer();
addr += 0x3b0;
if (vga_ioport_invalid(s, addr)) {
@@ -2544,7 +2543,6 @@ static void cirrus_vga_ioport_write(void *opaque, hwaddr
addr, uint64_t val,
VGACommonState *s = c-vga;
int index;
-qemu_flush_coalesced_mmio_buffer();
addr += 0x3b0;
/* check port range access depending on color/monochrome mode */
@@ -2843,6 +2841,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object
*owner,
/* Register ioport 0x3b0 - 0x3df */
memory_region_init_io(s-cirrus_vga_io, owner, cirrus_vga_io_ops, s,
cirrus-io, 0x30);
+memory_region_set_flush_coalesced(s-cirrus_vga_io);
memory_region_add_subregion(system_io, 0x3b0, s-cirrus_vga_io);
memory_region_init(s-low_mem_container, owner,
--
1.8.3.1
[Qemu-devel] [PATCH 0/3] Coalesced MMIO flushing cleanups
Three patches from Jan. They've never been posted publicly, so I'm doing that to get them review and exposure. I'll send a pull request sometime next week. Paolo Jan Kiszka (3): portio: Allow to mark portio lists as coalesced MMIO flushing cirrus: Mark vga io region as coalesced MMIO flushing vga: Mark relevant portio lists regions as coalesced MMIO flushing hw/display/cirrus_vga.c | 3 +-- hw/display/qxl.c| 1 + hw/display/vga.c| 5 + include/exec/ioport.h | 2 ++ ioport.c| 9 + 5 files changed, 14 insertions(+), 6 deletions(-) -- 1.8.3.1
[Qemu-devel] [PATCH 3/3] vga: Mark relevant portio lists regions as coalesced MMIO flushing
From: Jan Kiszka jan.kis...@siemens.com
This allows to remove the explicit qemu_flush_coalesced_mmio_buffer
calls.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/display/qxl.c | 1 +
hw/display/vga.c | 5 +
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index ee2db0d..3051006 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -2074,6 +2074,7 @@ static int qxl_init_primary(PCIDevice *dev)
pci_address_space(dev), pci_address_space_io(dev), false);
portio_list_init(qxl_vga_port_list, OBJECT(dev), qxl_vga_portio_list,
vga, vga);
+portio_list_set_flush_coalesced(qxl_vga_port_list);
portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
vga-con = graphic_console_init(DEVICE(dev), qxl_ops, qxl);
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 7b91d9c..b5e2284 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -359,8 +359,6 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)
VGACommonState *s = opaque;
int val, index;
-qemu_flush_coalesced_mmio_buffer();
-
if (vga_ioport_invalid(s, addr)) {
val = 0xff;
} else {
@@ -453,8 +451,6 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t
val)
VGACommonState *s = opaque;
int index;
-qemu_flush_coalesced_mmio_buffer();
-
/* check port range access depending on color/monochrome mode */
if (vga_ioport_invalid(s, addr)) {
return;
@@ -2373,6 +2369,7 @@ void vga_init(VGACommonState *s, Object *obj,
MemoryRegion *address_space,
memory_region_set_coalescing(vga_io_memory);
if (init_vga_ports) {
portio_list_init(vga_port_list, obj, vga_ports, s, vga);
+portio_list_set_flush_coalesced(vga_port_list);
portio_list_add(vga_port_list, address_space_io, 0x3b0);
}
if (vbe_ports) {
--
1.8.3.1
[Qemu-devel] [PATCH] compatfd: switch to QemuThread
From: Jan Kiszka jan.kis...@siemens.com
qemu_thread_create already does signal blocking and detaching for us.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
util/compatfd.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/util/compatfd.c b/util/compatfd.c
index 9cf3f28..430a41c 100644
--- a/util/compatfd.c
+++ b/util/compatfd.c
@@ -15,9 +15,9 @@
#include qemu-common.h
#include qemu/compatfd.h
+#include qemu/thread.h
#include sys/syscall.h
-#include pthread.h
struct sigfd_compat_info
{
@@ -28,10 +28,6 @@ struct sigfd_compat_info
static void *sigwait_compat(void *opaque)
{
struct sigfd_compat_info *info = opaque;
-sigset_t all;
-
-sigfillset(all);
-pthread_sigmask(SIG_BLOCK, all, NULL);
while (1) {
int sig;
@@ -71,9 +67,8 @@ static void *sigwait_compat(void *opaque)
static int qemu_signalfd_compat(const sigset_t *mask)
{
-pthread_attr_t attr;
-pthread_t tid;
struct sigfd_compat_info *info;
+QemuThread thread;
int fds[2];
info = malloc(sizeof(*info));
@@ -93,12 +88,7 @@ static int qemu_signalfd_compat(const sigset_t *mask)
memcpy(info-mask, mask, sizeof(*mask));
info-fd = fds[1];
-pthread_attr_init(attr);
-pthread_attr_setdetachstate(attr, PTHREAD_CREATE_DETACHED);
-
-pthread_create(tid, attr, sigwait_compat, info);
-
-pthread_attr_destroy(attr);
+qemu_thread_create(thread, sigwait_compat, info, QEMU_THREAD_DETACHED);
return fds[0];
}
--
1.8.3.1
[Qemu-devel] [PATCH 4/4] qdev: switch reset to post-order
Post-order is the only sensible direction for the reset signals.
For example, suppose pre-order is used and the parent has some data
structures that cache children state (for example a list of active
requests). When the reset method is invoked on the parent, these caches
could be in any state.
If post-order is used, on the other hand, these will be in a known state
when the reset method is invoked on the parent.
This change means that it is no longer possible to block the visit of
the devices, so the callback is changed to return void. This is not
a problem, because PCI was returning 1 exactly in order to achieve the
same ordering that this patch implements.
PCI can then rely on the qdev core having sent a reset signal (whatever
that means) to the device, and only do the PCI-specific initialization
with pci_do_device_reset.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/core/qdev.c |6 +++---
hw/pci/pci.c | 31 ---
include/hw/qdev-core.h |2 +-
3 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 1c114b7..9ba8ab1 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -233,19 +233,19 @@ static int qbus_reset_one(BusState *bus, void *opaque)
{
BusClass *bc = BUS_GET_CLASS(bus);
if (bc-reset) {
-return bc-reset(bus);
+bc-reset(bus);
}
return 0;
}
void qdev_reset_all(DeviceState *dev)
{
-qdev_walk_children(dev, qdev_reset_one, qbus_reset_one, NULL, NULL, NULL);
+qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
}
void qbus_reset_all(BusState *bus)
{
-qbus_walk_children(bus, qdev_reset_one, qbus_reset_one, NULL, NULL, NULL);
+qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
}
void qbus_reset_all_fn(void *opaque)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 0efc544..e10d74b 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -46,7 +46,7 @@
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *pcibus_get_dev_path(DeviceState *dev);
static char *pcibus_get_fw_dev_path(DeviceState *dev);
-static int pcibus_reset(BusState *qbus);
+static void pcibus_reset(BusState *qbus);
static Property pci_props[] = {
DEFINE_PROP_PCI_DEVFN(addr, PCIDevice, devfn, -1),
@@ -165,16 +165,10 @@ void pci_device_deassert_intx(PCIDevice *dev)
}
}
-/*
- * This function is called on #RST and FLR.
- * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
- */
-void pci_device_reset(PCIDevice *dev)
+static void pci_do_device_reset(PCIDevice *dev)
{
int r;
-qdev_reset_all(dev-qdev);
-
dev-irq_state = 0;
pci_update_irq_status(dev);
pci_device_deassert_intx(dev);
@@ -207,27 +201,34 @@ void pci_device_reset(PCIDevice *dev)
}
/*
+ * This function is called on #RST and FLR.
+ * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
+ */
+void pci_device_reset(PCIDevice *dev)
+{
+qdev_reset_all(dev-qdev);
+pci_do_device_reset(dev);
+}
+
+/*
* Trigger pci bus reset under a given bus.
- * To be called on RST# assert.
+ * Called via qbus_reset_all on RST# assert, after the devices
+ * have been reset qdev_reset_all-ed already.
*/
-static int pcibus_reset(BusState *qbus)
+static void pcibus_reset(BusState *qbus)
{
PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
int i;
for (i = 0; i ARRAY_SIZE(bus-devices); ++i) {
if (bus-devices[i]) {
-pci_device_reset(bus-devices[i]);
+pci_do_device_reset(bus-devices[i]);
}
}
for (i = 0; i bus-nirq; i++) {
assert(bus-irq_count[i] == 0);
}
-
-/* topology traverse is done by pci_bus_reset().
- Tell qbus/qdev walker not to traverse the tree */
-return 1;
}
static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 21ea2c6..409fd71 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -178,7 +178,7 @@ struct BusClass {
* bindings can be found at http://playground.sun.com/1275/bindings/.
*/
char *(*get_fw_dev_path)(DeviceState *dev);
-int (*reset)(BusState *bus);
+void (*reset)(BusState *bus);
/* maximum devices allowed on the bus, 0: no limit. */
int max_dev;
};
--
1.7.1
[Qemu-devel] [PATCH 0/4] qdev: switch reset to post-order, clean up PCI reset
PCI is handling resetting of its devices before the bus is reset, but this is only necessary because qdev is broken and usually does pre-order reset. Post-order is a much better definition. Drop the unnecessary flexibility that lets bus decide the reset order, convert to post-order, and make PCI use common code for reset. Paolo Bonzini (4): pci: do not export pci_bus_reset pci: clean up resetting of IRQs qdev: allow both pre- and post-order vists in qdev walking functions qdev: switch reset to post-order hw/core/qdev.c | 47 ++- hw/pci/pci.c | 42 -- hw/pci/pci_bridge.c|2 +- include/hw/pci/pci.h |1 - include/hw/qdev-core.h | 15 ++- 5 files changed, 65 insertions(+), 42 deletions(-)
[Qemu-devel] [PATCH 2/4] pci: clean up resetting of IRQs
pci_device_reset will deassert the INTX pins, and this will make the
irq_count array all-zeroes. Check that this is the case, and remove
the existing loop which might even unsync irq_count and irq_state.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/pci/pci.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ac3244b..0efc544 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -215,15 +215,16 @@ static int pcibus_reset(BusState *qbus)
PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
int i;
-for (i = 0; i bus-nirq; i++) {
-bus-irq_count[i] = 0;
-}
for (i = 0; i ARRAY_SIZE(bus-devices); ++i) {
if (bus-devices[i]) {
pci_device_reset(bus-devices[i]);
}
}
+for (i = 0; i bus-nirq; i++) {
+assert(bus-irq_count[i] == 0);
+}
+
/* topology traverse is done by pci_bus_reset().
Tell qbus/qdev walker not to traverse the tree */
return 1;
--
1.7.1
[Qemu-devel] [PATCH 1/4] pci: do not export pci_bus_reset
qbus_reset_all can be used instead. There is no semantic change
because pcibus_reset returns 1 and takes care of the device
tree traversal.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/pci/pci.c |8 ++--
hw/pci/pci_bridge.c |2 +-
include/hw/pci/pci.h |1 -
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bd084c7..ac3244b 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -210,8 +210,9 @@ void pci_device_reset(PCIDevice *dev)
* Trigger pci bus reset under a given bus.
* To be called on RST# assert.
*/
-void pci_bus_reset(PCIBus *bus)
+static int pcibus_reset(BusState *qbus)
{
+PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
int i;
for (i = 0; i bus-nirq; i++) {
@@ -222,11 +223,6 @@ void pci_bus_reset(PCIBus *bus)
pci_device_reset(bus-devices[i]);
}
}
-}
-
-static int pcibus_reset(BusState *qbus)
-{
-pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
/* topology traverse is done by pci_bus_reset().
Tell qbus/qdev walker not to traverse the tree */
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 307e076..06831a2 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -268,7 +268,7 @@ void pci_bridge_write_config(PCIDevice *d,
newctl = pci_get_word(d-config + PCI_BRIDGE_CONTROL);
if (~oldctl newctl PCI_BRIDGE_CTL_BUS_RESET) {
/* Trigger hot reset on 0-1 transition. */
-pci_bus_reset(s-sec_bus);
+qbus_reset_all(s-sec_bus.qbus);
}
}
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index ccec2ba..32f1419 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -376,7 +376,6 @@ void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
PCIINTxRoutingNotifier notifier);
void pci_device_reset(PCIDevice *dev);
-void pci_bus_reset(PCIBus *bus);
PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
const char *default_model,
--
1.7.1
[Qemu-devel] [PATCH 3/4] qdev: allow both pre- and post-order vists in qdev walking functions
Resetting should be done in post-order, not pre-order. However,
qdev_walk_children and qbus_walk_children do not allow this. Fix
it by adding two extra arguments to the functions.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/core/qdev.c | 45 +
include/hw/qdev-core.h | 13 +
2 files changed, 42 insertions(+), 16 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 758de9f..1c114b7 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -240,12 +240,12 @@ static int qbus_reset_one(BusState *bus, void *opaque)
void qdev_reset_all(DeviceState *dev)
{
-qdev_walk_children(dev, qdev_reset_one, qbus_reset_one, NULL);
+qdev_walk_children(dev, qdev_reset_one, qbus_reset_one, NULL, NULL, NULL);
}
void qbus_reset_all(BusState *bus)
{
-qbus_walk_children(bus, qdev_reset_one, qbus_reset_one, NULL);
+qbus_walk_children(bus, qdev_reset_one, qbus_reset_one, NULL, NULL, NULL);
}
void qbus_reset_all_fn(void *opaque)
@@ -343,49 +343,70 @@ BusState *qdev_get_child_bus(DeviceState *dev, const char
*name)
return NULL;
}
-int qbus_walk_children(BusState *bus, qdev_walkerfn *devfn,
- qbus_walkerfn *busfn, void *opaque)
+int qbus_walk_children(BusState *bus,
+ qdev_walkerfn *pre_devfn, qbus_walkerfn *pre_busfn,
+ qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
+ void *opaque)
{
BusChild *kid;
int err;
-if (busfn) {
-err = busfn(bus, opaque);
+if (pre_busfn) {
+err = pre_busfn(bus, opaque);
if (err) {
return err;
}
}
QTAILQ_FOREACH(kid, bus-children, sibling) {
-err = qdev_walk_children(kid-child, devfn, busfn, opaque);
+err = qdev_walk_children(kid-child,
+ pre_devfn, pre_busfn,
+ post_devfn, post_busfn, opaque);
if (err 0) {
return err;
}
}
+if (post_busfn) {
+err = post_busfn(bus, opaque);
+if (err) {
+return err;
+}
+}
+
return 0;
}
-int qdev_walk_children(DeviceState *dev, qdev_walkerfn *devfn,
- qbus_walkerfn *busfn, void *opaque)
+int qdev_walk_children(DeviceState *dev,
+ qdev_walkerfn *pre_devfn, qbus_walkerfn *pre_busfn,
+ qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
+ void *opaque)
{
BusState *bus;
int err;
-if (devfn) {
-err = devfn(dev, opaque);
+if (pre_devfn) {
+err = pre_devfn(dev, opaque);
if (err) {
return err;
}
}
QLIST_FOREACH(bus, dev-child_bus, sibling) {
-err = qbus_walk_children(bus, devfn, busfn, opaque);
+err = qbus_walk_children(bus, pre_devfn, pre_busfn,
+ post_devfn, post_busfn, opaque);
if (err 0) {
return err;
}
}
+if (post_devfn) {
+err = post_devfn(dev, opaque);
+if (err) {
+return err;
+}
+}
+
return 0;
}
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index d840f06..21ea2c6 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -274,10 +274,15 @@ BusState *qbus_create(const char *typename, DeviceState
*parent, const char *nam
/* Returns 0 if either devfn or busfn skip walk somewhere in cursion,
* 0 if either devfn or busfn terminate walk somewhere in cursion,
* 0 otherwise. */
-int qbus_walk_children(BusState *bus, qdev_walkerfn *devfn,
- qbus_walkerfn *busfn, void *opaque);
-int qdev_walk_children(DeviceState *dev, qdev_walkerfn *devfn,
- qbus_walkerfn *busfn, void *opaque);
+int qbus_walk_children(BusState *bus,
+ qdev_walkerfn *pre_devfn, qbus_walkerfn *pre_busfn,
+ qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
+ void *opaque);
+int qdev_walk_children(DeviceState *dev,
+ qdev_walkerfn *pre_devfn, qbus_walkerfn *pre_busfn,
+ qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
+ void *opaque);
+
void qdev_reset_all(DeviceState *dev);
/**
--
1.7.1
Re: [Qemu-devel] [PATCH 0/4] qdev: switch reset to post-order, clean up PCI reset
On Thu, Oct 03, 2013 at 03:46:11PM +0200, Paolo Bonzini wrote: PCI is handling resetting of its devices before the bus is reset, but this is only necessary because qdev is broken and usually does pre-order reset. Post-order is a much better definition. Drop the unnecessary flexibility that lets bus decide the reset order, convert to post-order, and make PCI use common code for reset. Need to go carefully here. I remember a bunch of targets were relying on reset in this order, though don't have the detail right now. What kind of testing did this patchset go through? Paolo Bonzini (4): pci: do not export pci_bus_reset pci: clean up resetting of IRQs qdev: allow both pre- and post-order vists in qdev walking functions qdev: switch reset to post-order hw/core/qdev.c | 47 ++- hw/pci/pci.c | 42 -- hw/pci/pci_bridge.c|2 +- include/hw/pci/pci.h |1 - include/hw/qdev-core.h | 15 ++- 5 files changed, 65 insertions(+), 42 deletions(-)
Re: [Qemu-devel] [PATCH 0/8 RFC] migration: Introduce side channel for RAM
On 10/03/2013 09:34 PM, Paolo Bonzini wrote:
Il 03/10/2013 15:29, Lei Li ha scritto:
On 10/03/2013 06:34 PM, Paolo Bonzini wrote:
Il 03/10/2013 12:28, Lei Li ha scritto:
The load_hook callback is only be called if the RAM_SAVE_FLAG_HOOK is
received.
To check this flags, it means there would be a check action first in
unix_accept_incoming_migration(), like:
f = qemu_fopen_pipe(c, rb);
flags = qemu_get_be64(f);
if (flags == RAM_SAVE_FLAG_HOOK) {
load_hook();
...
}
Otherwise, the incoming side has no idea whether the special 8-bytes
record
(RAM_SAVE_FLAG_HOOK) is sent.
No, ram_load is taking care of checking for RAM_SAVE_FLAG_HOOK. If
before_iterate writes the 8 bytes (followed by passing the fd for the
pipe's read-side via SCM_RIGHTS), ram_load will call load_hook before it
loads any page and load_hook will fetch the fd.
If let ram_load take care of checking for RAM_SAVE_FLAG_HOOK, then in
unix_accept_incoming_migration(), how to decide which QEMUFile should
be opened? Since there would be two types of QEMUFile, one is the original
QEMUFile opened by qemu_fopen_socket() for normal Unix migration, the
other is opened by qemu_fopen_pipe() for unix-page-flipping migration.
Or, were you suggesting replace this qemu_fopen_socket() with the
qemu_fopen_pipe(), which also contain the copy of the QEMUFile code for
Unix sockets?
Yes (though I'd call it qemu_fopen_socket_local() or something like that).
On the incoming side, if non-page-flipping was enabled you will use the
normal RAM loading code, if page-flipping was enabled you will get
load_hook calls.
Ah, I see. :)
qemu_fopen_socket_local() sounds good, thanks!
Paolo
Subsequent calls to load_hook will match data written by the sender's
save_page hook (so they contain a RAM address, with the 4k page data
sent on the pipe).
Paolo
--
Lei
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 3 October 2013 13:59, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 October 2013 21:51, Will Newton will.new...@linaro.org wrote:
This adds support for the VSEL floating point selection instruction
which was added in ARMv8. It is based on the previous patch[1] from
Mans Rullgard, but attempts to address the feedback given on that patch.
[1] http://lists.nongnu.org/archive/html/qemu-devel/2013-06/msg03117.html
This sort of commentary about previous patch versions should go below
the '---', not in the commit message.
Signed-off-by: Will Newton will.new...@linaro.org
---
target-arm/translate.c | 105
+
1 file changed, 105 insertions(+)
Changes in v2:
- Integrate vsel decoding into disas_vfp_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5e49334 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2880,6 +2880,98 @@ static int disas_vfp_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
rm = VFP_SREG_M(insn);
}
+if ((insn 0x0f800e50) == 0x0e000a00) {
+/* vsel */
+uint32_t cc = (insn 20) 3;
+TCGv_i32 tmp, zero;
+
+/* ARMv8 VFP. */
+if (!arm_feature(env, ARM_FEATURE_V8))
+return 1;
scripts/checkpatch.pl will tell you that omitting the braces
is a coding style violation.
Ok, I'll fix that.
+
+zero = tcg_const_tl(0);
+
+if (dp) {
+TCGv_i64 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i64();
+ftmp2 = tcg_temp_new_i64();
+ftmp3 = tcg_temp_new_i64();
+tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF,
zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF,
zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF,
zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+tcg_temp_free_i64(ftmp1);
+tcg_temp_free_i64(ftmp2);
+tcg_temp_free_i64(ftmp3);
+} else {
+TCGv_i32 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i32();
+ftmp2 = tcg_temp_new_i32();
+ftmp3 = tcg_temp_new_i32();
+tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF,
zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF,
zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF,
zero,
+
[Qemu-devel] [PATCH v3] target-arm: Implement ARMv8 VSEL instruction.
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton will.new...@linaro.org
---
target-arm/translate.c | 115 ++---
1 file changed, 110 insertions(+), 5 deletions(-)
Changes in v3:
- Move calls to disas_vfp_insn out of disas_coproc_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..10b4fac 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2880,6 +2880,99 @@ static int disas_vfp_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
rm = VFP_SREG_M(insn);
}
+if ((insn 0x0f800e50) == 0x0e000a00) {
+/* vsel */
+uint32_t cc = (insn 20) 3;
+TCGv_i32 tmp, zero;
+
+/* ARMv8 VFP. */
+if (!arm_feature(env, ARM_FEATURE_V8)) {
+return 1;
+}
+
+zero = tcg_const_tl(0);
+
+if (dp) {
+TCGv_i64 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i64();
+ftmp2 = tcg_temp_new_i64();
+ftmp3 = tcg_temp_new_i64();
+tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+tcg_temp_free_i64(ftmp1);
+tcg_temp_free_i64(ftmp2);
+tcg_temp_free_i64(ftmp3);
+} else {
+TCGv_i32 ftmp1, ftmp2, ftmp3;
+
+ftmp1 = tcg_temp_new_i32();
+ftmp2 = tcg_temp_new_i32();
+ftmp3 = tcg_temp_new_i32();
+tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn));
+tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm));
+switch (cc) {
+case 0: /* eq: Z */
+tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+break;
+case 1: /* vs: V */
+tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero,
+ftmp1, ftmp2);
+break;
+case 2: /* ge: N == V - N ^ V == 0 */
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp1, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+case 3: /* gt: !Z N == V */
+tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero,
+ftmp1, ftmp2);
+tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero,
+ftmp3, ftmp2);
+tcg_temp_free_i32(tmp);
+break;
+}
+tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd));
+tcg_temp_free_i32(ftmp1);
+tcg_temp_free_i32(ftmp2);
+tcg_temp_free_i32(ftmp3);
+
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 3 October 2013 23:31, Will Newton will.new...@linaro.org wrote: On 3 October 2013 13:59, Peter Maydell peter.mayd...@linaro.org wrote: This isn't what I meant. If our decoding matches up with the ARM ARM then this instruction pattern should already fall into disas_vfp_insn(), and we shouldn't need an extra check and call. (If it's not correct then we should adjust our decode so it does.) I'll respin the patch pulling the calls to disas_vfp_insn up a level which I think you alluded to in the original review. It still needs an additional call to disas_vfp_insn in the ARM case as condition code == 0xf is dealt with separately from the others. Let me know if this is not what you were looking for. Ah, that means the ARM ARM table is incorrect, because it implies that VSEL is conditional (which it definitely isn't). I need to look at where the new insns are in the T32/A32 encodings in more detail, then, which I don't have time for just at the moment. Pulling the disas_vfp_insn calls out of disas_coproc is a good idea anyway, though (it should be a separate patch to the one which adds VSEL). -- PMM
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 10/03/2013 05:51 AM, Will Newton wrote: +case 0: /* eq: Z */ +tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero, +ftmp1, ftmp2); +break; Does this compile when configured with --enable-debug? It shouldn't, since movcond_i64 takes 5 _i64 variables, and your comparison variables are _i32. r~
Re: [Qemu-devel] [Bug 1180777] Re: RDP traffic freeze on quiet network
Quoting Vasile Dumitrescu (launchpad.vas...@undeva.net): I added a rtl8139c netcard to the VM and connected through it by RDP - no more freezes. It looks like kvm does not play well with virtio network cards and RDP. Red Hat virtio net windows driver version: 62.65.104.6500, 6/19/2013 This makes me wonder if the bug may not actually be in the virtio net driver. The source for that is at https://github.com/YanVugenfirer/kvm-guest-drivers-windows . Something like commit 9b1b81a731f722efa8df24429649b527a17bf433 might be relevant (assuming the git HEAD has this fixed, which I've not tested). -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1180777 Title: RDP traffic freeze on quiet network Status in QEMU: New Status in “qemu-kvm” package in Ubuntu: Confirmed Status in Debian GNU/Linux: New Bug description: To summarize what I think has been found so far, 1. The main symptom is that RDP connections hang after some time 2. This bug affects qemu 1.0 .. 1.6.5 3. This bug affects at least windows xp and windows 7 guests 4. Keeping another network connection open, such as vnc, prevents the RDP connection from hanging. Hi, I have recently setup a Windows 7 VM on KVM and started using it through remote desktop. What happens is that, after some hours of usage, the remote desktop connection freezes. I thought it was a remmina bug, as the it was enough to kill and restart it to successfully connect again to the VM. However, today I've switched to a different RDP client (2X Client chromium app) and the freeze just happened again! Some information: - the host and the VM are completely idle when the freeze occurs - I've tried sniffing the network packets toward the RDP port during the freeze and found that the client is sending packets but no packet is sent back Could this be a KVM issue? How can I further debug this one (I expect the freeze to happen again...)? ProblemType: Bug DistroRelease: Ubuntu 12.04 Package: kvm 1:84+dfsg-0ubuntu16+1.0+noroms+0ubuntu14.8 ProcVersionSignature: Ubuntu 3.2.0-41.66-generic 3.2.42 Uname: Linux 3.2.0-41-generic x86_64 ApportVersion: 2.0.1-0ubuntu17.2 Architecture: amd64 Date: Thu May 16 14:12:40 2013 MachineType: Hewlett-Packard HP ProBook 4520s MarkForUpload: True ProcEnviron: TERM=xterm PATH=(custom, no user) LANG=en_US.UTF-8 SHELL=/bin/bash ProcKernelCmdLine: BOOT_IMAGE=/boot/vmlinuz-3.2.0-41-generic root=UUID=D2E20BC3E20BAAB5 loop=/hostname/disks/root.disk ro quiet splash vt.handoff=7 SourcePackage: qemu-kvm UpgradeStatus: No upgrade log present (probably fresh install) dmi.bios.date: 08/26/2010 dmi.bios.vendor: Hewlett-Packard dmi.bios.version: 68AZZ Ver. F.0A dmi.board.name: 1411 dmi.board.vendor: Hewlett-Packard dmi.board.version: KBC Version 57.30 dmi.chassis.type: 10 dmi.chassis.vendor: Hewlett-Packard dmi.modalias: dmi:bvnHewlett-Packard:bvr68AZZVer.F.0A:bd08/26/2010:svnHewlett-Packard:pnHPProBook4520s:pvr:rvnHewlett-Packard:rn1411:rvrKBCVersion57.30:cvnHewlett-Packard:ct10:cvr: dmi.product.name: HP ProBook 4520s dmi.sys.vendor: Hewlett-Packard To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1180777/+subscriptions
Re: [Qemu-devel] [PATCH RFC 04/11] s390/qemu: cpu model cpu facilitiy support
On 10/02/2013 04:33 AM, Michael Mueller wrote:
+/* set a specific bit in facility set */
+static void set_facility(unsigned int nr, void *facilities)
+{
+unsigned char *ptr;
+
+if (nr = MAX_S390_FACILITY_BIT) {
+return;
+}
+ptr = (unsigned char *) facilities + (nr 3);
+*ptr |= (0x80 (nr 7));
+}
I'd like to see this done in a host endian independent way.
See my recent patch set to add facility support to the tcg side
of target-s390, with which this patch set is going to conflict.
Is there a good reason not to compute these facility masks at
compile-time? See
http://patchwork.ozlabs.org/patch/279534/
where I have pre-computed (possibly incomplete) facilities lists
for the major cpu revisions.
It just seems like your facility_availability array is the wrong
way to go about things, taking up more memory and startup time
than necessary.
r~
[Qemu-devel] [PATCH v8 00/26] qemu: generate acpi tables for the guest
I sent v7 only today but that submission was botched: v7 was already sent yesterday, and missed a typo reported by Eric. Besides, I fixed whitespace issues noted by Igor. Resending properly, sorry about the noise. This code can also be found here: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi While this patch still uses info not available in QOM, I think it's reasonable to merge it and then refactor as QOM properties cover more ground. In particular, merging this patchset blocks other projects so I think its preferable to merge now and not wait for all required QOM properties to materialize. I added QOM properties in ich/piix where I knew how to do this. If you already reviewed v5 then the only patches that changed are: i386: define pc guest info i386: ACPI table generation code from seabios Gerd, Laszlo, I kept you Reviewed-by and Tested-by tags on these patches to ensure your contribution is recongnized, if you don't like this pls let me know. Or better yet re-ack this version :) Patches 1-3 are QOM patches really. Included here for completeness. Igor suggested dropping patches 1-2 and including error.h directly. I included his patch and dropped mine. I hope that's ok. If everything's in order, I intend to merge this through my tree. Please review, and comment. Changes from v7 reposted: - whitespace fixes - issues reported by Igor - typo fix in commit log reported by Eric Changes from v7: - removed all complex table patching and migration code we now only migrate a single byte patched/non patched all tables are simply regenerated on access, rewriting old data in particular this fixed a bug that Igor noticed: cpu online status is now updated correctly - removed bitmask of found cpus - use QOM to calculate it - dropped changes to typedefs.h - use Igor's patch instead Changes from v6: - fix 64 bit window bug reported by Igor - tweak comments in error.h Changes from v5: - update generated files to fix build on systems without iasl - fix mcfg failure reported by Gerd Changes from v4: - address comments by Paolo: rename loader interface reuse macro for hpet name better struct names move internal headers to hw/i386/ - fix typos resulting in bugs reported by Gerd Changes from v3: - reworked code to use QOM properties some info isn't yet available in QOM, use old-style APIs and lookups by type - address comments by Gerd: tables are now updated on guest access after pci configuration Changes from v2 repost: - address comment by Anthony - convert to use APIs implemented using QOM - address comment by Anthony - avoid tricky pointer path, use GArray from glib instead - Address lots of comments by Hu Tao and Laszlo Ersek Changes from v2: - added missing patches to make it actually build Changes from v1 RFC: - added code to address cross version compatibility - rebased to latest bits - updated seabios code to latest bits (added pvpanic device) This patchset moves all generation of ACPI tables from guest BIOS to the hypervisor. Although ACPI tables come from a system BIOS on real hw, it makes sense that the ACPI tables are coupled with the virtual machine, since they have to abstract the x86 machine to the OS's. This is widely desired as a way to avoid the churn and proliferation of QEMU-specific interfaces associated with ACPI tables in bios code. There's a bit of code duplication where we already declare similar acpi structures in qemu. I think it's best to do it in this order: port code directly, and apply cleanups and reduce duplication that results, on top. This way it's much easier to see that we don't introduce regressions. In particular, I booted a guest on qemu with and without the change, and verified that ACPI tables are unchanged except for trivial pointer address changes, and the SSDT P_BLK change in the last patch. Such binary compatibility makes it easier to be confident that this change won't break things. Igor Mammedov (1): cleanup object.h: include error.h directly Michael S. Tsirkin (25): qom: cleanup struct Error references qom: add pointer to int property helpers pci: fix up w64 size calculation helper fw_cfg: interface to trigger callback on read loader: support for unmapped ROM blobs pcie_host: expose UNMAPPED macro pcie_host: expose address format q35: use macro for MCFG property name q35: expose mmcfg size as a property i386: add ACPI table files from seabios acpi: add rules to compile ASL source acpi: pre-compiled ASL files acpi: ssdt pcihp: updat generated file loader: use file path size from fw_cfg.h i386: add bios linker/loader loader: allow adding ROMs in done callbacks i386: define pc guest info acpi/piix: add macros for acpi property names piix: APIs for pc guest info ich9: APIs for pc guest info pvpanic: add API to access io port hpet: add API to find it i386: ACPI table generation code from seabios ssdt: fix PBLK length ssdt-proc: update generated file
[Qemu-devel] [PATCH v8 04/26] pci: fix up w64 size calculation helper
BAR base was calculated incorrectly.
Use existing pci_bar_address to get it right.
Tested-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/pci/pci.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 00554a0..c3fdff4 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2264,7 +2264,7 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev,
void *opaque)
Range *range = opaque;
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
uint16_t cmd = pci_get_word(dev-config + PCI_COMMAND);
-int r;
+int i;
if (!(cmd PCI_COMMAND_MEMORY)) {
return;
@@ -2283,17 +2283,21 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev,
void *opaque)
range_extend(range, pref_range);
}
}
-for (r = 0; r PCI_NUM_REGIONS; ++r) {
-PCIIORegion *region = dev-io_regions[r];
+for (i = 0; i PCI_NUM_REGIONS; ++i) {
+PCIIORegion *r = dev-io_regions[i];
Range region_range;
-if (!region-size ||
-(region-type PCI_BASE_ADDRESS_SPACE_IO) ||
-!(region-type PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+if (!r-size ||
+(r-type PCI_BASE_ADDRESS_SPACE_IO) ||
+!(r-type PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+continue;
+}
+region_range.begin = pci_bar_address(dev, i, r-type, r-size);
+region_range.end = region_range.begin + r-size;
+
+if (region_range.begin == PCI_BAR_UNMAPPED) {
continue;
}
-region_range.begin = pci_get_quad(dev-config + pci_bar(dev, r));
-region_range.end = region_range.begin + region-size;
region_range.begin = MAX(region_range.begin, 0x1ULL 32);
--
MST
[Qemu-devel] [PATCH v8 02/26] qom: cleanup struct Error references
now that a typedef for struct Error is available, use it in qom/object.h to match coding style rules. Reviewed-by: Paolo Bonzini pbonz...@redhat.com Reviewed-by: Gerd Hoffmann kra...@redhat.com Tested-by: Gerd Hoffmann kra...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/qom/object.h | 50 +- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/include/qom/object.h b/include/qom/object.h index d9a0063..6c1e7d3 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -301,7 +301,7 @@ typedef void (ObjectPropertyAccessor)(Object *obj, struct Visitor *v, void *opaque, const char *name, - struct Error **errp); + Error **errp); /** * ObjectPropertyRelease: @@ -790,9 +790,9 @@ void object_property_add(Object *obj, const char *name, const char *type, ObjectPropertyAccessor *get, ObjectPropertyAccessor *set, ObjectPropertyRelease *release, - void *opaque, struct Error **errp); + void *opaque, Error **errp); -void object_property_del(Object *obj, const char *name, struct Error **errp); +void object_property_del(Object *obj, const char *name, Error **errp); /** * object_property_find: @@ -803,7 +803,7 @@ void object_property_del(Object *obj, const char *name, struct Error **errp); * Look up a property for an object and return its #ObjectProperty if found. */ ObjectProperty *object_property_find(Object *obj, const char *name, - struct Error **errp); + Error **errp); void object_unparent(Object *obj); @@ -818,7 +818,7 @@ void object_unparent(Object *obj); * Reads a property from a object. */ void object_property_get(Object *obj, struct Visitor *v, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_str: @@ -829,7 +829,7 @@ void object_property_get(Object *obj, struct Visitor *v, const char *name, * Writes a string value to a property. */ void object_property_set_str(Object *obj, const char *value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_str: @@ -842,7 +842,7 @@ void object_property_set_str(Object *obj, const char *value, * The caller should free the string. */ char *object_property_get_str(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_link: @@ -853,7 +853,7 @@ char *object_property_get_str(Object *obj, const char *name, * Writes an object's canonical path to a property. */ void object_property_set_link(Object *obj, Object *value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_link: @@ -866,7 +866,7 @@ void object_property_set_link(Object *obj, Object *value, * string or not a valid object path). */ Object *object_property_get_link(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_bool: @@ -877,7 +877,7 @@ Object *object_property_get_link(Object *obj, const char *name, * Writes a bool value to a property. */ void object_property_set_bool(Object *obj, bool value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_bool: @@ -889,7 +889,7 @@ void object_property_set_bool(Object *obj, bool value, * an error occurs (including when the property value is not a bool). */ bool object_property_get_bool(Object *obj, const char *name, - struct Error **errp); + Error **errp); /** * object_property_set_int: @@ -900,7 +900,7 @@ bool object_property_get_bool(Object *obj, const char *name, * Writes an integer value to a property. */ void object_property_set_int(Object *obj, int64_t value, - const char *name, struct Error **errp); + const char *name, Error **errp); /** * object_property_get_int: @@ -912,7 +912,7 @@ void object_property_set_int(Object *obj, int64_t value, * an error occurs (including when the property value is not an integer). */ int64_t object_property_get_int(Object *obj, const char *name, -struct Error **errp); +Error **errp);
[Qemu-devel] [PATCH v8 10/26] q35: expose mmcfg size as a property
Address is already exposed, expose size for symmetry.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 1 +
hw/pci-host/q35.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 33d75bd..acca45e 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -29,6 +29,7 @@
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
#define PCIE_HOST_MCFG_BASE MCFG
+#define PCIE_HOST_MCFG_SIZE mcfg_size
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index e46f286..a051b58 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj,
Visitor *v,
visit_type_uint64(v, w64.end, name, errp);
}
+static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
+void *opaque, const char *name,
+Error **errp)
+{
+PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
+uint32_t value = e-size;
+
+visit_type_uint32(v, value, name, errp);
+}
+
static Property mch_props[] = {
DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
@@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj)
q35_host_get_pci_hole64_end,
NULL, NULL, NULL, NULL);
+object_property_add(obj, PCIE_HOST_MCFG_SIZE, int,
+q35_host_get_mmcfg_size,
+NULL, NULL, NULL, NULL);
+
/* Leave enough space for the biggest MCFG BAR */
/* TODO: this matches current bios behaviour, but
* it's not a power of two, which means an MTRR
--
MST
[Qemu-devel] [PATCH v8 01/26] cleanup object.h: include error.h directly
From: Igor Mammedov imamm...@redhat.com qapi/error.h is simple enough to be included in qom/object.h direcly and prepares qom/object.h to use Error typedef. Signed-off-by: Igor Mammedov imamm...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qom/object.h b/include/qom/object.h index 1a7b71a..d9a0063 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -18,9 +18,9 @@ #include stdint.h #include stdbool.h #include qemu/queue.h +#include qapi/error.h struct Visitor; -struct Error; struct TypeImpl; typedef struct TypeImpl *Type; -- MST
[Qemu-devel] [PATCH v8 05/26] fw_cfg: interface to trigger callback on read
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/nvram/fw_cfg.h | 4
hw/nvram/fw_cfg.c | 33 -
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index f60dd67..2ab0fc2 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -60,6 +60,7 @@ typedef struct FWCfgFiles {
} FWCfgFiles;
typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
+typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset);
void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len);
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value);
@@ -70,6 +71,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
void *callback_opaque, void *data, size_t len);
void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
size_t len);
+void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
+ FWCfgReadCallback callback, void
*callback_opaque,
+ void *data, size_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
hwaddr crl_addr, hwaddr data_addr);
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index d0820e5..f5dc3ea 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -42,6 +42,7 @@ typedef struct FWCfgEntry {
uint8_t *data;
void *callback_opaque;
FWCfgCallback callback;
+FWCfgReadCallback read_callback;
} FWCfgEntry;
struct FWCfgState {
@@ -249,8 +250,12 @@ static uint8_t fw_cfg_read(FWCfgState *s)
if (s-cur_entry == FW_CFG_INVALID || !e-data || s-cur_offset = e-len)
ret = 0;
-else
+else {
+if (e-read_callback) {
+e-read_callback(e-callback_opaque, s-cur_offset);
+}
ret = e-data[s-cur_offset++];
+}
trace_fw_cfg_read(s, ret);
return ret;
@@ -381,7 +386,10 @@ static const VMStateDescription vmstate_fw_cfg = {
}
};
-void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
+ FWCfgReadCallback callback,
+ void *callback_opaque,
+ void *data, size_t len)
{
int arch = !!(key FW_CFG_ARCH_LOCAL);
@@ -391,6 +399,13 @@ void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void
*data, size_t len)
s-entries[arch][key].data = data;
s-entries[arch][key].len = (uint32_t)len;
+s-entries[arch][key].read_callback = callback;
+s-entries[arch][key].callback_opaque = callback_opaque;
+}
+
+void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+{
+fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len);
}
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
@@ -444,8 +459,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
s-entries[arch][key].callback = callback;
}
-void fw_cfg_add_file(FWCfgState *s, const char *filename,
- void *data, size_t len)
+void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
+ FWCfgReadCallback callback, void
*callback_opaque,
+ void *data, size_t len)
{
int i, index;
size_t dsize;
@@ -459,7 +475,8 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename,
index = be32_to_cpu(s-files-count);
assert(index FW_CFG_FILE_SLOTS);
-fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len);
+fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
+ callback, callback_opaque, data, len);
pstrcpy(s-files-f[index].name, sizeof(s-files-f[index].name),
filename);
@@ -477,6 +494,12 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename,
s-files-count = cpu_to_be32(index+1);
}
+void fw_cfg_add_file(FWCfgState *s, const char *filename,
+ void *data, size_t len)
+{
+fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
+}
+
static void fw_cfg_machine_ready(struct Notifier *n, void *data)
{
size_t len;
--
MST
[Qemu-devel] [PATCH v8 14/26] acpi: ssdt pcihp: updat generated file
update generated file, not sure what changed
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-pcihp.hex.generated | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
index 0d32a27..b3c2cd5 100644
--- a/hw/i386/ssdt-pcihp.hex.generated
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -17,7 +17,7 @@ static unsigned char ssdp_pcihp_aml[] = {
0x0,
0x0,
0x1,
-0x77,
+0x76,
0x42,
0x58,
0x50,
@@ -40,9 +40,9 @@ static unsigned char ssdp_pcihp_aml[] = {
0x4e,
0x54,
0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
0x20,
0x10,
0x33,
--
MST
[Qemu-devel] [PATCH v8 06/26] loader: support for unmapped ROM blobs
Support ROM blobs not mapped into guest memory:
same as ROM files really but use caller's buffer.
Support incoking callback on access and
return memory pointer making it easier
for caller to update memory if necessary.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Reviewed-by: Laszlo Ersek ler...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/lm32/lm32_hwsetup.h | 2 +-
include/hw/loader.h| 7 ---
hw/core/loader.c | 23 ---
3 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h
index 3449bd8..9fd5e69 100644
--- a/hw/lm32/lm32_hwsetup.h
+++ b/hw/lm32/lm32_hwsetup.h
@@ -73,7 +73,7 @@ static inline void hwsetup_free(HWSetup *hw)
static inline void hwsetup_create_rom(HWSetup *hw,
hwaddr base)
{
-rom_add_blob(hwsetup, hw-data, TARGET_PAGE_SIZE, base);
+rom_add_blob(hwsetup, hw-data, TARGET_PAGE_SIZE, base, NULL, NULL,
NULL);
}
static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 6145736..e0c576b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -40,8 +40,9 @@ extern bool rom_file_in_ram;
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex);
-int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr);
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+ hwaddr addr, const char *fw_file_name,
+ FWCfgReadCallback fw_callback, void *callback_opaque);
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
@@ -53,7 +54,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
#define rom_add_file_fixed(_f, _a, _i) \
rom_add_file(_f, NULL, _a, _i)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
-rom_add_blob(_f, _b, _l, _a)
+(rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) ? 0 : -1)
#define PC_ROM_MIN_VGA 0xc
#define PC_ROM_MIN_OPTION 0xc8000
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 7b3d3ee..449bd4c 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -700,10 +700,12 @@ err:
return -1;
}
-int rom_add_blob(const char *name, const void *blob, size_t len,
- hwaddr addr)
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+ hwaddr addr, const char *fw_file_name,
+ FWCfgReadCallback fw_callback, void *callback_opaque)
{
Rom *rom;
+void *data = NULL;
rom = g_malloc0(sizeof(*rom));
rom-name = g_strdup(name);
@@ -713,7 +715,22 @@ int rom_add_blob(const char *name, const void *blob,
size_t len,
rom-data = g_malloc0(rom-datasize);
memcpy(rom-data, blob, len);
rom_insert(rom);
-return 0;
+if (fw_file_name fw_cfg) {
+char devpath[100];
+
+snprintf(devpath, sizeof(devpath), /rom@%s, fw_file_name);
+
+if (rom_file_in_ram) {
+data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
+} else {
+data = rom-data;
+}
+
+fw_cfg_add_file_callback(fw_cfg, fw_file_name,
+ fw_callback, callback_opaque,
+ data, rom-romsize);
+}
+return data;
}
/* This function is specific for elf program because we don't need to allocate
--
MST
[Qemu-devel] [PATCH v8 15/26] loader: use file path size from fw_cfg.h
Avoid a bit of code duplication, make
max file path constant reusable.
Suggested-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/nvram/fw_cfg.h | 4 +++-
hw/core/loader.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 2ab0fc2..72b1549 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -46,12 +46,14 @@
#define FW_CFG_INVALID 0x
+#define FW_CFG_MAX_FILE_PATH56
+
#ifndef NO_QEMU_PROTOS
typedef struct FWCfgFile {
uint32_t size;/* file size */
uint16_t select; /* write this to 0x510 to read it */
uint16_t reserved;
-char name[56];
+char name[FW_CFG_MAX_FILE_PATH];
} FWCfgFile;
typedef struct FWCfgFiles {
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 449bd4c..060729f 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -663,7 +663,7 @@ int rom_add_file(const char *file, const char *fw_dir,
rom_insert(rom);
if (rom-fw_file fw_cfg) {
const char *basename;
-char fw_file_name[56];
+char fw_file_name[FW_CFG_MAX_FILE_PATH];
void *data;
basename = strrchr(rom-fw_file, '/');
--
MST
[Qemu-devel] [PATCH v8 07/26] pcie_host: expose UNMAPPED macro
Make it possible to test unmapped status through QMP.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 3 +++
hw/pci/pcie_host.c | 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 1228e36..bac3c67 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,9 @@
#define PCIE_HOST_BRIDGE(obj) \
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
+#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
+
struct PCIExpressHost {
PCIHostState pci;
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index b70e5ad..410ac08 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -104,9 +104,6 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
-
int pcie_host_init(PCIExpressHost *e)
{
e-base_addr = PCIE_BASE_ADDR_UNMAPPED;
--
MST
[Qemu-devel] [PATCH v8 08/26] pcie_host: expose address format
Callers pass in the address so it's helpful for them to be able to decode it. Reviewed-by: Gerd Hoffmann kra...@redhat.com Tested-by: Gerd Hoffmann kra...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- include/hw/pci/pcie_host.h | 21 + hw/pci/pcie_host.c | 21 - 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index bac3c67..da0f275 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -54,4 +54,25 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, hwaddr addr, uint32_t size); +/* + * PCI express ECAM (Enhanced Configuration Address Mapping) format. + * AKA mmcfg address + * bit 20 - 28: bus number + * bit 15 - 19: device number + * bit 12 - 14: function number + * bit 0 - 11: offset in configuration space of a given device + */ +#define PCIE_MMCFG_SIZE_MAX (1ULL 28) +#define PCIE_MMCFG_SIZE_MIN (1ULL 20) +#define PCIE_MMCFG_BUS_BIT 20 +#define PCIE_MMCFG_BUS_MASK 0x1ff +#define PCIE_MMCFG_DEVFN_BIT12 +#define PCIE_MMCFG_DEVFN_MASK 0xff +#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff +#define PCIE_MMCFG_BUS(addr)(((addr) PCIE_MMCFG_BUS_BIT) \ + PCIE_MMCFG_BUS_MASK) +#define PCIE_MMCFG_DEVFN(addr) (((addr) PCIE_MMCFG_DEVFN_BIT) \ + PCIE_MMCFG_DEVFN_MASK) +#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) PCIE_MMCFG_CONFOFFSET_MASK) + #endif /* PCIE_HOST_H */ diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 410ac08..c6e1b57 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -24,27 +24,6 @@ #include hw/pci/pcie_host.h #include exec/address-spaces.h -/* - * PCI express mmcfig address - * bit 20 - 28: bus number - * bit 15 - 19: device number - * bit 12 - 14: function number - * bit 0 - 11: offset in configuration space of a given device - */ -#define PCIE_MMCFG_SIZE_MAX (1ULL 28) -#define PCIE_MMCFG_SIZE_MIN (1ULL 20) -#define PCIE_MMCFG_BUS_BIT 20 -#define PCIE_MMCFG_BUS_MASK 0x1ff -#define PCIE_MMCFG_DEVFN_BIT12 -#define PCIE_MMCFG_DEVFN_MASK 0xff -#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff -#define PCIE_MMCFG_BUS(addr)(((addr) PCIE_MMCFG_BUS_BIT) \ - PCIE_MMCFG_BUS_MASK) -#define PCIE_MMCFG_DEVFN(addr) (((addr) PCIE_MMCFG_DEVFN_BIT) \ - PCIE_MMCFG_DEVFN_MASK) -#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) PCIE_MMCFG_CONFOFFSET_MASK) - - /* a helper function to get a PCIDevice for a given mmconfig address */ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, uint32_t mmcfg_addr) -- MST
[Qemu-devel] [PATCH v8 16/26] i386: add bios linker/loader
This adds a dynamic bios linker/loader.
This will be used by acpi table generation
code to:
- load each table in the appropriate memory segment
- link tables to each other
- fix up checksums after said linking
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/bios-linker-loader.h | 27
hw/i386/bios-linker-loader.c | 158 +++
hw/i386/Makefile.objs| 1 +
3 files changed, 186 insertions(+)
create mode 100644 hw/i386/bios-linker-loader.h
create mode 100644 hw/i386/bios-linker-loader.c
diff --git a/hw/i386/bios-linker-loader.h b/hw/i386/bios-linker-loader.h
new file mode 100644
index 000..498c0af
--- /dev/null
+++ b/hw/i386/bios-linker-loader.h
@@ -0,0 +1,27 @@
+#ifndef BIOS_LINKER_LOADER_H
+#define BIOS_LINKER_LOADER_H
+
+#include glib.h
+#include stdbool.h
+#include inttypes.h
+
+GArray *bios_linker_loader_init(void);
+
+void bios_linker_loader_alloc(GArray *linker,
+ const char *file,
+ uint32_t alloc_align,
+ bool alloc_fseg);
+
+void bios_linker_loader_add_checksum(GArray *linker, const char *file,
+ void *table,
+ void *start, unsigned size,
+ uint8_t *checksum);
+
+void bios_linker_loader_add_pointer(GArray *linker,
+const char *dest_file,
+const char *src_file,
+GArray *table, void *pointer,
+uint8_t pointer_size);
+
+void *bios_linker_loader_cleanup(GArray *linker);
+#endif
diff --git a/hw/i386/bios-linker-loader.c b/hw/i386/bios-linker-loader.c
new file mode 100644
index 000..0833853
--- /dev/null
+++ b/hw/i386/bios-linker-loader.c
@@ -0,0 +1,158 @@
+/* Dynamic linker/loader of ACPI tables
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin m...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+
+#include bios-linker-loader.h
+#include hw/nvram/fw_cfg.h
+
+#include string.h
+#include assert.h
+#include qemu/bswap.h
+
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+struct BiosLinkerLoaderEntry {
+uint32_t command;
+union {
+/*
+ * COMMAND_ALLOCATE - allocate a table from @alloc.file
+ * subject to @alloc.align alignment (must be power of 2)
+ * and @alloc.zone (can be HIGH or FSEG) requirements.
+ *
+ * Must appear exactly once for each file, and before
+ * this file is referenced by any other command.
+ */
+struct {
+char file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t align;
+uint8_t zone;
+} alloc;
+
+/*
+ * COMMAND_ADD_POINTER - patch the table (originating from
+ * @dest_file) at @pointer.offset, by adding a pointer to the table
+ * originating from @src_file. 1,2,4 or 8 byte unsigned
+ * addition is used depending on @pointer.size.
+ */
+struct {
+char dest_file[BIOS_LINKER_LOADER_FILESZ];
+char src_file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t offset;
+uint8_t size;
+} pointer;
+
+/*
+ * COMMAND_ADD_CHECKSUM - calculate checksum of the range specified by
+ * @cksum_start and @cksum_length fields,
+ * and then add the value at @cksum.offset.
+ * Checksum simply sums -X for each byte X in the range
+ * using 8-bit math.
+ */
+struct {
+char file[BIOS_LINKER_LOADER_FILESZ];
+uint32_t offset;
+uint32_t start;
+uint32_t length;
+} cksum;
+
+/* padding */
+char pad[124];
+};
+} QEMU_PACKED;
+typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
+
+enum {
+BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
+BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
+BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+GArray *bios_linker_loader_init(void)
+{
+return
[Qemu-devel] [PATCH v8 09/26] q35: use macro for MCFG property name
Useful to make it accessible through QOM.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/pci/pcie_host.h | 2 ++
hw/pci-host/q35.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index da0f275..33d75bd 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,8 @@
#define PCIE_HOST_BRIDGE(obj) \
OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+#define PCIE_HOST_MCFG_BASE MCFG
+
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 23dbeea..e46f286 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -110,7 +110,7 @@ static void q35_host_get_pci_hole64_end(Object *obj,
Visitor *v,
}
static Property mch_props[] = {
-DEFINE_PROP_UINT64(MCFG, Q35PCIHost, parent_obj.base_addr,
+DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
--
MST
[Qemu-devel] [PATCH v8 23/26] hpet: add API to find it
Add API to find HPET using QOM.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/timer/hpet.h | 2 ++
hw/timer/hpet.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
index 757f79f..ab44bd3 100644
--- a/include/hw/timer/hpet.h
+++ b/include/hw/timer/hpet.h
@@ -71,4 +71,6 @@ struct hpet_fw_config
} QEMU_PACKED;
extern struct hpet_fw_config hpet_cfg;
+
+bool hpet_find(void);
#endif
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index fcd22ae..2eb75ea 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -757,6 +757,11 @@ static void hpet_device_class_init(ObjectClass *klass,
void *data)
dc-props = hpet_device_properties;
}
+bool hpet_find(void)
+{
+return object_resolve_path_type(, TYPE_HPET, NULL);
+}
+
static const TypeInfo hpet_device_info = {
.name = TYPE_HPET,
.parent= TYPE_SYS_BUS_DEVICE,
--
MST
[Qemu-devel] [PATCH v8 18/26] i386: define pc guest info
This defines a structure that will be used to fill in acpi tables
where relevant properties are not yet available using QOM.
Reviewed-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 9 +
hw/i386/pc.c | 31 +++
2 files changed, 40 insertions(+)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9b2ddc4..085a621 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -9,6 +9,9 @@
#include hw/i386/ioapic.h
#include qemu/range.h
+#include qemu/bitmap.h
+#include sysemu/sysemu.h
+#include hw/pci/pci.h
/* PC-style peripherals (also used by other machines). */
@@ -20,6 +23,12 @@ typedef struct PcPciInfo {
struct PcGuestInfo {
bool has_pci_info;
bool isapc_ram_fw;
+hwaddr ram_size;
+unsigned apic_id_limit;
+bool apic_xrupt_override;
+uint64_t numa_nodes;
+uint64_t *node_mem;
+uint64_t *node_cpu;
FWCfgState *fw_cfg;
};
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0c313fe..dbae9da 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1028,6 +1028,23 @@ static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
fw_cfg_add_file(guest_info-fw_cfg, etc/pci-info, info, sizeof *info);
}
+static void pc_set_cpu_guest_info(CPUState *cpu, PcGuestInfo *guest_info)
+{
+CPUClass *klass = CPU_GET_CLASS(cpu);
+uint64_t apic_id = klass-get_arch_id(cpu);
+int j;
+
+assert(apic_id guest_info-apic_id_limit);
+
+for (j = 0; j guest_info-numa_nodes; j++) {
+assert(cpu-cpu_index max_cpus);
+if (test_bit(cpu-cpu_index, node_cpumask[j])) {
+guest_info-node_cpu[apic_id] = cpu_to_le64(j);
+break;
+}
+}
+}
+
typedef struct PcGuestInfoState {
PcGuestInfo info;
Notifier machine_done;
@@ -1047,6 +1064,20 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
{
PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
PcGuestInfo *guest_info = guest_info_state-info;
+CPUState *cpu;
+
+guest_info-ram_size = below_4g_mem_size + above_4g_mem_size;
+guest_info-apic_id_limit = pc_apic_id_limit(max_cpus);
+guest_info-apic_xrupt_override = kvm_allows_irq0_override();
+guest_info-numa_nodes = nb_numa_nodes;
+guest_info-node_mem = g_memdup(node_mem, guest_info-numa_nodes *
+sizeof *guest_info-node_mem);
+guest_info-node_cpu = g_malloc0(guest_info-apic_id_limit *
+ sizeof *guest_info-node_cpu);
+
+CPU_FOREACH(cpu) {
+pc_set_cpu_guest_info(cpu, guest_info);
+}
guest_info_state-machine_done.notify = pc_guest_info_machine_done;
qemu_add_machine_init_done_notifier(guest_info_state-machine_done);
--
MST
[Qemu-devel] [PATCH v8 25/26] ssdt: fix PBLK length
We don't really support CPU throttling, so supply 0 PBLK length.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-proc.dsl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/ssdt-proc.dsl b/hw/i386/ssdt-proc.dsl
index 58333c7..8229bfd 100644
--- a/hw/i386/ssdt-proc.dsl
+++ b/hw/i386/ssdt-proc.dsl
@@ -37,7 +37,7 @@ DefinitionBlock (ssdt-proc.aml, SSDT, 0x01, BXPC,
BXSSDT, 0x1)
ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
-Processor(CPAA, 0xAA, 0xb010, 0x06) {
+Processor(CPAA, 0xAA, 0x, 0x0) {
ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
Name(ID, 0xAA)
/*
--
MST
[Qemu-devel] [PATCH v8 19/26] acpi/piix: add macros for acpi property names
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 10 ++
hw/acpi/piix4.c | 6 +++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 085a621..5aefc5b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -20,6 +20,16 @@ typedef struct PcPciInfo {
Range w64;
} PcPciInfo;
+#define ACPI_PM_PROP_S3_DISABLED disable_s3
+#define ACPI_PM_PROP_S4_DISABLED disable_s4
+#define ACPI_PM_PROP_S4_VAL s4_val
+#define ACPI_PM_PROP_SCI_INT sci_int
+#define ACPI_PM_PROP_ACPI_ENABLE_CMD acpi_enable_cmd
+#define ACPI_PM_PROP_ACPI_DISABLE_CMD acpi_disable_cmd
+#define ACPI_PM_PROP_PM_IO_BASE pm_io_base
+#define ACPI_PM_PROP_GPE0_BLK gpe0_blk
+#define ACPI_PM_PROP_GPE0_BLK_LEN gpe0_blk_len
+
struct PcGuestInfo {
bool has_pci_info;
bool isapc_ram_fw;
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index b46bd5e..4b8c1da 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -489,9 +489,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
smb_io_base,
static Property piix4_pm_properties[] = {
DEFINE_PROP_UINT32(smb_io_base, PIIX4PMState, smb_io_base, 0),
-DEFINE_PROP_UINT8(disable_s3, PIIX4PMState, disable_s3, 0),
-DEFINE_PROP_UINT8(disable_s4, PIIX4PMState, disable_s4, 0),
-DEFINE_PROP_UINT8(s4_val, PIIX4PMState, s4_val, 2),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
+DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
DEFINE_PROP_END_OF_LIST(),
};
--
MST
[Qemu-devel] [PATCH v8 20/26] piix: APIs for pc guest info
This adds APIs that will be used to fill in guest acpi tables.
Some required information is still lacking in QOM, so we
fall back on lookups by type and returning explicit types.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/acpi/piix4.h | 8
include/hw/i386/pc.h| 1 +
hw/acpi/piix4.c | 44
hw/pci-host/piix.c | 8
4 files changed, 57 insertions(+), 4 deletions(-)
create mode 100644 include/hw/acpi/piix4.h
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
new file mode 100644
index 000..65e6fd7
--- /dev/null
+++ b/include/hw/acpi/piix4.h
@@ -0,0 +1,8 @@
+#ifndef HW_ACPI_PIIX4_H
+#define HW_ACPI_PIIX4_H
+
+#include qemu/typedefs.h
+
+Object *piix4_pm_find(void);
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 5aefc5b..95857be 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -192,6 +192,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int
*piix_devfn,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
+PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 4b8c1da..3bcd890 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -29,6 +29,7 @@
#include exec/ioport.h
#include hw/nvram/fw_cfg.h
#include exec/address-spaces.h
+#include hw/acpi/piix4.h
//#define DEBUG
@@ -69,6 +70,8 @@ typedef struct PIIX4PMState {
/* public */
MemoryRegion io;
+uint32_t io_base;
+
MemoryRegion io_gpe;
MemoryRegion io_pci;
MemoryRegion io_cpu;
@@ -152,14 +155,13 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
static void pm_io_space_update(PIIX4PMState *s)
{
PCIDevice *d = PCI_DEVICE(s);
-uint32_t pm_io_base;
-pm_io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x40));
-pm_io_base = 0xffc0;
+s-io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x40));
+s-io_base = 0xffc0;
memory_region_transaction_begin();
memory_region_set_enabled(s-io, d-config[0x80] 1);
-memory_region_set_address(s-io, pm_io_base);
+memory_region_set_address(s-io, s-io_base);
memory_region_transaction_commit();
}
@@ -407,6 +409,28 @@ static void piix4_pm_machine_ready(Notifier *n, void
*opaque)
(memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
}
+static void piix4_pm_add_propeties(PIIX4PMState *s)
+{
+static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
+static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
+static const uint32_t gpe0_blk = GPE_BASE;
+static const uint32_t gpe0_blk_len = GPE_LEN;
+static const uint16_t sci_int = 9;
+
+object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+ acpi_enable_cmd, NULL);
+object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+ acpi_disable_cmd, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
+ gpe0_blk, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
+ gpe0_blk_len, NULL);
+object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
+ sci_int, NULL);
+object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
+ s-io_base, NULL);
+}
+
static int piix4_pm_initfn(PCIDevice *dev)
{
PIIX4PMState *s = PIIX4_PM(dev);
@@ -456,9 +480,21 @@ static int piix4_pm_initfn(PCIDevice *dev)
piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev-bus, s);
+piix4_pm_add_propeties(s);
return 0;
}
+Object *piix4_pm_find(void)
+{
+bool ambig;
+Object *o = object_resolve_path_type(, TYPE_PIIX4_PM, ambig);
+
+if (ambig || !o) {
+return NULL;
+}
+return o;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int kvm_enabled, FWCfgState *fw_cfg)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index c041149..bad3953 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -416,6 +416,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
return b;
}
+PCIBus *find_i440fx(void)
+{
+PCIHostState *s = OBJECT_CHECK(PCIHostState,
+ object_resolve_path(/machine/i440fx,
NULL),
+ TYPE_PCI_HOST_BRIDGE);
+return s ? s-bus : NULL;
+}
+
/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
--
MST
[Qemu-devel] [PATCH v8 21/26] ich9: APIs for pc guest info
This adds APIs that will be used to fill in
acpi tables, implemented using QOM,
to various ich9 components.
Some information is still missing in QOM,
so we fall back on lookups by type instead.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/acpi/ich9.h| 2 ++
include/hw/i386/ich9.h| 2 ++
include/hw/pci-host/q35.h | 2 ++
hw/acpi/ich9.c| 24
hw/isa/lpc_ich9.c | 40
hw/pci-host/q35.c | 10 ++
6 files changed, 80 insertions(+)
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index b1fe71f..82fcf9f 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp);
+
#endif /* HW_ACPI_ICH9_H */
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index c5f637b..4a68b35 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -66,6 +66,8 @@ typedef struct ICH9LPCState {
qemu_irq *ioapic;
} ICH9LPCState;
+Object *ich9_lpc_find(void);
+
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL ((ms_bit) + 1)) - 1) ~((1ULL ls_bit) - 1)))
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 6eb7ab6..f9db770 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -156,4 +156,6 @@ typedef struct Q35PCIHost {
#define MCH_PCIE_DEV 1
#define MCH_PCIE_FUNC 0
+uint64_t mch_mcfg_base(void);
+
#endif /* HW_Q35_H */
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 3fb443d..7e0429e 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -24,6 +24,7 @@
* GNU GPL, version 2 or (at your option) any later version.
*/
#include hw/hw.h
+#include qapi/visitor.h
#include hw/i386/pc.h
#include hw/pci/pci.h
#include qemu/timer.h
@@ -228,3 +229,26 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
pm-powerdown_notifier.notify = pm_powerdown_req;
qemu_register_powerdown_notifier(pm-powerdown_notifier);
}
+
+static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+ICH9LPCPMRegs *pm = opaque;
+uint32_t value = pm-pm_io_base + ICH9_PMIO_GPE0_STS;
+
+visit_type_uint32(v, value, name, errp);
+}
+
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
+{
+static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
+
+object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
+ pm-pm_io_base, errp);
+object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, uint32,
+ich9_pm_get_gpe0_blk,
+NULL, NULL, pm, NULL);
+object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
+ gpe0_len, errp);
+}
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 5633d08..19b2198 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -29,6 +29,7 @@
*/
#include qemu-common.h
#include hw/hw.h
+#include qapi/visitor.h
#include qemu/range.h
#include hw/isa/isa.h
#include hw/sysbus.h
@@ -525,6 +526,43 @@ static const MemoryRegionOps ich9_rst_cnt_ops = {
.endianness = DEVICE_LITTLE_ENDIAN
};
+Object *ich9_lpc_find(void)
+{
+bool ambig;
+Object *o = object_resolve_path_type(, TYPE_ICH9_LPC_DEVICE, ambig);
+
+if (ambig) {
+return NULL;
+}
+return o;
+}
+
+static void ich9_lpc_get_sci_int(Object *obj, Visitor *v,
+ void *opaque, const char *name,
+ Error **errp)
+{
+ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
+uint32_t value = ich9_lpc_sci_irq(lpc);
+
+visit_type_uint32(v, value, name, errp);
+}
+
+static void ich9_lpc_add_properties(ICH9LPCState *lpc)
+{
+static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
+static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+
+object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, uint32,
+ich9_lpc_get_sci_int,
+NULL, NULL, NULL, NULL);
+object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+ acpi_enable_cmd, NULL);
+object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+ acpi_disable_cmd, NULL);
+
+ich9_pm_add_properties(OBJECT(lpc), lpc-pm, NULL);
+}
+
static int ich9_lpc_initfn(PCIDevice *d)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
@@ -552,6 +590,8 @@ static int ich9_lpc_initfn(PCIDevice *d)
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 3 October 2013 15:34, Richard Henderson r...@twiddle.net wrote: On 10/03/2013 05:51 AM, Will Newton wrote: +case 0: /* eq: Z */ +tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero, +ftmp1, ftmp2); +break; Does this compile when configured with --enable-debug? It shouldn't, since movcond_i64 takes 5 _i64 variables, and your comparison variables are _i32. No, thanks for picking that up. I was wondering if that was valid and the code seemed to work. What's the best way to work around the problem? Just extend everything up to 64bits? -- Will Newton Toolchain Working Group, Linaro
[Qemu-devel] [PATCH v8 22/26] pvpanic: add API to access io port
Add API to find pvpanic device and get its io port.
Will be used to fill in guest info structure.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 1 +
hw/misc/pvpanic.c| 13 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 95857be..e3ee0a8 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory,
/* pvpanic.c */
void pvpanic_init(ISABus *bus);
+uint16_t pvpanic_port(void);
/* e820 types */
#define E820_RAM1
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index b64e3bb..226e298 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -117,8 +117,19 @@ void pvpanic_init(ISABus *bus)
isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE);
}
+#define PVPANIC_IOPORT_PROP ioport
+
+uint16_t pvpanic_port(void)
+{
+Object *o = object_resolve_path_type(, TYPE_ISA_PVPANIC_DEVICE, NULL);
+if (!o) {
+return 0;
+}
+return object_property_get_int(o, PVPANIC_IOPORT_PROP, NULL);
+}
+
static Property pvpanic_isa_properties[] = {
-DEFINE_PROP_UINT16(ioport, PVPanicState, ioport, 0x505),
+DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
DEFINE_PROP_END_OF_LIST(),
};
--
MST
[Qemu-devel] [PATCH v8 26/26] ssdt-proc: update generated file
Update generated ssdt proc hex file (used for systems
lacking IASL) after P_BLK length change.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/ssdt-proc.hex.generated | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
index a28172e..bb9920d 100644
--- a/hw/i386/ssdt-proc.hex.generated
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -11,7 +11,7 @@ static unsigned char ssdp_proc_aml[] = {
0x0,
0x0,
0x1,
-0xb3,
+0xb8,
0x42,
0x58,
0x50,
@@ -34,9 +34,9 @@ static unsigned char ssdp_proc_aml[] = {
0x4e,
0x54,
0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
0x20,
0x5b,
0x83,
@@ -51,7 +51,7 @@ static unsigned char ssdp_proc_aml[] = {
0xb0,
0x0,
0x0,
-0x6,
+0x0,
0x8,
0x49,
0x44,
--
MST
[Qemu-devel] [PATCH v8 17/26] loader: allow adding ROMs in done callbacks
Don't abort if machine done callbacks add ROMs.
Reviewed-by: Gerd Hoffmann kra...@redhat.com
Tested-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/loader.h | 1 +
hw/core/loader.c| 6 +-
vl.c| 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index e0c576b..58eca98 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -46,6 +46,7 @@ void *rom_add_blob(const char *name, const void *blob, size_t
len,
int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_load_all(void);
+void rom_load_done(void);
void rom_set_fw(FWCfgState *f);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
void *rom_ptr(hwaddr addr);
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 060729f..60d2ebd 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -812,10 +812,14 @@ int rom_load_all(void)
memory_region_unref(section.mr);
}
qemu_register_reset(rom_reset, NULL);
-roms_loaded = 1;
return 0;
}
+void rom_load_done(void)
+{
+roms_loaded = 1;
+}
+
void rom_set_fw(FWCfgState *f)
{
fw_cfg = f;
diff --git a/vl.c b/vl.c
index fb8006e..46c29c4 100644
--- a/vl.c
+++ b/vl.c
@@ -4339,6 +4339,9 @@ int main(int argc, char **argv, char **envp)
qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
qemu_run_machine_init_done_notifiers();
+/* Done notifiers can load ROMs */
+rom_load_done();
+
qemu_system_reset(VMRESET_SILENT);
if (loadvm) {
if (load_vmstate(loadvm) 0) {
--
MST
Re: [Qemu-devel] [PATCH v2] target-arm: Implement ARMv8 VSEL instruction.
On 10/03/2013 08:10 AM, Will Newton wrote: No, thanks for picking that up. I was wondering if that was valid and the code seemed to work. What's the best way to work around the problem? Just extend everything up to 64bits? For the simple conditions, yes. For the more complex ones, you might want to do the computation in 32-bit and extend the result. r~
