Re: [Qemu-devel] [PATCH 1/3] configure: add option to disable -fstack-protector flags

[Stefan Weil]

Hi Steven,

--disable-stack-protector would also be useful for platforms which make
debugging of executables with stack protection difficult. When I must
debug Windows executables, I always disable stack protection, because
otherwise the stack back traces are unreadable.

So, for MinGW it might be reasonable to set the default to no stack
protection if --enable-debug is selected. This requires some
modifications in your patch.

# Don't set it to "yes" initially:
stack_protector=""

# Do the compile test if it is not "no":
if test "$stack_protector" != "no"; then

The usual logic is do nothing if the user says "no". Run the compile
tests otherwise. Show an error message if the compile tests fail and the
user said "yes". See the code which handles $pie for an example.

Please send your next patch inline - this makes it easier to add comments.

Best regards

Stefan

Re: [Qemu-devel] [PATCH 03/13] mxs/imx23: Add uart driver

[Peter Crosthwaite]

On Tue, Jan 7, 2014 at 1:19 AM, Peter Maydell  wrote:
> On 11 December 2013 13:56, Michel Pollet  wrote:
>> Prototype driver for the mxs/imx23 uart IO block. This has no
>> real 'uart' functional code, apart from letting itself be
>> initialized by linux without generating a timeout error.
>>
>> Signed-off-by: Michel Pollet 
>
> Hi; there are some minor code style/formatting errors
> with this patch. You can catch these by running the
> scripts/checkpatch.pl script on your patches. (It
> doesn't catch everything, and sometimes it gets
> confused and gives bogus results, but it's a good
> sanity check.)
>
>> ---
>>  hw/char/Makefile.objs |   1 +
>>  hw/char/mxs_uart.c| 146 
>> ++
>>  2 files changed, 147 insertions(+)
>>  create mode 100644 hw/char/mxs_uart.c
>>
>> diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
>> index cbd6a00..8ea5670 100644
>> --- a/hw/char/Makefile.objs
>> +++ b/hw/char/Makefile.objs
>> @@ -19,6 +19,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
>>  common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
>>  common-obj-$(CONFIG_GRLIB) += grlib_apbuart.o
>>  common-obj-$(CONFIG_IMX) += imx_serial.o
>> +common-obj-$(CONFIG_MXS) += mxs_uart.o
>
> This should be a CONFIG_MXS_UART (see remark on earlier patch).
>
>>  common-obj-$(CONFIG_LM32) += lm32_juart.o
>>  common-obj-$(CONFIG_LM32) += lm32_uart.o
>>  common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o
>> diff --git a/hw/char/mxs_uart.c b/hw/char/mxs_uart.c
>> new file mode 100644
>> index 000..79b2582
>> --- /dev/null
>> +++ b/hw/char/mxs_uart.c
>> @@ -0,0 +1,146 @@
>> +/*
>> + * mxs_uart.c
>> + *
>> + * Copyright: Michel Pollet 
>> + *
>> + * QEMU Licence
>
> This is too vague. If you mean GPLv2 please say so.
>
>> + */
>> +
>> +/*
>> + * Work in progress ! Right now there's just enough so that linux driver
>> + * will instantiate after a probe, there is no functional code.
>> + */
>> +#include "hw/sysbus.h"
>> +#include "hw/arm/mxs.h"
>> +
>> +#define D(w) w
>
> Please get rid of this. You can use a similar DPRINTF
> type macro as other devices do, or no debug tracing at
> all, as you wish.
>

To clarify further, make DPRINTF use a regular c-code if, rather than
conditional compilation. The reason being your debug printfery should
always be compile tested.

>> +
>> +enum {
>> +UART_CTRL = 0x0,
>> +UART_CTRL1 = 0x1,
>> +UART_CTRL2 = 0x2,
>> +UART_LINECTRL = 0x3,
>> +UART_LINECTRL2 = 0x4,
>> +UART_INTR = 0x5,
>> +UART_APP_DATA = 0x6,
>> +UART_APP_STAT = 0x7,
>> +UART_APP_DEBUG = 0x8,
>> +UART_APP_VERSION = 0x9,
>> +UART_APP_AUTOBAUD = 0xa,
>> +
>> +UART_MAX,
>> +};
>> +typedef struct mxs_uart_state {
>> +SysBusDevice busdev;
>> +MemoryRegion iomem;

Check QOM conventions (I commented in other patch - see for details).

>> +
>> +uint32_t r[UART_MAX];
>> +
>> +struct {
>> +uint16_t b[16];
>> +int w, r;
>> +} fifo[2];
>> +qemu_irq irq;
>> +CharDriverState *chr;

Dead variable. Just add it along with your functionality. Although the
functionality would help a lot. Its a bit of a trap, advertisiting a
UART which is just a NOP. Some qemu_log_mask(LOG_UNIMP, at various
places migt be in order, although depending on complexity it may not
be much harder to get basic txrx going.

>> +} mxs_uart_state;
>
> Structured type names should be in CamelCase;
> see CODING_STYLE.
>
>> +static uint64_t mxs_uart_read(
>> +void *opaque, hwaddr offset, unsigned size)
>> +{
>> +mxs_uart_state *s = (mxs_uart_state *) opaque;
>> +uint32_t res = 0;
>> +
>> +D(printf("%s %04x (%d) = ", __func__, (int)offset, size);)
>> +switch (offset >> 4) {
>> +case 0 ... UART_MAX:
>
> This indent is wrong, as checkpatch.pl will tell you.
>
>> +res = s->r[offset >> 4];
>> +break;
>> +default:
>> +qemu_log_mask(LOG_GUEST_ERROR,
>> +"%s: bad offset 0x%x\n", __func__, (int) offset);
>> +break;
>> +}
>> +D(printf("%08x\n", res);)
>> +
>> +return res;
>> +}
>> +
>> +static void mxs_uart_write(void *opaque, hwaddr offset,
>> +uint64_t value, unsigned size)
>> +{
>> +mxs_uart_state *s = (mxs_uart_state *) opaque;
>> +uint32_t oldvalue = 0;
>> +
>> +D(printf("%s %04x %08x(%d)\n", __func__, (int)offset, (int)value, 
>> size);)
>> +switch (offset >> 4) {
>> +case 0 ... UART_MAX:
>> +mxs_write(&s->r[offset >> 4], offset, value, size);
>> +break;
>> +default:
>> +qemu_log_mask(LOG_GUEST_ERROR,
>> +"%s: bad offset 0x%x\n", __func__, (int) offset);
>> +break;
>> +}
>> +switch (offset >> 4) {
>> +case UART_CTRL:
>> +if ((oldvalue ^ s->r[UART_CTRL]) == 0x8000
>> +&& !(oldvalue & 0x8000)) {
>> +printf("%s reseting, anding clockgate\n", __func__);
>
> S

Re: [Qemu-devel] [PATCH] Include bios-256k.bin blob during "make install"

[Peter Maydell]

On 10 January 2014 21:51, Gabriel L. Somlo  wrote:
> Signed-off-by: Gabriel Somlo 
> ---
>  Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Makefile b/Makefile
> index bdff4e4..807054b 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -290,7 +290,7 @@ common  de-ch  es fo  fr-ca  hu ja  mk  nl-be 
>  pt  sl tr \
>  bepocz
>
>  ifdef INSTALL_BLOBS
> -BLOBS=bios.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
> +BLOBS=bios.bin bios-256k.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \

We've now seen this patch four times from four different people.
Previously:
http://lists.gnu.org/archive/html/qemu-devel/2013-12/msg01612.html
https://lists.gnu.org/archive/html/qemu-devel/2014-01/msg00401.html
https://lists.gnu.org/archive/html/qemu-devel/2014-01/msg01036.html

Could somebody apply Eduardo's patch from December before
we get a fifth version? :-)

thanks
-- PMM

Re: [Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton for SIMD data processing insns

[Peter Maydell]

On 10 January 2014 19:05, Richard Henderson  wrote:
> On 01/10/2014 09:12 AM, Peter Maydell wrote:
>>  static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
>>  {
>>  /* Note that this is called with all non-FP cases from
>>   * table C3-6 so it must UNDEF for entries not specifically
>>   * allocated to instructions in that table.
>>   */
>> -unsupported_encoding(s, insn);
>> +AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
>> +if (fn) {
>> +(fn) (s, insn);
>
> Oh, do you want to CheckFPAdvSIMDEnabled64 here before calling fn?
> Otherwise that's the first thing I noticed missing from patch 4.

We don't currently check that for the FP insns either. Since it's a system
register check and will always pass for usermode emulation I was planning
to leave it for when I did system emulation and wired up the CPACR_EL1.

thanks
-- PMM

[Qemu-devel] [PATCH] spice: hook qemu_chr_fe_set_open() event to ports

[Marc-André Lureau]

This wires up a spice port event on virtio-ports open/close, so the
client is notified when the other end is ready.

Signed-off-by: Marc-André Lureau 
---
 spice-qemu-char.c | 25 -
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/spice-qemu-char.c b/spice-qemu-char.c
index 16439c5..6624559 100644
--- a/spice-qemu-char.c
+++ b/spice-qemu-char.c
@@ -212,7 +212,7 @@ static void spice_chr_close(struct CharDriverState *chr)
 g_free(s);
 }
 
-static void spice_chr_set_fe_open(struct CharDriverState *chr, int fe_open)
+static void spice_vmc_set_fe_open(struct CharDriverState *chr, int fe_open)
 {
 SpiceCharDriver *s = chr->opaque;
 if (fe_open) {
@@ -222,6 +222,19 @@ static void spice_chr_set_fe_open(struct CharDriverState 
*chr, int fe_open)
 }
 }
 
+static void spice_port_set_fe_open(struct CharDriverState *chr, int fe_open)
+{
+#if SPICE_SERVER_VERSION >= 0x000c02
+SpiceCharDriver *s = chr->opaque;
+
+if (fe_open) {
+spice_server_port_event(&s->sin, SPICE_PORT_EVENT_OPENED);
+} else {
+spice_server_port_event(&s->sin, SPICE_PORT_EVENT_CLOSED);
+}
+#endif
+}
+
 static void spice_chr_fe_event(struct CharDriverState *chr, int event)
 {
 #if SPICE_SERVER_VERSION >= 0x000c02
@@ -248,7 +261,9 @@ static void print_allowed_subtypes(void)
 fprintf(stderr, "\n");
 }
 
-static CharDriverState *chr_open(const char *subtype)
+static CharDriverState *chr_open(const char *subtype,
+void (*set_fe_open)(struct CharDriverState *, int))
+
 {
 CharDriverState *chr;
 SpiceCharDriver *s;
@@ -262,7 +277,7 @@ static CharDriverState *chr_open(const char *subtype)
 chr->chr_write = spice_chr_write;
 chr->chr_add_watch = spice_chr_add_watch;
 chr->chr_close = spice_chr_close;
-chr->chr_set_fe_open = spice_chr_set_fe_open;
+chr->chr_set_fe_open = set_fe_open;
 chr->explicit_be_open = true;
 chr->chr_fe_event = spice_chr_fe_event;
 
@@ -291,7 +306,7 @@ CharDriverState *qemu_chr_open_spice_vmc(const char *type)
 return NULL;
 }
 
-return chr_open(type);
+return chr_open(type, spice_vmc_set_fe_open);
 }
 
 #if SPICE_SERVER_VERSION >= 0x000c02
@@ -305,7 +320,7 @@ CharDriverState *qemu_chr_open_spice_port(const char *name)
 return NULL;
 }
 
-chr = chr_open("port");
+chr = chr_open("port", spice_port_set_fe_open);
 s = chr->opaque;
 s->sin.portname = g_strdup(name);
 
-- 
1.8.4.2

Re: [Qemu-devel] [PATCH 1/2] hw/net: add support for Allwinner EMAC Fast Ethernet controller

[Peter Crosthwaite]

On Mon, Jan 6, 2014 at 4:12 PM, Stefan Hajnoczi  wrote:
> On Mon, Jan 06, 2014 at 01:46:54PM +1000, Peter Crosthwaite wrote:
>> On Mon, Jan 6, 2014 at 1:27 PM, Stefan Hajnoczi  wrote:
>> > On Thu, Jan 02, 2014 at 08:25:10PM +1000, Peter Crosthwaite wrote:
>> >> Hi Beniamino,
>> >>
>> >> On Thu, Jan 2, 2014 at 7:18 PM, Beniamino Galvani  
>> >> wrote:
>> >> > This patch adds support for the Fast Ethernet MAC found on Allwinner
>> >> > SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
>> >> >
>> >>
>> >> More a comment for net in general, but I think sooner or later we need
>> >> to move towards a split between phy and mac on the device level.
>> >> continuing the phy-within-mac philosophy is going to make the
>> >> socification efforts awkward. Are MII and friends a busses (as in
>> >> TYPE_BUS) in their own right, and connection of mac and phy has to
>> >> happen on the board level?
>> >
>> > I see PHY and MAC split as advantageous because it allows code reuse and
>> > better testing.  The main thing I'd like to see is PHY device tests
>> > using tests/libqtest.h.
>> >
>> > If someone wants to implement it, great.  It would make it easier to add
>> > more NIC models in the future.
>> >
>> > Regarding SOCification and busses, I'm not sure.  Is it okay to just say
>> > a NIC has-a PHY (i.e. composition)?
>> >
>>
>> Generally speaking, in the (ARM) SoCification the MAC is part of the
>> SoC which in the latest styling guidelines is a composite device. This
>> composite is supposed to reflect the self contained SoC product which
>> the PHY is usually not a part of. So we have two opposing compositions
>> here:
>>
>> NIC = MAC + PHY
>> SOC = CPUs + MAC + ...
>>
>> MAC can't be in both. So for SoCs the NIC concept needs to abandoned.
>> After all the expansion of NIC as "Network Interface Card" is a little
>> bit PCish. Your average SoC networking solution has no such "card".
>> Just an on chip MAC (same pacakge/die as CPU etc) connecting to a PHY
>> via PCB traces.
>>
>> So I think long term, MII has to be a TYPE_BUS that is visible on the
>> top level SoC device. Self contained NICs (as we know them today) are
>> then also implementable as container devices (of MAC and PHY) that use
>> this bus internally (in much the same way the SoC boards would attach
>> external PHY to SoC).
>
> Okay, that makes sense.  Given the amount of emulated hardware in QEMU
> today, I think it would be okay to simply add new MAC/PHYs while still
> supporting the NICs of old.  If someone is enthusiastic about
> refactoring and testing existing NICs then great.  But I think it's more
> pragmatic to simply start working with a split MAC/PHY where that is
> beneficial.
>

Alright,

So lets make some plans. There is devil in the detail here. There was
a previous attempt to do something similar by Grant early last year so
cc as FYI.

So the main question is whether or not this new interface is just for
MDIO or is the full MII interface (both MDIO and packet data).

My inclination is the latter, we want a new proper QOM bus that is
both. What this would mean, is that these MAC-only devices wont be net
devices at all. the -net args are instead applied to the PHY. This
makes the most sense to me as its the phy that actually has copper
connection to the external network, not MAC.

MAC < TYPE_MII_BUS > PHY <-net layer --> external
network: "-net foo,bar,baz"

Another approach is to make both net devices in their own right. Phy
has two net-layer-managed attachments, one for external network, and
one point-to-point for the MII connecting to MAC. The MDIO bus is then
a side channel which may or may not be QOMified (depending on effort
levels). So you can still connect a standalone MAC to an external
network, assuming the guest can handle no PHY (may in reality have
limited use).

MAC < net layer > PHY <-net layer --> external network
< TYPE_MDIO_BUS >

OR:

MAC < net layer > external network


The third approach (which is closest to current implementation) is to
only have the phy do MDIO and still connect the MAC straight to an
external network:

MAC < net layer > external network
 \
  <-- TYPE_MDIO_BUS > PHY

I dont like this though, as its a little mismatched to real hw.
Although it may be a good stepping stone to approaches 1 or 2.

RFC

Regards,
Peter

> Stefan
>

Re: [Qemu-devel] [PATCHv4 6/6] ui/vnc: disable adaptive update calculations if not needed

[Peter Lieven]

Am 10.01.2014 04:09, schrieb Wenchao Xia:
> 于 2014/1/10 0:25, Peter Lieven 写道:
>> Am 09.01.2014 09:29, schrieb Wenchao Xia:
>>> 于 2014/1/8 17:08, Peter Lieven 写道:
 Signed-off-by: Peter Lieven 
 ---
ui/vnc.c |9 +
1 file changed, 9 insertions(+)

 diff --git a/ui/vnc.c b/ui/vnc.c
 index da552fe..a742d32 100644
 --- a/ui/vnc.c
 +++ b/ui/vnc.c
 @@ -3170,7 +3170,9 @@ void vnc_display_open(DisplayState *ds, const char 
 *display, Error **errp)
acl = 1;
#endif
} else if (strncmp(options, "lossy", 5) == 0) {
 +#ifdef CONFIG_VNC_JPEG
vs->lossy = true;
 +#endif
} else if (strncmp(options, "non-adaptive", 12) == 0) {
vs->non_adaptive = true;
} else if (strncmp(options, "share=", 6) == 0) {
 @@ -3187,6 +3189,13 @@ void vnc_display_open(DisplayState *ds, const char 
 *display, Error **errp)
}
}

 +/* adaptive updates are only used with tight encoding and
 + * if lossy updates are enabled so we can disable all the
 + * calculations otherwise */
 +if (!vs->lossy) {
 +vs->non_adaptive = true;
 +}
 +
>>>The code seems: if vs->loosy == false, then vs->non_adaptive = true,
>>> translate as: if loosy update is not used, then don't do adaptive
>>> update., which doesn't conform with the comments. I am not sure if this
>>> is on expectation.
>> It don't see the logic break. The option means non_adaptive, not adaptive.
>>
>> I write "adaptive updates are only used ... with lossy updates...". Which
>   So tight encoding means loosy updates?
It means you can only enable lossy updates if you have tight encoding. So if 
you are
missing tight encoding or lossy is false then you can set non_adaptive to true.

Peter

Re: [Qemu-devel] [PATCH 1/2] hw/net: add support for Allwinner EMAC Fast Ethernet controller

[Peter Crosthwaite]

On Sat, Jan 11, 2014 at 7:48 AM, Beniamino Galvani  wrote:
> On Mon, Jan 06, 2014 at 02:12:27PM +0800, Stefan Hajnoczi wrote:
>> > >> More a comment for net in general, but I think sooner or later we need
>> > >> to move towards a split between phy and mac on the device level.
>> > >> continuing the phy-within-mac philosophy is going to make the
>> > >> socification efforts awkward. Are MII and friends a busses (as in
>> > >> TYPE_BUS) in their own right, and connection of mac and phy has to
>> > >> happen on the board level?
>> > >
>> > > I see PHY and MAC split as advantageous because it allows code reuse and
>> > > better testing.  The main thing I'd like to see is PHY device tests
>> > > using tests/libqtest.h.
>> > >
>> > > If someone wants to implement it, great.  It would make it easier to add
>> > > more NIC models in the future.
>> > >
>> > > Regarding SOCification and busses, I'm not sure.  Is it okay to just say
>> > > a NIC has-a PHY (i.e. composition)?
>> > >
>> >
>> > Generally speaking, in the (ARM) SoCification the MAC is part of the
>> > SoC which in the latest styling guidelines is a composite device. This
>> > composite is supposed to reflect the self contained SoC product which
>> > the PHY is usually not a part of. So we have two opposing compositions
>> > here:
>> >
>> > NIC = MAC + PHY
>> > SOC = CPUs + MAC + ...
>> >
>> > MAC can't be in both. So for SoCs the NIC concept needs to abandoned.
>> > After all the expansion of NIC as "Network Interface Card" is a little
>> > bit PCish. Your average SoC networking solution has no such "card".
>> > Just an on chip MAC (same pacakge/die as CPU etc) connecting to a PHY
>> > via PCB traces.
>> >
>> > So I think long term, MII has to be a TYPE_BUS that is visible on the
>> > top level SoC device. Self contained NICs (as we know them today) are
>> > then also implementable as container devices (of MAC and PHY) that use
>> > this bus internally (in much the same way the SoC boards would attach
>> > external PHY to SoC).
>>
>> Okay, that makes sense.  Given the amount of emulated hardware in QEMU
>> today, I think it would be okay to simply add new MAC/PHYs while still
>> supporting the NICs of old.  If someone is enthusiastic about
>> refactoring and testing existing NICs then great.  But I think it's more
>> pragmatic to simply start working with a split MAC/PHY where that is
>> beneficial.
>
> Regarding the patch, can I resubmit it with MAC and PHY modeled as a
> single device? Or it's better to start thinking on how to implement
> proper MAC/PHY split?
>

Resubmit as a single. Don't wait on the proposed fifo cleanups either.
I'm not going to block.

Regards,
Peter

> Beniamino
>

[Qemu-devel] [PATCH] Include bios-256k.bin blob during "make install"

[Gabriel L. Somlo]

Signed-off-by: Gabriel Somlo 
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index bdff4e4..807054b 100644
--- a/Makefile
+++ b/Makefile
@@ -290,7 +290,7 @@ common  de-ch  es fo  fr-ca  hu ja  mk  nl-be  
pt  sl tr \
 bepocz
 
 ifdef INSTALL_BLOBS
-BLOBS=bios.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
+BLOBS=bios.bin bios-256k.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
 vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
 acpi-dsdt.aml q35-acpi-dsdt.aml \
 ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 1/2] hw/net: add support for Allwinner EMAC Fast Ethernet controller

[Beniamino Galvani]

On Mon, Jan 06, 2014 at 02:12:27PM +0800, Stefan Hajnoczi wrote:
> > >> More a comment for net in general, but I think sooner or later we need
> > >> to move towards a split between phy and mac on the device level.
> > >> continuing the phy-within-mac philosophy is going to make the
> > >> socification efforts awkward. Are MII and friends a busses (as in
> > >> TYPE_BUS) in their own right, and connection of mac and phy has to
> > >> happen on the board level?
> > >
> > > I see PHY and MAC split as advantageous because it allows code reuse and
> > > better testing.  The main thing I'd like to see is PHY device tests
> > > using tests/libqtest.h.
> > >
> > > If someone wants to implement it, great.  It would make it easier to add
> > > more NIC models in the future.
> > >
> > > Regarding SOCification and busses, I'm not sure.  Is it okay to just say
> > > a NIC has-a PHY (i.e. composition)?
> > >
> > 
> > Generally speaking, in the (ARM) SoCification the MAC is part of the
> > SoC which in the latest styling guidelines is a composite device. This
> > composite is supposed to reflect the self contained SoC product which
> > the PHY is usually not a part of. So we have two opposing compositions
> > here:
> > 
> > NIC = MAC + PHY
> > SOC = CPUs + MAC + ...
> > 
> > MAC can't be in both. So for SoCs the NIC concept needs to abandoned.
> > After all the expansion of NIC as "Network Interface Card" is a little
> > bit PCish. Your average SoC networking solution has no such "card".
> > Just an on chip MAC (same pacakge/die as CPU etc) connecting to a PHY
> > via PCB traces.
> > 
> > So I think long term, MII has to be a TYPE_BUS that is visible on the
> > top level SoC device. Self contained NICs (as we know them today) are
> > then also implementable as container devices (of MAC and PHY) that use
> > this bus internally (in much the same way the SoC boards would attach
> > external PHY to SoC).
> 
> Okay, that makes sense.  Given the amount of emulated hardware in QEMU
> today, I think it would be okay to simply add new MAC/PHYs while still
> supporting the NICs of old.  If someone is enthusiastic about
> refactoring and testing existing NICs then great.  But I think it's more
> pragmatic to simply start working with a split MAC/PHY where that is
> beneficial.

Regarding the patch, can I resubmit it with MAC and PHY modeled as a
single device? Or it's better to start thinking on how to implement
proper MAC/PHY split?

Beniamino

Re: [Qemu-devel] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions

[Richard Henderson]

On 01/10/2014 11:08 AM, Tom Musta wrote:
> This patch adds the non-signalling scalar conversion instructions:
> 
>   - VSX Scalar Convert Single Precision to Double Precision
> Non-Signalling (xscvspdpn)
>   - VSX Scalar Convert Double Precision to Single Precision
> Non-Signalling (xscvdpspn)
> 
> Signed-off-by: Tom Musta 
> ---
> V6: New.
> 
>  target-ppc/fpu_helper.c |   19 +++
>  target-ppc/helper.h |2 ++
>  target-ppc/translate.c  |4 
>  3 files changed, 25 insertions(+), 0 deletions(-)

Reviewed-by: Richard Henderson 

Of course, this also deserves the same cleanup that all of the other VSX
scalars ought to get -- reorg to be more like regular FP, with data passed by
value.


r~

Re: [Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision

[Richard Henderson]

On 01/10/2014 11:08 AM, Tom Musta wrote:
> This patch adds the VSX Scalar Round to Single Precision (xsrsp)
> instruction.
> 
> Signed-off-by: Tom Musta 
> ---
> V6: New.
> 
>  target-ppc/fpu_helper.c |   17 +
>  target-ppc/helper.h |1 +
>  target-ppc/translate.c  |2 ++
>  3 files changed, 20 insertions(+), 0 deletions(-)

Ok, I guess, although why aren't we passing and returning by value, rather than
by reference?

This is scalar, so we only need to pass and return uint64_t...


r~

Re: [Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions

[Richard Henderson]

On 01/10/2014 11:08 AM, Tom Musta wrote:
> +static void gen_fmrgow(DisasContext *ctx)
> +{
> +TCGv_i64 a1;
> +if (unlikely(!ctx->fpu_enabled)) {
> +gen_exception(ctx, POWERPC_EXCP_FPU);
> +return;
> +}
> +a1 = tcg_temp_new_i64();
> +tcg_gen_shli_i64(a1, cpu_fpr[rA(ctx->opcode)], 32);
> +tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
> +a1, cpu_fpr[rB(ctx->opcode)],
> +0, 32);
> +tcg_temp_free_i64(a1);
> +}

Better use of the deposit when you use it for the shift also:

tcg_gen_deposit_i64(cpu_fpr[rD],
cpu_fpr[rB],
cpu_fpr[rA], 32, 32);


r~

Re: [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions

[Richard Henderson]

On 01/10/2014 11:07 AM, Tom Musta wrote:
> +#define MV_VSR(name, tcgop1, tcgop2, target, source)\
> +static void gen_##name(DisasContext *ctx)   \
> +{   \
> +if (xS(ctx->opcode) < 32) { \
> +if (unlikely(!ctx->fpu_enabled)) {  \
> +gen_exception(ctx, POWERPC_EXCP_FPU);   \
> +return; \
> +}   \
> +} else {\
> +if (unlikely(!ctx->altivec_enabled)) {  \
> +gen_exception(ctx, POWERPC_EXCP_VPU);   \
> +return; \
> +}   \
> +}   \
> +TCGv_i64 tmp = tcg_temp_new_i64();  \
> +tcg_gen_##tcgop1(tmp, source);  \
> +tcg_gen_##tcgop2(target, tmp);  \
> +tcg_temp_free_i64(tmp); \
> +}
> +
> +
> +MV_VSR(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
> +   cpu_vsrh(xS(ctx->opcode)))
> +MV_VSR(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
> +   cpu_gpr[rA(ctx->opcode)])
> +MV_VSR(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
> +   cpu_gpr[rA(ctx->opcode)])
> +#if defined(TARGET_PPC64)
> +MV_VSR(mfvsrd, mov_i64, mov_i64, cpu_gpr[rA(ctx->opcode)], \
> +   cpu_vsrh(xS(ctx->opcode)))
> +MV_VSR(mtvsrd, mov_i64, mov_i64, cpu_vsrh(xT(ctx->opcode)), \
> +   cpu_gpr[rA(ctx->opcode)])
> +#endif

Better to do this in one step:

mfcsrwz:tcg_gen_ext32u_tl
mtvsrwa:tcg_gen_ext_tl_i64
mtvsrwz:tcg_gen_extu_tl_i64
m[tf]vsrd:  tcg_gen_mov_i64


r~

Re: [Qemu-devel] [ARM] Unused OMAP NAND support - can we remove?

[Peter Crosthwaite]

On Fri, Jan 10, 2014 at 7:02 PM, Peter Maydell  wrote:
> On 10 January 2014 08:47, Peter Crosthwaite
>  wrote:
>> I'm trying to apply a QOMification change pattern to NAND and I notice
>> that OMAP gpmc has NAND support. However no one is using it - there
>> are no calls to the omap_gpmc_attach_nand, nor does the code call
>> nand_init, leaving me to believe this is dead code. The fact that it
>> is so far out of stylistic date makes me think its best deleted and
>> can be updated and re-added later if wanted. Otherwise I need to apply
>> my change pattern to dead code which is not ideal.
>
> This is used by the omap3 patchset (git://git.linaro.org/qemu/qemu-linaro.git
> 'rebasing' branch). At the time I got the GPMC changes upstream I was
> planning to get the remainder of OMAP3 upstream in the immediate
> future, which is why the support is there. Unfortunately priorities
> changed and OMAP3 upstreaming got put on the back burner (partly
> because it's a huge job). I'd still like to get OMAP3 upstream someday,
> so if it's not too awful to apply your change to omap_gpmc_attach_nand()
> I think that would be preferable.
>

So on reviewing this controller properly just this morning, it's
actually one of the better examples for the conversion. My change
pattern is the BUSification of NAND and in doing so, it is naturally
adding support for multiple NANDs on the one bus, which is actually
what GPMC is try to emulate.

Currently GPMC is just an array of N (DeviceState *) pointers to the N
NAND devices and bangs them individually depending on which CS window
was hit. Instead following my change, GPMC would have only one
(NANDBus *), and correctly drive the N CS lines as GPIOs (will need to
be added) in the same way real HW does.

It will be a functional change as we are now modelling the proper
interleaving CS behaviour on GPMC, but if anything, it's actually
going to be an increase in modeling fidelity.

Regards,
Peter

> The specific users of the function in the omap3 code are the board
> model files like hw/arm/beagle.c, which do:
>
>  s->nand = nand_init(dmtd ? dmtd->bdrv : NULL, NAND_MFR_MICRON, 0xba);
>  nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */
>  omap_gpmc_attach_nand(s->cpu->gpmc, BEAGLE_NAND_CS, s->nand);
>
> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH target-arm v4 2/3] zynq_slcr: Add links to the CPUs

[Andreas Färber]

Am 10.01.2014 21:20, schrieb Peter Crosthwaite:
> On Sat, Jan 11, 2014 at 4:11 AM, Peter Maydell  
> wrote:
>> On 2 January 2014 07:31, Peter Crosthwaite  
>> wrote:
>>> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
>>> SLCR.
>>
>>> @@ -496,10 +500,17 @@ static const MemoryRegionOps slcr_ops = {
>>>  static int zynq_slcr_init(SysBusDevice *dev)
>>>  {
>>>  ZynqSLCRState *s = ZYNQ_SLCR(dev);
>>> +int i;
>>>
>>>  memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 
>>> 0x1000);
>>>  sysbus_init_mmio(dev, &s->iomem);
>>>
>>> +for (i = 0; i < NUM_CPUS; ++i) {
>>> +gchar *name = g_strdup_printf("cpu%d", i);
>>> +object_property_add_link(OBJECT(dev), name, TYPE_CPU,
>>> + (Object **)&s->cpus[i], NULL);
>>> +g_free(name);
>>> +}
>>
>> This is where we get into the nasty questions of how
>> we ought to be modelling reset. I don't think that
>> reset controllers ought to work by having direct links
>> to a pile of QOM device objects. I'd much rather we tried
>> to work towards modelling this the way the hardware does,
>> ie a QOM device has one or more inbound GPIO lines
>> corresponding to the hardware's reset signals, and the
>> SoC or board wires those up to the reset controller
>> appropriately.
>>
> 
> So all nice solutions to this really want named GPIOs which is
> something of a long term sore-point. Are you happy to take a simple
> addition of a reset GPIO to ARMCPU  (which itself just calls
> cpu_reset) without the need for the big planned GPIO fixups (whether
> than be pins of Andreas' QOMification)?

Pins are Anthony's topic, not mine. :) I rather recently suggested to do
a transparent QOM'ification. I thus have no objections against adding a
reset IRQ! That had BTW been discussed as possible solution for
partial/soft resets in PReP and x86 context.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

[Qemu-devel] [PATCH] target-i386: Fix CC_OP_CLR vs PF

[Richard Henderson]

Parity should be set for a zero result.

Signed-off-by: Richard Henderson 
---
 target-i386/cc_helper.c | 2 +-
 target-i386/translate.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index ee04092..05dd12b 100644
--- a/target-i386/cc_helper.c
+++ b/target-i386/cc_helper.c
@@ -103,7 +103,7 @@ target_ulong helper_cc_compute_all(target_ulong dst, 
target_ulong src1,
 case CC_OP_EFLAGS:
 return src1;
 case CC_OP_CLR:
-return CC_Z;
+return CC_Z | CC_P;
 
 case CC_OP_MULB:
 return compute_all_mulb(dst, src1);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index b0f2279..34f35e7 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -748,7 +748,7 @@ static void gen_compute_eflags(DisasContext *s)
 return;
 }
 if (s->cc_op == CC_OP_CLR) {
-tcg_gen_movi_tl(cpu_cc_src, CC_Z);
+tcg_gen_movi_tl(cpu_cc_src, CC_Z | CC_P);
 set_cc_op(s, CC_OP_EFLAGS);
 return;
 }
-- 
1.8.4.2

[Qemu-devel] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp

[Tom Musta]

This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.

The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Updated conversion to single precision.

 target-ppc/fpu_helper.c |   13 +
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index dc9849f..49cf09a 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1874,7 +1874,7 @@ VSX_MUL(xvmulsp, 4, float32, f32, 0, 0)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_DIV(op, nels, tp, fld, sfprf) \
+#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp)   \
 void helper_##op(CPUPPCState *env, uint32_t opcode)   \
 { \
 ppc_vsr_t xt, xa, xb; \
@@ -1903,6 +1903,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 } \
 } \
   \
+if (r2sp) {   \
+xt.fld[i] = helper_frsp(env, xt.fld[i]);  \
+} \
+  \
 if (sfprf) {  \
 helper_compute_fprf(env, xt.fld[i], sfprf);   \
 } \
@@ -1912,9 +1916,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 helper_float_check_status(env);   \
 }
 
-VSX_DIV(xsdivdp, 1, float64, f64, 1)
-VSX_DIV(xvdivdp, 2, float64, f64, 0)
-VSX_DIV(xvdivsp, 4, float32, f32, 0)
+VSX_DIV(xsdivdp, 1, float64, f64, 1, 0)
+VSX_DIV(xsdivsp, 1, float64, f64, 1, 1)
+VSX_DIV(xvdivdp, 2, float64, f64, 0, 0)
+VSX_DIV(xvdivsp, 4, float32, f32, 0, 0)
 
 /* VSX_RE  - VSX floating point reciprocal estimate
  *   op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0ccdc96..308f97c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -289,6 +289,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32)
 DEF_HELPER_2(xsaddsp, void, env, i32)
 DEF_HELPER_2(xssubsp, void, env, i32)
 DEF_HELPER_2(xsmulsp, void, env, i32)
+DEF_HELPER_2(xsdivsp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3a6a94b..eddb9d2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7361,6 +7361,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10171,6 +10172,7 @@ GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
+GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-- 
1.7.1

Re: [Qemu-devel] [PATCH v2] piix: fix 32bit pci hole

[Laszlo Ersek]

On 11/28/13 17:03, Laszlo Ersek wrote:
> Mike,
> 
> On 11/27/13 12:57, Gerd Hoffmann wrote:
>> Make the 32bit pci hole start at end of ram, so all possible address
>> space is covered.  Of course the firmware can use less than that.
>> Leaving space unused is no problem, mapping pci bars outside the
>> hole causes problems though.
>>
>> Signed-off-by: Gerd Hoffmann 
>> ---
>>  hw/pci-host/piix.c | 10 +-
>>  1 file changed, 1 insertion(+), 9 deletions(-)
>>
>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>> index edc974e..8e41ac1 100644
>> --- a/hw/pci-host/piix.c
>> +++ b/hw/pci-host/piix.c
>> @@ -345,15 +345,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
>>  f->ram_memory = ram_memory;
>>  
>>  i440fx = I440FX_PCI_HOST_BRIDGE(dev);
>> -/* Set PCI window size the way seabios has always done it. */
>> -/* Power of 2 so bios can cover it with a single MTRR */
>> -if (ram_size <= 0x8000) {
>> -i440fx->pci_info.w32.begin = 0x8000;
>> -} else if (ram_size <= 0xc000) {
>> -i440fx->pci_info.w32.begin = 0xc000;
>> -} else {
>> -i440fx->pci_info.w32.begin = 0xe000;
>> -}
>> +i440fx->pci_info.w32.begin = pci_hole_start;
>>  
>>  memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", 
>> f->pci_address_space,
>>   pci_hole_start, pci_hole_size);
>>
> 
> please pick this up for 1.7.1.
> 
> 1.7.0 has been released without this patch, also without etc/pci-info,
> but with etc/acpi/tables.
> 
> For OVMF to work with "etc/acpi/tables" correctly, with eg. a guest RAM
> size of 2560MB, OVMF needs:
> - either this patch in qemu, or
> - etc/pci-info (which won't come back), or
> - a hack in OVMF that mimicks the same 0x8000/0xc000/0xe000
>   logic (which I won't add).

Nominating this for v1.7.1 again.

The qemu-2.0 version (ie. a forward-port) of this patch has been merged as

  ddaaefb piix: fix 32bit pci hole

If necessary I can resubmit the v1.7.1 patch.

Thanks,
Laszlo

[Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions

[Tom Musta]

This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.

Signed-off-by: Tom Musta 
---
V6: New.

 target-ppc/translate.c |   31 +++
 1 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ec945a2..7f2a66f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2294,6 +2294,35 @@ static void gen_fcpsgn(DisasContext *ctx)
 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
 }
 
+static void gen_fmrgew(DisasContext *ctx)
+{
+TCGv_i64 b0;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+b0 = tcg_temp_new_i64();
+tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
+tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+b0, 0, 32);
+tcg_temp_free_i64(b0);
+}
+
+static void gen_fmrgow(DisasContext *ctx)
+{
+TCGv_i64 a1;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+a1 = tcg_temp_new_i64();
+tcg_gen_shli_i64(a1, cpu_fpr[rA(ctx->opcode)], 32);
+tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
+a1, cpu_fpr[rB(ctx->opcode)],
+0, 32);
+tcg_temp_free_i64(a1);
+}
+
 /***  Floating-Point status & ctrl register***/
 
 /* mcrfs */
@@ -9397,6 +9426,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F, PPC_FLOAT),
 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F, PPC_FLOAT),
 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F, PPC_FLOAT),
 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x0001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x0001, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions

[Tom Musta]

This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz).  These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vector instructions if the
indexed VSR is in the second half of the array (32-63).

Signed-off-by: Tom Musta 
---
V6: New.

 target-ppc/translate.c |   42 ++
 1 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e2dd272..ec945a2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7175,6 +7175,40 @@ static void gen_stxvw4x(DisasContext *ctx)
 tcg_temp_free_i64(tmp);
 }
 
+#define MV_VSR(name, tcgop1, tcgop2, target, source)\
+static void gen_##name(DisasContext *ctx)   \
+{   \
+if (xS(ctx->opcode) < 32) { \
+if (unlikely(!ctx->fpu_enabled)) {  \
+gen_exception(ctx, POWERPC_EXCP_FPU);   \
+return; \
+}   \
+} else {\
+if (unlikely(!ctx->altivec_enabled)) {  \
+gen_exception(ctx, POWERPC_EXCP_VPU);   \
+return; \
+}   \
+}   \
+TCGv_i64 tmp = tcg_temp_new_i64();  \
+tcg_gen_##tcgop1(tmp, source);  \
+tcg_gen_##tcgop2(target, tmp);  \
+tcg_temp_free_i64(tmp); \
+}
+
+
+MV_VSR(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
+   cpu_vsrh(xS(ctx->opcode)))
+MV_VSR(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
+   cpu_gpr[rA(ctx->opcode)])
+MV_VSR(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
+   cpu_gpr[rA(ctx->opcode)])
+#if defined(TARGET_PPC64)
+MV_VSR(mfvsrd, mov_i64, mov_i64, cpu_gpr[rA(ctx->opcode)], \
+   cpu_vsrh(xS(ctx->opcode)))
+MV_VSR(mtvsrd, mov_i64, mov_i64, cpu_vsrh(xT(ctx->opcode)), \
+   cpu_gpr[rA(ctx->opcode)])
+#endif
+
 static void gen_xxpermdi(DisasContext *ctx)
 {
 if (unlikely(!ctx->vsx_enabled)) {
@@ -10094,6 +10128,14 @@ GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, 
PPC2_VSX207),
 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
 
+GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0xF800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0xF800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0xF800, PPC_NONE, PPC2_VSX207),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0xF800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0xF800, PPC_NONE, PPC2_VSX207),
+#endif
+
 #undef GEN_XX2FORM
 #define GEN_XX2FORM(name, opc2, opc3, fl2)   \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
-- 
1.7.1

Re: [Qemu-devel] [PATCHv2 05/18] qemu-iotests: fix tests 014 and 023 to work with any protocol

[Kevin Wolf]

Am 10.01.2014 um 20:06 hat Peter Lieven geschrieben:
> Am 10.01.2014 20:04, schrieb Kevin Wolf:
> > Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
> >> On 06.01.2014 06:40, Fam Zheng wrote:
> >>> On 2014年01月06日 01:21, Peter Lieven wrote:
>  Signed-off-by: Peter Lieven 
>  ---
>   tests/qemu-iotests/014|4 ++--
>   tests/qemu-iotests/014.out|2 +-
>   tests/qemu-iotests/023|   11 +--
>   tests/qemu-iotests/023.out|   16 
>   tests/qemu-iotests/common.pattern |7 +++
>   5 files changed, 19 insertions(+), 21 deletions(-)
> 
>  diff --git a/tests/qemu-iotests/014 b/tests/qemu-iotests/014
>  index b23c2db..01fb614 100755
>  --- a/tests/qemu-iotests/014
>  +++ b/tests/qemu-iotests/014
>  @@ -43,14 +43,14 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
> 
>   # much of this could be generic for any format supporting snapshots
>   _supported_fmt qcow2
>  -_supported_proto file
>  +_supported_proto generic
>   _supported_os Linux
> 
>   TEST_OFFSETS="0 4294967296"
>   TEST_OPS="writev read write readv"
>   CLUSTER_SIZE=4096
> 
>  -_make_test_img 6G
>  +TEST_IMG=$TEST_IMG.orig _make_test_img 6G
> 
>   echo "Testing empty image:"
>   for offset in $TEST_OFFSETS; do
>  diff --git a/tests/qemu-iotests/014.out b/tests/qemu-iotests/014.out
>  index 4744b4b..6459af0 100644
>  --- a/tests/qemu-iotests/014.out
>  +++ b/tests/qemu-iotests/014.out
>  @@ -1,5 +1,5 @@
>   QA output created by 014
>  -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=6442450944
>  +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=6442450944
>   Testing empty image:
>   test2: With offset 0
>   === Clusters to be compressed [1]
>  diff --git a/tests/qemu-iotests/023 b/tests/qemu-iotests/023
>  index 9ad06b9..2357696 100755
>  --- a/tests/qemu-iotests/023
>  +++ b/tests/qemu-iotests/023
>  @@ -41,7 +41,7 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
> 
>   # much of this could be generic for any format supporting compression.
>   _supported_fmt qcow qcow2
>  -_supported_proto file
>  +_supported_proto generic
>   _supported_os Linux
> 
>   TEST_OFFSETS="0 4294967296"
>  @@ -55,7 +55,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>   echo "Creating new image; cluster size: $CLUSTER_SIZE"
>   echo
> 
>  -_make_test_img 8G
>  +TEST_IMG=$TEST_IMG.orig _make_test_img 8G
> 
>   echo "Testing empty image"
>   echo
>  @@ -63,15 +63,14 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>   for offset in $TEST_OFFSETS; do
>   echo "At offset $offset:"
>   for op in $TEST_OPS; do
>  -io_test $op $offset $CLUSTER_SIZE 3
>  +TEST_IMG=$TEST_IMG.orig io_test $op $offset $CLUSTER_SIZE 3
>   done
>  -_check_test_img
>  +TEST_IMG=$TEST_IMG.orig _check_test_img
>   done
> 
>   echo "Compressing image"
>   echo
> 
>  -mv "$TEST_IMG" "$TEST_IMG.orig"
>   $QEMU_IMG convert -f $IMGFMT -O $IMGFMT -c "$TEST_IMG.orig" 
>  "$TEST_IMG"
> 
>   echo "Testing compressed image"
>  @@ -101,7 +100,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>   echo "Creating another new image"
>   echo
> 
>  -_make_test_img 8G
>  +TEST_IMG=$TEST_IMG.orig _make_test_img 8G
> 
>   echo "More complex patterns"
>   echo
>  diff --git a/tests/qemu-iotests/023.out b/tests/qemu-iotests/023.out
>  index ec32341..b80836d 100644
>  --- a/tests/qemu-iotests/023.out
>  +++ b/tests/qemu-iotests/023.out
>  @@ -1,7 +1,7 @@
>   QA output created by 023
>   Creating new image; cluster size: 1024
> 
>  -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>  +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>   Testing empty image
> 
>   At offset 0:
>  @@ -5664,7 +5664,7 @@ read 3072/3072 bytes at offset 4295491072
>   No errors were found on the image.
>   Creating another new image
> 
>  -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>  +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>   More complex patterns
> 
>   test2: With offset 0
>  @@ -5887,7 +5887,7 @@ read 2048/2048 bytes at offset 4295001088
>   No errors were found on the image.
>   Creating new image; cluster size: 4096
> 
>  -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>  +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>   Testing empty image
> 
>   At offset 0:
>  @@ -12270,7 +12270,7 @@ read 12288/12288 bytes at offset 4301256704
>   No errors were found on the image.
> >

[Qemu-devel] [V6 PATCH 14/18] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc

[Tom Musta]

This patchs adds the VSX Logical instructions that are new with
ISA V2.07:

  - VSX Logical Equivalence (xxleqv)
  - VSX Logical NAND (xxlnand)
  - VSX Logical ORC (xxlorc)

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V5: Changes to address tcg-debug compilation errors.

 target-ppc/translate.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7659085..e2dd272 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7468,6 +7468,9 @@ VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
+VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
+VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
+VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
 
 #define VSX_XXMRG(name, high)   \
 static void glue(gen_, name)(DisasContext * ctx)\
@@ -10283,6 +10286,9 @@ VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
+VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
+VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
-- 
1.7.1

Re: [Qemu-devel] [PATCH target-arm v4 2/3] zynq_slcr: Add links to the CPUs

[Peter Crosthwaite]

On Sat, Jan 11, 2014 at 4:11 AM, Peter Maydell  wrote:
> On 2 January 2014 07:31, Peter Crosthwaite  
> wrote:
>> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
>> SLCR.
>
>> @@ -496,10 +500,17 @@ static const MemoryRegionOps slcr_ops = {
>>  static int zynq_slcr_init(SysBusDevice *dev)
>>  {
>>  ZynqSLCRState *s = ZYNQ_SLCR(dev);
>> +int i;
>>
>>  memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 
>> 0x1000);
>>  sysbus_init_mmio(dev, &s->iomem);
>>
>> +for (i = 0; i < NUM_CPUS; ++i) {
>> +gchar *name = g_strdup_printf("cpu%d", i);
>> +object_property_add_link(OBJECT(dev), name, TYPE_CPU,
>> + (Object **)&s->cpus[i], NULL);
>> +g_free(name);
>> +}
>
> This is where we get into the nasty questions of how
> we ought to be modelling reset. I don't think that
> reset controllers ought to work by having direct links
> to a pile of QOM device objects. I'd much rather we tried
> to work towards modelling this the way the hardware does,
> ie a QOM device has one or more inbound GPIO lines
> corresponding to the hardware's reset signals, and the
> SoC or board wires those up to the reset controller
> appropriately.
>

So all nice solutions to this really want named GPIOs which is
something of a long term sore-point. Are you happy to take a simple
addition of a reset GPIO to ARMCPU  (which itself just calls
cpu_reset) without the need for the big planned GPIO fixups (whether
than be pins of Andreas' QOMification)?

Regards,
Peter

> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Kevin Wolf]

Am 10.01.2014 um 20:03 hat Peter Feiner geschrieben:
> On Fri, Jan 10, 2014 at 1:26 PM, Kevin Wolf  wrote:
> > Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> >> On 10.01.2014 18:55, Kevin Wolf wrote:
> >> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >> >there?
> >>
> >> Yes, feel free to.
> >
> > Thanks, applied to the block branch.
> >
> > Peter, no need for a second version of the patch then. :-)
> 
> I'll still submit v2 to add braces and incorporate the examples in
> tests/qemu-iotests.

Oh, right, that should still be done. Thanks for stopping me.

Kevin

Re: [Qemu-devel] [PATCH 10/10] target-arm: A64: Add SIMD scalar copy instructions

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +/* C6.3.31 DUP (element, scalar)
> + *  31   21 2016 1510  95 40
> + * +---++-+--+--+
> + * | 0 1 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 0 1 |  Rn  |  Rd  |
> + * +---++-+--+--+
> + */

Error...  1

Otherwise,

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH 09/10] target-arm: A64: Add SIMD modified immediate group

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +case 0: /* Replicate(Zeros(24):imm8, 2) */
> +case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
> +case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
> +case 3: /* Replicate(imm8:Zeros(24), 2) */
> +{
> +int shift = cmode_3_1 * 8;
> +imm = (abcdefgh << shift) | (abcdefgh << (32 + shift));
> +break;
> +}

Better to use bitfield_replicate with these?

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [V6 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds

[Tom Musta]

This patch adds the Single Precision VSX Scalar Fused Multiply-Add
instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
xsnmaddmsp, xsnmsubasp, xsnmsubmsp.

The existing VSX_MADD() macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Re-implemented per feedback from Richard Henderson.  In order to
avoid double rounding and incorrect results, the operands must be
converted to true single precision values and use the single precision
fused multiply/add routine.

V3: Re-implemented per feedback from Richard Henderson (I did not
fully understand his comment when I implemented V2).

V4: Changed to use helper_frsp (inadvertently re-injected when I used
an earlier patch).  Thanks to Richard Henderson for catching this.

 target-ppc/fpu_helper.c |   82 ++
 target-ppc/helper.h |8 
 target-ppc/translate.c  |   16 +
 3 files changed, 77 insertions(+), 29 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 33da462..7e5003a 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2192,7 +2192,7 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
  *   afrm  - A form (1=A, 0=M)
  *   sfprf - set FPRF
  */
-#define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf)\
+#define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp)  \
 void helper_##op(CPUPPCState *env, uint32_t opcode)   \
 { \
 ppc_vsr_t xt_in, xa, xb, xt_out;  \
@@ -2218,8 +2218,18 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 for (i = 0; i < nels; i++) {  \
 float_status tstat = env->fp_status;  \
 set_float_exception_flags(0, &tstat); \
-xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i],  \
- maddflgs, &tstat);   \
+if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
+/* Avoid double rounding errors by rounding the intermediate */   \
+/* result to odd.*/   \
+set_float_rounding_mode(float_round_to_zero, &tstat); \
+xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i],  \
+   maddflgs, &tstat); \
+xt_out.fld[i] |= (get_float_exception_flags(&tstat) & \
+  float_flag_inexact) != 0;   \
+} else {  \
+xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i],  \
+maddflgs, &tstat);\
+} \
 env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
   \
 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
@@ -2242,6 +2252,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
 } \
 } \
+  \
+if (r2sp) {   \
+xt_out.fld[i] = helper_frsp(env, xt_out.fld[i]);  \
+} \
+  \
 if (sfprf) {  \
 helper_compute_fprf(env, xt_out.fld[i], sfprf);   \
 } \
@@ -2255,32 +2270,41 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) 
  \
 #define NMADD_FLGS float_muladd_negate_result
 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
 
-VSX_MADD(xsmaddadp, 1, float64, f64, MADD_FLGS, 1, 1)
-VSX_MADD(xsmaddmdp, 1, float64, f64, MADD_FLGS, 0, 1)
-VSX_MADD(xsmsubadp, 1, float64, f64, MSUB_FLGS, 1, 1)
-VSX_MADD(xsmsubmdp, 1, float64, f64, MSUB_FLGS, 0, 1)
-VSX_MADD(xsnmaddadp, 1, float64, f64, NMADD_FLGS, 1, 1)
-VSX_MADD(xsnmaddmdp, 

Re: [Qemu-devel] [PATCH 08/10] target-arm: A64: Add SIMD copy operations

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> From: Alex Bennée 
> 
> This adds support for the all the AdvSIMD vector copy operations
> (ARM ARM 3.6.5).
> 
> Signed-off-by: Alex Bennée 
> Signed-off-by: Peter Maydell 
> ---
>  target-arm/translate-a64.c | 210 
> -
>  1 file changed, 209 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [V6 PATCH 00/18] target-ppc: VSX Stage 4

[Tom Musta]

This is the fourth and final series of patches that add emulation support
to QEMU for the PowerPC Vector Scalar Extension (VSX).

This series adds the instructions that were newly introduced with Power ISA
V2.07.  This includes 3 scalar load instructions, 2 scalar store instructions,
7 standard single precision scalar arithmetic instructions, 8 scalar single
precision fused multiply/add instructions, two integer-to-single-precision
conversion instructions and 3 vector logical instructions.

The single-precision scalar arithmetic instructions all interpret the most
significant 64 bits of a VSR as a single precision floating point number
stored in double precision format (similar to the standard PowerPC floating
point single precision instructions).  Thus a common theme in the supporting
code is rounding of an intermediate double-precision number to single 
precision.

V2: (a) Changed the rounding to single precision to reuse the existing
helper_frsp() routine.  (b) Re-implemented the fused multiply/add instructions
to use float32_muladd instead of float64_muladd, which avoids subtle rounding
errors.

V3: Re-implemented fused multiply/add per clarification from Richard Henderson.

V4: Changed fused multiply/add to use helper_frsp (inadvertently re-injected
when I used an earlier patch).  

V5: Fixed tcg compilation problems.

V6: Added instructions that were previously missed.

Tom Musta (18):
  target-ppc: VSX Stage 4: Add VSX 2.07 Flag
  target-ppc: VSX Stage 4: Refactor lxsdx
  target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
  target-ppc: VSX Stage 4: Refactor stxsdx
  target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
  target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
  target-ppc: VSX Stage 4: Add xsmulsp
  target-ppc: VSX Stage 4: Add xsdivsp
  target-ppc: VSX Stage 4: Add xsresp
  target-ppc: VSX Stage 4: Add xssqrtsp
  target-ppc: VSX Stage 4: add xsrsqrtesp
  target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
  target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
  target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
  target-ppc: Move To/From VSR Instructions
  target-ppc: Floating Merge Word Instructions
  target-ppc: Scalar Round to Single Precision
  target-ppc: Scalar Non-Signalling Conversions

 target-ppc/cpu.h|4 +-
 target-ppc/fpu_helper.c |  231 ++-
 target-ppc/helper.h |   21 
 target-ppc/translate.c  |  195 +++-
 target-ppc/translate_init.c |2 +-
 5 files changed, 359 insertions(+), 94 deletions(-)

[Qemu-devel] [V6 PATCH 11/18] target-ppc: VSX Stage 4: add xsrsqrtesp

[Tom Musta]

This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.

The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Updated conversion to single precision range.

 target-ppc/fpu_helper.c |   13 +
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index fec9d1b..33da462 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2018,7 +2018,7 @@ VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_RSQRTE(op, nels, tp, fld, sfprf) \
+#define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp)   \
 void helper_##op(CPUPPCState *env, uint32_t opcode)  \
 {\
 ppc_vsr_t xt, xb;\
@@ -2043,6 +2043,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 }\
 }\
  \
+if (r2sp) {  \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+}\
+ \
 if (sfprf) { \
 helper_compute_fprf(env, xt.fld[i], sfprf);  \
 }\
@@ -2052,9 +2056,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 helper_float_check_status(env);  \
 }
 
-VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1)
-VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0)
-VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0)
+VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1, 0)
+VSX_RSQRTE(xsrsqrtesp, 1, float64, f64, 1, 1)
+VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0, 0)
+VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0, 0)
 
 static inline int ppc_float32_get_unbiased_exp(float32 f)
 {
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0192043..84c6ee1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -292,6 +292,7 @@ DEF_HELPER_2(xsmulsp, void, env, i32)
 DEF_HELPER_2(xsdivsp, void, env, i32)
 DEF_HELPER_2(xsresp, void, env, i32)
 DEF_HELPER_2(xssqrtsp, void, env, i32)
+DEF_HELPER_2(xsrsqrtesp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f4c1f42..950c02e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7364,6 +7364,7 @@ GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10177,6 +10178,7 @@ GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
 GEN_XX2FORM(xsresp,  0x14, 0x01, PPC2_VSX207),
 GEN_XX2FORM(xssqrtsp,  0x16, 0x00, PPC2_VSX207),
+GEN_XX2FORM(xsrsqrtesp,  0x14, 0x00, PPC2_VSX207),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-- 
1.7.1

Re: [Qemu-devel] [PATCH 07/10] target-arm: A64: Add SIMD across-lanes instructions

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> From: Michael Matz 
> 
> Add support for the SIMD "across lanes" instruction group (C3.6.4).
> 
> Signed-off-by: Michael Matz 
> [PMM: Updated to current codebase, added fp min/max ops,
>  added unallocated encoding checks]
> Signed-off-by: Peter Maydell 
> ---
>  target-arm/translate-a64.c | 177 
> -
>  1 file changed, 176 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCHv2 05/18] qemu-iotests: fix tests 014 and 023 to work with any protocol

[Peter Lieven]

Am 10.01.2014 20:14, schrieb Kevin Wolf:
> Am 10.01.2014 um 20:06 hat Peter Lieven geschrieben:
>> Am 10.01.2014 20:04, schrieb Kevin Wolf:
>>> Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
 On 06.01.2014 06:40, Fam Zheng wrote:
> On 2014年01月06日 01:21, Peter Lieven wrote:
>> Signed-off-by: Peter Lieven 
>> ---
>>  tests/qemu-iotests/014|4 ++--
>>  tests/qemu-iotests/014.out|2 +-
>>  tests/qemu-iotests/023|   11 +--
>>  tests/qemu-iotests/023.out|   16 
>>  tests/qemu-iotests/common.pattern |7 +++
>>  5 files changed, 19 insertions(+), 21 deletions(-)
>>
>> diff --git a/tests/qemu-iotests/014 b/tests/qemu-iotests/014
>> index b23c2db..01fb614 100755
>> --- a/tests/qemu-iotests/014
>> +++ b/tests/qemu-iotests/014
>> @@ -43,14 +43,14 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
>>
>>  # much of this could be generic for any format supporting snapshots
>>  _supported_fmt qcow2
>> -_supported_proto file
>> +_supported_proto generic
>>  _supported_os Linux
>>
>>  TEST_OFFSETS="0 4294967296"
>>  TEST_OPS="writev read write readv"
>>  CLUSTER_SIZE=4096
>>
>> -_make_test_img 6G
>> +TEST_IMG=$TEST_IMG.orig _make_test_img 6G
>>
>>  echo "Testing empty image:"
>>  for offset in $TEST_OFFSETS; do
>> diff --git a/tests/qemu-iotests/014.out b/tests/qemu-iotests/014.out
>> index 4744b4b..6459af0 100644
>> --- a/tests/qemu-iotests/014.out
>> +++ b/tests/qemu-iotests/014.out
>> @@ -1,5 +1,5 @@
>>  QA output created by 014
>> -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=6442450944
>> +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=6442450944
>>  Testing empty image:
>>  test2: With offset 0
>>  === Clusters to be compressed [1]
>> diff --git a/tests/qemu-iotests/023 b/tests/qemu-iotests/023
>> index 9ad06b9..2357696 100755
>> --- a/tests/qemu-iotests/023
>> +++ b/tests/qemu-iotests/023
>> @@ -41,7 +41,7 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
>>
>>  # much of this could be generic for any format supporting compression.
>>  _supported_fmt qcow qcow2
>> -_supported_proto file
>> +_supported_proto generic
>>  _supported_os Linux
>>
>>  TEST_OFFSETS="0 4294967296"
>> @@ -55,7 +55,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>>  echo "Creating new image; cluster size: $CLUSTER_SIZE"
>>  echo
>>
>> -_make_test_img 8G
>> +TEST_IMG=$TEST_IMG.orig _make_test_img 8G
>>
>>  echo "Testing empty image"
>>  echo
>> @@ -63,15 +63,14 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>>  for offset in $TEST_OFFSETS; do
>>  echo "At offset $offset:"
>>  for op in $TEST_OPS; do
>> -io_test $op $offset $CLUSTER_SIZE 3
>> +TEST_IMG=$TEST_IMG.orig io_test $op $offset $CLUSTER_SIZE 3
>>  done
>> -_check_test_img
>> +TEST_IMG=$TEST_IMG.orig _check_test_img
>>  done
>>
>>  echo "Compressing image"
>>  echo
>>
>> -mv "$TEST_IMG" "$TEST_IMG.orig"
>>  $QEMU_IMG convert -f $IMGFMT -O $IMGFMT -c "$TEST_IMG.orig" 
>> "$TEST_IMG"
>>
>>  echo "Testing compressed image"
>> @@ -101,7 +100,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
>>  echo "Creating another new image"
>>  echo
>>
>> -_make_test_img 8G
>> +TEST_IMG=$TEST_IMG.orig _make_test_img 8G
>>
>>  echo "More complex patterns"
>>  echo
>> diff --git a/tests/qemu-iotests/023.out b/tests/qemu-iotests/023.out
>> index ec32341..b80836d 100644
>> --- a/tests/qemu-iotests/023.out
>> +++ b/tests/qemu-iotests/023.out
>> @@ -1,7 +1,7 @@
>>  QA output created by 023
>>  Creating new image; cluster size: 1024
>>
>> -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>> +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>>  Testing empty image
>>
>>  At offset 0:
>> @@ -5664,7 +5664,7 @@ read 3072/3072 bytes at offset 4295491072
>>  No errors were found on the image.
>>  Creating another new image
>>
>> -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>> +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>>  More complex patterns
>>
>>  test2: With offset 0
>> @@ -5887,7 +5887,7 @@ read 2048/2048 bytes at offset 4295001088
>>  No errors were found on the image.
>>  Creating new image; cluster size: 4096
>>
>> -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
>> +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
>>  Testing empty image
>>
>>  At offset 0:
>> @@ -12270,7 +12270,7 @@ read 12288/12288 bytes at offset 4301256704
>>

[Qemu-devel] [V6 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp

[Tom Musta]

This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point
Format and Round to Single Precision (xscvsxdsp) instructions.

The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP)
is modified to support the rounding of the intermediate floating point
result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: updated conversion to single precision range.

 target-ppc/fpu_helper.c |   27 ---
 target-ppc/helper.h |2 ++
 target-ppc/translate.c  |4 
 3 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 7e5003a..1dfb3c0 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2558,7 +2558,7 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, f32[j], 
u32[i], i, 0)
  *   jdef  - definition of the j index (i or 2*i)
  *   sfprf - set FPRF
  */
-#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf)  \
+#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf, r2sp) \
 void helper_##op(CPUPPCState *env, uint32_t opcode) \
 {   \
 ppc_vsr_t xt, xb;   \
@@ -2570,6 +2570,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)   
  \
 for (i = 0; i < nels; i++) {\
 int j = jdef;   \
 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
+if (r2sp) { \
+xt.tfld = helper_frsp(env, xt.tfld);\
+}   \
 if (sfprf) {\
 helper_compute_fprf(env, xt.tfld, sfprf);   \
 }   \
@@ -2579,20 +2582,22 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) 
\
 helper_float_check_status(env); \
 }
 
-VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1)
-VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1)
-VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0)
-VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0)
+VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1, 0)
+VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1, 0)
+VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, u64[j], f64[i], i, 1, 1)
+VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, u64[j], f64[i], i, 1, 1)
+VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0, 0)
 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, u32[j], f64[i], \
-  2*i + JOFFSET, 0)
+  2*i + JOFFSET, 0, 0)
 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, u32[j], f64[i], \
-  2*i + JOFFSET, 0)
+  2*i + JOFFSET, 0, 0)
 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, u64[i], f32[j], \
-  2*i + JOFFSET, 0)
+  2*i + JOFFSET, 0, 0)
 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, u64[i], f32[j], \
-  2*i + JOFFSET, 0)
-VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0)
-VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0)
+  2*i + JOFFSET, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0, 0)
 
 /* For "use current rounding mode", define a value that will not be one of
  * the existing rounding model enums.
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 655b670..6250eba 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -279,6 +279,8 @@ DEF_HELPER_2(xscvdpsxws, void, env, i32)
 DEF_HELPER_2(xscvdpuxds, void, env, i32)
 DEF_HELPER_2(xscvdpuxws, void, env, i32)
 DEF_HELPER_2(xscvsxddp, void, env, i32)
+DEF_HELPER_2(xscvuxdsp, void, env, i32)
+DEF_HELPER_2(xscvsxdsp, void, env, i32)
 DEF_HELPER_2(xscvuxddp, void, env, i32)
 DEF_HELPER_2(xsrdpi, void, env, i32)
 DEF_HELPER_2(xsrdpic, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5b68c7e..7659085 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7373,6 +7373,8 @@ GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
 GEN_VSX_HELPE

Re: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +for (i = 0; i < elements; i++) {
> +switch (opcode) {
> +case 1: /* UZP1/2 */
> +{
> +int midpoint = elements / 2;
> +if (i < midpoint) {
> +read_vec_element(s, tcg_res, rn, 2 * i + part, size);
> +} else {
> +read_vec_element(s, tcg_res, rm,
> + 2 * (i - midpoint) + part, size);
> +}
> +break;
> +}

You're generating up to 16 * 3 + 2 = 50 opcodes here.  I do wonder if it
wouldn't be better to implement these as helpers.  But,

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH 05/10] target-arm: A64: Add SIMD TBL/TBLX

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t 
> indices,
> +  uint64_t rn, uint64_t numregs)

Better with rn and numregs uint32_t?

Otherwise,

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH 04/10] target-arm: A64: Add SIMD EXT

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +if (pos < 64) {
> +tcg_resl = do_ext64(s, rn, 1, rn, 0, pos);
> +tcg_resh = do_ext64(s, rm, 0, rn, 1, pos);
> +} else {
> +tcg_resl = do_ext64(s, rm, 0, rn, 1, pos - 64);
> +tcg_resh = do_ext64(s, rm, 1, rm, 0, pos - 64);
> +}

Perhaps better to pre-load the values before do_ext64?

In the first case you're loading rn[1] twice, and in the second rm[0] twice.

Otherwise,

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions

[Tom Musta]

This patch adds the non-signalling scalar conversion instructions:

  - VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
  - VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)

Signed-off-by: Tom Musta 
---
V6: New.

 target-ppc/fpu_helper.c |   19 +++
 target-ppc/helper.h |2 ++
 target-ppc/translate.c  |4 
 3 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c1524e3..8bb647c 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2487,6 +2487,25 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], 
f64[i], 1)
 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
 
+#define VSX_CVT_FP_TO_FP_NONSIG(op, stp, ttp, sfld, tfld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode)   \
+{ \
+ppc_vsr_t xt, xb; \
+  \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+  \
+float_status tstat = env->fp_status;  \
+set_float_exception_flags(0, &tstat); \
+  \
+xt.tfld[0] = stp##_to_##ttp(xb.sfld[0], &tstat);  \
+  \
+putVSR(xT(opcode), &xt, env); \
+}
+
+VSX_CVT_FP_TO_FP_NONSIG(xscvdpspn, float64, float32, f64, f32)
+VSX_CVT_FP_TO_FP_NONSIG(xscvspdpn, float32, float64, f32, f64)
+
 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
  *   op- instruction mnemonic
  *   nels  - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 300e194..753ab01 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -273,7 +273,9 @@ DEF_HELPER_2(xscmpudp, void, env, i32)
 DEF_HELPER_2(xsmaxdp, void, env, i32)
 DEF_HELPER_2(xsmindp, void, env, i32)
 DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvdpspn, void, env, i32)
 DEF_HELPER_2(xscvspdp, void, env, i32)
+DEF_HELPER_2(xscvspdpn, void, env, i32)
 DEF_HELPER_2(xscvdpsxds, void, env, i32)
 DEF_HELPER_2(xscvdpsxws, void, env, i32)
 DEF_HELPER_2(xscvdpuxds, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 48b93c8..dde5a06 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7408,7 +7408,9 @@ GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
@@ -10246,7 +10248,9 @@ GEN_XX2FORM(xscmpudp,  0x0C, 0x04, PPC2_VSX),
 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 05/18] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx

[Tom Musta]

This patch adds two store scalar instructions:

  - Store VSX Scalar as Integer Word Indexed (stxsiwx)
  - Store VSX Scalar Single-Precision Indexed (stxsspx)

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V5: Updated to address tcg-debug compliation errors.

 target-ppc/translate.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9f3dda7..28794d1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7128,6 +7128,8 @@ static void gen_##name(DisasContext *ctx) 
\
 }
 
 VSX_STORE_SCALAR(stxsdx, st64)
+VSX_STORE_SCALAR(stxsiwx, st32_i64)
+VSX_STORE_SCALAR(stxsspx, st32fs)
 
 static void gen_stxvd2x(DisasContext *ctx)
 {
@@ -10066,6 +10068,8 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, 
PPC2_VSX),
 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
 
 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
 
-- 
1.7.1

[Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision

[Tom Musta]

This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.

Signed-off-by: Tom Musta 
---
V6: New.

 target-ppc/fpu_helper.c |   17 +
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1dfb3c0..c1524e3 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2666,3 +2666,20 @@ VSX_ROUND(xvrspic, 4, float32, f32, FLOAT_ROUND_CURRENT, 
0)
 VSX_ROUND(xvrspim, 4, float32, f32, float_round_down, 0)
 VSX_ROUND(xvrspip, 4, float32, f32, float_round_up, 0)
 VSX_ROUND(xvrspiz, 4, float32, f32, float_round_to_zero, 0)
+
+void helper_xsrsp(CPUPPCState *env, uint32_t opcode)
+{
+ppc_vsr_t xt, xb;
+
+getVSR(xB(opcode), &xb, env);
+getVSR(xT(opcode), &xt, env);
+
+helper_reset_fpstatus(env);
+
+xt.f64[0] = helper_frsp(env, xb.f64[0]);
+
+helper_compute_fprf(env, xt.f64[0], 1);
+
+putVSR(xT(opcode), &xt, env);
+helper_float_check_status(env);
+}
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6250eba..300e194 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -293,6 +293,7 @@ DEF_HELPER_2(xssubsp, void, env, i32)
 DEF_HELPER_2(xsmulsp, void, env, i32)
 DEF_HELPER_2(xsdivsp, void, env, i32)
 DEF_HELPER_2(xsresp, void, env, i32)
+DEF_HELPER_2(xsrsp, void, env, i32)
 DEF_HELPER_2(xssqrtsp, void, env, i32)
 DEF_HELPER_2(xsrsqrtesp, void, env, i32)
 DEF_HELPER_2(xsmaddasp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7f2a66f..48b93c8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7426,6 +7426,7 @@ GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
@@ -10263,6 +10264,7 @@ GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
 GEN_XX2FORM(xsresp,  0x14, 0x01, PPC2_VSX207),
+GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
 GEN_XX2FORM(xssqrtsp,  0x16, 0x00, PPC2_VSX207),
 GEN_XX2FORM(xsrsqrtesp,  0x14, 0x00, PPC2_VSX207),
 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 07/18] target-ppc: VSX Stage 4: Add xsmulsp

[Tom Musta]

This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.

The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Updated conversion to single precision.

 target-ppc/fpu_helper.c |   13 +
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index f047640..dc9849f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1822,7 +1822,7 @@ VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_MUL(op, nels, tp, fld, sfprf)\
+#define VSX_MUL(op, nels, tp, fld, sfprf, r2sp)  \
 void helper_##op(CPUPPCState *env, uint32_t opcode)  \
 {\
 ppc_vsr_t xt, xa, xb;\
@@ -1849,6 +1849,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 }\
 }\
  \
+if (r2sp) {  \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+}\
+ \
 if (sfprf) { \
 helper_compute_fprf(env, xt.fld[i], sfprf);  \
 }\
@@ -1858,9 +1862,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 helper_float_check_status(env);  \
 }
 
-VSX_MUL(xsmuldp, 1, float64, f64, 1)
-VSX_MUL(xvmuldp, 2, float64, f64, 0)
-VSX_MUL(xvmulsp, 4, float32, f32, 0)
+VSX_MUL(xsmuldp, 1, float64, f64, 1, 0)
+VSX_MUL(xsmulsp, 1, float64, f64, 1, 1)
+VSX_MUL(xvmuldp, 2, float64, f64, 0, 0)
+VSX_MUL(xvmulsp, 4, float32, f32, 0, 0)
 
 /* VSX_DIV - VSX floating point divide
  *   op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 696b9d3..0ccdc96 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -288,6 +288,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32)
 
 DEF_HELPER_2(xsaddsp, void, env, i32)
 DEF_HELPER_2(xssubsp, void, env, i32)
+DEF_HELPER_2(xsmulsp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c50d800..3a6a94b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7360,6 +7360,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
 
 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10169,6 +10170,7 @@ GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
 
 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
+GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp

[Tom Musta]

This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.

The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Updated conversion to single precision range.

 target-ppc/fpu_helper.c |   14 ++
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 49cf09a..ac52c23 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1928,7 +1928,7 @@ VSX_DIV(xvdivsp, 4, float32, f32, 0, 0)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_RE(op, nels, tp, fld, sfprf)  \
+#define VSX_RE(op, nels, tp, fld, sfprf, r2sp)\
 void helper_##op(CPUPPCState *env, uint32_t opcode)   \
 { \
 ppc_vsr_t xt, xb; \
@@ -1943,6 +1943,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
 } \
 xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status);   \
+  \
+if (r2sp) {   \
+xt.fld[i] = helper_frsp(env, xt.fld[i]);  \
+} \
+  \
 if (sfprf) {  \
 helper_compute_fprf(env, xt.fld[0], sfprf);   \
 } \
@@ -1952,9 +1957,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
 \
 helper_float_check_status(env);   \
 }
 
-VSX_RE(xsredp, 1, float64, f64, 1)
-VSX_RE(xvredp, 2, float64, f64, 0)
-VSX_RE(xvresp, 4, float32, f32, 0)
+VSX_RE(xsredp, 1, float64, f64, 1, 0)
+VSX_RE(xsresp, 1, float64, f64, 1, 1)
+VSX_RE(xvredp, 2, float64, f64, 0, 0)
+VSX_RE(xvresp, 4, float32, f32, 0, 0)
 
 /* VSX_SQRT - VSX floating point square root
  *   op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 308f97c..b1cf3c0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -290,6 +290,7 @@ DEF_HELPER_2(xsaddsp, void, env, i32)
 DEF_HELPER_2(xssubsp, void, env, i32)
 DEF_HELPER_2(xsmulsp, void, env, i32)
 DEF_HELPER_2(xsdivsp, void, env, i32)
+DEF_HELPER_2(xsresp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index eddb9d2..3108a29 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7362,6 +7362,7 @@ GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10173,6 +10174,7 @@ GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
+GEN_XX2FORM(xsresp,  0x14, 0x01, PPC2_VSX207),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 10/18] target-ppc: VSX Stage 4: Add xssqrtsp

[Tom Musta]

This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.

The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: Updated conversion to single precision range.

 target-ppc/fpu_helper.c |   13 +
 target-ppc/helper.h |1 +
 target-ppc/translate.c  |2 ++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index ac52c23..fec9d1b 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1969,7 +1969,7 @@ VSX_RE(xvresp, 4, float32, f32, 0, 0)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_SQRT(op, nels, tp, fld, sfprf)   \
+#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
 void helper_##op(CPUPPCState *env, uint32_t opcode)  \
 {\
 ppc_vsr_t xt, xb;\
@@ -1993,6 +1993,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 }\
 }\
  \
+if (r2sp) {  \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+}\
+ \
 if (sfprf) { \
 helper_compute_fprf(env, xt.fld[i], sfprf);  \
 }\
@@ -2002,9 +2006,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)  
\
 helper_float_check_status(env);  \
 }
 
-VSX_SQRT(xssqrtdp, 1, float64, f64, 1)
-VSX_SQRT(xvsqrtdp, 2, float64, f64, 0)
-VSX_SQRT(xvsqrtsp, 4, float32, f32, 0)
+VSX_SQRT(xssqrtdp, 1, float64, f64, 1, 0)
+VSX_SQRT(xssqrtsp, 1, float64, f64, 1, 1)
+VSX_SQRT(xvsqrtdp, 2, float64, f64, 0, 0)
+VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0)
 
 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
  *   op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index b1cf3c0..0192043 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -291,6 +291,7 @@ DEF_HELPER_2(xssubsp, void, env, i32)
 DEF_HELPER_2(xsmulsp, void, env, i32)
 DEF_HELPER_2(xsdivsp, void, env, i32)
 DEF_HELPER_2(xsresp, void, env, i32)
+DEF_HELPER_2(xssqrtsp, void, env, i32)
 
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3108a29..f4c1f42 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7363,6 +7363,7 @@ GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
 
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10175,6 +10176,7 @@ GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
 GEN_XX2FORM(xsresp,  0x14, 0x01, PPC2_VSX207),
+GEN_XX2FORM(xssqrtsp,  0x16, 0x00, PPC2_VSX207),
 
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 06/18] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp

[Tom Musta]

This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.

The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V2: updated conversion of result to single precision.

 target-ppc/fpu_helper.c |   20 +---
 target-ppc/helper.h |3 +++
 target-ppc/translate.c  |6 ++
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 3165ef0..f047640 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState 
*env)
  *   fld   - vsr_t field (f32 or f64)
  *   sfprf - set FPRF
  */
-#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf)  \
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp)\
 void helper_##name(CPUPPCState *env, uint32_t opcode)\
 {\
 ppc_vsr_t xt, xa, xb;\
@@ -1794,6 +1794,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)
\
 }\
 }\
  \
+if (r2sp) {  \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+}\
+ \
 if (sfprf) { \
 helper_compute_fprf(env, xt.fld[i], sfprf);  \
 }\
@@ -1802,12 +1806,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)   
 \
 helper_float_check_status(env);  \
 }
 
-VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
-VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
-VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
-VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
-VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
-VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0)
+VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
 
 /* VSX_MUL - VSX floating point multiply
  *   op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0276b02..696b9d3 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -286,6 +286,9 @@ DEF_HELPER_2(xsrdpim, void, env, i32)
 DEF_HELPER_2(xsrdpip, void, env, i32)
 DEF_HELPER_2(xsrdpiz, void, env, i32)
 
+DEF_HELPER_2(xsaddsp, void, env, i32)
+DEF_HELPER_2(xssubsp, void, env, i32)
+
 DEF_HELPER_2(xvadddp, void, env, i32)
 DEF_HELPER_2(xvsubdp, void, env, i32)
 DEF_HELPER_2(xvmuldp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 28794d1..c50d800 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7358,6 +7358,9 @@ GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
 
+GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
+
 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
@@ -10164,6 +10167,9 @@ GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
 
+GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
+GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
+
 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 03/18] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx

[Tom Musta]

This patch adds the scalar load instructions introduced in ISA
V2.07:

  - Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
  - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
  - Load VSX Scalar Single-Precision Indexed (lxsspx)

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
V5: Updated to fix tcg-debug compilation failures.

 target-ppc/translate.c |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ca26dcf..958ea94 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2585,6 +2585,14 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, 
TCGv arg1, TCGv arg2)
 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
 }
 
+static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
+{
+TCGv tmp = tcg_temp_new();
+gen_qemu_ld32s(ctx, tmp, addr);
+tcg_gen_ext_tl_i64(val, tmp);
+tcg_temp_free(tmp);
+}
+
 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
 {
 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
@@ -7039,6 +7047,9 @@ static void gen_##name(DisasContext *ctx) 
\
 }
 
 VSX_LOAD_SCALAR(lxsdx, ld64)
+VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
+VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
+VSX_LOAD_SCALAR(lxsspx, ld32fs)
 
 static void gen_lxvd2x(DisasContext *ctx)
 {
@@ -10044,6 +10055,9 @@ GEN_VAFORM_PAIRED(vsel, vperm, 21),
 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
 
 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
-- 
1.7.1

[Qemu-devel] [V6 PATCH 02/18] target-ppc: VSX Stage 4: Refactor lxsdx

[Tom Musta]

This patch refactors the lxsdx generator. Resuable code is isolated
into a macro.  The macro will be used in subsequent patches in this
series to implement other scalar load instructions.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
 target-ppc/translate.c |   31 +--
 1 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 79be8ed..ca26dcf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7022,20 +7022,23 @@ static inline TCGv_i64 cpu_vsrl(int n)
 }
 }
 
-static void gen_lxsdx(DisasContext *ctx)
-{
-TCGv EA;
-if (unlikely(!ctx->vsx_enabled)) {
-gen_exception(ctx, POWERPC_EXCP_VSXU);
-return;
-}
-gen_set_access_type(ctx, ACCESS_INT);
-EA = tcg_temp_new();
-gen_addr_reg_index(ctx, EA);
-gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
-/* NOTE: cpu_vsrl is undefined */
-tcg_temp_free(EA);
-}
+#define VSX_LOAD_SCALAR(name, operation)  \
+static void gen_##name(DisasContext *ctx) \
+{ \
+TCGv EA;  \
+if (unlikely(!ctx->vsx_enabled)) {\
+gen_exception(ctx, POWERPC_EXCP_VSXU);\
+return;   \
+} \
+gen_set_access_type(ctx, ACCESS_INT); \
+EA = tcg_temp_new();  \
+gen_addr_reg_index(ctx, EA);  \
+gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
+/* NOTE: cpu_vsrl is undefined */ \
+tcg_temp_free(EA);\
+}
+
+VSX_LOAD_SCALAR(lxsdx, ld64)
 
 static void gen_lxvd2x(DisasContext *ctx)
 {
-- 
1.7.1

[Qemu-devel] [V6 PATCH 01/18] target-ppc: VSX Stage 4: Add VSX 2.07 Flag

[Tom Musta]

This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07.  The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
 target-ppc/cpu.h|4 +++-
 target-ppc/translate_init.c |2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index bb84767..0abc848 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1875,9 +1875,11 @@ enum {
 PPC2_DBRX  = 0x0010ULL,
 /* Book I 2.05 PowerPC specification */
 PPC2_ISA205= 0x0020ULL,
+/* VSX additions in ISA 2.07 */
+PPC2_VSX207= 0x0040ULL,
 
 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
-  PPC2_ISA205)
+PPC2_ISA205 | PPC2_VSX207)
 };
 
 /*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c030a20..dd57df3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7312,7 +7312,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
-pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
 pcc->msr_mask = 0x8284FF36ULL;
 pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
-- 
1.7.1

[Qemu-devel] [V6 PATCH 04/18] target-ppc: VSX Stage 4: Refactor stxsdx

[Tom Musta]

This patch refactors the stxsdx instruction.  Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.

Signed-off-by: Tom Musta 
Reviewed-by: Richard Henderson 
---
 target-ppc/translate.c |   27 +++
 1 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 958ea94..9f3dda7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7112,20 +7112,23 @@ static void gen_lxvw4x(DisasContext *ctx)
 tcg_temp_free_i64(tmp);
 }
 
-static void gen_stxsdx(DisasContext *ctx)
-{
-TCGv EA;
-if (unlikely(!ctx->vsx_enabled)) {
-gen_exception(ctx, POWERPC_EXCP_VSXU);
-return;
-}
-gen_set_access_type(ctx, ACCESS_INT);
-EA = tcg_temp_new();
-gen_addr_reg_index(ctx, EA);
-gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
-tcg_temp_free(EA);
+#define VSX_STORE_SCALAR(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+TCGv EA;  \
+if (unlikely(!ctx->vsx_enabled)) {\
+gen_exception(ctx, POWERPC_EXCP_VSXU);\
+return;   \
+} \
+gen_set_access_type(ctx, ACCESS_INT); \
+EA = tcg_temp_new();  \
+gen_addr_reg_index(ctx, EA);  \
+gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
+tcg_temp_free(EA);\
 }
 
+VSX_STORE_SCALAR(stxsdx, st64)
+
 static void gen_stxvd2x(DisasContext *ctx)
 {
 TCGv EA;
-- 
1.7.1

Re: [Qemu-devel] [PULL 00/50] migration queue

[Anthony Liguori]

I can't find the patches in my inbox but this breaks because
test-vmstate.c ignores ftruncate errors which are marked as
warn_unused_result on Ubuntu.

Regards,

Anthony Liguori

On Tue, Dec 24, 2013 at 8:06 AM, Juan Quintela  wrote:
> Hi Anthony
>
> This is the patches in the migration queue.  Please pull.
>
> This includes:
>
> - Eduardo refactorings & tests
> - Matthew rate limit fix
> - Zhanghaoyu CANCELLING fixes
> - My bitmap changes
>
> Integration work was done by Orit.
>
> Happy Christmas, Juan.
>
>
> The following changes since commit f976b09ea2493fd41c98aaf6512908db0bae:
>
>   PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100)
>
> are available in the git repository at:
>
>   git://github.com/juanquintela/qemu.git tags/migration/20131224
>
> for you to fetch changes up to bc864a4f0ce79a8f4c09bc479a81c5f919ee48f6:
>
>   ram: align ram_addr_t's regions in multiples of 64 (2013-12-24 16:13:07 
> +0100)
>
> 
> migration.next for 20131224
>
> 
> Eduardo Habkost (9):
>   qemu-file: Make a few functions non-static
>   migration: Move QEMU_VM_* defines to migration/migration.h
>   savevm: Convert all tabs to spaces
>   savevm.c: Coding style fixes
>   savevm.c: Coding style fix
>   vmstate: Move VMState code to vmstate.c
>   qemu-file: Move QEMUFile code to qemu-file.c
>   savevm: Small comment about why timer QEMUFile/VMState code is in 
> savevm.c
>   tests: Some unit tests for vmstate.c
>
> Juan Quintela (38):
>   bitmap: use long as index
>   memory: cpu_physical_memory_set_dirty_flags() result is never used
>   memory: cpu_physical_memory_set_dirty_range() return void
>   exec: use accessor function to know if memory is dirty
>   memory: create function to set a single dirty bit
>   exec: create function to get a single dirty bit
>   memory: make cpu_physical_memory_is_dirty return bool
>   memory: all users of cpu_physical_memory_get_dirty used only one flag
>   memory: set single dirty flags when possible
>   memory: cpu_physical_memory_set_dirty_range() always dirty all flags
>   memory: cpu_physical_memory_mask_dirty_range() always clears a single 
> flag
>   memory: use bit 2 for migration
>   memory: make sure that client is always inside range
>   memory: only resize dirty bitmap when memory size increases
>   memory: cpu_physical_memory_clear_dirty_flag() result is never used
>   bitmap: Add bitmap_zero_extend operation
>   memory: split dirty bitmap into three
>   memory: unfold cpu_physical_memory_clear_dirty_flag() in its only user
>   memory: unfold cpu_physical_memory_set_dirty() in its only user
>   memory: unfold cpu_physical_memory_set_dirty_flag()
>   memory: make cpu_physical_memory_get_dirty() the main function
>   memory: cpu_physical_memory_get_dirty() is used as returning a bool
>   memory: s/mask/clear/ cpu_physical_memory_mask_dirty_range
>   memory: use find_next_bit() to find dirty bits
>   memory: cpu_physical_memory_set_dirty_range() now uses bitmap operations
>   memory: cpu_physical_memory_clear_dirty_range() now uses bitmap 
> operations
>   memory: s/dirty/clean/ in cpu_physical_memory_is_dirty()
>   memory: make cpu_physical_memory_reset_dirty() take a length parameter
>   memory: cpu_physical_memory_set_dirty_tracking() should return void
>   memory: split cpu_physical_memory_* functions to its own include
>   memory: unfold memory_region_test_and_clear()
>   kvm: use directly cpu_physical_memory_* api for tracking dirty pages
>   kvm: refactor start address calculation
>   memory: move bitmap synchronization to its own function
>   memory: syncronize kvm bitmap using bitmaps operations
>   ram: split function that synchronizes a range
>   migration: synchronize memory bitmap 64bits at a time
>   ram: align ram_addr_t's regions in multiples of 64
>
> Matthew Garrett (1):
>   migration: Fix rate limit
>
> Zhanghaoyu (A) (2):
>   avoid a bogus COMPLETED->CANCELLED transition
>   introduce MIG_STATE_CANCELLING state
>
>  Makefile.objs  |2 +
>  arch_init.c|   52 +-
>  cputlb.c   |   11 +-
>  exec.c |   78 +-
>  include/exec/cpu-all.h |3 +-
>  include/exec/memory-internal.h |   90 ---
>  include/exec/memory.h  |   12 +-
>  include/exec/ram_addr.h|  147 
>  include/migration/migration.h  |   11 +
>  include/migration/qemu-file.h  |4 +
>  include/qemu/bitmap.h  |   86 ++-
>  include/qemu/bitops.h  |   14 +-
>  kvm-all.c  |   28 +-
>  memory.c   |   17 +-
>  migration.c|   33 +-
>  qemu-file.c|  826 +
>

Re: [Qemu-devel] [PATCH v2 16/24] block: Make zero-after-EOF work with larger alignment

[Max Reitz]

On 13.12.2013 14:22, Kevin Wolf wrote:

Odd file sizes could make bdrv_aligned_preadv() shorten the request in
non-aligned ways. Fix it by rounding to the required alignment instead
of 512 bytes.

Signed-off-by: Kevin Wolf 
---
  block.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/block.c b/block.c
index b4f6ead..6dddb7c 100644
--- a/block.c
+++ b/block.c
@@ -2725,7 +2725,7 @@ err:
   */
  static int coroutine_fn bdrv_aligned_preadv(BlockDriverState *bs,
  BdrvTrackedRequest *req, int64_t offset, unsigned int bytes,
-QEMUIOVector *qiov, int flags)
+int64_t align, QEMUIOVector *qiov, int flags)
  {
  BlockDriver *drv = bs->drv;
  int ret;
@@ -2773,7 +2773,7 @@ static int coroutine_fn 
bdrv_aligned_preadv(BlockDriverState *bs,
  }
  
  total_sectors = DIV_ROUND_UP(len, BDRV_SECTOR_SIZE);

-max_nb_sectors = MAX(0, total_sectors - sector_num);
+max_nb_sectors = MAX(0, ROUND_UP(total_sectors - sector_num, align));


It appears this should be an alignment given in sectors…


  if (max_nb_sectors > 0) {
  ret = drv->bdrv_co_readv(bs, sector_num,
   MIN(nb_sectors, max_nb_sectors), qiov);
@@ -2858,7 +2858,7 @@ static int coroutine_fn 
bdrv_co_do_preadv(BlockDriverState *bs,
  }
  
  tracked_request_begin(&req, bs, offset, bytes, false);

-ret = bdrv_aligned_preadv(bs, &req, offset, bytes,
+ret = bdrv_aligned_preadv(bs, &req, offset, bytes, align,


Whereas this one is an alignment given in bytes.

Max


use_local_qiov ? &local_qiov : qiov,
flags);
  tracked_request_end(&req);

Re: [Qemu-devel] [PATCHv2 05/18] qemu-iotests: fix tests 014 and 023 to work with any protocol

[Peter Lieven]

Am 10.01.2014 20:04, schrieb Kevin Wolf:
> Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
>> On 06.01.2014 06:40, Fam Zheng wrote:
>>> On 2014年01月06日 01:21, Peter Lieven wrote:
 Signed-off-by: Peter Lieven 
 ---
  tests/qemu-iotests/014|4 ++--
  tests/qemu-iotests/014.out|2 +-
  tests/qemu-iotests/023|   11 +--
  tests/qemu-iotests/023.out|   16 
  tests/qemu-iotests/common.pattern |7 +++
  5 files changed, 19 insertions(+), 21 deletions(-)

 diff --git a/tests/qemu-iotests/014 b/tests/qemu-iotests/014
 index b23c2db..01fb614 100755
 --- a/tests/qemu-iotests/014
 +++ b/tests/qemu-iotests/014
 @@ -43,14 +43,14 @@ trap "_cleanup; exit \$status" 0 1 2 3 15

  # much of this could be generic for any format supporting snapshots
  _supported_fmt qcow2
 -_supported_proto file
 +_supported_proto generic
  _supported_os Linux

  TEST_OFFSETS="0 4294967296"
  TEST_OPS="writev read write readv"
  CLUSTER_SIZE=4096

 -_make_test_img 6G
 +TEST_IMG=$TEST_IMG.orig _make_test_img 6G

  echo "Testing empty image:"
  for offset in $TEST_OFFSETS; do
 diff --git a/tests/qemu-iotests/014.out b/tests/qemu-iotests/014.out
 index 4744b4b..6459af0 100644
 --- a/tests/qemu-iotests/014.out
 +++ b/tests/qemu-iotests/014.out
 @@ -1,5 +1,5 @@
  QA output created by 014
 -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=6442450944
 +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=6442450944
  Testing empty image:
  test2: With offset 0
  === Clusters to be compressed [1]
 diff --git a/tests/qemu-iotests/023 b/tests/qemu-iotests/023
 index 9ad06b9..2357696 100755
 --- a/tests/qemu-iotests/023
 +++ b/tests/qemu-iotests/023
 @@ -41,7 +41,7 @@ trap "_cleanup; exit \$status" 0 1 2 3 15

  # much of this could be generic for any format supporting compression.
  _supported_fmt qcow qcow2
 -_supported_proto file
 +_supported_proto generic
  _supported_os Linux

  TEST_OFFSETS="0 4294967296"
 @@ -55,7 +55,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
  echo "Creating new image; cluster size: $CLUSTER_SIZE"
  echo

 -_make_test_img 8G
 +TEST_IMG=$TEST_IMG.orig _make_test_img 8G

  echo "Testing empty image"
  echo
 @@ -63,15 +63,14 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
  for offset in $TEST_OFFSETS; do
  echo "At offset $offset:"
  for op in $TEST_OPS; do
 -io_test $op $offset $CLUSTER_SIZE 3
 +TEST_IMG=$TEST_IMG.orig io_test $op $offset $CLUSTER_SIZE 3
  done
 -_check_test_img
 +TEST_IMG=$TEST_IMG.orig _check_test_img
  done

  echo "Compressing image"
  echo

 -mv "$TEST_IMG" "$TEST_IMG.orig"
  $QEMU_IMG convert -f $IMGFMT -O $IMGFMT -c "$TEST_IMG.orig" 
 "$TEST_IMG"

  echo "Testing compressed image"
 @@ -101,7 +100,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
  echo "Creating another new image"
  echo

 -_make_test_img 8G
 +TEST_IMG=$TEST_IMG.orig _make_test_img 8G

  echo "More complex patterns"
  echo
 diff --git a/tests/qemu-iotests/023.out b/tests/qemu-iotests/023.out
 index ec32341..b80836d 100644
 --- a/tests/qemu-iotests/023.out
 +++ b/tests/qemu-iotests/023.out
 @@ -1,7 +1,7 @@
  QA output created by 023
  Creating new image; cluster size: 1024

 -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
 +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
  Testing empty image

  At offset 0:
 @@ -5664,7 +5664,7 @@ read 3072/3072 bytes at offset 4295491072
  No errors were found on the image.
  Creating another new image

 -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
 +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
  More complex patterns

  test2: With offset 0
 @@ -5887,7 +5887,7 @@ read 2048/2048 bytes at offset 4295001088
  No errors were found on the image.
  Creating new image; cluster size: 4096

 -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
 +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
  Testing empty image

  At offset 0:
 @@ -12270,7 +12270,7 @@ read 12288/12288 bytes at offset 4301256704
  No errors were found on the image.
  Creating another new image

 -Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
 +Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
  More complex patterns

  test2: With offset 0
 @@ -12493,7 +12493,7 @@ read 8192/8192 bytes at offset 4295102464
  No

Re: [Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton for SIMD data processing insns

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
>  static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
>  {
>  /* Note that this is called with all non-FP cases from
>   * table C3-6 so it must UNDEF for entries not specifically
>   * allocated to instructions in that table.
>   */
> -unsupported_encoding(s, insn);
> +AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
> +if (fn) {
> +(fn) (s, insn);

Oh, do you want to CheckFPAdvSIMDEnabled64 here before calling fn?
Otherwise that's the first thing I noticed missing from patch 4.


r~

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Peter Feiner]

On Fri, Jan 10, 2014 at 1:26 PM, Kevin Wolf  wrote:
> Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
>> On 10.01.2014 18:55, Kevin Wolf wrote:
>> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
>> >there?
>>
>> Yes, feel free to.
>
> Thanks, applied to the block branch.
>
> Peter, no need for a second version of the patch then. :-)

I'll still submit v2 to add braces and incorporate the examples in
tests/qemu-iotests.

Re: [Qemu-devel] [PATCHv2 05/18] qemu-iotests: fix tests 014 and 023 to work with any protocol

[Kevin Wolf]

Am 06.01.2014 um 07:49 hat Peter Lieven geschrieben:
> On 06.01.2014 06:40, Fam Zheng wrote:
> >On 2014年01月06日 01:21, Peter Lieven wrote:
> >>Signed-off-by: Peter Lieven 
> >>---
> >>  tests/qemu-iotests/014|4 ++--
> >>  tests/qemu-iotests/014.out|2 +-
> >>  tests/qemu-iotests/023|   11 +--
> >>  tests/qemu-iotests/023.out|   16 
> >>  tests/qemu-iotests/common.pattern |7 +++
> >>  5 files changed, 19 insertions(+), 21 deletions(-)
> >>
> >>diff --git a/tests/qemu-iotests/014 b/tests/qemu-iotests/014
> >>index b23c2db..01fb614 100755
> >>--- a/tests/qemu-iotests/014
> >>+++ b/tests/qemu-iotests/014
> >>@@ -43,14 +43,14 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
> >>
> >>  # much of this could be generic for any format supporting snapshots
> >>  _supported_fmt qcow2
> >>-_supported_proto file
> >>+_supported_proto generic
> >>  _supported_os Linux
> >>
> >>  TEST_OFFSETS="0 4294967296"
> >>  TEST_OPS="writev read write readv"
> >>  CLUSTER_SIZE=4096
> >>
> >>-_make_test_img 6G
> >>+TEST_IMG=$TEST_IMG.orig _make_test_img 6G
> >>
> >>  echo "Testing empty image:"
> >>  for offset in $TEST_OFFSETS; do
> >>diff --git a/tests/qemu-iotests/014.out b/tests/qemu-iotests/014.out
> >>index 4744b4b..6459af0 100644
> >>--- a/tests/qemu-iotests/014.out
> >>+++ b/tests/qemu-iotests/014.out
> >>@@ -1,5 +1,5 @@
> >>  QA output created by 014
> >>-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=6442450944
> >>+Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=6442450944
> >>  Testing empty image:
> >>  test2: With offset 0
> >>  === Clusters to be compressed [1]
> >>diff --git a/tests/qemu-iotests/023 b/tests/qemu-iotests/023
> >>index 9ad06b9..2357696 100755
> >>--- a/tests/qemu-iotests/023
> >>+++ b/tests/qemu-iotests/023
> >>@@ -41,7 +41,7 @@ trap "_cleanup; exit \$status" 0 1 2 3 15
> >>
> >>  # much of this could be generic for any format supporting compression.
> >>  _supported_fmt qcow qcow2
> >>-_supported_proto file
> >>+_supported_proto generic
> >>  _supported_os Linux
> >>
> >>  TEST_OFFSETS="0 4294967296"
> >>@@ -55,7 +55,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
> >>  echo "Creating new image; cluster size: $CLUSTER_SIZE"
> >>  echo
> >>
> >>-_make_test_img 8G
> >>+TEST_IMG=$TEST_IMG.orig _make_test_img 8G
> >>
> >>  echo "Testing empty image"
> >>  echo
> >>@@ -63,15 +63,14 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
> >>  for offset in $TEST_OFFSETS; do
> >>  echo "At offset $offset:"
> >>  for op in $TEST_OPS; do
> >>-io_test $op $offset $CLUSTER_SIZE 3
> >>+TEST_IMG=$TEST_IMG.orig io_test $op $offset $CLUSTER_SIZE 3
> >>  done
> >>-_check_test_img
> >>+TEST_IMG=$TEST_IMG.orig _check_test_img
> >>  done
> >>
> >>  echo "Compressing image"
> >>  echo
> >>
> >>-mv "$TEST_IMG" "$TEST_IMG.orig"
> >>  $QEMU_IMG convert -f $IMGFMT -O $IMGFMT -c "$TEST_IMG.orig" 
> >> "$TEST_IMG"
> >>
> >>  echo "Testing compressed image"
> >>@@ -101,7 +100,7 @@ for CLUSTER_SIZE in $CLUSTER_SIZES; do
> >>  echo "Creating another new image"
> >>  echo
> >>
> >>-_make_test_img 8G
> >>+TEST_IMG=$TEST_IMG.orig _make_test_img 8G
> >>
> >>  echo "More complex patterns"
> >>  echo
> >>diff --git a/tests/qemu-iotests/023.out b/tests/qemu-iotests/023.out
> >>index ec32341..b80836d 100644
> >>--- a/tests/qemu-iotests/023.out
> >>+++ b/tests/qemu-iotests/023.out
> >>@@ -1,7 +1,7 @@
> >>  QA output created by 023
> >>  Creating new image; cluster size: 1024
> >>
> >>-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
> >>+Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
> >>  Testing empty image
> >>
> >>  At offset 0:
> >>@@ -5664,7 +5664,7 @@ read 3072/3072 bytes at offset 4295491072
> >>  No errors were found on the image.
> >>  Creating another new image
> >>
> >>-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
> >>+Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
> >>  More complex patterns
> >>
> >>  test2: With offset 0
> >>@@ -5887,7 +5887,7 @@ read 2048/2048 bytes at offset 4295001088
> >>  No errors were found on the image.
> >>  Creating new image; cluster size: 4096
> >>
> >>-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
> >>+Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
> >>  Testing empty image
> >>
> >>  At offset 0:
> >>@@ -12270,7 +12270,7 @@ read 12288/12288 bytes at offset 4301256704
> >>  No errors were found on the image.
> >>  Creating another new image
> >>
> >>-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=8589934592
> >>+Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=8589934592
> >>  More complex patterns
> >>
> >>  test2: With offset 0
> >>@@ -12493,7 +12493,7 @@ read 8192/8192 bytes at offset 4295102464
> >>  No errors were found on the image.
> >>  Creating new image; cluster size: 16384
> >>
> >>-Formatting

Re: [Qemu-devel] [PATCH] gtk: Support keyboard translation for hosts running Windows

[Stefan Weil]

Am 18.12.2013 19:14, schrieb Stefan Weil:
> Am 07.12.2013 16:25, schrieb Stefan Weil:
>> GTK uses different hardware keycodes on Windows hosts, so some special
>> handling is needed to get the QEMU keycode.
>>
>> Signed-off-by: Stefan Weil 
>> ---
>>  ui/gtk.c |   18 +++---
>>  1 file changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/ui/gtk.c b/ui/gtk.c
>> index 6316f5b..a633d89 100644
>> --- a/ui/gtk.c
>> +++ b/ui/gtk.c
>> @@ -34,6 +34,10 @@
>>  #define GETTEXT_PACKAGE "qemu"
>>  #define LOCALEDIR "po"
>>  
>> +#ifdef _WIN32
>> +# define _WIN32_WINNT 0x0601 /* needed to get definition of MAPVK_VK_TO_VSC 
>> */
>> +#endif
>> +
>>  #include "qemu-common.h"
>>  
>>  #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
>> @@ -704,11 +708,18 @@ static gboolean gd_button_event(GtkWidget *widget, 
>> GdkEventButton *button,
>>  static gboolean gd_key_event(GtkWidget *widget, GdkEventKey *key, void 
>> *opaque)
>>  {
>>  GtkDisplayState *s = opaque;
>> -int gdk_keycode;
>> -int qemu_keycode;
>> +int gdk_keycode = key->hardware_keycode;
>>  int i;
>>  
>> -gdk_keycode = key->hardware_keycode;
>> +#ifdef _WIN32
>> +UINT qemu_keycode = MapVirtualKey(gdk_keycode, MAPVK_VK_TO_VSC);
>> +switch (qemu_keycode) {
>> +case 103:   /* alt gr */
>> +qemu_keycode = 56 | SCANCODE_GREY;
>> +break;
>> +}
>> +#else
>> +int qemu_keycode;
>>  
>>  if (gdk_keycode < 9) {
>>  qemu_keycode = 0;
>> @@ -723,6 +734,7 @@ static gboolean gd_key_event(GtkWidget *widget, 
>> GdkEventKey *key, void *opaque)
>>  } else {
>>  qemu_keycode = 0;
>>  }
>> +#endif
>>  
>>  trace_gd_key_event(gdk_keycode, qemu_keycode,
>> (key->type == GDK_KEY_PRESS) ? "down" : "up");
> 
> Ping? Should I send a MinGW pull request for this patch?
> 


Ping^2? I tried to answer Andreas' questions. Are there any more?

Stefan

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Richard Henderson]

On 01/10/2014 10:37 AM, Peter Maydell wrote:
> On 10 January 2014 18:28, Richard Henderson  wrote:
>> On 01/10/2014 10:18 AM, Peter Maydell wrote:
> Maybe better to hoist load of
> tcg_rn to before initial assignment of tcg_addr?
>>> Not sure what you have in mind here. Pulling the
>>> cpu_reg_sp() call out one level like:
>>>
>>> if (is_postidx) {
>>> int rm = extract32(insn, 16, 5);
>>> TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>>> if (rm == 31) {
>>> tcg_gen_mov_i64(tcg_rn, tcg_addr);
>>> } else {
>>> tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
>>> }
>>> }
>>>
>>> seems like a good idea though.
>>
>> I was thinking
>>
>>   TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>>   TCGv_i64 tcg_addr = tcg_temp_new_i64();
>>   tcg_gen_mov_i64(tcg_addr, tcg_rn);
>>
>> up above.  But even as you have there is good.
> 
> Oh, right. Yes, I like that -- have made the change.

Don't forget the free, of course.  Or use new_tmp_a64.


r~

[Qemu-devel] [Bug 1267955] [NEW] [i386] Parity Flag Not Set On xor %eax, %eax

[Chris P]

Public bug reported:

Tested against qemu-1.7.0 as well as qemu-1.7.50 on Debian Sid

Steps To Reproduce

$ cat > prog.hex << EOF

7f 45 4c 46 01 01 01 00  00 00 00 00 00 00 00 00
02 00 03 00 01 00 00 00  54 80 04 08 34 00 00 00
00 00 00 00 00 00 00 00  34 00 20 00 01 00 28 00
00 00 00 00 01 00 00 00  00 00 00 00 00 80 04 08
00 80 04 08 76 00 00 00  76 00 00 00 05 00 00 00
00 10 00 00

31 c0
9c

b8 04 00 00 00
bb 01 00 00 00
89 e1
ba 04 00 00 00
cd 80

b8 01 00 00 00
bb 00 00 00 00
cd 80

EOF

$ xxd -p -r prog.hex > prog
$ chmod 700 prog

$ ./prog | hexdump -vC
  46 02 00 00   |F...|
0004

$ qemu-i386 ./prog | hexdump -vC
  42 02 00 00   |B...|
0004

On the other hand if [xor %eax, %eax] (31 c0) is replaced with sub
%eax,%eax (29 c0), then the parity flag is set correctly.

** Affects: qemu
 Importance: Undecided
 Status: New


** Tags: eflags i386 parity

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1267955

Title:
  [i386] Parity Flag Not Set On xor %eax,%eax

Status in QEMU:
  New

Bug description:
  Tested against qemu-1.7.0 as well as qemu-1.7.50 on Debian Sid

  Steps To Reproduce

  $ cat > prog.hex << EOF

  7f 45 4c 46 01 01 01 00  00 00 00 00 00 00 00 00
  02 00 03 00 01 00 00 00  54 80 04 08 34 00 00 00
  00 00 00 00 00 00 00 00  34 00 20 00 01 00 28 00
  00 00 00 00 01 00 00 00  00 00 00 00 00 80 04 08
  00 80 04 08 76 00 00 00  76 00 00 00 05 00 00 00
  00 10 00 00

  31 c0
  9c

  b8 04 00 00 00
  bb 01 00 00 00
  89 e1
  ba 04 00 00 00
  cd 80

  b8 01 00 00 00
  bb 00 00 00 00
  cd 80

  EOF

  $ xxd -p -r prog.hex > prog
  $ chmod 700 prog

  $ ./prog | hexdump -vC
    46 02 00 00   |F...|
  0004

  $ qemu-i386 ./prog | hexdump -vC
    42 02 00 00   |B...|
  0004

  On the other hand if [xor %eax, %eax] (31 c0) is replaced with sub
  %eax,%eax (29 c0), then the parity flag is set correctly.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1267955/+subscriptions

Re: [Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton for SIMD data processing insns

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +static inline AArch64DecodeFn *lookup_disas_fn(AArch64DecodeTable *table,
> +   uint32_t insn)

Better make table const.

> +static AArch64DecodeTable data_proc_simd[] = {

So that you can make this const.

> +/* C3.6.1 EXT
> + *   31  30 29 24 23 22  21 20  16 15  14  11 10  95 40
> + * +---+---+-+-+---+--+---+--+---+--+--+
> + * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | imm4 | 0 |  Rn  |  Rd  |
> + * +---+---+-+-+---+--+---+--+---+--+--+
> + */

Error...1

> +/* C3.6.16 AdvSIMD three same
> + *  31 30  29 28   24 23  22  21 20  16 1511  10 95 40
> + * +-+---+---+--+---+--++---+--+--+
> + * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
> + * +-+---+---+--+---+--++---+--+--+
> + */

Error.  Cut and paste?

> +/* pattern  ,  mask ,  fn*/
> +{ 0x0e200400, 0x9f200400, disas_simd_three_reg_same },   ok
> +{ 0x0e20, 0x9f200c00, disas_simd_three_reg_diff },   ok
> +{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, ok
> +{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, ok
> +{ 0x0e000400, 0x9fe08400, disas_simd_copy }, ok
> +{ 0x0f00, 0x9f000400, disas_simd_indexed_vector },   ok
> +/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it 
> */
> +{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm },  ok
> +{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },ok
> +{ 0x0e00, 0xbf208c00, disas_simd_tb },   ok
> +{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },  ok
> +{ 0x2e00, 0xbf208400, disas_simd_ext },  ok
> +{ 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },ok
> +{ 0x5e20, 0xdf200c00, disas_simd_scalar_three_reg_diff },ok
> +{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },  ok
> +{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },  ok
> +{ 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },  ok
> +{ 0x5f00, 0xdf000400, disas_simd_scalar_indexed },   ok
> +{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, ok
> +{ 0x4e280800, 0xff3e0c00, disas_crypto_aes },ok
> +{ 0x5e00, 0xff208c00, disas_crypto_three_reg_sha },  ok
> +{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },ok
> +{ 0x, 0x, NULL }

The errors in the comments above are not present in this table.  I've verified
the pattern and mask entries, but not the ordering requirements.

> +(fn) (s, insn);

Surely coding style sez

fn(s, insn);
or
(*fn)(s, insn);

Otherwise,

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Kevin Wolf]

Am 10.01.2014 um 19:38 hat Max Reitz geschrieben:
> On 10.01.2014 19:26, Kevin Wolf wrote:
> >Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> >>On 10.01.2014 18:55, Kevin Wolf wrote:
> >>>Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >>>there?
> >>Yes, feel free to.
> >Thanks, applied to the block branch.
> >
> >Peter, no need for a second version of the patch then. :-)
> >
> >>>In the long run, we need to get rid of all this copying anyway. I'm
> >>>imagining a BlockDriver function that returns a file name to reproduce
> >>>the same setup, and a removal of bs->backing_file and bs->file_name.
> >>>
> >>>For some drivers, the returned filename would be a URL or some other
> >>>string that that particular driver can parse.
> >>>
> >>>While doing that, we might also consider a fake protocol that handles
> >>>filenames like 'json:{"driver":"qcow2","lazy-refcounts":"on",...}',
> >>>because for some drivers this might be the only thing that comes close
> >>>to a filename as it is a single string at least...
> >>Urgh. *g*
> >>
> >>I'm not sure if we should force every BDS to have a clearly defining
> >>file name. If there are options, which completely change the
> >>behavior of the block driver (I wouldn't consider lazy-refcounts one
> >>of them since it doesn't change the contents of the block device),
> >>I'd rather return NULL when asked for a file name. But then again,
> >>maybe an ugly filename is better than none at all…
> >We need filenames for backing file relationships. For example, when you
> >take a live snapshot, we need to reference the old image. If you don't
> >use the filename, but driver-specific options, I believe this fails
> >today.
> >
> >You might also want to set some options for the backing file in images
> >created with qemu-img.
> 
> Yes, I hoped we could use the options instead. But if it fails…
> Maybe it's worth fixing, I don't know. ;-)

You just need to make them storable in images, qcow2 at least.

The way in which I think live snapshots fail today (untested) is that
the VM continues to run happily on the new overlay image, but you can't
restart the VM because the backing file link in the image file is
missing. That's a nasty way of failure and should definitely be fixed.

> >The alternative would be to extend qcow2 to have something more complex
> >than a string to describe backing files. However, this would mean that
> >qcow2 is the only possible format for live snapshots.
> 
> Well, the problem would arise only for backing files which can't be
> sufficiently described through a rather simple filename. If there
> are exceptions where we are indeed forced to specify some options,
> qemu would be the only program knowing how to interpret those
> filenames anyway, therefore, there is no point in trying to be
> compatible.

Fair enough. Let's try to cope without a json: protocol if we can.

Kevin

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[Peter Lieven]

Am 10.01.2014 19:24, schrieb Paolo Bonzini:
> Il 10/01/2014 19:07, Peter Lieven ha scritto:
>>
>>
>> Von meinem iPad gesendet
>>
>> Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :
>>
>>> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
 There is a common exception though, for the case where you read past
 the end of file.
 So short reads should normally not happen. Unless QEMU or the guest
 sends a request to libnfs to read past the end of the file.
>>> Yes, this can happen in QEMU and the various drivers are careful to pad
>>> with zeroes.  It could perhaps be moved to block.c, but for now each
>>> driver handles it separately.
>> ok i will add this as well. however, i thought i had seen code for this in 
>> block.c  already?,
> No, it corresponds to this code in block/raw-posix.c:
>
> static int aio_worker(void *arg)
> {
> RawPosixAIOData *aiocb = arg;
> ssize_t ret = 0;
>
> switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) {
> case QEMU_AIO_READ:
> ret = handle_aiocb_rw(aiocb);
> if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->bs->growable) {
> iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret,
>   0, aiocb->aio_nbytes - ret);
>
> ret = aiocb->aio_nbytes;
> }
> if (ret == aiocb->aio_nbytes) {
> ret = 0;
> } else if (ret >= 0 && ret < aiocb->aio_nbytes) {
> ret = -EINVAL;
> }
> break;

I am a little confused... but it seems what I had in mind just fills up full 
sectors?!

if (!(bs->zero_beyond_eof && bs->growable)) {
ret = drv->bdrv_co_readv(bs, sector_num, nb_sectors, qiov);
} else {
/* Read zeros after EOF of growable BDSes */
int64_t len, total_sectors, max_nb_sectors;

len = bdrv_getlength(bs);
if (len < 0) {
ret = len;
goto out;
}

total_sectors = DIV_ROUND_UP(len, BDRV_SECTOR_SIZE);
max_nb_sectors = MAX(0, total_sectors - sector_num);
if (max_nb_sectors > 0) {
ret = drv->bdrv_co_readv(bs, sector_num,
 MIN(nb_sectors, max_nb_sectors), qiov);
} else {
ret = 0;
}

/* Reading beyond end of file is supposed to produce zeroes */
if (ret == 0 && total_sectors < sector_num + nb_sectors) {
uint64_t offset = MAX(0, total_sectors - sector_num);
uint64_t bytes = (sector_num + nb_sectors - offset) *
  BDRV_SECTOR_SIZE;
qemu_iovec_memset(qiov, offset * BDRV_SECTOR_SIZE, 0, bytes);
}
}

Peter



>
> Paolo

Re: [Qemu-devel] QEMU detachable overlays and Union Mounts

[kausik pal]

hi Stefan,

Off course we can develop this feature as open source software.

Not sure whether GSoC would be a good route, because as far as I know GSoC
projects will be completed by coming October.

Please let me know of any other possible way we can work together (i.e.
organizational approach).

Basically myself a System Integrator and have very little knowledge of
coding, but I have worked with different Virtualization technologies and
have always found there are challenges/difficulties which the administrator
faces for their day to day activities.

I believe QEMU/KVM along with oVirt can address these challenges and have
the great potential to become a frontrunner in virtualization/VDI front.

Looking forward for you reply.

Thanks

Kausik







On Fri, Jan 10, 2014 at 3:50 PM, Stefan Hajnoczi  wrote:

>
> On Jan 10, 2014 1:52 PM, "kausik pal"  wrote:
> > If the above mentioned QEMU/KVM overlay feature can be made into
> existence then we can bring out a cost effective VDI management or VM
> management solution that can compete with the commercial vendors.
>
> It's an interesting problem to solve. I suspect others would find
> detachable overlays useful too.
>
> I hope you want to develop this feature as open source software.
>
> It's also in scope for a Google Summer of Code project. In that case a
> student could work on the project for 12 weeks during the summer. More
> requirements and design details need to be fleshed out before it can be
> packaged as a GSoC project idea though.
>
> Let me know if GSoC sounds like a good route to create this feature. Not
> sure if it fits your timeframe.
>

Re: [Qemu-devel] [PULL 00/18] Block patches

[Anthony Liguori]

I'm working through the backlog from the holidays.  I should be
through the full backlog today for PULL requests.

On Fri, Jan 10, 2014 at 10:06 AM, Paolo Bonzini  wrote:
> Il 10/01/2014 18:29, Stefan Weil ha scritto:
>> Ping.
>>
>> QEMU compilation is broken on Debian hosts since several weeks now.
>> These block patches include the fix. I'd appreciate if they could be pulled.
>
> And also all the other pull requests.  Seriously, if it was not for the
> few email messages on the disable TCG thread, I would have been worried
> about Anthony's health...
>
> Paolo
>

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Peter Maydell]

On 10 January 2014 18:28, Richard Henderson  wrote:
> On 01/10/2014 10:18 AM, Peter Maydell wrote:
>>> > Maybe better to hoist load of
>>> > tcg_rn to before initial assignment of tcg_addr?
>> Not sure what you have in mind here. Pulling the
>> cpu_reg_sp() call out one level like:
>>
>> if (is_postidx) {
>> int rm = extract32(insn, 16, 5);
>> TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>> if (rm == 31) {
>> tcg_gen_mov_i64(tcg_rn, tcg_addr);
>> } else {
>> tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
>> }
>> }
>>
>> seems like a good idea though.
>
> I was thinking
>
>   TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
>   TCGv_i64 tcg_addr = tcg_temp_new_i64();
>   tcg_gen_mov_i64(tcg_addr, tcg_rn);
>
> up above.  But even as you have there is good.

Oh, right. Yes, I like that -- have made the change.

thanks
-- PMM

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Kevin Wolf]

Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:
> On 10.01.2014 18:55, Kevin Wolf wrote:
> >Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
> >there?
> 
> Yes, feel free to.

Thanks, applied to the block branch.

Peter, no need for a second version of the patch then. :-)

> >In the long run, we need to get rid of all this copying anyway. I'm
> >imagining a BlockDriver function that returns a file name to reproduce
> >the same setup, and a removal of bs->backing_file and bs->file_name.
> >
> >For some drivers, the returned filename would be a URL or some other
> >string that that particular driver can parse.
> >
> >While doing that, we might also consider a fake protocol that handles
> >filenames like 'json:{"driver":"qcow2","lazy-refcounts":"on",...}',
> >because for some drivers this might be the only thing that comes close
> >to a filename as it is a single string at least...
> 
> Urgh. *g*
> 
> I'm not sure if we should force every BDS to have a clearly defining
> file name. If there are options, which completely change the
> behavior of the block driver (I wouldn't consider lazy-refcounts one
> of them since it doesn't change the contents of the block device),
> I'd rather return NULL when asked for a file name. But then again,
> maybe an ugly filename is better than none at all…

We need filenames for backing file relationships. For example, when you
take a live snapshot, we need to reference the old image. If you don't
use the filename, but driver-specific options, I believe this fails
today.

You might also want to set some options for the backing file in images
created with qemu-img.

The alternative would be to extend qcow2 to have something more complex
than a string to describe backing files. However, this would mean that
qcow2 is the only possible format for live snapshots.

> In general, I'd prefer abandoning filenames* (especially protocol
> filenames) altogether. The set of options with which to recreate the
> same BDS is already available.
> 
> Max
> 
> *Of course, we need filenames for, well, opening files, but I'm
> referring to have an explicit string "filename" in addition to the
> option dicts (nearly) everywhere.

Agreed. The reason why filenames are still passed separately and not
converted to a file.filename QDict entry is the convenience magic that
they enable (at least protocol names) and that file.filename doesn't
have in order to have less special cases with blockdev-add.

So what you'd need to do is to parse the protocol names in the top-level
function bdrv_open() and convert them into the right QDict entries.
Perhaps this is also a better place for the .bdrv_parse_filename()
calls. And then you could call a new bdrv_file_open() that doesn't take
a separate filename argument any more.

Kevin

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Max Reitz]

On 10.01.2014 19:26, Kevin Wolf wrote:

Am 10.01.2014 um 19:05 hat Max Reitz geschrieben:

On 10.01.2014 18:55, Kevin Wolf wrote:

Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
there?

Yes, feel free to.

Thanks, applied to the block branch.

Peter, no need for a second version of the patch then. :-)


In the long run, we need to get rid of all this copying anyway. I'm
imagining a BlockDriver function that returns a file name to reproduce
the same setup, and a removal of bs->backing_file and bs->file_name.

For some drivers, the returned filename would be a URL or some other
string that that particular driver can parse.

While doing that, we might also consider a fake protocol that handles
filenames like 'json:{"driver":"qcow2","lazy-refcounts":"on",...}',
because for some drivers this might be the only thing that comes close
to a filename as it is a single string at least...

Urgh. *g*

I'm not sure if we should force every BDS to have a clearly defining
file name. If there are options, which completely change the
behavior of the block driver (I wouldn't consider lazy-refcounts one
of them since it doesn't change the contents of the block device),
I'd rather return NULL when asked for a file name. But then again,
maybe an ugly filename is better than none at all…

We need filenames for backing file relationships. For example, when you
take a live snapshot, we need to reference the old image. If you don't
use the filename, but driver-specific options, I believe this fails
today.

You might also want to set some options for the backing file in images
created with qemu-img.


Yes, I hoped we could use the options instead. But if it fails… Maybe 
it's worth fixing, I don't know. ;-)



The alternative would be to extend qcow2 to have something more complex
than a string to describe backing files. However, this would mean that
qcow2 is the only possible format for live snapshots.


Well, the problem would arise only for backing files which can't be 
sufficiently described through a rather simple filename. If there are 
exceptions where we are indeed forced to specify some options, qemu 
would be the only program knowing how to interpret those filenames 
anyway, therefore, there is no point in trying to be compatible.


Max




In general, I'd prefer abandoning filenames* (especially protocol
filenames) altogether. The set of options with which to recreate the
same BDS is already available.

Max

*Of course, we need filenames for, well, opening files, but I'm
referring to have an explicit string "filename" in addition to the
option dicts (nearly) everywhere.

Agreed. The reason why filenames are still passed separately and not
converted to a file.filename QDict entry is the convenience magic that
they enable (at least protocol names) and that file.filename doesn't
have in order to have less special cases with blockdev-add.

So what you'd need to do is to parse the protocol names in the top-level
function bdrv_open() and convert them into the right QDict entries.
Perhaps this is also a better place for the .bdrv_parse_filename()
calls. And then you could call a new bdrv_file_open() that doesn't take
a separate filename argument any more.

Kevin

Re: [Qemu-devel] [PATCH v2 14/24] block: Switch BdrvTrackedRequest to byte granularity

[Max Reitz]

On 13.12.2013 14:22, Kevin Wolf wrote:

Signed-off-by: Kevin Wolf 
---
  block.c   | 52 +++
  block/backup.c|  7 ++-
  include/block/block_int.h |  4 ++--
  3 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/block.c b/block.c
index a80db2e..fa888d9 100644
--- a/block.c
+++ b/block.c
@@ -2037,13 +2037,13 @@ static void tracked_request_end(BdrvTrackedRequest *req)
   */
  static void tracked_request_begin(BdrvTrackedRequest *req,
BlockDriverState *bs,
-  int64_t sector_num,
-  int nb_sectors, bool is_write)
+  int64_t offset,
+  unsigned int bytes, bool is_write)
  {
  *req = (BdrvTrackedRequest){
  .bs = bs,
-.sector_num = sector_num,
-.nb_sectors = nb_sectors,
+.offset = offset,
+.bytes = bytes,
  .is_write = is_write,
  .co = qemu_coroutine_self(),
  };
@@ -2074,25 +2074,43 @@ void bdrv_round_to_clusters(BlockDriverState *bs,
  }
  }
  
+static void round_bytes_to_clusters(BlockDriverState *bs,

+int64_t offset, unsigned int bytes,
+int64_t *cluster_offset,
+unsigned int *cluster_bytes)
+{
+BlockDriverInfo bdi;
+
+if (bdrv_get_info(bs, &bdi) < 0 || bdi.cluster_size == 0) {
+*cluster_offset = offset;
+*cluster_bytes = bytes;
+} else {
+*cluster_offset = QEMU_ALIGN_DOWN(offset, bdi.cluster_size);
+*cluster_bytes = QEMU_ALIGN_UP(offset - *cluster_offset + bytes,
+   bdi.cluster_size);
+}
+}
+
  static bool tracked_request_overlaps(BdrvTrackedRequest *req,
- int64_t sector_num, int nb_sectors) {
+ int64_t offset, int bytes)


Shouldn't this be "unsigned int bytes"?

Max


+{
  /*    */
-if (sector_num >= req->sector_num + req->nb_sectors) {
+if (offset >= req->offset + req->bytes) {
  return false;
  }
  /*    */
-if (req->sector_num >= sector_num + nb_sectors) {
+if (req->offset >= offset + bytes) {
  return false;
  }
  return true;
  }
  
  static void coroutine_fn wait_for_overlapping_requests(BlockDriverState *bs,

-int64_t sector_num, int nb_sectors)
+int64_t offset, unsigned int bytes)
  {
  BdrvTrackedRequest *req;
-int64_t cluster_sector_num;
-int cluster_nb_sectors;
+int64_t cluster_offset;
+unsigned int cluster_bytes;
  bool retry;
  
  /* If we touch the same cluster it counts as an overlap.  This guarantees

@@ -2101,14 +2119,12 @@ static void coroutine_fn 
wait_for_overlapping_requests(BlockDriverState *bs,
   * CoR read and write operations are atomic and guest writes cannot
   * interleave between them.
   */
-bdrv_round_to_clusters(bs, sector_num, nb_sectors,
-   &cluster_sector_num, &cluster_nb_sectors);
+round_bytes_to_clusters(bs, offset, bytes, &cluster_offset, 
&cluster_bytes);
  
  do {

  retry = false;
  QLIST_FOREACH(req, &bs->tracked_requests, list) {
-if (tracked_request_overlaps(req, cluster_sector_num,
- cluster_nb_sectors)) {
+if (tracked_request_overlaps(req, cluster_offset, cluster_bytes)) {
  /* Hitting this means there was a reentrant request, for
   * example, a block driver issuing nested requests.  This must
   * never happen since it means deadlock.
@@ -2723,10 +2739,10 @@ static int coroutine_fn 
bdrv_aligned_preadv(BlockDriverState *bs,
  }
  
  if (bs->copy_on_read_in_flight) {

-wait_for_overlapping_requests(bs, sector_num, nb_sectors);
+wait_for_overlapping_requests(bs, offset, bytes);
  }
  
-tracked_request_begin(&req, bs, sector_num, nb_sectors, false);

+tracked_request_begin(&req, bs, offset, bytes, false);
  
  if (flags & BDRV_REQ_COPY_ON_READ) {

  int pnum;
@@ -2974,10 +2990,10 @@ static int coroutine_fn 
bdrv_aligned_pwritev(BlockDriverState *bs,
  assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0);
  
  if (bs->copy_on_read_in_flight) {

-wait_for_overlapping_requests(bs, sector_num, nb_sectors);
+wait_for_overlapping_requests(bs, offset, bytes);
  }
  
-tracked_request_begin(&req, bs, sector_num, nb_sectors, true);

+tracked_request_begin(&req, bs, offset, bytes, true);
  
  ret = notifier_with_return_list_notify(&bs->before_write_notifiers, &req);
  
diff --git a/block/backup.c b/block/backup.c

index 0198514..15a2e55 100644
--- a/block/backup.c
+++ b/block/backup.c
@@ -181,8 +181,13 @@ static int 

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Richard Henderson]

On 01/10/2014 10:18 AM, Peter Maydell wrote:
>> > Maybe better to hoist load of
>> > tcg_rn to before initial assignment of tcg_addr?
> Not sure what you have in mind here. Pulling the
> cpu_reg_sp() call out one level like:
> 
> if (is_postidx) {
> int rm = extract32(insn, 16, 5);
> TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
> if (rm == 31) {
> tcg_gen_mov_i64(tcg_rn, tcg_addr);
> } else {
> tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
> }
> }
> 
> seems like a good idea though.

I was thinking

  TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
  TCGv_i64 tcg_addr = tcg_temp_new_i64();
  tcg_gen_mov_i64(tcg_addr, tcg_rn);

up above.  But even as you have there is good.


r~

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Peter Maydell]

On 10 January 2014 18:05, Richard Henderson  wrote:
> On 01/10/2014 09:12 AM, Peter Maydell wrote:
>> +TCGMemOp memop =  MO_TE + size;
>
> Double space after =.  Multiple occurrences.

Just this one plus its copy-n-paste in do_vec_st, I think.

>> +if (is_postidx) {
>> +int rm = extract32(insn, 16, 5);
>> +if (rm == 31) {
>> +tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
>> +} else {
>> +tcg_gen_add_i64(cpu_reg_sp(s, rn), cpu_reg(s, rn), cpu_reg(s, 
>> rm));
>> +}
>
> Second cpu_reg must be cpu_reg_sp as well.

Yes. Unfortunately the testing tool we're using doesn't
support testing of SP-relative accesses, so this kind
of bug can slip through.

> Maybe better to hoist load of
> tcg_rn to before initial assignment of tcg_addr?

Not sure what you have in mind here. Pulling the
cpu_reg_sp() call out one level like:

if (is_postidx) {
int rm = extract32(insn, 16, 5);
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
if (rm == 31) {
tcg_gen_mov_i64(tcg_rn, tcg_addr);
} else {
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}

seems like a good idea though.

thanks
-- PMM

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[Paolo Bonzini]

Il 10/01/2014 19:07, Peter Lieven ha scritto:
> 
> 
> 
> Von meinem iPad gesendet
> 
> Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :
> 
>> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
>>>
>>> There is a common exception though, for the case where you read past
>>> the end of file.
>>> So short reads should normally not happen. Unless QEMU or the guest
>>> sends a request to libnfs to read past the end of the file.
>>
>> Yes, this can happen in QEMU and the various drivers are careful to pad
>> with zeroes.  It could perhaps be moved to block.c, but for now each
>> driver handles it separately.
> 
> ok i will add this as well. however, i thought i had seen code for this in 
> block.c  already?,

No, it corresponds to this code in block/raw-posix.c:

static int aio_worker(void *arg)
{
RawPosixAIOData *aiocb = arg;
ssize_t ret = 0;

switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) {
case QEMU_AIO_READ:
ret = handle_aiocb_rw(aiocb);
if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->bs->growable) {
iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret,
  0, aiocb->aio_nbytes - ret);

ret = aiocb->aio_nbytes;
}
if (ret == aiocb->aio_nbytes) {
ret = 0;
} else if (ret >= 0 && ret < aiocb->aio_nbytes) {
ret = -EINVAL;
}
break;

Paolo

Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Add SIMD ld/st single

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +tcg_gen_add_i64(cpu_reg_sp(s, rn), cpu_reg(s, rn), cpu_reg(s, 
> rm));

Same cpu_reg_sp bug as patch 1.


r~

Re: [Qemu-devel] [PATCH target-arm v4 2/3] zynq_slcr: Add links to the CPUs

[Peter Maydell]

On 2 January 2014 07:31, Peter Crosthwaite  wrote:
> The SLCR needs to be able to reset the CPUs, so link the CPUs to the
> SLCR.

> @@ -496,10 +500,17 @@ static const MemoryRegionOps slcr_ops = {
>  static int zynq_slcr_init(SysBusDevice *dev)
>  {
>  ZynqSLCRState *s = ZYNQ_SLCR(dev);
> +int i;
>
>  memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 
> 0x1000);
>  sysbus_init_mmio(dev, &s->iomem);
>
> +for (i = 0; i < NUM_CPUS; ++i) {
> +gchar *name = g_strdup_printf("cpu%d", i);
> +object_property_add_link(OBJECT(dev), name, TYPE_CPU,
> + (Object **)&s->cpus[i], NULL);
> +g_free(name);
> +}

This is where we get into the nasty questions of how
we ought to be modelling reset. I don't think that
reset controllers ought to work by having direct links
to a pile of QOM device objects. I'd much rather we tried
to work towards modelling this the way the hardware does,
ie a QOM device has one or more inbound GPIO lines
corresponding to the hardware's reset signals, and the
SoC or board wires those up to the reset controller
appropriately.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 13/24] block: Introduce bdrv_co_do_pwritev()

[Max Reitz]

On 13.12.2013 14:22, Kevin Wolf wrote:

This is going to become the bdrv_co_do_preadv() equivalent for writes.
In this patch, however, just a function taking byte offsets is created,
it doesn't align anything yet.

Signed-off-by: Kevin Wolf 
---
  block.c | 23 +--
  1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/block.c b/block.c
index 385fb8a..a80db2e 100644
--- a/block.c
+++ b/block.c
@@ -3010,8 +3010,8 @@ static int coroutine_fn 
bdrv_aligned_pwritev(BlockDriverState *bs,
  /*
   * Handle a write request in coroutine context
   */
-static int coroutine_fn bdrv_co_do_writev(BlockDriverState *bs,
-int64_t sector_num, int nb_sectors, QEMUIOVector *qiov,
+static int coroutine_fn bdrv_co_do_pwritev(BlockDriverState *bs,
+int64_t offset, unsigned int bytes, QEMUIOVector *qiov,
  BdrvRequestFlags flags)
  {
  int ret;
@@ -3022,21 +3022,32 @@ static int coroutine_fn 
bdrv_co_do_writev(BlockDriverState *bs,
  if (bs->read_only) {
  return -EACCES;
  }
-if (bdrv_check_request(bs, sector_num, nb_sectors)) {
+if (bdrv_check_byte_request(bs, offset, bytes)) {
  return -EIO;
  }
  
  /* throttling disk I/O */

  if (bs->io_limits_enabled) {
-bdrv_io_limits_intercept(bs, nb_sectors, true);
+bdrv_io_limits_intercept(bs, bytes << BDRV_SECTOR_BITS, true);
  }
  
-ret = bdrv_aligned_pwritev(bs, sector_num << BDRV_SECTOR_BITS,

-   nb_sectors << BDRV_SECTOR_BITS, qiov, flags);
+ret = bdrv_aligned_pwritev(bs, offset, bytes, qiov, flags);
  
  return ret;

  }
  
+static int coroutine_fn bdrv_co_do_writev(BlockDriverState *bs,

+int64_t sector_num, int nb_sectors, QEMUIOVector *qiov,
+BdrvRequestFlags flags)
+{
+if (nb_sectors < 0 || nb_sectors > (UINT_MAX >> BDRV_SECTOR_BITS)) {


This should probably be INT_MAX, since nb_sectors is an integer. If 
nb_sectors is between INT_MAX >> BDRV_SECTOR_BITS and UINT_MAX >> 
BDRV_SECTOR_BITS, the result of nb_sectors << BDRV_SECTOR_BITS (which 
will be a signed integer) is undefined. It is obviously then implicitly 
casted to an unsigned integer (which is the type of the parameter 
"bytes") which will probably solve the problem as intended, but it is 
still technically undefined.


Thus, I'd either change this to INT_MAX or cast nb_sectors to an 
unsigned int before shifting it below.


Max


+return -EINVAL;
+}
+
+return bdrv_co_do_pwritev(bs, sector_num << BDRV_SECTOR_BITS,
+  nb_sectors << BDRV_SECTOR_BITS, qiov, flags);
+}
+
  int coroutine_fn bdrv_co_writev(BlockDriverState *bs, int64_t sector_num,
  int nb_sectors, QEMUIOVector *qiov)
  {

Re: [Qemu-devel] [PATCH target-arm v4 1/3] xilinx_zynq: added SMP support:

[Peter Maydell]

On 2 January 2014 07:30, Peter Crosthwaite  wrote:
> Added Linux SMP support for the Xilinx Zynq platform (2x CPUs are
> supported)
>
> Signed-off-by: Peter Crosthwaite 
> ---
> Changed from v3:
> Author reset
> s/zynq_cpus/cpus
> simplified custom secondary bootloader
> Rebased
> Changed from v2:
> macro defined the maximum number of CPUS
> Changed from v1:
> Addressed PMM review
> Shorted secondary bootloop using MVN instruction.
> Used default reset secondary instead of custom one.
> Rebased against QOM cpu developments.
> Few whitespace fixes.
>
>  hw/arm/xilinx_zynq.c | 69 
> 
>  1 file changed, 53 insertions(+), 16 deletions(-)
>
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 17251c7..c09ff36 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -27,6 +27,8 @@
>  #include "hw/ssi.h"
>  #include "qemu/error-report.h"
>
> +#define MAX_CPUS 2
> +
>  #define NUM_SPI_FLASHES 4
>  #define NUM_QSPI_FLASHES 2
>  #define NUM_QSPI_BUSSES 2
> @@ -38,10 +40,37 @@
>
>  #define MPCORE_PERIPHBASE 0xF8F0
>
> +/* Dummy bootreg addr to keep ARM bootloader happy. Very top of OCM */
> +#define SMP_BOOTREG_ADDR 0xfffc

It would probably be nicer to provide your own
reset_secondary hook, and then hw/arm/boot.c won't
ever look at what you set in bootreg_addr.

Looks ok otherwise, though.

thanks
-- PMM

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[Peter Lieven]

Von meinem iPad gesendet

Am 10.01.2014 um 19:05 schrieb "Paolo Bonzini" :

> Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
>> 
>> There is a common exception though, for the case where you read past
>> the end of file.
>> So short reads should normally not happen. Unless QEMU or the guest
>> sends a request to libnfs to read past the end of the file.
> 
> Yes, this can happen in QEMU and the various drivers are careful to pad
> with zeroes.  It could perhaps be moved to block.c, but for now each
> driver handles it separately.

ok i will add this as well. however, i thought i had seen code for this in 
block.c  already?,

> 
> Paolo

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Richard Henderson]

On 01/10/2014 09:12 AM, Peter Maydell wrote:
> +TCGMemOp memop =  MO_TE + size;

Double space after =.  Multiple occurrences.

> +if (is_postidx) {
> +int rm = extract32(insn, 16, 5);
> +if (rm == 31) {
> +tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
> +} else {
> +tcg_gen_add_i64(cpu_reg_sp(s, rn), cpu_reg(s, rn), cpu_reg(s, 
> rm));
> +}

Second cpu_reg must be cpu_reg_sp as well.  Maybe better to hoist load of
tcg_rn to before initial assignment of tcg_addr?


r~

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Max Reitz]

On 10.01.2014 18:55, Kevin Wolf wrote:

Am 10.01.2014 um 18:27 hat Max Reitz geschrieben:

On 09.01.2014 11:59, Kevin Wolf wrote:

[ CCing Max, who was recently active in this area, for another opinion ]

Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:

When a backing file is opened such that (1) a protocol is directly
used as the block driver and (2) the block driver has bdrv_file_open,
bdrv_open_backing_file segfaults. The problem arises because
bdrv_open_common returns without setting bd->backing_hd->file.

To effect (1), you seem to have to use the -F flag in qemu-img. There
are several block drivers that satisfy (2), such as "file" and "nbd".
Here are some concrete examples:

 #!/bin/bash

 echo Test file format
 ./qemu-img create -f file base.file 1m
 ./qemu-img create -f qcow2 -F file -o backing_file=base.file\
 file-overlay.qcow2
 ./qemu-img convert -O raw file-overlay.qcow2 file-convert.raw

 echo Test nbd format
 SOCK=$PWD/nbd.sock
 ./qemu-img create -f raw base.raw 1m
 ./qemu-nbd -t -k $SOCK base.raw &
 trap "kill $!" EXIT
 while ! test -e $SOCK; do sleep 1; done
 ./qemu-img create -f qcow2 -F nbd -o backing_file=nbd:unix:$SOCK\
 nbd-overlay.qcow2
 ./qemu-img convert -O raw nbd-overlay.qcow2 nbd-convert.raw

Without this patch, the two qemu-img convert commands segfault.

This is a regression that was introduced in v1.7 by
dbecebddfa4932d1c83915bcb9b5ba5984eb91be.

Signed-off-by: Peter Feiner 
---
  block.c |5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/block.c b/block.c
index 64e7d22..a4a172d 100644
--- a/block.c
+++ b/block.c
@@ -1016,8 +1016,9 @@ int bdrv_open_backing_file(BlockDriverState *bs, QDict 
*options, Error **errp)
  error_free(local_err);
  return ret;
  }
-pstrcpy(bs->backing_file, sizeof(bs->backing_file),
-bs->backing_hd->file->filename);
+if (bs->backing_hd->file)
+pstrcpy(bs->backing_file, sizeof(bs->backing_file),
+bs->backing_hd->file->filename);
  return 0;
  }

I think if there is no bs->backing_hd->file, we should get the filename

>from bs->backing_hd->filename instead of leaving it empty.

In fact, can we always do that or does bs->backing_hd normally lack the
filename? If so, perhaps that is what we need to fix, so we can always
directly use bs->backing_hd->filename here.

bs->backing_hd->filename would be set by the bdrv_open_common() in
bdrv_open(), the filename is read from file->filename (if file !=
NULL; in this case, that would be bs->backing_hd->file->filename) or
from the configuration option "filename".

The latter configuration option is not used by
bdrv_open_backing_file(), as far as I can see. However,
bs->backing_hd->file->filename is exactly the field the old code
uses, therefore, using bs->backing_hd->filename directly should not
break anything.

However, the patch does something different: If file is NULL, it
leaves bs->backing_file unchanged; whereas using
bs->backing_hd->filename would in this case result in the value of
the "filename" option. I think leaving bs->backing_file unchanged is
probably better, unless it is "" and the "filename" option is set.

If we want bs->backing_hd->filename to always point to a valid
filename, we'd probably have to copy to contents of bs->backing_file
there at some point in time, if it is not valid. But this is exactly
a point in code where bs->backing_file is updated, so there'd be no
gain if we instead updated bs->backing_hd->filename if necessary and
then copied that to bs->backing_file, as long as there is no other
place in the code where bs->backing_hd->filename always has to be a
valid filename.

Thus, I think the patch is okay, but I'd probably prefer "if
(bs->backing_hd->filename[0]) pstrcpy(...,
bs->backing_hd->filename);" - although that should not differ from
the given patch, unless the "filename" option is set for the
backing_hd.

Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
there?


Yes, feel free to.


In the long run, we need to get rid of all this copying anyway. I'm
imagining a BlockDriver function that returns a file name to reproduce
the same setup, and a removal of bs->backing_file and bs->file_name.

For some drivers, the returned filename would be a URL or some other
string that that particular driver can parse.

While doing that, we might also consider a fake protocol that handles
filenames like 'json:{"driver":"qcow2","lazy-refcounts":"on",...}',
because for some drivers this might be the only thing that comes close
to a filename as it is a single string at least...


Urgh. *g*

I'm not sure if we should force every BDS to have a clearly defining 
file name. If there are options, which completely change the behavior of 
the block driver (I wouldn't consider lazy-refcounts one of them since 
it doesn't change the contents of the block device), I'd rather return 
NULL when asked for a file name. But th

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[Paolo Bonzini]

Il 10/01/2014 18:16, ronnie sahlberg ha scritto:
> 
> There is a common exception though, for the case where you read past
> the end of file.
> So short reads should normally not happen. Unless QEMU or the guest
> sends a request to libnfs to read past the end of the file.

Yes, this can happen in QEMU and the various drivers are careful to pad
with zeroes.  It could perhaps be moved to block.c, but for now each
driver handles it separately.

Paolo

Re: [Qemu-devel] [PULL 00/18] Block patches

[Paolo Bonzini]

Il 10/01/2014 18:29, Stefan Weil ha scritto:
> Ping.
> 
> QEMU compilation is broken on Debian hosts since several weeks now.
> These block patches include the fix. I'd appreciate if they could be pulled.

And also all the other pull requests.  Seriously, if it was not for the
few email messages on the disable TCG thread, I would have been worried
about Anthony's health...

Paolo

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Kevin Wolf]

Am 10.01.2014 um 18:27 hat Max Reitz geschrieben:
> On 09.01.2014 11:59, Kevin Wolf wrote:
> >[ CCing Max, who was recently active in this area, for another opinion ]
> >
> >Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:
> >>When a backing file is opened such that (1) a protocol is directly
> >>used as the block driver and (2) the block driver has bdrv_file_open,
> >>bdrv_open_backing_file segfaults. The problem arises because
> >>bdrv_open_common returns without setting bd->backing_hd->file.
> >>
> >>To effect (1), you seem to have to use the -F flag in qemu-img. There
> >>are several block drivers that satisfy (2), such as "file" and "nbd".
> >>Here are some concrete examples:
> >>
> >> #!/bin/bash
> >>
> >> echo Test file format
> >> ./qemu-img create -f file base.file 1m
> >> ./qemu-img create -f qcow2 -F file -o backing_file=base.file\
> >> file-overlay.qcow2
> >> ./qemu-img convert -O raw file-overlay.qcow2 file-convert.raw
> >>
> >> echo Test nbd format
> >> SOCK=$PWD/nbd.sock
> >> ./qemu-img create -f raw base.raw 1m
> >> ./qemu-nbd -t -k $SOCK base.raw &
> >> trap "kill $!" EXIT
> >> while ! test -e $SOCK; do sleep 1; done
> >> ./qemu-img create -f qcow2 -F nbd -o backing_file=nbd:unix:$SOCK\
> >> nbd-overlay.qcow2
> >> ./qemu-img convert -O raw nbd-overlay.qcow2 nbd-convert.raw
> >>
> >>Without this patch, the two qemu-img convert commands segfault.
> >>
> >>This is a regression that was introduced in v1.7 by
> >>dbecebddfa4932d1c83915bcb9b5ba5984eb91be.
> >>
> >>Signed-off-by: Peter Feiner 
> >>---
> >>  block.c |5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >>diff --git a/block.c b/block.c
> >>index 64e7d22..a4a172d 100644
> >>--- a/block.c
> >>+++ b/block.c
> >>@@ -1016,8 +1016,9 @@ int bdrv_open_backing_file(BlockDriverState *bs, 
> >>QDict *options, Error **errp)
> >>  error_free(local_err);
> >>  return ret;
> >>  }
> >>-pstrcpy(bs->backing_file, sizeof(bs->backing_file),
> >>-bs->backing_hd->file->filename);
> >>+if (bs->backing_hd->file)
> >>+pstrcpy(bs->backing_file, sizeof(bs->backing_file),
> >>+bs->backing_hd->file->filename);
> >>  return 0;
> >>  }
> >I think if there is no bs->backing_hd->file, we should get the filename
> >from bs->backing_hd->filename instead of leaving it empty.
> >
> >In fact, can we always do that or does bs->backing_hd normally lack the
> >filename? If so, perhaps that is what we need to fix, so we can always
> >directly use bs->backing_hd->filename here.
> 
> bs->backing_hd->filename would be set by the bdrv_open_common() in
> bdrv_open(), the filename is read from file->filename (if file !=
> NULL; in this case, that would be bs->backing_hd->file->filename) or
> from the configuration option "filename".
> 
> The latter configuration option is not used by
> bdrv_open_backing_file(), as far as I can see. However,
> bs->backing_hd->file->filename is exactly the field the old code
> uses, therefore, using bs->backing_hd->filename directly should not
> break anything.
> 
> However, the patch does something different: If file is NULL, it
> leaves bs->backing_file unchanged; whereas using
> bs->backing_hd->filename would in this case result in the value of
> the "filename" option. I think leaving bs->backing_file unchanged is
> probably better, unless it is "" and the "filename" option is set.
> 
> If we want bs->backing_hd->filename to always point to a valid
> filename, we'd probably have to copy to contents of bs->backing_file
> there at some point in time, if it is not valid. But this is exactly
> a point in code where bs->backing_file is updated, so there'd be no
> gain if we instead updated bs->backing_hd->filename if necessary and
> then copied that to bs->backing_file, as long as there is no other
> place in the code where bs->backing_hd->filename always has to be a
> valid filename.
> 
> Thus, I think the patch is okay, but I'd probably prefer "if
> (bs->backing_hd->filename[0]) pstrcpy(...,
> bs->backing_hd->filename);" - although that should not differ from
> the given patch, unless the "filename" option is set for the
> backing_hd.

Ok, if you're happy with it, I'll apply it. Can I put your Reviewed-by
there?

In the long run, we need to get rid of all this copying anyway. I'm
imagining a BlockDriver function that returns a file name to reproduce
the same setup, and a removal of bs->backing_file and bs->file_name.

For some drivers, the returned filename would be a URL or some other
string that that particular driver can parse.

While doing that, we might also consider a fake protocol that handles
filenames like 'json:{"driver":"qcow2","lazy-refcounts":"on",...}',
because for some drivers this might be the only thing that comes close
to a filename as it is a single string at least...

Kevin

[Qemu-devel] [PATCH 02/10] target-arm: A64: Add SIMD ld/st single

[Peter Maydell]

Implement the SIMD ld/st single structure instructions.

Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 141 -
 1 file changed, 139 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 4482e73..ee56588 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2084,10 +2084,147 @@ static void disas_ldst_multiple_struct(DisasContext 
*s, uint32_t insn)
 }
 }
 
-/* AdvSIMD load/store single structure */
+/* C3.3.3 AdvSIMD load/store single structure
+ *
+ *  31  30  29   23 22 21 20   16 15 13 12  11  10 95 40
+ * +---+---+---+-+---+-+---+--+--+--+
+ * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size |  Rn  |  Rt  |
+ * +---+---+---+-+---+-+---+--+--+--+
+ *
+ * C3.3.4 AdvSIMD load/store single structure (post-indexed)
+ *
+ *  31  30  29   23 22 21 20   16 15 13 12  11  10 95 40
+ * +---+---+---+-+---+-+---+--+--+--+
+ * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm| opc | S | size |  Rn  |  Rt  |
+ * +---+---+---+-+---+-+---+--+--+--+
+ *
+ * Rt: first (or only) SIMD&FP register to be transferred
+ * Rn: base address or SP
+ * Rm (post-index only): post-index register (when !31) or size dependent #imm
+ * index = encoded in Q:S:size dependent on size
+ *
+ * lane_size = encoded in R, opc
+ * transfer width = encoded in opc, S, size
+ */
 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int rt = extract32(insn, 0, 5);
+int rn = extract32(insn, 5, 5);
+int size = extract32(insn, 10, 2);
+int S = extract32(insn, 12, 1);
+int opc = extract32(insn, 13, 3);
+int R = extract32(insn, 21, 1);
+int is_load = extract32(insn, 22, 1);
+int is_postidx = extract32(insn, 23, 1);
+int is_q = extract32(insn, 30, 1);
+
+int scale = extract32(opc, 1, 2);
+int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
+bool replicate = false;
+int index = is_q << 3 | S << 2 | size;
+int ebytes, xs;
+TCGv_i64 tcg_addr;
+
+switch (scale) {
+case 3:
+if (!is_load || S) {
+unallocated_encoding(s);
+return;
+}
+scale = size;
+replicate = true;
+break;
+case 0:
+break;
+case 1:
+if (extract32(size, 0, 1)) {
+unallocated_encoding(s);
+return;
+}
+index >>= 1;
+break;
+case 2:
+if (extract32(size, 1, 1)) {
+unallocated_encoding(s);
+return;
+}
+if (!extract32(size, 0, 1)) {
+index >>= 2;
+} else {
+if (S) {
+unallocated_encoding(s);
+return;
+}
+index >>= 3;
+scale = 3;
+}
+break;
+default:
+g_assert_not_reached();
+}
+
+ebytes = 1 << scale;
+
+tcg_addr = read_cpu_reg_sp(s, rn, 1);
+
+if (rn == 31) {
+gen_check_sp_alignment(s);
+}
+
+for (xs = 0; xs < selem; xs++) {
+if (replicate) {
+/* Load and replicate to all elements */
+uint64_t mulconst;
+TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+
+tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
+get_mem_index(s), MO_TE + scale);
+switch (scale) {
+case 0:
+mulconst = 0x0101010101010101ULL;
+break;
+case 1:
+mulconst = 0x0001000100010001ULL;
+break;
+case 2:
+mulconst = 0x00010001ULL;
+break;
+case 3:
+mulconst = 0;
+break;
+default:
+g_assert_not_reached();
+}
+if (mulconst) {
+tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
+}
+write_vec_element(s, tcg_tmp, rt, 0, MO_64);
+if (is_q) {
+write_vec_element(s, tcg_tmp, rt, 1, MO_64);
+} else {
+clear_vec_high(s, rt);
+}
+tcg_temp_free_i64(tcg_tmp);
+} else {
+/* Load/store one element per register */
+if (is_load) {
+do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
+} else {
+do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
+}
+}
+tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+rt = (rt + 1) % 32;
+}
+
+if (is_postidx) {
+int rm = extract32(insn, 16, 5);
+if (rm == 31) {
+tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
+} else {
+tcg_gen_add_i64(cpu_reg_sp(s, 

[Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton for SIMD data processing insns

[Peter Maydell]

From: Alex Bennée 

Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.

Signed-off-by: Alex Bennée 
Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 306 -
 1 file changed, 305 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ee56588..fe5ad52 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -61,6 +61,17 @@ enum a64_shift_type {
 A64_SHIFT_TYPE_ROR = 3
 };
 
+/* Table based decoder typedefs - used when the relevant bits for decode
+ * are too awkwardly scattered across the instruction (eg SIMD).
+ */
+typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
+
+typedef struct AArch64DecodeTable {
+uint32_t pattern;
+uint32_t mask;
+AArch64DecodeFn *disas_fn;
+} AArch64DecodeTable;
+
 /* initialize TCG globals.  */
 void a64_translate_init(void)
 {
@@ -846,6 +857,31 @@ static inline void gen_check_sp_alignment(DisasContext *s)
 }
 
 /*
+ * This provides a simple table based table lookup decoder. It is
+ * intended to be used when the relevant bits for decode are too
+ * awkwardly placed and switch/if based logic would be confusing and
+ * deeply nested. Since it's a linear search through the table, tables
+ * should be kept small.
+ *
+ * It returns the first handler where insn & mask == pattern, or
+ * NULL if there is no match.
+ * The table is terminated by an empty mask (i.e. 0)
+ */
+static inline AArch64DecodeFn *lookup_disas_fn(AArch64DecodeTable *table,
+   uint32_t insn)
+{
+AArch64DecodeTable *tptr = table;
+
+while (tptr->mask) {
+if ((insn & tptr->mask) == tptr->pattern) {
+return tptr->disas_fn;
+}
+tptr++;
+}
+return NULL;
+}
+
+/*
  * the instruction disassembly implemented here matches
  * the instruction encoding classifications in chapter 3 (C3)
  * of the ARM Architecture Reference Manual (DDI0487A_a)
@@ -4604,13 +4640,281 @@ static void disas_data_proc_fp(DisasContext *s, 
uint32_t insn)
 }
 }
 
+/* C3.6.1 EXT
+ *   31  30 29 24 23 22  21 20  16 15  14  11 10  95 40
+ * +---+---+-+-+---+--+---+--+---+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | imm4 | 0 |  Rn  |  Rd  |
+ * +---+---+-+-+---+--+---+--+---+--+--+
+ */
+static void disas_simd_ext(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.2 TBL/TBX
+ *   31  30 29 24 23 22  21 20  16 15  14 13  12  11 10 95 40
+ * +---+---+-+-+---+--+---+-++-+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | len | op | 0 0 |  Rn  |  Rd  |
+ * +---+---+-+-+---+--+---+-++-+--+--+
+ */
+static void disas_simd_tb(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.3 ZIP/UZP/TRN
+ *   31  30 29 24 23  22  21 20   16 15 14 12 11 10 95 40
+ * +---+---+-+--+---+--+---+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 | size | 0 |  Rm  | 0 | opc | 1 0 |  Rn  |  Rd  |
+ * +---+---+-+--+---+--+---+--+--+
+ */
+static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.4 AdvSIMD across lanes
+ *   31  30  29 28   24 23  22 21   17 1612 11 10 95 40
+ * +---+---+---+---+--+---++-+--+--+
+ * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
+ * +---+---+---+---+--+---++-+--+--+
+ */
+static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.5 AdvSIMD copy
+ *   31  30  29  28 21 20  16 15  14  11 10  95 40
+ * +---+---++-+--+---+--+---+--+--+
+ * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
+ * +---+---++-+--+---+--+---+--+--+
+ */
+static void disas_simd_copy(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.6 AdvSIMD modified immediate
+ *  31  30   29  28 19 18 16 15   12  11  10  9 5 40
+ * +---+---++-+-+---++---+---+--+
+ * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh |  Rd  |
+ * +---+---++-+-+---++---+---+--+
+ */
+static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
+{
+unsupported_encoding(s, insn);
+}
+
+/* C3.6.7 AdvSIMD s

Re: [Qemu-devel] [PULL 00/18] Block patches

[Stefan Weil]

Am 20.12.2013 16:46, schrieb Stefan Hajnoczi:
> Happy holidays to all!  I'll be back on January 2nd.  Kevin is also away so
> there will be no block pull request next Friday.
> 
> If there is anything urgent, please contact me at stefa...@gmail.com.
> 
> The following changes since commit f8251db121c3f051b22a7536b97d160c30bcccd4:
> 
>   Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into 
> staging (2013-12-19 17:03:17 -0800)
> 
> are available in the git repository at:
> 
> 
>   git://github.com/stefanha/qemu.git block
> 
> for you to fetch changes up to 18da7f94cdce130f2a71387de4980ffa817181a1:
> 
>   commit: Remove unused check (2013-12-20 16:26:16 +0100)
> 
> 
> Fam Zheng (8):
>   vmdk: Check VMFS extent line field number
>   vmdk: Allow vmdk_create to work with protocol
>   mirror: Don't close target
>   mirror: Move base to MirrorBlockJob
>   block: Add commit_active_start()
>   commit: Support commit active layer
>   qemu-iotests: Update test cases for commit active
>   commit: Remove unused check
> 
> Jeff Cody (2):
>   block: vhdx - improve error message, and .bdrv_check implementation
>   docs: updated qemu-img man page and qemu-doc to reflect VHDX support.
> 
> Liu Yuan (1):
>   sheepdog: fix dynamic grow for running qcow2 format
> 
> Paolo Bonzini (4):
>   vring: create a common function to parse descriptors
>   vring: factor common code for error exits
>   dataplane: change vring API to use VirtQueueElement
>   dataplane: replace hostmem with memory_region_find
> 
> Stefan Hajnoczi (2):
>   qapi-schema: fix QEMU 1.8 references
>   qemu-iotests: drop duplicate virtio-blk initialization failure
> 
> Stefan Weil (1):
>   block/iscsi: Fix compilation for libiscsi 1.4.0 (API change)


Ping.

QEMU compilation is broken on Debian hosts since several weeks now.
These block patches include the fix. I'd appreciate if they could be pulled.

Thanks,
Stefan W.

[Qemu-devel] [PATCH 04/10] target-arm: A64: Add SIMD EXT

[Peter Maydell]

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 62 +-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index fe5ad52..83ae222 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4640,6 +4640,32 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t 
insn)
 }
 }
 
+static TCGv_i64 do_ext64(DisasContext *s, int leftreg, int leftelt,
+ int rightreg, int rightelt, int pos)
+{
+/* Extract 64 bits from the middle of two concatenated 64 bit
+ * vector register slices left:right. The extracted bits start
+ * at 'pos' bits into the right (least significant) side.
+ * For each slice, 'reg' indicates the vector register and
+ * 'elt' indicates which of the two 64 bit elements of it to use.
+ * The extracted value is returned in a TCGv_i64 temp.
+ */
+TCGv_i64 tcg_res = tcg_temp_new_i64();
+assert(pos >= 0 && pos < 64);
+
+read_vec_element(s, tcg_res, rightreg, rightelt, MO_64);
+if (pos != 0) {
+TCGv_i64 tcg_left = tcg_temp_new_i64();
+
+read_vec_element(s, tcg_left, leftreg, leftelt, MO_64);
+tcg_gen_shli_i64(tcg_left, tcg_left, 64 - pos);
+tcg_gen_shri_i64(tcg_res, tcg_res, pos);
+tcg_gen_or_i64(tcg_res, tcg_res, tcg_left);
+tcg_temp_free_i64(tcg_left);
+}
+return tcg_res;
+}
+
 /* C3.6.1 EXT
  *   31  30 29 24 23 22  21 20  16 15  14  11 10  95 40
  * +---+---+-+-+---+--+---+--+---+--+--+
@@ -4648,7 +4674,41 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t 
insn)
  */
 static void disas_simd_ext(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int is_q = extract32(insn, 30, 1);
+int op2 = extract32(insn, 22, 2);
+int imm4 = extract32(insn, 11, 4);
+int rm = extract32(insn, 16, 5);
+int rn = extract32(insn, 5, 5);
+int rd = extract32(insn, 0, 5);
+int pos = imm4 << 3;
+TCGv_i64 tcg_resl, tcg_resh;
+
+if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
+unallocated_encoding(s);
+return;
+}
+
+/* Vd gets bits starting at pos bits into Vm:Vn. This is
+ * either extracting 128 bits from a 128:128 concatenation, or
+ * extracting 64 bits from a 64:64 concatenation.
+ */
+if (!is_q) {
+tcg_resl = do_ext64(s, rm, 0, rn, 0, pos);
+tcg_resh = tcg_const_i64(0);
+} else {
+if (pos < 64) {
+tcg_resl = do_ext64(s, rn, 1, rn, 0, pos);
+tcg_resh = do_ext64(s, rm, 0, rn, 1, pos);
+} else {
+tcg_resl = do_ext64(s, rm, 0, rn, 1, pos - 64);
+tcg_resh = do_ext64(s, rm, 1, rm, 0, pos - 64);
+}
+}
+
+write_vec_element(s, tcg_resl, rd, 0, MO_64);
+tcg_temp_free_i64(tcg_resl);
+write_vec_element(s, tcg_resh, rd, 1, MO_64);
+tcg_temp_free_i64(tcg_resh);
 }
 
 /* C3.6.2 TBL/TBX
-- 
1.8.5

[Qemu-devel] [PATCH 05/10] target-arm: A64: Add SIMD TBL/TBLX

[Peter Maydell]

From: Michael Matz 

Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz 
[PMM: rewritten to do more of the decode in translate-a64.c,
 and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell 
---
 target-arm/helper-a64.c| 31 ++
 target-arm/helper-a64.h|  1 +
 target-arm/translate-a64.c | 54 +-
 3 files changed, 85 insertions(+), 1 deletion(-)

diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 4ce0d01..810e7c5 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -122,3 +122,34 @@ uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void 
*fp_status)
 {
 return float_rel_to_flags(float64_compare(x, y, fp_status));
 }
+
+uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
+  uint64_t rn, uint64_t numregs)
+{
+/* Helper function for SIMD TBL and TBX. We have to do the table
+ * lookup part for the 64 bits worth of indices we're passed in.
+ * result is the initial results vector (either zeroes for TBL
+ * or some guest values for TBX), rn the register number where
+ * the table starts, and numregs the number of registers in the table.
+ * We return the results of the lookups.
+ */
+int shift;
+
+for (shift = 0; shift < 64; shift += 8) {
+int index = extract64(indices, shift, 8);
+if (index < 16 * numregs) {
+/* Convert index (a byte offset into the virtual table
+ * which is a series of 128-bit vectors concatenated)
+ * into the correct vfp.regs[] element plus a bit offset
+ * into that element, bearing in mind that the table
+ * can wrap around from V31 to V0.
+ */
+int elt = (rn * 2 + (index >> 3)) % 64;
+int bitidx = (index & 7) * 8;
+uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
+
+result = deposit64(result, shift, 8, val);
+}
+}
+return result;
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index bca19f3..0d265d5 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -26,3 +26,4 @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
 DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
 DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
 DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
+DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i64, i64)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 83ae222..336e544 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4719,7 +4719,59 @@ static void disas_simd_ext(DisasContext *s, uint32_t 
insn)
  */
 static void disas_simd_tb(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int op2 = extract32(insn, 22, 2);
+int is_q = extract32(insn, 30, 1);
+int rm = extract32(insn, 16, 5);
+int rn = extract32(insn, 5, 5);
+int rd = extract32(insn, 0, 5);
+int is_tblx = extract32(insn, 12, 1);
+int len = extract32(insn, 13, 2);
+TCGv_i64 tcg_resl, tcg_resh, tcg_idx, tcg_regno, tcg_numregs;
+
+if (op2 != 0) {
+unallocated_encoding(s);
+return;
+}
+
+/* This does a table lookup: for every byte element in the input
+ * we index into a table formed from up to four vector registers,
+ * and then the output is the result of the lookups. Our helper
+ * function does the lookup operation for a single 64 bit part of
+ * the input.
+ */
+tcg_resl = tcg_temp_new_i64();
+tcg_resh = tcg_temp_new_i64();
+
+if (is_tblx) {
+read_vec_element(s, tcg_resl, rd, 0, MO_64);
+} else {
+tcg_gen_movi_i64(tcg_resl, 0);
+}
+if (is_tblx && is_q) {
+read_vec_element(s, tcg_resh, rd, 1, MO_64);
+} else {
+tcg_gen_movi_i64(tcg_resh, 0);
+}
+
+tcg_idx = tcg_temp_new_i64();
+tcg_regno = tcg_const_i64(rn);
+tcg_numregs = tcg_const_i64(len + 1);
+read_vec_element(s, tcg_idx, rm, 0, MO_64);
+gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
+tcg_regno, tcg_numregs);
+if (is_q) {
+read_vec_element(s, tcg_idx, rm, 1, MO_64);
+gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
+tcg_regno, tcg_numregs);
+}
+tcg_temp_free_i64(tcg_idx);
+tcg_temp_free_i64(tcg_regno);
+tcg_temp_free_i64(tcg_numregs);
+
+write_vec_element(s, tcg_resl, rd, 0, MO_64);
+tcg_temp_free_i64(tcg_resl);
+write_vec_element(s, tcg_resh, rd, 1, MO_64);
+tcg_temp_free_i64(tcg_resh);
 }
 
 /* C3.6.3 ZIP/UZP/TRN
-- 
1.8.5

[Qemu-devel] [PATCH 09/10] target-arm: A64: Add SIMD modified immediate group

[Peter Maydell]

From: Alex Bennée 

This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf 
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée 
Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 131 -
 1 file changed, 130 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 396782e..153a28a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5269,10 +5269,139 @@ static void disas_simd_copy(DisasContext *s, uint32_t 
insn)
  * +---+---++-+-+---++---+---+--+
  * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh |  Rd  |
  * +---+---++-+-+---++---+---+--+
+ *
+ * There are a number of operations that can be carried out here:
+ *   MOVI - move (shifted) imm into register
+ *   MVNI - move inverted (shifted) imm into register
+ *   ORR  - bitwise OR of (shifted) imm with register
+ *   BIC  - bitwise clear of (shifted) imm with register
  */
 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int rd = extract32(insn, 0, 5);
+int cmode = extract32(insn, 12, 4);
+int cmode_3_1 = extract32(cmode, 1, 3);
+int cmode_0 = extract32(cmode, 0, 1);
+int o2 = extract32(insn, 11, 1);
+uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
+bool is_neg = extract32(insn, 29, 1);
+bool is_q = extract32(insn, 30, 1);
+uint64_t imm = 0;
+TCGv_i64 tcg_rd, tcg_imm;
+int i;
+
+if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
+unallocated_encoding(s);
+return;
+}
+
+/* See AdvSIMDExpandImm() in ARM ARM */
+switch (cmode_3_1) {
+case 0: /* Replicate(Zeros(24):imm8, 2) */
+case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
+case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
+case 3: /* Replicate(imm8:Zeros(24), 2) */
+{
+int shift = cmode_3_1 * 8;
+imm = (abcdefgh << shift) | (abcdefgh << (32 + shift));
+break;
+}
+case 4: /* Replicate(Zeros(8):imm8, 4) */
+case 5: /* Replicate(imm8:Zeros(8), 4) */
+{
+int shift = (cmode_3_1 & 0x1) * 8;
+imm = (abcdefgh << shift) |
+  (abcdefgh << (16 + shift)) |
+  (abcdefgh << (32 + shift)) |
+  (abcdefgh << (48 + shift));
+break;
+}
+case 6:
+if (cmode_0) {
+/* Replicate(Zeros(8):imm8:Ones(16), 2) */
+imm = (abcdefgh << 16) | 0x;
+imm |= (imm << 32);
+} else {
+/* Replicate(Zeros(16):imm8:Ones(8), 2) */
+imm = (abcdefgh << 8) | 0xff;
+imm |= (imm << 32);
+}
+break;
+case 7:
+if (!cmode_0 && !is_neg) {
+imm = abcdefgh |
+  (abcdefgh << 8) |
+  (abcdefgh << 16) |
+  (abcdefgh << 24) |
+  (abcdefgh << 32) |
+  (abcdefgh << 40) |
+  (abcdefgh << 48) |
+  (abcdefgh << 56);
+} else if (!cmode_0 && is_neg) {
+int i;
+imm = 0;
+for (i = 0; i < 8; i++) {
+if ((abcdefgh) & (1 << i)) {
+imm |= 0xffULL << (i * 8);
+}
+}
+} else if (cmode_0) {
+if (is_neg) {
+imm = (abcdefgh & 0x3f) << 48;
+if (abcdefgh & 0x80) {
+imm |= 0x8000ULL;
+}
+if (abcdefgh & 0x40) {
+imm |= 0x3fc0ULL;
+} else {
+imm |= 0x4000ULL;
+}
+} else {
+imm = (abcdefgh & 0x3f) << 19;
+if (abcdefgh & 0x80) {
+imm |= 0x8000;
+}
+if (abcdefgh & 0x40) {
+imm |= 0x3e00;
+} else {
+imm |= 0x4000;
+}
+imm |= (imm << 32);
+}
+}
+break;
+}
+
+if (cmode_3_1 != 7 && is_neg) {
+imm = ~imm;
+}
+
+tcg_imm = tcg_const_i64(imm);
+tcg_rd = new_tmp_a64(s);
+
+for (i = 0; i < 2; i++) {
+int foffs = i ? fp_reg_hi_offset(rd) : fp_reg_offset(rd, MO_64);
+
+if (i == 1 && !is_q) {
+/* non-quad ops clear high half of vector */
+tcg_gen_movi_i64(tcg_rd, 0);
+} else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
+tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
+if (is_neg) {
+/* AND (BIC) */
+tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
+ 

[Qemu-devel] [PATCH 00/10] A64 SIMD patchset one: ld/st, C3.6.1..C3.6.7

[Peter Maydell]

This is an initial set of patches which make a start on SIMD (Neon)
emulation in the A64 decoder. The patches implement all the SIMD
load/store operations, provide a decoder skeleton for the SIMD
dp instructions, and implement all the instructions in the ARM ARM's
groupings C3.6.1 through C3.6.7.

(It's more fluke than anything else that I ended up with all the
first seven groupings in this set; they happened to all be easy small
groupings. For some of the larger SIMD instruction groups I expect
that we will end up implementing only some of the instructions
in a group, in order to get more quickly to the useful milestone
of "implement all the instructions gcc happens to emit today".)

thanks
-- PMM

Alex Bennée (4):
  target-arm: A64: Add SIMD ld/st multiple
  target-arm: A64: Add decode skeleton for SIMD data processing insns
  target-arm: A64: Add SIMD copy operations
  target-arm: A64: Add SIMD modified immediate group

Michael Matz (3):
  target-arm: A64: Add SIMD TBL/TBLX
  target-arm: A64: Add SIMD ZIP/UZP/TRN
  target-arm: A64: Add SIMD across-lanes instructions

Peter Maydell (3):
  target-arm: A64: Add SIMD ld/st single
  target-arm: A64: Add SIMD EXT
  target-arm: A64: Add SIMD scalar copy instructions

 target-arm/helper-a64.c|   31 +
 target-arm/helper-a64.h|1 +
 target-arm/translate-a64.c | 1440 +++-
 3 files changed, 1463 insertions(+), 9 deletions(-)

-- 
1.8.5

Re: [Qemu-devel] [PATCH] block: fix backing file segfault

[Max Reitz]

On 09.01.2014 11:59, Kevin Wolf wrote:

[ CCing Max, who was recently active in this area, for another opinion ]

Am 08.01.2014 um 20:43 hat Peter Feiner geschrieben:

When a backing file is opened such that (1) a protocol is directly
used as the block driver and (2) the block driver has bdrv_file_open,
bdrv_open_backing_file segfaults. The problem arises because
bdrv_open_common returns without setting bd->backing_hd->file.

To effect (1), you seem to have to use the -F flag in qemu-img. There
are several block drivers that satisfy (2), such as "file" and "nbd".
Here are some concrete examples:

 #!/bin/bash

 echo Test file format
 ./qemu-img create -f file base.file 1m
 ./qemu-img create -f qcow2 -F file -o backing_file=base.file\
 file-overlay.qcow2
 ./qemu-img convert -O raw file-overlay.qcow2 file-convert.raw

 echo Test nbd format
 SOCK=$PWD/nbd.sock
 ./qemu-img create -f raw base.raw 1m
 ./qemu-nbd -t -k $SOCK base.raw &
 trap "kill $!" EXIT
 while ! test -e $SOCK; do sleep 1; done
 ./qemu-img create -f qcow2 -F nbd -o backing_file=nbd:unix:$SOCK\
 nbd-overlay.qcow2
 ./qemu-img convert -O raw nbd-overlay.qcow2 nbd-convert.raw

Without this patch, the two qemu-img convert commands segfault.

This is a regression that was introduced in v1.7 by
dbecebddfa4932d1c83915bcb9b5ba5984eb91be.

Signed-off-by: Peter Feiner 
---
  block.c |5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/block.c b/block.c
index 64e7d22..a4a172d 100644
--- a/block.c
+++ b/block.c
@@ -1016,8 +1016,9 @@ int bdrv_open_backing_file(BlockDriverState *bs, QDict 
*options, Error **errp)
  error_free(local_err);
  return ret;
  }
-pstrcpy(bs->backing_file, sizeof(bs->backing_file),
-bs->backing_hd->file->filename);
+if (bs->backing_hd->file)
+pstrcpy(bs->backing_file, sizeof(bs->backing_file),
+bs->backing_hd->file->filename);
  return 0;
  }

I think if there is no bs->backing_hd->file, we should get the filename
from bs->backing_hd->filename instead of leaving it empty.

In fact, can we always do that or does bs->backing_hd normally lack the
filename? If so, perhaps that is what we need to fix, so we can always
directly use bs->backing_hd->filename here.


bs->backing_hd->filename would be set by the bdrv_open_common() in 
bdrv_open(), the filename is read from file->filename (if file != NULL; 
in this case, that would be bs->backing_hd->file->filename) or from the 
configuration option "filename".


The latter configuration option is not used by bdrv_open_backing_file(), 
as far as I can see. However, bs->backing_hd->file->filename is exactly 
the field the old code uses, therefore, using bs->backing_hd->filename 
directly should not break anything.


However, the patch does something different: If file is NULL, it leaves 
bs->backing_file unchanged; whereas using bs->backing_hd->filename would 
in this case result in the value of the "filename" option. I think 
leaving bs->backing_file unchanged is probably better, unless it is "" 
and the "filename" option is set.


If we want bs->backing_hd->filename to always point to a valid filename, 
we'd probably have to copy to contents of bs->backing_file there at some 
point in time, if it is not valid. But this is exactly a point in code 
where bs->backing_file is updated, so there'd be no gain if we instead 
updated bs->backing_hd->filename if necessary and then copied that to 
bs->backing_file, as long as there is no other place in the code where 
bs->backing_hd->filename always has to be a valid filename.


Thus, I think the patch is okay, but I'd probably prefer "if 
(bs->backing_hd->filename[0]) pstrcpy(..., bs->backing_hd->filename);" - 
although that should not differ from the given patch, unless the 
"filename" option is set for the backing_hd.



Max

[Qemu-devel] [PATCH 01/10] target-arm: A64: Add SIMD ld/st multiple

[Peter Maydell]

From: Alex Bennée 

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:

  * do_vec_get - fetch value from a slice of a vector register
  * do_vec_set - set a slice of a vector register

which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:

  * do_vec_ld - load value into SIMD
  * do_vec_st - store value from SIMD

which load or store a slice of a vector register to memory.
These don't zero extend like the fp variants.

Signed-off-by: Alex Bennée 
Signed-off-by: Peter Maydell 
---

v2 -> v3:
   - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):
   - move into new decoder structure
   - use new API for loading temp addr
   - push various variables to local blocks
   - fix semantics of clearing V reg on load
   - tested with risu

v4 -> v5 (ajb):
   - catch more unallocated values
   - add missing returns
   - use do_fp_ld for offset==0 instead of explicit clear_reg

v5 -> v6 (ajb):
   - merge all the various vector helpers into one commit
---
 target-arm/translate-a64.c | 247 -
 1 file changed, 245 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cf80c46..4482e73 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -308,6 +308,28 @@ static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, 
int sf)
 return v;
 }
 
+/* Return the offset into CPUARMState of an element of specified
+ * size, 'element' places in from the least significant end of
+ * the FP/vector register Qn.
+ */
+static inline int vec_reg_offset(int regno, int element, TCGMemOp size)
+{
+int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
+#ifdef HOST_WORDS_BIGENDIAN
+/* This is complicated slightly because vfp.regs[2n] is
+ * still the low half and  vfp.regs[2n+1] the high half
+ * of the 128 bit vector, even on big endian systems.
+ * Calculate the offset assuming a fully bigendian 128 bits,
+ * then XOR to account for the order of the two 64 bit halves.
+ */
+offs += (16 - ((element + 1) * (1 << size)));
+offs ^= 8;
+#else
+offs += element * (1 << size);
+#endif
+return offs;
+}
+
 /* Return the offset into CPUARMState of a slice (from
  * the least significant end) of FP register Qn (ie
  * Dn, Sn, Hn or Bn).
@@ -661,6 +683,108 @@ static void do_fp_ld(DisasContext *s, int destidx, 
TCGv_i64 tcg_addr, int size)
 }
 
 /*
+ * Vector load/store helpers.
+ *
+ * The principal difference between this and a FP load is that we don't
+ * zero extend as we are filling a partial chunk of the vector register.
+ * These functions don't support 128 bit loads/stores, which would be
+ * normal load/store operations.
+ */
+
+/* Get value of an element within a vector register */
+static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
+ int element, TCGMemOp memop)
+{
+int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
+switch (memop) {
+case MO_8:
+tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_16:
+tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_32:
+tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_8|MO_SIGN:
+tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_16|MO_SIGN:
+tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_32|MO_SIGN:
+tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
+break;
+case MO_64:
+case MO_64|MO_SIGN:
+tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+/* Set value of an element within a vector register */
+static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
+  int element, TCGMemOp memop)
+{
+int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
+switch (memop) {
+case MO_8:
+tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
+break;
+case MO_16:
+tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
+break;
+case MO_32:
+tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
+break;
+case MO_64:
+tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+/* Clear the high 64 bits of a 128 bit vector (in general non-quad
+ * vector ops all need to do this).
+ */
+static void clear_vec_high(DisasContext *s, int rd)
+{
+TCGv_i64 tcg_zero = tcg_const_i64(0);
+
+write_vec_element(s, tcg_zero, rd, 1, MO_64);
+tcg_temp_free_i64(tcg_zero);
+}
+
+/* Store from vector register to memory */
+static void

[Qemu-devel] [PATCH 07/10] target-arm: A64: Add SIMD across-lanes instructions

[Peter Maydell]

From: Michael Matz 

Add support for the SIMD "across lanes" instruction group (C3.6.4).

Signed-off-by: Michael Matz 
[PMM: Updated to current codebase, added fp min/max ops,
 added unallocated encoding checks]
Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 177 -
 1 file changed, 176 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ec39dd3..e9aeaa0 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4859,6 +4859,29 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t 
insn)
 tcg_temp_free_i64(tcg_resh);
 }
 
+static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
+int opc, bool is_min, TCGv_ptr fpst)
+{
+/* Helper function for disas_simd_across_lanes: do a single precision
+ * min/max operation on the specified two inputs,
+ * and return the result in tcg_elt1.
+ */
+if (opc == 0xc) {
+if (is_min) {
+gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+} else {
+gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+}
+} else {
+assert(opc == 0xf);
+if (is_min) {
+gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+} else {
+gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+}
+}
+}
+
 /* C3.6.4 AdvSIMD across lanes
  *   31  30  29 28   24 23  22 21   17 1612 11 10 95 40
  * +---+---+---+---+--+---++-+--+--+
@@ -4867,7 +4890,159 @@ static void disas_simd_zip_trn(DisasContext *s, 
uint32_t insn)
  */
 static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int rd = extract32(insn, 0, 5);
+int rn = extract32(insn, 5, 5);
+int size = extract32(insn, 22, 2);
+int opcode = extract32(insn, 12, 5);
+bool is_q = extract32(insn, 30, 1);
+bool is_u = extract32(insn, 29, 1);
+bool is_fp = false;
+bool is_min = false;
+int esize;
+int elements;
+int i;
+TCGv_i64 tcg_res, tcg_elt;
+
+switch (opcode) {
+case 0x1b: /* ADDV */
+if (is_u) {
+unallocated_encoding(s);
+return;
+}
+/* fall through */
+case 0x3: /* SADDLV, UADDLV */
+case 0xa: /* SMAXV, UMAXV */
+case 0x1a: /* SMINV, UMINV */
+if (size == 3 || (size == 2 && !is_q)) {
+unallocated_encoding(s);
+return;
+}
+break;
+case 0xc: /* FMAXNMV, FMINNMV */
+case 0xf: /* FMAXV, FMINV */
+if (!is_u || !is_q || extract32(size, 0, 1)) {
+unallocated_encoding(s);
+return;
+}
+/* Bit 1 of size field encodes min vs max, and actual size is always
+ * 32 bits: adjust the size variable so following code can rely on it
+ */
+is_min = extract32(size, 1, 1);
+is_fp = true;
+size = 2;
+break;
+default:
+unallocated_encoding(s);
+return;
+}
+
+esize = 8 << size;
+elements = (is_q ? 128 : 64) / esize;
+
+tcg_res = tcg_temp_new_i64();
+tcg_elt = tcg_temp_new_i64();
+
+/* These instructions operate across all lanes of a vector
+ * to produce a single result. We can guarantee that a 64
+ * bit intermediate is sufficient:
+ *  + for [US]ADDLV the maximum element size is 32 bits, and
+ *the result type is 64 bits
+ *  + for FMAX*V, FMIN*V, ADDV the intermediate type is the
+ *same as the element size, which is 32 bits at most
+ * For the integer operations we can choose to work at 64
+ * or 32 bits and truncate at the end; for simplicity
+ * we use 64 bits always. The floating point
+ * ops do require 32 bit intermediates, though.
+ */
+if (!is_fp) {
+read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
+
+for (i = 1; i < elements; i++) {
+read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
+
+switch (opcode) {
+case 0x03: /* SADDLV / UADDLV */
+case 0x1b: /* ADDV */
+tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
+break;
+case 0x0a: /* SMAXV / UMAXV */
+tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
+tcg_res,
+tcg_res, tcg_elt, tcg_res, tcg_elt);
+break;
+case 0x1a: /* SMINV / UMINV */
+tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE,
+tcg_res,
+tcg_res, tcg_elt, tcg_res, tcg_elt);
+break;
+break;
+default:
+g_assert_not_reached();
+}
+
+}
+  

[Qemu-devel] [PATCH 10/10] target-arm: A64: Add SIMD scalar copy instructions

[Peter Maydell]

Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).

Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 153a28a..70a8314 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5084,6 +5084,35 @@ static void handle_simd_dupe(DisasContext *s, int is_q, 
int rd, int rn,
 tcg_temp_free_i64(tmp);
 }
 
+/* C6.3.31 DUP (element, scalar)
+ *  31   21 2016 1510  95 40
+ * +---++-+--+--+
+ * | 0 1 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 0 1 |  Rn  |  Rd  |
+ * +---++-+--+--+
+ */
+static void handle_simd_dupes(DisasContext *s, int rd, int rn,
+  int imm5)
+{
+int size = ctz32(imm5);
+int index;
+TCGv_i64 tmp;
+
+if (size > 3) {
+unallocated_encoding(s);
+return;
+}
+
+index = imm5 >> (size + 1);
+
+/* This instruction just extracts the specified element and
+ * zero-extends it into the bottom of the destination register.
+ */
+tmp = tcg_temp_new_i64();
+read_vec_element(s, tmp, rn, index, size);
+write_fp_dreg(s, rd, tmp);
+tcg_temp_free_i64(tmp);
+}
+
 /* C6.3.32 DUP (General)
  *
  *  31  30   29  21 2016 1510  95 40
@@ -5412,7 +5441,18 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t 
insn)
  */
 static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int rd = extract32(insn, 0, 5);
+int rn = extract32(insn, 5, 5);
+int imm4 = extract32(insn, 11, 4);
+int imm5 = extract32(insn, 16, 5);
+int op = extract32(insn, 29, 1);
+
+if (op != 0 || imm4 != 0) {
+unallocated_encoding(s);
+}
+
+/* DUP (element, scalar) */
+handle_simd_dupes(s, rd, rn, imm5);
 }
 
 /* C3.6.8 AdvSIMD scalar pairwise
-- 
1.8.5

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[ronnie sahlberg]

On Fri, Jan 10, 2014 at 8:10 AM, Peter Lieven  wrote:
>
> Ronnie, can you also give a short advise on Kevin's question about short 
> reads.
> I think they can happen if we read beyond past EOF or not?
>

Short reads should normally not happen in libnfs itself since servers
are often careful always trying to sending back as much data as the
client requested.

There is a common exception though, for the case where you read past
the end of file.
So short reads should normally not happen. Unless QEMU or the guest
sends a request to libnfs to read past the end of the file.


If you send a READ for 1024 bytes to an nfs server at the offset 512
bytes from the end-of-file
then the server will respond with a read reply containing 512 bytes of
data  (and the eof flag set in the reply).

In my experience, most kernel/os based clients seem to be very careful
to never try to read beyond enf of file, so this rarely happens in
normal nfs.
(I only recall HPUX being a system where it would be common to always
issue nfs i/o in multiples of 4k   so for those clients it was very
important to make sure you implement short reads correctly in the
server).


I don't know how careful QEMU is in trying to prevent reading past the
end of the device or if it enforces it if the guest tries.
It is probably worth checking for short reads, at least for the case
where you might be reading past end of file.

[Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN

[Peter Maydell]

From: Michael Matz 

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz 
[PMM: use new do_vec_get/set etc functions and generally update to new
 codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 76 +-
 1 file changed, 75 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 336e544..ec39dd3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4782,7 +4782,81 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
 {
-unsupported_encoding(s, insn);
+int rd = extract32(insn, 0, 5);
+int rn = extract32(insn, 5, 5);
+int rm = extract32(insn, 16, 5);
+int size = extract32(insn, 22, 2);
+/* opc field bits [1:0] indicate ZIP/UZP/TRN;
+ * bit 2 indicates 1 vs 2 variant of the insn.
+ */
+int opcode = extract32(insn, 12, 2);
+bool part = extract32(insn, 14, 1);
+bool is_q = extract32(insn, 30, 1);
+int esize = 8 << size;
+int i, ofs;
+int datasize = is_q ? 128 : 64;
+int elements = datasize / esize;
+TCGv_i64 tcg_res, tcg_resl, tcg_resh;
+
+if (opcode == 0 || (size == 3 && !is_q)) {
+unallocated_encoding(s);
+return;
+}
+
+tcg_resl = tcg_const_i64(0);
+tcg_resh = tcg_const_i64(0);
+tcg_res = tcg_temp_new_i64();
+
+for (i = 0; i < elements; i++) {
+switch (opcode) {
+case 1: /* UZP1/2 */
+{
+int midpoint = elements / 2;
+if (i < midpoint) {
+read_vec_element(s, tcg_res, rn, 2 * i + part, size);
+} else {
+read_vec_element(s, tcg_res, rm,
+ 2 * (i - midpoint) + part, size);
+}
+break;
+}
+case 2: /* TRN1/2 */
+if (i & 1) {
+read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
+} else {
+read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
+}
+break;
+case 3: /* ZIP1/2 */
+{
+int base = part * elements / 2;
+if (i & 1) {
+read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
+} else {
+read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
+}
+break;
+}
+default:
+g_assert_not_reached();
+}
+
+ofs = i * esize;
+if (ofs < 64) {
+tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
+tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
+} else {
+tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
+tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
+}
+}
+
+tcg_temp_free_i64(tcg_res);
+
+write_vec_element(s, tcg_resl, rd, 0, MO_64);
+tcg_temp_free_i64(tcg_resl);
+write_vec_element(s, tcg_resh, rd, 1, MO_64);
+tcg_temp_free_i64(tcg_resh);
 }
 
 /* C3.6.4 AdvSIMD across lanes
-- 
1.8.5

[Qemu-devel] [PATCH 08/10] target-arm: A64: Add SIMD copy operations

[Peter Maydell]

From: Alex Bennée 

This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).

Signed-off-by: Alex Bennée 
Signed-off-by: Peter Maydell 
---
 target-arm/translate-a64.c | 210 -
 1 file changed, 209 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e9aeaa0..396782e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5045,6 +5045,173 @@ static void disas_simd_across_lanes(DisasContext *s, 
uint32_t insn)
 tcg_temp_free_i64(tcg_res);
 }
 
+/* C6.3.31 DUP (Element, Vector)
+ *
+ *  31  30   29  21 2016 1510  95 40
+ * +---+---+---++-+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 0 1 |  Rn  |  Rd  |
+ * +---+---+---++-+--+--+
+ *
+ * size: encoded in imm5 (see ARM ARM LowestSetBit())
+ */
+static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
+ int imm5)
+{
+int size = ctz32(imm5);
+int esize = 8 << size;
+int elements = (is_q ? 128 : 64) / esize;
+int index, i;
+TCGv_i64 tmp;
+
+if (size > 3 || (size == 3 && !is_q)) {
+unallocated_encoding(s);
+return;
+}
+
+index = imm5 >> (size + 1);
+
+tmp = tcg_temp_new_i64();
+read_vec_element(s, tmp, rn, index, size);
+
+for (i = 0; i < elements; i++) {
+write_vec_element(s, tmp, rd, i, size);
+}
+
+if (!is_q) {
+clear_vec_high(s, rd);
+}
+
+tcg_temp_free_i64(tmp);
+}
+
+/* C6.3.32 DUP (General)
+ *
+ *  31  30   29  21 2016 1510  95 40
+ * +---+---+---++-+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 1 1 |  Rn  |  Rd  |
+ * +---+---+---++-+--+--+
+ *
+ * size: encoded in imm5 (see ARM ARM LowestSetBit())
+ */
+static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
+ int imm5)
+{
+int size = ctz32(imm5);
+int esize = 8 << size;
+int elements = (is_q ? 128 : 64)/esize;
+int i = 0;
+
+if (size > 3 || ((size == 3) && !is_q)) {
+unallocated_encoding(s);
+return;
+}
+for (i = 0; i < elements; i++) {
+write_vec_element(s, cpu_reg(s, rn), rd, i, size);
+}
+if (!is_q) {
+clear_vec_high(s, rd);
+}
+}
+
+/* C6.3.150 INS (Element)
+ *
+ *  31   21 2016 15  1411  10 95 40
+ * +---+++---+--+--+
+ * | 0 1 1 0 1 1 1 0 0 0 0 |  imm5  | 0 |  imm4  | 1 |  Rn  |  Rd  |
+ * +---+++---+--+--+
+ *
+ * size: encoded in imm5 (see ARM ARM LowestSetBit())
+ * index: encoded in imm5<4:size+1>
+ */
+static void handle_simd_inse(DisasContext *s, int rd, int rn,
+ int imm4, int imm5)
+{
+int size = ctz32(imm5);
+int src_index, dst_index;
+TCGv_i64 tmp;
+
+if (size > 3) {
+unallocated_encoding(s);
+return;
+}
+dst_index = extract32(imm5, 1+size, 5);
+src_index = extract32(imm4, size, 4);
+
+tmp = tcg_temp_new_i64();
+
+read_vec_element(s, tmp, rn, src_index, size);
+write_vec_element(s, tmp, rd, dst_index, size);
+
+tcg_temp_free_i64(tmp);
+}
+
+
+/* C6.3.151 INS (General)
+ *
+ *  31   21 2016 1510  95 40
+ * +---++-+--+--+
+ * | 0 1 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 0 1 1 1 |  Rn  |  Rd  |
+ * +---++-+--+--+
+ *
+ * size: encoded in imm5 (see ARM ARM LowestSetBit())
+ * index: encoded in imm5<4:size+1>
+ */
+static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
+{
+int size = ctz32(imm5);
+int idx;
+
+if (size > 3) {
+unallocated_encoding(s);
+return;
+}
+
+idx = extract32(imm5, 1 + size, 4 - size);
+write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
+}
+
+/*
+ * C6.3.321 UMOV (General)
+ * C6.3.237 SMOV (General)
+ *
+ *  31  30   29  21 2016 1512   10 95 40
+ * +---+---+---++-+--+--+
+ * | 0 | Q | 0 0 1 1 1 0 0 0 0 |  imm5  | 0 0 1 U 1 1 |  Rn  |  Rd  |
+ * +---+---+---++-+--+--+
+ *
+ * U: unsigned when set
+ * size: encoded in imm5 (see ARM ARM LowestSetBit())
+ */
+static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
+  int rn, int rd, int imm5)
+{
+int size = ctz32(imm5);
+int element;
+TCGv_i64 tcg_rd;
+
+/* Check for UnallocatedEncodings */
+if (is_signed) {
+if (size > 2 || (size == 2 && !is_q)) {
+unallocated_encoding(s);
+  

Re: [Qemu-devel] [PATCH] Add option to disable FDC from ISA bus and ACPI on i386

[Igor Mammedov]

On Fri, 10 Jan 2014 10:35:14 -0500
"Gabriel L. Somlo"  wrote:

> On Fri, Jan 10, 2014 at 01:37:14PM +0100, Paolo Bonzini wrote:
> > Il 09/01/2014 22:44, Gabriel L. Somlo ha scritto:
> > > 1. hardcode "IRQNoFlags(){2, 8}" and require -no-hpet to prevent XP
> > >from bluescreening. Basically, this means we don't support XP on
> > >a VM where HPET is enabled.
> > > 
> > > 2. conditionally insert "IRQNoFlags(){2, 8}" if _OSI("Darwin") returns
> > >0x, which is only necessary if we want to run OS X on piix+smp
> > >(all other combinations of (piix vs. q35) x (up vs.  smp) work fine
> > >already).
> > 
> > _OSI is bad, but (1) is worse.
> 
> Agreed.
> 
> > > I still don't get why on real hardware where the HPET has
> > > "IRQNoFlags(){2, 8}" in its _CRS method XP seems to be OK...
> > 
> > My laptop has this:
> >
> > [...] 
> >
> > Name (BUF0, ResourceTemplate ()
> > {
> > Memory32Fixed (ReadOnly,
> > 0xFED0, // Address Base
> > 0x0400, // Address Length
> > _Y27)
> > })
> > Method (_CRS, 0, Serialized)  // _CRS: Current Resource 
> > Settings
> > {
> > CreateDWordField (BUF0, 
> > \_SB.PCI0.LPC.HPET._Y27._BAS, HPT0)  // _BAS: Base Address
> > Store (\HPET, HPT0)// HPET comes from a table 
> > that BIOS fills in reserved memory
> > Return (BUF0)
> > }
> > }
> > 
> > so no IRQs, and my workstation is similar.  They are respectively from
> > Lenovo and Fujitsu.  Looks like an Apple quirk.
> 
> Hmmm, I could have sworn I saw IRQNoFlags on one of my old Dell
> laptops (Dell Latitude D630), but I just had another look and it's
> not there, so I was clearly misremembering that !
> 
> I think you're right, of all the hardware I currently have access to,
> only the various Apple machines have IRQNoFlags in HPET._CRS !
> 
> Given that, I'm starting to feel better and better about using _OSI().
> 
> Michael: regarding your comment about "ConcatenateResTemplate" not
> being supported by XP: Can I safely assume that as long as it's always
> on the branch NOT taken by XP, we're OK having it in there ? E.g.,
there is harder route to get a clue why XP BSODs,
one can use AMLI debugger to see what is happening in XP on boot
http://msdn.microsoft.com/en-us/library/windows/hardware/ff537808%28v=vs.85%29.aspx
that was how I found out about not supported ConcatenateResTemplate first.

> 
> if _OSI("Darwin") then
>   ConcatenateResTemplate...
> else
>   stuff_that_XP_cares_about
> 
> Once I have that sorted out, I'll send a patch.
> 
> Thanks,
> --Gabriel

[Qemu-devel] [Bug 1267520] Re: Keyboard input not working when the "-k en-us" argument is specified.

[Mofi Taiwo]

** Description changed:

  This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.
  
  Additional information:
  Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
  I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.
  
  Update: I have narrowed the bug to be attributable to versions later
  than qemu-1.1.2.
+ 
+ Here's a listing of key being mapped:
+ 
+ Setting keysym exclam (33) to 258
+ Setting keysym at (64) to 259
+ Setting keysym numbersign (35) to 260
+ Setting keysym dollar (36) to 261
+ Setting keysym percent (37) to 262
+ Setting keysym asciicircum (94) to 263
+ Setting keysym ampersand (38) to 264
+ Setting keysym asterisk (42) to 265
+ Setting keysym parenleft (40) to 266
+ Setting keysym parenright (41) to 267
+ Setting keysym minus (45) to 12
+ Setting keysym underscore (95) to 268
+ Setting keysym equal (61) to 13
+ Setting keysym plus (43) to 269
+ Setting keysym bracketleft (91) to 26
+ Setting keysym braceleft (123) to 282
+ Setting keysym bracketright (93) to 27
+ Setting keysym braceright (125) to 283
+ Setting keysym semicolon (59) to 39
+ Setting keysym colon (58) to 295
+ Setting keysym apostrophe (39) to 40
+ Setting keysym quotedbl (34) to 296
+ Setting keysym grave (96) to 41
+ Setting keysym asciitilde (126) to 297
+ Setting keysym backslash (92) to 43
+ Setting keysym bar (124) to 299
+ Setting keysym comma (44) to 51
+ Setting keysym less (60) to 307
+ Setting keysym period (46) to 52
+ Setting keysym greater (62) to 308
+ Setting keysym slash (47) to 53
+ Setting keysym question (63) to 309
+ 
+ As one can see, the pc-bios/keymaps/common is not processed in
+ parse_init_keyboard at ui/keymaps.c even though the XKB map (keymaps/en-
+ us) includes the file.

** Description changed:

  This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.
  
  Additional information:
  Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
  I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.
  
  Update: I have narrowed the bug to be attributable to versions later
  than qemu-1.1.2.
  
  Here's a listing of key being mapped:
  
  Setting keysym exclam (33) to 258
  Setting keysym at (64) to 259
  Setting keysym numbersign (35) to 260
  Setting keysym dollar (36) to 261
  Setting keysym percent (37) to 262
  Setting keysym asciicircum (94) to 263
  Setting keysym ampersand (38) to 264
  Setting keysym asterisk (42) to 265
  Setting keysym parenleft (40) to 266
  Setting keysym parenright (41) to 267
  Setting keysym minus (45) to 12
  Setting keysym underscore (95) to 268
  Setting keysym equal (61) to 13
  Setting keysym plus (43) to 269
  Setting keysym bracketleft (91) to 26
  Setting keysym braceleft (123) to 282
  Setting keysym bracketright (93) to 27
  Setting keysym braceright (125) to 283
  Setting keysym semicolon (59) to 39
  Setting keysym colon (58) to 295
  Setting keysym apostrophe (39) to 40
  Setting keysym quotedbl (34) to 296
  Setting keysym grave (96) to 41
  Setting keysym asciitilde (126) to 297
  Setting keysym backslash (92) to 43
  Setting keysym bar (124) to 299
  Setting keysym comma (44) to 51
  Setting keysym less (60) to 307
  Setting keysym period (46) to 52
  Setting keysym greater (62) to 308
  Setting keysym slash (47) to 53
  Setting keysym question (63) to 309
  
- As one can see, the pc-bios/keymaps/common is not processed in
- parse_init_keyboard at ui/keymaps.c even though the XKB map (keymaps/en-
- us) includes the file.
+ As one can see, the pc-bios/keymaps/common, contaning the QWWERTY keys,
+ is not processed in parse_init_k

Re: [Qemu-devel] [PATCHv5] block: add native support for NFS

[Peter Lieven]

Am 10.01.2014 16:46, schrieb Kevin Wolf:
> Am 10.01.2014 um 16:05 hat Peter Lieven geschrieben:
>> On 10.01.2014 15:49, ronnie sahlberg wrote:
>>> On Fri, Jan 10, 2014 at 4:30 AM, Paolo Bonzini  wrote:
 Il 10/01/2014 13:12, Peter Lieven ha scritto:
> Then I shall convert everything to a qapi schema whereby the current
> design of libnfs is designed to work with plain URLs.
 No, no one is asking you to do this.  URLs are fine, but I agree with
 Kevin that parsing them in QEMU is better.

 Also because the QEMU parser is known to be based on RFCs and good code
>>> >from libxml2.  For example, the iSCSI URL parser, when introduced,
 didn't even have percent-escape parsing, causing libvirt to fail with
 old libiscsi (and actually not that old too: IIRC libiscsi 1.7 will
 still fail).  Unless the libnfs parser is as good as libxml2's, I think
 there's value in using the QEMU URI parser.
>>> I think that is fair enough.
>>>
>>> The arguments we are talking about are the type of arguments that only
>>> affect the interface between libnfs and the nfs server itself
>>> and is not strictly all that interesting to the application that links
>>> to libnfs.
>>>
>>> Since parsing a URL does require a fair amount of code, a hundred
>>> lines or more, it is a bit annoying having to re-implement the parsing
>>> code for every single small utility. For example  nfs-ls   nfs-cp
>>> nfs-cpor for the parsing, that is still done, in the sg-utils
>>> patch.
>>> For a lot of these small and semi-trivial applications we don't really
>>> care all that much about what the options are but we might care a lot
>>> about making it easier to use libnfs and to avoid having to write a
>>> parser each time.
>>>
>>> For those use cases, I definitely think that having a built in
>>> function to parse a url, and automatically update the nfs context with
>>> connection related tweaks is a good thing. It eliminates the need to
>>> re-implement the parsing functions in every single trivial
>>> application.
>>>
>>>
>>> For QEMU and libvirt things may be different. These are non-trivial
>>> applications and may have needs to be able to control the settings
>>> explicitely in the QEMU code.
>>> That is still possible to do. All the url arguments so far tweak
>>> arguments that can also be controlled through explicit existing APIs.
>>> So for QEMU, there are functions available in libnfs now that will
>>> automatically update the nfs context with things like UID/GID to use
>>> when talking to the server, passed via the URL and QEMU can use them.
>>> On the other hand, if QEMU rather wants to parse the URL itself
>>> and make calls into the libnfs API to tweak these settings directly
>> >from the QEMU codebase, that is also possible.
>>>
>>> For example:   nfs://1.2.3.4/path/file?uid=10&gid=10
>>> When parsing these using the libnfs functions, the parsing functions
>>> will automatically update the nfs context so that it will use these
>>> values when it fills in the rpc header to send to the server.
>>> But if you want to parse the url yourself, you can do that too, by
>>> just calling   nfs_set_auth(nfs,  libnfs_authunix_create(..., 10, 10,
>>> ...
>>
>> Proposal:
>> I revert the URL parsing code to v4 of the patch:
>> [...]
> Agreed.
>
>> And then pipe all the URL params (in QueryParams) through a (to be defined
>> public) function in libnfs
>>
>> nfs_set_context_args(struct nfs_context *nfs, char *arg, char *val);
> I wouldn't do that. We should use specific functions like Ronnie
> suggested in his nfs_set_auth() example.
Ronnie, I would map to the following functions. Especially for uid,gid because
we would have to add all that specific what to do on windows and what to do if
a user specifies only a uid and no gid stuff again:

uid => rpc_set_uid
gid => rpc_set_gid
tcp-syncnt => rpc_set_tcp_syncnt
autoreconnect => rpc_{set,unset}_autoreconnect

Ronnie, can you also give a short advise on Kevin's question about short reads.
I think they can happen if we read beyond past EOF or not?

>
>> And we leave all the
>>
>> QemuOptsList
>>
>> and qapi-schema.json stuff for a later version when we touch all the other 
>> protocols.
> Okay, I'll take care of it. For the time being, please include the TODO
> comment that the other network-based drivers have.
Thanks. Kevin, can you please give an advice how to proceed with the 
qemu-iotests.

Peter

[Qemu-devel] [Bug 1267520] Re: Keyboard input not working when the "-k en-us" argument is specified.

[Mofi Taiwo]

** Description changed:

- This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit).
+ This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit). (Haven't confirmed this for other targets).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.
  
  Additional information:
  Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
  I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.
  
  Update: I have narrowed the bug to be attributable to versions later
  than qemu-1.1.2.
  
  Here's a listing of key being mapped:
  
  Setting keysym exclam (33) to 258
  Setting keysym at (64) to 259
  Setting keysym numbersign (35) to 260
  Setting keysym dollar (36) to 261
  Setting keysym percent (37) to 262
  Setting keysym asciicircum (94) to 263
  Setting keysym ampersand (38) to 264
  Setting keysym asterisk (42) to 265
  Setting keysym parenleft (40) to 266
  Setting keysym parenright (41) to 267
  Setting keysym minus (45) to 12
  Setting keysym underscore (95) to 268
  Setting keysym equal (61) to 13
  Setting keysym plus (43) to 269
  Setting keysym bracketleft (91) to 26
  Setting keysym braceleft (123) to 282
  Setting keysym bracketright (93) to 27
  Setting keysym braceright (125) to 283
  Setting keysym semicolon (59) to 39
  Setting keysym colon (58) to 295
  Setting keysym apostrophe (39) to 40
  Setting keysym quotedbl (34) to 296
  Setting keysym grave (96) to 41
  Setting keysym asciitilde (126) to 297
  Setting keysym backslash (92) to 43
  Setting keysym bar (124) to 299
  Setting keysym comma (44) to 51
  Setting keysym less (60) to 307
  Setting keysym period (46) to 52
  Setting keysym greater (62) to 308
  Setting keysym slash (47) to 53
  Setting keysym question (63) to 309
  
  As one can see, the pc-bios/keymaps/common, contaning the QWWERTY keys,
  is not processed in parse_init_keyboard at ui/keymaps.c even though the
  XKB map (keymaps/en-us) includes the file.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1267520

Title:
  Keyboard input not working when the "-k en-us" argument is specified.

Status in QEMU:
  New

Bug description:
  This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit). (Haven't confirmed this for other targets).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.

  Additional information:
  Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
  I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.

  Update: I have narrowed the bug to be attributable to versions later
  than qemu-1.1.2.

  Here's a listing of key being mapped:

  Setting keysym exclam (33) to 258
  Setting keysym at (64) to 259
  Setting keysym numbersign (35) to 260
  Setting keysym dollar (36) to 261
  Setting keysym percent (37) to 262
  Setting keysym asciicircum (94) to 263
  Setting keysym ampersand (38) to 264
  Setting keysym asterisk (42) to 265
  Setting keysym parenleft (40) to 266
  Setting keysym parenright (41) to 267
  Setting keysym minus (45) to 12
  Setting keysym underscore (95) to 268
  Setting keysym equal (61) to 13
  Setting keysym plus (43) to 269
  Setting keysym bracketleft (91) to 26
  Setting keysym braceleft (123) to 282
  Setting keysym bracketright (93) to 27
  Setting keysym braceright (125) to 283
  Setting keysym semicolon (59) to 39
  Setting keysym colon (58) to 295
  Setting keysym apostrophe (39) to 40
  Setting keysym quotedbl (34) to 296
  Setting keysym grave (96) to 41
  Setting keysym asciitilde (126) to 297
  Setting keysym backslash (92) to 43
  Setting keysym bar (124) to 299
  Setting keysym comma (44)

Re: [Qemu-devel] [PATCH 0/2] acpi: Fix PCI hole handling on SRAT table

[Eduardo Habkost]

On Fri, Jan 10, 2014 at 04:17:14PM +0100, Igor Mammedov wrote:
> On Thu,  9 Jan 2014 17:12:41 -0200
> Eduardo Habkost  wrote:
> 
> > The original SeaBIOS code used the RamSize variable, that was used by
> > SeaBIOS for the size of RAM below 4GB, not for all RAM. When copied to
> > QEMU, the code was changed to use the full RAM size, and this broke the
> > build_srat() code that handles the PCI hole.
> > 
> > This series fixes the problem by restoring the original behavior from 
> > SeaBIOS.
> > 
[...]
> > 
> > Eduardo Habkost (2):
> >   pc: Save size of RAM below 4GB
> >   acpi-build: Fix PCI hole handling on build_srat()
> > 
> >  hw/i386/acpi-build.c | 10 +-
> >  hw/i386/pc.c |  1 +
> >  include/hw/i386/pc.h |  2 +-
> >  3 files changed, 7 insertions(+), 6 deletions(-)
> > 
> 
> since purpose of the the block you are touching is to exclude PCI hole
> from SRAT could you use acpi_get_pci_info() instead?

That would make sense, but as that was not the original behavior from
SeaBIOS, I prefer to first fix this obvious and simple translation
mistake, and then make the code able to use acpi_get_pci_info() (which
won't be as trivial to write/review as this fix).

(I didn't even review the existing PCI hole exclusion logic myself. I
simply made sure that the code matches what's inside SeaBIOS today and
is known to work.)

-- 
Eduardo

Re: [Qemu-devel] [Xen-devel] [PATCH] xen_pt: Fix debug output.

[Konrad Rzeszutek Wilk]

On Fri, Jan 10, 2014 at 03:52:54PM +, Anthony PERARD wrote:
> Signed-off-by: Anthony PERARD 

Reviewed-by: Konrad Rzeszutek Wilk 

I saw myself and was going to post a fix, but you beat me to it.
> ---
>  hw/xen/xen_pt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
> index d58cb61..eee4354 100644
> --- a/hw/xen/xen_pt.c
> +++ b/hw/xen/xen_pt.c
> @@ -420,8 +420,8 @@ static int xen_pt_register_regions(XenPCIPassthroughState 
> *s)
>"xen-pci-pt-bar", r->size);
>  pci_register_bar(&s->dev, i, type, &s->bar[i]);
>  
> -XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%lx"PRIx64
> -   " base_addr=0x%lx"PRIx64" type: %#x)\n",
> +XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64
> +   " base_addr=0x%08"PRIx64" type: %#x)\n",
> i, r->size, r->base_addr, type);
>  }
>  
> -- 
> Anthony PERARD
> 
> 
> ___
> Xen-devel mailing list
> xen-de...@lists.xen.org
> http://lists.xen.org/xen-devel

[Qemu-devel] [Bug 1267520] Re: Keyboard input not working when the "-k en-us" argument is specified.

[Mofi Taiwo]

** Description changed:

  This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.
  
  Additional information:
- Setting keymaps directory on command line -L doesn't resolve this. 
+ Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
- I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific.
+ I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.
+ 
+ Update: I have narrowed the bug to be attributable to versions later
+ than qemu-1.1.2.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1267520

Title:
  Keyboard input not working when the "-k en-us" argument is specified.

Status in QEMU:
  New

Bug description:
  This bug occurs on qemu compiled with i386_softmmu and x86-64_softmmu on 
linux kernel 3.5.0 (64-bit).
  Whenever I run qemu (both i386 and x86_64) to use the en-us language (even 
though it is the default), I get "Warning: no scancode found for keysym X" (X 
is an integer).
  In the disk image I need qemu to run, I had a shell set up.  The shell 
doesn't register keyboard input when the '-k en-us' command line argument is 
set to run qemu. I did not have this problem with earlier versions of qemu.

  Additional information:
  Setting keymaps directory on command line -L doesn't resolve this.
  Bug occurs with on both curses and sdl VGA output.
  I am running qemu on Ubuntu 12.04 and I have not been able see if the bug is 
distribution-specific. However, I am also experiencing the bug on Kali-Linux; 
another debian based distribution.
  It turns out that all languages reproduce the bug, not just 'en-us'.

  Update: I have narrowed the bug to be attributable to versions later
  than qemu-1.1.2.

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