Re: [Qemu-devel] [PATCH 2.1 11/28] qmp: improve error reporting for -object and object-add
Il 07/03/2014 04:07, Hu Tao ha scritto: There is already an accepted version de580dafade551. Paolo, I found that your numa tree is behind current master about 99 commits. I'd like to take over this series if you have no time on it. Sure, I rebased it and pushed it again (not tested the rebase yet). Paolo
Re: [Qemu-devel] [PATCH] mempath: add option to specify minimum huge page size
Il 07/03/2014 01:40, Marcelo Tosatti ha scritto:
Failing initialization in case hugepage path has
hugepage smaller than specified.
Signed-off-by: Marcelo Tosatti
Why is this needed? Isn't it just operator error?
Perhaps libvirt could add an attribute to its XML element,
and could use it to find the appropriate hugetlbfs mount. But I don't
think this check belongs in QEMU.
Also, see the series I posted recently for a complete (and more powerful
+ more extensible) replacement of -mem-path and -mem-prealloc.
Paolo
diff --git a/exec.c b/exec.c
index b69fd29..c95a0f3 100644
--- a/exec.c
+++ b/exec.c
@@ -1034,6 +1034,13 @@ static void *file_ram_alloc(RAMBlock *block,
return NULL;
}
+if (mem_path_min_hpagesize && hpagesize < mem_path_min_hpagesize) {
+fprintf(stderr, "mount point (%s) has page size "
+"(%ld) < (%ld) = min_hpagesize\n", path, hpagesize,
+mem_path_min_hpagesize);
+exit(1);
+}
+
if (memory < hpagesize) {
return NULL;
}
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 4cb4b4a..cc9e28a 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -470,6 +470,7 @@ extern RAMList ram_list;
extern const char *mem_path;
extern int mem_prealloc;
+extern unsigned long int mem_path_min_hpagesize;
/* Flags stored in the low bits of the TLB virtual address. These are
defined so that fast path ram access is all zeros. */
diff --git a/qemu-options.hx b/qemu-options.hx
index 56e5fdf..36743e1 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -221,9 +221,9 @@ gigabytes respectively.
ETEXI
DEF("mem-path", HAS_ARG, QEMU_OPTION_mempath,
-"-mem-path FILE provide backing storage for guest RAM\n", QEMU_ARCH_ALL)
+"-mem-path [mem-path=]file[,min-hpage-size=value] provide backing storage for
guest RAM\n", QEMU_ARCH_ALL)
STEXI
-@item -mem-path @var{path}
+@item -mem-path [mem-path=]@var{path}[,min-hpage-size=@var{min-hpage-size}]
@findex -mem-path
Allocate guest RAM from a temporarily created file in @var{path}.
ETEXI
diff --git a/vl.c b/vl.c
index 1d27b34..08f9bee 100644
--- a/vl.c
+++ b/vl.c
@@ -136,6 +136,7 @@ static int display_remote;
const char* keyboard_layout = NULL;
ram_addr_t ram_size;
const char *mem_path = NULL;
+unsigned long int mem_path_min_hpagesize;
int mem_prealloc = 0; /* force preallocation of physical target memory */
int nb_nics;
NICInfo nd_table[MAX_NICS];
@@ -479,6 +480,22 @@ static QemuOptsList qemu_msg_opts = {
},
};
+static QemuOptsList qemu_mempath_opts = {
+.name = "mem-path",
+.implied_opt_name = "mem-path",
+.head = QTAILQ_HEAD_INITIALIZER(qemu_mempath_opts.head),
+.desc = {
+{
+.name = "mem-path",
+.type = QEMU_OPT_STRING,
+},{
+.name = "min-hpage-size",
+.type = QEMU_OPT_SIZE,
+},
+{ /* end of list */ }
+},
+};
+
/**
* Get machine options
*
@@ -2863,6 +2880,7 @@ int main(int argc, char **argv, char **envp)
qemu_add_opts(&qemu_tpmdev_opts);
qemu_add_opts(&qemu_realtime_opts);
qemu_add_opts(&qemu_msg_opts);
+qemu_add_opts(&qemu_mempath_opts);
runstate_init();
@@ -3189,9 +3207,16 @@ int main(int argc, char **argv, char **envp)
}
break;
#endif
-case QEMU_OPTION_mempath:
-mem_path = optarg;
+case QEMU_OPTION_mempath: {
+opts = qemu_opts_parse(qemu_find_opts("mem-path"), optarg, 1);
+if (!opts) {
+exit(1);
+}
+mem_path = qemu_opt_get(opts, "mem-path");
+mem_path_min_hpagesize = qemu_opt_get_size(opts,
+ "min-hpage-size",
0);
break;
+}
case QEMU_OPTION_mem_prealloc:
mem_prealloc = 1;
break;
Re: [Qemu-devel] [PATCH v15 05/14] block: Add bdrv_set_backing_hd()
On Wed, 02/26 17:35, Jeff Cody wrote:
> On Sun, Feb 23, 2014 at 09:54:46AM +0800, Fam Zheng wrote:
> > This is the common but non-trivial steps to assign or change the
> > backing_hd of BDS.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > block.c | 46 ++
> > include/block/block.h | 1 +
> > 2 files changed, 39 insertions(+), 8 deletions(-)
> >
> > diff --git a/block.c b/block.c
> > index 684b9d6..9caade9 100644
> > --- a/block.c
> > +++ b/block.c
> > @@ -1041,6 +1041,32 @@ fail:
> > return ret;
> > }
> >
> > +void bdrv_set_backing_hd(BlockDriverState *bs, BlockDriverState
> > *backing_hd)
> > +{
> > +if (backing_hd) {
> > +/* Grab the reference before unref original backing_hd, so we are
> > safe
> > + * when rebasing in the backing chain.
> > + */
> > +bdrv_ref(backing_hd);
>
> I think the problem is performing this bdrv_ref() makes the
> assumptions that:
>
> A) bs->backing_hd is non-NULL, and
> B) backing_hd is currently a backing file, at some level, of
>bs->backing_chain.
>
> The above conditions are not always true, which is what led to my
> concerns in my previous email. I think we could avoid the spurious
> bdrv_ref() if we check for both conditions A and B before calling
> bdrv_ref(backing_hd).
>
> But I think there could still be a problem...
>
> > +}
> > +
> > +if (bs->backing_hd) {
> > +bdrv_unref(bs->backing_hd);
>
> Only if conditions A and B are true would this bdrv_unref()
> potentially lead to a bdrv_unref() being called on backing_hd.
>
> But what if the refcnt on bs->backing_hd is > 1? Then even if
> conditions A and B are met, we still won't eventually unref
> backing_hd, making the bdrv_ref(backing_hd) spurious.
>
> But as I mentioned before, manually checking refcnt, or making
> assumptions on refcnt, seems very wrong.
>
> It is almost like what is needed, are some conditional refcnt
> implementations. Something like:
>
>void bdrv_cond_ref(BlockDriverState *bs_cond, BlockDriverState *bs)
>
> That would increase the refcnt on bs_cond IFF:
>
> 1) bs is non-NULL
> 2) bs_cond is in the backing chain of bs
> 3) bs is at risk of deletion on the next unref
>
I see the problem, however these rules (bdrv_cond_ref) still look hard to
infer.
To keep it simple, I prefer to remove bdrv_ref/bdrv_unref in
bdrv_set_backing_hd and leave it to caller, which is the most readable I think.
Fam
Re: [Qemu-devel] [PATCH v15 03/14] block: Replace in_use with operation blocker
On Thu, 02/27 13:12, Markus Armbruster wrote:
> Fam Zheng writes:
>
> > This drops BlockDriverState.in_use with op_blockers:
> >
> > - Call bdrv_op_block_all in place of bdrv_set_in_use(bs, 1).
> > - Call bdrv_op_unblock_all in place of bdrv_set_in_use(bs, 0).
> > - Check bdrv_op_is_blocked() in place of bdrv_in_use(bs).
> > The specific types are used, e.g. in place of starting block backup,
> > bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_BACKUP, ...).
> > - Check bdrv_op_blocker_is_empty() in place of assert(!bs->in_use).
> >
> > Note: there is only bdrv_op_block_all and bdrv_op_unblock_all callers at
> > this moment. So although the checks are specific to op types, this
> > changes can still be seen as identical logic with previously with
> > in_use. The difference is error message are improved because of blocker
> > error info.
> [...]
> > diff --git a/blockdev.c b/blockdev.c
> > index 357f760..5c5a9c4 100644
> > --- a/blockdev.c
> > +++ b/blockdev.c
> [...]
> > @@ -1723,7 +1722,7 @@ int do_drive_del(Monitor *mon, const QDict *qdict,
> > QObject **ret_data)
> > qerror_report(QERR_DEVICE_NOT_FOUND, id);
> > return -1;
> > }
> > -if (bdrv_in_use(bs)) {
> > +if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_DRIVE_DEL, NULL)) {
> > qerror_report(QERR_DEVICE_IN_USE, id);
> > return -1;
> > }
>
> Loses the nice message you stored in bs->blockers[]. You could put it
> to use like this:
>
> diff --git a/blockdev.c b/blockdev.c
> index 0843ca7..4ab9832 100644
> --- a/blockdev.c
> +++ b/blockdev.c
> @@ -1763,6 +1763,7 @@ void qmp_block_set_io_throttle(const char *device,
> int64_t bps, int64_t bps_rd,
> int do_drive_del(Monitor *mon, const QDict *qdict, QObject **ret_data)
> {
> const char *id = qdict_get_str(qdict, "id");
> +Error *local_err = NULL;
> BlockDriverState *bs;
>
> bs = bdrv_find(id);
> @@ -1770,8 +1771,9 @@ int do_drive_del(Monitor *mon, const QDict *qdict,
> QObject **ret_data)
> qerror_report(QERR_DEVICE_NOT_FOUND, id);
> return -1;
> }
> -if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_DRIVE_DEL, NULL)) {
> -qerror_report(QERR_DEVICE_IN_USE, id);
> +if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_DRIVE_DEL, &local_err)) {
> +error_report("%s", error_get_pretty(local_err));
> +error_free(local_err);
> return -1;
> }
>
> I can do it on top, if you prefer.
>
Nice. Thanks, will update this patch when respin.
Fam
Re: [Qemu-devel] [PATCH 2.1 16/28] memory: reorganize file-based allocation
Il 07/03/2014 07:09, Hu Tao ha scritto:
On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
Split the internal interface in exec.c to a separate function, and
push the check on mem_path up to memory_region_init_ram.
Signed-off-by: Paolo Bonzini
---
exec.c | 105 +---
include/exec/cpu-all.h | 3 --
include/exec/ram_addr.h | 2 +
include/sysemu/sysemu.h | 2 +
memory.c| 7 +++-
5 files changed, 73 insertions(+), 46 deletions(-)
diff --git a/exec.c b/exec.c
index b69fd29..0aa4947 100644
--- a/exec.c
+++ b/exec.c
@@ -1240,56 +1240,30 @@ static int memory_try_enable_merging(void *addr, size_t
len)
return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
}
-ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
- MemoryRegion *mr)
+static ram_addr_t ram_block_add(RAMBlock *new_block)
{
-RAMBlock *block, *new_block;
+RAMBlock *block;
ram_addr_t old_ram_size, new_ram_size;
old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
-size = TARGET_PAGE_ALIGN(size);
-new_block = g_malloc0(sizeof(*new_block));
-new_block->fd = -1;
-
/* This assumes the iothread lock is taken here too. */
qemu_mutex_lock_ramlist();
-new_block->mr = mr;
-new_block->offset = find_ram_offset(size);
-if (host) {
-new_block->host = host;
-new_block->flags |= RAM_PREALLOC_MASK;
-} else if (xen_enabled()) {
-if (mem_path) {
-fprintf(stderr, "-mem-path not supported with Xen\n");
-exit(1);
-}
-xen_ram_alloc(new_block->offset, size, mr);
-} else {
-if (mem_path) {
-if (phys_mem_alloc != qemu_anon_ram_alloc) {
-/*
- * file_ram_alloc() needs to allocate just like
- * phys_mem_alloc, but we haven't bothered to provide
- * a hook there.
- */
-fprintf(stderr,
-"-mem-path not supported with this accelerator\n");
-exit(1);
-}
-new_block->host = file_ram_alloc(new_block, size, mem_path);
-}
-if (!new_block->host) {
-new_block->host = phys_mem_alloc(size);
+new_block->offset = find_ram_offset(new_block->length);
+
+if (!new_block->host) {
+if (xen_enabled()) {
+xen_ram_alloc(new_block->offset, new_block->length, new_block->mr);
+} else {
+new_block->host = phys_mem_alloc(new_block->length);
if (!new_block->host) {
fprintf(stderr, "Cannot set up guest memory '%s': %s\n",
new_block->mr->name, strerror(errno));
exit(1);
}
-memory_try_enable_merging(new_block->host, size);
+memory_try_enable_merging(new_block->host, new_block->length);
}
}
-new_block->length = size;
/* Keep the list sorted from biggest to smallest block. */
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
@@ -1317,18 +1291,65 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size,
void *host,
old_ram_size, new_ram_size);
}
}
-cpu_physical_memory_set_dirty_range(new_block->offset, size);
+cpu_physical_memory_set_dirty_range(new_block->offset, new_block->length);
-qemu_ram_setup_dump(new_block->host, size);
-qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE);
-qemu_madvise(new_block->host, size, QEMU_MADV_DONTFORK);
+qemu_ram_setup_dump(new_block->host, new_block->length);
+qemu_madvise(new_block->host, new_block->length, QEMU_MADV_HUGEPAGE);
+qemu_madvise(new_block->host, new_block->length, QEMU_MADV_DONTFORK);
-if (kvm_enabled())
-kvm_setup_guest_memory(new_block->host, size);
+if (kvm_enabled()) {
+kvm_setup_guest_memory(new_block->host, new_block->length);
+}
return new_block->offset;
}
+ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
+const char *mem_path)
+{
+RAMBlock *new_block;
+
+if (xen_enabled()) {
+fprintf(stderr, "-mem-path not supported with Xen\n");
+exit(1);
+}
+
+if (phys_mem_alloc != qemu_anon_ram_alloc) {
+/*
+ * file_ram_alloc() needs to allocate just like
+ * phys_mem_alloc, but we haven't bothered to provide
+ * a hook there.
+ */
+fprintf(stderr,
+"-mem-path not supported with this accelerator\n");
+exit(1);
+}
+
+size = TARGET_PAGE_ALIGN(size);
+new_block = g_malloc0(sizeof(*new_block));
+new_block->mr = mr;
+new_block->length = size;
+new_block->host = file_ram_alloc(new_block, size, mem_path);
+return ram_block_add(new_block);
+}
+
+ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
+
Re: [Qemu-devel] [PATCH 2.1 15/28] numa: add -numa node, memdev= option
Il 07/03/2014 06:33, Hu Tao ha scritto:
On Tue, Mar 04, 2014 at 03:00:43PM +0100, Paolo Bonzini wrote:
This option provides the infrastructure for binding guest NUMA nodes
to host NUMA nodes. For example:
-object memory-ram,size=1024M,policy=membind,host-nodes=0,id=ram-node0 \
-numa node,nodeid=0,cpus=0,memdev=ram-node0 \
-object memory-ram,size=1024M,policy=interleave,host-nodes=1-3,id=ram-node1 \
-numa node,nodeid=1,cpus=1,memdev=ram-node1
The option replaces "-numa node,mem=".
Signed-off-by: Paolo Bonzini
---
include/sysemu/sysemu.h | 1 +
numa.c | 63 +++--
qapi-schema.json| 8 ++-
qemu-options.hx | 12 ++
4 files changed, 77 insertions(+), 7 deletions(-)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 54a6f28..4870129 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -139,6 +139,7 @@ extern int nb_numa_nodes;
typedef struct node_info {
uint64_t node_mem;
DECLARE_BITMAP(node_cpu, MAX_CPUMASK_BITS);
+struct HostMemoryBackend *node_memdev;
} NodeInfo;
extern NodeInfo numa_info[MAX_NODES];
void set_numa_nodes(void);
diff --git a/numa.c b/numa.c
index 930f49d..b00ef90 100644
--- a/numa.c
+++ b/numa.c
@@ -32,6 +32,7 @@
#include "qapi/dealloc-visitor.h"
#include "qapi/qmp/qerror.h"
#include "hw/boards.h"
+#include "sysemu/hostmem.h"
QemuOptsList qemu_numa_opts = {
.name = "numa",
@@ -40,6 +41,8 @@ QemuOptsList qemu_numa_opts = {
.desc = { { 0 } } /* validated with OptsVisitor */
};
+static int have_memdevs = -1;
+
bool?
It is three-state and "-1" means "I haven't seen -numa yet". Because of
the nodeid parameter you cannot change "have_memdevs == -1 to for
example "nodenr == 0".
Paolo
Re: [Qemu-devel] [PATCH] virtio-scsi: actually honor sense_size from configuration space
On Thu, 03/06 11:27, Paolo Bonzini wrote:
> We were always truncating the sense size to 96 bytes.
>
> Signed-off-by: Paolo Bonzini
> ---
> hw/scsi/virtio-scsi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
> index 6610b3a..b0d7517 100644
> --- a/hw/scsi/virtio-scsi.c
> +++ b/hw/scsi/virtio-scsi.c
> @@ -304,6 +304,8 @@ static void virtio_scsi_command_complete(SCSIRequest *r,
> uint32_t status,
> size_t resid)
> {
> VirtIOSCSIReq *req = r->hba_private;
> +VirtIOSCSI *s = req->dev;
> +VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s);
> uint32_t sense_len;
>
> if (r->io_canceled) {
> @@ -317,7 +319,7 @@ static void virtio_scsi_command_complete(SCSIRequest *r,
> uint32_t status,
> } else {
> req->resp.cmd->resid = 0;
> sense_len = scsi_req_get_sense(r, req->resp.cmd->sense,
> - VIRTIO_SCSI_SENSE_SIZE);
> + vs->sense_size);
> req->resp.cmd->sense_len = tswap32(sense_len);
> }
> virtio_scsi_complete_req(req);
Do we need to increase VIRTIO_SCSI_SENSE_SIZE as well?
$ git grep -n VIRTIO_SCSI_SENSE_SIZE
hw/scsi/virtio-scsi.c:463:vs->sense_size = VIRTIO_SCSI_SENSE_SIZE;
hw/scsi/virtio-scsi.c:609:s->sense_size = VIRTIO_SCSI_SENSE_SIZE;
include/hw/virtio/virtio-scsi.h:40:#define VIRTIO_SCSI_SENSE_SIZE 96
Fam
Re: [Qemu-devel] [PATCH 2.1 09/28] vl: redo -object parsing
Il 07/03/2014 03:56, Hu Tao ha scritto:
-obj = object_new(type);
-if (qemu_opt_foreach(opts, object_set_property, obj, 1) < 0) {
-object_unref(obj);
-return -1;
+qdict_del(pdict, "qom-type");
+visit_type_str(opts_get_visitor(ov), &type, "qom-type", &err);
+if (err) {
+goto out;
}
Can be moved up right before creating qdict.
-if (!object_dynamic_cast(obj, TYPE_USER_CREATABLE)) {
-error_setg(&local_err, "object '%s' isn't supported by -object",
- id);
+qdict_del(pdict, "id");
+visit_type_str(opts_get_visitor(ov), &id, "id", &err);
+if (err) {
goto out;
}
Can be moved up right before creating qdict.
In both cases I prefer to keep the qdict_del and visit_type_str together.
-user_creatable_complete(obj, &local_err);
-if (local_err) {
+object_add(type, id, pdict, opts_get_visitor(ov), &err);
I think it's better to move object_add() from qmp.c to qom/object.c.
No, I don't think so. qom/object.c is not using QDict. It is common
for "human user interface" files (hmp.c, ui/gtk.c, in this case vl.c) to
use qmp.c, the structure should be
hmp.c, ui/gtk.c, vl.c
|
qmp.c
|
qom/, cpus.c, etc.
We could move parts of qmp.c to qom/qmp.c, that would be fine.
Paolo
+if (err) {
goto out;
}
-
-object_property_add_child(container_get(object_get_root(), "/objects"),
- id, obj, &local_err);
+visit_end_struct(opts_get_visitor(ov), &err);
+if (err) {
+qmp_object_del(id, NULL);
+}
out:
-object_unref(obj);
-if (local_err) {
-qerror_report_err(local_err);
-error_free(local_err);
-return -1;
+opts_visitor_cleanup(ov);
+
+QDECREF(pdict);
+g_free(id);
+g_free(type);
+g_free(dummy);
+if (err) {
+qerror_report_err(err);
}
return 0;
}
--
1.8.5.3
Re: [Qemu-devel] pcie
Il 07/03/2014 04:31, Serge Hallyn ha scritto: Hi, At https://bugs.launchpad.net/bugs/1284793 it was found that commit a66e657e: "pci/pcie: convert PCIE hotplug to use hotplug-handler API" seems to break vga passthrough. Reverting that commit (plus one more to reintroduce a needed definition) fixed it. Do you have any idea what would have broken vga passthrough, and how to fix it without completely reverting that commit? The fix will be in the next pull request from Michael Tsirkin: http://permalink.gmane.org/gmane.comp.emulators.qemu/259366 Paolo
Re: [Qemu-devel] [PATCH] build: Fix installation of target-dependent files
Il 07/03/2014 02:19, Lluís Vilanova ha scritto: Lluís Vilanova writes: Lluís Vilanova writes: Pass all the relevant sub-directory make variables. Ping. Ping^2 Thanks, Lluis Signed-off-by: Lluís Vilanova --- Makefile |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index bdff4e4..02ae76d 100644 --- a/Makefile +++ b/Makefile @@ -366,7 +366,7 @@ endif $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x "$(DESTDIR)$(qemu_datadir)/keymaps"; \ done for d in $(TARGET_DIRS); do \ - $(MAKE) -C $$d $@ || exit 1 ; \ + $(MAKE) $(SUBDIR_MAKEFLAGS) TARGET_DIR=$$d/ -C $$d $@ || exit 1 ; \ done # various test targets Reviewed-by: Paolo Bonzini Paolo
Re: [Qemu-devel] [PULL 007/130] KVM: Split QEMUMachine typedef into separate header
Il 07/03/2014 00:32, Alexander Graf ha scritto:
Older gcc versions (such as the one in SLES11) get confused when you declare
a typedef on the same struct twice.
To work around that limitation, let's extract the QEMUMachine typedef into a
separate header file that is guarded by preprocessor duplicate include checks.
This fixes the following type of compile errors for me:
In file included from vl.c:125:
include/hw/xen/xen.h:39: error: redefinition of typedef "QEMUMachine"
include/sysemu/kvm.h:155: error: previous declaration of "QEMUMachine" was
here
Signed-off-by: Alexander Graf
When was this posted to the list?
This is exactly the purpose of include/qemu/typedefs.h.
Paolo
---
include/hw/boards.h | 3 +--
include/hw/xen/xen.h | 1 +
include/sysemu/kvm.h | 1 +
include/sysemu/qemumachine.h | 16
include/sysemu/qtest.h | 1 +
kvm-stub.c | 1 +
6 files changed, 21 insertions(+), 2 deletions(-)
create mode 100644 include/sysemu/qemumachine.h
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 2151460..ed6d9f8 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -4,10 +4,9 @@
#define HW_BOARDS_H
#include "sysemu/blockdev.h"
+#include "sysemu/qemumachine.h"
#include "hw/qdev.h"
-typedef struct QEMUMachine QEMUMachine;
-
typedef struct QEMUMachineInitArgs {
const QEMUMachine *machine;
ram_addr_t ram_size;
diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h
index e1f88bf..81e5bb1 100644
--- a/include/hw/xen/xen.h
+++ b/include/hw/xen/xen.h
@@ -10,6 +10,7 @@
#include "hw/irq.h"
#include "qemu-common.h"
+#include "sysemu/qemumachine.h"
/* xen-machine.c */
enum xen_mode {
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index a02d67c..c982570 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -18,6 +18,7 @@
#include "config-host.h"
#include "qemu/queue.h"
#include "qom/cpu.h"
+#include "sysemu/qemumachine.h"
#ifdef CONFIG_KVM
#include
diff --git a/include/sysemu/qemumachine.h b/include/sysemu/qemumachine.h
new file mode 100644
index 000..4cefd56
--- /dev/null
+++ b/include/sysemu/qemumachine.h
@@ -0,0 +1,16 @@
+/*
+ * QEMU Machine typedef
+ *
+ * Copyright Alexander Graf
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef QEMUMACHINE_H
+#define QEMUMACHINE_H
+
+typedef struct QEMUMachine QEMUMachine;
+
+#endif /* !QEMUMACHINE_H */
diff --git a/include/sysemu/qtest.h b/include/sysemu/qtest.h
index 28f4875..d6434cd 100644
--- a/include/sysemu/qtest.h
+++ b/include/sysemu/qtest.h
@@ -16,6 +16,7 @@
#include "qemu-common.h"
#include "qapi/error.h"
+#include "sysemu/qemumachine.h"
extern bool qtest_allowed;
diff --git a/kvm-stub.c b/kvm-stub.c
index e979f76..b1c4429 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -14,6 +14,7 @@
#include "hw/hw.h"
#include "cpu.h"
#include "sysemu/kvm.h"
+#include "sysemu/qemumachine.h"
#ifndef CONFIG_USER_ONLY
#include "hw/pci/msi.h"
Re: [Qemu-devel] [PATCH 2.1 22/28] hostmem: separate allocation from UserCreatable complete method
On Tue, Mar 04, 2014 at 03:00:50PM +0100, Paolo Bonzini wrote:
> This allows the superclass to set various policies on the memory
> region that the subclass creates.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Paolo Bonzini
> ---
> backends/hostmem-file.c | 9 -
> backends/hostmem-ram.c | 8 +++-
> backends/hostmem.c | 12 ++--
> include/sysemu/hostmem.h | 2 ++
> 4 files changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
> index 8c6ea5d..7e91665 100644
> --- a/backends/hostmem-file.c
> +++ b/backends/hostmem-file.c
> @@ -30,10 +30,9 @@ struct HostMemoryBackendFile {
> };
>
> static void
> -file_backend_memory_init(UserCreatable *uc, Error **errp)
> +file_backend_memory_alloc(HostMemoryBackend *backend, Error **errp)
> {
> -HostMemoryBackend *backend = MEMORY_BACKEND(uc);
> -HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(uc);
> +HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(backend);
>
> if (!backend->size) {
> error_setg(errp, "can't create backend with size 0");
> @@ -58,9 +57,9 @@ file_backend_memory_init(UserCreatable *uc, Error **errp)
> static void
> file_backend_class_init(ObjectClass *oc, void *data)
> {
> -UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
> +HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc);
>
> -ucc->complete = file_backend_memory_init;
> +bc->alloc = file_backend_memory_alloc;
> }
>
> static char *get_mem_path(Object *o, Error **errp)
> diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c
> index ce06fbe..e4d244a 100644
> --- a/backends/hostmem-ram.c
> +++ b/backends/hostmem-ram.c
> @@ -16,10 +16,8 @@
>
>
> static void
> -ram_backend_memory_init(UserCreatable *uc, Error **errp)
> +ram_backend_memory_alloc(HostMemoryBackend *backend, Error **errp)
> {
> -HostMemoryBackend *backend = MEMORY_BACKEND(uc);
> -
> if (!backend->size) {
> error_setg(errp, "can't create backend with size 0");
> return;
> @@ -33,9 +31,9 @@ ram_backend_memory_init(UserCreatable *uc, Error **errp)
> static void
> ram_backend_class_init(ObjectClass *oc, void *data)
> {
> -UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
> +HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc);
>
> -ucc->complete = ram_backend_memory_init;
> +bc->alloc = ram_backend_memory_alloc;
> }
>
> static const TypeInfo ram_backend_info = {
> diff --git a/backends/hostmem.c b/backends/hostmem.c
> index 06817dd..7d6199f 100644
> --- a/backends/hostmem.c
> +++ b/backends/hostmem.c
> @@ -69,8 +69,16 @@ static void host_memory_backend_finalize(Object *obj)
> static void
> host_memory_backend_memory_init(UserCreatable *uc, Error **errp)
> {
> -error_setg(errp, "memory_init is not implemented for type [%s]",
> - object_get_typename(OBJECT(uc)));
> +HostMemoryBackend *backend = MEMORY_BACKEND(uc);
> +HostMemoryBackendClass *bc = MEMORY_BACKEND_GET_CLASS(uc);
> +
> +if (!bc->alloc) {
> +error_setg(errp, "memory_init is not implemented for type [%s]",
s/memory_init/memory_alloc/ ?
> + object_get_typename(OBJECT(uc)));
> +return;
> +}
> +
> +bc->alloc(backend, errp);
> }
>
> MemoryRegion *
> diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h
> index bc3ffb3..4738107 100644
> --- a/include/sysemu/hostmem.h
> +++ b/include/sysemu/hostmem.h
> @@ -34,6 +34,8 @@ typedef struct HostMemoryBackendClass
> HostMemoryBackendClass;
> */
> struct HostMemoryBackendClass {
> ObjectClass parent_class;
> +
> +void (*alloc)(HostMemoryBackend *backend, Error **errp);
> };
>
> /**
> --
> 1.8.5.3
>
[Qemu-devel] [PATCH V3] virtio-net: calculate proper msix vectors on init
Currently, the default msix vectors for virtio-net-pci is 3 which is
obvious not suitable for multiqueue guest, so we depends on the user
or management tools to pass a correct vectors parameter. In fact, we
can simplifying this by calculate the number of vectors on init.
Consider we have N queues, the number of vectors needed is 2*N + 2
(plus one config interrupt and control vq). We didn't check whether or
not host support control vq because it was added unconditionally by
qemu to avoid breaking legacy guests such as Minix.
Cc: Paolo Bonzini
Cc: Michael S. Tsirkin
Signed-off-by: Jason Wang
---
Changes from V2:
- add compat flag to avoid breaking the migration
Changes from V1:
- remove the debug line
---
hw/virtio/virtio-pci.c | 8 +++-
include/hw/i386/pc.h | 5 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 7b91841..3b3b0e2 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1416,7 +1416,8 @@ static const TypeInfo virtio_serial_pci_info = {
static Property virtio_net_properties[] = {
DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false),
-DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
+DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
+ DEV_NVECTORS_UNSPECIFIED),
DEFINE_VIRTIO_NET_FEATURES(VirtIOPCIProxy, host_features),
DEFINE_NIC_PROPERTIES(VirtIONetPCI, vdev.nic_conf),
DEFINE_VIRTIO_NET_PROPERTIES(VirtIONetPCI, vdev.net_conf),
@@ -1428,6 +1429,11 @@ static int virtio_net_pci_init(VirtIOPCIProxy *vpci_dev)
DeviceState *qdev = DEVICE(vpci_dev);
VirtIONetPCI *dev = VIRTIO_NET_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
+VirtIONet *net = VIRTIO_NET(&dev->vdev);
+
+if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
+vpci_dev->nvectors = 2 * MAX(net->nic_conf.queues, 1) + 2;
+}
virtio_net_set_config_size(&dev->vdev, vpci_dev->host_features);
virtio_net_set_netclient_name(&dev->vdev, qdev->id,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9010246..ea71d1c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -270,6 +270,11 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
.driver = "PIIX4_PM",\
.property = "acpi-pci-hotplug-with-bridge-support",\
.value= "off",\
+},\
+{\
+.driver = "virtio-net-pci", \
+.property = "vectors",\
+.value= stringify(3),\
}
#define PC_COMPAT_1_6 \
--
1.8.3.2
Re: [Qemu-devel] [PATCH 2.1 21/28] hostmem: add file-based HostMemoryBackend
On Tue, Mar 04, 2014 at 03:00:49PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> backends/Makefile.objs | 1 +
> backends/hostmem-file.c | 108
>
> 2 files changed, 109 insertions(+)
> create mode 100644 backends/hostmem-file.c
>
> diff --git a/backends/Makefile.objs b/backends/Makefile.objs
> index e6bdc11..509e4a3 100644
> --- a/backends/Makefile.objs
> +++ b/backends/Makefile.objs
> @@ -8,3 +8,4 @@ $(obj)/baum.o: QEMU_CFLAGS += $(SDL_CFLAGS)
> common-obj-$(CONFIG_TPM) += tpm.o
>
> common-obj-y += hostmem.o hostmem-ram.o
> +common-obj-$(CONFIG_LINUX) += hostmem-file.o
> diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
> new file mode 100644
> index 000..8c6ea5d
> --- /dev/null
> +++ b/backends/hostmem-file.c
> @@ -0,0 +1,108 @@
> +/*
> + * QEMU Host Memory Backend for hugetlbfs
> + *
> + * Copyright (C) 2013 Red Hat Inc
> + *
> + * Authors:
> + * Paolo Bonzini
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#include "sysemu/hostmem.h"
> +#include "qom/object_interfaces.h"
> +
> +/* hostmem-file.c */
> +/**
> + * @TYPE_MEMORY_BACKEND_FILE:
> + * name of backend that uses mmap on a file descriptor
> + */
> +#define TYPE_MEMORY_BACKEND_FILE "memory-file"
> +
> +#define MEMORY_BACKEND_FILE(obj) \
> +OBJECT_CHECK(HostMemoryBackendFile, (obj), TYPE_MEMORY_BACKEND_FILE)
> +
> +typedef struct HostMemoryBackendFile HostMemoryBackendFile;
> +
> +struct HostMemoryBackendFile {
> +HostMemoryBackend parent_obj;
> +char *mem_path;
> +};
> +
> +static void
> +file_backend_memory_init(UserCreatable *uc, Error **errp)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(uc);
> +HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(uc);
> +
> +if (!backend->size) {
> +error_setg(errp, "can't create backend with size 0");
> +return;
> +}
> +if (!fb->mem_path) {
> +error_setg(errp, "mem-path property not set");
> +return;
> +}
> +#ifndef CONFIG_LINUX
> +error_setg(errp, "-mem-path not supported on this host");
> +#else
> +if (!memory_region_size(&backend->mr)) {
> +memory_region_init_ram_from_file(&backend->mr, OBJECT(backend),
> +
> object_get_canonical_path(OBJECT(backend)),
> + backend->size,
> + fb->mem_path, errp);
> +}
> +#endif
> +}
> +
> +static void
> +file_backend_class_init(ObjectClass *oc, void *data)
> +{
> +UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
> +
> +ucc->complete = file_backend_memory_init;
> +}
> +
> +static char *get_mem_path(Object *o, Error **errp)
> +{
> +HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(o);
> +
> +return g_strdup(fb->mem_path);
> +}
> +
> +static void set_mem_path(Object *o, const char *str, Error **errp)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(o);
> +HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(o);
> +
> +if (memory_region_size(&backend->mr)) {
> +error_setg(errp, "cannot change property value");
It's ambiguous that doesn't explain why the property value can't be
changed.
> +return;
> +}
> +if (fb->mem_path) {
> +g_free(fb->mem_path);
> +}
> +fb->mem_path = g_strdup(str);
> +}
> +
> +static void
> +file_backend_instance_init(Object *o)
> +{
> +object_property_add_str(o, "mem-path", get_mem_path,
> +set_mem_path, NULL);
> +}
> +
> +static const TypeInfo file_backend_info = {
> +.name = TYPE_MEMORY_BACKEND_FILE,
> +.parent = TYPE_MEMORY_BACKEND,
> +.class_init = file_backend_class_init,
> +.instance_init = file_backend_instance_init,
> +.instance_size = sizeof(HostMemoryBackendFile),
> +};
> +
> +static void register_types(void)
> +{
> +type_register_static(&file_backend_info);
> +}
> +
> +type_init(register_types);
> --
> 1.8.5.3
>
Re: [Qemu-devel] [PATCH 2.1 16/28] memory: reorganize file-based allocation
On Fri, Mar 07, 2014 at 02:09:25PM +0800, Hu Tao wrote:
> On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
> > Split the internal interface in exec.c to a separate function, and
> > push the check on mem_path up to memory_region_init_ram.
> >
> > Signed-off-by: Paolo Bonzini
> > ---
> > exec.c | 105
> > +---
> > include/exec/cpu-all.h | 3 --
> > include/exec/ram_addr.h | 2 +
> > include/sysemu/sysemu.h | 2 +
> > memory.c| 7 +++-
> > 5 files changed, 73 insertions(+), 46 deletions(-)
> >
> > diff --git a/exec.c b/exec.c
> > index b69fd29..0aa4947 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -1240,56 +1240,30 @@ static int memory_try_enable_merging(void *addr,
> > size_t len)
> > return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
> > }
> >
> > -ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
> > - MemoryRegion *mr)
> > +static ram_addr_t ram_block_add(RAMBlock *new_block)
> > {
> > -RAMBlock *block, *new_block;
> > +RAMBlock *block;
> > ram_addr_t old_ram_size, new_ram_size;
> >
> > old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
> >
> > -size = TARGET_PAGE_ALIGN(size);
> > -new_block = g_malloc0(sizeof(*new_block));
> > -new_block->fd = -1;
> > -
> > /* This assumes the iothread lock is taken here too. */
> > qemu_mutex_lock_ramlist();
> > -new_block->mr = mr;
> > -new_block->offset = find_ram_offset(size);
> > -if (host) {
> > -new_block->host = host;
> > -new_block->flags |= RAM_PREALLOC_MASK;
> > -} else if (xen_enabled()) {
> > -if (mem_path) {
> > -fprintf(stderr, "-mem-path not supported with Xen\n");
> > -exit(1);
> > -}
> > -xen_ram_alloc(new_block->offset, size, mr);
> > -} else {
> > -if (mem_path) {
> > -if (phys_mem_alloc != qemu_anon_ram_alloc) {
> > -/*
> > - * file_ram_alloc() needs to allocate just like
> > - * phys_mem_alloc, but we haven't bothered to provide
> > - * a hook there.
> > - */
> > -fprintf(stderr,
> > -"-mem-path not supported with this accelerator\n");
> > -exit(1);
> > -}
> > -new_block->host = file_ram_alloc(new_block, size, mem_path);
> > -}
> > -if (!new_block->host) {
> > -new_block->host = phys_mem_alloc(size);
> > +new_block->offset = find_ram_offset(new_block->length);
> > +
> > +if (!new_block->host) {
> > +if (xen_enabled()) {
> > +xen_ram_alloc(new_block->offset, new_block->length,
> > new_block->mr);
> > +} else {
> > +new_block->host = phys_mem_alloc(new_block->length);
> > if (!new_block->host) {
> > fprintf(stderr, "Cannot set up guest memory '%s': %s\n",
> > new_block->mr->name, strerror(errno));
> > exit(1);
> > }
> > -memory_try_enable_merging(new_block->host, size);
> > +memory_try_enable_merging(new_block->host, new_block->length);
> > }
> > }
> > -new_block->length = size;
> >
> > /* Keep the list sorted from biggest to smallest block. */
> > QTAILQ_FOREACH(block, &ram_list.blocks, next) {
> > @@ -1317,18 +1291,65 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size,
> > void *host,
> > old_ram_size, new_ram_size);
> > }
> > }
> > -cpu_physical_memory_set_dirty_range(new_block->offset, size);
> > +cpu_physical_memory_set_dirty_range(new_block->offset,
> > new_block->length);
> >
> > -qemu_ram_setup_dump(new_block->host, size);
> > -qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE);
> > -qemu_madvise(new_block->host, size, QEMU_MADV_DONTFORK);
> > +qemu_ram_setup_dump(new_block->host, new_block->length);
> > +qemu_madvise(new_block->host, new_block->length, QEMU_MADV_HUGEPAGE);
> > +qemu_madvise(new_block->host, new_block->length, QEMU_MADV_DONTFORK);
> >
> > -if (kvm_enabled())
> > -kvm_setup_guest_memory(new_block->host, size);
> > +if (kvm_enabled()) {
> > +kvm_setup_guest_memory(new_block->host, new_block->length);
> > +}
> >
> > return new_block->offset;
> > }
> >
> > +ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
> > +const char *mem_path)
> > +{
> > +RAMBlock *new_block;
> > +
> > +if (xen_enabled()) {
> > +fprintf(stderr, "-mem-path not supported with Xen\n");
> > +exit(1);
> > +}
> > +
> > +if (phys_mem_alloc != qemu_anon_ram_alloc) {
> > +/*
> > + * file_ram_alloc() needs to allocate just like
> > + * phys_me
Re: [Qemu-devel] [PATCH v4 2/2] query-command-line-options: query all the options in qemu-options.hx
On Thu, Mar 06, 2014 at 02:23:15PM -0700, Eric Blake wrote: > On 03/05/2014 07:36 PM, Amos Kong wrote: > > vm_config_groups[] only contains part of the options which have > > argument, and all options which have no argument aren't added > > to vm_config_groups[]. Current query-command-line-options only > > checks options from vm_config_groups[], so some options will > > be lost. > > > > We have macro in qemu-options.hx to generate a table that > > contains all the options. This patch tries to query options > > from the table. > > > > Then we won't lose the legacy options that weren't added to > > vm_config_groups[] (eg: -vnc, -smbios). The options that have > > no argument will also be returned (eg: -enable-fips) > > > > Some options that have argument have a NULL desc list, some > > options don't have argument, and "parameters" is mandatory > > in the past. So we add a new field "argument" to present > > if the option takes unspecified arguments. > > I like Markus' suggestion of naming the new field > 'unspecified-parameters' rather than 'argument'. > > > > > This patch also fixes options to match their actual command-line > > spelling rather than an alternate name associated with the > > option table in use by the command. > > Should we independently patch hw/acpi/core.c to rename qemu_acpi_opts > from "acpi" to "acpitable" to match the command line option? Same for > vl.c and qemu_boot_opts from "boot-opts" to "boot"? Same for vl.c and > qemu_smp_opts from "smp-opts" to "smp"? Yes, we should. > Those were the obvious > mismatches I found where the command line was spelled differently than > the vm_config_groups entry. > > This is a bug fix patch, so let's shoot to get it into 2.0. > > > > > Signed-off-by: Amos Kong > > --- > > qapi-schema.json | 8 ++-- > > qemu-options.h | 10 ++ > > util/qemu-config.c | 44 ++-- > > vl.c | 15 --- > > 4 files changed, 54 insertions(+), 23 deletions(-) > > > > > +++ b/util/qemu-config.c > > @@ -6,6 +6,16 @@ > > #include "hw/qdev.h" > > #include "qapi/error.h" > > #include "qmp-commands.h" > > +#include "qemu-options.h" > > + > > +#define HAS_ARG 0x0001 > > Hmm, we are now duplicating this macro between here and vl.c. I'd > prefer it gets hoisted into the .h file, so that it doesn't get out of > sync between the two clients. > > -- > Eric Blake eblake redhat com+1-919-301-3266 > Libvirt virtualization library http://libvirt.org > -- Amos. pgpwCuWD7_I9C.pgp Description: PGP signature
Re: [Qemu-devel] [PATCH 2.1 16/28] memory: reorganize file-based allocation
On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
> Split the internal interface in exec.c to a separate function, and
> push the check on mem_path up to memory_region_init_ram.
>
> Signed-off-by: Paolo Bonzini
> ---
> exec.c | 105
> +---
> include/exec/cpu-all.h | 3 --
> include/exec/ram_addr.h | 2 +
> include/sysemu/sysemu.h | 2 +
> memory.c| 7 +++-
> 5 files changed, 73 insertions(+), 46 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index b69fd29..0aa4947 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1240,56 +1240,30 @@ static int memory_try_enable_merging(void *addr,
> size_t len)
> return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
> }
>
> -ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
> - MemoryRegion *mr)
> +static ram_addr_t ram_block_add(RAMBlock *new_block)
> {
> -RAMBlock *block, *new_block;
> +RAMBlock *block;
> ram_addr_t old_ram_size, new_ram_size;
>
> old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
>
> -size = TARGET_PAGE_ALIGN(size);
> -new_block = g_malloc0(sizeof(*new_block));
> -new_block->fd = -1;
> -
> /* This assumes the iothread lock is taken here too. */
> qemu_mutex_lock_ramlist();
> -new_block->mr = mr;
> -new_block->offset = find_ram_offset(size);
> -if (host) {
> -new_block->host = host;
> -new_block->flags |= RAM_PREALLOC_MASK;
> -} else if (xen_enabled()) {
> -if (mem_path) {
> -fprintf(stderr, "-mem-path not supported with Xen\n");
> -exit(1);
> -}
> -xen_ram_alloc(new_block->offset, size, mr);
> -} else {
> -if (mem_path) {
> -if (phys_mem_alloc != qemu_anon_ram_alloc) {
> -/*
> - * file_ram_alloc() needs to allocate just like
> - * phys_mem_alloc, but we haven't bothered to provide
> - * a hook there.
> - */
> -fprintf(stderr,
> -"-mem-path not supported with this accelerator\n");
> -exit(1);
> -}
> -new_block->host = file_ram_alloc(new_block, size, mem_path);
> -}
> -if (!new_block->host) {
> -new_block->host = phys_mem_alloc(size);
> +new_block->offset = find_ram_offset(new_block->length);
> +
> +if (!new_block->host) {
> +if (xen_enabled()) {
> +xen_ram_alloc(new_block->offset, new_block->length,
> new_block->mr);
> +} else {
> +new_block->host = phys_mem_alloc(new_block->length);
> if (!new_block->host) {
> fprintf(stderr, "Cannot set up guest memory '%s': %s\n",
> new_block->mr->name, strerror(errno));
> exit(1);
> }
> -memory_try_enable_merging(new_block->host, size);
> +memory_try_enable_merging(new_block->host, new_block->length);
> }
> }
> -new_block->length = size;
>
> /* Keep the list sorted from biggest to smallest block. */
> QTAILQ_FOREACH(block, &ram_list.blocks, next) {
> @@ -1317,18 +1291,65 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size,
> void *host,
> old_ram_size, new_ram_size);
> }
> }
> -cpu_physical_memory_set_dirty_range(new_block->offset, size);
> +cpu_physical_memory_set_dirty_range(new_block->offset,
> new_block->length);
>
> -qemu_ram_setup_dump(new_block->host, size);
> -qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE);
> -qemu_madvise(new_block->host, size, QEMU_MADV_DONTFORK);
> +qemu_ram_setup_dump(new_block->host, new_block->length);
> +qemu_madvise(new_block->host, new_block->length, QEMU_MADV_HUGEPAGE);
> +qemu_madvise(new_block->host, new_block->length, QEMU_MADV_DONTFORK);
>
> -if (kvm_enabled())
> -kvm_setup_guest_memory(new_block->host, size);
> +if (kvm_enabled()) {
> +kvm_setup_guest_memory(new_block->host, new_block->length);
> +}
>
> return new_block->offset;
> }
>
> +ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
> +const char *mem_path)
> +{
> +RAMBlock *new_block;
> +
> +if (xen_enabled()) {
> +fprintf(stderr, "-mem-path not supported with Xen\n");
> +exit(1);
> +}
> +
> +if (phys_mem_alloc != qemu_anon_ram_alloc) {
> +/*
> + * file_ram_alloc() needs to allocate just like
> + * phys_mem_alloc, but we haven't bothered to provide
> + * a hook there.
> + */
> +fprintf(stderr,
> +"-mem-path not supported with this accelerator\n");
> +exit(1);
> +}
> +
> +size = TARGET_PAGE_ALIGN(size);
> +new_block = g_malloc0(sizeof(*new_block));
>
[Qemu-devel] [PATCH v5 2/2] query-command-line-options: query all the options in qemu-options.hx
vm_config_groups[] only contains part of the options which have
parameters, and all options which have no parameter aren't added
to vm_config_groups[]. Current query-command-line-options only
checks options from vm_config_groups[], so some options will
be lost.
We have macro in qemu-options.hx to generate a table that
contains all the options. This patch tries to query options
from the table.
Then we won't lose the legacy options that weren't added to
vm_config_groups[] (eg: -vnc, -smbios). The options that have
no parameter will also be returned (eg: -enable-fips)
Some options that have parameters have a NULL desc list, some
options don't have parameters, and "parameters" is mandatory
in the past. So we add a new field "unspecified-parameters" to
present if the option takes unspecified parameters.
This patch also fixes options to match their actual command-line
spelling rather than an alternate name associated with the
option table in use by the command.
Signed-off-by: Amos Kong
---
qapi-schema.json | 9 +++--
qemu-options.h | 12
util/qemu-config.c | 43 ---
vl.c | 19 ++-
4 files changed, 57 insertions(+), 26 deletions(-)
diff --git a/qapi-schema.json b/qapi-schema.json
index 193e7e4..fb7ca1b 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -4070,12 +4070,17 @@
#
# @option: option name
#
-# @parameters: an array of @CommandLineParameterInfo
+# @parameters: array of @CommandLineParameterInfo, possibly empty
+# @unspecified-parameters: @optional present if the @parameters array is empty.
+# If true, then the option takes unspecified
+# parameters, if false, then the option takes no
+# parameter (since 2.0)
#
# Since 1.5
##
{ 'type': 'CommandLineOptionInfo',
- 'data': { 'option': 'str', 'parameters': ['CommandLineParameterInfo'] } }
+ 'data': { 'option': 'str', 'parameters': ['CommandLineParameterInfo'],
+'*unspecified-parameters': 'bool' } }
##
# @query-command-line-options:
diff --git a/qemu-options.h b/qemu-options.h
index 89a009e..4024487 100644
--- a/qemu-options.h
+++ b/qemu-options.h
@@ -28,9 +28,21 @@
#ifndef _QEMU_OPTIONS_H_
#define _QEMU_OPTIONS_H_
+#include "sysemu/arch_init.h"
+
enum {
#define QEMU_OPTIONS_GENERATE_ENUM
#include "qemu-options-wrapper.h"
};
+#define HAS_ARG 0x0001
+
+typedef struct QEMUOption {
+const char *name;
+int flags;
+int index;
+uint32_t arch_mask;
+} QEMUOption;
+
+extern const QEMUOption qemu_options[];
#endif
diff --git a/util/qemu-config.c b/util/qemu-config.c
index d2facfd..ea8a419 100644
--- a/util/qemu-config.c
+++ b/util/qemu-config.c
@@ -6,6 +6,14 @@
#include "hw/qdev.h"
#include "qapi/error.h"
#include "qmp-commands.h"
+#include "qemu-options.h"
+
+const QEMUOption qemu_options[] = {
+{ "h", 0, QEMU_OPTION_h, QEMU_ARCH_ALL },
+#define QEMU_OPTIONS_GENERATE_OPTIONS
+#include "qemu-options-wrapper.h"
+{ NULL },
+};
static QemuOptsList *vm_config_groups[32];
static QemuOptsList *drive_config_groups[4];
@@ -78,6 +86,17 @@ static CommandLineParameterInfoList
*get_param_infolist(const QemuOptDesc *desc)
return param_list;
}
+static int get_group_index(const char *name)
+{
+int i;
+
+for (i = 0; vm_config_groups[i] != NULL; i++) {
+if (!strcmp(vm_config_groups[i]->name, name)) {
+return i;
+}
+}
+return -1;
+}
/* remove repeated entry from the info list */
static void cleanup_infolist(CommandLineParameterInfoList *head)
{
@@ -137,17 +156,25 @@ CommandLineOptionInfoList
*qmp_query_command_line_options(bool has_option,
{
CommandLineOptionInfoList *conf_list = NULL, *entry;
CommandLineOptionInfo *info;
-int i;
+int i, idx;
-for (i = 0; vm_config_groups[i] != NULL; i++) {
-if (!has_option || !strcmp(option, vm_config_groups[i]->name)) {
+for (i = 0; qemu_options[i].name; i++) {
+if (!has_option || !strcmp(option, qemu_options[i].name)) {
info = g_malloc0(sizeof(*info));
-info->option = g_strdup(vm_config_groups[i]->name);
-if (!strcmp("drive", vm_config_groups[i]->name)) {
+info->option = g_strdup(qemu_options[i].name);
+
+idx = get_group_index(qemu_options[i].name);
+
+if (!strcmp("drive", qemu_options[i].name)) {
info->parameters = get_drive_infolist();
-} else {
+} else if (idx >= 0) {
info->parameters =
-get_param_infolist(vm_config_groups[i]->desc);
+get_param_infolist(vm_config_groups[idx]->desc);
+}
+
+if (!info->parameters) {
+info->has_unspecified_parameters = true;
+info->unspecified_parameters = qemu_options[i].flags & HAS_ARG;
}
entry = g_malloc0(sizeof(*entry));
[Qemu-devel] [PATCH v5 1/2] qmp: rename query_option_descs() to get_param_infolist()
Signed-off-by: Amos Kong
Reviewed-by: Eric Blake
---
util/qemu-config.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/qemu-config.c b/util/qemu-config.c
index f610101..d2facfd 100644
--- a/util/qemu-config.c
+++ b/util/qemu-config.c
@@ -39,7 +39,7 @@ QemuOptsList *qemu_find_opts(const char *group)
return ret;
}
-static CommandLineParameterInfoList *query_option_descs(const QemuOptDesc
*desc)
+static CommandLineParameterInfoList *get_param_infolist(const QemuOptDesc
*desc)
{
CommandLineParameterInfoList *param_list = NULL, *entry;
CommandLineParameterInfo *info;
@@ -120,9 +120,9 @@ static CommandLineParameterInfoList
*get_drive_infolist(void)
for (i = 0; drive_config_groups[i] != NULL; i++) {
if (!head) {
-head = query_option_descs(drive_config_groups[i]->desc);
+head = get_param_infolist(drive_config_groups[i]->desc);
} else {
-cur = query_option_descs(drive_config_groups[i]->desc);
+cur = get_param_infolist(drive_config_groups[i]->desc);
connect_infolist(head, cur);
}
}
@@ -147,7 +147,7 @@ CommandLineOptionInfoList
*qmp_query_command_line_options(bool has_option,
info->parameters = get_drive_infolist();
} else {
info->parameters =
-query_option_descs(vm_config_groups[i]->desc);
+get_param_infolist(vm_config_groups[i]->desc);
}
entry = g_malloc0(sizeof(*entry));
entry->value = info;
--
1.8.5.3
[Qemu-devel] [PATCH v5 0/2] fix query-command-line-options
This patchset fixed some issues of query-command-line-options: * some new options that haven't argument can't be queried. (eg: -enable-fips) * some legacy options that have argument can't be queried. (eg: -vnc display) More discussion: http://marc.info/?l=qemu-devel&m=139081830416684&w=2 V2: remove duplicate option tables, update schema (eric) V3: fix typo in commitlog and export qemu_options talbe (eric) V4: avoid the duplicate static table (eric) V5: rename new field, other fix (markus) Thanks for your review! Amos Kong (2): qmp: rename query_option_descs() to get_param_infolist() query-command-line-options: query all the options in qemu-options.hx qapi-schema.json | 9 +++-- qemu-options.h | 12 util/qemu-config.c | 49 +++-- vl.c | 19 ++- 4 files changed, 60 insertions(+), 29 deletions(-) -- 1.8.5.3
Re: [Qemu-devel] [PATCH 2.1 15/28] numa: add -numa node, memdev= option
On Tue, Mar 04, 2014 at 03:00:43PM +0100, Paolo Bonzini wrote:
> This option provides the infrastructure for binding guest NUMA nodes
> to host NUMA nodes. For example:
>
> -object memory-ram,size=1024M,policy=membind,host-nodes=0,id=ram-node0 \
> -numa node,nodeid=0,cpus=0,memdev=ram-node0 \
> -object memory-ram,size=1024M,policy=interleave,host-nodes=1-3,id=ram-node1 \
> -numa node,nodeid=1,cpus=1,memdev=ram-node1
>
> The option replaces "-numa node,mem=".
>
> Signed-off-by: Paolo Bonzini
> ---
> include/sysemu/sysemu.h | 1 +
> numa.c | 63
> +++--
> qapi-schema.json| 8 ++-
> qemu-options.hx | 12 ++
> 4 files changed, 77 insertions(+), 7 deletions(-)
>
> diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
> index 54a6f28..4870129 100644
> --- a/include/sysemu/sysemu.h
> +++ b/include/sysemu/sysemu.h
> @@ -139,6 +139,7 @@ extern int nb_numa_nodes;
> typedef struct node_info {
> uint64_t node_mem;
> DECLARE_BITMAP(node_cpu, MAX_CPUMASK_BITS);
> +struct HostMemoryBackend *node_memdev;
> } NodeInfo;
> extern NodeInfo numa_info[MAX_NODES];
> void set_numa_nodes(void);
> diff --git a/numa.c b/numa.c
> index 930f49d..b00ef90 100644
> --- a/numa.c
> +++ b/numa.c
> @@ -32,6 +32,7 @@
> #include "qapi/dealloc-visitor.h"
> #include "qapi/qmp/qerror.h"
> #include "hw/boards.h"
> +#include "sysemu/hostmem.h"
>
> QemuOptsList qemu_numa_opts = {
> .name = "numa",
> @@ -40,6 +41,8 @@ QemuOptsList qemu_numa_opts = {
> .desc = { { 0 } } /* validated with OptsVisitor */
> };
>
> +static int have_memdevs = -1;
> +
bool?
Re: [Qemu-devel] [PATCH v3 3/3] hw/boards: converted current_machine to be an instance of MachineCLass
On Fri, 2014-03-07 at 12:16 +1100, Alexey Kardashevskiy wrote:
> On 03/07/2014 10:44 AM, Andreas Färber wrote:
> > Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> >> In order to allow attaching machine options to a machine instance,
> >> current_machine is converted into MachineState.
> >> As a first step of deprecating QEMUMachine, some of the functions
> >> were modified to return MachineCLass.
> >>
> >> Signed-off-by: Marcel Apfelbaum
> >
> > Looks mostly good, but same issue as Alexey's patch: We are risking
> > qdev_get_machine() creating a Container-typed /machine node.
>
> Sorry, I am not following you here. object_resolve_path() can create objects?
Hi Alexey,
No, object_resolve_path() does not create objects, the point is that the machine
is created before, you only need to get it. You don't want to risk creating
a container.
>
>
> > What about the following on top?
> >
> > Alexey, if we reach agreement here, this means for you that we can just
> > use type_register_static() in place of qemu_machine_register() to
> > register your custom machine type with interface added.
>
> I am perfectly fine with that, I just do not see what difference does it
> make and why do you still keep qemu_machine_register() (or this is in the
> plan already?)?
It is in my plan to eliminate qemu_machine_register(), however it will
take some time as it includes making changes to lots of files.
For the moment, subclassing MachineClass and registering it to QOM
will be exactly like calling qemu_machine_register().
Thanks,
Marcel
>
>
>
> > Regards,
> > Andreas
> >
> > diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> > index b6deebd..749c83a 100644
> > --- a/hw/core/qdev.c
> > +++ b/hw/core/qdev.c
> > @@ -861,7 +861,8 @@ Object *qdev_get_machine(void)
> > static Object *dev;
> >
> > if (dev == NULL) {
> > -dev = container_get(object_get_root(), "/machine");
> > +dev = object_resolve_path("/machine", NULL);
> > +g_assert(dev);
> > }
> >
> > return dev;
> >
> >
>
>
Re: [Qemu-devel] [PATCH v3 3/3] hw/boards: converted current_machine to be an instance of MachineCLass
On Fri, 2014-03-07 at 00:44 +0100, Andreas Färber wrote:
> Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> > In order to allow attaching machine options to a machine instance,
> > current_machine is converted into MachineState.
> > As a first step of deprecating QEMUMachine, some of the functions
> > were modified to return MachineCLass.
> >
> > Signed-off-by: Marcel Apfelbaum
>
> Looks mostly good, but same issue as Alexey's patch: We are risking
> qdev_get_machine() creating a Container-typed /machine node.
>
> What about the following on top?
Hi Andreas,
I checked with the debugger and qdev_get_machine is called
long after we add the machine to the QOM tree.
However, the race still exists as someone can call qdev_get_machine
before the machine is added to the tree, not being aware of that.
Your change solves the problem, thank you!
Do you want me to add this diff and resend,
or I will send yours separately?
Thanks,
Marcel
>
> Alexey, if we reach agreement here, this means for you that we can just
> use type_register_static() in place of qemu_machine_register() to
> register your custom machine type with interface added.
>
> Regards,
> Andreas
>
> diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> index b6deebd..749c83a 100644
> --- a/hw/core/qdev.c
> +++ b/hw/core/qdev.c
> @@ -861,7 +861,8 @@ Object *qdev_get_machine(void)
> static Object *dev;
>
> if (dev == NULL) {
> -dev = container_get(object_get_root(), "/machine");
> +dev = object_resolve_path("/machine", NULL);
> +g_assert(dev);
> }
>
> return dev;
>
>
Re: [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register
Ping
On Fri, Feb 28, 2014 at 9:15 AM, Alistair Francis
wrote:
> This patch implements the ARM PMCCNTR register including
> the disable and reset components of the PMCR register.
>
> Signed-off-by: Alistair Francis
> ---
> V9: Completely #ifndef out the PMCR and PMCCNTR registers. Also use
> CONFIG_USER_ONLY instead of CONFIG_LINUX_USER
> V8: Only implement the register in system mode to make sure it doesn't
> break compilation of linux-user targets.
> V7: Fixed a bug that caused the cycle count scaling to be determined
> by the PMCRDP register instead of PMCRD. Also stopped PMCRDP from
> disabling the counter. Thanks to Peter Maydell
> V6: Rebase to include Peter Maydell's 'Convert performance monitor
> reginfo to accesfn' patch. Remove the raw_fn's as the read/write
> functions already do what is required.
> V5: Implement the actual write function to make sure that
> migration works correctly. Also includes the raw_read/write as
> the normal read/write functions depend on the pmcr register. So
> they don't allow for the pmccntr register to be written first.
> V4: Some bug fixes pointed out by Peter Crosthwaite. Including
> increasing the accuracy of the timer.
> V3: Fixed up incorrect reset, disable and enable handling that
> was submitted in V2. The patch should now also handle changing
> of the clock scaling.
> V2: Incorporated the comments that Peter Maydell and Peter
> Crosthwaite had. Now the implementation only requires one
> CPU state
>
> target-arm/cpu.h|4 ++
> target-arm/helper.c | 89 --
> 2 files changed, 89 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 3c8a2db..14fd1ae 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -215,6 +215,10 @@ typedef struct CPUARMState {
> uint32_t c15_diagnostic; /* diagnostic register */
> uint32_t c15_power_diagnostic;
> uint32_t c15_power_control; /* power control */
> +/* If the counter is enabled, this stores the last time the counter
> + * was reset. Otherwise it stores the counter value
> + */
> +uint32_t c15_ccnt;
> } cp15;
>
> struct {
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b547f04..21d14c9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -11,6 +11,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t
> address,
> int access_type, int is_user,
> hwaddr *phys_ptr, int *prot,
> target_ulong *page_size);
> +
> +/* Definitions for the PMCCNTR and PMCR registers */
> +#define PMCRD 0x8
> +#define PMCRC 0x4
> +#define PMCRE 0x1
> #endif
>
> static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
> @@ -475,13 +480,84 @@ static CPAccessResult pmreg_access(CPUARMState *env,
> const ARMCPRegInfo *ri)
> return CP_ACCESS_OK;
> }
>
> +#ifndef CONFIG_USER_ONLY
> static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> +/* Don't computer the number of ticks in user mode */
> +uint32_t temp_ticks;
> +
> +temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
> + get_ticks_per_sec() / 100;
> +
> +if (env->cp15.c9_pmcr & PMCRE) {
> +/* If the counter is enabled */
> +if (env->cp15.c9_pmcr & PMCRD) {
> +/* Increment once every 64 processor clock cycles */
> +env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
> +} else {
> +env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> +}
> +}
> +
> +if (value & PMCRC) {
> +/* The counter has been reset */
> +env->cp15.c15_ccnt = 0;
> +}
> +
> /* only the DP, X, D and E bits are writable */
> env->cp15.c9_pmcr &= ~0x39;
> env->cp15.c9_pmcr |= (value & 0x39);
> +
> +if (env->cp15.c9_pmcr & PMCRE) {
> +if (env->cp15.c9_pmcr & PMCRD) {
> +/* Increment once every 64 processor clock cycles */
> +temp_ticks /= 64;
> +}
> +env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> +}
> +}
> +
> +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +uint32_t total_ticks;
> +
> +if (!(env->cp15.c9_pmcr & PMCRE)) {
> +/* Counter is disabled, do not change value */
> +return env->cp15.c15_ccnt;
> +}
> +
> +total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
> + get_ticks_per_sec() / 100;
> +
> +if (env->cp15.c9_pmcr & PMCRD) {
> +/* Increment once every 64 processor clock cycles */
> +total_ticks /= 64;
> +}
> +return total_ticks - env->cp15.c15_ccnt;
> +}
> +
> +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +uint64_t value)
> +{
> +uint32_t total_ticks;
> +
> +
[Qemu-devel] [PATCH v4 2/3] spapr-hcall: fix little-endian resource handling in H_SET_MODE
This changes resource code definitions to ones used in the host kernel.
This fixes H_SET_MODE_RESOURCE_LE (switch between big endian and
little endian) to sync registers from KVM before changing LPCR value.
This adds a set_spr() helper to update an SPR in a CPU's context to avoid
possible races and makes use of it to change LPCR.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_hcall.c | 38 ++
include/hw/ppc/spapr.h | 9 +++--
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index d918780..1bf19b2 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -4,6 +4,33 @@
#include "hw/ppc/spapr.h"
#include "mmu-hash64.h"
+struct spr_sync_struct {
+CPUState *cs;
+int spr;
+target_ulong value;
+target_ulong mask;
+};
+
+static void do_spr_sync(void *arg)
+{
+struct spr_sync_struct *s = arg;
+PowerPCCPU *cp = POWERPC_CPU(s->cs);
+CPUPPCState *env = &cp->env;
+
+cpu_synchronize_state(s->cs);
+env->spr[s->spr] &= ~s->mask;
+env->spr[s->spr] |= s->value;
+}
+
+static void set_spr(CPUState *cs, int spr, target_ulong value,
+target_ulong mask)
+{
+struct spr_sync_struct s = {
+.cs = cs, .spr = spr, .value = value, .mask = mask
+};
+run_on_cpu(cs, do_spr_sync, &s);
+}
+
static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
target_ulong pte_index)
{
@@ -690,7 +717,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
target_ulong value2 = args[3];
target_ulong ret = H_P2;
-if (resource == H_SET_MODE_ENDIAN) {
+if (resource == H_SET_MODE_RESOURCE_LE) {
if (value1) {
ret = H_P3;
goto out;
@@ -699,22 +726,17 @@ static target_ulong h_set_mode(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
ret = H_P4;
goto out;
}
-
switch (mflags) {
case H_SET_MODE_ENDIAN_BIG:
CPU_FOREACH(cs) {
-PowerPCCPU *cp = POWERPC_CPU(cs);
-CPUPPCState *env = &cp->env;
-env->spr[SPR_LPCR] &= ~LPCR_ILE;
+set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
}
ret = H_SUCCESS;
break;
case H_SET_MODE_ENDIAN_LITTLE:
CPU_FOREACH(cs) {
-PowerPCCPU *cp = POWERPC_CPU(cs);
-CPUPPCState *env = &cp->env;
-env->spr[SPR_LPCR] |= LPCR_ILE;
+set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
}
ret = H_SUCCESS;
break;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 449fc7c..5fdac1e 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -153,8 +153,13 @@ typedef struct sPAPREnvironment {
#define H_PP1 (1ULL<<(63-62))
#define H_PP2 (1ULL<<(63-63))
-/* H_SET_MODE flags */
-#define H_SET_MODE_ENDIAN4
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR 1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
+#define H_SET_MODE_RESOURCE_LE 4
+
+/* Flags for H_SET_MODE_RESOURCE_LE */
#define H_SET_MODE_ENDIAN_BIG0
#define H_SET_MODE_ENDIAN_LITTLE 1
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 0/3] spapr: fix H_SET_MODE
This fixes H_SET_MODE. Changes: v4: * rebased on top of current ppc-next. * changed PPC2_ISA207S flag value Alexey Kardashevskiy (3): target-ppc: introduce powerisa-207-server flag spapr-hcall: fix little-endian resource handling in H_SET_MODE spapr-hcall: add address-translation-mode-on-interrupt resource in H_SET_MODE hw/ppc/spapr_hcall.c| 64 +++-- include/hw/ppc/spapr.h | 9 +-- target-ppc/cpu.h| 4 +++ target-ppc/translate_init.c | 3 ++- 4 files changed, 69 insertions(+), 11 deletions(-) -- 1.8.4.rc4
[Qemu-devel] [PATCH v4 3/3] spapr-hcall: add address-translation-mode-on-interrupt resource in H_SET_MODE
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_hcall.c | 26 ++
target-ppc/cpu.h | 2 ++
2 files changed, 28 insertions(+)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 1bf19b2..d0e0889 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -744,6 +744,32 @@ static target_ulong h_set_mode(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
default:
ret = H_UNSUPPORTED_FLAG;
}
+} else if (resource == H_SET_MODE_RESOURCE_ADDR_TRANS_MODE) {
+PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
+return H_P2;
+}
+if (value1) {
+ret = H_P3;
+goto out;
+}
+if (value2) {
+ret = H_P4;
+goto out;
+}
+switch (mflags) {
+case 0:
+case 2:
+case 3:
+CPU_FOREACH(cs) {
+set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
+}
+return H_SUCCESS;
+
+default:
+return H_UNSUPPORTED_FLAG;
+}
}
out:
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 27a2cd9..13fa6a3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -462,6 +462,8 @@ struct ppc_slb_t {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
#define LPCR_ILE (1 << (63-38))
+#define LPCR_AIL 0x0180 /* Alternate interrupt location */
+#define LPCR_AIL_SH (63-40)
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 1/3] target-ppc: introduce powerisa-207-server flag
This flag will be used to decide whether to emulate some bits of
H_SET_MODE hypercall because some are POWER8-only.
While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already
have it.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 2 ++
target-ppc/translate_init.c | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index afab267..27a2cd9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1900,6 +1900,8 @@ enum {
PPC2_LSQ_ISA207= 0x2000ULL,
/* ISA 2.07 Altivec */
PPC2_ALTIVEC_207 = 0x4000ULL,
+/* PowerISA 2.07 Book3s specification*/
+PPC2_ISA207S = 0x8000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3eafbb0..9f896eb 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7172,7 +7172,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
-PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207;
+PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+PPC2_ISA205 | PPC2_ISA207S;
pcc->msr_mask = 0x8284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.8.4.rc4
Re: [Qemu-devel] [PATCH] mempath: add option to specify minimum huge page size
On 03/06/2014 05:40 PM, Marcelo Tosatti wrote:
>
> Failing initialization in case hugepage path has
> hugepage smaller than specified.
>
> Signed-off-by: Marcelo Tosatti
>
> diff --git a/exec.c b/exec.c
> index b69fd29..c95a0f3 100644
> --- a/exec.c
> +++ b/exec.c
> };
>
> +static QemuOptsList qemu_mempath_opts = {
> +.name = "mem-path",
> -case QEMU_OPTION_mempath:
> -mem_path = optarg;
> +case QEMU_OPTION_mempath: {
> +opts = qemu_opts_parse(qemu_find_opts("mem-path"), optarg,
> 1);
Pre-existing, but this is yet another inconsistent naming between C
objects and the command line. If we were consistent, it should be named
QEMU_OPTION_mem_path, and qemu_mem_path_options. (See my recent
complaint about other misnamed options:
https://lists.gnu.org/archive/html/qemu-devel/2014-03/msg01131.html)
--
Eric Blake eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org
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Re: [Qemu-devel] [PATCH v4 00/21] AArch64 system emulation (boots a kernel!)
On 03/07/2014 03:32 AM, Peter Maydell wrote: This is v4 of the AArch64 system emulation patches, and it's an important milestone -- this is enough to boot a Linux kernel. Does this boot an aarch64 kernel with tcg on x86 host? -- Thanks, Xuebing Wang
Re: [Qemu-devel] [PATCH v3 0/3] spapr: fix H_SET_MODE
On 02/14/2014 08:30 PM, Alexey Kardashevskiy wrote: > On 02/11/2014 11:16 PM, Alexey Kardashevskiy wrote: >> On 02/11/2014 11:12 PM, Alexander Graf wrote: >>> On 02/11/2014 08:44 AM, Alexey Kardashevskiy wrote: On 01/22/2014 04:43 PM, Alexey Kardashevskiy wrote: > This fixes H_SET_MODE. > > Alexey Kardashevskiy (3): >target-ppc: introduce powerisa-207-server flag >spapr-hcall: fix little-endian resource handling in H_SET_MODE >spapr-hcall: add address-translation-mode-on-interrupt resource in > H_SET_MODE > > hw/ppc/spapr_hcall.c| 64 > +++-- > include/hw/ppc/spapr.h | 9 +-- > target-ppc/cpu.h| 4 +++ > target-ppc/translate_init.c | 3 ++- > 4 files changed, 69 insertions(+), 11 deletions(-) Ping? >>> >>> Why are you pinging? There were review comments on this patch set, no? > > > Have I answered these questions? Or am I still missing some review > comments? Or what? Thanks. > > >> >> >> I saw question from Aneesh (which does not require a change, I believe) and >> that is it. What did I miss? Ping? I really (really) do not understand what comments were meant. Thanks. -- Alexey
Re: [Qemu-devel] [PATCH 2.1 14/28] add memdev backend infrastructure
On Tue, Mar 04, 2014 at 03:00:42PM +0100, Paolo Bonzini wrote:
> From: Igor Mammedov
>
> Provides framework for splitting host RAM allocation/
> policies into a separate backend that could be used
> by devices.
>
> Initially only legacy RAM backend is provided, which
> uses memory_region_init_ram() allocator and compatible
> with every CLI option that affects memory_region_init_ram().
>
> Signed-off-by: Igor Mammedov
> Signed-off-by: Paolo Bonzini
> ---
> backends/Makefile.objs | 2 +
> backends/hostmem-ram.c | 52 ++
> backends/hostmem.c | 110
> +++
> include/sysemu/hostmem.h | 60 ++
> 4 files changed, 224 insertions(+)
> create mode 100644 backends/hostmem-ram.c
> create mode 100644 backends/hostmem.c
> create mode 100644 include/sysemu/hostmem.h
>
> diff --git a/backends/Makefile.objs b/backends/Makefile.objs
> index 42557d5..e6bdc11 100644
> --- a/backends/Makefile.objs
> +++ b/backends/Makefile.objs
> @@ -6,3 +6,5 @@ common-obj-$(CONFIG_BRLAPI) += baum.o
> $(obj)/baum.o: QEMU_CFLAGS += $(SDL_CFLAGS)
>
> common-obj-$(CONFIG_TPM) += tpm.o
> +
> +common-obj-y += hostmem.o hostmem-ram.o
> diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c
> new file mode 100644
> index 000..ce06fbe
> --- /dev/null
> +++ b/backends/hostmem-ram.c
> @@ -0,0 +1,52 @@
> +/*
> + * QEMU Host Memory Backend
> + *
> + * Copyright (C) 2013 Red Hat Inc
> + *
> + * Authors:
> + * Igor Mammedov
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#include "sysemu/hostmem.h"
> +#include "qom/object_interfaces.h"
> +
> +#define TYPE_MEMORY_BACKEND_RAM "memory-ram"
> +
> +
> +static void
> +ram_backend_memory_init(UserCreatable *uc, Error **errp)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(uc);
> +
> +if (!backend->size) {
> +error_setg(errp, "can't create backend with size 0");
> +return;
> +}
> +
> +memory_region_init_ram(&backend->mr, OBJECT(backend),
> + object_get_canonical_path(OBJECT(backend)),
> + backend->size);
> +}
> +
> +static void
> +ram_backend_class_init(ObjectClass *oc, void *data)
> +{
> +UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
> +
> +ucc->complete = ram_backend_memory_init;
> +}
> +
> +static const TypeInfo ram_backend_info = {
> +.name = TYPE_MEMORY_BACKEND_RAM,
> +.parent = TYPE_MEMORY_BACKEND,
> +.class_init = ram_backend_class_init,
> +};
> +
> +static void register_types(void)
> +{
> +type_register_static(&ram_backend_info);
> +}
> +
> +type_init(register_types);
> diff --git a/backends/hostmem.c b/backends/hostmem.c
> new file mode 100644
> index 000..06817dd
> --- /dev/null
> +++ b/backends/hostmem.c
> @@ -0,0 +1,110 @@
> +/*
> + * QEMU Host Memory Backend
> + *
> + * Copyright (C) 2013 Red Hat Inc
> + *
> + * Authors:
> + * Igor Mammedov
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#include "sysemu/hostmem.h"
> +#include "sysemu/sysemu.h"
> +#include "qapi/visitor.h"
> +#include "qapi/qmp/qerror.h"
> +#include "qemu/config-file.h"
> +#include "qom/object_interfaces.h"
> +
> +static void
> +host_memory_backend_get_size(Object *obj, Visitor *v, void *opaque,
> +const char *name, Error **errp)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(obj);
> +uint64_t value = backend->size;
> +
> +visit_type_size(v, &value, name, errp);
> +}
> +
> +static void
> +host_memory_backend_set_size(Object *obj, Visitor *v, void *opaque,
> +const char *name, Error **errp)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(obj);
> +uint64_t value;
> +
> +if (memory_region_size(&backend->mr)) {
> +error_setg(errp, "cannot change property value\n");
> +return;
> +}
> +
> +visit_type_size(v, &value, name, errp);
> +if (error_is_set(errp)) {
> +return;
> +}
> +if (!value) {
> +error_setg(errp, "Property '%s.%s' doesn't take value '%" PRIu64 "'",
> + object_get_typename(obj), name , value);
> +return;
> +}
> +backend->size = value;
> +}
> +
> +static void host_memory_backend_initfn(Object *obj)
> +{
> +object_property_add(obj, "size", "int",
> +host_memory_backend_get_size,
> +host_memory_backend_set_size, NULL, NULL, NULL);
> +}
> +
> +static void host_memory_backend_finalize(Object *obj)
> +{
> +HostMemoryBackend *backend = MEMORY_BACKEND(obj);
> +
> +if (memory_region_size(&backend->mr)) {
> +memory_region_destroy(&backend->mr);
> +}
> +}
> +
> +static void
> +host_memory_backend_memory_init(UserCreatable *uc, Error **errp)
> +{
[Qemu-devel] pcie
Hi, At https://bugs.launchpad.net/bugs/1284793 it was found that commit a66e657e: "pci/pcie: convert PCIE hotplug to use hotplug-handler API" seems to break vga passthrough. Reverting that commit (plus one more to reintroduce a needed definition) fixed it. Do you have any idea what would have broken vga passthrough, and how to fix it without completely reverting that commit? thanks, -serge
Re: [Qemu-devel] [PATCH 2.1 13/28] numa: introduce memory_region_allocate_system_memory
On Tue, Mar 04, 2014 at 03:00:41PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/i386/pc.c| 4 +---
> include/hw/boards.h | 4
> include/sysemu/sysemu.h | 1 +
> numa.c | 11 +++
> 4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 17d4820..ff078fb 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1165,9 +1165,7 @@ FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
> * with older qemus that used qemu_ram_alloc().
> */
> ram = g_malloc(sizeof(*ram));
> -memory_region_init_ram(ram, NULL, "pc.ram",
> - below_4g_mem_size + above_4g_mem_size);
> -vmstate_register_ram_global(ram);
> +memory_region_allocate_system_memory(ram, NULL, "pc.ram", args);
> *ram_memory = ram;
> ram_below_4g = g_malloc(sizeof(*ram_below_4g));
> memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index 2151460..8b68878 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -48,6 +48,10 @@ struct QEMUMachine {
> const char *hw_version;
> };
>
> +void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
> + const char *name,
> + QEMUMachineInitArgs *args);
> +
> int qemu_register_machine(QEMUMachine *m);
> QEMUMachine *find_default_machine(void);
>
> diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
> index 4c94cf5..54a6f28 100644
> --- a/include/sysemu/sysemu.h
> +++ b/include/sysemu/sysemu.h
> @@ -10,6 +10,7 @@
> #include "qemu/notify.h"
> #include "qemu/main-loop.h"
> #include "qemu/bitmap.h"
> +#include "qom/object.h"
>
> /* vl.c */
>
> diff --git a/numa.c b/numa.c
> index 6563232..930f49d 100644
> --- a/numa.c
> +++ b/numa.c
> @@ -31,6 +31,7 @@
> #include "qapi/opts-visitor.h"
> #include "qapi/dealloc-visitor.h"
> #include "qapi/qmp/qerror.h"
> +#include "hw/boards.h"
>
> QemuOptsList qemu_numa_opts = {
> .name = "numa",
> @@ -191,3 +192,13 @@ void set_numa_modes(void)
> }
> }
> }
> +
> +void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
> + const char *name,
> + QEMUMachineInitArgs *args)
What's needed is only ram_size.
> +{
> +uint64_t ram_size = args->ram_size;
> +
> +memory_region_init_ram(mr, owner, name, ram_size);
> +vmstate_register_ram_global(mr);
> +}
> --
> 1.8.5.3
>
Re: [Qemu-devel] [PATCH 2.1 12/28] pc: pass QEMUMachineInitArgs to pc_memory_init
Reviewed-by: Hu Tao
On Tue, Mar 04, 2014 at 03:00:40PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/i386/pc.c | 11 +--
> hw/i386/pc_piix.c| 8 +++-
> hw/i386/pc_q35.c | 4 +---
> include/hw/i386/pc.h | 7 +++
> 4 files changed, 12 insertions(+), 18 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a464e48..17d4820 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1145,10 +1145,8 @@ void pc_acpi_init(const char *default_dsdt)
> }
> }
>
> -FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> - const char *kernel_filename,
> - const char *kernel_cmdline,
> - const char *initrd_filename,
> +FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
> + MemoryRegion *system_memory,
> ram_addr_t below_4g_mem_size,
> ram_addr_t above_4g_mem_size,
> MemoryRegion *rom_memory,
> @@ -1160,7 +1158,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> MemoryRegion *ram_below_4g, *ram_above_4g;
> FWCfgState *fw_cfg;
>
> -linux_boot = (kernel_filename != NULL);
> +linux_boot = (args->kernel_filename != NULL);
>
> /* Allocate RAM. We allocate it as a single memory region and use
> * aliases to address portions of it, mostly for backwards compatibility
> @@ -1201,7 +1199,8 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> rom_set_fw(fw_cfg);
>
> if (linux_boot) {
> -load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline,
> below_4g_mem_size);
> +load_linux(fw_cfg, args->kernel_filename, args->initrd_filename,
> + args->kernel_cmdline, below_4g_mem_size);
> }
>
> for (i = 0; i < nb_option_roms; i++) {
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index d5dc1ef..96adc01 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -151,11 +151,9 @@ static void pc_init1(QEMUMachineInitArgs *args,
>
> /* allocate ram and load rom/bios */
> if (!xen_enabled()) {
> -fw_cfg = pc_memory_init(system_memory,
> - args->kernel_filename, args->kernel_cmdline,
> - args->initrd_filename,
> - below_4g_mem_size, above_4g_mem_size,
> - rom_memory, &ram_memory, guest_info);
> +fw_cfg = pc_memory_init(args, system_memory,
> +below_4g_mem_size, above_4g_mem_size,
> +rom_memory, &ram_memory, guest_info);
> }
>
> gsi_state = g_malloc0(sizeof(*gsi_state));
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index a7f6260..95fa01fc 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -138,9 +138,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
>
> /* allocate ram and load rom/bios */
> if (!xen_enabled()) {
> -pc_memory_init(get_system_memory(),
> - args->kernel_filename, args->kernel_cmdline,
> - args->initrd_filename,
> +pc_memory_init(args, get_system_memory(),
> below_4g_mem_size, above_4g_mem_size,
> rom_memory, &ram_memory, guest_info);
> }
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 9010246..8fc0527 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -3,6 +3,7 @@
>
> #include "qemu-common.h"
> #include "exec/memory.h"
> +#include "hw/boards.h"
> #include "hw/isa/isa.h"
> #include "hw/block/fdc.h"
> #include "net/net.h"
> @@ -134,10 +135,8 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
> below_4g_mem_size,
> void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
> MemoryRegion *pci_address_space);
>
> -FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> - const char *kernel_filename,
> - const char *kernel_cmdline,
> - const char *initrd_filename,
> +FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
> + MemoryRegion *system_memory,
> ram_addr_t below_4g_mem_size,
> ram_addr_t above_4g_mem_size,
> MemoryRegion *rom_memory,
> --
> 1.8.5.3
>
Re: [Qemu-devel] [PATCH 2.1 11/28] qmp: improve error reporting for -object and object-add
On Tue, Mar 04, 2014 at 03:00:39PM +0100, Paolo Bonzini wrote:
> Use QERR_INVALID_PARAMETER_VALUE for consistency, and avoid an assertion
> failure if the class name is incorrect.
>
> Signed-off-by: Paolo Bonzini
> ---
> qmp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/qmp.c b/qmp.c
> index 2ff943d..a3b0b73 100644
> --- a/qmp.c
> +++ b/qmp.c
> @@ -541,7 +541,8 @@ void object_add(const char *type, const char *id, const
> QDict *qdict,
> Error *local_err = NULL;
>
> if (!object_class_by_name(type)) {
> -error_setg(errp, "invalid class name");
> +error_set(errp, QERR_INVALID_PARAMETER_VALUE,
> + "qom-type", "a valid class name");
> return;
> }
>
> @@ -556,8 +557,8 @@ void object_add(const char *type, const char *id, const
> QDict *qdict,
> }
>
> if (!object_dynamic_cast(obj, TYPE_USER_CREATABLE)) {
> -error_setg(&local_err, "object '%s' isn't supported by object-add",
> - id);
> +error_setg(&local_err, "class '%s' isn't supported by object-add",
> + type);
> goto out;
> }
There is already an accepted version de580dafade551.
Paolo, I found that your numa tree is behind current master about 99
commits. I'd like to take over this series if you have no time on it.
Re: [Qemu-devel] [PATCH 2.1 09/28] vl: redo -object parsing
On Tue, Mar 04, 2014 at 03:00:37PM +0100, Paolo Bonzini wrote:
> Follow the lines of the HMP implementation, using OptsVisitor
> to parse the options. This gives access to OptsVisitor's
> rich parsing of integer lists.
>
> Signed-off-by: Paolo Bonzini
> ---
> vl.c | 87
> +++-
> 1 file changed, 35 insertions(+), 52 deletions(-)
>
> diff --git a/vl.c b/vl.c
> index ac5f425..e8709ee 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -119,8 +119,7 @@ int main(int argc, char **argv)
> #include "qemu/osdep.h"
>
> #include "ui/qemu-spice.h"
> -#include "qapi/string-input-visitor.h"
> -#include "qom/object_interfaces.h"
> +#include "qapi/opts-visitor.h"
>
> #define DEFAULT_RAM_SIZE 128
>
> @@ -2629,69 +2628,53 @@ static void free_and_trace(gpointer mem)
> free(mem);
> }
>
> -static int object_set_property(const char *name, const char *value, void
> *opaque)
> -{
> -Object *obj = OBJECT(opaque);
> -StringInputVisitor *siv;
> -Error *local_err = NULL;
> -
> -if (strcmp(name, "qom-type") == 0 || strcmp(name, "id") == 0) {
> -return 0;
> -}
> -
> -siv = string_input_visitor_new(value);
> -object_property_set(obj, string_input_get_visitor(siv), name,
> &local_err);
> -string_input_visitor_cleanup(siv);
> -
> -if (local_err) {
> -qerror_report_err(local_err);
> -error_free(local_err);
> -return -1;
> -}
> -
> -return 0;
> -}
> -
> static int object_create(QemuOpts *opts, void *opaque)
> {
> -const char *type = qemu_opt_get(opts, "qom-type");
> -const char *id = qemu_opts_id(opts);
> -Error *local_err = NULL;
> -Object *obj;
> -
> -g_assert(type != NULL);
> -
> -if (id == NULL) {
> -qerror_report(QERR_MISSING_PARAMETER, "id");
> -return -1;
> +Error *err = NULL;
> +char *type = NULL;
> +char *id = NULL;
> +void *dummy = NULL;
> +OptsVisitor *ov;
> +QDict *pdict;
> +
> +ov = opts_visitor_new(opts);
> +pdict = qemu_opts_to_qdict(opts, NULL);
> +
> +visit_start_struct(opts_get_visitor(ov), &dummy, NULL, NULL, 0, &err);
> +if (err) {
> +goto out;
> }
>
> -obj = object_new(type);
> -if (qemu_opt_foreach(opts, object_set_property, obj, 1) < 0) {
> -object_unref(obj);
> -return -1;
> +qdict_del(pdict, "qom-type");
> +visit_type_str(opts_get_visitor(ov), &type, "qom-type", &err);
> +if (err) {
> +goto out;
> }
Can be moved up right before creating qdict.
>
> -if (!object_dynamic_cast(obj, TYPE_USER_CREATABLE)) {
> -error_setg(&local_err, "object '%s' isn't supported by -object",
> - id);
> +qdict_del(pdict, "id");
> +visit_type_str(opts_get_visitor(ov), &id, "id", &err);
> +if (err) {
> goto out;
> }
Can be moved up right before creating qdict.
>
> -user_creatable_complete(obj, &local_err);
> -if (local_err) {
> +object_add(type, id, pdict, opts_get_visitor(ov), &err);
I think it's better to move object_add() from qmp.c to qom/object.c.
> +if (err) {
> goto out;
> }
> -
> -object_property_add_child(container_get(object_get_root(), "/objects"),
> - id, obj, &local_err);
> +visit_end_struct(opts_get_visitor(ov), &err);
> +if (err) {
> +qmp_object_del(id, NULL);
> +}
>
> out:
> -object_unref(obj);
> -if (local_err) {
> -qerror_report_err(local_err);
> -error_free(local_err);
> -return -1;
> +opts_visitor_cleanup(ov);
> +
> +QDECREF(pdict);
> +g_free(id);
> +g_free(type);
> +g_free(dummy);
> +if (err) {
> +qerror_report_err(err);
> }
> return 0;
> }
> --
> 1.8.5.3
>
[Qemu-devel] [PULL 002/130] target-ppc: fix LPCR SPR number
From: Alexey Kardashevskiy PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of 316. This fixes the definition of LPCR SPR. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/cpu.h| 2 +- target-ppc/translate_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index bb84767..4369e7c 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1322,12 +1322,12 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_BOOKE_IAC3(0x13A) #define SPR_HSRR1 (0x13B) #define SPR_BOOKE_IAC4(0x13B) -#define SPR_LPCR (0x13C) #define SPR_BOOKE_DAC1(0x13C) #define SPR_LPIDR (0x13D) #define SPR_DABR2 (0x13D) #define SPR_BOOKE_DAC2(0x13D) #define SPR_BOOKE_DVC1(0x13E) +#define SPR_LPCR (0x13E) #define SPR_BOOKE_DVC2(0x13F) #define SPR_BOOKE_TSR (0x150) #define SPR_BOOKE_TCR (0x154) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7bbda13..ed70087 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -2578,8 +2578,8 @@ static void gen_spr_8xx (CPUPPCState *env) * HRMOR => SPR 313 (Power 2.04 hypv) * HSRR0 => SPR 314 (Power 2.04 hypv) * HSRR1 => SPR 315 (Power 2.04 hypv) - * LPCR=> SPR 316 (970) * LPIDR => SPR 317 (970) + * LPCR=> SPR 318 (970) * EPR => SPR 702 (Power 2.04 emb) * perf=> 768-783 (Power 2.04) * perf=> 784-799 (Power 2.04) -- 1.8.1.4
[Qemu-devel] [PULL 060/130] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
From: Tom Musta
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 91 --
1 file changed, 44 insertions(+), 47 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index de7de76..9014134 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3231,8 +3231,8 @@ LARX(lwarx, 4, ld32u);
#if defined(CONFIG_USER_ONLY)
-static void gen_conditional_store (DisasContext *ctx, TCGv EA,
- int reg, int size)
+static void gen_conditional_store(DisasContext *ctx, TCGv EA,
+ int reg, int size)
{
TCGv t0 = tcg_temp_new();
uint32_t save_exception = ctx->exception;
@@ -3246,62 +3246,57 @@ static void gen_conditional_store (DisasContext *ctx,
TCGv EA,
gen_exception(ctx, POWERPC_EXCP_STCX);
ctx->exception = save_exception;
}
-#endif
-
-/* stwcx. */
-static void gen_stwcx_(DisasContext *ctx)
-{
-TCGv t0;
-gen_set_access_type(ctx, ACCESS_RES);
-t0 = tcg_temp_local_new();
-gen_addr_reg_index(ctx, t0);
-gen_check_align(ctx, t0, 0x03);
-#if defined(CONFIG_USER_ONLY)
-gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
#else
-{
-int l1;
+static void gen_conditional_store(DisasContext *ctx, TCGv EA,
+ int reg, int size)
+{
+int l1;
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-l1 = gen_new_label();
-tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
-gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_reserve, -1);
+tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+l1 = gen_new_label();
+tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
+tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
+#if defined(TARGET_PPC64)
+if (size == 8) {
+gen_qemu_st64(ctx, cpu_gpr[reg], EA);
+} else
+#endif
+if (size == 4) {
+gen_qemu_st32(ctx, cpu_gpr[reg], EA);
+} else if (size == 2) {
+gen_qemu_st16(ctx, cpu_gpr[reg], EA);
+} else {
+gen_qemu_st8(ctx, cpu_gpr[reg], EA);
}
+gen_set_label(l1);
+tcg_gen_movi_tl(cpu_reserve, -1);
+}
#endif
-tcg_temp_free(t0);
+
+#define STCX(name, len) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+TCGv t0; \
+gen_set_access_type(ctx, ACCESS_RES); \
+t0 = tcg_temp_local_new();\
+gen_addr_reg_index(ctx, t0); \
+if (len > 1) {\
+gen_check_align(ctx, t0, (len)-1);\
+} \
+gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
+tcg_temp_free(t0);\
}
+STCX(stbcx_, 1);
+STCX(sthcx_, 2);
+STCX(stwcx_, 4);
+
#if defined(TARGET_PPC64)
/* ldarx */
LARX(ldarx, 8, ld64);
/* stdcx. */
-static void gen_stdcx_(DisasContext *ctx)
-{
-TCGv t0;
-gen_set_access_type(ctx, ACCESS_RES);
-t0 = tcg_temp_local_new();
-gen_addr_reg_index(ctx, t0);
-gen_check_align(ctx, t0, 0x07);
-#if defined(CONFIG_USER_ONLY)
-gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
-#else
-{
-int l1;
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-l1 = gen_new_label();
-tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
-gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_reserve, -1);
-}
-#endif
-tcg_temp_free(t0);
-}
+STCX(stdcx_, 8);
#endif /* defined(TARGET_PPC64) */
/* sync */
@@ -9512,6 +9507,8 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x, PPC_RES),
+GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
+GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x, PPC_64B),
--
1.8.1.4
[Qemu-devel] [PULL 031/130] target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions
From: Tom Musta
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h | 4
target-ppc/translate.c | 8
3 files changed, 58 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 128605e..6a428c9 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2384,3 +2384,49 @@ VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define JOFFSET 0
+#else
+#define JOFFSET 1
+#endif
+
+/* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * stp - source type (float32 or float64)
+ * ttp - target type (float32 or float64)
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf)\
+void helper_##op(CPUPPCState *env, uint32_t opcode)\
+{ \
+ppc_vsr_t xt, xb; \
+int i; \
+ \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+ \
+for (i = 0; i < nels; i++) { \
+int j = 2*i + JOFFSET; \
+xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);\
+if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+} \
+if (sfprf) { \
+helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
+&env->fp_status), sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env);\
+}
+
+VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, f64[i], f32[j], 1)
+VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], f64[i], 1)
+VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
+VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 35389c5..dd9518c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -272,6 +272,8 @@ DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -295,6 +297,7 @@ DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HELPER_2(xvcmpeqdp, void, env, i32)
DEF_HELPER_2(xvcmpgedp, void, env, i32)
DEF_HELPER_2(xvcmpgtdp, void, env, i32)
+DEF_HELPER_2(xvcvdpsp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -318,6 +321,7 @@ DEF_HELPER_2(xvminsp, void, env, i32)
DEF_HELPER_2(xvcmpeqsp, void, env, i32)
DEF_HELPER_2(xvcmpgesp, void, env, i32)
DEF_HELPER_2(xvcmpgtsp, void, env, i32)
+DEF_HELPER_2(xvcvspdp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2fae1f3..9344f38 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7325,6 +7325,8 @@ GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7348,6 +7350,7 @@ GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0
[Qemu-devel] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx
From: Tom Musta
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 18ff8f7..2dfdf6c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7112,20 +7112,23 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(tmp);
}
-static void gen_stxsdx(DisasContext *ctx)
-{
-TCGv EA;
-if (unlikely(!ctx->vsx_enabled)) {
-gen_exception(ctx, POWERPC_EXCP_VSXU);
-return;
-}
-gen_set_access_type(ctx, ACCESS_INT);
-EA = tcg_temp_new();
-gen_addr_reg_index(ctx, EA);
-gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
-tcg_temp_free(EA);
+#define VSX_STORE_SCALAR(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+TCGv EA; \
+if (unlikely(!ctx->vsx_enabled)) {\
+gen_exception(ctx, POWERPC_EXCP_VSXU);\
+return; \
+} \
+gen_set_access_type(ctx, ACCESS_INT); \
+EA = tcg_temp_new(); \
+gen_addr_reg_index(ctx, EA); \
+gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
+tcg_temp_free(EA);\
}
+VSX_STORE_SCALAR(stxsdx, st64)
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
--
1.8.1.4
Re: [Qemu-devel] [PATCH v3 3/3] hw/boards: converted current_machine to be an instance of MachineCLass
Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> In order to allow attaching machine options to a machine instance,
> current_machine is converted into MachineState.
> As a first step of deprecating QEMUMachine, some of the functions
> were modified to return MachineCLass.
>
> Signed-off-by: Marcel Apfelbaum
Looks mostly good, but same issue as Alexey's patch: We are risking
qdev_get_machine() creating a Container-typed /machine node.
What about the following on top?
Alexey, if we reach agreement here, this means for you that we can just
use type_register_static() in place of qemu_machine_register() to
register your custom machine type with interface added.
Regards,
Andreas
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index b6deebd..749c83a 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -861,7 +861,8 @@ Object *qdev_get_machine(void)
static Object *dev;
if (dev == NULL) {
-dev = container_get(object_get_root(), "/machine");
+dev = object_resolve_path("/machine", NULL);
+g_assert(dev);
}
return dev;
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PULL 065/130] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions
From: Tom Musta
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 4 +++-
target-ppc/translate_init.c | 9 ++---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 1dbeb81..bb299d7 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1885,12 +1885,14 @@ enum {
PPC2_ATOMIC_ISA206 = 0x0200ULL,
/* ISA 2.06B floating point integer conversion */
PPC2_FP_CVT_ISA206 = 0x0400ULL,
+/* ISA 2.06B floating point test instructions*/
+PPC2_FP_TST_ISA206 = 0x0800ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
-PPC2_FP_CVT_ISA206)
+PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206)
};
/*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 21c56e6..6947934 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7071,7 +7071,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+PPC2_FP_TST_ISA206;
pcc->msr_mask = 0x8284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7112,7 +7113,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+PPC2_FP_TST_ISA206;
pcc->msr_mask = 0x8204FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7153,7 +7155,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+PPC2_FP_TST_ISA206;
pcc->msr_mask = 0x8284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.8.1.4
[Qemu-devel] [PULL 079/130] qdev: Keep global allocation counter per bus
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
If we now spawn a device that connects to a ide.0 the last created
bus gets the device, with the first created bus inaccessible to the
command line.
After some discussion on IRC we concluded that the best quick fix way
forward for this is to make automated bus-class type based allocation
count a global counter. That's what this patch implements. With this
we instead get
dev: macio-ide, id ""
bus: ide.1
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
on the example mentioned above.
This also means that if you did -device ...,bus=ide.0 you got a device
on the first bus (the last created one) before this patch and get that
device on the second one (the first created one) now. Breaks
migration unless you change bus=ide.0 to bus=ide.1 on the destination.
This is intended and makes the bus enumeration work as expected.
As per review request follows a list of otherwise affected boards and
the reasoning for the conclusion that they are ok:
target machine bus id times
-- --- -- -
aarch64 n800i2c-bus.0 2
aarch64 n810i2c-bus.0 2
arm n800i2c-bus.0 2
arm n810i2c-bus.0 2
-> Devices are only created explicitly on one of the two buses, using
s->mpu->i2c[0], so no change to the guest.
aarch64 vexpress-a15virtio-mmio-bus.0 4
aarch64 vexpress-a9 virtio-mmio-bus.0 4
aarch64 virtvirtio-mmio-bus.0 32
arm vexpress-a15virtio-mmio-bus.0 4
arm vexpress-a9 virtio-mmio-bus.0 4
arm virtvirtio-mmio-bus.0 32
-> Makes -device bus= work for all virtio-mmio buses. Breaks
migration. Workaround for migration from old to new: specify
virtio-mmio-bus.4 or .32 respectively rather than .0 on the
destination.
aarch64 xilinx-zynq-a9 usb-bus.0 2
arm xilinx-zynq-a9 usb-bus.0 2
mips64elfulong2eusb-bus.0 2
-> Normal USB operation not affected. Migration driver needs command
line to use the other bus.
i386isapc ide.0 2
x86_64 isapc ide.0 2
mipsmipside.0 2
mips64 mipside.0 2
mips64elmipside.0 2
mipsel mipside.0 2
ppc g3beige ide.0 2
ppc mac99 ide.0 2
ppc prepide.0 2
ppc64 g3beige ide.0 2
ppc64 mac99 ide.0 2
ppc64 prepide.0 2
-> Makes -device bus= work for all IDE buses. Breaks migration.
Workaround for migration from old to new: specify ide.1 rather than
ide.0 on the destination.
Signed-off-by: Alexander Graf
Signed-off-by: Markus Armbruster
Reviewed-by: Andreas Faerber
Signed-off-by: Alexander Graf
---
hw/core/qdev.c | 20 +---
hw/i386/pc_piix.c | 8 +++-
include/hw/qdev-core.h | 2 ++
3 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index c0b857f..380976a 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -440,27 +440,33 @@ DeviceState *qdev_find_recursive(BusState *bus, const
char *id)
static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
{
const char *typename = object_get_typename(OBJECT(bus));
+BusClass *bc;
char *buf;
-int i,len;
+int i, len, bus_id;
bus->parent = parent;
if (name) {
bus->name = g_strdup(name);
} else if (bus->parent && bus->parent->id) {
-/* parent device has id -> use it for bus name */
+/* parent device has id -> use it plus parent-bus-id for bus name */
+bus_id = bus->parent->num_child_bus;
+
len = strlen(bus->parent->id) + 16;
buf = g_malloc(len);
-snprintf(buf, len, "%s.%d", bus->parent->id,
bus->parent->num_child_bus);
+snprintf(buf, len, "%s.%d", bus->parent->id, bus_id);
bus->name = buf;
} else {
-/* no id -> use lowercase bus type for bus name */
+/* no id -> use lowercase bus type plus global bus-id for bus name */
+bc = BUS_GET_CLASS(bus);
+bus_id = bc->automatic_ids++;
+
len = strlen(typename) + 16;
buf = g_malloc(len);
-len = snprintf(buf, len, "%s.%d", typename,
- bu
[Qemu-devel] [PULL 064/130] target-ppc: Fix and enable fri[mnpz]
From: Tom Musta
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 18 +++---
target-ppc/translate_init.c | 3 +++
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index eb56082..87ff60f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -669,24 +669,28 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t
arg,
if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN round */
-farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
-POWERPC_EXCP_FP_VXCVI, 1);
-} else if (unlikely(float64_is_quiet_nan(farg.d) ||
-float64_is_infinity(farg.d))) {
-/* qNan / infinity round */
-farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+farg.ll = arg | 0x0008ul;
} else {
+int inexact = get_float_exception_flags(&env->fp_status) &
+ float_flag_inexact;
set_float_rounding_mode(rounding_mode, &env->fp_status);
farg.ll = float64_round_to_int(farg.d, &env->fp_status);
/* Restore rounding mode from FPSCR */
fpscr_set_rounding_mode(env);
+
+/* fri* does not set FPSCR[XX] */
+if (!inexact) {
+env->fp_status.float_exception_flags &= ~float_flag_inexact;
+}
}
+helper_float_check_status(env);
return farg.ll;
}
uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
{
-return do_fri(env, arg, float_round_nearest_even);
+return do_fri(env, arg, float_round_ties_away);
}
uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6dd0f84..21c56e6 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7062,6 +7062,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7102,6 +7103,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7142,6 +7144,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
--
1.8.1.4
[Qemu-devel] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true
From: Alexey Kardashevskiy
When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.
This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device status which now is "can
receive". The patch basically does the same thing as e8b4c68 does.
Suggested-by: Max Filippov
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/net/spapr_llan.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c
index 1bd6f50..f6fbcb5 100644
--- a/hw/net/spapr_llan.c
+++ b/hw/net/spapr_llan.c
@@ -405,6 +405,8 @@ static target_ulong h_add_logical_lan_buffer(PowerPCCPU
*cpu,
dev->rx_bufs++;
+qemu_flush_queued_packets(qemu_get_queue(dev->nic));
+
DPRINTF("h_add_logical_lan_buffer(): Added buf ptr=%d rx_bufs=%d"
" bd=0x%016llx\n", dev->add_buf_ptr, dev->rx_bufs,
(unsigned long long)buf);
--
1.8.1.4
[Qemu-devel] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions
From: Tom Musta This patch adds the Vector Minimum and Maximum Doubleword instructions that are introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 4 target-ppc/int_helper.c | 2 ++ target-ppc/translate.c | 8 3 files changed, 14 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 793877d..38bebea 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -123,15 +123,19 @@ DEF_HELPER_3(vavgsw, void, avr, avr, avr) DEF_HELPER_3(vminsb, void, avr, avr, avr) DEF_HELPER_3(vminsh, void, avr, avr, avr) DEF_HELPER_3(vminsw, void, avr, avr, avr) +DEF_HELPER_3(vminsd, void, avr, avr, avr) DEF_HELPER_3(vmaxsb, void, avr, avr, avr) DEF_HELPER_3(vmaxsh, void, avr, avr, avr) DEF_HELPER_3(vmaxsw, void, avr, avr, avr) +DEF_HELPER_3(vmaxsd, void, avr, avr, avr) DEF_HELPER_3(vminub, void, avr, avr, avr) DEF_HELPER_3(vminuh, void, avr, avr, avr) DEF_HELPER_3(vminuw, void, avr, avr, avr) +DEF_HELPER_3(vminud, void, avr, avr, avr) DEF_HELPER_3(vmaxub, void, avr, avr, avr) DEF_HELPER_3(vmaxuh, void, avr, avr, avr) DEF_HELPER_3(vmaxuw, void, avr, avr, avr) +DEF_HELPER_3(vmaxud, void, avr, avr, avr) DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr) DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr) DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 3b67ae3..fc2bff1 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -824,9 +824,11 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, VMINMAX(sb, s8) VMINMAX(sh, s16) VMINMAX(sw, s32) +VMINMAX(sd, s64) VMINMAX(ub, u8) VMINMAX(uh, u16) VMINMAX(uw, u32) +VMINMAX(ud, u64) #undef VMINMAX_DO #undef VMINMAX diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e1f39e9..95a751c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6940,15 +6940,19 @@ GEN_VXFORM(vsubudm, 0, 19); GEN_VXFORM(vmaxub, 1, 0); GEN_VXFORM(vmaxuh, 1, 1); GEN_VXFORM(vmaxuw, 1, 2); +GEN_VXFORM(vmaxud, 1, 3); GEN_VXFORM(vmaxsb, 1, 4); GEN_VXFORM(vmaxsh, 1, 5); GEN_VXFORM(vmaxsw, 1, 6); +GEN_VXFORM(vmaxsd, 1, 7); GEN_VXFORM(vminub, 1, 8); GEN_VXFORM(vminuh, 1, 9); GEN_VXFORM(vminuw, 1, 10); +GEN_VXFORM(vminud, 1, 11); GEN_VXFORM(vminsb, 1, 12); GEN_VXFORM(vminsh, 1, 13); GEN_VXFORM(vminsw, 1, 14); +GEN_VXFORM(vminsd, 1, 15); GEN_VXFORM(vavgub, 1, 16); GEN_VXFORM(vavguh, 1, 17); GEN_VXFORM(vavguw, 1, 18); @@ -10372,15 +10376,19 @@ GEN_VXFORM_207(vsubudm, 0, 19), GEN_VXFORM(vmaxub, 1, 0), GEN_VXFORM(vmaxuh, 1, 1), GEN_VXFORM(vmaxuw, 1, 2), +GEN_VXFORM_207(vmaxud, 1, 3), GEN_VXFORM(vmaxsb, 1, 4), GEN_VXFORM(vmaxsh, 1, 5), GEN_VXFORM(vmaxsw, 1, 6), +GEN_VXFORM_207(vmaxsd, 1, 7), GEN_VXFORM(vminub, 1, 8), GEN_VXFORM(vminuh, 1, 9), GEN_VXFORM(vminuw, 1, 10), +GEN_VXFORM_207(vminud, 1, 11), GEN_VXFORM(vminsb, 1, 12), GEN_VXFORM(vminsh, 1, 13), GEN_VXFORM(vminsw, 1, 14), +GEN_VXFORM_207(vminsd, 1, 15), GEN_VXFORM(vavgub, 1, 16), GEN_VXFORM(vavguh, 1, 17), GEN_VXFORM(vavguw, 1, 18), -- 1.8.1.4
[Qemu-devel] [PULL 019/130] target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
From: Tom Musta
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 50 +
target-ppc/helper.h | 9 +
target-ppc/translate.c | 18 ++
3 files changed, 77 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index cea94ac..74c1ce1 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1758,3 +1758,53 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState
*env)
}
#define float64_to_float64(x, env) x
+
+
+/* VSX_ADD_SUB - VSX floating point add/subract
+ * name - instruction mnemonic
+ * op- operation (add or sub)
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \
+void helper_##name(CPUPPCState *env, uint32_t opcode)\
+{\
+ppc_vsr_t xt, xa, xb;\
+int i; \
+ \
+getVSR(xA(opcode), &xa, env);\
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);\
+} else if (tp##_is_signaling_nan(xa.fld[i]) || \
+ tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
+VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
+VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
+VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
+VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
+VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6d282bb..966200d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -251,6 +251,15 @@ DEF_HELPER_4(vcfsx, void, env, avr, avr, i32)
DEF_HELPER_4(vctuxs, void, env, avr, avr, i32)
DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
+DEF_HELPER_2(xsadddp, void, env, i32)
+DEF_HELPER_2(xssubdp, void, env, i32)
+
+DEF_HELPER_2(xvadddp, void, env, i32)
+DEF_HELPER_2(xvsubdp, void, env, i32)
+
+DEF_HELPER_2(xvaddsp, void, env, i32)
+DEF_HELPER_2(xvsubsp, void, env, i32)
+
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
DEF_HELPER_2(efscfuf, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8c17005..9b4e8b1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7304,6 +7304,15 @@ static void gen_##name(DisasContext * ctx)
\
tcg_temp_free_i32(opc); \
}
+GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
+
+GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C
[Qemu-devel] [PULL 020/130] target-ppc: Add VSX ISA2.06 xmul Instructions
From: Tom Musta
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 47 +++
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 ++
3 files changed, 56 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 74c1ce1..51ca589 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1808,3 +1808,50 @@ VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+
+/* VSX_MUL - VSX floating point multiply
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_MUL(op, nels, tp, fld, sfprf)\
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xt, xa, xb;\
+int i; \
+ \
+getVSR(xA(opcode), &xa, env);\
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_mul(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(xb.fld[i])) || \
+(tp##_is_infinity(xb.fld[i]) && tp##_is_zero(xa.fld[i]))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf);\
+} else if (tp##_is_signaling_nan(xa.fld[i]) || \
+ tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+ \
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_MUL(xsmuldp, 1, float64, f64, 1)
+VSX_MUL(xvmuldp, 2, float64, f64, 0)
+VSX_MUL(xvmulsp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 966200d..ecb900f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -253,12 +253,15 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
+DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
+DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
+DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9b4e8b1..bf15f91 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7306,12 +7306,15 @@ static void gen_##name(DisasContext * ctx)
\
GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D
Re: [Qemu-devel] [PATCH 2.1 07/28] qemu-option: introduce qemu_find_opts_singleton
On Tue, Mar 04, 2014 at 03:00:35PM +0100, Paolo Bonzini wrote:
> Reviewed-by: Laszlo Ersek
> Signed-off-by: Paolo Bonzini
> ---
> include/qemu/config-file.h | 2 ++
> util/qemu-config.c | 14 ++
> vl.c | 11 +--
> 3 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/include/qemu/config-file.h b/include/qemu/config-file.h
> index dbd97c4..d4ba20e 100644
> --- a/include/qemu/config-file.h
> +++ b/include/qemu/config-file.h
> @@ -8,6 +8,8 @@
>
> QemuOptsList *qemu_find_opts(const char *group);
> QemuOptsList *qemu_find_opts_err(const char *group, Error **errp);
> +QemuOpts *qemu_find_opts_singleton(const char *group);
> +
> void qemu_add_opts(QemuOptsList *list);
> void qemu_add_drive_opts(QemuOptsList *list);
> int qemu_set_option(const char *str);
> diff --git a/util/qemu-config.c b/util/qemu-config.c
> index f610101..60051df 100644
> --- a/util/qemu-config.c
> +++ b/util/qemu-config.c
> @@ -39,6 +39,20 @@ QemuOptsList *qemu_find_opts(const char *group)
> return ret;
> }
>
> +QemuOpts *qemu_find_opts_singleton(const char *group)
> +{
> +QemuOptsList *list;
> +QemuOpts *opts;
> +
> +list = qemu_find_opts(group);
> +assert(list);
> +opts = qemu_opts_find(list, NULL);
> +if (!opts) {
> +opts = qemu_opts_create(list, NULL, 0, &error_abort);
> +}
> +return opts;
> +}
> +
> static CommandLineParameterInfoList *query_option_descs(const QemuOptDesc
> *desc)
> {
> CommandLineParameterInfoList *param_list = NULL, *entry;
> diff --git a/vl.c b/vl.c
> index 899b63f..dafe6f6 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -485,16 +485,7 @@ static QemuOptsList qemu_msg_opts = {
> */
> QemuOpts *qemu_get_machine_opts(void)
> {
> -QemuOptsList *list;
> -QemuOpts *opts;
> -
> -list = qemu_find_opts("machine");
> -assert(list);
> -opts = qemu_opts_find(list, NULL);
> -if (!opts) {
> -opts = qemu_opts_create(list, NULL, 0, &error_abort);
> -}
> -return opts;
> +return qemu_find_opts_singleton("machine");
> }
>
> const char *qemu_get_vm_name(void)
> --
> 1.8.5.3
>
This patch itself has no problem, so:
Reviewed-by: Hu Tao
BTW, why not let qemu_opt_find() return NULL for a NULL QemuOpts? Then
we can avoid creating an empty QemuOpts.
[Qemu-devel] [PATCH] linux-user: implement F_[GS]ETOWN_EX
F_[GS]ETOWN is replaced by F_[GS]ETOWN_EX inside the glibc fcntl wrapper.
Signed-off-by: Andreas Schwab
---
linux-user/syscall.c | 10 ++
linux-user/syscall_defs.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 2f573b8..51fbc91 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4366,6 +4366,14 @@ static int target_to_host_fcntl_cmd(int cmd)
#endif
case TARGET_F_NOTIFY:
return F_NOTIFY;
+#ifdef F_GETOWN_EX
+ case TARGET_F_GETOWN_EX:
+ return F_GETOWN_EX;
+#endif
+#ifdef F_SETOWN_EX
+ case TARGET_F_SETOWN_EX:
+ return F_SETOWN_EX;
+#endif
default:
return -TARGET_EINVAL;
}
@@ -4487,6 +4495,8 @@ static abi_long do_fcntl(int fd, int cmd, abi_ulong arg)
case TARGET_F_GETSIG:
case TARGET_F_SETLEASE:
case TARGET_F_GETLEASE:
+case TARGET_F_GETOWN_EX:
+case TARGET_F_SETOWN_EX:
ret = get_errno(fcntl(fd, host_cmd, arg));
break;
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 3c8869e..ed3d1a6 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -2134,6 +2134,9 @@ struct target_statfs64 {
#define TARGET_F_SETSIG10 /* for sockets. */
#define TARGET_F_GETSIG11 /* for sockets. */
+#define TARGET_F_SETOWN_EX 15
+#define TARGET_F_GETOWN_EX 16
+
#if defined(TARGET_MIPS)
#define TARGET_F_GETLK64 33 /* using 'struct flock64' */
#define TARGET_F_SETLK64 34
--
1.9.0
--
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
[Qemu-devel] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions
From: Tom Musta This patch adds the Unpack Signed Word instructions introduced in Power ISA Version 2.07: - Vector Unpack High Signed Word (vupkusw) - Vector Unpack Low Signed Word (vupklsw) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 2 ++ target-ppc/int_helper.c | 2 ++ target-ppc/translate.c | 4 3 files changed, 8 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 080142c..6a7e99f 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -224,8 +224,10 @@ DEF_HELPER_2(vupkhpx, void, avr, avr) DEF_HELPER_2(vupklpx, void, avr, avr) DEF_HELPER_2(vupkhsb, void, avr, avr) DEF_HELPER_2(vupkhsh, void, avr, avr) +DEF_HELPER_2(vupkhsw, void, avr, avr) DEF_HELPER_2(vupklsb, void, avr, avr) DEF_HELPER_2(vupklsh, void, avr, avr) +DEF_HELPER_2(vupklsw, void, avr, avr) DEF_HELPER_5(vmsumubm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsummbm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vsel, void, env, avr, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 534efb5..56e8d9a 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1524,8 +1524,10 @@ VUPKPX(hpx, UPKHI) } VUPK(hsb, s16, s8, UPKHI) VUPK(hsh, s32, s16, UPKHI) +VUPK(hsw, s64, s32, UPKHI) VUPK(lsb, s16, s8, UPKLO) VUPK(lsh, s32, s16, UPKLO) +VUPK(lsw, s64, s32, UPKLO) #undef VUPK #undef UPKHI #undef UPKLO diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 14d7985..07c0c39 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7149,8 +7149,10 @@ static void glue(gen_, name)(DisasContext *ctx) \ GEN_VXFORM_NOA(vupkhsb, 7, 8); GEN_VXFORM_NOA(vupkhsh, 7, 9); +GEN_VXFORM_NOA(vupkhsw, 7, 25); GEN_VXFORM_NOA(vupklsb, 7, 10); GEN_VXFORM_NOA(vupklsh, 7, 11); +GEN_VXFORM_NOA(vupklsw, 7, 27); GEN_VXFORM_NOA(vupkhpx, 7, 13); GEN_VXFORM_NOA(vupklpx, 7, 15); GEN_VXFORM_NOA_ENV(vrefp, 5, 4); @@ -10503,8 +10505,10 @@ GEN_VXFORM_SIMM(vspltisw, 6, 14), GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f, PPC_ALTIVEC) GEN_VXFORM_NOA(vupkhsb, 7, 8), GEN_VXFORM_NOA(vupkhsh, 7, 9), +GEN_VXFORM_207(vupkhsw, 7, 25), GEN_VXFORM_NOA(vupklsb, 7, 10), GEN_VXFORM_NOA(vupklsh, 7, 11), +GEN_VXFORM_207(vupklsw, 7, 27), GEN_VXFORM_NOA(vupkhpx, 7, 13), GEN_VXFORM_NOA(vupklpx, 7, 15), GEN_VXFORM_NOA(vrefp, 5, 4), -- 1.8.1.4
[Qemu-devel] [PULL 014/130] spapr-pci: enable adding PHB via -device
From: Alexey Kardashevskiy
Recent changes introduced cannot_instantiate_with_device_add_yet
and removed capability of adding yet another PCI host bridge via
command line for SPAPR platform (POWERPC64 server).
This brings the capability back and puts SPAPR PHB into "bridge"
category.
This is not much use for emulated PHB but it is absolutely required
for VFIO as we put an IOMMU group onto a separate PHB on SPAPR.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/ppc/spapr_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 4c7c3ae..3956328 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -728,6 +728,8 @@ static void spapr_phb_class_init(ObjectClass *klass, void
*data)
dc->props = spapr_phb_properties;
dc->reset = spapr_phb_reset;
dc->vmsd = &vmstate_spapr_pci;
+set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+dc->cannot_instantiate_with_device_add_yet = false;
}
static const TypeInfo spapr_phb_info = {
--
1.8.1.4
[Qemu-devel] [PULL 124/130] target-ppc: Fix htab_mask calculation
From: "Aneesh Kumar K.V"
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. We check for external htab and if
found true, we don't need to update sdr1
Signed-off-by: Aneesh Kumar K.V
[ fixed pte group offset computation in ppc_hash64_htab_lookup() that
caused TCG to fail, Greg Kurz ]
Signed-off-by: Greg Kurz
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 8 +++-
hw/ppc/spapr_hcall.c | 19 +++
target-ppc/cpu.h | 1 +
target-ppc/kvm.c | 4 +++-
target-ppc/machine.c | 11 +++
target-ppc/misc_helper.c | 4 +++-
target-ppc/mmu-hash64.c | 4 ++--
target-ppc/mmu_helper.c | 3 ++-
8 files changed, 40 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0989ed6..8ac4d8a 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -749,7 +749,13 @@ static void spapr_cpu_reset(void *opaque)
env->external_htab = (void *)1;
}
env->htab_base = -1;
-env->htab_mask = HTAB_SIZE(spapr) - 1;
+/*
+ * htab_mask is the mask used to normalize hash value to PTEG index.
+ * htab_shift is log2 of hash table size.
+ * We have 8 hpte per group, and each hpte is 16 bytes.
+ * ie have 128 bytes per hpte entry.
+ */
+env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1;
env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
(spapr->htab_shift - 18);
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 3ffcc65..d19e3fc 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -40,6 +40,17 @@ static target_ulong compute_tlbie_rb(target_ulong v,
target_ulong r,
return rb;
}
+static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
+{
+/*
+ * hash value/pteg group index is normalized by htab_mask
+ */
+if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) {
+return false;
+}
+return true;
+}
+
static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
@@ -91,7 +102,7 @@ static target_ulong h_enter(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
pteh &= ~0x60ULL;
-if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
+if (!valid_pte_index(env, pte_index)) {
return H_PARAMETER;
}
if (likely((flags & H_EXACT) == 0)) {
@@ -136,7 +147,7 @@ static RemoveResult remove_hpte(CPUPPCState *env,
target_ulong ptex,
hwaddr hpte;
target_ulong v, r, rb;
-if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
+if (!valid_pte_index(env, ptex)) {
return REMOVE_PARM;
}
@@ -262,7 +273,7 @@ static target_ulong h_protect(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
hwaddr hpte;
target_ulong v, r, rb;
-if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
+if (!valid_pte_index(env, pte_index)) {
return H_PARAMETER;
}
@@ -299,7 +310,7 @@ static target_ulong h_read(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
uint8_t *hpte;
int i, ridx, n_entries = 1;
-if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
+if (!valid_pte_index(env, pte_index)) {
return H_PARAMETER;
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 7ccf4c6..44ade0c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -966,6 +966,7 @@ struct CPUPPCState {
#endif
/* segment registers */
hwaddr htab_base;
+/* mask used to normalize hash value to PTEG index */
hwaddr htab_mask;
target_ulong sr[32];
/* externally stored hash table */
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 33d69d2..969ebdd 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1031,7 +1031,9 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
-ppc_store_sdr1(env, sregs.u.s.sdr1);
+if (!env->external_htab) {
+ppc_store_sdr1(env, sregs.u.s.sdr1);
+}
/* Sync SLB */
#ifdef TARGET_PPC64
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 12c174f..2d46cec 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -70,7 +70,9 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int
version_id)
qemu_get_betls(f, &env->pb[i]);
for (i = 0; i < 1024; i++)
qemu_get_betls(f, &env->spr[i]);
-ppc_store_sdr1(env, sdr1);
+if (!env->external_htab) {
+ppc_store_sdr1(env, sdr1);
+}
qemu_get_be32s(f, &env->vscr);
qemu_get_be64s(f, &env->spe_acc);
qemu_get_be32s(f, &env->spe_fscr);
@@ -179,9 +181,10 @@ static int cpu_post_load(void *opaque, int version_id)
env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
}
-/* Restore htab_base and htab_mask variables */
-ppc_store_sdr1(env, env->spr[SPR_SDR1]);
-
+if (!env->external_htab) {
+/* Restore htab_base and ht
[Qemu-devel] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes
From: Tom Musta
This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 5 +
target-ppc/int_helper.c | 29 +
target-ppc/translate.c | 9 +
3 files changed, 43 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index c20d50e..7ca219f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -273,6 +273,11 @@ DEF_HELPER_4(vcfsx, void, env, avr, avr, i32)
DEF_HELPER_4(vctuxs, void, env, avr, avr, i32)
DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
+DEF_HELPER_2(vclzb, void, avr, avr)
+DEF_HELPER_2(vclzh, void, avr, avr)
+DEF_HELPER_2(vclzw, void, avr, avr)
+DEF_HELPER_2(vclzd, void, avr, avr)
+
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 7a50f4a..7fca9f0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1524,6 +1524,35 @@ VUPK(lsh, s32, s16, UPKLO)
#undef UPKHI
#undef UPKLO
+#define VGENERIC_DO(name, element) \
+void helper_v##name(ppc_avr_t *r, ppc_avr_t *b) \
+{ \
+int i; \
+\
+VECTOR_FOR_INORDER_I(i, element) { \
+r->element[i] = name(b->element[i]);\
+} \
+}
+
+#define clzb(v) ((v) ? clz32((uint32_t)(v) << 24) : 8)
+#define clzh(v) ((v) ? clz32((uint32_t)(v) << 16) : 16)
+#define clzw(v) clz32((v))
+#define clzd(v) clz64((v))
+
+VGENERIC_DO(clzb, u8)
+VGENERIC_DO(clzh, u16)
+VGENERIC_DO(clzw, u32)
+VGENERIC_DO(clzd, u64)
+
+#undef clzb
+#undef clzh
+#undef clzw
+#undef clzd
+
+
+#undef VGENERIC_DO
+
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ca253e0..a1b85b5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7283,6 +7283,10 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
+GEN_VXFORM_NOA(vclzb, 1, 28)
+GEN_VXFORM_NOA(vclzh, 1, 29)
+GEN_VXFORM_NOA(vclzw, 1, 30)
+GEN_VXFORM_NOA(vclzd, 1, 31)
/*** VSX extension ***/
static inline TCGv_i64 cpu_vsrh(int n)
@@ -10504,6 +10508,11 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_VXFORM_207(vclzb, 1, 28),
+GEN_VXFORM_207(vclzh, 1, 29),
+GEN_VXFORM_207(vclzw, 1, 30),
+GEN_VXFORM_207(vclzd, 1, 31),
+
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
--
1.8.1.4
[Qemu-devel] [PULL 080/130] target-ppc: add extended opcodes for dcbt/dcbtst
From: Cédric Le Goater The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 : a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes for dcbt/dcbtst as no-ops just like the 'dcbt' instruction. Signed-off-by: Cédric Le Goater Signed-off-by: Alexander Graf --- target-ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 951f15e..8885490 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9596,8 +9596,8 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0001, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), -GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), +GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0001, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x0201, PPC_ALTIVEC), -- 1.8.1.4
[Qemu-devel] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
From: Alexey Kardashevskiy Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with 970 user manuals/P5-bookIV/PowerISA204 which define the number as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL -no32 S 152 00100 11000 CTRL yes-32 S This swaps the numbers. No effect from this change is expected though. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 4369e7c..51bcd4a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1250,7 +1250,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_EIE (0x050) #define SPR_MPC_EID (0x051) #define SPR_MPC_NRI (0x052) -#define SPR_CTRL (0x088) +#define SPR_UCTRL (0x088) #define SPR_MPC_CMPA (0x090) #define SPR_MPC_CMPB (0x091) #define SPR_MPC_CMPC (0x092) @@ -1259,7 +1259,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_DER (0x095) #define SPR_MPC_COUNTA(0x096) #define SPR_MPC_COUNTB(0x097) -#define SPR_UCTRL (0x098) +#define SPR_CTRL (0x098) #define SPR_MPC_CMPE (0x098) #define SPR_MPC_CMPF (0x099) #define SPR_MPC_CMPG (0x09A) -- 1.8.1.4
Re: [Qemu-devel] [PATCH 3/4] linux-user: set minimum kernel version to2.6.322
On 4 March 2014 13:41, Peter Maydell wrote: > On 4 March 2014 11:32, Alex Bennée wrote: > > Is the effect of this to report system uname or minimum whichever is higher? > > That's what this patch does. The old configure stuff which > this patchset removed made it report "always that version", > IIRC. Yes, configure indeed has that effect, so with the current ubuntu qemu you get: uname -r 3.8.0-35-generic qemu-arm ./arm/busybox uname -r 2.6.32 With these patches, qemu will report 2.6.32 or newer, if host kernel is newer. > >It would be nice to > > have an upstream fix for the hacks the distros are adding. > I think that's what this patchset is supposed to be :-) Yes. The patch 5/5 is heavy hammer to make distributions start using the new way. Else I fear they will just continue using the configure flag and their own hacks. > Only to the extent that they're still carrying bogus patches > borrowed from the SuSE tree rather than using the better > way of setting per-arch minumum reported uname that we > applied upstream. So you agree these patches are the way to go? If you believe these are too close to hard freeze, I can just send this list of patches for merging: https://git.linaro.org/people/riku.voipio/qemu.git/shortlog/refs/heads/linux-user-for-upstream Riku
[Qemu-devel] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions
From: Tom Musta
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 35 +++
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 ++
3 files changed, 44 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c84f432..5908e41 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1904,3 +1904,38 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_DIV(xsdivdp, 1, float64, f64, 1)
VSX_DIV(xvdivdp, 2, float64, f64, 0)
VSX_DIV(xvdivsp, 4, float32, f32, 0)
+
+/* VSX_RE - VSX floating point reciprocal estimate
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_RE(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xb; \
+int i;\
+ \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
+} \
+xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status); \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[0], sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env); \
+}
+
+VSX_RE(xsredp, 1, float64, f64, 1)
+VSX_RE(xvredp, 2, float64, f64, 0)
+VSX_RE(xvresp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6ede7ea..fe5b61c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -255,16 +255,19 @@ DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
+DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvdivdp, void, env, i32)
+DEF_HELPER_2(xvredp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(xvdivsp, void, env, i32)
+DEF_HELPER_2(xvresp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 076574e..897ffd9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7308,16 +7308,19 @@ GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op)\
static void glue(gen_, name)(DisasContext * ctx) \
@@ -10004,16 +10007,19 @@ GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC
[Qemu-devel] [PULL 078/130] target-ppc: Update external_htab even when HTAB is managed by kernel
From: "Aneesh Kumar K.V"
We will use this in later patches to make sure we use the right load
functions when copying hpte entries.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c9dfc6c..0989ed6 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -741,6 +741,13 @@ static void spapr_cpu_reset(void *opaque)
env->spr[SPR_HIOR] = 0;
env->external_htab = (uint8_t *)spapr->htab;
+if (kvm_enabled() && !env->external_htab) {
+/*
+ * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
+ * functions do the right thing.
+ */
+env->external_htab = (void *)1;
+}
env->htab_base = -1;
env->htab_mask = HTAB_SIZE(spapr) - 1;
env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
--
1.8.1.4
[Qemu-devel] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt
From: Tom Musta
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 31 +++
target-ppc/helper.h | 1 +
target-ppc/translate.c | 10 ++
3 files changed, 42 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 772b135..4ef3e2f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1039,6 +1039,37 @@ uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
}
+uint32_t helper_ftsqrt(uint64_t frb)
+{
+int fe_flag = 0;
+int fg_flag = 0;
+
+if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
+fe_flag = 1;
+fg_flag = 1;
+} else {
+int e_b = ppc_float64_get_unbiased_exp(frb);
+
+if (unlikely(float64_is_any_nan(frb))) {
+fe_flag = 1;
+} else if (unlikely(float64_is_zero(frb))) {
+fe_flag = 1;
+} else if (unlikely(float64_is_neg(frb))) {
+fe_flag = 1;
+} else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
+fe_flag = 1;
+}
+
+if (unlikely(float64_is_zero_or_denormal(frb))) {
+/* XB is not zero because of the above check and */
+/* therefore must be denormalized. */
+fg_flag = 1;
+}
+}
+
+return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+}
+
void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint32_t crfD)
{
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 2fb337c..a4480e8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -100,6 +100,7 @@ DEF_HELPER_2(frsqrte, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64)
+DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f372742..c9aebc5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2248,6 +2248,15 @@ static void gen_ftdiv(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
}
+static void gen_ftsqrt(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
+}
+
/*** Floating-Point compare***/
@@ -9869,6 +9878,7 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
+GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
--
1.8.1.4
[Qemu-devel] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction
From: Tom Musta
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 4 +++-
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 20
target-ppc/translate.c | 10 ++
target-ppc/translate_init.c | 11 +++
5 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c7bbbe3..74ff4c6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1877,9 +1877,11 @@ enum {
PPC2_ISA205= 0x0020ULL,
/* VSX additions in ISA 2.07 */
PPC2_VSX207= 0x0040ULL,
+/* ISA 2.06B bpermd */
+PPC2_PERM_ISA206 = 0x0080ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
-PPC2_ISA205 | PPC2_VSX207)
+PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206)
};
/*/
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0976930..a7833db 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
#endif
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index e50bdd2..0e7afb3 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t)
}
#endif
+#if defined(TARGET_PPC64)
+
+uint64_t helper_bpermd(uint64_t rs, uint64_t rb)
+{
+int i;
+uint64_t ra = 0;
+
+for (i = 0; i < 8; i++) {
+int index = (rs >> (i*8)) & 0xFF;
+if (index < 64) {
+if (rb & (1ull << (63-index))) {
+ra |= 1 << i;
+}
+}
+}
+return ra;
+}
+
+#endif
+
target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
{
target_ulong mask = 0xff;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d57d683..f00384b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1525,6 +1525,15 @@ static void gen_prtyd(DisasContext *ctx)
#endif
#if defined(TARGET_PPC64)
+/* bpermd */
+static void gen_bpermd(DisasContext *ctx)
+{
+gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
+ cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+}
+#endif
+
+#if defined(TARGET_PPC64)
/* extsw & extsw. */
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -9433,6 +9442,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0xF801,
PPC_NONE, PPC2_ISA205),
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0xF801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x, PPC_64B),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0xF801, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x0001, PPC_NONE,
PPC2_PERM_ISA206),
#endif
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x, PPC_INTEGER),
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x, PPC_INTEGER),
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 60ec9cd..53fa424 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4722,7 +4722,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
PPC_FLOAT_STFIWX | PPC_WAIT |
PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
-pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
+pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
pcc->msr_mask = 0x9402FB36ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE206;
pcc->excp_model = POWERPC_EXCP_BOOKE;
@@ -7068,7 +7068,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
-pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
+pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
+PPC2_PERM_ISA206;
pcc->msr_mask = 0x8284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7106,7 +7107,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
-pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA20
[Qemu-devel] [PULL 120/130] target-ppc/translate.c: Use ULL suffix for 64 bit constants
From: Peter Maydell 64 bit constants need the "ULL" suffix, not just "UL", because on 32 bit platforms 'long' is not large enough and this will cause a compiler warning. Signed-off-by: Peter Maydell Reviewed-by: Stefan Weil Signed-off-by: Alexander Graf --- target-ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index cf8f98a..051693b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7727,8 +7727,8 @@ static void gen_xxpermdi(DisasContext *ctx) #define OP_NABS 2 #define OP_NEG 3 #define OP_CPSGN 4 -#define SGN_MASK_DP 0x8000ul -#define SGN_MASK_SP 0x80008000ul +#define SGN_MASK_DP 0x8000ull +#define SGN_MASK_SP 0x80008000ull #define VSX_SCALAR_MOVE(name, op, sgn_mask) \ static void glue(gen_, name)(DisasContext * ctx) \ -- 1.8.1.4
[Qemu-devel] [PULL 070/130] PPC: KVM: store SLB slot number
From: Alexey Kardashevskiy
When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR
enabled as now the guest is handling interrupts in virtual mode and unable
to reconstruct correct SLBs anymore.
This adds "index" field for valid SLBs when putting them to KVM.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Aneesh Kumar K.V
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alexander Graf
---
target-ppc/kvm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 7af3fe2..e4a1a35 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -820,6 +820,9 @@ int kvm_arch_put_registers(CPUState *cs, int level)
#ifdef TARGET_PPC64
for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
+if (env->slb[i].esid & SLB_ESID_V) {
+sregs.u.s.ppc64.slb[i].slbe |= i;
+}
sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
}
#endif
--
1.8.1.4
[Qemu-devel] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo
From: Tom Musta This patch adds two Altivec unsigned doublword modulo instructions that are introduced in Power ISA Version V2.07: - vaddudm : Vector Add Unsigned Doubleword Modulo - vsubudm : Vector Subtrace Unsigned Doubleword Modulo Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 2 ++ target-ppc/int_helper.c | 1 + target-ppc/translate.c | 4 3 files changed, 7 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index a4480e8..1106e29 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -109,9 +109,11 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) DEF_HELPER_3(vaddubm, void, avr, avr, avr) DEF_HELPER_3(vadduhm, void, avr, avr, avr) DEF_HELPER_3(vadduwm, void, avr, avr, avr) +DEF_HELPER_3(vaddudm, void, avr, avr, avr) DEF_HELPER_3(vsububm, void, avr, avr, avr) DEF_HELPER_3(vsubuhm, void, avr, avr, avr) DEF_HELPER_3(vsubuwm, void, avr, avr, avr) +DEF_HELPER_3(vsubudm, void, avr, avr, avr) DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) DEF_HELPER_3(vavguw, void, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 71db3fb..3e36c0a 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -504,6 +504,7 @@ void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) VARITH(ubm, u8) VARITH(uhm, u16) VARITH(uwm, u32) +VARITH(udm, u64) #undef VARITH_DO #undef VARITH diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ed1cf1d..b1986f4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6932,9 +6932,11 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ GEN_VXFORM(vaddubm, 0, 0); GEN_VXFORM(vadduhm, 0, 1); GEN_VXFORM(vadduwm, 0, 2); +GEN_VXFORM(vaddudm, 0, 3); GEN_VXFORM(vsububm, 0, 16); GEN_VXFORM(vsubuhm, 0, 17); GEN_VXFORM(vsubuwm, 0, 18); +GEN_VXFORM(vsubudm, 0, 19); GEN_VXFORM(vmaxub, 1, 0); GEN_VXFORM(vmaxuh, 1, 1); GEN_VXFORM(vmaxuw, 1, 2); @@ -10338,9 +10340,11 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x, tp0, tp1), GEN_VXFORM(vaddubm, 0, 0), GEN_VXFORM(vadduhm, 0, 1), GEN_VXFORM(vadduwm, 0, 2), +GEN_VXFORM_207(vaddudm, 0, 3), GEN_VXFORM(vsububm, 0, 16), GEN_VXFORM(vsubuhm, 0, 17), GEN_VXFORM(vsubuwm, 0, 18), +GEN_VXFORM_207(vsubudm, 0, 19), GEN_VXFORM(vmaxub, 1, 0), GEN_VXFORM(vmaxuh, 1, 1), GEN_VXFORM(vmaxuw, 1, 2), -- 1.8.1.4
[Qemu-devel] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
From: Tom Musta This patch adds the Multilpy Even/Odd Word instructions that are introduced in Power ISA Version 2.07: - Vector Multiply Even Unsigned Word (vmuleuw) - Vector Multiply Even Signed Word (vmulesw) - Vector Multiply Odd Unsigned Word (vmulouw) - Vector Multiply Odd Signed Word (vmulosw) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 4 target-ppc/int_helper.c | 2 ++ target-ppc/translate.c | 8 3 files changed, 14 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 1106e29..ca18447 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -166,12 +166,16 @@ DEF_HELPER_3(vmrghh, void, avr, avr, avr) DEF_HELPER_3(vmrghw, void, avr, avr, avr) DEF_HELPER_3(vmulesb, void, avr, avr, avr) DEF_HELPER_3(vmulesh, void, avr, avr, avr) +DEF_HELPER_3(vmulesw, void, avr, avr, avr) DEF_HELPER_3(vmuleub, void, avr, avr, avr) DEF_HELPER_3(vmuleuh, void, avr, avr, avr) +DEF_HELPER_3(vmuleuw, void, avr, avr, avr) DEF_HELPER_3(vmulosb, void, avr, avr, avr) DEF_HELPER_3(vmulosh, void, avr, avr, avr) +DEF_HELPER_3(vmulosw, void, avr, avr, avr) DEF_HELPER_3(vmuloub, void, avr, avr, avr) DEF_HELPER_3(vmulouh, void, avr, avr, avr) +DEF_HELPER_3(vmulouw, void, avr, avr, avr) DEF_HELPER_3(vsrab, void, avr, avr, avr) DEF_HELPER_3(vsrah, void, avr, avr, avr) DEF_HELPER_3(vsraw, void, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 20d34e6..09590c7 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1005,8 +1005,10 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, VMUL_DO(mulo##suffix, mul_element, prod_element, cast, 0) VMUL(sb, s8, s16, int16_t) VMUL(sh, s16, s32, int32_t) +VMUL(sw, s32, s64, int64_t) VMUL(ub, u8, u16, uint16_t) VMUL(uh, u16, u32, uint32_t) +VMUL(uw, u32, u64, uint64_t) #undef VMUL_DO #undef VMUL diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b1986f4..4d2579d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6963,12 +6963,16 @@ GEN_VXFORM(vmrglh, 6, 5); GEN_VXFORM(vmrglw, 6, 6); GEN_VXFORM(vmuloub, 4, 0); GEN_VXFORM(vmulouh, 4, 1); +GEN_VXFORM(vmulouw, 4, 2); GEN_VXFORM(vmulosb, 4, 4); GEN_VXFORM(vmulosh, 4, 5); +GEN_VXFORM(vmulosw, 4, 6); GEN_VXFORM(vmuleub, 4, 8); GEN_VXFORM(vmuleuh, 4, 9); +GEN_VXFORM(vmuleuw, 4, 10); GEN_VXFORM(vmulesb, 4, 12); GEN_VXFORM(vmulesh, 4, 13); +GEN_VXFORM(vmulesw, 4, 14); GEN_VXFORM(vslb, 2, 4); GEN_VXFORM(vslh, 2, 5); GEN_VXFORM(vslw, 2, 6); @@ -10371,12 +10375,16 @@ GEN_VXFORM(vmrglh, 6, 5), GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM(vmuloub, 4, 0), GEN_VXFORM(vmulouh, 4, 1), +GEN_VXFORM_207(vmulouw, 4, 2), GEN_VXFORM(vmulosb, 4, 4), GEN_VXFORM(vmulosh, 4, 5), +GEN_VXFORM_207(vmulosw, 4, 6), GEN_VXFORM(vmuleub, 4, 8), GEN_VXFORM(vmuleuh, 4, 9), +GEN_VXFORM_207(vmuleuw, 4, 10), GEN_VXFORM(vmulesb, 4, 12), GEN_VXFORM(vmulesh, 4, 13), +GEN_VXFORM_207(vmulesw, 4, 14), GEN_VXFORM(vslb, 2, 4), GEN_VXFORM(vslh, 2, 5), GEN_VXFORM(vslw, 2, 6), -- 1.8.1.4
[Qemu-devel] [PULL 021/130] target-ppc: Add VSX ISA2.06 xdiv Instructions
From: Tom Musta
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 49 +
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 ++
3 files changed, 58 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 51ca589..c84f432 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1855,3 +1855,52 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_MUL(xsmuldp, 1, float64, f64, 1)
VSX_MUL(xvmuldp, 2, float64, f64, 0)
VSX_MUL(xvmulsp, 4, float32, f32, 0)
+
+/* VSX_DIV - VSX floating point divide
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_DIV(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xa, xb; \
+int i;\
+ \
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat); \
+xt.fld[i] = tp##_div(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
+if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
+} else if (tp##_is_zero(xa.fld[i]) && \
+tp##_is_zero(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
+} else if (tp##_is_signaling_nan(xa.fld[i]) ||\
+tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
+} \
+} \
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env); \
+}
+
+VSX_DIV(xsdivdp, 1, float64, f64, 1)
+VSX_DIV(xvdivdp, 2, float64, f64, 0)
+VSX_DIV(xvdivsp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ecb900f..6ede7ea 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -254,14 +254,17 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
+DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
+DEF_HELPER_2(xvdivdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
DEF_HELPER_2(xvmulsp, void, env, i32)
+DEF_HELPER_2(xvdivsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bf15f91..076574e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7307,14 +7307,17 @@ static void ge
Re: [Qemu-devel] [libvirt] Looking for project ideas and mentors for Google Summer of Code 2014
> -Original Message- > From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] > On Behalf Of Stefan Hajnoczi > Sent: Friday, February 14, 2014 7:58 AM > To: Cedric Bosdonnat > Cc: Jan Kiszka; qemu-devel; kvm; libvir-l...@redhat.com; Kevin Wolf; Peter > Maydell; Peter Crosthwaite; Max Reitz; Anthony Liguori; Paolo Bonzini; > Andreas Färber; Richard Henderson > Subject: Re: [libvirt] Looking for project ideas and mentors for Google > Summer of Code 2014 > > On Fri, Feb 14, 2014 at 03:22:04PM +0100, Cedric Bosdonnat wrote: > > On Fri, 2014-02-14 at 09:16 +0100, Jan Kiszka wrote: > > > > I need to submit our organization application (including our > > > > project > > > > ideas) on Friday. > > > > > > Hope it's not too late: just added the VT-d emulation proposal. > > > > It's not too late. Ideas page must be ready when students will > > discover the list of accepted organizations on Monday 24th. > > > > I'm not GSoc admin here, but on LibreOffice ;) > > The project ideas list is linked from the organization application form and > Google folks have mentioned messy/incomplete project ideas lists when > giving feedback to orgs that were not accepted. > > This is why it's worth having the project ideas list ready. > > But Cedric is right that we can still add project ideas later. I set the hard > deadline at March 10th when students begin applying. > > Stefan There are only a few days left before the hard deadline (March 10th) but I wanted to mention one possible project which I think is worth considering: Integration of Libvirt and CRIU to allow live-migration (and snapshots?) for containers In [1] you can find more details about the reasons why this feature would make sense together with a first analysis by Daniel about what to consider for the design. I am not applying as a student and I am not offering myself as a mentor (I do not qualify as a mentor), I Just wanted to point out a possible interesting (and challenging) project. I am afraid it would be too challenging for a 12 weeks projects, but I'll let you decide that. Having said that, I would be happy to help with the testing and reviews if needed. /Chris [1] http://www.redhat.com/archives/libvir-list/2013-November/msg00055.html
[Qemu-devel] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions
From: Tom Musta
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 16
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 4
3 files changed, 22 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c35135e..dfd9b80 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2487,6 +2487,22 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j],
f64[i], 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
+uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
+{
+float_status tstat = env->fp_status;
+set_float_exception_flags(0, &tstat);
+
+return (uint64_t)float64_to_float32(xb, &tstat) << 32;
+}
+
+uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
+{
+float_status tstat = env->fp_status;
+set_float_exception_flags(0, &tstat);
+
+return float32_to_float64(xb >> 32, &tstat);
+}
+
/* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
* op- instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1654589..0976930 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -273,7 +273,9 @@ DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvspdp, void, env, i32)
+DEF_HELPER_2(xscvspdpn, i64, env, i64)
DEF_HELPER_2(xscvdpsxds, void, env, i32)
DEF_HELPER_2(xscvdpsxws, void, env, i32)
DEF_HELPER_2(xscvdpuxds, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c307f24..d57d683 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7437,7 +7437,9 @@ GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
@@ -10275,7 +10277,9 @@ GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
--
1.8.1.4
[Qemu-devel] [PULL 003/130] target-ppc: remove powerpc 970gx
From: Alexey Kardashevskiy
The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.
This removes 970GX.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/STATUS | 9
target-ppc/cpu-models.c | 2 -
target-ppc/cpu-models.h | 1 -
target-ppc/translate_init.c | 100
4 files changed, 112 deletions(-)
diff --git a/target-ppc/STATUS b/target-ppc/STATUS
index c8e9018..a4d48a7 100644
--- a/target-ppc/STATUS
+++ b/target-ppc/STATUS
@@ -377,15 +377,6 @@ MMU OK
EXCP KO partially implemented
Remarks: Should be able to boot but there is no hw platform currently emulated.
-PowerPC 970GX:
-INSN KO Altivec missing and more
-SPR KO
-MSR ?
-IRQ OK
-MMU OK
-EXCP KO partially implemented
-Remarks: Should be able to boot but there is no hw platform currently emulated.
-
PowerPC Cell:
INSN KO Altivec missing and more
SPR KO
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 7c9466f..f6c9b3a 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1156,8 +1156,6 @@
"PowerPC 970FX v3.0 (G5)")
POWERPC_DEF("970fx_v3.1",CPU_POWERPC_970FX_v31, 970FX,
"PowerPC 970FX v3.1 (G5)")
-POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX,
-"PowerPC 970GX (G5)")
POWERPC_DEF("970mp_v1.0",CPU_POWERPC_970MP_v10, 970MP,
"PowerPC 970MP v1.0")
POWERPC_DEF("970mp_v1.1",CPU_POWERPC_970MP_v11, 970MP,
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index 49ba4a4..644a126 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -570,7 +570,6 @@ enum {
CPU_POWERPC_970FX_v21 = 0x003C0201,
CPU_POWERPC_970FX_v30 = 0x003C0300,
CPU_POWERPC_970FX_v31 = 0x003C0301,
-CPU_POWERPC_970GX = 0x0045,
CPU_POWERPC_970MP_v10 = 0x00440100,
CPU_POWERPC_970MP_v11 = 0x00440101,
#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ed70087..df8b4b1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6830,106 +6830,6 @@ POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-static int check_pow_970GX (CPUPPCState *env)
-{
-if (env->spr[SPR_HID0] & 0x0060)
-return 1;
-
-return 0;
-}
-
-static void init_proc_970GX (CPUPPCState *env)
-{
-gen_spr_ne_601(env);
-gen_spr_7xx(env);
-/* Time base */
-gen_tbl(env);
-/* Hardware implementation registers */
-/* XXX : not implemented */
-spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x6000);
-/* XXX : not implemented */
-spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_750FX_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
-/* XXX : not implemented */
-spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x);
-/* Memory management */
-/* XXX: not correct */
-gen_low_BATs(env);
-/* XXX : not implemented */
-spr_register(env, SPR_MMUCFG, "MMUCFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x); /* TOFIX */
-/* XXX : not implemented */
-spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x); /* TOFIX */
-spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x);
-#if !defined(CONFIG_USER_ONLY)
-env->slb_nr = 32;
-#endif
-init_excp_970(env);
-env->dcache_line_size = 128;
-env->icache_line_size = 128;
-/* Allocate hardware IRQ controller */
-ppc970_irq_init(env);
-/* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
-vscr_init
[Qemu-devel] [PULL 087/130] target-ppc: Load Quadword
From: Tom Musta
This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07. Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Little Endian
mode.
Note that this patch also adds the PPC_64BX flag to the Power8 model,
which enables the lq instruction.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 36 ++--
target-ppc/translate_init.c | 2 +-
2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f6ff248..06372b9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2872,36 +2872,44 @@ static void gen_ld(DisasContext *ctx)
/* lq */
static void gen_lq(DisasContext *ctx)
{
-#if defined(CONFIG_USER_ONLY)
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-#else
int ra, rd;
TCGv EA;
-/* Restore CPU state */
-if (unlikely(ctx->mem_idx == 0)) {
+/* lq is a legal user mode instruction starting in ISA 2.07 */
+bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
+bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
+
+if (!legal_in_user_mode && is_user_mode(ctx)) {
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
return;
}
+
+if (!le_is_supported && ctx->le_mode) {
+gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
+return;
+}
+
ra = rA(ctx->opcode);
rd = rD(ctx->opcode);
if (unlikely((rd & 1) || rd == ra)) {
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
-if (unlikely(ctx->le_mode)) {
-/* Little-endian mode is not handled */
-gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
-return;
-}
+
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_imm_index(ctx, EA, 0x0F);
-gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
-gen_addr_add(ctx, EA, EA, 8);
-gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
+
+if (unlikely(ctx->le_mode)) {
+gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
+gen_addr_add(ctx, EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
+} else {
+gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
+gen_addr_add(ctx, EA, EA, 8);
+gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
+}
tcg_temp_free(EA);
-#endif
}
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 64f56de..b9576ac 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7165,7 +7165,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_ALTIVEC |
+ PPC_64B | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
--
1.8.1.4
[Qemu-devel] [PULL 112/130] target-ppc: Altivec 2.07: Doubleword Compares
From: Tom Musta
This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:
- Vector Compare Equal to Unsigned Doubleword (vcmpequd)
- Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
- Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)
These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.
The helper macro for integer compares is enhanced to account for 64-bit
operands.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 6 ++
target-ppc/int_helper.c | 14 ++
target-ppc/translate.c | 16 +---
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ca1dc83..9613654 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -139,12 +139,15 @@ DEF_HELPER_3(vmaxud, void, avr, avr, avr)
DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtud, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsw, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtsd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
@@ -152,12 +155,15 @@ DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtud_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtsw_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpgtsd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 5885b7e..27a34c0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -626,15 +626,18 @@ VCF(sx, int32_to_float32, s32)
void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r,\
ppc_avr_t *a, ppc_avr_t *b)\
{ \
-uint32_t ones = (uint32_t)-1; \
-uint32_t all = ones;\
-uint32_t none = 0; \
+uint64_t ones = (uint64_t)-1; \
+uint64_t all = ones;\
+uint64_t none = 0; \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
-uint32_t result = (a->element[i] compare b->element[i] ?\
+uint64_t result = (a->element[i] compare b->element[i] ?\
ones : 0x0); \
switch (sizeof(a->element[0])) {\
+case 8: \
+r->u64[i] = result; \
+break; \
case 4: \
r->u32[i] = result; \
break; \
@@ -658,12 +661,15 @@ VCF(sx, int32_to_float32, s32)
VCMP(equb, ==, u8)
VCMP(equh, ==, u16)
VCMP(equw, ==, u32)
+VCMP(equd, ==, u64)
VCMP(gtub, >, u8)
VCMP(gtuh, >, u16)
VCMP(gtuw, >, u32)
+VCMP(gtud, >, u64)
VCMP(gtsb, >, s8)
VCMP(gtsh, >, s16)
VCMP(gtsw, >, s32)
+VCMP(gtsd, >, s64)
#undef VCMP_DO
#undef VCMP
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fb7bcbe..c6242c8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7136,17 +7136,27 @@ static void glue(gen_, name0##_##name1)(DisasContext
*ctx)
Re: [Qemu-devel] [PATCH 4/5] block/raw-posix: Strip protocol prefix on creation
On 03/06/2014 03:25 PM, Max Reitz wrote: > The hdev_create() implementation in block/raw-posix.c is used by the > "host_device", "host_cdrom" and "host_floppy" protocol block drivers > together. Thus, it any of the associated prefixes may occur and exactly s/it // > one should be stripped, if it does (thus, > "host_device:host_cdrom:/dev/cdrom" is not shortened to "/dev/cdrom"). > > Signed-off-by: Max Reitz > --- > block/raw-posix.c | 12 > 1 file changed, 12 insertions(+) -- Eric Blake eblake redhat com+1-919-301-3266 Libvirt virtualization library http://libvirt.org signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PULL 00/130] ppc patch queue 2014-03-05
Hi Blue / Aurelien / Anthony / Peter, This is my current patch queue for ppc. Please pull. This pull request includes: - VSX emulation support - book3s pr/hv selection - some bug fixes - qdev stable numbering - eTSEC emulation Alex The following changes since commit f55ea6297cc0224fe4934b90ff5343b620b14669: block/gluster: Add missing argument to qemu_gluster_init() call (2014-03-04 20:20:57 +) are available in the git repository at: git://github.com/agraf/qemu.git tags/signed-ppc-for-upstream for you to fetch changes up to 0f20ba62c35e6a779ba4ea00616192ef2abb6896: target-ppc: spapr: e500: fix to use cpu_dt_id (2014-03-05 03:07:04 +0100) Patch queue for ppc - 2014-03-05 This pull request includes: - VSX emulation support - book3s pr/hv selection - some bug fixes - qdev stable numbering - eTSEC emulation Alexander Graf (3): KVM: Split QEMUMachine typedef into separate header qdev: Keep global allocation counter per bus PPC: sPAPR: Only use getpagesize() when we run with kvm Alexey Kardashevskiy (19): target-ppc: fix compile error when PPC_DUMP_CPU is enabled target-ppc: fix LPCR SPR number target-ppc: remove powerpc 970gx target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8 target-ppc: remove unsupported SPRs from 970 and P5+ target-ppc: fix Authority Mask Register init value PPC: KVM: fix "set one register" spapr-pci: enable adding PHB via -device target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL PPC: KVM: store SLB slot number PPC: KVM: suppress warnings about not supported SPRs spapr: support only ELF kernel images moxie: fix load_elf() usage elf-loader: add more return codes spapr: print more detailed error message on failed load_elf() spapr-vlan: flush queue whenever can_receive can go from false to true target-ppc: add PowerPCCPU::cpu_dt_id target-ppc: spapr: e500: fix to use cpu_dt_id Aneesh Kumar K.V (6): kvm: Add a new machine option kvm-type target-ppc: Update external_htab even when HTAB is managed by kernel target-ppc: Fix htab_mask calculation target-ppc: Fix page table lookup with kvm enabled target-ppc: Change the hpte store API target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab Anton Blanchard (1): target-ppc: dump DAR and DSISR Cédric Le Goater (2): mmu-hash64: fix Virtual Page Class Key Protection target-ppc: add extended opcodes for dcbt/dcbtst Edgar E. Iglesias (1): virtex_ml507: Add support for loading initrd images Fabien Chouteau (1): Add Enhanced Three-Speed Ethernet Controller (eTSEC) Greg Kurz (1): PPC: KVM: add support for LPCR Laurent Dufour (1): target-ppc: Introduce hypervisor call H_GET_TCE Nathan Whitehorn (1): spapr_vscsi: Fix REPORT_LUNS handling Peter Maydell (1): target-ppc/translate.c: Use ULL suffix for 64 bit constants Tom Musta (93): target-ppc: Add set_fprf Argument to fload_invalid_op_excp() target-ppc: General Support for VSX Helpers target-ppc: Add VSX ISA2.06 xadd/xsub Instructions target-ppc: Add VSX ISA2.06 xmul Instructions target-ppc: Add VSX ISA2.06 xdiv Instructions target-ppc: Add VSX ISA2.06 xre Instructions target-ppc: Add VSX ISA2.06 xsqrt Instructions target-ppc: Add VSX ISA2.06 xrsqrte Instructions target-ppc: Add VSX ISA2.06 xtdiv Instructions target-ppc: Add VSX ISA2.06 xtsqrt Instructions target-ppc: Add VSX ISA2.06 Multiply Add Instructions target-ppc: Add VSX xscmp*dp Instructions target-ppc: Add VSX xmax/xmin Instructions target-ppc: Add VSX Vector Compare Instructions target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions target-ppc: Add VSX ISA2.06 Integer Conversion Instructions target-ppc: Add VSX Rounding Instructions target-ppc: VSX Stage 4: Add VSX 2.07 Flag target-ppc: VSX Stage 4: Refactor lxsdx target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx target-ppc: VSX Stage 4: Refactor stxsdx target-ppc: VSX Stage 4: Add stxsiwx and stxsspx target-ppc: VSX Stage 4: Add xsaddsp and xssubsp target-ppc: VSX Stage 4: Add xsmulsp target-ppc: VSX Stage 4: Add xsdivsp target-ppc: VSX Stage 4: Add xsresp target-ppc: VSX Stage 4: Add xssqrtsp target-ppc: VSX Stage 4: add xsrsqrtesp target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc target-ppc: Move To/From VSR Instructions target-ppc: Floating Merge Word Instructions
[Qemu-devel] [PULL 071/130] virtex_ml507: Add support for loading initrd images
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
[agraf: fix up stray quotes and newlines in strings]
Signed-off-by: Alexander Graf
---
hw/ppc/virtex_ml507.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 85a0e53..ce8ea91 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -174,6 +174,19 @@ static int xilinx_load_device_tree(hwaddr addr,
if (!fdt) {
return 0;
}
+
+r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
+ initrd_base);
+if (r < 0) {
+error_report("couldn't set /chosen/linux,initrd-start");
+}
+
+r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ (initrd_base + initrd_size));
+if (r < 0) {
+error_report("couldn't set /chosen/linux,initrd-end");
+}
+
r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
if (r < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
@@ -187,6 +200,8 @@ static void virtex_init(QEMUMachineInitArgs *args)
const char *cpu_model = args->cpu_model;
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
+hwaddr initrd_base = 0;
+int initrd_size = 0;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
PowerPCCPU *cpu;
@@ -259,10 +274,27 @@ static void virtex_init(QEMUMachineInitArgs *args)
boot_info.ima_size = kernel_size;
+/* Load initrd. */
+if (args->initrd_filename) {
+initrd_base = high = ROUND_UP(high, 4);
+initrd_size = load_image_targphys(args->initrd_filename,
+ high, ram_size - high);
+
+if (initrd_size < 0) {
+error_report("couldn't load ram disk '%s'",
+ args->initrd_filename);
+exit(1);
+}
+high = ROUND_UP(high + initrd_size, 4);
+}
+
/* Provide a device-tree. */
boot_info.fdt = high + (8192 * 2);
boot_info.fdt &= ~8191;
-xilinx_load_device_tree(boot_info.fdt, ram_size, 0, 0, kernel_cmdline);
+
+xilinx_load_device_tree(boot_info.fdt, ram_size,
+initrd_base, initrd_size,
+kernel_cmdline);
}
env->load_info = &boot_info;
}
--
1.8.1.4
[Qemu-devel] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
From: Tom Musta
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 20 +---
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 3165ef0..f047640 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState
*env)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp)\
void helper_##name(CPUPPCState *env, uint32_t opcode)\
{\
ppc_vsr_t xt, xa, xb;\
@@ -1794,6 +1794,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)
\
}\
}\
\
+if (r2sp) { \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+}\
+ \
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
}\
@@ -1802,12 +1806,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
-VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
-VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
-VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
-VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
-VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0)
+VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
/* VSX_MUL - VSX floating point multiply
* op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0276b02..696b9d3 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -286,6 +286,9 @@ DEF_HELPER_2(xsrdpim, void, env, i32)
DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
+DEF_HELPER_2(xsaddsp, void, env, i32)
+DEF_HELPER_2(xssubsp, void, env, i32)
+
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d67bf2d..f0925d5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7358,6 +7358,9 @@ GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
+
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
@@ -10164,6 +10167,9 @@ GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
+GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
+GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
+
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
--
1.8.1.4
Re: [Qemu-devel] [PATCH] pseries: Update SLOF firmware image to 20140204
On 02/21/2014 07:24 PM, Alexander Graf wrote:
>
> On 21.02.2014, at 07:09, Alexey Kardashevskiy wrote:
>
>> On 02/10/2014 05:52 PM, Alexey Kardashevskiy wrote:
>>> The changelog is:
version: update to 20140204
virtio-9p: disable unused structure
Make "boot net:dhcp" boot from IPv4 only
Fix virtio device shutdown
Change shutdown method name for virtio-scsi
Add support for 64bit LE ABI v1 and v2 support
Change representation of string environment variable
cas: return error when unknown node found
version: update
Reset obp-tftp arguments before parsing
Enable seamless netboot on IPv6 network
Fix shutdown for virtio devices
Fix zero checksum in UDP header
Handle router advertisement message properly
[oex]hci_exit: Check before freeing/unmapping memory
Work around missing sc 1 traps on pHyp
fix print_version() to return where it came from
usb-xhci: memory freeing and using returns as bool uniformly
Output banner and initial display output in VNC window
use VERSION file to generate FW version
cas: remove warning
Add support for loading little endian ELF binaries.
Add bswap_{16,32,64}p
dhcpv6 and other minor net-snk fixes
Fix missing drop in virtio-fs setup-alias
Find next available alias name
SLOF does not exit if given 1KB disk
boot: enable support for bootindex
pci-properties: add properties to enable hotplug for spapr
e1000: remember node handle
Increase quiesce tokens array size
virtio: timeout after 5sec
Enable IPv6 support in dns
usb-ohci: fix warnings
Add ipv6 support in net-snk
ipv4: fix frame overwriting following arp_send_request
e1000: fix SLOF_dma_map_out arguments
Maintain single global packet buffer for tftp
Increase virtio-net receive queue size
Increase veth receive queue size
Fix dprintf macros at various points
usb-ohci: rewrite done_head processing code
boot: add net in default boot order
block 0 address in the allocator
scsi: make-media-alias fix
usb-xhci: add xhci host controller support
usb-xhci: add xhci support
Avoid veth read/write calls with zero length buffer
boot: include other aliases
usb-core: disable xhci
>>
>>
>> Ping?
>
> Anthony / Stefan, could you please update the SLOF.git mirror on git.qemu.org?
It has been updated quite a while ago and it did not get included in
"[Qemu-devel] [PULL 00/130] ppc patch queue 2014-03-05" so I assume there
is something terribly wrong with it but what? Thanks.
--
Alexey
[Qemu-devel] [PULL 072/130] PPC: KVM: suppress warnings about not supported SPRs
From: Alexey Kardashevskiy
PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/kvm.c | 7 +++
trace-events | 2 ++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index e4a1a35..33d69d2 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -36,6 +36,7 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_vio.h"
#include "sysemu/watchdog.h"
+#include "trace.h"
//#define DEBUG_KVM
@@ -480,8 +481,7 @@ static void kvm_get_one_spr(CPUState *cs, uint64_t id, int
spr)
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret != 0) {
-fprintf(stderr, "Warning: Unable to retrieve SPR %d from KVM: %s\n",
-spr, strerror(errno));
+trace_kvm_failed_spr_get(spr, strerror(errno));
} else {
switch (id & KVM_REG_SIZE_MASK) {
case KVM_REG_SIZE_U32:
@@ -529,8 +529,7 @@ static void kvm_put_one_spr(CPUState *cs, uint64_t id, int
spr)
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret != 0) {
-fprintf(stderr, "Warning: Unable to set SPR %d to KVM: %s\n",
-spr, strerror(errno));
+trace_kvm_failed_spr_set(spr, strerror(errno));
}
}
diff --git a/trace-events b/trace-events
index d86f98c..bd9a1cf 100644
--- a/trace-events
+++ b/trace-events
@@ -1176,6 +1176,8 @@ kvm_vm_ioctl(int type, void *arg) "type 0x%x, arg %p"
kvm_vcpu_ioctl(int cpu_index, int type, void *arg) "cpu_index %d, type 0x%x,
arg %p"
kvm_run_exit(int cpu_index, uint32_t reason) "cpu_index %d, reason %d"
kvm_device_ioctl(int fd, int type, void *arg) "dev fd %d, type 0x%x, arg %p"
+kvm_failed_spr_set(int str, const char *msg) "Warning: Unable to set SPR %d to
KVM: %s"
+kvm_failed_spr_get(int str, const char *msg) "Warning: Unable to retrieve SPR
%d from KVM: %s"
# memory.c
memory_region_ops_read(void *mr, uint64_t addr, uint64_t value, unsigned size)
"mr %p addr %#"PRIx64" value %#"PRIx64" size %u"
--
1.8.1.4
[Qemu-devel] [PULL 025/130] target-ppc: Add VSX ISA2.06 xtdiv Instructions
From: Tom Musta
This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 67 +
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 +
3 files changed, 76 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 31669f1..ee03942 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2028,3 +2028,70 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1)
VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0)
VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0)
+
+static inline int ppc_float32_get_unbiased_exp(float32 f)
+{
+return ((f >> 23) & 0xFF) - 127;
+}
+
+static inline int ppc_float64_get_unbiased_exp(float64 f)
+{
+return ((f >> 52) & 0x7FF) - 1023;
+}
+
+/* VSX_TDIV - VSX floating point test for divide
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * emin - minimum unbiased exponent
+ * emax - maximum unbiased exponent
+ * nbits - number of fraction bits
+ */
+#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xa, xb; \
+int i; \
+int fe_flag = 0;\
+int fg_flag = 0;\
+\
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+\
+for (i = 0; i < nels; i++) {\
+if (unlikely(tp##_is_infinity(xa.fld[i]) || \
+ tp##_is_infinity(xb.fld[i]) || \
+ tp##_is_zero(xb.fld[i]))) {\
+fe_flag = 1;\
+fg_flag = 1;\
+} else {\
+int e_a = ppc_##tp##_get_unbiased_exp(xa.fld[i]); \
+int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
+\
+if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+fe_flag = 1;\
+} else if ((e_b <= emin) || (e_b >= (emax-2))) {\
+fe_flag = 1;\
+} else if (!tp##_is_zero(xa.fld[i]) && \
+ (((e_a - e_b) >= emax) ||\
+((e_a - e_b) <= (emin+1)) ||\
+ (e_a <= (emin+nbits { \
+fe_flag = 1;\
+} \
+\
+if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) {\
+/* XB is not zero because of the above check and */ \
+/* so must be denormalized. */ \
+fg_flag = 1;\
+} \
+} \
+} \
+\
+env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
+}
+
+VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
+VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
+VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4d5e31b..80cffc9 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -258,6 +258,7 @@ DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xssqrtdp, void, env, i32)
DEF_HELPER_2(xsrsqrtedp, void,
[Qemu-devel] [PULL 016/130] target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL
From: Alexey Kardashevskiy The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL -no32 S 152 00100 11000 CTRL yes-32 S According to this chart, the hypervisor's CTRL (#152) does not support reading, the user-space's CTRL (UCTRL, #136) does not support writing. This replaces unsupported operations with the default SPR_NOACCESS hook. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index d751fc3..02f5867 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6739,11 +6739,11 @@ static void init_proc_970FX (CPUPPCState *env) 0x); spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + SPR_NOACCESS, &spr_write_generic, 0x); spr_register(env, SPR_UCTRL, "SPR_UCTRL", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, SPR_NOACCESS, 0x); spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", &spr_read_generic, &spr_write_generic, @@ -6909,11 +6909,11 @@ static void init_proc_power5plus(CPUPPCState *env) 0x); spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + SPR_NOACCESS, &spr_write_generic, 0x); spr_register(env, SPR_UCTRL, "SPR_UCTRL", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, SPR_NOACCESS, 0x); spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", &spr_read_generic, &spr_write_generic, @@ -7014,11 +7014,11 @@ static void init_proc_POWER7 (CPUPPCState *env) /* XXX : not implemented */ spr_register(env, SPR_CTRL, "SPR_CTRLT", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + SPR_NOACCESS, &spr_write_generic, 0x8080); spr_register(env, SPR_UCTRL, "SPR_CTRLF", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, SPR_NOACCESS, 0x8080); spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", &spr_read_generic, &spr_write_generic, -- 1.8.1.4
[Qemu-devel] [PULL 092/130] target-ppc: Altivec 2.07: Update AVR Structure
From: Tom Musta
This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 88c2788..7ccf4c6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -352,6 +352,10 @@ union ppc_avr_t {
int16_t s16[8];
int32_t s32[4];
uint64_t u64[2];
+int64_t s64[2];
+#ifdef CONFIG_INT128
+__uint128_t u128;
+#endif
};
#if !defined(CONFIG_USER_ONLY)
--
1.8.1.4
[Qemu-devel] [PULL 006/130] target-ppc: remove unsupported SPRs from 970 and P5+
From: Alexey Kardashevskiy SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5 bookIV nor PowerISA 2.04, the numbers assigned to them are not defined either so remove them. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 39 --- 1 file changed, 39 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index d645b1b..f5a8490 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6644,20 +6644,10 @@ static void init_proc_970 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x); /* XXX : not implemented */ -spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); -/* XXX : not implemented */ spr_register(env, SPR_970_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, POWERPC970_HID5_INIT); -/* XXX : not implemented */ -spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x); /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); @@ -6734,20 +6724,10 @@ static void init_proc_970FX (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x); /* XXX : not implemented */ -spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); -/* XXX : not implemented */ spr_register(env, SPR_970_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, POWERPC970_HID5_INIT); -/* XXX : not implemented */ -spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x); /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); @@ -6836,20 +6816,11 @@ static void init_proc_970MP (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x); /* XXX : not implemented */ -spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); -/* XXX : not implemented */ spr_register(env, SPR_970_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, POWERPC970_HID5_INIT); /* XXX : not implemented */ -spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x); /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); @@ -6918,20 +6889,10 @@ static void init_proc_power5plus(CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x); /* XXX : not implemented */ -spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); -/* XXX : not implemented */ spr_register(env, SPR_970_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, POWERPC970_HID5_INIT); -/* XXX : not implemented */ -spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x); /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); -- 1.8.1.4
[Qemu-devel] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions
From: Tom Musta This patch adds the Vector Population Count instructions introduced in Power ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 4 target-ppc/int_helper.c | 14 ++ target-ppc/translate.c | 22 ++ 3 files changed, 36 insertions(+), 4 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 7ca219f..793877d 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -277,6 +277,10 @@ DEF_HELPER_2(vclzb, void, avr, avr) DEF_HELPER_2(vclzh, void, avr, avr) DEF_HELPER_2(vclzw, void, avr, avr) DEF_HELPER_2(vclzd, void, avr, avr) +DEF_HELPER_2(vpopcntb, void, avr, avr) +DEF_HELPER_2(vpopcnth, void, avr, avr) +DEF_HELPER_2(vpopcntw, void, avr, avr) +DEF_HELPER_2(vpopcntd, void, avr, avr) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 7fca9f0..3b67ae3 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1549,6 +1549,20 @@ VGENERIC_DO(clzd, u64) #undef clzw #undef clzd +#define popcntb(v) ctpop8(v) +#define popcnth(v) ctpop16(v) +#define popcntw(v) ctpop32(v) +#define popcntd(v) ctpop64(v) + +VGENERIC_DO(popcntb, u8) +VGENERIC_DO(popcnth, u16) +VGENERIC_DO(popcntw, u32) +VGENERIC_DO(popcntd, u64) + +#undef popcntb +#undef popcnth +#undef popcntw +#undef popcntd #undef VGENERIC_DO diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a1b85b5..e1f39e9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7287,6 +7287,19 @@ GEN_VXFORM_NOA(vclzb, 1, 28) GEN_VXFORM_NOA(vclzh, 1, 29) GEN_VXFORM_NOA(vclzw, 1, 30) GEN_VXFORM_NOA(vclzd, 1, 31) +GEN_VXFORM_NOA(vpopcntb, 1, 28) +GEN_VXFORM_NOA(vpopcnth, 1, 29) +GEN_VXFORM_NOA(vpopcntw, 1, 30) +GEN_VXFORM_NOA(vpopcntd, 1, 31) +GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ +vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ +vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ +vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ +vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) + /*** VSX extension ***/ static inline TCGv_i64 cpu_vsrh(int n) @@ -10508,10 +10521,11 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), -GEN_VXFORM_207(vclzb, 1, 28), -GEN_VXFORM_207(vclzh, 1, 29), -GEN_VXFORM_207(vclzw, 1, 30), -GEN_VXFORM_207(vclzd, 1, 31), +GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), + GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), -- 1.8.1.4
[Qemu-devel] [PULL 081/130] target-ppc: Fix xxpermdi When T==A or T==B
From: Tom Musta
The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR. This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 41 +
1 file changed, 33 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8885490..655aca6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7332,15 +7332,40 @@ static void gen_xxpermdi(DisasContext *ctx)
return;
}
-if ((DM(ctx->opcode) & 2) == 0) {
-tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
-} else {
-tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
-}
-if ((DM(ctx->opcode) & 1) == 0) {
-tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
+if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
+ (xT(ctx->opcode) == xB(ctx->opcode {
+TCGv_i64 xh, xl;
+
+xh = tcg_temp_new_i64();
+xl = tcg_temp_new_i64();
+
+if ((DM(ctx->opcode) & 2) == 0) {
+tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
+} else {
+tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
+}
+if ((DM(ctx->opcode) & 1) == 0) {
+tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
+} else {
+tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
+}
+
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
+
+tcg_temp_free_i64(xh);
+tcg_temp_free_i64(xl);
} else {
-tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
+if ((DM(ctx->opcode) & 2) == 0) {
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)),
cpu_vsrh(xA(ctx->opcode)));
+} else {
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)),
cpu_vsrl(xA(ctx->opcode)));
+}
+if ((DM(ctx->opcode) & 1) == 0) {
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)),
cpu_vsrh(xB(ctx->opcode)));
+} else {
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)),
cpu_vsrl(xB(ctx->opcode)));
+}
}
}
--
1.8.1.4
[Qemu-devel] [PULL 049/130] target-ppc: Floating Merge Word Instructions
From: Tom Musta
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 28
1 file changed, 28 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bc608ee..c6a357a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2294,6 +2294,32 @@ static void gen_fcpsgn(DisasContext *ctx)
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
+static void gen_fmrgew(DisasContext *ctx)
+{
+TCGv_i64 b0;
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+b0 = tcg_temp_new_i64();
+tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
+tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+b0, 0, 32);
+tcg_temp_free_i64(b0);
+}
+
+static void gen_fmrgow(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
+cpu_fpr[rB(ctx->opcode)],
+cpu_fpr[rA(ctx->opcode)],
+32, 32);
+}
+
/*** Floating-Point status & ctrl register***/
/* mcrfs */
@@ -9414,6 +9440,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F, PPC_FLOAT),
GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F, PPC_FLOAT),
GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F, PPC_FLOAT),
GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x0001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x0001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
--
1.8.1.4
Re: [Qemu-devel] [PATCH] build: Fix installation of target-dependent files
Lluís Vilanova writes: > Lluís Vilanova writes: >> Pass all the relevant sub-directory make variables. > Ping. Ping^2 > Thanks, > Lluis >> Signed-off-by: Lluís Vilanova >> --- >> Makefile |2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> diff --git a/Makefile b/Makefile >> index bdff4e4..02ae76d 100644 >> --- a/Makefile >> +++ b/Makefile >> @@ -366,7 +366,7 @@ endif >> $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x >> "$(DESTDIR)$(qemu_datadir)/keymaps"; \ >> done >> for d in $(TARGET_DIRS); do \ >> -$(MAKE) -C $$d $@ || exit 1 ; \ >> +$(MAKE) $(SUBDIR_MAKEFLAGS) TARGET_DIR=$$d/ -C $$d $@ || exit 1 ; \ >> done >> # various test targets -- "And it's much the same thing with knowledge, for whenever you learn something new, the whole world becomes that much richer." -- The Princess of Pure Reason, as told by Norton Juster in The Phantom Tollbooth
[Qemu-devel] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions
From: Tom Musta
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 31 +++
target-ppc/translate.c | 5 +
3 files changed, 37 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a09a618..52e49f1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -34,6 +34,7 @@ DEF_HELPER_3(mulldo, i64, env, i64, i64)
DEF_HELPER_4(divdeu, i64, env, i64, i64, i32)
DEF_HELPER_4(divde, i64, env, i64, i64, i32)
#endif
+DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 920dba7..45586be 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -41,6 +41,37 @@ uint64_t helper_mulldo(CPUPPCState *env, uint64_t arg1,
uint64_t arg2)
}
#endif
+target_ulong helper_divweu(CPUPPCState *env, target_ulong ra, target_ulong rb,
+ uint32_t oe)
+{
+uint64_t rt = 0;
+int overflow = 0;
+
+uint64_t dividend = (uint64_t)ra << 32;
+uint64_t divisor = (uint32_t)rb;
+
+if (unlikely(divisor == 0)) {
+overflow = 1;
+} else {
+rt = dividend / divisor;
+overflow = rt > UINT32_MAX;
+}
+
+if (unlikely(overflow)) {
+rt = 0; /* Undefined */
+}
+
+if (oe) {
+if (unlikely(overflow)) {
+env->so = env->ov = 1;
+} else {
+env->ov = 0;
+}
+}
+
+return (target_ulong)rt;
+}
+
#if defined(TARGET_PPC64)
uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7751b29..e361d49 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -998,6 +998,9 @@ static void gen_##name(DisasContext *ctx)
\
} \
}
+GEN_DIVE(divweu, divweu, 0);
+GEN_DIVE(divweuo, divweu, 1);
+
#if defined(TARGET_PPC64)
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -9716,6 +9719,8 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
+GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
+GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
#if defined(TARGET_PPC64)
#undef GEN_INT_ARITH_DIVD
--
1.8.1.4
Re: [Qemu-devel] [PATCH v3 3/3] hw/boards: converted current_machine to be an instance of MachineCLass
On 03/07/2014 10:44 AM, Andreas Färber wrote:
> Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
>> In order to allow attaching machine options to a machine instance,
>> current_machine is converted into MachineState.
>> As a first step of deprecating QEMUMachine, some of the functions
>> were modified to return MachineCLass.
>>
>> Signed-off-by: Marcel Apfelbaum
>
> Looks mostly good, but same issue as Alexey's patch: We are risking
> qdev_get_machine() creating a Container-typed /machine node.
Sorry, I am not following you here. object_resolve_path() can create objects?
> What about the following on top?
>
> Alexey, if we reach agreement here, this means for you that we can just
> use type_register_static() in place of qemu_machine_register() to
> register your custom machine type with interface added.
I am perfectly fine with that, I just do not see what difference does it
make and why do you still keep qemu_machine_register() (or this is in the
plan already?)?
> Regards,
> Andreas
>
> diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> index b6deebd..749c83a 100644
> --- a/hw/core/qdev.c
> +++ b/hw/core/qdev.c
> @@ -861,7 +861,8 @@ Object *qdev_get_machine(void)
> static Object *dev;
>
> if (dev == NULL) {
> -dev = container_get(object_get_root(), "/machine");
> +dev = object_resolve_path("/machine", NULL);
> +g_assert(dev);
> }
>
> return dev;
>
>
--
Alexey
[Qemu-devel] [PULL 061/130] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
From: Tom Musta
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 5 -
target-ppc/translate_init.c | 6 +++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index bf2b64f..1dbeb81 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1883,11 +1883,14 @@ enum {
PPC2_DIVE_ISA206 = 0x0100ULL,
/* ISA 2.06B larx/stcx. instructions */
PPC2_ATOMIC_ISA206 = 0x0200ULL,
+/* ISA 2.06B floating point integer conversion */
+PPC2_FP_CVT_ISA206 = 0x0400ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
-PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206)
+PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
+PPC2_FP_CVT_ISA206)
};
/*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index abe0a21..6dd0f84 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7070,7 +7070,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
pcc->msr_mask = 0x8284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7110,7 +7110,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
pcc->msr_mask = 0x8204FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7150,7 +7150,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
-PPC2_ATOMIC_ISA206;
+PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206;
pcc->msr_mask = 0x8284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.8.1.4
[Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers
From: Tom Musta
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.
This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type. This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/int_helper.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 3e36c0a..20d34e6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -983,28 +983,30 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a,
}
}
-#define VMUL_DO(name, mul_element, prod_element, evenp) \
+#define VMUL_DO(name, mul_element, prod_element, cast, evenp) \
void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
VECTOR_FOR_INORDER_I(i, prod_element) { \
if (evenp) {\
-r->prod_element[i] = a->mul_element[i * 2 + HI_IDX] * \
-b->mul_element[i * 2 + HI_IDX]; \
+r->prod_element[i] =\
+(cast)a->mul_element[i * 2 + HI_IDX] * \
+(cast)b->mul_element[i * 2 + HI_IDX]; \
} else {\
-r->prod_element[i] = a->mul_element[i * 2 + LO_IDX] * \
-b->mul_element[i * 2 + LO_IDX]; \
+r->prod_element[i] =\
+(cast)a->mul_element[i * 2 + LO_IDX] * \
+(cast)b->mul_element[i * 2 + LO_IDX]; \
} \
} \
}
-#define VMUL(suffix, mul_element, prod_element) \
-VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
-VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
-VMUL(sb, s8, s16)
-VMUL(sh, s16, s32)
-VMUL(ub, u8, u16)
-VMUL(uh, u16, u32)
+#define VMUL(suffix, mul_element, prod_element, cast)\
+VMUL_DO(mule##suffix, mul_element, prod_element, cast, 1)\
+VMUL_DO(mulo##suffix, mul_element, prod_element, cast, 0)
+VMUL(sb, s8, s16, int16_t)
+VMUL(sh, s16, s32, int32_t)
+VMUL(ub, u8, u16, uint16_t)
+VMUL(uh, u16, u32, uint32_t)
#undef VMUL_DO
#undef VMUL
--
1.8.1.4
Re: [Qemu-devel] [RFC PATCH V2 0/5] add direct support of event in qapi schema
于 2014/3/7 3:58, Luiz Capitulino 写道: On Thu, 06 Mar 2014 11:14:01 -0700 Eric Blake wrote: On 01/06/2014 04:18 PM, Luiz Capitulino wrote: On Fri, 3 Jan 2014 07:10:29 +0800 Wenchao Xia wrote: This series add support for tag/keyword 'event' in qapi-schema. A new file was created to store some helper functions in patch 2, patch 4 is the test case, patch 5 is a convert example. The implemention is done by generate API and a batch of parameters for each event define, it doesn't generate a struture and visit function in the background for every event, so it doesn't support nested structure in the define to avoid trouble. A callback layer is added to control the behavior. More detail can be found in patch 3's message and incode comments. The general approach seems good to me. Would be nice to get another reviewer though, maybe Eric and/or Michael. Just now looking at this thread. Is this still something that we want in 2.0, or at this point are we late enough to delay to 2.1? We could get this in if we get it posted and fully reviewed before hard freeze (which is on March 12). But I'd suggest postponing to 2.1. There is still something not solved perfectly, I'll update later,guess it can't catch up with 2.0.
Re: [Qemu-devel] [PATCH V9 07/10] qapi script: support enum type as discriminator in union
于 2014/3/6 21:03, Luiz Capitulino 写道:
On Thu, 06 Mar 2014 19:54:33 +0800
Wenchao Xia wrote:
于 2014/3/6 16:25, Markus Armbruster 写道:
Wenchao Xia writes:
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
is specified as a pre-defined enum type in schema. After this patch,
the pre-defined enum type will be really used as the switch case
condition in generated C code, if discriminator is an enum field.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
docs/qapi-code-gen.txt |8 -
scripts/qapi-types.py| 18 +---
scripts/qapi-visit.py| 29 +--
scripts/qapi.py | 32 +-
tests/Makefile |2 +-
tests/qapi-schema/flat-union-reverse-define.exit |1 +
tests/qapi-schema/flat-union-reverse-define.json | 17 +++
tests/qapi-schema/flat-union-reverse-define.out |9 ++
8 files changed, 99 insertions(+), 17 deletions(-)
create mode 100644 tests/qapi-schema/flat-union-reverse-define.err
create mode 100644 tests/qapi-schema/flat-union-reverse-define.exit
create mode 100644 tests/qapi-schema/flat-union-reverse-define.json
create mode 100644 tests/qapi-schema/flat-union-reverse-define.out
diff --git a/docs/qapi-code-gen.txt b/docs/qapi-code-gen.txt
index 0728f36..a2e7921 100644
--- a/docs/qapi-code-gen.txt
+++ b/docs/qapi-code-gen.txt
@@ -123,11 +123,15 @@ And it looks like this on the wire:
Flat union types avoid the nesting on the wire. They are used whenever a
specific field of the base type is declared as the discriminator ('type' is
-then no longer generated). The discriminator must always be a string field.
+then no longer generated). The discriminator can be a string field or a
+predefined enum field. If it is a string field, a hidden enum type will be
+generated as "[UNION_NAME]Kind". If it is an enum field, a compile time check
+will be done to verify the correctness. It is recommended to use an enum field.
The above example can then be modified as follows:
+ { 'enum': 'BlockdevDriver', 'data': [ 'raw', 'qcow2' ] }
{ 'type': 'BlockdevCommonOptions',
- 'data': { 'driver': 'str', 'readonly': 'bool' } }
+ 'data': { 'driver': 'BlockdevDriver', 'readonly': 'bool' } }
{ 'union': 'BlockdevOptions',
'base': 'BlockdevCommonOptions',
'discriminator': 'driver',
diff --git a/scripts/qapi-types.py b/scripts/qapi-types.py
index 5885bac..10864ef 100644
--- a/scripts/qapi-types.py
+++ b/scripts/qapi-types.py
@@ -201,14 +201,21 @@ def generate_union(expr):
base = expr.get('base')
discriminator = expr.get('discriminator')
+enum_define = discriminator_find_enum_define(expr)
+if enum_define:
+discriminator_type_name = enum_define['enum_name']
+else:
+discriminator_type_name = '%sKind' % (name)
+
ret = mcgen('''
struct %(name)s
{
-%(name)sKind kind;
+%(discriminator_type_name)s kind;
union {
void *data;
''',
-name=name)
+name=name,
+discriminator_type_name=discriminator_type_name)
for key in typeinfo:
ret += mcgen('''
@@ -389,8 +396,11 @@ for expr in exprs:
fdef.write(generate_enum_lookup(expr['enum'], expr['data']))
elif expr.has_key('union'):
ret += generate_fwd_struct(expr['union'], expr['data']) + "\n"
-ret += generate_enum('%sKind' % expr['union'], expr['data'].keys())
-fdef.write(generate_enum_lookup('%sKind' % expr['union'],
expr['data'].keys()))
+enum_define = discriminator_find_enum_define(expr)
+if not enum_define:
+ret += generate_enum('%sKind' % expr['union'], expr['data'].keys())
+fdef.write(generate_enum_lookup('%sKind' % expr['union'],
+expr['data'].keys()))
if expr.get('discriminator') == {}:
fdef.write(generate_anon_union_qtypes(expr))
else:
diff --git a/scripts/qapi-visit.py b/scripts/qapi-visit.py
index 0baaf60..45ce3a9 100644
--- a/scripts/qapi-visit.py
+++ b/scripts/qapi-visit.py
@@ -259,10 +259,16 @@ def generate_visit_union(expr):
assert not base
return generate_visit_anon_union(name, members)
-# There will always be a discriminator in the C switch code, by default it
-# is an enum type generated silently as "'%sKind' % (name)"
-ret = generate_visit_enum('%sKind' % name, members.keys())
-disc_type = '%sKind' % (name)
+enum_define = discriminator_find_enum_define(expr)
+if enum_define:
+# Use the enum type as discriminator
+ret = ""
+disc_type = enum_define['enum_name']
+else:
+# There will always be a discriminator in the C switch code, by
default it
+# is an en
[Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp
From: Tom Musta
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 13 +
target-ppc/helper.h | 1 +
target-ppc/translate.c | 2 ++
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index dc9849f..49cf09a 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1874,7 +1874,7 @@ VSX_MUL(xvmulsp, 4, float32, f32, 0, 0)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_DIV(op, nels, tp, fld, sfprf) \
+#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xa, xb; \
@@ -1903,6 +1903,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
} \
} \
\
+if (r2sp) { \
+xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+} \
+ \
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
} \
@@ -1912,9 +1916,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_DIV(xsdivdp, 1, float64, f64, 1)
-VSX_DIV(xvdivdp, 2, float64, f64, 0)
-VSX_DIV(xvdivsp, 4, float32, f32, 0)
+VSX_DIV(xsdivdp, 1, float64, f64, 1, 0)
+VSX_DIV(xsdivsp, 1, float64, f64, 1, 1)
+VSX_DIV(xvdivdp, 2, float64, f64, 0, 0)
+VSX_DIV(xvdivsp, 4, float32, f32, 0, 0)
/* VSX_RE - VSX floating point reciprocal estimate
* op- instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0ccdc96..308f97c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -289,6 +289,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
DEF_HELPER_2(xsmulsp, void, env, i32)
+DEF_HELPER_2(xsdivsp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 87817c2..dd4ddad 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7361,6 +7361,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10171,6 +10172,7 @@ GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
+GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
--
1.8.1.4
[Qemu-devel] [PATCH 07/10] qapi script: support enum type as discriminator in union
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
is specified as a pre-defined enum type in schema. After this patch,
the pre-defined enum type will be really used as the switch case
condition in generated C code, if discriminator is an enum field.
Signed-off-by: Wenchao Xia
---
docs/qapi-code-gen.txt |8 -
scripts/qapi-types.py| 18 ++---
scripts/qapi-visit.py| 29 +++---
scripts/qapi.py | 27 +++-
tests/Makefile |2 +-
tests/qapi-schema/flat-union-reverse-define.exit |1 +
tests/qapi-schema/flat-union-reverse-define.json | 17 +
tests/qapi-schema/flat-union-reverse-define.out |9 +++
8 files changed, 94 insertions(+), 17 deletions(-)
create mode 100644 tests/qapi-schema/flat-union-reverse-define.err
create mode 100644 tests/qapi-schema/flat-union-reverse-define.exit
create mode 100644 tests/qapi-schema/flat-union-reverse-define.json
create mode 100644 tests/qapi-schema/flat-union-reverse-define.out
diff --git a/docs/qapi-code-gen.txt b/docs/qapi-code-gen.txt
index 0728f36..a2e7921 100644
--- a/docs/qapi-code-gen.txt
+++ b/docs/qapi-code-gen.txt
@@ -123,11 +123,15 @@ And it looks like this on the wire:
Flat union types avoid the nesting on the wire. They are used whenever a
specific field of the base type is declared as the discriminator ('type' is
-then no longer generated). The discriminator must always be a string field.
+then no longer generated). The discriminator can be a string field or a
+predefined enum field. If it is a string field, a hidden enum type will be
+generated as "[UNION_NAME]Kind". If it is an enum field, a compile time check
+will be done to verify the correctness. It is recommended to use an enum field.
The above example can then be modified as follows:
+ { 'enum': 'BlockdevDriver', 'data': [ 'raw', 'qcow2' ] }
{ 'type': 'BlockdevCommonOptions',
- 'data': { 'driver': 'str', 'readonly': 'bool' } }
+ 'data': { 'driver': 'BlockdevDriver', 'readonly': 'bool' } }
{ 'union': 'BlockdevOptions',
'base': 'BlockdevCommonOptions',
'discriminator': 'driver',
diff --git a/scripts/qapi-types.py b/scripts/qapi-types.py
index 5885bac..10864ef 100644
--- a/scripts/qapi-types.py
+++ b/scripts/qapi-types.py
@@ -201,14 +201,21 @@ def generate_union(expr):
base = expr.get('base')
discriminator = expr.get('discriminator')
+enum_define = discriminator_find_enum_define(expr)
+if enum_define:
+discriminator_type_name = enum_define['enum_name']
+else:
+discriminator_type_name = '%sKind' % (name)
+
ret = mcgen('''
struct %(name)s
{
-%(name)sKind kind;
+%(discriminator_type_name)s kind;
union {
void *data;
''',
-name=name)
+name=name,
+discriminator_type_name=discriminator_type_name)
for key in typeinfo:
ret += mcgen('''
@@ -389,8 +396,11 @@ for expr in exprs:
fdef.write(generate_enum_lookup(expr['enum'], expr['data']))
elif expr.has_key('union'):
ret += generate_fwd_struct(expr['union'], expr['data']) + "\n"
-ret += generate_enum('%sKind' % expr['union'], expr['data'].keys())
-fdef.write(generate_enum_lookup('%sKind' % expr['union'],
expr['data'].keys()))
+enum_define = discriminator_find_enum_define(expr)
+if not enum_define:
+ret += generate_enum('%sKind' % expr['union'], expr['data'].keys())
+fdef.write(generate_enum_lookup('%sKind' % expr['union'],
+expr['data'].keys()))
if expr.get('discriminator') == {}:
fdef.write(generate_anon_union_qtypes(expr))
else:
diff --git a/scripts/qapi-visit.py b/scripts/qapi-visit.py
index 0baaf60..45ce3a9 100644
--- a/scripts/qapi-visit.py
+++ b/scripts/qapi-visit.py
@@ -259,10 +259,16 @@ def generate_visit_union(expr):
assert not base
return generate_visit_anon_union(name, members)
-# There will always be a discriminator in the C switch code, by default it
-# is an enum type generated silently as "'%sKind' % (name)"
-ret = generate_visit_enum('%sKind' % name, members.keys())
-disc_type = '%sKind' % (name)
+enum_define = discriminator_find_enum_define(expr)
+if enum_define:
+# Use the enum type as discriminator
+ret = ""
+disc_type = enum_define['enum_name']
+else:
+# There will always be a discriminator in the C switch code, by
default it
+# is an enum type generated silently as "'%sKind' % (name)"
+ret = generate_visit_enum('%sKind' % name, members.keys())
+disc_type = '%sKind' % (name)
if base:
base_fields = find_struct(base
[Qemu-devel] [PULL 077/130] spapr: print more detailed error message on failed load_elf()
From: Alexey Kardashevskiy
This makes use of new error codes which load_elf() can return and
prints more informative error message.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 851ce4b..c9dfc6c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1306,15 +1306,15 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
-if (kernel_size < 0) {
+if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
kernel_size = load_elf(kernel_filename,
translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0);
kernel_le = kernel_size > 0;
}
if (kernel_size < 0) {
-fprintf(stderr, "qemu: could not load kernel '%s'\n",
-kernel_filename);
+fprintf(stderr, "qemu: error loading %s: %s\n",
+kernel_filename, load_elf_strerror(kernel_size));
exit(1);
}
--
1.8.1.4
[Qemu-devel] [PULL 109/130] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions
From: Tom Musta This patch adds the vector doublword rotate and shift instructions introduced in Power ISA Version 2.07: - Vector Rotate Left Doubleword instruction (vrld) - Vector Shift Left Doubleword (vsld) - Vector Shift Right Doubleword (vsrd) - Vector Shift Right Algegbraic Doubleword (vsrad) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/helper.h | 4 target-ppc/int_helper.c | 4 target-ppc/translate.c | 8 3 files changed, 16 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 6a7e99f..3201268 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -184,12 +184,15 @@ DEF_HELPER_3(vmuluwm, void, avr, avr, avr) DEF_HELPER_3(vsrab, void, avr, avr, avr) DEF_HELPER_3(vsrah, void, avr, avr, avr) DEF_HELPER_3(vsraw, void, avr, avr, avr) +DEF_HELPER_3(vsrad, void, avr, avr, avr) DEF_HELPER_3(vsrb, void, avr, avr, avr) DEF_HELPER_3(vsrh, void, avr, avr, avr) DEF_HELPER_3(vsrw, void, avr, avr, avr) +DEF_HELPER_3(vsrd, void, avr, avr, avr) DEF_HELPER_3(vslb, void, avr, avr, avr) DEF_HELPER_3(vslh, void, avr, avr, avr) DEF_HELPER_3(vslw, void, avr, avr, avr) +DEF_HELPER_3(vsld, void, avr, avr, avr) DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) DEF_HELPER_3(vaddcuw, void, avr, avr, avr) @@ -211,6 +214,7 @@ DEF_HELPER_4(vsubuws, void, env, avr, avr, avr) DEF_HELPER_3(vrlb, void, avr, avr, avr) DEF_HELPER_3(vrlh, void, avr, avr, avr) DEF_HELPER_3(vrlw, void, avr, avr, avr) +DEF_HELPER_3(vrld, void, avr, avr, avr) DEF_HELPER_3(vsl, void, avr, avr, avr) DEF_HELPER_3(vsr, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 59b5a1f..b4a7298 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1142,6 +1142,7 @@ VRFI(z, float_round_to_zero) VROTATE(b, u8, 0x7) VROTATE(h, u16, 0xF) VROTATE(w, u32, 0x1F) +VROTATE(d, u64, 0x3F) #undef VROTATE void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) @@ -1236,6 +1237,7 @@ VSHIFT(r, RIGHT) VSL(b, u8, 0x7) VSL(h, u16, 0x0F) VSL(w, u32, 0x1F) +VSL(d, u64, 0x3F) #undef VSL void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift) @@ -1332,9 +1334,11 @@ VSPLTI(w, s32, int32_t) VSR(ab, s8, 0x7) VSR(ah, s16, 0xF) VSR(aw, s32, 0x1F) +VSR(ad, s64, 0x3F) VSR(b, u8, 0x7) VSR(h, u16, 0xF) VSR(w, u32, 0x1F) +VSR(d, u64, 0x3F) #undef VSR void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ec32771..3d38a25 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7018,12 +7018,15 @@ GEN_VXFORM(vmulesw, 4, 14); GEN_VXFORM(vslb, 2, 4); GEN_VXFORM(vslh, 2, 5); GEN_VXFORM(vslw, 2, 6); +GEN_VXFORM(vsld, 2, 23); GEN_VXFORM(vsrb, 2, 8); GEN_VXFORM(vsrh, 2, 9); GEN_VXFORM(vsrw, 2, 10); +GEN_VXFORM(vsrd, 2, 27); GEN_VXFORM(vsrab, 2, 12); GEN_VXFORM(vsrah, 2, 13); GEN_VXFORM(vsraw, 2, 14); +GEN_VXFORM(vsrad, 2, 15); GEN_VXFORM(vslo, 6, 16); GEN_VXFORM(vsro, 6, 17); GEN_VXFORM(vaddcuw, 0, 6); @@ -7043,6 +7046,7 @@ GEN_VXFORM_ENV(vsubsws, 0, 30); GEN_VXFORM(vrlb, 2, 0); GEN_VXFORM(vrlh, 2, 1); GEN_VXFORM(vrlw, 2, 2); +GEN_VXFORM(vrld, 2, 3); GEN_VXFORM(vsl, 2, 7); GEN_VXFORM(vsr, 2, 11); GEN_VXFORM_ENV(vpkuhum, 7, 0); @@ -10459,12 +10463,15 @@ GEN_VXFORM_207(vmulesw, 4, 14), GEN_VXFORM(vslb, 2, 4), GEN_VXFORM(vslh, 2, 5), GEN_VXFORM(vslw, 2, 6), +GEN_VXFORM_207(vsld, 2, 23), GEN_VXFORM(vsrb, 2, 8), GEN_VXFORM(vsrh, 2, 9), GEN_VXFORM(vsrw, 2, 10), +GEN_VXFORM_207(vsrd, 2, 27), GEN_VXFORM(vsrab, 2, 12), GEN_VXFORM(vsrah, 2, 13), GEN_VXFORM(vsraw, 2, 14), +GEN_VXFORM_207(vsrad, 2, 15), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), GEN_VXFORM(vaddcuw, 0, 6), @@ -10484,6 +10491,7 @@ GEN_VXFORM(vsubsws, 0, 30), GEN_VXFORM(vrlb, 2, 0), GEN_VXFORM(vrlh, 2, 1), GEN_VXFORM(vrlw, 2, 2), +GEN_VXFORM_207(vrld, 2, 3), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0), -- 1.8.1.4
[Qemu-devel] [PULL 084/130] target-ppc: Add bctar Instruction
From: Tom Musta
This patch adds the Branch Conditional to Address Register (bctar)
instruction.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 655aca6..6abe71a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3745,6 +3745,7 @@ static void gen_b(DisasContext *ctx)
#define BCOND_IM 0
#define BCOND_LR 1
#define BCOND_CTR 2
+#define BCOND_TAR 3
static inline void gen_bcond(DisasContext *ctx, int type)
{
@@ -3753,10 +3754,12 @@ static inline void gen_bcond(DisasContext *ctx, int
type)
TCGv target;
ctx->exception = POWERPC_EXCP_BRANCH;
-if (type == BCOND_LR || type == BCOND_CTR) {
+if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new();
if (type == BCOND_CTR)
tcg_gen_mov_tl(target, cpu_ctr);
+else if (type == BCOND_TAR)
+gen_load_spr(target, SPR_TAR);
else
tcg_gen_mov_tl(target, cpu_lr);
} else {
@@ -3838,6 +3841,11 @@ static void gen_bclr(DisasContext *ctx)
gen_bcond(ctx, BCOND_LR);
}
+static void gen_bctar(DisasContext *ctx)
+{
+gen_bcond(ctx, BCOND_TAR);
+}
+
/*** Condition register logical ***/
#define GEN_CRLOGIC(name, tcg_op, opc)\
static void glue(gen_, name)(DisasContext *ctx)
\
@@ -9594,6 +9602,7 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x, PPC_FLOW),
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x, PPC_FLOW),
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x, PPC_FLOW),
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x, PPC_FLOW),
+GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x0001, PPC_INTEGER),
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
#if defined(TARGET_PPC64)
--
1.8.1.4
[Qemu-devel] [PULL 005/130] target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
From: Alexey Kardashevskiy PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so remove it from POWER7/8 class as it is "S" (server) category. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 46 - 1 file changed, 46 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index df8b4b1..d645b1b 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6661,16 +6661,6 @@ static void init_proc_970 (CPUPPCState *env) /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); -/* XXX : not implemented */ -spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x); /* TOFIX */ -/* XXX : not implemented */ -spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); /* TOFIX */ spr_register(env, SPR_HIOR, "SPR_HIOR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, @@ -6761,16 +6751,6 @@ static void init_proc_970FX (CPUPPCState *env) /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); -/* XXX : not implemented */ -spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x); /* TOFIX */ -/* XXX : not implemented */ -spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); /* TOFIX */ spr_register(env, SPR_HIOR, "SPR_HIOR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, @@ -6873,16 +6853,6 @@ static void init_proc_970MP (CPUPPCState *env) /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); -/* XXX : not implemented */ -spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x); /* TOFIX */ -/* XXX : not implemented */ -spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); /* TOFIX */ spr_register(env, SPR_HIOR, "SPR_HIOR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, @@ -6965,16 +6935,6 @@ static void init_proc_power5plus(CPUPPCState *env) /* Memory management */ /* XXX: not correct */ gen_low_BATs(env); -/* XXX : not implemented */ -spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x); /* TOFIX */ -/* XXX : not implemented */ -spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x); /* TOFIX */ spr_register(env, SPR_HIOR, "SPR_HIOR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, @@ -7077,12 +7037,6 @@ static void init_proc_POWER7 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, KVM_REG_PPC_PMC6, 0x); #endif /* !CONFIG_USER_ONLY */ -/* Memory management */ -/* XXX : not implemented */ -spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x); /* TOFIX */ gen_spr_amr(env); /* XXX : not implemented */ spr_register(env, SPR_CTRL, "SPR_CTRLT", -- 1.8.1.4
[Qemu-devel] [PULL 066/130] target-ppc: Add ISA 2.06 ftdiv Instruction
From: Tom Musta
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 56 -
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 13
3 files changed, 61 insertions(+), 10 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 87ff60f..772b135 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -50,6 +50,16 @@ static inline int isden(float64 d)
return ((u.ll >> 52) & 0x7FF) == 0;
}
+static inline int ppc_float32_get_unbiased_exp(float32 f)
+{
+return ((f >> 23) & 0xFF) - 127;
+}
+
+static inline int ppc_float64_get_unbiased_exp(float64 f)
+{
+return ((f >> 52) & 0x7FF) - 1023;
+}
+
uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
{
CPU_DoubleU farg;
@@ -993,6 +1003,42 @@ uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
}
}
+uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
+{
+int fe_flag = 0;
+int fg_flag = 0;
+
+if (unlikely(float64_is_infinity(fra) ||
+ float64_is_infinity(frb) ||
+ float64_is_zero(frb))) {
+fe_flag = 1;
+fg_flag = 1;
+} else {
+int e_a = ppc_float64_get_unbiased_exp(fra);
+int e_b = ppc_float64_get_unbiased_exp(frb);
+
+if (unlikely(float64_is_any_nan(fra) ||
+ float64_is_any_nan(frb))) {
+fe_flag = 1;
+} else if ((e_b <= -1022) || (e_b >= 1021)) {
+fe_flag = 1;
+} else if (!float64_is_zero(fra) &&
+ (((e_a - e_b) >= 1023) ||
+((e_a - e_b) <= -1021) ||
+(e_a <= -970))) {
+fe_flag = 1;
+}
+
+if (unlikely(float64_is_zero_or_denormal(frb))) {
+/* XB is not zero because of the above check and */
+/* so must be denormalized. */
+fg_flag = 1;
+}
+}
+
+return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+}
+
void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint32_t crfD)
{
@@ -2021,16 +2067,6 @@ VSX_RSQRTE(xsrsqrtesp, 1, float64, f64, 1, 1)
VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0, 0)
VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0, 0)
-static inline int ppc_float32_get_unbiased_exp(float32 f)
-{
-return ((f >> 23) & 0xFF) - 127;
-}
-
-static inline int ppc_float64_get_unbiased_exp(float64 f)
-{
-return ((f >> 52) & 0x7FF) - 1023;
-}
-
/* VSX_TDIV - VSX floating point test for divide
* op- instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index c7c915f..2fb337c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -99,6 +99,8 @@ DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64)
+
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
#define dh_is_signed_avr dh_is_signed_ptr
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4c08fe5..f372742 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2238,6 +2238,18 @@ GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
/* frim */
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
+static void gen_ftdiv(DisasContext *ctx)
+{
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+ cpu_fpr[rB(ctx->opcode)]);
+}
+
+
+
/*** Floating-Point compare***/
/* fcmpo */
@@ -9856,6 +9868,7 @@ GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
+GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
--
1.8.1.4
[Qemu-devel] [PULL 076/130] elf-loader: add more return codes
From: Alexey Kardashevskiy
The existing load_elf() just returns -1 if it fails to load ELF. However
it could be smarter than this and tell more about the failure such as
wrong endianness or incompatible platform.
This adds additional return codes for wrong architecture, wrong
endianness and if the image is not ELF at all.
This adds a load_elf_strerror() helper to convert return codes into
string messages.
This fixes handling of what load_elf() returns for s390x, other
callers just check the return value for <0 and this remains unchanged.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/core/loader.c | 30 --
hw/s390x/ipl.c | 4 ++--
include/hw/elf_ops.h | 19 ++-
include/hw/loader.h | 6 ++
4 files changed, 46 insertions(+), 13 deletions(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index e1c3f3a..b323c0c 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -284,12 +284,30 @@ static void *load_at(int fd, int offset, int size)
#define SZ 64
#include "hw/elf_ops.h"
+const char *load_elf_strerror(int error)
+{
+switch (error) {
+case 0:
+return "No error";
+case ELF_LOAD_FAILED:
+return "Failed to load ELF";
+case ELF_LOAD_NOT_ELF:
+return "The image is not ELF";
+case ELF_LOAD_WRONG_ARCH:
+return "The image is from incompatible architecture";
+case ELF_LOAD_WRONG_ENDIAN:
+return "The image has incorrect endianness";
+default:
+return "Unknown error";
+}
+}
+
/* return < 0 if error, otherwise the number of bytes loaded in memory */
int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
uint64_t *highaddr, int big_endian, int elf_machine, int
clear_lsb)
{
-int fd, data_order, target_data_order, must_swab, ret;
+int fd, data_order, target_data_order, must_swab, ret = ELF_LOAD_FAILED;
uint8_t e_ident[EI_NIDENT];
fd = open(filename, O_RDONLY | O_BINARY);
@@ -302,8 +320,10 @@ int load_elf(const char *filename, uint64_t
(*translate_fn)(void *, uint64_t),
if (e_ident[0] != ELFMAG0 ||
e_ident[1] != ELFMAG1 ||
e_ident[2] != ELFMAG2 ||
-e_ident[3] != ELFMAG3)
+e_ident[3] != ELFMAG3) {
+ret = ELF_LOAD_NOT_ELF;
goto fail;
+}
#ifdef HOST_WORDS_BIGENDIAN
data_order = ELFDATA2MSB;
#else
@@ -317,6 +337,7 @@ int load_elf(const char *filename, uint64_t
(*translate_fn)(void *, uint64_t),
}
if (target_data_order != e_ident[EI_DATA]) {
+ret = ELF_LOAD_WRONG_ENDIAN;
goto fail;
}
@@ -329,12 +350,9 @@ int load_elf(const char *filename, uint64_t
(*translate_fn)(void *, uint64_t),
pentry, lowaddr, highaddr, elf_machine, clear_lsb);
}
-close(fd);
-return ret;
-
fail:
close(fd);
-return -1;
+return ret;
}
static void bswap_uboot_header(uboot_image_header_t *hdr)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 04fb1a8..32d38a0 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -98,10 +98,10 @@ static int s390_ipl_init(SysBusDevice *dev)
uint64_t pentry = KERN_IMAGE_START;
kernel_size = load_elf(ipl->kernel, NULL, NULL, &pentry, NULL,
NULL, 1, ELF_MACHINE, 0);
-if (kernel_size == -1) {
+if (kernel_size < 0) {
kernel_size = load_image_targphys(ipl->kernel, 0, ram_size);
}
-if (kernel_size == -1) {
+if (kernel_size < 0) {
fprintf(stderr, "could not load kernel '%s'\n", ipl->kernel);
return -1;
}
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index acc701e..c6b5129 100644
--- a/include/hw/elf_ops.h
+++ b/include/hw/elf_ops.h
@@ -201,6 +201,7 @@ static int glue(load_elf, SZ)(const char *name, int fd,
uint64_t addr, low = (uint64_t)-1, high = 0;
uint8_t *data = NULL;
char label[128];
+int ret = ELF_LOAD_FAILED;
if (read(fd, &ehdr, sizeof(ehdr)) != sizeof(ehdr))
goto fail;
@@ -211,22 +212,30 @@ static int glue(load_elf, SZ)(const char *name, int fd,
switch (elf_machine) {
case EM_PPC64:
if (EM_PPC64 != ehdr.e_machine)
-if (EM_PPC != ehdr.e_machine)
+if (EM_PPC != ehdr.e_machine) {
+ret = ELF_LOAD_WRONG_ARCH;
goto fail;
+}
break;
case EM_X86_64:
if (EM_X86_64 != ehdr.e_machine)
-if (EM_386 != ehdr.e_machine)
+if (EM_386 != ehdr.e_machine) {
+ret = ELF_LOAD_WRONG_ARCH;
goto fail;
+}
break;
case EM_MICROBLAZE:
if (EM_MICROBLAZE != ehdr.e_machine)
-if (EM_MICROBLAZE_OLD != ehdr.e_machi
