Re: [Qemu-devel] [PATCH COLO-Frame v11 08/39] migration: Rename the'file' member of MigrationState

[Wen Congyang]

On 11/24/2015 05:25 PM, zhanghailiang wrote:
> Rename the 'file' member of MigrationState to 'to_dst_file'.
> 
> Signed-off-by: zhanghailiang 
> Cc: Dr. David Alan Gilbert 
> ---
> v11:
> - Only rename 'file' member of MigrationState

You forgot to update migration/rdma.c.

Thanks
Wen Congyang

> ---
>  include/migration/migration.h |  2 +-
>  migration/exec.c  |  4 +--
>  migration/fd.c|  4 +--
>  migration/migration.c | 72 
> ++-
>  migration/postcopy-ram.c  |  6 ++--
>  migration/savevm.c|  2 +-
>  migration/tcp.c   |  4 +--
>  migration/unix.c  |  4 +--
>  8 files changed, 51 insertions(+), 47 deletions(-)
> 
> diff --git a/include/migration/migration.h b/include/migration/migration.h
> index a57a734..ba5bcec 100644
> --- a/include/migration/migration.h
> +++ b/include/migration/migration.h
> @@ -140,7 +140,7 @@ struct MigrationState
>  size_t xfer_limit;
>  QemuThread thread;
>  QEMUBH *cleanup_bh;
> -QEMUFile *file;
> +QEMUFile *to_dst_file;
>  int parameters[MIGRATION_PARAMETER_MAX];
>  
>  int state;
> diff --git a/migration/exec.c b/migration/exec.c
> index 8406d2b..9037109 100644
> --- a/migration/exec.c
> +++ b/migration/exec.c
> @@ -36,8 +36,8 @@
>  
>  void exec_start_outgoing_migration(MigrationState *s, const char *command, 
> Error **errp)
>  {
> -s->file = qemu_popen_cmd(command, "w");
> -if (s->file == NULL) {
> +s->to_dst_file = qemu_popen_cmd(command, "w");
> +if (s->to_dst_file == NULL) {
>  error_setg_errno(errp, errno, "failed to popen the migration 
> target");
>  return;
>  }
> diff --git a/migration/fd.c b/migration/fd.c
> index 3e4bed0..9a9d6c5 100644
> --- a/migration/fd.c
> +++ b/migration/fd.c
> @@ -50,9 +50,9 @@ void fd_start_outgoing_migration(MigrationState *s, const 
> char *fdname, Error **
>  }
>  
>  if (fd_is_socket(fd)) {
> -s->file = qemu_fopen_socket(fd, "wb");
> +s->to_dst_file = qemu_fopen_socket(fd, "wb");
>  } else {
> -s->file = qemu_fdopen(fd, "wb");
> +s->to_dst_file = qemu_fdopen(fd, "wb");
>  }
>  
>  migrate_fd_connect(s);
> diff --git a/migration/migration.c b/migration/migration.c
> index 41eac0d..a4c690d 100644
> --- a/migration/migration.c
> +++ b/migration/migration.c
> @@ -834,7 +834,7 @@ static void migrate_fd_cleanup(void *opaque)
>  
>  flush_page_queue(s);
>  
> -if (s->file) {
> +if (s->to_dst_file) {
>  trace_migrate_fd_cleanup();
>  qemu_mutex_unlock_iothread();
>  if (s->migration_thread_running) {
> @@ -844,8 +844,8 @@ static void migrate_fd_cleanup(void *opaque)
>  qemu_mutex_lock_iothread();
>  
>  migrate_compress_threads_join();
> -qemu_fclose(s->file);
> -s->file = NULL;
> +qemu_fclose(s->to_dst_file);
> +s->to_dst_file = NULL;
>  }
>  
>  assert((s->state != MIGRATION_STATUS_ACTIVE) &&
> @@ -862,7 +862,7 @@ static void migrate_fd_cleanup(void *opaque)
>  void migrate_fd_error(MigrationState *s)
>  {
>  trace_migrate_fd_error();
> -assert(s->file == NULL);
> +assert(s->to_dst_file == NULL);
>  migrate_set_state(&s->state, MIGRATION_STATUS_SETUP,
>MIGRATION_STATUS_FAILED);
>  notifier_list_notify(&migration_state_notifiers, s);
> @@ -871,7 +871,7 @@ void migrate_fd_error(MigrationState *s)
>  static void migrate_fd_cancel(MigrationState *s)
>  {
>  int old_state ;
> -QEMUFile *f = migrate_get_current()->file;
> +QEMUFile *f = migrate_get_current()->to_dst_file;
>  trace_migrate_fd_cancel();
>  
>  if (s->rp_state.from_dst_file) {
> @@ -942,7 +942,7 @@ MigrationState *migrate_init(const MigrationParams 
> *params)
>  s->bytes_xfer = 0;
>  s->xfer_limit = 0;
>  s->cleanup_bh = 0;
> -s->file = NULL;
> +s->to_dst_file = NULL;
>  s->state = MIGRATION_STATUS_NONE;
>  s->params = *params;
>  s->rp_state.from_dst_file = NULL;
> @@ -1122,8 +1122,9 @@ void qmp_migrate_set_speed(int64_t value, Error **errp)
>  
>  s = migrate_get_current();
>  s->bandwidth_limit = value;
> -if (s->file) {
> -qemu_file_set_rate_limit(s->file, s->bandwidth_limit / 
> XFER_LIMIT_RATIO);
> +if (s->to_dst_file) {
> +qemu_file_set_rate_limit(s->to_dst_file,
> + s->bandwidth_limit / XFER_LIMIT_RATIO);
>  }
>  }
>  
> @@ -1393,7 +1394,7 @@ out:
>  static int open_return_path_on_source(MigrationState *ms)
>  {
>  
> -ms->rp_state.from_dst_file = qemu_file_get_return_path(ms->file);
> +ms->rp_state.from_dst_file = qemu_file_get_return_path(ms->to_dst_file);
>  if (!ms->rp_state.from_dst_file) {
>  return -1;
>  }
> @@ -1415,7 +1416,7 @@ static int 
> await_return_path_close_on_source(MigrationState *ms)
>   * rp_thread will exit, however if there's an error we need to 

[Qemu-devel] [RFC PATCH v0 6/9] cpu: Introduce CPU core device

[Bharata B Rao]

CPU core device is a container of CPU thread devices. Core device links
to the backend socket object. All the cores within a socket defined
in the topology specification will link to the same socket object.
CPU hotplug is performed in the granularity of CPU core device.
When hotplugged, CPU core creates CPU thread devices.

Signed-off-by: Bharata B Rao 
---
 hw/cpu/Makefile.objs  |  2 +-
 hw/cpu/core.c | 98 +++
 include/hw/cpu/core.h | 28 +++
 3 files changed, 127 insertions(+), 1 deletion(-)
 create mode 100644 hw/cpu/core.c
 create mode 100644 include/hw/cpu/core.h

diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs
index 93d1226..de5c313 100644
--- a/hw/cpu/Makefile.objs
+++ b/hw/cpu/Makefile.objs
@@ -2,5 +2,5 @@ obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o
 obj-$(CONFIG_REALVIEW) += realview_mpcore.o
 obj-$(CONFIG_A9MPCORE) += a9mpcore.o
 obj-$(CONFIG_A15MPCORE) += a15mpcore.o
-obj-y += socket.o
+obj-y += socket.o core.o
 
diff --git a/hw/cpu/core.c b/hw/cpu/core.c
new file mode 100644
index 000..d14bd77
--- /dev/null
+++ b/hw/cpu/core.c
@@ -0,0 +1,98 @@
+/*
+ * CPU core device, acts as container of CPU thread devices.
+ *
+ * Copyright (C) 2015 Bharata B Rao 
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw/cpu/core.h"
+#include "hw/boards.h"
+#include 
+#include "qemu/error-report.h"
+
+static int cpu_core_realize_child(Object *child, void *opaque)
+{
+Error **errp = opaque;
+
+object_property_set_bool(child, true, "realized", errp);
+if (*errp) {
+return 1;
+}
+
+return 0;
+}
+
+static void cpu_core_realize(DeviceState *dev, Error **errp)
+{
+CPUCore *core = CPU_CORE(OBJECT(dev));
+
+if (!core->socket) {
+error_setg(errp, "'" CPU_CORE_SOCKET_PROP "' property is not set");
+return;
+}
+object_child_foreach(OBJECT(dev), cpu_core_realize_child, errp);
+}
+
+static void cpu_core_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = cpu_core_realize;
+}
+
+static void cpu_core_check_socket_is_full(Object *obj, const char *name,
+  Object *val, Error **errp)
+{
+CPUSocket *socket = CPU_SOCKET(val);
+
+if (socket->nr_cores == smp_cores) {
+char *path = object_get_canonical_path_component(val);
+error_setg(errp, "Socket already full: %s", path);
+g_free(path);
+} else {
+socket->nr_cores++;
+qdev_prop_allow_set_link_before_realize(obj, name, val, errp);
+}
+}
+
+static void cpu_core_instance_init(Object *obj)
+{
+int i;
+CPUState *cpu;
+MachineState *machine = MACHINE(qdev_get_machine());
+CPUCore *core = CPU_CORE(obj);
+
+object_property_add_link(obj, CPU_CORE_SOCKET_PROP, TYPE_CPU_SOCKET,
+ (Object **)&core->socket,
+ cpu_core_check_socket_is_full,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+
+/* Create as many CPU threads as specified in the topology */
+for (i = 0; i < smp_threads; i++) {
+cpu = cpu_generic_init(machine->cpu_type, machine->cpu_model);
+if (!cpu) {
+error_report("Unable to find CPU definition: %s\n",
+  machine->cpu_model);
+exit(EXIT_FAILURE);
+}
+object_property_add_child(obj, "thread[*]", OBJECT(cpu), &error_abort);
+object_unref(OBJECT(cpu));
+}
+}
+
+static const TypeInfo cpu_core_type_info = {
+.name = TYPE_CPU_CORE,
+.parent = TYPE_DEVICE,
+.class_init = cpu_core_class_init,
+.instance_init = cpu_core_instance_init,
+.instance_size = sizeof(CPUCore),
+};
+
+static void cpu_core_register_types(void)
+{
+type_register_static(&cpu_core_type_info);
+}
+
+type_init(cpu_core_register_types)
diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h
new file mode 100644
index 000..0314098
--- /dev/null
+++ b/include/hw/cpu/core.h
@@ -0,0 +1,28 @@
+/*
+ * CPU core device.
+ *
+ * Copyright (C) 2015 Bharata B Rao 
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef HW_CPU_CORE_H
+#define HW_CPU_CORE_H
+
+#include "hw/qdev.h"
+#include "hw/cpu/socket.h"
+
+#define TYPE_CPU_CORE "cpu-core"
+#define CPU_CORE(obj) \
+OBJECT_CHECK(CPUCore, (obj), TYPE_CPU_CORE)
+
+#define CPU_CORE_SOCKET_PROP "socket"
+
+typedef struct CPUCore {
+/*< private >*/
+DeviceState parent_obj;
+/*< public >*/
+CPUSocket *socket;
+} CPUCore;
+
+#endif
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 9/9] pc: Convert boot CPUs into CPU core device initialization

[Bharata B Rao]

Initialize boot CPUs specified with -smp option as CPU core devices.

Signed-off-by: Bharata B Rao 
---
 hw/i386/pc.c | 30 +-
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 80a4d98..661e577 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -65,6 +65,7 @@
 #include "hw/mem/pc-dimm.h"
 #include "qapi/visitor.h"
 #include "qapi-visit.h"
+#include "hw/cpu/core.h"
 
 /* debug PC/ISA interrupts */
 //#define DEBUG_IRQ
@@ -1086,11 +1087,10 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
 
 void pc_cpus_init(PCMachineState *pcms)
 {
-int i;
-X86CPU *cpu = NULL;
+int i, j;
 MachineState *machine = MACHINE(pcms);
-Error *error = NULL;
 unsigned long apic_id_limit;
+int sockets = DIV_ROUND_UP(smp_cpus, smp_cores * smp_threads);
 
 /* init CPUs */
 if (machine->cpu_model == NULL) {
@@ -1109,18 +1109,17 @@ void pc_cpus_init(PCMachineState *pcms)
 exit(1);
 }
 
-for (i = 0; i < smp_cpus; i++) {
-cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i),
- &error);
-if (error) {
-error_report_err(error);
-exit(1);
+for (i = 0; i < sockets; i++) {
+char sid[32];
+
+snprintf(sid, 32, "" TYPE_CPU_SOCKET "%d", i);
+for (j = 0; j < smp_cores; j++) {
+Object *core = object_new(TYPE_CPU_CORE);
+
+object_property_set_str(core, sid, "socket", &error_abort);
+object_property_set_bool(core, true, "realized", &error_abort);
 }
-object_unref(OBJECT(cpu));
 }
-
-/* tell smbios about cpuid version and features */
-smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 }
 
 /* pci-info ROM file. Little endian format */
@@ -1660,6 +1659,11 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
 HotplugHandlerClass *hhc;
 Error *local_err = NULL;
 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+CPUState *cs = CPU(dev);
+X86CPU *cpu = X86_CPU(cs);
+
+/* tell smbios about cpuid version and features */
+smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 
 if (!dev->hotplugged) {
 goto out;
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 5/9] vl: Create CPU socket backend objects

[Bharata B Rao]

Create as many CPU socket objects as necessary to contain the
max_cpus.

Signed-off-by: Bharata B Rao 
---
 vl.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/vl.c b/vl.c
index e656f53..83d08c6 100644
--- a/vl.c
+++ b/vl.c
@@ -124,6 +124,7 @@ int main(int argc, char **argv)
 #include "crypto/init.h"
 #include "sysemu/replay.h"
 #include "qapi/qmp/qerror.h"
+#include "hw/cpu/socket.h"
 
 #define MAX_VIRTIO_CONSOLES 1
 #define MAX_SCLP_CONSOLES 1
@@ -3014,6 +3015,7 @@ int main(int argc, char **argv, char **envp)
 FILE *vmstate_dump_file = NULL;
 Error *main_loop_err = NULL;
 Error *err = NULL;
+int sockets;
 
 qemu_init_cpu_loop();
 qemu_mutex_lock_iothread();
@@ -4154,6 +4156,17 @@ int main(int argc, char **argv, char **envp)
 }
 
 /*
+ * Create CPU socket objects which house CPU cores.
+ */
+sockets = DIV_ROUND_UP(max_cpus, smp_cores * smp_threads);
+for (i = 0; i < sockets; i++) {
+char id[32];
+
+snprintf(id, 32, "" TYPE_CPU_SOCKET "%d", i);
+object_add(TYPE_CPU_SOCKET, id, NULL, NULL, &error_abort);
+}
+
+/*
  * Get the default machine options from the machine if it is not already
  * specified either by the configuration file or by the command line.
  */
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 7/9] spapr: Convert boot CPUs into CPU core device initialization

[Bharata B Rao]

Initialize boot CPUs specified with -smp option as CPU core devices.

Signed-off-by: Bharata B Rao 
---
 hw/ppc/spapr.c | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index db441f2..9499871 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -63,7 +63,7 @@
 
 #include "hw/compat.h"
 #include "qemu-common.h"
-
+#include "hw/cpu/core.h"
 #include 
 
 /* SLOF memory layout:
@@ -1713,9 +1713,8 @@ static void ppc_spapr_init(MachineState *machine)
 const char *kernel_filename = machine->kernel_filename;
 const char *kernel_cmdline = machine->kernel_cmdline;
 const char *initrd_filename = machine->initrd_filename;
-PowerPCCPU *cpu;
 PCIHostState *phb;
-int i;
+int i, j;
 MemoryRegion *sysmem = get_system_memory();
 MemoryRegion *ram = g_new(MemoryRegion, 1);
 MemoryRegion *rma_region;
@@ -1727,6 +1726,7 @@ static void ppc_spapr_init(MachineState *machine)
 long load_limit, fw_size;
 bool kernel_le = false;
 char *filename;
+int sockets = DIV_ROUND_UP(smp_cpus, smp_cores * smp_threads);
 
 msi_supported = true;
 
@@ -1799,13 +1799,16 @@ static void ppc_spapr_init(MachineState *machine)
 }
 machine->cpu_type = TYPE_POWERPC_CPU;
 
-for (i = 0; i < smp_cpus; i++) {
-cpu = cpu_ppc_init(machine->cpu_model);
-if (cpu == NULL) {
-fprintf(stderr, "Unable to find PowerPC CPU definition\n");
-exit(1);
+for (i = 0; i < sockets; i++) {
+char sid[32];
+
+snprintf(sid, 32, "" TYPE_CPU_SOCKET "%d", i);
+for (j = 0; j < smp_cores; j++) {
+Object *core = object_new(TYPE_CPU_CORE);
+
+object_property_set_str(core, sid, "socket", &error_abort);
+object_property_set_bool(core, true, "realized", &error_abort);
 }
-spapr_cpu_init(spapr, cpu);
 }
 
 if (kvm_enabled()) {
@@ -2192,6 +2195,7 @@ static void spapr_machine_device_plug(HotplugHandler 
*hotplug_dev,
   DeviceState *dev, Error **errp)
 {
 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
+sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
 
 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 int node;
@@ -2228,6 +2232,11 @@ static void spapr_machine_device_plug(HotplugHandler 
*hotplug_dev,
 }
 
 spapr_memory_plug(hotplug_dev, dev, node, errp);
+} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
+CPUState *cs = CPU(dev);
+PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+spapr_cpu_init(ms, cpu);
 }
 }
 
@@ -2242,7 +2251,8 @@ static void spapr_machine_device_unplug(HotplugHandler 
*hotplug_dev,
 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
  DeviceState *dev)
 {
-if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
+if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
+object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 return HOTPLUG_HANDLER(machine);
 }
 return NULL;
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 3/9] cpu: Don't realize CPU from cpu_generic_init()

[Bharata B Rao]

Don't do CPU realization from cpu_generic_init(). With this
cpu_generic_init() can be used from instance_init to just create
CPU threads and they could be realized separately from realizefn call.

Convert the existing callers to do explicit realization.

Signed-off-by: Bharata B Rao 
---
 qom/cpu.c   |  6 --
 target-arm/helper.c | 16 +++-
 target-cris/cpu.c   | 16 +++-
 target-lm32/helper.c| 16 +++-
 target-moxie/cpu.c  | 16 +++-
 target-openrisc/cpu.c   | 16 +++-
 target-ppc/translate_init.c | 16 +++-
 target-sh4/cpu.c| 16 +++-
 target-tricore/helper.c | 16 +++-
 target-unicore32/helper.c   | 16 +++-
 10 files changed, 135 insertions(+), 15 deletions(-)

diff --git a/qom/cpu.c b/qom/cpu.c
index fb80d13..e7a17c1 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -63,13 +63,7 @@ CPUState *cpu_generic_init(const char *typename, const char 
*cpu_model)
 featurestr = strtok(NULL, ",");
 cc->parse_features(cpu, featurestr, &err);
 g_free(str);
-if (err != NULL) {
-goto out;
-}
-
-object_property_set_bool(OBJECT(cpu), true, "realized", &err);
 
-out:
 if (err != NULL) {
 error_report_err(err);
 object_unref(OBJECT(cpu));
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4ecae61..0d8c94e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4546,7 +4546,21 @@ void register_cp_regs_for_features(ARMCPU *cpu)
 
 ARMCPU *cpu_arm_init(const char *cpu_model)
 {
-return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
+CPUState *cpu = cpu_generic_init(TYPE_ARM_CPU, cpu_model);
+Error *err = NULL;
+
+if (!cpu) {
+return NULL;
+}
+
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err != NULL) {
+error_report_err(err);
+object_unref(OBJECT(cpu));
+return NULL;
+} else {
+return ARM_CPU(cpu);
+}
 }
 
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 8eaf5a5..d2c0822 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -89,7 +89,21 @@ static ObjectClass *cris_cpu_class_by_name(const char 
*cpu_model)
 
 CRISCPU *cpu_cris_init(const char *cpu_model)
 {
-return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
+CPUState *cpu = cpu_generic_init(TYPE_CRIS_CPU, cpu_model);
+Error *err = NULL;
+
+if (!cpu) {
+return NULL;
+}
+
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err != NULL) {
+error_report_err(err);
+object_unref(OBJECT(cpu));
+return NULL;
+} else {
+return CRIS_CPU(cpu);
+}
 }
 
 /* Sort alphabetically by VR. */
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index e26c133..49ac960 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -218,7 +218,21 @@ bool lm32_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
 
 LM32CPU *cpu_lm32_init(const char *cpu_model)
 {
-return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
+CPUState *cpu = cpu_generic_init(TYPE_LM32_CPU, cpu_model);
+Error *err = NULL;
+
+if (!cpu) {
+return NULL;
+}
+
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err != NULL) {
+error_report_err(err);
+object_unref(OBJECT(cpu));
+return NULL;
+} else {
+return LM32_CPU(cpu);
+}
 }
 
 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 0c60c65..5989fa6 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -152,7 +152,21 @@ static const MoxieCPUInfo moxie_cpus[] = {
 
 MoxieCPU *cpu_moxie_init(const char *cpu_model)
 {
-return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model));
+CPUState *cpu = cpu_generic_init(TYPE_MOXIE_CPU, cpu_model);
+Error *err = NULL;
+
+if (!cpu) {
+return NULL;
+}
+
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err != NULL) {
+error_report_err(err);
+object_unref(OBJECT(cpu));
+return NULL;
+} else {
+return MOXIE_CPU(cpu);
+}
 }
 
 static void cpu_register(const MoxieCPUInfo *info)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index cc5e2d1..873eafb 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -222,7 +222,21 @@ static void openrisc_cpu_register_types(void)
 
 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 {
-return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
+CPUState *cpu = cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model);
+Error *err = NULL;
+
+if (!cpu) {
+return NULL;
+}
+
+object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+if (err != NULL) {
+ 

[Qemu-devel] [RFC PATCH v0 8/9] target-i386: Set apic_id during CPU initfn

[Bharata B Rao]

Move back the setting of apic_id to instance_init routine (x86_cpu_initfn)
This is needed to initialize X86 CPUs using generic cpu-package device.

TODO: I am not fully aware of the general direction in which apic_id
changes in X86 have evolved and hence not sure if this is indeed aligned with
the X86 way of doing things. This is just to help the PoC implementation
that I have in this patchset to convert PC CPUs initialization into
cpu-package device based initialization.

Signed-off-by: Bharata B Rao 
---
 hw/i386/pc.c  | 33 -
 target-i386/cpu.c | 37 +++--
 target-i386/cpu.h |  1 +
 3 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ffcd645..80a4d98 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -670,39 +670,6 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t 
*address, uint64_t *length)
 return false;
 }
 
-/* Enables contiguous-apic-ID mode, for compatibility */
-static bool compat_apic_id_mode;
-
-void enable_compat_apic_id_mode(void)
-{
-compat_apic_id_mode = true;
-}
-
-/* Calculates initial APIC ID for a specific CPU index
- *
- * Currently we need to be able to calculate the APIC ID from the CPU index
- * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces 
have
- * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
- * all CPUs up to max_cpus.
- */
-static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
-{
-uint32_t correct_id;
-static bool warned;
-
-correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
-if (compat_apic_id_mode) {
-if (cpu_index != correct_id && !warned && !qtest_enabled()) {
-error_report("APIC IDs set in compatibility mode, "
- "CPU topology won't match the configuration");
-warned = true;
-}
-return cpu_index;
-} else {
-return correct_id;
-}
-}
-
 /* Calculates the limit to CPU APIC ID values
  *
  * This function returns the limit for the APIC ID value, so that all
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 11e5e39..c97a646 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -25,6 +25,7 @@
 #include "sysemu/kvm.h"
 #include "sysemu/cpus.h"
 #include "kvm_i386.h"
+#include "hw/i386/topology.h"
 
 #include "qemu/error-report.h"
 #include "qemu/option.h"
@@ -3028,6 +3029,39 @@ static void x86_cpu_register_feature_bit_props(X86CPU 
*cpu,
 g_strfreev(names);
 }
 
+/* Enables contiguous-apic-ID mode, for compatibility */
+static bool compat_apic_id_mode;
+
+void enable_compat_apic_id_mode(void)
+{
+compat_apic_id_mode = true;
+}
+
+/* Calculates initial APIC ID for a specific CPU index
+ *
+ * Currently we need to be able to calculate the APIC ID from the CPU index
+ * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces 
have
+ * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
+ * all CPUs up to max_cpus.
+ */
+uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
+{
+uint32_t correct_id;
+static bool warned;
+
+correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
+if (compat_apic_id_mode) {
+if (cpu_index != correct_id && !warned) {
+error_report("APIC IDs set in compatibility mode, "
+ "CPU topology won't match the configuration");
+warned = true;
+}
+return cpu_index;
+} else {
+return correct_id;
+}
+}
+
 static void x86_cpu_initfn(Object *obj)
 {
 CPUState *cs = CPU(obj);
@@ -3071,8 +3105,7 @@ static void x86_cpu_initfn(Object *obj)
 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
 
 #ifndef CONFIG_USER_ONLY
-/* Any code creating new X86CPU objects have to set apic-id explicitly */
-cpu->apic_id = -1;
+cpu->apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
 #endif
 
 for (w = 0; w < FEATURE_WORDS; w++) {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index fc4a605..a5368cf 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1333,6 +1333,7 @@ void x86_cpu_change_kvm_default(const char *prop, const 
char *value);
 /* Return name of 32-bit register, from a R_* constant */
 const char *get_register_name_32(unsigned int reg);
 
+uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
 void enable_compat_apic_id_mode(void);
 
 #define APIC_DEFAULT_ADDRESS 0xfee0
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 4/9] cpu: CPU socket backend

[Bharata B Rao]

Backend object for CPU socket.

TODO: Prevent creation of socket objects beyond what is needed by
max_cpus so that all the required socket objects are pre-created
and user can't ever add a socket slot.

Signed-off-by: Bharata B Rao 
---
 hw/cpu/Makefile.objs|  1 +
 hw/cpu/socket.c | 48 
 include/hw/cpu/socket.h | 26 ++
 3 files changed, 75 insertions(+)
 create mode 100644 hw/cpu/socket.c
 create mode 100644 include/hw/cpu/socket.h

diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs
index 0954a18..93d1226 100644
--- a/hw/cpu/Makefile.objs
+++ b/hw/cpu/Makefile.objs
@@ -2,4 +2,5 @@ obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o
 obj-$(CONFIG_REALVIEW) += realview_mpcore.o
 obj-$(CONFIG_A9MPCORE) += a9mpcore.o
 obj-$(CONFIG_A15MPCORE) += a15mpcore.o
+obj-y += socket.o
 
diff --git a/hw/cpu/socket.c b/hw/cpu/socket.c
new file mode 100644
index 000..e0a2af9
--- /dev/null
+++ b/hw/cpu/socket.c
@@ -0,0 +1,48 @@
+/*
+ * CPU socket backend
+ *
+ * Copyright (C) 2015 Bharata B Rao 
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw/cpu/socket.h"
+#include "qom/object_interfaces.h"
+
+static bool cpu_socket_can_be_deleted(UserCreatable *uc, Error **errp)
+{
+return false;
+}
+
+static void cpu_socket_class_init(ObjectClass *oc, void *data)
+{
+UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
+
+ucc->can_be_deleted = cpu_socket_can_be_deleted;
+}
+
+static void cpu_socket_instance_init(Object *obj)
+{
+CPUSocket *socket = CPU_SOCKET(obj);
+
+socket->nr_cores = 0;
+}
+
+static const TypeInfo cpu_socket_info = {
+.name = TYPE_CPU_SOCKET,
+.parent = TYPE_OBJECT,
+.instance_init = cpu_socket_instance_init,
+.instance_size = sizeof(CPUSocket),
+.class_init = cpu_socket_class_init,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_USER_CREATABLE },
+{ }
+}
+};
+
+static void cpu_socket_register_types(void)
+{
+type_register_static(&cpu_socket_info);
+}
+
+type_init(cpu_socket_register_types)
diff --git a/include/hw/cpu/socket.h b/include/hw/cpu/socket.h
new file mode 100644
index 000..ff29367
--- /dev/null
+++ b/include/hw/cpu/socket.h
@@ -0,0 +1,26 @@
+/*
+ * CPU socket backend
+ *
+ * Copyright (C) 2015 Bharata B Rao 
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef HW_CPU_SOCKET_H
+#define HW_CPU_SOCKET_H
+
+#include "hw/qdev.h"
+
+#define TYPE_CPU_SOCKET "cpu-socket"
+#define CPU_SOCKET(obj) \
+OBJECT_CHECK(CPUSocket, (obj), TYPE_CPU_SOCKET)
+
+typedef struct CPUSocket {
+/* private */
+Object parent;
+
+/* public */
+int nr_cores;
+} CPUSocket;
+
+#endif
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 0/9] Generic cpu-core device

[Bharata B Rao]

Hi,

This is an attempt to define a generic CPU device that serves as a
containing device to underlying arch-specific CPU devices. The motivation
for this is to have an arch-neutral way to specify CPUs mainly during
hotplug.

Instead of individual archs having their own semantics to specify the
CPU like

-device POWER8-powerpc64-cpu (pseries)
-device qemu64-x86_64-cpu (pc)
-device s390-cpu (s390)

this patch introduces a new device named cpu-core that could be
used for all target archs as

-device cpu-core,socket="sid"

This adds a CPU core with all its associated threads into the specified
socket with id "sid". The number of target architecture specific CPU threads
that get created during this operation is based on the CPU topology specified
using -smp sockets=S,cores=C,threads=T option. Also the number of cores that
can be accommodated in the same socket is dictated by the cores= parameter
in the same -smp option.

CPU sockets are represented by QOM objects and the number of sockets required
to fit in max_cpus are created at boottime. As cpu-core devices are
created, they are linked to socket object specified by socket="sid" device
property.

Thus the model consists of backend socket objects which can be considered
as container of one or more cpu-core devices. Each cpu-core object is
linked to the appropriate backend socket object. Each CPU thread device
appears as child object of cpu-core device.

All the required socket objects are created upfront and they can't be deleted.
Though currently socket objects can be created using object_add monitor
command, I am planning to prevent that so that a guest boots with the
required number of sockets and only CPU cores can be hotplugged into
them.

CPU hotplug granularity
---
CPU hotplug will now be done in cpu-core device granularity.

This patchset includes a patch to prevent topologies that result in
partially filled cores. Hence with this patchset, we will always
have fully filled cpu-core devices both for boot time and during hotplug.

For archs like PowerPC, where there is no requirement to be fully
similar to the physical system, hotplugging CPU at core granularity
is common. While core level hotplug will fit in naturally for such
archs, for others which want socket level hotplug, could higher level
tools like libvirt perform multiple core hotplugs in response to one
socket hotplug request ?

Are there archs that would need thread level CPU addition ?

Boot time CPUs as cpu-core devices
--
In this patchset, I am coverting the boot time CPU initialization
(from -smp option) to initialize the required number of cpu-core
devices and linking them with the appropriate socket objects.

Initially I thought we should be able to completely replace -smp with
-device cpu-core, but then I realized that at least both x86 and pseries
guests' machine init code has dependencies on first CPU being available
for the machine init code to work correctly.

Currently I have converted boot CPUs to cpu-core devices only PowerPC sPAPR
and i386 PC targets. I am not really sure about the i386 changes and the
intention in this iteration was to check if it is indeed possible to
fit i386 into cpu-core model. Having said that I am able to boot an x86
guest with this patchset.

NUMA

TODO: In this patchset, I haven't explicitly done anything for NUMA yet.
I am thinking if we could add node=N option to cpu-core device.
That could specify the NUMA node to which the CPU core belongs to.

-device cpu-core,socket="sid",node=N

QOM composition tree
-
QOM composition tree for x86 where I don't have CPU hotplug enabled, but
just initializing boot CPUs as cpu-core devices appears like this:

-smp 4,sockets=4,cores=2,threads=2,maxcpus=16

/machine (pc-i440fx-2.5-machine)
  /unattached (container)
/device[0] (cpu-core)
  /thread[0] (qemu64-x86_64-cpu)
  /thread[1] (qemu64-x86_64-cpu)
/device[4] (cpu-core)
  /thread[0] (qemu64-x86_64-cpu)
  /thread[1] (qemu64-x86_64-cpu)

For PowerPC where I have CPU hotplug enabled:

-smp 4,sockets=4,cores=2,threads=2,maxcpus=16 -device 
cpu-core,socket=cpu-socket1,id=core3

/machine (pseries-2.5-machine)
  /unattached (container)
/device[1] (cpu-core)
  /thread[0] (host-powerpc64-cpu)
  /thread[1] (host-powerpc64-cpu)
/device[2] (cpu-core)
  /thread[0] (host-powerpc64-cpu)
  /thread[1] (host-powerpc64-cpu)
  /peripheral (container)
/core3 (cpu-core)
  /thread[0] (host-powerpc64-cpu)
  /thread[1] (host-powerpc64-cpu)

As can be seen, the boot CPU and hotplugged CPU come under separate
parents. Guess I should work towards getting both boot time and hotplugged
CPUs under same parent ?

Socket ID generation
-
In the current approach the socket ID generation is implicit somewhat.
All the sockets objects are created with pre-fixed format for ids like
cpu-socket0, cpu-socket1 etc. And machine init code of each arch is

[Qemu-devel] [RFC PATCH v0 2/9] cpu: Store CPU typename in MachineState

[Bharata B Rao]

Storing CPU typename in MachineState lets us to create CPU threads
for all architectures in uniform manner from arch-neutral code.

TODO: Touching only i386 and spapr targets for now

Signed-off-by: Bharata B Rao 
---
 hw/i386/pc.c| 1 +
 hw/ppc/spapr.c  | 2 ++
 include/hw/boards.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5e20e07..ffcd645 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1133,6 +1133,7 @@ void pc_cpus_init(PCMachineState *pcms)
 machine->cpu_model = "qemu32";
 #endif
 }
+machine->cpu_type = TYPE_X86_CPU;
 
 apic_id_limit = pc_apic_id_limit(max_cpus);
 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 030ee35..db441f2 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1797,6 +1797,8 @@ static void ppc_spapr_init(MachineState *machine)
 if (machine->cpu_model == NULL) {
 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
 }
+machine->cpu_type = TYPE_POWERPC_CPU;
+
 for (i = 0; i < smp_cpus; i++) {
 cpu = cpu_ppc_init(machine->cpu_model);
 if (cpu == NULL) {
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 24eb6f0..a1f9512 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -128,6 +128,7 @@ struct MachineState {
 char *kernel_cmdline;
 char *initrd_filename;
 const char *cpu_model;
+const char *cpu_type;
 AccelState *accelerator;
 };
 
-- 
2.1.0

[Qemu-devel] [RFC PATCH v0 1/9] vl: Don't allow CPU toplogies with partially filled cores

[Bharata B Rao]

Prevent guests from booting with CPU topologies that have partially
filled CPU cores or can result in partially filled CPU cores after CPU
hotplug like

-smp 15,sockets=1,cores=4,threads=4,maxcpus=16 or
-smp 15,sockets=1,cores=4,threads=4,maxcpus=17 or

Signed-off-by: Bharata B Rao 
---
 vl.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/vl.c b/vl.c
index 525929b..e656f53 100644
--- a/vl.c
+++ b/vl.c
@@ -1252,6 +1252,19 @@ static void smp_parse(QemuOpts *opts)
 smp_cores = cores > 0 ? cores : 1;
 smp_threads = threads > 0 ? threads : 1;
 
+if (smp_cpus % smp_threads) {
+error_report("cpu topology: "
+ "smp_cpus (%u) should be multiple of threads (%u)",
+ smp_cpus, smp_threads);
+exit(1);
+}
+
+if (max_cpus % smp_threads) {
+error_report("cpu topology: "
+ "maxcpus (%u) should be multiple of threads (%u)",
+ max_cpus, smp_threads);
+exit(1);
+}
 }
 
 if (max_cpus == 0) {
-- 
2.1.0

Re: [Qemu-devel] [Patch v8 0/3] qapi: child add/delete support

[Wen Congyang]

Kevin: ping

On 11/27/2015 02:06 PM, Wen Congyang wrote:
> If quorum's child is broken, we can use mirror job to replace it.
> But sometimes, the user only need to remove the broken child, and
> add it later when the problem is fixed.
> 
> It is based on the Kevin's child name related patch:
> http://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg04949.html
> 
> ChangLog:
> v8:
> 1. Rebase to the newest codes
> 2. Address the comments from Eric Blake
> v7:
> 1. Remove the qmp command x-blockdev-change's parameter operation according
>to Kevin's comments.
> 2. Remove the hmp command.
> v6:
> 1. Use a single qmp command x-blockdev-change to replace x-blockdev-child-add
>and x-blockdev-child-delete
> v5:
> 1. Address Eric Blake's comments
> v4:
> 1. drop nbd driver's implementation. We can use human-monitor-command
>to do it.
> 2. Rename the command name.
> v3:
> 1. Don't open BDS in bdrv_add_child(). Use the existing BDS which is
>created by the QMP command blockdev-add.
> 2. The driver NBD can support filename, path, host:port now.
> v2:
> 1. Use bdrv_get_device_or_node_name() instead of new function
>bdrv_get_id_or_node_name()
> 2. Update the error message
> 3. Update the documents in block-core.json
> 
> Wen Congyang (3):
>   Add new block driver interface to add/delete a BDS's child
>   quorum: implement bdrv_add_child() and bdrv_del_child()
>   qmp: add monitor command to add/remove a child
> 
>  block.c   |  58 --
>  block/quorum.c| 124 
> +-
>  blockdev.c|  54 
>  include/block/block.h |   9 
>  include/block/block_int.h |   5 ++
>  qapi/block-core.json  |  23 +
>  qmp-commands.hx   |  47 ++
>  7 files changed, 314 insertions(+), 6 deletions(-)
> 

[Qemu-devel] what is the plan for seabios merged into qemu?

[Han, Huaitong]

Hi, Gerd

I find pc-bios/bios-256k.bin has not been updated for a long time, even
seabios is released a new version, what is the plan for seabios merged
into qemu?

Thanks
Huaitong.

Re: [Qemu-devel] HTTP access to QEMU Git repositories

[Anthony Liguori]

On Dec 9, 2015 6:14 PM, "Stefan Hajnoczi"  wrote:
>
> On Wed, Dec 09, 2015 at 06:07:07PM +0100, Paolo Bonzini wrote:
> > On 09/12/2015 17:37, Kai Noda wrote:
> > > Those auxiliary repositories referenced by git-submodule, such as
> > > dtc.git in my last email, are only available on git.qemu.org
> > > .
> >
> > Hmm, that should be fixed but I don't know who manages github.com/qemu.
> >  Is it still Anthony?
>
> ENOCONTEXT.  Where are you getting HTTP from?
>
> https://github.com/qemu/qemu/blob/master/.gitmodules has
> git://git.qemu-project.org/ URLs.
>
> I have push access to github.com/qemu/qemu.git but Anthony has the
> GitHub username/password needed to make account changes, new repos, etc.

qemu is an organization, not an account.  At least Paolo and Andreas are
owners of the org and can add more people.

Let me know if this I am missing anything here.  It's been a while and I
only half remember setting this up.

> Stefan

Re: [Qemu-devel] [PATCH v2 1/1] target-ppc: Implement rtas_get_sysparm(PROCESSOR_MODULE_INFO)

[David Gibson]

On Fri, Dec 04, 2015 at 05:04:16PM -0800, Nishanth Aravamudan wrote:
> On 01.12.2015 [14:41:25 +1100], David Gibson wrote:
> > On Thu, Nov 12, 2015 at 08:46:27AM -0800, Nishanth Aravamudan wrote:
> > > On 12.11.2015 [15:47:15 +1100], David Gibson wrote:
> > > > On Wed, Nov 11, 2015 at 02:10:48PM -0800, Nishanth Aravamudan wrote:
> > > > > On 11.11.2015 [12:41:26 +1100], David Gibson wrote:
> > > > > > On Tue, Nov 10, 2015 at 04:56:38PM -0800, Nishanth Aravamudan wrote:
> > > > > > > On 11.11.2015 [11:17:58 +1100], David Gibson wrote:
> > > > > > > > On Mon, Nov 09, 2015 at 08:22:32PM -0800, Sukadev Bhattiprolu 
> > > > > > > > wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > > > > The trouble with xscom is that it's extremely specific to the 
> > > > > > > > way the
> > > > > > > > current IBM servers present things.  It won't work on other 
> > > > > > > > types of
> > > > > > > > host machine (which could happen with PR KVM), and could even 
> > > > > > > > break if
> > > > > > > > IBM changes the way it organizes the SCOMs in a future machine.
> > > > > > > > 
> > > > > > > > Working from the nodes in /cpus still has some dependencies on 
> > > > > > > > IBM
> > > > > > > > specific properties, but it's at least partially based on OF
> > > > > > > > standards.
> > > > > > > > 
> > > > > > > > There's also another possible approach here, though I don't 
> > > > > > > > know if it
> > > > > > > > will work.  Instead of looking directly in the device tree, try 
> > > > > > > > to get
> > > > > > > > the information from lscpu, or libosinfo.  That would at least 
> > > > > > > > give
> > > > > > > > you some hope of providing meaningful information on other host 
> > > > > > > > types.
> > > > > > > 
> > > > > > > Heh, the issue that is underlying all of this, is that `lscpu` 
> > > > > > > itself is
> > > > > > > quite wrong.
> > > > > > > 
> > > > > > > On PAPR-compliant hypervisors (well, PowerVM, at least), the only
> > > > > > > supported means of determining the underlying hardware CPU 
> > > > > > > information
> > > > > > > (which is what licensing models want in the end), is to use this 
> > > > > > > RTAS
> > > > > > > call in an LPAR. `lscpu` is explicitly incorrect in these 
> > > > > > > environments
> > > > > > > (it's values are "derived" from sysfs and some are adjusted to 
> > > > > > > ensure
> > > > > > > the division of values works out).
> > > > > > 
> > > > > > So.. I'm not sure if you're just saying that lscpu is wrong because 
> > > > > > it
> > > > > > gives the guest information, or because of other problems.
> > > > > 
> > > > > `lscpu`'s man-page specifically says that on virtualized platforms, 
> > > > > the
> > > > > output may be inaccurate. And, in fact, on Power, in a KVM guest (and
> > > > > in a LPAR), `lscpu` is outputting the guest CPU information, which is
> > > > > completely fake. This is true on x86 KVM guests too, afaict.
> > > > 
> > > > Um.. yes, I was assuming lscpu reporting information about virtual
> > > > cpus and sockets was intended and correct behaviour.
> > > 
> > > "lscpu - display information about the CPU architecture"
> > 
> > Right, without qualification I'd take that as virtual architecture.
> 
> Ok, I did not. I suppose the manpage could be reviewed and/or updated.
> 
> Regardless, Suka has gotten a patch merged which at least for power, can
> display the physical information via `lscpu`, when the RTAS call is
> available.

Ok.

> > > but at the same time "lscpu   gathers   CPU   architecture   information
> > > from   sysfs   and /proc/cpuinfo" which is explicitly logical (or
> > > virtual).
> > > 
> > > but at the same time "There is also information about the CPU caches and
> > > cache sharing, family, model, bogoMIPS, byte order, and stepping." which
> > > seems rather physical to me.
> > 
> > bogomips and byte order are absolutely properties of a virtual cpu.
> 
> I think the distinction to be made is they are *also* properties of a
> virtual CPU. That is, they are properties of both,and where they vary,
> it might be relevant to know both cases.

No, they're really not.

Byte order isn't even really a property of the cpu at all, but of a
particularly piece of software running on it.  Bogomips is an internal
parameter of the Linux kernel which depends (somewhat) on the CPU.  To
the guest kernel, the host bogomips is absolutely irrelevant.

> > As are family and model, really, since they're generally at least
> > partially visible to a guest, and there may be some capacity for
> > faking them (x86 is more flexible in this regard than Power).
> > Stepping might be depending on exactly what level the system is
> > virtualized at (it's not for the case of PAPR).
> > 
> > Cache info is probably purely physical but amongst everything else
> > that's a property of the virtual cpu, I don't think that's an argument
> > that lscpu should return host cpu information in general.
> > 
> > 
> > > So perhaps, as I kind of stumbled upon myself in my last rep

Re: [Qemu-devel] [PATCH v9 0/5] implement vNVDIMM

[Xiao Guangrong]

New version, new week, and unfortunate new ping... :(


On 12/02/2015 03:20 PM, Xiao Guangrong wrote:

This patchset can be found at:
   https://github.com/xiaogr/qemu.git nvdimm-v9

It is based on pci branch on Michael's tree and the top commit is:
commit 0c73277af7 (vhost-user-test: fix crash with glib < 2.36).

Changelog in v9:
- the changes address Michael's comments:
   1) move the control parameter to -machine and it is off on default, then
  it can be enabled by, for example, -machine pc,nvdimm
   2) introduce a macro to define "NCAL"
   3) abstract the function, nvdimm_build_device_dsm(), to clean up the
  code
   4) adjust the code style of dsm method
   5) add spec reference in the code comment

other:
   pick up Stefan's Reviewed-by

Changelog in v8:
We split the long patch series into the small parts, as you see now, this
is the first part which enables NVDIMM without label data support.

The command line has been changed because some patches simplifying the
things have not been included into this series, you should specify the
file size exactly using the parameters as follows:
memory-backend-file,id=mem1,share,mem-path=/tmp/nvdimm1,size=10G \
-device nvdimm,memdev=mem1,id=nv1

Changelog in v7:
- changes from Vladimir Sementsov-Ogievskiy's comments:
   1) let gethugepagesize() realize if fstat is failed instead of get
  normal page size
   2) rename  open_file_path to open_ram_file_path
   3) better log the error message by using error_setg_errno
   4) update commit in the commit log to explain hugepage detection on
  Windows

- changes from Eduardo Habkost's comments:
   1) use 'Error**' to collect error message for qemu_file_get_page_size()
   2) move gethugepagesize() replacement to the same patch to make it
  better for review
   3) introduce qemu_get_file_size to unity the code with raw_getlength()

- changes from Stefan's comments:
   1) check the memory region is large enough to contain DSM output
  buffer

- changes from Eric Blake's comments:
   1) update the shell command in the commit log to generate the patch
  which drops 'pc-dimm' prefix

- others:
   pick up Reviewed-by from Stefan, Vladimir Sementsov-Ogievskiy, and
   Eric Blake.

Changelog in v6:
- changes from Stefan's comments:
   1) fix code style of struct naming by CamelCase way
   2) fix offset + length overflow when read/write label data
   3) compile hw/acpi/nvdimm.c for per target so that TARGET_PAGE_SIZE can
  be used to replace getpagesize()

Changelog in v5:
- changes from Michael's comments:
   1) prefix nvdimm_ to everything in NVDIMM source files
   2) make parsing _DSM Arg3 more clear
   3) comment style fix
   5) drop single used definition
   6) fix dirty dsm buffer lost due to memory write happened on host
   7) check dsm buffer if it is big enough to contain input data
   8) use build_append_int_noprefix to store single value to GArray

- changes from Michael's and Igor's comments:
   1) introduce 'nvdimm-support' parameter to control nvdimm
  enablement and it is disabled for 2.4 and its earlier versions
  to make live migration compatible
   2) only reserve 1 RAM page and 4 bytes IO Port for NVDIMM ACPI
  virtualization

- changes from Stefan's comments:
   1) do endian adjustment for the buffer length

- changes from Bharata B Rao's comments:
   1) fix compile on ppc

- others:
   1) the buffer length is directly got from IO read rather than got
  from dsm memory
   2) fix dirty label data lost due to memory write happened on host

Changelog in v4:
- changes from Michael's comments:
   1) show the message, "Memory is not allocated from HugeTlbfs", if file
  based memory is not allocated from hugetlbfs.
   2) introduce function, acpi_get_nvdimm_state(), to get NVDIMMState
  from Machine.
   3) statically define UUID and make its operation more clear
   4) use GArray to build device structures to avoid potential buffer
  overflow
   4) improve comments in the code
   5) improve code style

- changes from Igor's comments:
   1) add NVDIMM ACPI spec document
   2) use serialized method to avoid Mutex
   3) move NVDIMM ACPI's code to hw/acpi/nvdimm.c
   4) introduce a common ASL method used by _DSM for all devices to reduce
  ACPI size
   5) handle UUID in ACPI AML code. BTW, i'd keep handling revision in QEMU
  it's better to upgrade QEMU to support Rev2 in the future

- changes from Stefan's comments:
   1) copy input data from DSM memory to local buffer to avoid potential
  issues as DSM memory is visible to guest. Output data is handled
  in a similar way

- changes from Dan's comments:
   1) drop static namespace as Linux has already supported label-less
  nvdimm devices

- changes from Vladimir's comments:
   1) print better message, "failed to get file size for %s, can't create
  backend on it", if any file operation filed to obtain file size

- others:
   create a git repo on github.com for better review/t

Re: [Qemu-devel] live migration vs device assignment (motivation)

[Lan, Tianyu]

On 12/10/2015 1:14 AM, Alexander Duyck wrote:

On Wed, Dec 9, 2015 at 8:26 AM, Lan, Tianyu  wrote:


For other kind of devices, it's hard to work.
We are also adding migration support for QAT(QuickAssist Technology) device.

QAT device user case introduction.
Server, networking, big data, and storage applications use QuickAssist
Technology to offload servers from handling compute-intensive operations,
such as:
1) Symmetric cryptography functions including cipher operations and
authentication operations
2) Public key functions including RSA, Diffie-Hellman, and elliptic curve
cryptography
3) Compression and decompression functions including DEFLATE and LZS

PCI hotplug will not work for such devices during migration and these
operations will fail when unplug device.


I assume the problem is that with a PCI hotplug event you are losing
the state information for the device, do I have that right?

Looking over the QAT drivers it doesn't seem like any of them support
the suspend/resume PM calls.  I would imagine it makes it difficult
for a system with a QAT card in it to be able to drop the system to a
low power state.  You might want to try enabling suspend/resume
support for the devices on bare metal before you attempt to take on
migration as it would provide you with a good testing framework to see
what needs to be saved/restored within the device and in what order
before you attempt to do the same while migrating from one system to
another.


Sure. The suspend/resume job is under way.
Actually, we have enabled QAT work for migration internally. Doing more 
test and fixing bugs.




- Alex

Re: [Qemu-devel] live migration vs device assignment (motivation)

[Lan, Tianyu]

On 12/10/2015 4:07 AM, Michael S. Tsirkin wrote:

On Thu, Dec 10, 2015 at 12:26:25AM +0800, Lan, Tianyu wrote:

On 12/8/2015 12:50 AM, Michael S. Tsirkin wrote:

I thought about what this is doing at the high level, and I do have some
value in what you are trying to do, but I also think we need to clarify
the motivation a bit more.  What you are saying is not really what the
patches are doing.

And with that clearer understanding of the motivation in mind (assuming
it actually captures a real need), I would also like to suggest some
changes.


Motivation:
Most current solutions for migration with passthough device are based on
the PCI hotplug but it has side affect and can't work for all device.

For NIC device:
PCI hotplug solution can work around Network device migration
via switching VF and PF.


This is just more confusion. hotplug is just a way to add and remove
devices. switching VF and PF is up to guest and hypervisor.


This is a combination. Because it's not able to migrate device state in
the current world during migration(What we are doing), Exist solutions
of migrating VM with passthough NIC relies on the PCI hotplug. Unplug VF
before starting migration and then switch network from VF NIC to PV NIC
in order to maintain the network connection. Plug VF again after
migration and then switch from PV back to VF. Bond driver provides a way 
to switch between PV and VF NIC automatically with save IP and MAC and 
so bond driver is more preferred.





But switching network interface will introduce service down time.

I tested the service down time via putting VF and PV interface
into a bonded interface and ping the bonded interface during plug
and unplug VF.
1) About 100ms when add VF
2) About 30ms when del VF


OK and what's the source of the downtime?
I'm guessing that's just arp being repopulated.  So simply save and
re-populate it.

There would be a much cleaner solution.

Or maybe there's a timer there that just delays hotplug
for no reason. Fix it, everyone will benefit.


It also requires guest to do switch configuration.


That's just wrong. if you want a switch, you need to
configure a switch.


I meant the config of switching operation between PV and VF.




These are hard to
manage and deploy from our customers.


So kernel want to remain flexible, and the stack is
configurable. Downside: customers need to deploy userspace
to configure it. Your solution: a hard-coded configuration
within kernel and hypervisor.  Sorry, this makes no sense.
If kernel is easier for you to deploy than userspace,
you need to rethink your deployment strategy.


This is one factor.




To maintain PV performance during
migration, host side also needs to assign a VF to PV device. This
affects scalability.


No idea what this means.


These factors block SRIOV NIC passthough usage in the cloud service and
OPNFV which require network high performance and stability a lot.


Everyone needs performance and scalability.



For other kind of devices, it's hard to work.
We are also adding migration support for QAT(QuickAssist Technology) device.

QAT device user case introduction.
Server, networking, big data, and storage applications use QuickAssist
Technology to offload servers from handling compute-intensive operations,
such as:
1) Symmetric cryptography functions including cipher operations and
authentication operations
2) Public key functions including RSA, Diffie-Hellman, and elliptic curve
cryptography
3) Compression and decompression functions including DEFLATE and LZS

PCI hotplug will not work for such devices during migration and these
operations will fail when unplug device.

So we are trying implementing a new solution which really migrates
device state to target machine and won't affect user during migration
with low service down time.


Let's assume for the sake of the argument that there's a lot going on
and removing the device is just too slow (though you should figure out
what's going on before giving up and just building something new from
scratch).


No, we can find a PV NIC as backup for VF NIC during migration but it 
doesn't work for other kinds of device since there is no backup for 
them. E,G When migration happens during users compresses files via QAT, 
it's impossible to remove QAT at that point. If do that, the compress 
operation will fail and affect user experience.




I still don't think you should be migrating state.  That's just too
fragile, and it also means you depend on driver to be nice and shut down
device on source, so you can not migrate at will.  Instead, reset device
on destination and re-initialize it.



Yes, saving and restoring device state relies on the driver and so we 
reworks driver and make it more friend to migration.

Re: [Qemu-devel] [PATCH 2/2] configure: fix trace backend check

[Eric Blake]

On 12/09/2015 05:47 PM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau 
> 
> Found thanks to shellcheck!
> 
> Signed-off-by: Marc-André Lureau 
> ---
>  configure | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Eric Blake 

> 
> diff --git a/configure b/configure
> index 6a971a2..ba57b3f 100755
> --- a/configure
> +++ b/configure
> @@ -4816,7 +4816,7 @@ echo "libcap-ng support $cap_ng"
>  echo "vhost-net support $vhost_net"
>  echo "vhost-scsi support $vhost_scsi"
>  echo "Trace backends$trace_backends"
> -if test "$trace_backend" = "simple"; then
> +if have_backend "simple"; then
>  echo "Trace output file $trace_file-"
>  fi
>  if test "$spice" = "yes"; then
> 

-- 
Eric Blake   eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org



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Re: [Qemu-devel] [PATCH 1/2] configure: remove unused or undefined variables

[Eric Blake]

On 12/09/2015 05:47 PM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau 
> 
> Found thanks to shellcheck!

When sending two or more patches in a series, it's best to also include
a 0/2 cover letter.  It doesn't matter how trivial the patches are;
series are handled better by the tooling when they have a cover.

> 
> Signed-off-by: Marc-André Lureau 
> ---
>  configure | 6 --
>  1 file changed, 6 deletions(-)
> 

Reviewed-by: Eric Blake 

-- 
Eric Blake   eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org



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Re: [Qemu-devel] [PATCH] configure: remove bashism (since 2010)

[Eric Blake]

On 12/09/2015 05:57 PM, Marc-André Lureau wrote:
> Hi
> 
> On Thu, Dec 10, 2015 at 1:53 AM,   wrote:
>> From: Marc-André Lureau 
>>
>> "type" is not POSIX shell, but a bashism. (found thanks to shellcheck)
>>
> 
> A subsidiary question is whether qemu really care about using POSIX
> shell, or we can just depend on bashism. That would help with
> simplifying some Makefile lines too.

Debian uses dash, not bash, as /bin/sh.  As both 'configure' and
'Makefile' depend on '/bin/sh', then yes, we care about POSIX compliance.

Only in scripts that explicitly require /bin/bash, such as much of the
scripts under tests/, can we get away with bashisms.

-- 
Eric Blake   eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org



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Re: [Qemu-devel] [PATCH] configure: remove bashism (since 2010)

[Eric Blake]

On 12/09/2015 05:53 PM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau 
> 
> "type" is not POSIX shell, but a bashism. (found thanks to shellcheck)

NACK.  'type' is POSIX, and shellcheck is buggy.

http://pubs.opengroup.org/onlinepubs/9699919799/utilities/type.html

> 
> Signed-off-by: Marc-André Lureau 
> ---
>  configure | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/configure b/configure
> index ba57b3f..90eff82 100755
> --- a/configure
> +++ b/configure
> @@ -158,7 +158,7 @@ symlink() {
>  # check whether a command is available to this shell (may be either an
>  # executable or a builtin)
>  has() {
> -type "$1" >/dev/null 2>&1
> +which "$1" >/dev/null 2>&1

Conversely, 'which' is _not_ POSIX, and therefore less portable than 'type'.

-- 
Eric Blake   eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org



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Re: [Qemu-devel] HTTP access to QEMU Git repositories

[Stefan Hajnoczi]

On Wed, Dec 09, 2015 at 06:07:07PM +0100, Paolo Bonzini wrote:
> On 09/12/2015 17:37, Kai Noda wrote:
> > Those auxiliary repositories referenced by git-submodule, such as
> > dtc.git in my last email, are only available on git.qemu.org
> > .
> 
> Hmm, that should be fixed but I don't know who manages github.com/qemu.
>  Is it still Anthony?

ENOCONTEXT.  Where are you getting HTTP from?

https://github.com/qemu/qemu/blob/master/.gitmodules has
git://git.qemu-project.org/ URLs.

I have push access to github.com/qemu/qemu.git but Anthony has the
GitHub username/password needed to make account changes, new repos, etc.

Stefan


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Re: [Qemu-devel] [PATCH 23/74] acpi: extend aml_and() to accept target argument

[Shannon Zhao]

On 2015/12/10 7:41, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov 
> ---
>  hw/acpi/aml-build.c | 4 ++--
>  hw/arm/virt-acpi-build.c| 2 +-
>  hw/i386/acpi-build.c| 8 +---
>  include/hw/acpi/aml-build.h | 2 +-
>  4 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 4f62512..2ca9207 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -499,9 +499,9 @@ build_opcode_2arg_dst(uint8_t op, Aml *arg1, Aml *arg2, 
> Aml *dst)
>  }
>  
>  /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
> -Aml *aml_and(Aml *arg1, Aml *arg2)
> +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *dst)
>  {
> -return build_opcode_2arg_dst(0x7B /* AndOp */, arg1, arg2, NULL);
> +return build_opcode_2arg_dst(0x7B /* AndOp */, arg1, arg2, dst);
>  }
>  
>  /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 1cc98f5..698b5f2 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -272,7 +272,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const 
> MemMapEntry *memmap, int irq,
>  aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
>  aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
>  aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> -aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
> +aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), 
> NULL),

I'm not sure why you must extend this kind functions now. When I post
the patch to add aml_and(), you said
"
 +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
>> I know that it's possible to Store inside of And(a, b, save_here)
>> ASL op, but could you instead rewrite it to
>>
>>  Store(And(a, b), save_here)
>>
>> so it wouldn't clatter trivial  And(a,b) uses and drop this hunk.
>>
> Yes, we can use Store(And(a, b), save_here) but according to the SPEC
> the And op can have 3 args. We don't support it?
I don't think that we should do it if it could be implemented
using 2 already existing API calls to keep it simple and not to
pollute code with extra ", NULL" argument in most cases.
"

Thanks,
-- 
Shannon

Re: [Qemu-devel] [PATCH 07/74] acpi: aml: add helper for Opcode Arg2 Arg2 [Dst] AML pattern

[Shannon Zhao]

On 2015/12/10 7:41, Igor Mammedov wrote:
> Currently AML API doesn't compose terms in form of
> following pattern:
> 
>Opcode Arg2 Arg2 [Dst]
> 
> but ASL used in piix4/q35 DSDT ACPI tables uses that
> form, so for clean conversion of it, AML API should
> be able to handle an optional 'Dst' argumet used there.
> 
> Since above pattern is used by arithmetic/bit ops,
> introduce helper that they could reuse.
> It reduces code duplication in existing 5 aml_foo()
> functions and also will prevent more duplication
> when exiting functions are extended to support
> optional 'Dst' argument.
> 
> Signed-off-by: Igor Mammedov 
> ---
>  hw/acpi/aml-build.c | 61 
> -
>  1 file changed, 32 insertions(+), 29 deletions(-)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index a6e4c54..22015d2 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -436,44 +436,55 @@ Aml *aml_store(Aml *val, Aml *target)
>  return var;
>  }
>  
> -/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
> -Aml *aml_and(Aml *arg1, Aml *arg2)
> +/**
> + * build_opcode_2arg_dst:
> + * @op: 1-byte opcode
> + * @arg1: 1st operand
> + * @arg2: 2nd operand
> + * @dst: optional target to store to, set to NULL if it's not required
> + *
> + * An internal helper to compose AML terms that have
> + *   "Op Operand Operand Target"
> + * pattern.
> + *
> + * Returns: The newly allocated and composed according to patter Aml object.
> + */
> +static Aml *
> +build_opcode_2arg_dst(uint8_t op, Aml *arg1, Aml *arg2, Aml *dst)
>  {
> -Aml *var = aml_opcode(0x7B /* AndOp */);
> +Aml *var = aml_opcode(op);
>  aml_append(var, arg1);
>  aml_append(var, arg2);
> -build_append_byte(var->buf, 0x00 /* NullNameOp */);
> +if (dst) {
> +aml_append(var, dst);
> +} else {
> +build_append_byte(var->buf, 0x00 /* NullNameOp */);
> +}
>  return var;
>  }
> 
This looks good. Maybe you could add a helper like build_opcode_2arg(),
then aml_lor() and aml_lgreater() could use this.

-- 
Shannon

Re: [Qemu-devel] [PATCH 24/74] acpi: extend aml_interrupt() to support multiple irqs

[Shannon Zhao]

On 2015/12/10 7:41, Igor Mammedov wrote:
>  static void acpi_dsdt_add_virtio(Aml *scope,
>   const MemMapEntry *virtio_mmio_memmap,
> - int mmio_irq, int num)
> + uint32_t mmio_irq, int num)
>  {
>  hwaddr base = virtio_mmio_memmap->base;
>  hwaddr size = virtio_mmio_memmap->size;
> -int irq = mmio_irq;
> +uint32_t irq = mmio_irq;
>  int i;
>  
>  for (i = 0; i < num; i++) {
> @@ -152,15 +152,15 @@ static void acpi_dsdt_add_virtio(Aml *scope,
>  aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
>  aml_append(crs,
> aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> - AML_EXCLUSIVE, irq + i));
> + AML_EXCLUSIVE, &irq, 1));

This looks not right. You could move uint32_t irq = mmio_irq; into the
for loop and make it as uint32_t irq = mmio_irq + i;

Thanks,
-- 
Shannon

Re: [Qemu-devel] [v3 1/3] cutils: add avx2 instruction optimization

[Li, Liang Z]

> On 12/09/2015 01:32 AM, Li, Liang Z wrote:
> > I think you means the ' __attribute__((target("avx2")))', I have tried this
> way, the issue here is:
> >   without the ' -mavx2' option for gcc, there are compiling error:
> > '__m256i undeclared', the __attribute__((target("avx2"))) can't solve this
> issue.  Any idea?
> 
> You're right that you can't use the normal __m256i, as it doesn't get 
> declared.
>   But you can define the same type within the function itself.
> 
> Which is a simple matter of
> 
>typedef long long __m256i __attribute__((vector_size(32)));
> 
>  From there, you might as well rely on other gcc extensions to instead write
> 
> __m256i tmp0 = p[i + 0] | p[i + 1];
> 
> rather than obfuscating the code with AVX2_VEC_OR.
> 
>
Comparing this way to  putting the related code to a separate file, I think the 
latter is more simple.

Thanks
Liang 

Re: [Qemu-devel] subpage_write() and duplicated memory_region_ops_write tracepoints

[Hollis Blanchard]

On 12/09/2015 01:12 PM, Paolo Bonzini wrote:


On 09/12/2015 21:54, Hollis Blanchard wrote:

#0  trace_memory_region_ops_write (mr=0x185b620, addr=16, absaddr=738205712, 
value=136, size=4)
 at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/trace/generated-tracers.h:7374
#1  0x0045eb8a in *memory_region_write_with_attrs_accessor* 
(mr=0x185b620, addr=16,
 value=0x45203338, size=4, shift=0, mask=4294967295, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:513
#2  0x0045ed08 in access_with_adjusted_size (addr=16, value=0x45203338, 
size=4,
 access_size_min=1, access_size_max=4, access=0x45eb15 
,
 mr=0x185b620, attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:556
#3  0x00461ed7 in memory_region_dispatch_write (mr=0x185b620, addr=16, 
data=136, size=4,
 attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:1214
#4  0x00411bbf in address_space_rw (as=0x11f3440, addr=738205712, 
attrs=...,
 buf=0x45203490 "\210", len=4, is_write=true)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2497
#5  0x00411ea9 in address_space_write (as=0x11f3440, addr=738205712, 
attrs=...,
 buf=0x45203490 "\210", len=4) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2579
#6  0x00410d89 in subpage_write (opaque=0x19148f0, addr=16, value=136, 
len=4, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2139
#7  0x0045ebb2 in *memory_region_write_with_attrs_accessor* 
(mr=0x19148f0, addr=16,
 value=0x452035a8, size=4, shift=0, mask=4294967295, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:516
#8  0x0045ed08 in access_with_adjusted_size (addr=16, value=0x452035a8, 
size=4,
 access_size_min=1, access_size_max=8, access=0x45eb15 
,
 mr=0x19148f0, attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:556
#9  0x00461ed7 in memory_region_dispatch_write (mr=0x19148f0, addr=16, 
data=136, size=4,
 attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:1214
#10 0x0046c61c in io_writel (env=0x2aabace89268, 
iotlbentry=0x2aabace99808, val=136,
 addr=18446743523953745936, retaddr=1107508028)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/softmmu_template.h:470
#11 0x0046c3cb in helper_le_stl_mmu (env=0x2aabace89268, 
addr=18446743523953745936, val=136,
 oi=33, retaddr=1107508028)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/softmmu_template.h:510
#12 0x42033b3e in code_gen_buffer ()


The first tracepoint in each pair is an artifact, and should be omitted.
Any suggestions? We could special case "if (mr->ops->write !=
subpage_write) { emit tracepoint }", but that's a bit of a hack... :-)

You can add an argument to the tracepoint for mr->subpage.  I would keep
the duplicate however.
OK, I understand your suggestion now, but not your rationale. Are you 
thinking about QEMU developers needing to debug the subpage 
implementation? If so, I think tracing guest MMIO activity is a far more 
common need... perhaps we could use a different tracepoint for the latter?


if (mr->subpage)
trace_memory_region_ops_write_subpage(mr, addr, tmp, size);
else
trace_memory_region_ops_write(mr, addr, tmp, size);

That way, people debugging guest behavior can enable just the 
memory_region_ops_write tracepoint, and QEMU developers can also enable 
the other.


Hollis Blanchard
Mentor Graphics Emulation Division

Re: [Qemu-devel] [PATCH] configure: remove bashism (since 2010)

[Marc-André Lureau]

Hi

On Thu, Dec 10, 2015 at 1:53 AM,   wrote:
> From: Marc-André Lureau 
>
> "type" is not POSIX shell, but a bashism. (found thanks to shellcheck)
>

A subsidiary question is whether qemu really care about using POSIX
shell, or we can just depend on bashism. That would help with
simplifying some Makefile lines too.

> Signed-off-by: Marc-André Lureau 
> ---
>  configure | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configure b/configure
> index ba57b3f..90eff82 100755
> --- a/configure
> +++ b/configure
> @@ -158,7 +158,7 @@ symlink() {
>  # check whether a command is available to this shell (may be either an
>  # executable or a builtin)
>  has() {
> -type "$1" >/dev/null 2>&1
> +which "$1" >/dev/null 2>&1
>  }
>
>  # search for an executable in PATH
> --
> 2.5.0
>
>



-- 
Marc-André Lureau

[Qemu-devel] [PATCH] configure: remove bashism (since 2010)

[marcandre . lureau]

From: Marc-André Lureau 

"type" is not POSIX shell, but a bashism. (found thanks to shellcheck)

Signed-off-by: Marc-André Lureau 
---
 configure | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure b/configure
index ba57b3f..90eff82 100755
--- a/configure
+++ b/configure
@@ -158,7 +158,7 @@ symlink() {
 # check whether a command is available to this shell (may be either an
 # executable or a builtin)
 has() {
-type "$1" >/dev/null 2>&1
+which "$1" >/dev/null 2>&1
 }
 
 # search for an executable in PATH
-- 
2.5.0

[Qemu-devel] [PATCH 2/2] configure: fix trace backend check

[marcandre . lureau]

From: Marc-André Lureau 

Found thanks to shellcheck!

Signed-off-by: Marc-André Lureau 
---
 configure | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure b/configure
index 6a971a2..ba57b3f 100755
--- a/configure
+++ b/configure
@@ -4816,7 +4816,7 @@ echo "libcap-ng support $cap_ng"
 echo "vhost-net support $vhost_net"
 echo "vhost-scsi support $vhost_scsi"
 echo "Trace backends$trace_backends"
-if test "$trace_backend" = "simple"; then
+if have_backend "simple"; then
 echo "Trace output file $trace_file-"
 fi
 if test "$spice" = "yes"; then
-- 
2.5.0

[Qemu-devel] [PATCH 1/2] configure: remove unused or undefined variables

[marcandre . lureau]

From: Marc-André Lureau 

Found thanks to shellcheck!

Signed-off-by: Marc-André Lureau 
---
 configure | 6 --
 1 file changed, 6 deletions(-)

diff --git a/configure b/configure
index b55dcdd..6a971a2 100755
--- a/configure
+++ b/configure
@@ -3994,7 +3994,6 @@ EOF
 fi
 
 # check for smartcard support
-smartcard_cflags=""
 if test "$smartcard" != "no"; then
 if $pkg_config libcacard; then
 libcacard_cflags=$($pkg_config --cflags libcacard)
@@ -4356,7 +4355,6 @@ fi
 # If we can't selectively disable warning in the code, disable -Werror so that
 # the build doesn't fail anyway.
 
-pragma_disable_unused_but_set=no
 cat > $TMPC << EOF
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wunused-but-set-variable"
@@ -4791,9 +4789,6 @@ if test "$vnc" = "yes" ; then
 echo "VNC JPEG support  $vnc_jpeg"
 echo "VNC PNG support   $vnc_png"
 fi
-if test -n "$sparc_cpu"; then
-echo "Target Sparc Arch $sparc_cpu"
-fi
 echo "xen support   $xen"
 if test "$xen" = "yes" ; then
   echo "xen ctrl version  $xen_ctrl_version"
@@ -5285,7 +5280,6 @@ if test "$qom_cast_debug" = "yes" ; then
 fi
 if test "$rbd" = "yes" ; then
   echo "CONFIG_RBD=m" >> $config_host_mak
-  echo "RBD_CFLAGS=$rbd_cflags" >> $config_host_mak
   echo "RBD_LIBS=$rbd_libs" >> $config_host_mak
 fi
 
-- 
2.5.0

Re: [Qemu-devel] subpage_write() and duplicated memory_region_ops_write tracepoints

[Hollis Blanchard]

On 12/09/2015 01:12 PM, Paolo Bonzini wrote:

On 09/12/2015 21:54, Hollis Blanchard wrote:

#0  trace_memory_region_ops_write (mr=0x185b620, addr=16, absaddr=738205712, 
value=136, size=4)
 at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/trace/generated-tracers.h:7374
#1  0x0045eb8a in memory_region_write_with_attrs_accessor 
(mr=0x185b620, addr=16,
 value=0x45203338, size=4, shift=0, mask=4294967295, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:513
#2  0x0045ed08 in access_with_adjusted_size (addr=16, value=0x45203338, 
size=4,
 access_size_min=1, access_size_max=4, access=0x45eb15 
,
 mr=0x185b620, attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:556
#3  0x00461ed7 in memory_region_dispatch_write (mr=0x185b620, addr=16, 
data=136, size=4,
 attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:1214
#4  0x00411bbf in address_space_rw (as=0x11f3440, addr=738205712, 
attrs=...,
 buf=0x45203490 "\210", len=4, is_write=true)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2497
#5  0x00411ea9 in address_space_write (as=0x11f3440, addr=738205712, 
attrs=...,
 buf=0x45203490 "\210", len=4) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2579
#6  0x00410d89 in subpage_write (opaque=0x19148f0, addr=16, value=136, 
len=4, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/exec.c:2139
#7  0x0045ebb2 in memory_region_write_with_attrs_accessor 
(mr=0x19148f0, addr=16,
 value=0x452035a8, size=4, shift=0, mask=4294967295, attrs=...)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:516
#8  0x0045ed08 in access_with_adjusted_size (addr=16, value=0x452035a8, 
size=4,
 access_size_min=1, access_size_max=8, access=0x45eb15 
,
 mr=0x19148f0, attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:556
#9  0x00461ed7 in memory_region_dispatch_write (mr=0x19148f0, addr=16, 
data=136, size=4,
 attrs=...) at 
/scratch1/hblancha/install/customq/qemu-2.4.0/src/memory.c:1214
#10 0x0046c61c in io_writel (env=0x2aabace89268, 
iotlbentry=0x2aabace99808, val=136,
 addr=18446743523953745936, retaddr=1107508028)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/softmmu_template.h:470
#11 0x0046c3cb in helper_le_stl_mmu (env=0x2aabace89268, 
addr=18446743523953745936, val=136,
 oi=33, retaddr=1107508028)
 at /scratch1/hblancha/install/customq/qemu-2.4.0/src/softmmu_template.h:510
#12 0x42033b3e in code_gen_buffer ()


The first tracepoint in each pair is an artifact, and should be omitted.
Any suggestions? We could special case "if (mr->ops->write !=
subpage_write) { emit tracepoint }", but that's a bit of a hack... :-)

You can add an argument to the tracepoint for mr->subpage.  I would keep
the duplicate however.


Not sure I understand. Do you mean something like this?
-trace_memory_region_ops_write(mr, addr, tmp, size);
+trace_memory_region_ops_write(mr, addr, mr->ops->write == 
subpage_write, tmp, size);


Maybe this isn't the right tracepoint to begin with. I'm trying to trace 
guest MMIO activity; is there a better place to intercept that?


Hollis Blanchard
Mentor Graphics Emulation Division

[Qemu-devel] [PATCH 0/1] m68k linux user-space emulation fix (with sign-off this time)

[Michael Karcher]

This patch fixes cmake blocking on m68k when starting the second child
process. cmake relies on getting SIGCHLD to know when the child process 
finished,
and the uninitialised sigmask set on return of the first SIGCHLD oftentimes
blocked the second SIGCHLD.

The patch has been created against Laurent's qemu-m68k git tree, but according
to visual inspection, it should also apply to HEAD.

Michael Karcher (1):
  Fix do_rt_sigreturn on m68k linux userspace emulation

 linux-user/signal.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

-- 
2.1.4

[Qemu-devel] [PATCH 1/1] Fix do_rt_sigreturn on m68k linux userspace emulation

[Michael Karcher]

do_rt_sigreturn forgets to initialize the signal mask variable before
trying to use it to restore the mask, so the signal mask is undefined
after do_rt_sigreturn. This bug has been in all the time since
7181155d when do_rt_sigreturn was implemented for m68k.
---
 linux-user/signal.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index e03ed60..ae1014b 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -5260,11 +5260,14 @@ long do_rt_sigreturn(CPUM68KState *env)
 abi_ulong frame_addr = env->aregs[7] - 4;
 target_sigset_t target_set;
 sigset_t set;
-int d0;
+int d0, i;
 
 if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
 goto badframe;
 
+for(i = 0; i < TARGET_NSIG_WORDS; i++) {
+target_set.sig[i] = frame->uc.tuc_sigmask.sig[i];
+}
 target_to_host_sigset_internal(&set, &target_set);
 do_sigprocmask(SIG_SETMASK, &set, NULL);
 
-- 
2.1.4

Re: [Qemu-devel] [Patch V0] x86, mce: Basic support to add LMCE support to QEMU

[Raj, Ashok]

On Wed, Dec 09, 2015 at 10:07:48PM +0100, Paolo Bonzini wrote:
> 
> 
> On 09/12/2015 20:57, Ashok Raj wrote:
> > +/*
> > + * We need to read back the value of MSREXT_MCG_CTL that was set by the
> > + * guest kernel back into Qemu
> > + */
> > +cs->kvm_vcpu_dirty = false;
> > +cpu_synchronize_state(cs);

This wasn't in my original patch, but was found required.

Will have Gong check this and report back.
> 
> This should not be necessary.  I've only skimmed the patches but, apart
> from this, the patches look good.  Eduardo knows more than me about
> machine types and backwards compatibility to older kernels, however, and
> I'm deferring to him on this aspect.
> 
> How was this tested?  (In general, how do you test MCE? :))

We tested on a real hardware that supported error injection via EINJ.

One additional patch is required to support the testing to translate
from GPA to HPA. Probably we could include this as well to make it easy
and not have us maintain out of tree? 

Here are logs from Gong's testing.. he has a pretty eloborate test to 
test this.  :-)

Look at the MCGCAP and MCGSTATUS in host and guest for the values
introduced by this change set.

===

dmesg on guest system:
…
[   35.294009] mce: [Hardware Error]: Machine check events logged
[   35.294009] mce: Uncorrected hardware memory error in user-access at 7451b000
[   35.334006] MCE 0x7451b: Killing victim:1822 due to hardware memory 
corruption
[   35.334515] MCE 0x7451b: dirty mlocked LRU page still referenced by 1 users
[   35.334930] MCE 0x7451b: recovery action for dirty mlocked LRU page: Failed
[   35.335372] mce: Memory error not recovered
…



dmesg on host system:
…
[57629.858659] kvm: zapping shadow pages for mmio generation wraparound
[57629.859592] kvm: zapping shadow pages for mmio generation wraparound
[57637.023199] kvm [46095]: vcpu0 disabled perfctr wrmsr: 0xc2 data 0x
[57637.116429] kvm [46095]: vcpu0 unhandled rdmsr: 0x570
[57637.122112] kvm [46095]: vcpu1 unhandled rdmsr: 0x570
[57672.381651] mce: [Hardware Error]: Machine check events logged
[57672.388178] mce: Uncorrected hardware memory error in user-access at 
1da71b000
[57672.396057] mce: [Hardware Error]: Machine check events logged
[57672.403345] MCE 0x1da71b: Killing qemu-system-x86:46095 due to hardware 
memory corruption
[57672.412499] MCE 0x1da71b: recovery action for dirty LRU page: Recovered

===
Mcelog on host system:

[root@BKD06SDP host]# mcelog
Hardware event. This is not a software error.
MCE 0
CPU 68 BANK 1 TSC 835ad3e00dfe
MISC 86 ADDR 1da71b000
TIME 1449669775 Wed Dec  9 09:02:55 2015
MCG status:RIPV EIPV MCIP
MCi status:
Uncorrected error
Error enabled
MCi_MISC register valid
MCi_ADDR register valid
SRAR
MCA: Data CACHE Level-0 Data-Read Error
STATUS bd8000100134 MCGSTATUS 7
MCGCAP 7000c16 APICID f0 SOCKETID 3
CPUID Vendor Intel Family 6 Model 63
Hardware event. This is not a software error.
MCE 1
CPU 0 BANK 7
MISC 146588a86 ADDR 1da71b000
TIME 1449669775 Wed Dec  9 09:02:55 2015
MCG status:
MCi status:
Uncorrected error
MCi_MISC register valid
MCi_ADDR register valid
MCA: MEMORY CONTROLLER RD_CHANNEL2_ERR
Transaction: Memory read error
STATUS ac010092 MCGSTATUS 0
MCGCAP 7000c16 APICID 0 SOCKETID 0
CPUID Vendor Intel Family 6 Model 63
[root@BKD06SDP host]#



GUEST system mcelog:

[root@localhost ~]# cat /var/log/mcelog
mcelog: mcelog server already running
mcelog: mcelog server already running
Hardware event. This is not a software error.
MCE 0
CPU 0 BANK 9 TSC 18ce71469a
RIP 33:401535
MISC 8c ADDR 7451b000
TIME 1449669775 Wed Dec  9 09:02:55 2015
MCG status:EIPV MCIP LMCE
MCi status:
Uncorrected error
Error enabled
MCi_MISC register valid
MCi_ADDR register valid
SRAR
MCA: Data CACHE Level-0 Data-Read Error
STATUS bd800134 MCGSTATUS e
MCGCAP 900010a APICID 0 SOCKETID 0
CPUID Vendor Intel Family 6 Model 6
Signed-off-by: Feng Liu 

From: root 


---
 hmp-commands.hx   |   14 ++
 include/exec/memory.h |2 ++
 kvm-all.c |   24 
 memory.c  |   13 +
 monitor.c |   16 
 5 files changed, 69 insertions(+)
 mode change 100644 => 100755 include/exec/memory.h
 mode change 100644 => 100755 kvm-all.c
 mode change 100644 => 100755 memory.c
 mode change 100644 => 100755 monitor.c

diff --git a/hmp-commands.hx b/hmp-commands.hx
index bb52e4d..673c00e 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -444,6 +444,20 @@ Start gdbserver session (default @var{port}=1234)
 ETEXI
 
 {
+.name = "x-gpa2hva",
+.ar

[Qemu-devel] [Patch V0] This patch adds some support required for KVM in order to support LMCE.

[Ashok Raj]

- Add support for MSR_IA32_MCG_EXT_CTL
- Add MCG_LMCE_P to KVM_MCE_CAP_SUPPORTED
- Changes to IA32_FEATURE_CONTROL, allow this MSR to be defined just not for
  nested VMM, but now its required for Local MCE.

Reviewed-by: Andi Kleen 
Reviewed-by: Tony Luck 
Tested-by: Gong Chen 
Signed-off-by: Ashok Raj 
---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/vmx.c  | 26 +-
 arch/x86/kvm/x86.c  | 17 -
 3 files changed, 38 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 30cfd64..6940141 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -525,6 +525,7 @@ struct kvm_vcpu_arch {
u64 mcg_cap;
u64 mcg_status;
u64 mcg_ctl;
+   u64 mcg_ext_ctl;
u64 *mce_banks;
 
/* Cache MMIO info */
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 87acc52..c2ce9f4 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2747,6 +2747,20 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 
msr_index, u64 *pdata)
return 0;
 }
 
+bool can_feature_control_exist(struct kvm_vcpu *vcpu)
+{
+   /*
+* There are some features that require BIOS enabling.
+* In such cases BIOS is supposed to set this bit and indicate
+* the feature is enabled and available to the OS.
+* Local Machine Check Exception (LMCE) is one such feature.
+*/
+   if (vcpu->arch.mcg_cap & MCG_LMCE_P)
+   return true;
+
+   return (nested_vmx_allowed(vcpu));
+}
+
 /*
  * Reads an msr value (of 'msr_index') into 'pdata'.
  * Returns 0 on success, non-0 otherwise.
@@ -2789,9 +2803,11 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
msr_info->data = vmcs_read64(GUEST_BNDCFGS);
break;
case MSR_IA32_FEATURE_CONTROL:
-   if (!nested_vmx_allowed(vcpu))
+   if (can_feature_control_exist(vcpu))
+   msr_info->data =
+   to_vmx(vcpu)->nested.msr_ia32_feature_control;
+   else
return 1;
-   msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
break;
case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
if (!nested_vmx_allowed(vcpu))
@@ -2882,9 +2898,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
ret = kvm_set_msr_common(vcpu, msr_info);
break;
case MSR_IA32_FEATURE_CONTROL:
-   if (!nested_vmx_allowed(vcpu) ||
-   (to_vmx(vcpu)->nested.msr_ia32_feature_control &
-FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
+   if ((can_feature_control_exist(vcpu) == false) ||
+   ((to_vmx(vcpu)->nested.msr_ia32_feature_control &
+FEATURE_CONTROL_LOCKED) && !msr_info->host_initiated))
return 1;
vmx->nested.msr_ia32_feature_control = data;
if (msr_info->host_initiated && data == 0)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 00462bd..0da3871 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -70,7 +70,7 @@
 
 #define MAX_IO_MSRS 256
 #define KVM_MAX_MCE_BANKS 32
-#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
+#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P | MCG_LMCE_P)
 
 #define emul_to_vcpu(ctxt) \
container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
@@ -974,6 +974,7 @@ static u32 emulated_msrs[] = {
MSR_IA32_MISC_ENABLE,
MSR_IA32_MCG_STATUS,
MSR_IA32_MCG_CTL,
+   MSR_IA32_MCG_EXT_CTL,
MSR_IA32_SMBASE,
 };
 
@@ -1913,6 +1914,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, 
u64 data)
return -1;
vcpu->arch.mcg_ctl = data;
break;
+   case MSR_IA32_MCG_EXT_CTL:
+   if (!(mcg_cap & MCG_LMCE_P))
+   return 1;
+   if (data != 0 && data != 0x1)
+   return -1;
+   vcpu->arch.mcg_ext_ctl = data;
+   break;
default:
if (msr >= MSR_IA32_MC0_CTL &&
msr < MSR_IA32_MCx_CTL(bank_num)) {
@@ -2170,6 +2178,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
 
case MSR_IA32_MCG_CTL:
case MSR_IA32_MCG_STATUS:
+   case MSR_IA32_MCG_EXT_CTL:
case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
return set_msr_mce(vcpu, msr, data);
 
@@ -2266,6 +2275,11 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, 
u64 *pdata)
return 1;
data = vcpu->arch.mcg_ctl;
break;
+   case MSR_IA32_MCG_EXT_CTL:
+   if (!(mcg_cap & MCG_LMCE_P))
+ 

[Qemu-devel] [PATCH 1/1] Fix do_rt_sigreturn on m68k linux userspace emulation

[Michael Karcher]

do_rt_sigreturn forgets to initialize the signal mask variable before
trying to use it to restore the mask, so the signal mask is undefined
after do_rt_sigreturn. This bug has been in all the time since
7181155d when do_rt_sigreturn was implemented for m68k.

Signed-off-by: Michael Karcher 
---
 linux-user/signal.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index e03ed60..ae1014b 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -5260,11 +5260,14 @@ long do_rt_sigreturn(CPUM68KState *env)
 abi_ulong frame_addr = env->aregs[7] - 4;
 target_sigset_t target_set;
 sigset_t set;
-int d0;
+int d0, i;
 
 if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
 goto badframe;
 
+for(i = 0; i < TARGET_NSIG_WORDS; i++) {
+target_set.sig[i] = frame->uc.tuc_sigmask.sig[i];
+}
 target_to_host_sigset_internal(&set, &target_set);
 do_sigprocmask(SIG_SETMASK, &set, NULL);
 
-- 
2.1.4

[Qemu-devel] [Bug 1524546] [NEW] qemu-img rebase error message mentions wrong file name

[Surojit Pathak]

Public bug reported:

While doing 'qemu-img rebase' for linking to a different backing file, if the 
old backing file does not exist, the command fails. During this failure, the 
error message shown is misleading.
e.g. qemu-img rebase -b   throws error saying "Could 
not open "
Ideally it should "Could not open "

snippet -
[root@oxy-dev ~]# qemu-img info 
/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
image: /opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
file format: qcow2
virtual size: 20G (21474836480 bytes)
disk size: 174M
cluster_size: 65536
backing file: /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b
Format specific information:
compat: 1.1
lazy refcounts: false
[root@oxy-dev ~]# mv /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b 
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383a
[root@oxy-dev ~]# file !$
file /tmp/3559241a79b79ae663ec6e3d9b75d469967b383a
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383a: x86 boot sector; partition 1: 
ID=0x83, active, starthead 32, startsector 2048, 409600 sectors; partition 2: 
ID=0x8e, starthead 159, startsector 411648, 16365568 sectors, code offset 0xc0
[root@oxy-dev ~]# file /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383b: cannot open (No such file or 
directory)
[root@oxy-dev ~]# qemu-img rebase -b 
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383a 
/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
qemu-img: Could not open 
'/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk': 
Could not open file: No such file or directory
[root@oxy-dev ~]# 
qemu-img version 1.5.3
OS: RHEL7 - 3.10.0-229
libvirtd (libvirt) 1.2.8

** Affects: qemu
 Importance: Undecided
 Status: New

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1524546

Title:
  qemu-img rebase error message mentions wrong file name

Status in QEMU:
  New

Bug description:
  While doing 'qemu-img rebase' for linking to a different backing file, if the 
old backing file does not exist, the command fails. During this failure, the 
error message shown is misleading.
  e.g. qemu-img rebase -b   throws error saying "Could 
not open "
  Ideally it should "Could not open "

  snippet -
  [root@oxy-dev ~]# qemu-img info 
/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
  image: 
/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
  file format: qcow2
  virtual size: 20G (21474836480 bytes)
  disk size: 174M
  cluster_size: 65536
  backing file: /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b
  Format specific information:
  compat: 1.1
  lazy refcounts: false
  [root@oxy-dev ~]# mv /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b 
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383a
  [root@oxy-dev ~]# file !$
  file /tmp/3559241a79b79ae663ec6e3d9b75d469967b383a
  /tmp/3559241a79b79ae663ec6e3d9b75d469967b383a: x86 boot sector; partition 1: 
ID=0x83, active, starthead 32, startsector 2048, 409600 sectors; partition 2: 
ID=0x8e, starthead 159, startsector 411648, 16365568 sectors, code offset 0xc0
  [root@oxy-dev ~]# file /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b
  /tmp/3559241a79b79ae663ec6e3d9b75d469967b383b: cannot open (No such file or 
directory)
  [root@oxy-dev ~]# qemu-img rebase -b 
/tmp/3559241a79b79ae663ec6e3d9b75d469967b383a 
/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk
  qemu-img: Could not open 
'/opt/stack/data/nova/instances/94864a64-ebf8-45e6-a777-615921216a0a/disk': 
Could not open file: No such file or directory
  [root@oxy-dev ~]# 
  qemu-img version 1.5.3
  OS: RHEL7 - 3.10.0-229
  libvirtd (libvirt) 1.2.8

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1524546/+subscriptions

[Qemu-devel] [Patch V0] x86, mce: Basic support to add LMCE support to QEMU

[Ashok Raj]

This patch adds basic enumeration, control msr's required to support
Local Machine Check Exception Support (LMCE).

- Added Local Machine Check definitions, changed MCG_CAP
- Added support for IA32_FEATURE_CONTROL.
- When delivering MCE to guest, we deliver to just a single CPU
  when guest OS has opted in to Local delivery.

Signed-off-by: Ashok Raj 
Tested-by: Gong Chen 
---
 target-i386/cpu.c |  8 
 target-i386/cpu.h |  8 ++--
 target-i386/kvm.c | 39 ---
 3 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 11e5e39..167669a 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2737,6 +2737,13 @@ static void mce_init(X86CPU *cpu)
 }
 }
 
+static void feature_control_init(X86CPU *cpu)
+{
+   CPUX86State *cenv = &cpu->env;
+
+   cenv->msr_ia32_feature_control = ((1<<20) | (1<<0));
+}
+
 #ifndef CONFIG_USER_ONLY
 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
 {
@@ -2858,6 +2865,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error 
**errp)
 #endif
 
 mce_init(cpu);
+feature_control_init(cpu);
 
 #ifndef CONFIG_USER_ONLY
 if (tcg_enabled()) {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 84edfd0..a567d7a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -282,8 +282,9 @@
 
 #define MCG_CTL_P   (1ULL<<8)   /* MCG_CAP register available */
 #define MCG_SER_P   (1ULL<<24) /* MCA recovery/new status bits */
+#define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
 
-#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
+#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P|MCG_LMCE_P)
 #define MCE_BANKS_DEF   10
 
 #define MCG_CAP_BANKS_MASK 0xff
@@ -291,6 +292,7 @@
 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
+#define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
 
 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
@@ -333,6 +335,7 @@
 #define MSR_MCG_CAP 0x179
 #define MSR_MCG_STATUS  0x17a
 #define MSR_MCG_CTL 0x17b
+#define MSR_MCG_EXT_CTL0x4d0
 
 #define MSR_P6_EVNTSEL0 0x186
 
@@ -892,7 +895,6 @@ typedef struct CPUX86State {
 
 uint64_t mcg_status;
 uint64_t msr_ia32_misc_enable;
-uint64_t msr_ia32_feature_control;
 
 uint64_t msr_fixed_ctr_ctrl;
 uint64_t msr_global_ctrl;
@@ -977,8 +979,10 @@ typedef struct CPUX86State {
 int64_t tsc_khz;
 void *kvm_xsave_buf;
 
+uint64_t msr_ia32_feature_control;
 uint64_t mcg_cap;
 uint64_t mcg_ctl;
+uint64_t mcg_ext_ctl;
 uint64_t mce_banks[MCE_BANKS_DEF*4];
 
 uint64_t tsc_aux;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 6dc9846..d787fd9 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -72,6 +72,7 @@ static bool has_msr_tsc_aux;
 static bool has_msr_tsc_adjust;
 static bool has_msr_tsc_deadline;
 static bool has_msr_feature_control;
+static bool has_msr_ext_mcg_ctl;
 static bool has_msr_async_pf_en;
 static bool has_msr_pv_eoi_en;
 static bool has_msr_misc_enable;
@@ -370,18 +371,31 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int 
code)
 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
   MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 uint64_t mcg_status = MCG_STATUS_MCIP;
+int flags = 0;
+CPUState *cs = CPU(cpu);
+
+/*
+ * We need to read back the value of MSREXT_MCG_CTL that was set by the
+ * guest kernel back into Qemu
+ */
+cs->kvm_vcpu_dirty = false;
+cpu_synchronize_state(cs);
+
+flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 
 if (code == BUS_MCEERR_AR) {
-status |= MCI_STATUS_AR | 0x134;
-mcg_status |= MCG_STATUS_EIPV;
+   status |= MCI_STATUS_AR | 0x134;
+   mcg_status |= MCG_STATUS_EIPV;
+   if (env->mcg_ext_ctl & 0x1) {
+   mcg_status |= MCG_STATUS_LMCE;
+   flags = 0; /* No Broadcast when LMCE is opted by guest */
+   }
 } else {
 status |= 0xc0;
 mcg_status |= MCG_STATUS_RIPV;
 }
 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
-   (MCM_ADDR_PHYS << 6) | 0xc,
-   cpu_x86_support_mca_broadcast(env) ?
-   MCE_INJECT_BROADCAST : 0);
+  (MCM_ADDR_PHYS << 6) | 0xc, flags);
 }
 
 static void hardware_memory_error(void)
@@ -808,10 +822,14 @@ int kvm_arch_init_vcpu(CPUState *cs)
 
 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
 if (c) {
-has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
-  !!(c->ecx & CPUID_EXT_SMX);
+has_msr_featu

[Qemu-devel] [PATCH 74/74] pc: acpi: remove unused ASL templates and related blobs/utils

[Igor Mammedov]

QEMU now uses internally composed DSDT so drop now
empty *.dsl templates and related *.generated
binary blobs.

Also since templates are not used anymore/obolete
remove utility scripts used for extracting/patching
AML blobs compiled by IASL and for updating them
in git tree.

Signed-off-by: Igor Mammedov 
---
 hw/i386/Makefile.objs   |   31 +-
 hw/i386/acpi-dsdt.dsl   |   33 -
 hw/i386/acpi-dsdt.hex.generated | 2972 --
 hw/i386/q35-acpi-dsdt.dsl   |   40 -
 hw/i386/q35-acpi-dsdt.hex.generated | 7610 ---
 scripts/acpi_extract.py |  367 --
 scripts/acpi_extract_preprocess.py  |   51 -
 scripts/update-acpi.sh  |4 -
 8 files changed, 1 insertion(+), 11107 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt.dsl
 delete mode 100644 hw/i386/acpi-dsdt.hex.generated
 delete mode 100644 hw/i386/q35-acpi-dsdt.dsl
 delete mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
 delete mode 100755 scripts/acpi_extract.py
 delete mode 100755 scripts/acpi_extract_preprocess.py
 delete mode 100644 scripts/update-acpi.sh

diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index c250deb..fd4a524 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -8,33 +8,4 @@ obj-$(CONFIG_XEN) += ../xenpv/ xen/
 obj-y += kvmvapic.o
 obj-y += acpi-build.o
 obj-y += pci-assign-load-rom.o
-
-gen-hex-y += hw/i386/acpi-dsdt.hex
-gen-hex-y += hw/i386/q35-acpi-dsdt.hex
-
-hw/i386/acpi-build.o: hw/i386/acpi-build.c \
-   $(gen-hex-y)
-
--include $(gen-hex-y:.hex=.d)
-
-iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
-; then echo "$(2)"; else echo "$(3)"; fi ;)
-
-ifdef IASL
-#IASL Present. Generate hex files from .dsl
-hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl 
$(SRC_PATH)/scripts/acpi_extract_preprocess.py 
$(SRC_PATH)/scripts/acpi_extract.py
-   $(call quiet-command, $(CPP) -x c -P $(QEMU_DGFLAGS) $(QEMU_INCLUDES) 
$< -o $*.dsl.i.orig, "  CPP $(TARGET_DIR)$*.dsl.i.orig")
-   $(call quiet-command, $(PYTHON) 
$(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig > $*.dsl.i, "  
ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i")
-   $(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l 
-tc -p $* $*.dsl.i $(if $(V), , > /dev/null) 2>&1 ,"  IASL 
$(TARGET_DIR)$*.dsl.i")
-   $(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract.py 
$*.lst > $*.off, "  ACPI_EXTRACT $(TARGET_DIR)$*.off")
-   $(call quiet-command, cat $*.off > $@, "  CAT $(TARGET_DIR)$@")
-else
-#IASL Not present. Restore pre-generated hex files.
-hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.hex.generated
-   $(call quiet-command, cp -f $< $@, "  CP $(TARGET_DIR)$@")
-endif
-
-.PHONY: cleanhex
-cleanhex:
-   rm -f hw/i386/*hex
-clean: cleanhex
+obj-y += acpi-build.o
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
deleted file mode 100644
index 82e4470..000
--- a/hw/i386/acpi-dsdt.dsl
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Bochs/QEMU ACPI DSDT ASL definition
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License version 2 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode
-
-DefinitionBlock (
-"acpi-dsdt.aml",// Output Filename
-"DSDT", // Signature
-0x01,   // DSDT Compliance Revision
-"BXPC", // OEMID
-"BXDSDT",   // TABLE ID
-0x1 // OEM Revision
-)
-{
-Scope(\_SB) {
-}
-}
diff --git a/hw/i386/acpi-dsdt.hex.generated b/hw/i386/acpi-dsdt.hex.generated
deleted file mode 100644
index ecaa4a5..000
--- a/hw/i386/acpi-dsdt.hex.generated
+++ /dev/null
@@ -1,2972 +0,0 @@
-static unsigned char AcpiDsdtAmlCode[] = {
-0x44,
-0x53,
-0x44,
-0x54,
-0x9a,
-0xb,
-0x0,
-0x0,
-0x1,
-0xf8,
-0x42,
-0x58,
-0x50,
-0x43,
-0x0,
-0x0,
-0x42,
-0x58,
-0x44,
-0x53,
-0x44,
-0x54,
-0x0,
-0x0,
-0x1,
-0x0,
-0x0,
-0x0,
-0x49,
-0x4e,
-0x54,
-0x4c,
-0x7,
-0x11,
-0x14,
-0x20,
-0x10,
-0x49,
-0x4,
-0x5c,
-0x0,
-0x5b,
-0x80,
-0x44,
-0x42,
-0x47,
-0x5f,
-0x1,
-0xb,
-0x2,
-0x4,
-0x1,
-0x5b,
-0x81,
-0xb,
-0x44,
-0x42,
-0x47,
-0x5f,
-0x1,
-0x44,
-0x42,
-0x47,
-0x42,
-0x8,
-0x14,
-0x2c,
-0x44,
-0x42,
-0x55,
-0x47,
-0x1,
-0x98,
-0x68,
-0x60,
-0x96,
-0x60,
-0x60,
-0x74,
-0x87,
-0x60,
-0x1,
-0x61,
-0x70,
-0x0,
-0x62,
-0xa2,
-0x10,
-0x95,
-0x62,
-0x61,
-0x70,
-0x83,
-0x88,
-0x60,
-0x62,

[Qemu-devel] [PATCH 67/74] pc: acpi: q35: move PRTA routing table into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 61 +++
 hw/i386/q35-acpi-dsdt.dsl | 57 ---
 2 files changed, 61 insertions(+), 57 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 744f047..0008d9f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1550,6 +1550,64 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(table, sb_scope);
 }
 
+static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
+{
+int i;
+int head;
+Aml *pkg;
+char base = name[3] < 'E' ? 'A' : 'E';
+char *s = g_strdup(name);
+Aml *a_nr = aml_int((nr << 16) | 0x);
+
+assert(strlen(s) == 4);
+
+head = name[3] - base;
+for (i = 0; i < 4; i++) {
+if (head + i > 3) {
+head = i * -1;
+}
+s[3] = base + head + i;
+pkg = aml_package(4);
+aml_append(pkg, a_nr);
+aml_append(pkg, aml_int(i));
+aml_append(pkg, aml_name("%s", s));
+aml_append(pkg, aml_int(0));
+aml_append(ctx, pkg);
+}
+g_free(s);
+}
+
+static Aml *build_q35_routing_table(const char *str)
+{
+int i;
+Aml *pkg;
+char *name = g_strdup_printf("%s ", str);
+
+pkg = aml_package(128);
+for (i = 0; i < 0x18; i++) {
+name[3] = 'E' + (i & 0x3);
+append_q35_prt_entry(pkg, i, name);
+}
+
+name[3] = 'E';
+append_q35_prt_entry(pkg, 0x18, name);
+
+/* INTA -> PIRQA for slot 25 - 31, see the default value of DIR */
+for (i = 0x0019; i < 0x1e; i++) {
+name[3] = 'A';
+append_q35_prt_entry(pkg, i, name);
+}
+
+/* PCIe->PCI bridge. use PIRQ[E-H] */
+name[3] = 'E';
+append_q35_prt_entry(pkg, 0x1e, name);
+name[3] = 'A';
+append_q35_prt_entry(pkg, 0x1f, name);
+
+g_free(name);
+return pkg;
+}
+
 static void build_q35_pci0_int(Aml *table)
 {
 Aml *field;
@@ -1557,6 +1615,9 @@ static void build_q35_pci0_int(Aml *table)
 Aml *sb_scope = aml_scope("_SB");
 Aml *pci0_scope = aml_scope("PCI0");
 
+aml_append(pci0_scope,
+aml_name_decl("PRTA", build_q35_routing_table("GSI")));
+
 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
 {
 Aml *if_ctx;
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index f265583..a3073ad 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -181,63 +181,6 @@ DefinitionBlock (
 
 prt_slot_lnkA(0x001f)
 })
-
-#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
-Package() { nr##, 0, gsi0, 0 },   \
-Package() { nr##, 1, gsi1, 0 },   \
-Package() { nr##, 2, gsi2, 0 },   \
-Package() { nr##, 3, gsi3, 0 }
-
-#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
-#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
-#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
-#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
-
-#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
-#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
-#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
-#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
-
-Name(PRTA, package() {
-prt_slot_gsiE(0x),
-prt_slot_gsiF(0x0001),
-prt_slot_gsiG(0x0002),
-prt_slot_gsiH(0x0003),
-prt_slot_gsiE(0x0004),
-prt_slot_gsiF(0x0005),
-prt_slot_gsiG(0x0006),
-prt_slot_gsiH(0x0007),
-prt_slot_gsiE(0x0008),
-prt_slot_gsiF(0x0009),
-prt_slot_gsiG(0x000a),
-prt_slot_gsiH(0x000b),
-prt_slot_gsiE(0x000c),
-prt_slot_gsiF(0x000d),
-prt_slot_gsiG(0x000e),
-prt_slot_gsiH(0x000f),
-prt_slot_gsiE(0x0010),
-prt_slot_gsiF(0x0011),
-prt_slot_gsiG(0x0012),
-prt_slot_gsiH(0x0013),
-prt_slot_gsiE(0x0014),
-prt_slot_gsiF(0x0015),
-prt_slot_gsiG(0x0016),
-prt_slot_gsiH(0x0017),
-prt_slot_gsiE(0x0018),
-
-/* INTA -> PIRQA for slot 25 - 31, but 30
-   see the default value of DIR */
-prt_slot_gsiA(0x0019),
-prt_slot_gsiA(0x001a),
-prt_slot_gsiA(0x001b),
-prt_slot_gsiA(0x001c),
-prt_slot_gsiA(0x001d),
-
-/* PCIe->PCI bridge. use PIRQ[E-H] */
-prt_slot_gsiE(0x001e),
-
-prt_slot_gsiA(0x001f)
-})
 }
 
 External(LNKA, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 65/74] pc: acpi: q35: move ISA bridge into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 54 +++
 hw/i386/q35-acpi-dsdt.dsl | 46 
 2 files changed, 54 insertions(+), 46 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2f0b9b7..876605d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1552,8 +1552,21 @@ static void build_piix4_pci0_int(Aml *table)
 
 static void build_q35_pci0_int(Aml *table)
 {
+Aml *field;
 Aml *sb_scope = aml_scope("_SB");
 
+field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("PRQA", 8));
+aml_append(field, aml_named_field("PRQB", 8));
+aml_append(field, aml_named_field("PRQC", 8));
+aml_append(field, aml_named_field("PRQD", 8));
+aml_append(field, aml_reserved_field(0x20));
+aml_append(field, aml_named_field("PRQE", 8));
+aml_append(field, aml_named_field("PRQF", 8));
+aml_append(field, aml_named_field("PRQG", 8));
+aml_append(field, aml_named_field("PRQH", 8));
+aml_append(sb_scope, field);
+
 aml_append(sb_scope, build_irq_status_method());
 aml_append(sb_scope, build_iqcr_method(false));
 
@@ -1582,6 +1595,46 @@ static void build_q35_pci0_int(Aml *table)
 aml_append(table, sb_scope);
 }
 
+static void build_q35_isa_bridge(Aml *table)
+{
+Aml *dev;
+Aml *scope;
+Aml *field;
+
+scope =  aml_scope("_SB.PCI0");
+dev = aml_device("ISA");
+aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F)));
+
+/* ICH9 PCI to ISA irq remapping */
+aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
+ 0x60, 0x0C));
+
+aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
+ 0x80, 0x02));
+field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("COMA", 3));
+aml_append(field, aml_reserved_field(1));
+aml_append(field, aml_named_field("COMB", 3));
+aml_append(field, aml_reserved_field(1));
+aml_append(field, aml_named_field("LPTD", 2));
+aml_append(field, aml_reserved_field(2));
+aml_append(field, aml_named_field("FDCD", 2));
+aml_append(dev, field);
+
+aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
+ 0x82, 0x02));
+/* enable bits */
+field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("CAEN", 1));
+aml_append(field, aml_named_field("CBEN", 1));
+aml_append(field, aml_named_field("LPEN", 1));
+aml_append(field, aml_named_field("FDEN", 1));
+aml_append(dev, field);
+
+aml_append(scope, dev);
+aml_append(table, scope);
+}
+
 static void build_piix4_pm(Aml *table)
 {
 Aml *dev;
@@ -1709,6 +1762,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_piix4_pci0_int(ssdt);
 } else {
 build_hpet_aml(ssdt);
+build_q35_isa_bridge(ssdt);
 build_isa_devices_aml(ssdt);
 build_q35_pci0_int(ssdt);
 }
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index ec8a48c..b01d4de 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -114,39 +114,6 @@ DefinitionBlock (
 }
 
 /
- * LPC ISA bridge
- /
-
-Scope(\_SB.PCI0) {
-/* PCI D31:f0 LPC ISA bridge */
-Device(ISA) {
-Name (_ADR, 0x001F)  // _ADR: Address
-
-/* ICH9 PCI to ISA irq remapping */
-OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
-
-OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
-Field(LPCD, AnyAcc, NoLock, Preserve) {
-COMA,   3,
-,   1,
-COMB,   3,
-
-Offset(0x01),
-LPTD,   2,
-,   2,
-FDCD,   2
-}
-OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
-Field(LPCE, AnyAcc, NoLock, Preserve) {
-CAEN,   1,
-CBEN,   1,
-LPEN,   1,
-FDEN,   1
-}
-}
-}
-
-/
  * PCI IRQs
  /
 
@@ -285,19 +252,6 @@ DefinitionBlock (
 }
 }
 
-Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
-PRQA,   8,
-PRQB,   8,
-PRQC,   8,
-PRQD,   8,
-
-Offset(0x08),
-PRQE,   8,
-PRQF,   8,
-PRQG,   8,
-PRQH,   8
-}
-
 External(LNKA, DeviceObj)
 External(LNKB, DeviceObj)
 External(LNKC, DeviceObj)
-- 
1.8.3.

[Qemu-devel] [PATCH 66/74] pc: acpi: q35: move _PRT() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 21 +
 hw/i386/q35-acpi-dsdt.dsl | 12 
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 876605d..744f047 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1553,7 +1553,28 @@ static void build_piix4_pci0_int(Aml *table)
 static void build_q35_pci0_int(Aml *table)
 {
 Aml *field;
+Aml *method;
 Aml *sb_scope = aml_scope("_SB");
+Aml *pci0_scope = aml_scope("PCI0");
+
+method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
+{
+Aml *if_ctx;
+Aml *else_ctx;
+
+/* PCI IRQ routing table, example from ACPI 2.0a specification,
+   section 6.2.8.1 */
+/* Note: we provide the same info as the PCI routing
+   table of the Bochs BIOS */
+if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
+aml_append(if_ctx, aml_return(aml_name("PRTP")));
+aml_append(method, if_ctx);
+else_ctx = aml_else();
+aml_append(else_ctx, aml_return(aml_name("PRTA")));
+aml_append(method, else_ctx);
+}
+aml_append(pci0_scope, method);
+aml_append(sb_scope, pci0_scope);
 
 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 aml_append(field, aml_named_field("PRQA", 8));
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index b01d4de..f265583 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -238,18 +238,6 @@ DefinitionBlock (
 
 prt_slot_gsiA(0x001f)
 })
-
-Method(_PRT, 0, NotSerialized) {
-/* PCI IRQ routing table, example from ACPI 2.0a specification,
-   section 6.2.8.1 */
-/* Note: we provide the same info as the PCI routing
-   table of the Bochs BIOS */
-If (LEqual(\PICF, Zero)) {
-Return (PRTP)
-} Else {
-Return (PRTA)
-}
-}
 }
 
 External(LNKA, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 62/74] pc: acpi: q35: move link devices to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  9 +
 hw/i386/q35-acpi-dsdt.dsl | 40 
 2 files changed, 17 insertions(+), 32 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 75a46c7..51a07eb 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1537,6 +1537,15 @@ static void build_q35_pci0_int(Aml *table)
 {
 Aml *sb_scope = aml_scope("_SB");
 
+aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
+aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
+aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
+aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
+aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
+aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
+aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
+aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
+
 /*
  * TODO: UID probably shouldn't be the same for GSIx devices
  * but that's how it was in original ASL so keep it for now
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index f2c154a..2da3515 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -315,38 +315,14 @@ DefinitionBlock (
 Return (PRR0)
 }
 
-#define define_link(link, uid, reg) \
-Device(link) {  \
-Name(_HID, EISAID("PNP0C0F"))   \
-Name(_UID, uid) \
-Name(_PRS, ResourceTemplate() { \
-Interrupt(, Level, ActiveHigh, Shared) {\
-5, 10, 11   \
-}   \
-})  \
-Method(_STA, 0, NotSerialized) {\
-Return (IQST(reg))  \
-}   \
-Method(_DIS, 0, NotSerialized) {\
-Or(reg, 0x80, reg)  \
-}   \
-Method(_CRS, 0, NotSerialized) {\
-Return (IQCR(reg))  \
-}   \
-Method(_SRS, 1, NotSerialized) {\
-CreateDWordField(Arg0, 0x05, PRRI)  \
-Store(PRRI, reg)\
-}   \
-}
-
-define_link(LNKA, 0, PRQA)
-define_link(LNKB, 1, PRQB)
-define_link(LNKC, 2, PRQC)
-define_link(LNKD, 3, PRQD)
-define_link(LNKE, 4, PRQE)
-define_link(LNKF, 5, PRQF)
-define_link(LNKG, 6, PRQG)
-define_link(LNKH, 7, PRQH)
+External(LNKA, DeviceObj)
+External(LNKB, DeviceObj)
+External(LNKC, DeviceObj)
+External(LNKD, DeviceObj)
+External(LNKE, DeviceObj)
+External(LNKF, DeviceObj)
+External(LNKG, DeviceObj)
+External(LNKH, DeviceObj)
 
 External(GSIA, DeviceObj)
 External(GSIB, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 64/74] pc: acpi: q35: move IQST() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 25 +++--
 hw/i386/q35-acpi-dsdt.dsl |  8 
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a4c2b43..2f0b9b7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1405,6 +1405,19 @@ static Aml *build_iqcr_method(bool is_piix4)
 return method;
 }
 
+/* _STA method - get status */
+static Aml *build_irq_status_method(void)
+{
+Aml *if_ctx;
+Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
+
+if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
+aml_append(if_ctx, aml_return(aml_int(0x09)));
+aml_append(method, if_ctx);
+aml_append(method, aml_return(aml_int(0x0B)));
+return method;
+}
+
 static void build_piix4_pci0_int(Aml *table)
 {
 Aml *dev;
@@ -1494,16 +1507,7 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(field, aml_named_field("PRQ3", 8));
 aml_append(sb_scope, field);
 
-/* _STA method - get status */
-method = aml_method("IQST", 1, AML_NOTSERIALIZED);
-{
-if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
-aml_append(if_ctx, aml_return(aml_int(0x09)));
-aml_append(method, if_ctx);
-aml_append(method, aml_return(aml_int(0x0B)));
-}
-aml_append(sb_scope, method);
-
+aml_append(sb_scope, build_irq_status_method());
 aml_append(sb_scope, build_iqcr_method(true));
 
 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
@@ -1550,6 +1554,7 @@ static void build_q35_pci0_int(Aml *table)
 {
 Aml *sb_scope = aml_scope("_SB");
 
+aml_append(sb_scope, build_irq_status_method());
 aml_append(sb_scope, build_iqcr_method(false));
 
 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 85b0a2c..ec8a48c 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -298,14 +298,6 @@ DefinitionBlock (
 PRQH,   8
 }
 
-Method(IQST, 1, NotSerialized) {
-// _STA method - get status
-If (And(0x80, Arg0)) {
-Return (0x09)
-}
-Return (0x0B)
-}
-
 External(LNKA, DeviceObj)
 External(LNKB, DeviceObj)
 External(LNKC, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 60/74] pc: acpi: piix4: acpi move PCI0 device to SSDT

[Igor Mammedov]

leave Scope(\_SB) definition in DSDT so that iasl
would be able to compile DSDT since we are still
need definition block for table.
After Q35 ASL is converted, DSDT templates will
be completly replaced by AML API generated tables.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 8 
 hw/i386/acpi-dsdt.dsl | 8 
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index ba941aa..4b1bd0b 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1619,6 +1619,14 @@ build_ssdt(GArray *table_data, GArray *linker,
 
 build_dbg_aml(ssdt);
 if (misc->is_piix4) {
+sb_scope = aml_scope("_SB");
+dev = aml_device("PCI0");
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
+aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+aml_append(sb_scope, dev);
+aml_append(ssdt, sb_scope);
+
 build_hpet_aml(ssdt);
 build_piix4_pm(ssdt);
 build_piix4_isa_bridge(ssdt);
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index a7769fc..82e4470 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -28,14 +28,6 @@ DefinitionBlock (
 0x1 // OEM Revision
 )
 {
-
 Scope(\_SB) {
-Device(PCI0) {
-Name(_HID, EisaId("PNP0A03"))
-Name(_ADR, 0x00)
-Name(_UID, 1)
-//#define PX13 S0B_
-//External(PX13, DeviceObj)
-}
 }
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 57/74] pc: acpi: piix4: move IQST() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 10 ++
 hw/i386/acpi-dsdt.dsl |  9 -
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2720262..cf98037 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1356,6 +1356,16 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(field, aml_named_field("PRQ3", 8));
 aml_append(sb_scope, field);
 
+/* _STA method - get status */
+method = aml_method("IQST", 1, AML_NOTSERIALIZED);
+{
+if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
+aml_append(if_ctx, aml_return(aml_int(0x09)));
+aml_append(method, if_ctx);
+aml_append(method, aml_return(aml_int(0x0B)));
+}
+aml_append(sb_scope, method);
+
 /* _CRS method - get current settings */
 method = aml_method("IQCR", 1, AML_SERIALIZED);
 {
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 1f58ec4..bc6bd45 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -132,15 +132,6 @@ DefinitionBlock (
 External(PRQ1, FieldUnitObj)
 External(PRQ2, FieldUnitObj)
 External(PRQ3, FieldUnitObj)
-
-Method(IQST, 1, NotSerialized) {
-// _STA method - get status
-If (And(0x80, Arg0)) {
-Return (0x09)
-}
-Return (0x0B)
-}
-
 External(LNKA, DeviceObj)
 External(LNKB, DeviceObj)
 External(LNKC, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 56/74] pc: acpi: piix4: move IQCR() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 20 
 hw/i386/acpi-dsdt.dsl | 11 ---
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f5e519b..2720262 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1344,6 +1344,7 @@ static void build_piix4_pci0_int(Aml *table)
 Aml *dev;
 Aml *crs;
 Aml *field;
+Aml *if_ctx;
 Aml *method;
 uint32_t irqs;
 Aml *sb_scope = aml_scope("_SB");
@@ -1355,6 +1356,25 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(field, aml_named_field("PRQ3", 8));
 aml_append(sb_scope, field);
 
+/* _CRS method - get current settings */
+method = aml_method("IQCR", 1, AML_SERIALIZED);
+{
+crs = aml_resource_template();
+irqs = 0;
+aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+  AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
+aml_append(method, aml_name_decl("PRR0", crs));
+
+aml_append(method,
+aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
+
+if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
+aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
+aml_append(method, if_ctx);
+aml_append(method, aml_return(aml_name("PRR0")));
+}
+aml_append(sb_scope, method);
+
 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index b74cffd..1f58ec4 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -140,17 +140,6 @@ DefinitionBlock (
 }
 Return (0x0B)
 }
-Method(IQCR, 1, Serialized) {
-// _CRS method - get current settings
-Name(PRR0, ResourceTemplate() {
-Interrupt(, Level, ActiveHigh, Shared) { 0 }
-})
-CreateDWordField(PRR0, 0x05, PRRI)
-If (LLess(Arg0, 0x80)) {
-Store(Arg0, PRRI)
-}
-Return (PRR0)
-}
 
 External(LNKA, DeviceObj)
 External(LNKB, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 54/74] pc: acpi: move remaining GPE handlers into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 26 +-
 hw/i386/acpi-dsdt.dsl | 40 
 hw/i386/q35-acpi-dsdt.dsl | 36 
 3 files changed, 25 insertions(+), 77 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 581ad98..99c0294 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1400,8 +1400,25 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
 
-scope =  aml_scope("\\_GPE");
+scope =  aml_scope("_GPE");
 {
+aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
+
+method = aml_method("_L00", 0, AML_NOTSERIALIZED);
+aml_append(scope, method);
+
+if (misc->is_piix4) {
+method = aml_method("_E01", 0, AML_NOTSERIALIZED);
+aml_append(method,
+aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0x));
+aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
+aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
+aml_append(scope, method);
+} else {
+method = aml_method("_L01", 0, AML_NOTSERIALIZED);
+aml_append(scope, method);
+}
+
 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
 aml_append(scope, method);
@@ -1409,6 +1426,13 @@ build_ssdt(GArray *table_data, GArray *linker,
 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
 aml_append(scope, method);
+
+for (i = 4; i <= 0xF; i++) {
+char *name = g_strdup_printf("_L0%X", i);
+method = aml_method(name, 0, AML_NOTSERIALIZED);
+aml_append(scope, method);
+g_free(name);
+}
 }
 aml_append(ssdt, scope);
 
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 11e2e61..c9b2725 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -197,44 +197,4 @@ DefinitionBlock (
 Method(_SRS, 1, NotSerialized) { }
 }
 }
-
-/
- * General purpose events
- /
-Scope(\_GPE) {
-Name(_HID, "ACPI0006")
-
-Method(_L00) {
-}
-Method(_E01) {
-// PCI hotplug event
-Acquire(\_SB.PCI0.BLCK, 0x)
-\_SB.PCI0.PCNT()
-Release(\_SB.PCI0.BLCK)
-}
-Method(_L04) {
-}
-Method(_L05) {
-}
-Method(_L06) {
-}
-Method(_L07) {
-}
-Method(_L08) {
-}
-Method(_L09) {
-}
-Method(_L0A) {
-}
-Method(_L0B) {
-}
-Method(_L0C) {
-}
-Method(_L0D) {
-}
-Method(_L0E) {
-}
-Method(_L0F) {
-}
-}
 }
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 4862ded..e157615 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -375,40 +375,4 @@ DefinitionBlock (
 define_gsi_link(GSIG, 0, 0x16)
 define_gsi_link(GSIH, 0, 0x17)
 }
-
-/
- * General purpose events
- /
-Scope(\_GPE) {
-Name(_HID, "ACPI0006")
-
-Method(_L00) {
-}
-Method(_L01) {
-}
-Method(_L04) {
-}
-Method(_L05) {
-}
-Method(_L06) {
-}
-Method(_L07) {
-}
-Method(_L08) {
-}
-Method(_L09) {
-}
-Method(_L0A) {
-}
-Method(_L0B) {
-}
-Method(_L0C) {
-}
-Method(_L0D) {
-}
-Method(_L0E) {
-}
-Method(_L0F) {
-}
-}
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 53/74] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT

[Igor Mammedov]

and also move PRQx fields declaration as it can't be
split out into separate patch since fields use
PCI0.ISA.P40C operation region and OperationRegion
must be declared in the same table as a Field that
uses it. If this condition is not statisfied Windows
will BSOD ans IASL (make check) will error out as well.

For the same reason pm is moved together with isa-bridge
as the later refernces P13C OperationRegion from pm device.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c| 77 +++--
 hw/i386/acpi-dsdt.dsl   | 52 +++---
 include/hw/acpi/aml-build.h |  1 +
 3 files changed, 81 insertions(+), 49 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 9bb10d6..581ad98 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -107,6 +107,7 @@ typedef struct AcpiPmInfo {
 } AcpiPmInfo;
 
 typedef struct AcpiMiscInfo {
+bool is_piix4;
 bool has_hpet;
 TPMVersion tpm_version;
 const unsigned char *dsdt_code;
@@ -129,10 +130,12 @@ static void acpi_get_dsdt(AcpiMiscInfo *info)
 assert(!!piix != !!lpc);
 
 if (piix) {
+info->is_piix4 = true;
 info->dsdt_code = AcpiDsdtAmlCode;
 info->dsdt_size = sizeof AcpiDsdtAmlCode;
 }
 if (lpc) {
+info->is_piix4 = false;
 info->dsdt_code = Q35AcpiDsdtAmlCode;
 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
 }
@@ -1300,6 +1303,68 @@ static void build_dbg_aml(Aml *table)
 aml_append(table, scope);
 }
 
+static void build_piix4_pci0_int(Aml *table)
+{
+Aml *field;
+Aml *sb_scope = aml_scope("_SB");
+
+field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("PRQ0", 8));
+aml_append(field, aml_named_field("PRQ1", 8));
+aml_append(field, aml_named_field("PRQ2", 8));
+aml_append(field, aml_named_field("PRQ3", 8));
+aml_append(sb_scope, field);
+
+aml_append(table, sb_scope);
+}
+
+static void build_piix4_pm(Aml *table)
+{
+Aml *dev;
+Aml *scope;
+
+scope =  aml_scope("_SB.PCI0");
+dev = aml_device("PX13");
+aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
+
+aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
+ 0x00, 0xff));
+aml_append(scope, dev);
+aml_append(table, scope);
+}
+
+static void build_piix4_isa_bridge(Aml *table)
+{
+Aml *dev;
+Aml *scope;
+Aml *field;
+
+scope =  aml_scope("_SB.PCI0");
+dev = aml_device("ISA");
+aml_append(dev, aml_name_decl("_ADR", aml_int(0x0001)));
+
+/* PIIX PCI to ISA irq remapping */
+aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
+ 0x60, 0x04));
+/* enable bits */
+field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+/* Offset(0x5f),, 7, */
+aml_append(field, aml_reserved_field(0x2f8));
+aml_append(field, aml_reserved_field(7));
+aml_append(field, aml_named_field("LPEN", 1));
+/* Offset(0x67),, 3, */
+aml_append(field, aml_reserved_field(0x38));
+aml_append(field, aml_reserved_field(3));
+aml_append(field, aml_named_field("CAEN", 1));
+aml_append(field, aml_reserved_field(3));
+aml_append(field, aml_named_field("CBEN", 1));
+aml_append(dev, field);
+aml_append(dev, aml_name_decl("FDEN", aml_int(1)));
+
+aml_append(scope, dev);
+aml_append(table, scope);
+}
+
 static void
 build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -1321,8 +1386,16 @@ build_ssdt(GArray *table_data, GArray *linker,
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
 build_dbg_aml(ssdt);
-build_hpet_aml(ssdt);
-build_isa_devices_aml(ssdt);
+if (misc->is_piix4) {
+build_hpet_aml(ssdt);
+build_piix4_pm(ssdt);
+build_piix4_isa_bridge(ssdt);
+build_isa_devices_aml(ssdt);
+build_piix4_pci0_int(ssdt);
+} else {
+build_hpet_aml(ssdt);
+build_isa_devices_aml(ssdt);
+}
 build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 6048cc7..11e2e61 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -40,47 +40,6 @@ DefinitionBlock (
 }
 
 /
- * PIIX4 PM
- /
-
-Scope(\_SB.PCI0) {
-Device(PX13) {
-Name(_ADR, 0x00010003)
-OperationRegion(P13C, PCI_Config, 0x00, 0xff)
-}
-}
-
-
-/
- * PIIX3 ISA bridge
- /
-
-Scope(\_SB.PCI0) {
-

[Qemu-devel] [PATCH 45/74] pc: acpi: move HPET from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c   | 53 ++
 hw/i386/acpi-dsdt-hpet.dsl | 48 -
 hw/i386/acpi-dsdt.dsl  |  2 --
 hw/i386/q35-acpi-dsdt.dsl  |  3 ---
 hw/timer/hpet.c|  2 +-
 include/hw/timer/hpet.h|  1 +
 6 files changed, 55 insertions(+), 54 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt-hpet.dsl

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 72883ad..62f932e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -50,6 +50,7 @@
 #include "hw/pci/pci_bus.h"
 #include "hw/pci-host/q35.h"
 #include "hw/i386/intel_iommu.h"
+#include "hw/timer/hpet.h"
 
 #include "hw/i386/q35-acpi-dsdt.hex"
 #include "hw/i386/acpi-dsdt.hex"
@@ -1119,6 +1120,57 @@ static void build_memory_devices(Aml *sb_scope, int 
nr_mem,
 aml_append(sb_scope, method);
 }
 
+static void build_hpet_aml(Aml *table)
+{
+Aml *crs;
+Aml *field;
+Aml *method;
+Aml *if_ctx;
+Aml *scope = aml_scope("_SB");
+Aml *dev = aml_device("HPET");
+Aml *a_zero = aml_int(0);
+Aml *a_id = aml_local(0);
+Aml *a_period = aml_local(1);
+
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
+aml_append(dev, aml_name_decl("_UID", a_zero));
+
+aml_append(dev, aml_operation_region("HPTM", AML_SYSTEM_MEMORY,
+ HPET_BASE, HPET_LEN));
+field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("VEND", 32));
+aml_append(field, aml_named_field("PRD", 32));
+aml_append(dev, field);
+
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_store(aml_name("VEND"), a_id));
+aml_append(method, aml_store(aml_name("PRD"), a_period));
+aml_append(method, aml_shiftright(a_id, aml_int(16), a_id));
+if_ctx = aml_if(aml_lor(
+aml_equal(a_id, a_zero),
+aml_equal(a_id, aml_int(0x;
+aml_append(if_ctx, aml_return(a_zero));
+aml_append(method, if_ctx);
+
+if_ctx = aml_if(aml_lor(
+aml_equal(a_period, a_zero),
+aml_lgreater(a_period, aml_int(1;
+aml_append(if_ctx, aml_return(a_zero));
+aml_append(method, if_ctx);
+
+aml_append(method, aml_return(aml_int(0x0F)));
+aml_append(dev, method);
+
+crs = aml_resource_template();
+aml_append(crs,
+aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)
+);
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+aml_append(scope, dev);
+aml_append(table, scope);
+}
+
 static void
 build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -1139,6 +1191,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
+build_hpet_aml(ssdt);
 build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
diff --git a/hw/i386/acpi-dsdt-hpet.dsl b/hw/i386/acpi-dsdt-hpet.dsl
deleted file mode 100644
index 44961b8..000
--- a/hw/i386/acpi-dsdt-hpet.dsl
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see .
- */
-
-/
- * HPET
- /
-
-Scope(\_SB) {
-Device(HPET) {
-Name(_HID, EISAID("PNP0103"))
-Name(_UID, 0)
-OperationRegion(HPTM, SystemMemory, 0xFED0, 0x400)
-Field(HPTM, DWordAcc, Lock, Preserve) {
-VEND, 32,
-PRD, 32,
-}
-Method(_STA, 0, NotSerialized) {
-Store(VEND, Local0)
-Store(PRD, Local1)
-ShiftRight(Local0, 16, Local0)
-If (LOr(LEqual(Local0, 0), LEqual(Local0, 0x))) {
-Return (0x0)
-}
-If (LOr(LEqual(Local1, 0), LGreater(Local1, 1))) {
-Return (0x0)
-}
-Return (0x0F)
-}
-Name(_CRS, ResourceTemplate() {
-Memory32Fixed(ReadOnly,
-0xFED0, // Address Base
-0x

[Qemu-devel] [PATCH 44/74] pc: acpi: factor out cpu hotplug code from build_ssdt() into separate function

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 174 ---
 1 file changed, 94 insertions(+), 80 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 7ca38f0..72883ad 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -765,6 +765,98 @@ static void crs_replace_with_free_ranges(GPtrArray *ranges,
 g_ptr_array_free(free_ranges, false);
 }
 
+static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
+AcpiCpuInfo *cpu, AcpiPmInfo *pm)
+{
+int i;
+Aml *dev;
+Aml *crs;
+Aml *pkg;
+Aml *field;
+Aml *ifctx;
+Aml *method;
+
+/* The current AML generator can cover the APIC ID range [0..255],
+ * inclusive, for VCPU hotplug. */
+QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
+g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
+
+/* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
+dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
+aml_append(dev,
+aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
+);
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+crs = aml_resource_template();
+aml_append(crs,
+aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
+   pm->cpu_hp_io_len)
+);
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(sb_scope, dev);
+/* declare CPU hotplug MMIO region and PRS field to access it */
+aml_append(sb_scope, aml_operation_region(
+"PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
+field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("PRS", 256));
+aml_append(sb_scope, field);
+
+/* build Processor object for each processor */
+for (i = 0; i < acpi_cpus; i++) {
+dev = aml_processor(i, 0, 0, "CP%.02X", i);
+
+method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
+aml_append(method,
+aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i;
+aml_append(dev, method);
+
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+aml_append(method,
+aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i;
+aml_append(dev, method);
+
+method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+aml_append(method,
+aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
+);
+aml_append(dev, method);
+
+aml_append(sb_scope, dev);
+}
+
+/* build this code:
+ *   Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
+ */
+/* Arg0 = Processor ID = APIC ID */
+method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
+for (i = 0; i < acpi_cpus; i++) {
+ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
+aml_append(ifctx,
+aml_notify(aml_name("CP%.02X", i), aml_arg(1))
+);
+aml_append(method, ifctx);
+}
+aml_append(sb_scope, method);
+
+/* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
+ *
+ * Note: The ability to create variable-sized packages was first
+ * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
+ * ith up to 255 elements. Windows guests up to win2k8 fail when
+ * VarPackageOp is used.
+ */
+pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
+ aml_varpackage(acpi_cpus);
+
+for (i = 0; i < acpi_cpus; i++) {
+uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
+aml_append(pkg, aml_int(b));
+}
+aml_append(sb_scope, aml_name_decl(CPU_CPU_ON_BITMAP, pkg));
+}
+
 static Aml *build_crs(PCIHostState *host,
   GPtrArray *io_ranges, GPtrArray *mem_ranges)
 {
@@ -1034,8 +1126,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 {
 MachineState *machine = MACHINE(qdev_get_machine());
 uint32_t nr_mem = machine->ram_slots;
-unsigned acpi_cpus = guest_info->apic_id_limit;
-Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
+Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field;
 PCIBus *bus = NULL;
 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
@@ -1044,10 +1135,6 @@ build_ssdt(GArray *table_data, GArray *linker,
 int i;
 
 ssdt = init_aml_allocator();
-/* The current AML generator can cover the APIC ID range [0..255],
- * inclusive, for VCPU hotplug. */
-QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
-g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
 
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(A

[Qemu-devel] [PATCH 73/74] pc: acpi: switch to AML API composed DSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 228 +--
 1 file changed, 112 insertions(+), 116 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4808a53..36c5a4e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -52,9 +52,6 @@
 #include "hw/i386/intel_iommu.h"
 #include "hw/timer/hpet.h"
 
-#include "hw/i386/q35-acpi-dsdt.hex"
-#include "hw/i386/acpi-dsdt.hex"
-
 #include "hw/acpi/aml-build.h"
 
 #include "qapi/qmp/qint.h"
@@ -123,24 +120,6 @@ typedef struct AcpiBuildPciBusHotplugState {
 bool pcihp_bridge_en;
 } AcpiBuildPciBusHotplugState;
 
-static void acpi_get_dsdt(AcpiMiscInfo *info)
-{
-Object *piix = piix4_pm_find();
-Object *lpc = ich9_lpc_find();
-assert(!!piix != !!lpc);
-
-if (piix) {
-info->is_piix4 = true;
-info->dsdt_code = AcpiDsdtAmlCode;
-info->dsdt_size = sizeof AcpiDsdtAmlCode;
-}
-if (lpc) {
-info->is_piix4 = false;
-info->dsdt_code = Q35AcpiDsdtAmlCode;
-info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
-}
-}
-
 static
 int acpi_add_cpu_info(Object *o, void *opaque)
 {
@@ -239,6 +218,17 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
 
 static void acpi_get_misc_info(AcpiMiscInfo *info)
 {
+Object *piix = piix4_pm_find();
+Object *lpc = ich9_lpc_find();
+assert(!!piix != !!lpc);
+
+if (piix) {
+info->is_piix4 = true;
+}
+if (lpc) {
+info->is_piix4 = false;
+}
+
 info->has_hpet = hpet_find();
 info->tpm_version = tpm_get_version();
 info->pvpanic_port = pvpanic_port();
@@ -1884,91 +1874,6 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
-build_dbg_aml(ssdt);
-if (misc->is_piix4) {
-sb_scope = aml_scope("_SB");
-dev = aml_device("PCI0");
-aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
-aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
-aml_append(dev, aml_name_decl("_UID", aml_int(1)));
-aml_append(sb_scope, dev);
-aml_append(ssdt, sb_scope);
-
-build_hpet_aml(ssdt);
-build_piix4_pm(ssdt);
-build_piix4_isa_bridge(ssdt);
-build_isa_devices_aml(ssdt);
-build_piix4_pci_hotplug(ssdt);
-build_piix4_pci0_int(ssdt);
-} else {
-sb_scope = aml_scope("_SB");
-aml_append(sb_scope,
-aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x0c));
-aml_append(sb_scope,
-aml_operation_region("PCSB", AML_SYSTEM_IO, 0xae0c, 0x01));
-field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
-aml_append(field, aml_named_field("PCIB", 8));
-aml_append(sb_scope, field);
-aml_append(ssdt, sb_scope);
-
-sb_scope = aml_scope("_SB");
-dev = aml_device("PCI0");
-aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
-aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
-aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
-aml_append(dev, aml_name_decl("_UID", aml_int(1)));
-aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
-aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
-aml_append(dev, build_q35_osc_method());
-aml_append(sb_scope, dev);
-aml_append(ssdt, sb_scope);
-
-build_hpet_aml(ssdt);
-build_q35_isa_bridge(ssdt);
-build_isa_devices_aml(ssdt);
-build_q35_pci0_int(ssdt);
-}
-
-build_cpu_hotplug_aml(ssdt);
-build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
- pm->mem_hp_io_len);
-
-scope =  aml_scope("_GPE");
-{
-aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
-
-method = aml_method("_L00", 0, AML_NOTSERIALIZED);
-aml_append(scope, method);
-
-if (misc->is_piix4) {
-method = aml_method("_E01", 0, AML_NOTSERIALIZED);
-aml_append(method,
-aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0x));
-aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
-aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
-aml_append(scope, method);
-} else {
-method = aml_method("_L01", 0, AML_NOTSERIALIZED);
-aml_append(scope, method);
-}
-
-method = aml_method("_E02", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
-aml_append(scope, method);
-
-method = aml_method("_E03", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
-aml_append(scope, method);
-
-for (i = 4; i <= 0xF; i++) {
-char *name = g_strdup_printf("_L0%X", i);
-method = aml_method(name, 0, AML_NOTSERIALIZED);
-   

[Qemu-devel] [PATCH 48/74] pc: acpi: move KBD device from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 20 ++--
 hw/i386/acpi-dsdt-isa.dsl | 12 
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 55bb466..c485530 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1171,12 +1171,21 @@ static void build_hpet_aml(Aml *table)
 aml_append(table, scope);
 }
 
-static Aml *build_eisa_device_aml(const char *name, const char *hid, Aml *crs)
+static Aml *
+build_eisa_device_aml(const char *name, const char *hid, Aml *crs,
+  bool have_sta)
 {
 Aml *dev;
+Aml *method;
+Aml *a_device_present = aml_int(0x0f);
 
 dev = aml_device("%s", name);
 aml_append(dev, aml_name_decl("_HID", aml_eisaid(hid)));
+if (have_sta) {
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_return(a_device_present));
+aml_append(dev, method);
+}
 aml_append(dev, aml_name_decl("_CRS", crs));
 
 return dev;
@@ -1192,7 +1201,14 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(crs, aml_irq_no_flags(8));
 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
 aml_append(scope, build_eisa_device_aml(
-"RTC", "PNP0B00", crs));
+"RTC", "PNP0B00", crs, false));
+
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
+aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
+aml_append(crs, aml_irq_no_flags(1));
+aml_append(scope, build_eisa_device_aml(
+"KBD", "PNP0303", crs, true));
 
 aml_append(table, scope);
 }
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index f2cbbea..f7a3c0a 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,18 +16,6 @@
 /* Common legacy ISA style devices. */
 Scope(\_SB.PCI0.ISA) {
 
-Device(KBD) {
-Name(_HID, EisaId("PNP0303"))
-Method(_STA, 0, NotSerialized) {
-Return (0x0f)
-}
-Name(_CRS, ResourceTemplate() {
-IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
-IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
-IRQNoFlags() { 1 }
-})
-}
-
 Device(MOU) {
 Name(_HID, EisaId("PNP0F13"))
 Method(_STA, 0, NotSerialized) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 43/74] pc: acpi: cpuhp: move \_GPE._E02() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/cpu_hotplug_acpi_table.c  |  2 +-
 hw/i386/acpi-build.c  | 12 +---
 hw/i386/acpi-dsdt-cpu-hotplug.dsl | 23 ---
 hw/i386/acpi-dsdt.dsl |  9 -
 hw/i386/q35-acpi-dsdt.dsl |  9 -
 include/hw/acpi/cpu_hotplug.h |  1 +
 include/hw/acpi/pc-hotplug.h  |  1 -
 7 files changed, 11 insertions(+), 46 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl

diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c
index 4ff444d..b56f3d3 100644
--- a/hw/acpi/cpu_hotplug_acpi_table.c
+++ b/hw/acpi/cpu_hotplug_acpi_table.c
@@ -67,7 +67,7 @@ void build_cpu_hotplug_aml(Aml *ctx)
 aml_append(method, aml_sleep(200));
 aml_append(sb_scope, method);
 
-method = aml_method(stringify(CPU_SCAN_METHOD), 0, AML_NOTSERIALIZED);
+method = aml_method(CPU_SCAN_METHOD, 0, AML_NOTSERIALIZED);
 {
 Aml *while_ctx, *if_ctx2;
 Aml *a_bus_check_evt = aml_int(1);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 39e7434..7ca38f0 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1057,9 +1057,15 @@ build_ssdt(GArray *table_data, GArray *linker,
  pm->mem_hp_io_len);
 
 scope =  aml_scope("\\_GPE");
-method = aml_method("_E03", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
-aml_append(scope, method);
+{
+method = aml_method("_E02", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
+aml_append(scope, method);
+
+method = aml_method("_E03", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
+aml_append(scope, method);
+}
 aml_append(ssdt, scope);
 
 /* Extra PCI root buses are implemented  only for i440fx */
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
deleted file mode 100644
index 88c472b..000
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see .
- */
-
-/
- * CPU hotplug
- /
-
-Scope(\_SB) {
-/* Objects filled in by run-time generated SSDT */
-External(CPU_SCAN_METHOD, MethodObj)
-}
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 6a0c656..007d3c9 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -247,11 +247,6 @@ DefinitionBlock (
 }
 }
 
-#include "hw/acpi/pc-hotplug.h"
-#define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE
-#include "acpi-dsdt-cpu-hotplug.dsl"
-
-
 /
  * General purpose events
  /
@@ -266,10 +261,6 @@ DefinitionBlock (
 \_SB.PCI0.PCNT()
 Release(\_SB.PCI0.BLCK)
 }
-Method(_E02) {
-// CPU hotplug event
-\_SB.CPU_SCAN_METHOD()
-}
 Method(_L04) {
 }
 Method(_L05) {
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 7211665..0511e26 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -384,11 +384,6 @@ DefinitionBlock (
 define_gsi_link(GSIH, 0, 0x17)
 }
 
-#include "hw/acpi/pc-hotplug.h"
-#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
-#include "acpi-dsdt-cpu-hotplug.dsl"
-
-
 /
  * General purpose events
  /
@@ -399,10 +394,6 @@ DefinitionBlock (
 }
 Method(_L01) {
 }
-Method(_E02) {
-// CPU hotplug event
-\_SB.CPU_SCAN_METHOD()
-}
 Method(_L04) {
 }
 Method(_L05) {
diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
index 1c5f630..bfa7e89 100644
--- a/include/hw/acpi/cpu_hotplug.h
+++ b/include/hw/acpi/cpu_hotplug.h
@@ -32,6 +32,7 @@ void acpi_cpu_hotplug_init(MemoryRegion *parent, Object 
*owner,
 #define CPU_CPU_ON_BITMAP "CPON"
 #define CPU_STATUS_METHOD "CPST"
 #define CPU_STATUS_MAP "PRS"
+#define CPU_SCAN_METH

[Qemu-devel] [PATCH 72/74] pc: acpi: q35: PCST, PCSB opregions and PCIB field into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 10 ++
 hw/i386/q35-acpi-dsdt.dsl |  5 -
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index b546516..4808a53 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1902,6 +1902,16 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_piix4_pci0_int(ssdt);
 } else {
 sb_scope = aml_scope("_SB");
+aml_append(sb_scope,
+aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x0c));
+aml_append(sb_scope,
+aml_operation_region("PCSB", AML_SYSTEM_IO, 0xae0c, 0x01));
+field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+aml_append(field, aml_named_field("PCIB", 8));
+aml_append(sb_scope, field);
+aml_append(ssdt, sb_scope);
+
+sb_scope = aml_scope("_SB");
 dev = aml_device("PCI0");
 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index f234f5c..3ecdb50 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -36,10 +36,5 @@ DefinitionBlock (
 {
 
 Scope(\_SB) {
-OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
-OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
-Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
-PCIB, 8,
-}
 }
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 70/74] pc: acpi: q35: move PCI0._OSC() method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 56 ++
 hw/i386/q35-acpi-dsdt.dsl | 57 ---
 2 files changed, 56 insertions(+), 57 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bd8d864..59041b3 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1815,6 +1815,54 @@ static void build_piix4_pci_hotplug(Aml *table)
 aml_append(table, scope);
 }
 
+static Aml *build_q35_osc_method(void)
+{
+Aml *if_ctx;
+Aml *if_ctx2;
+Aml *else_ctx;
+Aml *method;
+Aml *a_cwd1 = aml_name("CDW1");
+Aml *a_ctrl = aml_name("CTRL");
+
+method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
+aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+if_ctx = aml_if(aml_equal(
+aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
+aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+
+aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
+
+/*
+ * Always allow native PME, AER (no dependencies)
+ * Never allow SHPC (no SHPC controller in this system)
+ */
+aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
+
+if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1;
+/* Unknown revision */
+aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
+aml_append(if_ctx, if_ctx2);
+
+if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
+/* Capabilities bits were masked */
+aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
+aml_append(if_ctx, if_ctx2);
+
+/* Update DWORD3 in the buffer */
+aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
+aml_append(method, if_ctx);
+
+else_ctx = aml_else();
+/* Unrecognized UUID */
+aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
+aml_append(method, else_ctx);
+
+aml_append(method, aml_return(aml_arg(3)));
+return method;
+}
 
 static void
 build_ssdt(GArray *table_data, GArray *linker,
@@ -1853,6 +1901,14 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_piix4_pci_hotplug(ssdt);
 build_piix4_pci0_int(ssdt);
 } else {
+sb_scope = aml_scope("_SB");
+scope = aml_scope("PCI0");
+aml_append(scope, aml_name_decl("SUPP", aml_int(0)));
+aml_append(scope, aml_name_decl("CTRL", aml_int(0)));
+aml_append(scope, build_q35_osc_method());
+aml_append(sb_scope, scope);
+aml_append(ssdt, sb_scope);
+
 build_hpet_aml(ssdt);
 build_q35_isa_bridge(ssdt);
 build_isa_devices_aml(ssdt);
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 7c7aef7..b53663c 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -53,63 +53,6 @@ DefinitionBlock (
 Name(_CID, EisaId("PNP0A03"))
 Name(_ADR, 0x00)
 Name(_UID, 1)
-
-External(ISA, DeviceObj)
-
-// _OSC: based on sample of ACPI3.0b spec
-Name(SUPP, 0) // PCI _OSC Support Field value
-Name(CTRL, 0) // PCI _OSC Control Field value
-Method(_OSC, 4) {
-// Create DWORD-addressable fields from the Capabilities Buffer
-CreateDWordField(Arg3, 0, CDW1)
-
-// Check for proper UUID
-If (LEqual(Arg0, 
ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
-// Create DWORD-addressable fields from the Capabilities 
Buffer
-CreateDWordField(Arg3, 4, CDW2)
-CreateDWordField(Arg3, 8, CDW3)
-
-// Save Capabilities DWORD2 & 3
-Store(CDW2, SUPP)
-Store(CDW3, CTRL)
-
-// Always allow native PME, AER (no dependencies)
-// Never allow SHPC (no SHPC controller in this system)
-And(CTRL, 0x1D, CTRL)
-
-#if 0 // For now, nothing to do
-If (Not(And(CDW1, 1))) { // Query flag clear?
-// Disable GPEs for features granted native control.
-If (And(CTRL, 0x01)) { // Hot plug control granted?
-Store(0, HPCE) // clear the hot plug SCI enable bit
-Store(1, HPCS) // clear the hot plug SCI status bit
-}
-If (And(CTRL, 0x04)) { // PME control granted?
-Store(0, PMCE) // clear the PME SCI enable bit
-Store(1, PMCS) // clear the PME SCI status bit
-}
-If (And(CTRL, 0x10)) { // OS restoring PCI Express cap 
structure?
-

[Qemu-devel] [PATCH 61/74] pc: acpi: q35: move GSI links to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 47 +++
 hw/i386/q35-acpi-dsdt.dsl | 34 --
 2 files changed, 55 insertions(+), 26 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4b1bd0b..75a46c7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1339,6 +1339,31 @@ static Aml *build_link_dev(const char *name, uint8_t 
uid, Aml *reg)
 return dev;
  }
 
+static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
+{
+Aml *dev;
+Aml *crs;
+Aml *method;
+uint32_t irqs;
+
+dev = aml_device("%s", name);
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+crs = aml_resource_template();
+irqs = gsi;
+aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+  AML_SHARED, &irqs, 1));
+aml_append(dev, aml_name_decl("_PRS", crs));
+
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+aml_append(dev, method);
+
+return dev;
+}
+
 static Aml *build_prt_entry(const char *dev)
 {
 Aml *a_zero = aml_int(0);
@@ -1508,6 +1533,26 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(table, sb_scope);
 }
 
+static void build_q35_pci0_int(Aml *table)
+{
+Aml *sb_scope = aml_scope("_SB");
+
+/*
+ * TODO: UID probably shouldn't be the same for GSIx devices
+ * but that's how it was in original ASL so keep it for now
+ */
+aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
+aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
+aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
+aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
+aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
+aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
+aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
+aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
+
+aml_append(table, sb_scope);
+}
+
 static void build_piix4_pm(Aml *table)
 {
 Aml *dev;
@@ -1636,7 +1681,9 @@ build_ssdt(GArray *table_data, GArray *linker,
 } else {
 build_hpet_aml(ssdt);
 build_isa_devices_aml(ssdt);
+build_q35_pci0_int(ssdt);
 }
+
 build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index e157615..f2c154a 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -348,31 +348,13 @@ DefinitionBlock (
 define_link(LNKG, 6, PRQG)
 define_link(LNKH, 7, PRQH)
 
-#define define_gsi_link(link, uid, gsi) \
-Device(link) {  \
-Name(_HID, EISAID("PNP0C0F"))   \
-Name(_UID, uid) \
-Name(_PRS, ResourceTemplate() { \
-Interrupt(, Level, ActiveHigh, Shared) {\
-gsi \
-}   \
-})  \
-Name(_CRS, ResourceTemplate() { \
-Interrupt(, Level, ActiveHigh, Shared) {\
-gsi \
-}   \
-})  \
-Method(_SRS, 1, NotSerialized) {\
-}   \
-}
-
-define_gsi_link(GSIA, 0, 0x10)
-define_gsi_link(GSIB, 0, 0x11)
-define_gsi_link(GSIC, 0, 0x12)
-define_gsi_link(GSID, 0, 0x13)
-define_gsi_link(GSIE, 0, 0x14)
-define_gsi_link(GSIF, 0, 0x15)
-define_gsi_link(GSIG, 0, 0x16)
-define_gsi_link(GSIH, 0, 0x17)
+External(GSIA, DeviceObj)
+External(GSIB, DeviceObj)
+External(GSIC, DeviceObj)
+External(GSID, DeviceObj)
+External(GSIE, DeviceObj)
+External(GSIF, DeviceObj)
+External(GSIG, DeviceObj)
+External(GSIH, DeviceObj)
 }
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 42/74] pc: acpi: cpuhp: move PRSC() method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/cpu_hotplug_acpi_table.c  | 55 +++
 hw/i386/acpi-build.c  |  2 +-
 hw/i386/acpi-dsdt-cpu-hotplug.dsl | 39 +--
 hw/i386/acpi-dsdt.dsl |  2 +-
 hw/i386/q35-acpi-dsdt.dsl |  2 +-
 include/hw/acpi/aml-build.h   |  2 ++
 include/hw/acpi/cpu_hotplug.h |  1 +
 include/hw/acpi/pc-hotplug.h  |  1 +
 8 files changed, 63 insertions(+), 41 deletions(-)

diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c
index 8255937..4ff444d 100644
--- a/hw/acpi/cpu_hotplug_acpi_table.c
+++ b/hw/acpi/cpu_hotplug_acpi_table.c
@@ -26,6 +26,8 @@ void build_cpu_hotplug_aml(Aml *ctx)
 Aml *a_cpu_on = aml_local(0);
 Aml *a_madt = aml_local(1);
 Aml *a_cpus_map = aml_name(CPU_CPU_ON_BITMAP);
+Aml *a_zero = aml_int(0);
+Aml *a_one = aml_int(1);
 
 /*
  * _MAT method - creates an madt apic buffer
@@ -65,5 +67,58 @@ void build_cpu_hotplug_aml(Aml *ctx)
 aml_append(method, aml_sleep(200));
 aml_append(sb_scope, method);
 
+method = aml_method(stringify(CPU_SCAN_METHOD), 0, AML_NOTSERIALIZED);
+{
+Aml *while_ctx, *if_ctx2;
+Aml *a_bus_check_evt = aml_int(1);
+Aml *a_remove_evt = aml_int(3);
+Aml *a_status_map = aml_local(5); /* Local5 = active cpu bitmap */
+Aml *a_byte = aml_local(2); /* Local2 = last read byte from bitmap */
+Aml *a_idx = aml_local(0); /* Processor ID / APIC ID iterator */
+Aml *a_is_cpu_on = aml_local(1); /* Local1 = CPON flag for cpu */
+Aml *a_status = aml_local(3); /* Local3 = active state for cpu */
+
+aml_append(method, aml_store(aml_name(CPU_STATUS_MAP), a_status_map));
+aml_append(method, aml_store(a_zero, a_byte));
+aml_append(method, aml_store(a_zero, a_idx));
+
+/* While (a_idx < SizeOf(CPON)) */
+while_ctx = aml_while(aml_lless(a_idx, aml_sizeof(a_cpus_map)));
+aml_append(while_ctx, aml_store(
+aml_derefof(aml_index(a_cpus_map, a_idx)), a_is_cpu_on));
+
+if_ctx = aml_if(aml_and(a_idx, aml_int(0x07), NULL));
+/* Shift down previously read bitmap byte */
+aml_append(if_ctx, aml_shiftright(a_byte, a_one, a_byte));
+aml_append(while_ctx, if_ctx);
+
+else_ctx = aml_else();
+/* Read next byte from cpu bitmap */
+aml_append(else_ctx, aml_store(aml_derefof(
+aml_index(a_status_map, aml_shiftright(a_idx, aml_int(3), NULL))),
+a_byte));
+aml_append(while_ctx, else_ctx);
+
+aml_append(while_ctx,
+aml_store(aml_and(a_byte, a_one, NULL), a_status));
+if_ctx = aml_if(aml_lnot(aml_equal(a_is_cpu_on, a_status)));
+
+/* State change - update CPON with new state */
+aml_append(if_ctx, aml_store(a_status, aml_index(a_cpus_map, a_idx)));
+if_ctx2 = aml_if(aml_equal(a_status, a_one));
+aml_append(if_ctx2,
+aml_call2(AML_NOTIFY_METHOD, a_idx, a_bus_check_evt));
+aml_append(if_ctx, if_ctx2);
+else_ctx = aml_else();
+aml_append(else_ctx,
+aml_call2(AML_NOTIFY_METHOD, a_idx, a_remove_evt));
+aml_append(if_ctx, else_ctx);
+aml_append(while_ctx, if_ctx);
+
+aml_append(while_ctx, aml_increment(a_idx)); /* go to next cpu */
+aml_append(method, while_ctx);
+}
+aml_append(sb_scope, method);
+
 aml_append(ctx, sb_scope);
 }
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 3675928..39e7434 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1313,7 +1313,7 @@ build_ssdt(GArray *table_data, GArray *linker,
  *   Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
  */
 /* Arg0 = Processor ID = APIC ID */
-method = aml_method("NTFY", 2, AML_NOTSERIALIZED);
+method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
 for (i = 0; i < acpi_cpus; i++) {
 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
 aml_append(ifctx,
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index fb75eda..88c472b 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -19,42 +19,5 @@
 
 Scope(\_SB) {
 /* Objects filled in by run-time generated SSDT */
-External(NTFY, MethodObj)
-External(CPON, PkgObj)
-External(PRS, FieldUnitObj)
-
-/* Methods called by run-time generated SSDT Processor objects */
-Method(PRSC, 0) {
-// Local5 = active cpu bitmap
-Store(PRS, Local5)
-// Local2 = last read byte from bitmap
-Store(Zero, Local2)
-// Local0 = Processor ID / APIC ID iterator
-Store(Zero, Local0)
-While (LLess(Local0, SizeOf(CPON))) {
-// Local1 = CPON flag for this cpu
-Store(DerefOf(Index(CPON, Local0)), Local1)
-  

[Qemu-devel] [PATCH 71/74] pc: acpi: q35: move PCI0 device definition into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 14 +-
 hw/i386/q35-acpi-dsdt.dsl | 13 -
 2 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 59041b3..b546516 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1902,11 +1902,15 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_piix4_pci0_int(ssdt);
 } else {
 sb_scope = aml_scope("_SB");
-scope = aml_scope("PCI0");
-aml_append(scope, aml_name_decl("SUPP", aml_int(0)));
-aml_append(scope, aml_name_decl("CTRL", aml_int(0)));
-aml_append(scope, build_q35_osc_method());
-aml_append(sb_scope, scope);
+dev = aml_device("PCI0");
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
+aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
+aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
+aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
+aml_append(dev, build_q35_osc_method());
+aml_append(sb_scope, dev);
 aml_append(ssdt, sb_scope);
 
 build_hpet_aml(ssdt);
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index b53663c..f234f5c 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -42,17 +42,4 @@ DefinitionBlock (
 PCIB, 8,
 }
 }
-
-
-/
- * PCI Bus definition
- /
-Scope(\_SB) {
-Device(PCI0) {
-Name(_HID, EisaId("PNP0A08"))
-Name(_CID, EisaId("PNP0A03"))
-Name(_ADR, 0x00)
-Name(_UID, 1)
-}
-}
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 41/74] pc: acpi: cpuhp: move CPST() method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/cpu_hotplug_acpi_table.c  | 18 ++
 hw/i386/acpi-build.c  |  3 ++-
 hw/i386/acpi-dsdt-cpu-hotplug.dsl | 12 
 include/hw/acpi/cpu_hotplug.h |  1 +
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c
index fd1f85e..8255937 100644
--- a/hw/acpi/cpu_hotplug_acpi_table.c
+++ b/hw/acpi/cpu_hotplug_acpi_table.c
@@ -18,6 +18,8 @@
 void build_cpu_hotplug_aml(Aml *ctx)
 {
 Aml *method;
+Aml *if_ctx;
+Aml *else_ctx;
 Aml *sb_scope = aml_scope("_SB");
 uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0};
 Aml *a_cpu_id = aml_arg(0);
@@ -43,6 +45,22 @@ void build_cpu_hotplug_aml(Aml *ctx)
 aml_append(method, aml_return(a_madt));
 aml_append(sb_scope, method);
 
+/*
+ * _STA method - return ON status of cpu
+ * a_cpu_id = Arg0 = Processor ID = Local APIC ID
+ * a_cpu_on = Local0 = CPON flag for this cpu
+ */
+method = aml_method(CPU_STATUS_METHOD, 1, AML_NOTSERIALIZED);
+aml_append(method, aml_store(
+aml_derefof(aml_index(a_cpus_map, a_cpu_id)), a_cpu_on));
+if_ctx = aml_if(a_cpu_on);
+aml_append(if_ctx, aml_return(aml_int(0xF)));
+aml_append(method, if_ctx);
+else_ctx = aml_else();
+aml_append(else_ctx, aml_return(aml_int(0x0)));
+aml_append(method, else_ctx);
+aml_append(sb_scope, method);
+
 method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED);
 aml_append(method, aml_sleep(200));
 aml_append(sb_scope, method);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index eb1f90b..3675928 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1296,7 +1296,8 @@ build_ssdt(GArray *table_data, GArray *linker,
 aml_append(dev, method);
 
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_return(aml_call1("CPST", aml_int(i;
+aml_append(method,
+aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i;
 aml_append(dev, method);
 
 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index 9739191..fb75eda 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -24,18 +24,6 @@ Scope(\_SB) {
 External(PRS, FieldUnitObj)
 
 /* Methods called by run-time generated SSDT Processor objects */
-Method(CPST, 1, NotSerialized) {
-// _STA method - return ON status of cpu
-// Arg0 = Processor ID = Local APIC ID
-// Local0 = CPON flag for this cpu
-Store(DerefOf(Index(CPON, Arg0)), Local0)
-If (Local0) {
-Return (0xF)
-} Else {
-Return (0x0)
-}
-}
-
 Method(PRSC, 0) {
 // Local5 = active cpu bitmap
 Store(PRS, Local5)
diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
index d0b6d6b..1ae3b29 100644
--- a/include/hw/acpi/cpu_hotplug.h
+++ b/include/hw/acpi/cpu_hotplug.h
@@ -30,6 +30,7 @@ void acpi_cpu_hotplug_init(MemoryRegion *parent, Object 
*owner,
 #define CPU_EJECT_METHOD "CPEJ"
 #define CPU_MAT_METHOD "CPMA"
 #define CPU_CPU_ON_BITMAP "CPON"
+#define CPU_STATUS_METHOD "CPST"
 
 void build_cpu_hotplug_aml(Aml *ctx);
 #endif
-- 
1.8.3.1

[Qemu-devel] [PATCH 69/74] pc: acpi: q35: move _PIC() method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  8 
 hw/i386/q35-acpi-dsdt.dsl | 10 --
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index b54fb0a..bd8d864 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1615,6 +1615,14 @@ static void build_q35_pci0_int(Aml *table)
 Aml *sb_scope = aml_scope("_SB");
 Aml *pci0_scope = aml_scope("PCI0");
 
+/* Zero => PIC mode, One => APIC Mode */
+aml_append(table, aml_name_decl("PICF", aml_int(0)));
+method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
+{
+aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
+}
+aml_append(table, method);
+
 aml_append(pci0_scope,
 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
 aml_append(pci0_scope,
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 34485e7..7c7aef7 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -112,14 +112,4 @@ DefinitionBlock (
 }
 }
 }
-
-/
- * PCI IRQs
- /
-
-/* Zero => PIC mode, One => APIC Mode */
-Name(\PICF, Zero)
-Method(\_PIC, 1, NotSerialized) {
-Store(Arg0, \PICF)
-}
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 52/74] pc: acpi: move COM devices from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 27 ++--
 hw/i386/acpi-dsdt-isa.dsl | 52 ---
 hw/i386/acpi-dsdt.dsl |  3 ---
 hw/i386/q35-acpi-dsdt.dsl |  3 ---
 4 files changed, 21 insertions(+), 64 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt-isa.dsl

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bd03491..9bb10d6 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1172,7 +1172,7 @@ static void build_hpet_aml(Aml *table)
 }
 
 static Aml *
-build_eisa_device_aml(const char *name, const char *hid, Aml *crs,
+build_eisa_device_aml(const char *name, const char *hid, Aml *uid, Aml *crs,
   bool have_sta, const char *present_field)
 {
 Aml *dev;
@@ -1180,6 +1180,9 @@ build_eisa_device_aml(const char *name, const char *hid, 
Aml *crs,
 
 dev = aml_device("%s", name);
 aml_append(dev, aml_name_decl("_HID", aml_eisaid(hid)));
+if (uid) {
+aml_append(dev, aml_name_decl("_UID", uid));
+}
 if (have_sta) {
 Aml *if_ctx;
 Aml *else_ctx;
@@ -1218,19 +1221,19 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(crs, aml_irq_no_flags(8));
 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
 aml_append(scope, build_eisa_device_aml(
-"RTC", "PNP0B00", crs, false, NULL));
+"RTC", "PNP0B00", NULL, crs, false, NULL));
 
 crs = aml_resource_template();
 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
 aml_append(crs, aml_irq_no_flags(1));
 aml_append(scope, build_eisa_device_aml(
-"KBD", "PNP0303", crs, true, NULL));
+"KBD", "PNP0303", NULL, crs, true, NULL));
 
 crs = aml_resource_template();
 aml_append(crs, aml_irq_no_flags(12));
 aml_append(scope, build_eisa_device_aml(
-"MOU", "PNP0F13", crs, true, NULL));
+"MOU", "PNP0F13", NULL, crs, true, NULL));
 
 crs = aml_resource_template();
 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
@@ -1239,13 +1242,25 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(crs,
 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
 aml_append(scope, build_eisa_device_aml(
-"FDC0", "PNP0700", crs, true, "FDEN"));
+"FDC0", "PNP0700", NULL, crs, true, "FDEN"));
 
 crs = aml_resource_template();
 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
 aml_append(crs, aml_irq_no_flags(7));
 aml_append(scope, build_eisa_device_aml(
-"LPT", "PNP0400", crs, true, "LPEN"));
+"LPT", "PNP0400", NULL, crs, true, "LPEN"));
+
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x03F8, 0x03F8, 0x00, 0x08));
+aml_append(crs, aml_irq_no_flags(4));
+aml_append(scope, build_eisa_device_aml(
+"COM1", "PNP0501", aml_int(1), crs, true, "CAEN"));
+
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x02F8, 0x02F8, 0x00, 0x08));
+aml_append(crs, aml_irq_no_flags(3));
+aml_append(scope, build_eisa_device_aml(
+"COM2", "PNP0501", aml_int(2), crs, true, "CBEN"));
 
 aml_append(table, scope);
 }
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
deleted file mode 100644
index cc5e8f9..000
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see .
- */
-
-/* Common legacy ISA style devices. */
-Scope(\_SB.PCI0.ISA) {
-
-Device(COM1) {
-Name(_HID, EisaId("PNP0501"))
-Name(_UID, 0x01)
-Method(_STA, 0, NotSerialized) {
-Store(CAEN, Local0)
-If (LEqual(Local0, 0)) {
-Return (0x00)
-} Else {
-Return (0x0F)
-}
-}
-Name(_CRS, ResourceTemplate() {
-IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
-IRQNoFlags() { 4 }
-})
-}
-
-Device(COM2) {
-Name(_HID, EisaId("PNP0501"))
-Name(_UID, 0x02)
-Method(_STA, 0, NotSerialized) {
-Store(CBEN, Local0)
-If (LEqual(Local0, 0)) {
-Return (0x00)
-} Else {
-Return (0x0F)
-}
-

[Qemu-devel] [PATCH 37/74] pc: acpi: memhp: drop not needed stringify(MEMORY_foo) usage

[Igor Mammedov]

most of MEMORY_foo defines are not shared
with ASL anymore and are used only inside of
memory_hotplug_acpi_table.c, so move them
there and make them strings. As result we
can replace stringify(MEMORY_foo) with just
MEMORY_foo, which makes code a bit cleaner.

No AML change introduced by this patch.

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 53 +
 hw/i386/acpi-build.c| 52 ++--
 include/hw/acpi/memory_hotplug.h|  6 ++---
 include/hw/acpi/pc-hotplug.h| 42 ++---
 4 files changed, 74 insertions(+), 79 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index b913edc..3e943c3 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -35,14 +35,14 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 Aml *while_ctx;
 Aml *a_zero = aml_int(0);
 Aml *a_one = aml_int(1);
-Aml *a_slots_nr = aml_name(stringify(MEMORY_SLOTS_NUMBER));
+Aml *a_slots_nr = aml_name(MEMORY_SLOTS_NUMBER);
 
 /* scope for memory hotplug controller device node */
 pci_scope = aml_scope("_SB.PCI0");
-ctrl_dev = aml_device(stringify(MEMORY_HOTPLUG_DEVICE));
+ctrl_dev = aml_device(MEMORY_HOTPLUG_DEVICE);
 {
-Aml *a_ctrl_lock = aml_name(stringify(MEMORY_SLOT_LOCK));
-Aml *a_slot_selector = aml_name(stringify(MEMORY_SLOT_SLECTOR));
+Aml *a_ctrl_lock = aml_name(MEMORY_SLOT_LOCK);
+Aml *a_slot_selector = aml_name(MEMORY_SLOT_SLECTOR);
 Aml *a_ret_val = aml_local(0);
 Aml *a_slot_arg0 = aml_arg(0);
 
@@ -59,10 +59,9 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(method, aml_return(aml_int(0xB)));
 aml_append(ctrl_dev, method);
 
-aml_append(ctrl_dev, aml_mutex(stringify(MEMORY_SLOT_LOCK), 0));
+aml_append(ctrl_dev, aml_mutex(MEMORY_SLOT_LOCK, 0));
 
-method = aml_method(stringify(MEMORY_SLOT_SCAN_METHOD), 0,
-AML_NOTSERIALIZED);
+method = aml_method(MEMORY_SLOT_SCAN_METHOD, 0, AML_NOTSERIALIZED);
 {
 Aml *a_idx = aml_local(0);
 
@@ -75,13 +74,13 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 while_ctx = aml_while(
 aml_lless(a_idx, a_slots_nr));
 {
-Aml *a_ins_evt = aml_name(stringify(MEMORY_SLOT_INSERT_EVENT));
-Aml *a_rm_evt = aml_name(stringify(MEMORY_SLOT_REMOVE_EVENT));
+Aml *a_ins_evt = aml_name(MEMORY_SLOT_INSERT_EVENT);
+Aml *a_rm_evt = aml_name(MEMORY_SLOT_REMOVE_EVENT);
 
 aml_append(while_ctx, aml_store(a_idx, a_slot_selector));
 ifctx = aml_if(aml_equal(a_ins_evt, a_one));
 aml_append(ifctx,
-aml_call2(stringify(MEMORY_SLOT_NOTIFY_METHOD),
+aml_call2(MEMORY_SLOT_NOTIFY_METHOD,
   a_idx, a_one));
 aml_append(ifctx, aml_store(a_one, a_ins_evt));
 aml_append(while_ctx, ifctx);
@@ -89,7 +88,7 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 else_ctx = aml_else();
 ifctx = aml_if(aml_equal(a_rm_evt, a_one));
 aml_append(ifctx,
-aml_call2(stringify(MEMORY_SLOT_NOTIFY_METHOD),
+aml_call2(MEMORY_SLOT_NOTIFY_METHOD,
   a_idx, aml_int(3)));
 aml_append(ifctx, aml_store(a_one, a_rm_evt));
 aml_append(else_ctx, ifctx);
@@ -103,10 +102,9 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 }
 aml_append(ctrl_dev, method);
 
-method = aml_method(stringify(MEMORY_SLOT_STATUS_METHOD), 1,
-AML_NOTSERIALIZED);
+method = aml_method(MEMORY_SLOT_STATUS_METHOD, 1, AML_NOTSERIALIZED);
 {
-Aml *a_slot_enabled = aml_name(stringify(MEMORY_SLOT_ENABLED));
+Aml *a_slot_enabled = aml_name(MEMORY_SLOT_ENABLED);
 
 aml_append(method, aml_store(a_zero, a_ret_val));
 aml_append(method, aml_acquire(a_ctrl_lock, 0x));
@@ -122,8 +120,7 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 }
 aml_append(ctrl_dev, method);
 
-method = aml_method(stringify(MEMORY_SLOT_CRS_METHOD), 1,
-AML_SERIALIZED);
+method = aml_method(MEMORY_SLOT_CRS_METHOD, 1, AML_SERIALIZED);
 {
 Aml *a_mr64 = aml_name("MR64");
 Aml *a_mr32 = aml_name("MR32");
@@ -159,13 +156,13 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_create_dword_field(a_mr64, aml_int(26), "MAXH"));
 
 aml_append(method,
-aml_store(aml_name(stringify(MEMORY_SLOT_ADDR_HIGH)), a_minh));

[Qemu-devel] [PATCH 47/74] pc: acpi: move RTC device from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 27 +++
 hw/i386/acpi-dsdt-isa.dsl |  9 -
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4b7229d..55bb466 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1171,6 +1171,32 @@ static void build_hpet_aml(Aml *table)
 aml_append(table, scope);
 }
 
+static Aml *build_eisa_device_aml(const char *name, const char *hid, Aml *crs)
+{
+Aml *dev;
+
+dev = aml_device("%s", name);
+aml_append(dev, aml_name_decl("_HID", aml_eisaid(hid)));
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+return dev;
+}
+
+static void build_isa_devices_aml(Aml *table)
+{
+Aml *crs;
+Aml *scope = aml_scope("_SB.PCI0.ISA");
+
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
+aml_append(crs, aml_irq_no_flags(8));
+aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
+aml_append(scope, build_eisa_device_aml(
+"RTC", "PNP0B00", crs));
+
+aml_append(table, scope);
+}
+
 static void build_dbg_aml(Aml *table)
 {
 Aml *field;
@@ -1228,6 +1254,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 
 build_dbg_aml(ssdt);
 build_hpet_aml(ssdt);
+build_isa_devices_aml(ssdt);
 build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index 89caa16..f2cbbea 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,15 +16,6 @@
 /* Common legacy ISA style devices. */
 Scope(\_SB.PCI0.ISA) {
 
-Device(RTC) {
-Name(_HID, EisaId("PNP0B00"))
-Name(_CRS, ResourceTemplate() {
-IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
-IRQNoFlags() { 8 }
-IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
-})
-}
-
 Device(KBD) {
 Name(_HID, EisaId("PNP0303"))
 Method(_STA, 0, NotSerialized) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 68/74] pc: acpi: q35: move PRTP routing table into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  2 ++
 hw/i386/q35-acpi-dsdt.dsl | 79 ---
 2 files changed, 2 insertions(+), 79 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0008d9f..b54fb0a 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1616,6 +1616,8 @@ static void build_q35_pci0_int(Aml *table)
 Aml *pci0_scope = aml_scope("PCI0");
 
 aml_append(pci0_scope,
+aml_name_decl("PRTP", build_q35_routing_table("LNK")));
+aml_append(pci0_scope,
 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
 
 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index a3073ad..34485e7 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -122,83 +122,4 @@ DefinitionBlock (
 Method(\_PIC, 1, NotSerialized) {
 Store(Arg0, \PICF)
 }
-
-Scope(\_SB) {
-Scope(PCI0) {
-#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
-Package() { nr##, 0, lnk0, 0 },   \
-Package() { nr##, 1, lnk1, 0 },   \
-Package() { nr##, 2, lnk2, 0 },   \
-Package() { nr##, 3, lnk3, 0 }
-
-#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
-#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
-
-#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
-#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
-#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
-#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
-
-Name(PRTP, package() {
-prt_slot_lnkE(0x),
-prt_slot_lnkF(0x0001),
-prt_slot_lnkG(0x0002),
-prt_slot_lnkH(0x0003),
-prt_slot_lnkE(0x0004),
-prt_slot_lnkF(0x0005),
-prt_slot_lnkG(0x0006),
-prt_slot_lnkH(0x0007),
-prt_slot_lnkE(0x0008),
-prt_slot_lnkF(0x0009),
-prt_slot_lnkG(0x000a),
-prt_slot_lnkH(0x000b),
-prt_slot_lnkE(0x000c),
-prt_slot_lnkF(0x000d),
-prt_slot_lnkG(0x000e),
-prt_slot_lnkH(0x000f),
-prt_slot_lnkE(0x0010),
-prt_slot_lnkF(0x0011),
-prt_slot_lnkG(0x0012),
-prt_slot_lnkH(0x0013),
-prt_slot_lnkE(0x0014),
-prt_slot_lnkF(0x0015),
-prt_slot_lnkG(0x0016),
-prt_slot_lnkH(0x0017),
-prt_slot_lnkE(0x0018),
-
-/* INTA -> PIRQA for slot 25 - 31
-   see the default value of DIR */
-prt_slot_lnkA(0x0019),
-prt_slot_lnkA(0x001a),
-prt_slot_lnkA(0x001b),
-prt_slot_lnkA(0x001c),
-prt_slot_lnkA(0x001d),
-
-/* PCIe->PCI bridge. use PIRQ[E-H] */
-prt_slot_lnkE(0x001e),
-
-prt_slot_lnkA(0x001f)
-})
-}
-
-External(LNKA, DeviceObj)
-External(LNKB, DeviceObj)
-External(LNKC, DeviceObj)
-External(LNKD, DeviceObj)
-External(LNKE, DeviceObj)
-External(LNKF, DeviceObj)
-External(LNKG, DeviceObj)
-External(LNKH, DeviceObj)
-
-External(GSIA, DeviceObj)
-External(GSIB, DeviceObj)
-External(GSIC, DeviceObj)
-External(GSID, DeviceObj)
-External(GSIE, DeviceObj)
-External(GSIF, DeviceObj)
-External(GSIG, DeviceObj)
-External(GSIH, DeviceObj)
-}
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 36/74] pc: acpi: memhp: move \_GPE._E03 into SSDT

[Igor Mammedov]

in addition remove no longer needed acpi-dsdt-mem-hotplug.dsl.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  6 ++
 hw/i386/acpi-dsdt-mem-hotplug.dsl | 16 
 hw/i386/acpi-dsdt.dsl |  5 -
 hw/i386/q35-acpi-dsdt.dsl |  5 -
 include/hw/acpi/memory_hotplug.h  |  5 +
 include/hw/acpi/pc-hotplug.h  |  2 --
 6 files changed, 11 insertions(+), 28 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt-mem-hotplug.dsl

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 765fccd..94371f7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1055,6 +1055,12 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
 
+scope =  aml_scope("\\_GPE");
+method = aml_method("_E03", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
+aml_append(scope, method);
+aml_append(ssdt, scope);
+
 /* Extra PCI root buses are implemented  only for i440fx */
 bus = find_i440fx();
 if (bus) {
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
deleted file mode 100644
index 20c5ec1..000
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see .
- */
-
-External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD, 
MethodObj)
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 8dba096..9cf1b88 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -250,7 +250,6 @@ DefinitionBlock (
 #include "hw/acpi/pc-hotplug.h"
 #define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE
 #include "acpi-dsdt-cpu-hotplug.dsl"
-#include "acpi-dsdt-mem-hotplug.dsl"
 
 
 /
@@ -271,10 +270,6 @@ DefinitionBlock (
 // CPU hotplug event
 \_SB.PRSC()
 }
-Method(_E03) {
-// Memory hotplug event
-\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD()
-}
 Method(_L04) {
 }
 Method(_L05) {
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 7be7b37..f950f39 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -387,7 +387,6 @@ DefinitionBlock (
 #include "hw/acpi/pc-hotplug.h"
 #define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
 #include "acpi-dsdt-cpu-hotplug.dsl"
-#include "acpi-dsdt-mem-hotplug.dsl"
 
 
 /
@@ -404,10 +403,6 @@ DefinitionBlock (
 // CPU hotplug event
 \_SB.PRSC()
 }
-Method(_E03) {
-// Memory hotplug event
-\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD()
-}
 Method(_L04) {
 }
 Method(_L05) {
diff --git a/include/hw/acpi/memory_hotplug.h b/include/hw/acpi/memory_hotplug.h
index b6e9f50..de164f2 100644
--- a/include/hw/acpi/memory_hotplug.h
+++ b/include/hw/acpi/memory_hotplug.h
@@ -47,6 +47,11 @@ extern const VMStateDescription vmstate_memory_hotplug;
 
 void acpi_memory_ospm_status(MemHotplugState *mem_st, ACPIOSTInfoList ***list);
 
+#define MEMORY_HOTPLUG_DEVICEMHPD
+#define MEMORY_SLOT_SCAN_METHOD  MSCN
+#define MEMORY_HOTPLUG_HANDLER_PATH "\\_SB.PCI0." \
+ stringify(MEMORY_HOTPLUG_DEVICE) "." stringify(MEMORY_SLOT_SCAN_METHOD)
+
 void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
   uint16_t io_base, uint16_t io_len);
 #endif
diff --git a/include/hw/acpi/pc-hotplug.h b/include/hw/acpi/pc-hotplug.h
index 77b1569..e5bb321 100644
--- a/include/hw/acpi/pc-hotplug.h
+++ b/include/hw/acpi/pc-hotplug.h
@@ -32,7 +32,6 @@
 #define ACPI_MEMORY_HOTPLUG_IO_LEN 24
 #define ACPI_MEMORY_HOTPLUG_BASE 0x0a00
 
-#define MEMORY_HOTPLUG_DEVICEMHPD
 #define MEMORY_SLOTS_NUMBER  MDNR
 #define MEMORY_HOTPLUG_IO_REGION HPMR
 #define MEMORY_SLOT_ADDR_LOW MRBL
@@ -54,6 +53,5 @@
 #define MEMORY_SLOT_PROXIMITY_METHOD MPXM
 #define MEMORY_SLOT_EJECT_METHOD MEJ0
 #define MEMORY_SLOT_NOTIFY_METHODMTFY
-#define MEMORY_SLOT_SCAN_METHOD  MSCN
 
 #endif
-- 
1.8.3.1

[Qemu-devel] [PATCH 58/74] pc: acpi: piix4: move PCI0._PRT() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 83 +++
 hw/i386/acpi-dsdt.dsl | 60 -
 2 files changed, 83 insertions(+), 60 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index cf98037..f0966b8 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1339,6 +1339,17 @@ static Aml *build_link_dev(const char *name, uint8_t 
uid, Aml *reg)
 return dev;
  }
 
+static Aml *build_prt_entry(const char *dev)
+{
+Aml *a_zero = aml_int(0);
+Aml *pkg = aml_package(4);
+aml_append(pkg, a_zero);
+aml_append(pkg, a_zero);
+aml_append(pkg, aml_name("%s", dev));
+aml_append(pkg, a_zero);
+return pkg;
+}
+
 static void build_piix4_pci0_int(Aml *table)
 {
 Aml *dev;
@@ -1348,6 +1359,78 @@ static void build_piix4_pci0_int(Aml *table)
 Aml *method;
 uint32_t irqs;
 Aml *sb_scope = aml_scope("_SB");
+Aml *pci0_scope = aml_scope("PCI0");
+
+method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
+{
+Aml *w_ctx;
+Aml *if_ctx2;
+Aml *else_ctx2;
+Aml *a_zero = aml_int(0);
+Aml *a_prt = aml_local(0);
+Aml *a_pin = aml_local(1);
+Aml *a_lnk = aml_local(3);
+Aml *a_slot = aml_local(2);
+Aml *a_prt_ent = aml_local(4);
+
+aml_append(method, aml_store(aml_package(128), a_prt));
+aml_append(method, aml_store(a_zero, a_pin));
+w_ctx = aml_while(aml_lless(a_pin, aml_int(128)));
+
+/* slot = pin >> 2 */
+aml_append(w_ctx,
+aml_store(aml_shiftright(a_pin, aml_int(2), NULL), a_slot));
+
+/* lnk = (slot + pin) & 3 */
+aml_append(w_ctx,
+aml_store(aml_and(aml_add(a_pin, a_slot, NULL), aml_int(3), NULL),
+  a_lnk));
+
+if_ctx = aml_if(aml_equal(a_lnk, a_zero));
+aml_append(if_ctx, aml_store(build_prt_entry("LNKD"), a_prt_ent));
+aml_append(w_ctx, if_ctx);
+
+if_ctx = aml_if(aml_equal(a_lnk, aml_int(1)));
+/* device 1 is the power-management device, needs SCI */
+if_ctx2 = aml_if(aml_equal(a_pin, aml_int(4)));
+aml_append(if_ctx2, aml_store(build_prt_entry("LNKS"), a_prt_ent));
+aml_append(if_ctx, if_ctx2);
+else_ctx2 = aml_else();
+aml_append(else_ctx2, aml_store(build_prt_entry("LNKA"), a_prt_ent));
+aml_append(if_ctx, else_ctx2);
+aml_append(w_ctx, if_ctx);
+
+if_ctx = aml_if(aml_equal(a_lnk, aml_int(2)));
+aml_append(if_ctx, aml_store(build_prt_entry("LNKB"), a_prt_ent));
+aml_append(w_ctx, if_ctx);
+
+if_ctx = aml_if(aml_equal(a_lnk, aml_int(3)));
+aml_append(if_ctx, aml_store(build_prt_entry("LNKC"), a_prt_ent));
+aml_append(w_ctx, if_ctx);
+
+/*
+ * Complete the interrupt routing entry:
+ *Package(4) { 0x[slot], [pin], [link], 0) }
+ */
+aml_append(w_ctx,
+aml_store(
+aml_or(aml_shiftleft(a_slot, aml_int(16)),
+   aml_int(0x), NULL),
+aml_index(a_prt_ent, a_zero)
+)
+);
+aml_append(w_ctx,
+aml_store(aml_and(a_pin, aml_int(3), NULL),
+  aml_index(a_prt_ent, aml_int(1;
+aml_append(w_ctx, aml_store(a_prt_ent, aml_index(a_prt, a_pin)));
+
+aml_append(w_ctx, aml_increment(a_pin));
+aml_append(method, w_ctx);
+
+aml_append(method, aml_return(aml_local(0)));
+}
+aml_append(pci0_scope, method);
+aml_append(sb_scope, pci0_scope);
 
 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 aml_append(field, aml_named_field("PRQ0", 8));
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index bc6bd45..5d741dd 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -78,64 +78,4 @@ DefinitionBlock (
 /* Hotplug notification method supplied by SSDT */
 External(\_SB.PCI0.PCNT, MethodObj)
 }
-
-
-/
- * PCI IRQs
- /
-
-Scope(\_SB) {
-Scope(PCI0) {
-Method (_PRT, 0) {
-Store(Package(128) {}, Local0)
-Store(Zero, Local1)
-While(LLess(Local1, 128)) {
-// slot = pin >> 2
-Store(ShiftRight(Local1, 2), Local2)
-
-// lnk = (slot + pin) & 3
-Store(And(Add(Local1, Local2), 3), Local3)
-If (LEqual(Local3, 0)) {
-Store(Package(4) { Zero, Zero, LNKD, Zero }, Local4)
-}
-If (LEqual(Local3, 1)) {
-// device 1 is the power-management device, needs SCI
-If (LEqual(Local1, 4)) {
-   

[Qemu-devel] [PATCH 40/74] pc: acpi: cpuhp: move CPMA() method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/cpu_hotplug_acpi_table.c  | 23 +++
 hw/i386/acpi-build.c  |  5 +++--
 hw/i386/acpi-dsdt-cpu-hotplug.dsl | 13 -
 include/hw/acpi/cpu_hotplug.h |  2 ++
 4 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c
index 422e57b..fd1f85e 100644
--- a/hw/acpi/cpu_hotplug_acpi_table.c
+++ b/hw/acpi/cpu_hotplug_acpi_table.c
@@ -19,6 +19,29 @@ void build_cpu_hotplug_aml(Aml *ctx)
 {
 Aml *method;
 Aml *sb_scope = aml_scope("_SB");
+uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0};
+Aml *a_cpu_id = aml_arg(0);
+Aml *a_cpu_on = aml_local(0);
+Aml *a_madt = aml_local(1);
+Aml *a_cpus_map = aml_name(CPU_CPU_ON_BITMAP);
+
+/*
+ * _MAT method - creates an madt apic buffer
+ * a_cpu_id = Arg0 = Processor ID = Local APIC ID
+ * a_cpu_on = Local0 = CPON flag for this cpu
+ * a_madt = Local1 = Buffer (in madt apic form) to return
+ */
+method = aml_method(CPU_MAT_METHOD, 1, AML_NOTSERIALIZED);
+aml_append(method, aml_store(
+aml_derefof(aml_index(a_cpus_map, a_cpu_id)), a_cpu_on));
+aml_append(method, aml_store(
+aml_buffer(sizeof(madt_tmpl), madt_tmpl), a_madt));
+/* Update the processor id, lapic id, and enable/disable status */
+aml_append(method, aml_store(a_cpu_id, aml_index(a_madt, aml_int(2;
+aml_append(method, aml_store(a_cpu_id, aml_index(a_madt, aml_int(3;
+aml_append(method, aml_store(a_cpu_on, aml_index(a_madt, aml_int(4;
+aml_append(method, aml_return(a_madt));
+aml_append(sb_scope, method);
 
 method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED);
 aml_append(method, aml_sleep(200));
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 9f8f769..eb1f90b 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1291,7 +1291,8 @@ build_ssdt(GArray *table_data, GArray *linker,
 dev = aml_processor(i, 0, 0, "CP%.02X", i);
 
 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_return(aml_call1("CPMA", aml_int(i;
+aml_append(method,
+aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i;
 aml_append(dev, method);
 
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
@@ -1335,7 +1336,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
 aml_append(pkg, aml_int(b));
 }
-aml_append(sb_scope, aml_name_decl("CPON", pkg));
+aml_append(sb_scope, aml_name_decl(CPU_CPU_ON_BITMAP, pkg));
 
 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index 18331be..9739191 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -24,19 +24,6 @@ Scope(\_SB) {
 External(PRS, FieldUnitObj)
 
 /* Methods called by run-time generated SSDT Processor objects */
-Method(CPMA, 1, NotSerialized) {
-// _MAT method - create an madt apic buffer
-// Arg0 = Processor ID = Local APIC ID
-// Local0 = CPON flag for this cpu
-Store(DerefOf(Index(CPON, Arg0)), Local0)
-// Local1 = Buffer (in madt apic form) to return
-Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-// Update the processor id, lapic id, and enable/disable status
-Store(Arg0, Index(Local1, 2))
-Store(Arg0, Index(Local1, 3))
-Store(Local0, Index(Local1, 4))
-Return (Local1)
-}
 Method(CPST, 1, NotSerialized) {
 // _STA method - return ON status of cpu
 // Arg0 = Processor ID = Local APIC ID
diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
index 87504be..d0b6d6b 100644
--- a/include/hw/acpi/cpu_hotplug.h
+++ b/include/hw/acpi/cpu_hotplug.h
@@ -28,6 +28,8 @@ void acpi_cpu_hotplug_init(MemoryRegion *parent, Object 
*owner,
AcpiCpuHotplug *gpe_cpu, uint16_t base);
 
 #define CPU_EJECT_METHOD "CPEJ"
+#define CPU_MAT_METHOD "CPMA"
+#define CPU_CPU_ON_BITMAP "CPON"
 
 void build_cpu_hotplug_aml(Aml *ctx);
 #endif
-- 
1.8.3.1

[Qemu-devel] [PATCH 63/74] pc: acpi: q35: move IQCR() into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 51 ++-
 hw/i386/q35-acpi-dsdt.dsl |  9 -
 2 files changed, 33 insertions(+), 27 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 51a07eb..a4c2b43 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1375,6 +1375,36 @@ static Aml *build_prt_entry(const char *dev)
 return pkg;
 }
 
+/* _CRS method - get current settings */
+static Aml *build_iqcr_method(bool is_piix4)
+{
+Aml *if_ctx;
+uint32_t irqs;
+Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
+Aml *crs = aml_resource_template();
+
+irqs = 0;
+aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+  AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
+aml_append(method, aml_name_decl("PRR0", crs));
+
+aml_append(method,
+aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
+
+if (is_piix4) {
+if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
+aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
+aml_append(method, if_ctx);
+} else {
+aml_append(method,
+aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
+  aml_name("PRRI")));
+}
+
+aml_append(method, aml_return(aml_name("PRR0")));
+return method;
+}
+
 static void build_piix4_pci0_int(Aml *table)
 {
 Aml *dev;
@@ -1474,24 +1504,7 @@ static void build_piix4_pci0_int(Aml *table)
 }
 aml_append(sb_scope, method);
 
-/* _CRS method - get current settings */
-method = aml_method("IQCR", 1, AML_SERIALIZED);
-{
-crs = aml_resource_template();
-irqs = 0;
-aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
-  AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
-aml_append(method, aml_name_decl("PRR0", crs));
-
-aml_append(method,
-aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
-
-if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
-aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
-aml_append(method, if_ctx);
-aml_append(method, aml_return(aml_name("PRR0")));
-}
-aml_append(sb_scope, method);
+aml_append(sb_scope, build_iqcr_method(true));
 
 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
@@ -1537,6 +1550,8 @@ static void build_q35_pci0_int(Aml *table)
 {
 Aml *sb_scope = aml_scope("_SB");
 
+aml_append(sb_scope, build_iqcr_method(false));
+
 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 2da3515..85b0a2c 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -305,15 +305,6 @@ DefinitionBlock (
 }
 Return (0x0B)
 }
-Method(IQCR, 1, Serialized) {
-// _CRS method - get current settings
-Name(PRR0, ResourceTemplate() {
-Interrupt(, Level, ActiveHigh, Shared) { 0 }
-})
-CreateDWordField(PRR0, 0x05, PRRI)
-Store(And(Arg0, 0x0F), PRRI)
-Return (PRR0)
-}
 
 External(LNKA, DeviceObj)
 External(LNKB, DeviceObj)
-- 
1.8.3.1

[Qemu-devel] [PATCH 33/74] pc: acpi: memhp: move MHPD.MCRS method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 85 +
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 72 ---
 2 files changed, 85 insertions(+), 72 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index 9795a9f..622cd5c 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -118,6 +118,91 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 }
 aml_append(ctrl_dev, method);
 
+method = aml_method(stringify(MEMORY_SLOT_CRS_METHOD), 1,
+AML_SERIALIZED);
+{
+Aml *a_mr64 = aml_name("MR64");
+Aml *a_mr32 = aml_name("MR32");
+Aml *a_crs_tmpl = aml_resource_template();
+Aml *a_minl = aml_name("MINL");
+Aml *a_minh = aml_name("MINH");
+Aml *a_maxl =  aml_name("MAXL");
+Aml *a_maxh =  aml_name("MAXH");
+Aml *a_lenl = aml_name("LENL");
+Aml *a_lenh = aml_name("LENH");
+
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+aml_append(method, aml_store(aml_to_integer(a_slot_arg0),
+ a_slot_selector));
+
+aml_append(a_crs_tmpl,
+aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
+ 0, 0x0, 0xFFFE, 0,
+ 0x));
+aml_append(method, aml_name_decl("MR64", a_crs_tmpl));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(14), "MINL"));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(18), "MINH"));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(38), "LENL"));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(42), "LENH"));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(22), "MAXL"));
+aml_append(method,
+aml_create_dword_field(a_mr64, aml_int(26), "MAXH"));
+
+aml_append(method,
+aml_store(aml_name(stringify(MEMORY_SLOT_ADDR_HIGH)), a_minh));
+aml_append(method,
+aml_store(aml_name(stringify(MEMORY_SLOT_ADDR_LOW)), a_minl));
+aml_append(method,
+aml_store(aml_name(stringify(MEMORY_SLOT_SIZE_HIGH)), a_lenh));
+aml_append(method,
+aml_store(aml_name(stringify(MEMORY_SLOT_SIZE_LOW)), a_lenl));
+
+/* 64-bit math: MAX = MIN + LEN - 1 */
+aml_append(method, aml_add(a_minl, a_lenl, a_maxl));
+aml_append(method, aml_add(a_minh, a_lenh, a_maxh));
+ifctx = aml_if(aml_lless(a_maxl, a_minl));
+aml_append(ifctx, aml_add(a_maxh, a_one, a_maxh));
+aml_append(method, ifctx);
+ifctx = aml_if(aml_lless(a_maxl, a_one));
+aml_append(ifctx, aml_subtract(a_maxh, a_one, a_maxh));
+aml_append(method, ifctx);
+aml_append(method, aml_subtract(a_maxl, a_one, a_maxl));
+
+/* return 32-bit _CRS if addr/size is in low mem */
+/* TODO: remove it since all hotplugged DIMMs are in high mem */
+ifctx = aml_if(aml_equal(a_maxh, a_zero));
+a_crs_tmpl = aml_resource_template();
+aml_append(a_crs_tmpl,
+aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
+ 0, 0x0, 0xFFFE, 0,
+ 0x));
+aml_append(ifctx, aml_name_decl("MR32", a_crs_tmpl));
+aml_append(ifctx,
+aml_create_dword_field(a_mr32, aml_int(10), "MIN"));
+aml_append(ifctx,
+aml_create_dword_field(a_mr32, aml_int(14), "MAX"));
+aml_append(ifctx,
+aml_create_dword_field(a_mr32, aml_int(22), "LEN"));
+aml_append(ifctx, aml_store(a_minl, aml_name("MIN")));
+aml_append(ifctx, aml_store(a_maxl, aml_name("MAX")));
+aml_append(ifctx, aml_store(a_lenl, aml_name("LEN")));
+
+aml_append(ifctx, aml_release(a_ctrl_lock));
+aml_append(ifctx, aml_return(a_mr32));
+aml_append(method, ifctx);
+
+aml_append(method, aml_release(a_ctrl_lock));
+aml_append(method, aml_return(a_mr64));
+}
+aml_append(ctrl_dev, method);
+
 method = aml_method(stringify(MEMORY_SLOT_PROXIMITY_METHOD), 1,
 AML_NOTSERIALIZED);
 {
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 87d8d66.

[Qemu-devel] [PATCH 35/74] pc: acpi: factor out memhp code from build_ssdt() into separate function

[Igor Mammedov]

before consolidating memhp code in memory_hotplug_acpi_table.c
and for simplifying review, first factor out memhp code into
new function build_memory_devices() in i386/acpi-build.c

Signed-off-by: Igor Mammedov 

PS:
   no functional change, only code movement.
---
 hw/i386/acpi-build.c | 239 +++
 1 file changed, 126 insertions(+), 113 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1b609e6..765fccd 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -903,6 +903,130 @@ static Aml *build_crs(PCIHostState *host,
 return crs;
 }
 
+static void build_memory_devices(Aml *sb_scope, int nr_mem,
+ uint16_t io_base, uint16_t io_len)
+{
+int i;
+Aml *scope;
+Aml *crs;
+Aml *field;
+Aml *dev;
+Aml *method;
+Aml *ifctx;
+
+/* build memory devices */
+assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
+scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
+aml_append(scope,
+aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
+);
+
+crs = aml_resource_template();
+aml_append(crs,
+aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
+);
+aml_append(scope, aml_name_decl("_CRS", crs));
+
+aml_append(scope, aml_operation_region(
+stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
+io_base, io_len)
+);
+
+field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
+  AML_NOLOCK, AML_PRESERVE);
+aml_append(field, /* read only */
+aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
+aml_append(field, /* read only */
+aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
+aml_append(field, /* read only */
+aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
+aml_append(field, /* read only */
+aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
+aml_append(field, /* read only */
+aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
+aml_append(scope, field);
+
+field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
+  AML_NOLOCK, AML_WRITE_AS_ZEROS);
+aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
+aml_append(field, /* 1 if enabled, read only */
+aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
+aml_append(field,
+/*(read) 1 if has a insert event. (write) 1 to clear event */
+aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
+aml_append(field,
+/* (read) 1 if has a remove event. (write) 1 to clear event */
+aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1));
+aml_append(field,
+/* initiates device eject, write only */
+aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
+aml_append(scope, field);
+
+field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
+  AML_NOLOCK, AML_PRESERVE);
+aml_append(field, /* DIMM selector, write only */
+aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
+aml_append(field, /* _OST event code, write only */
+aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
+aml_append(field, /* _OST status code, write only */
+aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
+aml_append(scope, field);
+aml_append(sb_scope, scope);
+
+for (i = 0; i < nr_mem; i++) {
+#define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
+const char *s;
+
+dev = aml_device("MP%02X", i);
+aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
+
+method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
+aml_append(method, aml_return(aml_call1(s, aml_name("_UID";
+aml_append(dev, method);
+
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
+aml_append(method, aml_return(aml_call1(s, aml_name("_UID";
+aml_append(dev, method);
+
+method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
+s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
+aml_append(method, aml_return(aml_call1(s, aml_name("_UID";
+aml_append(dev, method);
+
+method = aml_method("_OST", 3, AML_NOTSERIALIZED);
+s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
+aml_append(method, aml_return(aml_call4(
+s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
+)));
+aml_append(dev, method);
+
+method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD);
+aml_append(method, aml_return(aml_call2(
+   s, aml_name("_UID"), am

[Qemu-devel] [PATCH 59/74] pc: acpi: piix4: move remaining PCI hotplug bits into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 43 +++
 hw/i386/acpi-dsdt.dsl | 40 
 2 files changed, 43 insertions(+), 40 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f0966b8..ba941aa 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1555,6 +1555,48 @@ static void build_piix4_isa_bridge(Aml *table)
 aml_append(table, scope);
 }
 
+static void build_piix4_pci_hotplug(Aml *table)
+{
+Aml *scope;
+Aml *field;
+Aml *method;
+
+scope =  aml_scope("_SB.PCI0");
+
+aml_append(scope,
+aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08));
+field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+aml_append(field, aml_named_field("PCIU", 32));
+aml_append(field, aml_named_field("PCID", 32));
+aml_append(scope, field);
+
+aml_append(scope,
+aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04));
+field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+aml_append(field, aml_named_field("B0EJ", 32));
+aml_append(scope, field);
+
+aml_append(scope,
+aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04));
+field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+aml_append(field, aml_named_field("BNUM", 32));
+aml_append(scope, field);
+
+aml_append(scope, aml_mutex("BLCK", 0));
+
+method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
+aml_append(method, aml_acquire(aml_name("BLCK"), 0x));
+aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+aml_append(method,
+aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
+aml_append(method, aml_release(aml_name("BLCK")));
+aml_append(method, aml_return(aml_int(0)));
+aml_append(scope, method);
+
+aml_append(table, scope);
+}
+
+
 static void
 build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -1581,6 +1623,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 build_piix4_pm(ssdt);
 build_piix4_isa_bridge(ssdt);
 build_isa_devices_aml(ssdt);
+build_piix4_pci_hotplug(ssdt);
 build_piix4_pci0_int(ssdt);
 } else {
 build_hpet_aml(ssdt);
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 5d741dd..a7769fc 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -38,44 +38,4 @@ DefinitionBlock (
 //External(PX13, DeviceObj)
 }
 }
-
-/
- * PCI hotplug
- /
-
-Scope(\_SB.PCI0) {
-OperationRegion(PCST, SystemIO, 0xae00, 0x08)
-Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
-PCIU, 32,
-PCID, 32,
-}
-
-OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
-Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
-B0EJ, 32,
-}
-
-OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
-Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
-BNUM, 32,
-}
-
-/* Lock to protect access to fields above. */
-Mutex(BLCK, 0)
-
-/* Methods called by bulk generated PCI devices below */
-
-/* Methods called by hotplug devices */
-Method(PCEJ, 2, NotSerialized) {
-// _EJ0 method - eject callback
-Acquire(BLCK, 0x)
-Store(Arg0, BNUM)
-Store(ShiftLeft(1, Arg1), B0EJ)
-Release(BLCK)
-Return (0x0)
-}
-
-/* Hotplug notification method supplied by SSDT */
-External(\_SB.PCI0.PCNT, MethodObj)
-}
 }
-- 
1.8.3.1

[Qemu-devel] [PATCH 50/74] pc: acpi: move FDC0 device from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 38 --
 hw/i386/acpi-dsdt-isa.dsl | 18 --
 2 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index e5ec6af..2f0f2e1 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1173,17 +1173,34 @@ static void build_hpet_aml(Aml *table)
 
 static Aml *
 build_eisa_device_aml(const char *name, const char *hid, Aml *crs,
-  bool have_sta)
+  bool have_sta, const char *present_field)
 {
 Aml *dev;
 Aml *method;
-Aml *a_device_present = aml_int(0x0f);
 
 dev = aml_device("%s", name);
 aml_append(dev, aml_name_decl("_HID", aml_eisaid(hid)));
 if (have_sta) {
+Aml *if_ctx;
+Aml *else_ctx;
+Aml *a_zero = aml_int(0);
+Aml *a_is_present = aml_local(0);
+Aml *a_device_present = aml_int(0x0f);
+Aml *a_device_not_present = aml_int(0x00);
+
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_return(a_device_present));
+if (!present_field) {
+aml_append(method, aml_return(a_device_present));
+} else {
+aml_append(method,
+aml_store(aml_name("%s", present_field), a_is_present));
+if_ctx = aml_if(aml_equal(a_is_present, a_zero));
+aml_append(if_ctx, aml_return(a_device_not_present));
+aml_append(method, if_ctx);
+else_ctx = aml_else();
+aml_append(else_ctx, aml_return(a_device_present));
+aml_append(method, else_ctx);
+}
 aml_append(dev, method);
 }
 aml_append(dev, aml_name_decl("_CRS", crs));
@@ -1201,19 +1218,28 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(crs, aml_irq_no_flags(8));
 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
 aml_append(scope, build_eisa_device_aml(
-"RTC", "PNP0B00", crs, false));
+"RTC", "PNP0B00", crs, false, NULL));
 
 crs = aml_resource_template();
 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
 aml_append(crs, aml_irq_no_flags(1));
 aml_append(scope, build_eisa_device_aml(
-"KBD", "PNP0303", crs, true));
+"KBD", "PNP0303", crs, true, NULL));
 
 crs = aml_resource_template();
 aml_append(crs, aml_irq_no_flags(12));
 aml_append(scope, build_eisa_device_aml(
-"MOU", "PNP0F13", crs, true));
+"MOU", "PNP0F13", crs, true, NULL));
+
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
+aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
+aml_append(crs, aml_irq_no_flags(6));
+aml_append(crs,
+aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
+aml_append(scope, build_eisa_device_aml(
+"FDC0", "PNP0700", crs, true, "FDEN"));
 
 aml_append(table, scope);
 }
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index 8936271..64dd4ac 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,24 +16,6 @@
 /* Common legacy ISA style devices. */
 Scope(\_SB.PCI0.ISA) {
 
-Device(FDC0) {
-Name(_HID, EisaId("PNP0700"))
-Method(_STA, 0, NotSerialized) {
-Store(FDEN, Local0)
-If (LEqual(Local0, 0)) {
-Return (0x00)
-} Else {
-Return (0x0F)
-}
-}
-Name(_CRS, ResourceTemplate() {
-IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-IRQNoFlags() { 6 }
-DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
-})
-}
-
 Device(LPT) {
 Name(_HID, EisaId("PNP0400"))
 Method(_STA, 0, NotSerialized) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 34/74] pc: acpi: memhp: move MHPD Device into SSDT

[Igor Mammedov]

move remnants of MHPD device from DSDT into SSDT.
 i.e. Device(MHPD), _UID, _HID

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 6 +-
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 7 ---
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index 622cd5c..b913edc 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -39,13 +39,17 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 
 /* scope for memory hotplug controller device node */
 pci_scope = aml_scope("_SB.PCI0");
-ctrl_dev = aml_scope(stringify(MEMORY_HOTPLUG_DEVICE));
+ctrl_dev = aml_device(stringify(MEMORY_HOTPLUG_DEVICE));
 {
 Aml *a_ctrl_lock = aml_name(stringify(MEMORY_SLOT_LOCK));
 Aml *a_slot_selector = aml_name(stringify(MEMORY_SLOT_SLECTOR));
 Aml *a_ret_val = aml_local(0);
 Aml *a_slot_arg0 = aml_arg(0);
 
+aml_append(ctrl_dev, aml_name_decl("_HID", aml_string("PNP0A06")));
+aml_append(ctrl_dev,
+aml_name_decl("_UID", aml_string("Memory hotplug resources")));
+
 /* MHPD._STA() method */
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
 ifctx = aml_if(aml_equal(a_slots_nr, a_zero));
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 50b7541..20c5ec1 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -14,10 +14,3 @@
  */
 
 External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD, 
MethodObj)
-
-Scope(\_SB.PCI0) {
-Device(MEMORY_HOTPLUG_DEVICE) {
-Name(_HID, "PNP0A06")
-Name(_UID, "Memory hotplug resources")
-} // Device()
-} // Scope()
-- 
1.8.3.1

[Qemu-devel] [PATCH 55/74] pc: acpi: pci: move link devices into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  | 77 +++
 hw/i386/acpi-dsdt.dsl | 49 
 2 files changed, 82 insertions(+), 44 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 99c0294..f5e519b 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1303,9 +1303,49 @@ static void build_dbg_aml(Aml *table)
 aml_append(table, scope);
 }
 
+static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
+{
+Aml *dev;
+Aml *crs;
+Aml *method;
+uint32_t irqs[] = {5, 10, 11};
+
+dev = aml_device("%s", name);
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+crs = aml_resource_template();
+aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+  AML_SHARED, irqs, ARRAY_SIZE(irqs)));
+aml_append(dev, aml_name_decl("_PRS", crs));
+
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_return(aml_call1("IQST", reg)));
+aml_append(dev, method);
+
+method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_or(reg, aml_int(0x80), reg));
+aml_append(dev, method);
+
+method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_return(aml_call1("IQCR", reg)));
+aml_append(dev, method);
+
+method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
+aml_append(method, aml_store(aml_name("PRRI"), reg));
+aml_append(dev, method);
+
+return dev;
+ }
+
 static void build_piix4_pci0_int(Aml *table)
 {
+Aml *dev;
+Aml *crs;
 Aml *field;
+Aml *method;
+uint32_t irqs;
 Aml *sb_scope = aml_scope("_SB");
 
 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
@@ -1315,6 +1355,43 @@ static void build_piix4_pci0_int(Aml *table)
 aml_append(field, aml_named_field("PRQ3", 8));
 aml_append(sb_scope, field);
 
+aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
+aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
+aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
+aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
+
+dev = aml_device("LNKS");
+{
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+aml_append(dev, aml_name_decl("_UID", aml_int(4)));
+
+crs = aml_resource_template();
+irqs = 9;
+aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+  AML_ACTIVE_HIGH, AML_SHARED,
+  &irqs, 1));
+aml_append(dev, aml_name_decl("_PRS", crs));
+
+/* The SCI cannot be disabled and is always attached to GSI 9,
+ * so these are no-ops.  We only need this link to override the
+ * polarity to active high and match the content of the MADT.
+ */
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_return(aml_int(0x0b)));
+aml_append(dev, method);
+
+method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+aml_append(dev, method);
+
+method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+aml_append(method, aml_return(aml_name("_PRS")));
+aml_append(dev, method);
+
+method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+aml_append(dev, method);
+}
+aml_append(sb_scope, dev);
+
 aml_append(table, sb_scope);
 }
 
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index c9b2725..b74cffd 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -152,49 +152,10 @@ DefinitionBlock (
 Return (PRR0)
 }
 
-#define define_link(link, uid, reg) \
-Device(link) {  \
-Name(_HID, EISAID("PNP0C0F"))   \
-Name(_UID, uid) \
-Name(_PRS, ResourceTemplate() { \
-Interrupt(, Level, ActiveHigh, Shared) {\
-5, 10, 11   \
-}   \
-})  \
-Method(_STA, 0, NotSerialized) {\
-Return (IQST(reg))  \
-}   \
-Method(_DIS, 0, NotSerialized) {\
-Or(reg, 0x80, reg)  \
-}   \
-Method(_CRS, 0, NotSerialized) {\
- 

[Qemu-devel] [PATCH 31/74] pc: acpi: memhp: move MHPD.MOST method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 15 +++
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 10 --
 2 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index 92591f6..5dfdab7 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -131,6 +131,21 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(method, aml_return(a_ret_val));
 }
 aml_append(ctrl_dev, method);
+
+method = aml_method(stringify(MEMORY_SLOT_OST_METHOD), 4,
+AML_NOTSERIALIZED);
+{
+Aml *a_ost_evt = aml_name(stringify(MEMORY_SLOT_OST_EVENT));
+Aml *a_ost_status = aml_name(stringify(MEMORY_SLOT_OST_STATUS));
+
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+aml_append(method, aml_store(aml_to_integer(a_slot_arg0),
+ a_slot_selector));
+aml_append(method, aml_store(aml_arg(1), a_ost_evt));
+aml_append(method, aml_store(aml_arg(2), a_ost_status));
+aml_append(method, aml_release(a_ctrl_lock));
+}
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 02fecf2..8889eca 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -27,8 +27,6 @@
 External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
 External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device 
eject, write only
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
-External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
-External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status 
code, write only
 External(MEMORY_SLOT_LOCK, MutexObj)
 
 Method(MEMORY_SLOT_CRS_METHOD, 1, Serialized) {
@@ -95,14 +93,6 @@
 Return(MR64)
 }
 
-Method(MEMORY_SLOT_OST_METHOD, 4) {
-Acquire(MEMORY_SLOT_LOCK, 0x)
-Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-Store(Arg1, MEMORY_SLOT_OST_EVENT)
-Store(Arg2, MEMORY_SLOT_OST_STATUS)
-Release(MEMORY_SLOT_LOCK)
-}
-
 Method(MEMORY_SLOT_EJECT_METHOD, 2) {
 Acquire(MEMORY_SLOT_LOCK, 0x)
 Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-- 
1.8.3.1

[Qemu-devel] [PATCH 46/74] pc: acpi: move DBUG() from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c   | 36 
 hw/i386/acpi-dsdt-dbug.dsl | 41 -
 hw/i386/acpi-dsdt.dsl  |  2 --
 hw/i386/q35-acpi-dsdt.dsl  |  2 --
 4 files changed, 36 insertions(+), 45 deletions(-)
 delete mode 100644 hw/i386/acpi-dsdt-dbug.dsl

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 62f932e..4b7229d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1171,6 +1171,41 @@ static void build_hpet_aml(Aml *table)
 aml_append(table, scope);
 }
 
+static void build_dbg_aml(Aml *table)
+{
+Aml *field;
+Aml *method;
+Aml *while_ctx;
+Aml *scope = aml_scope("\\");
+Aml *a_buf = aml_local(0);
+Aml *a_len = aml_local(1);
+Aml *a_idx = aml_local(2);
+
+aml_append(scope, aml_operation_region("DBG", AML_SYSTEM_IO,
+ 0x0402, 0x01));
+field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("DBGB", 8));
+aml_append(scope, field);
+
+method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
+
+aml_append(method, aml_to_hexstring(aml_arg(0), a_buf));
+aml_append(method, aml_to_buffer(a_buf, a_buf));
+aml_append(method, aml_subtract(aml_sizeof(a_buf), aml_int(1), a_len));
+aml_append(method, aml_store(aml_int(0), a_idx));
+
+while_ctx = aml_while(aml_lless(a_idx, a_len));
+aml_append(while_ctx,
+aml_store(aml_derefof(aml_index(a_buf, a_idx)), aml_name("DBGB")));
+aml_append(while_ctx, aml_increment(a_idx));
+aml_append(method, while_ctx);
+
+aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
+aml_append(scope, method);
+
+aml_append(table, scope);
+}
+
 static void
 build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -1191,6 +1226,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
+build_dbg_aml(ssdt);
 build_hpet_aml(ssdt);
 build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
diff --git a/hw/i386/acpi-dsdt-dbug.dsl b/hw/i386/acpi-dsdt-dbug.dsl
deleted file mode 100644
index 86230f7..000
--- a/hw/i386/acpi-dsdt-dbug.dsl
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see .
- */
-
-/
- * Debugging
- /
-
-Scope(\) {
-/* Debug Output */
-OperationRegion(DBG, SystemIO, 0x0402, 0x01)
-Field(DBG, ByteAcc, NoLock, Preserve) {
-DBGB,   8,
-}
-
-/* Debug method - use this method to send output to the QEMU
- * BIOS debug port.  This method handles strings, integers,
- * and buffers.  For example: DBUG("abc") DBUG(0x123) */
-Method(DBUG, 1) {
-ToHexString(Arg0, Local0)
-ToBuffer(Local0, Local0)
-Subtract(SizeOf(Local0), 1, Local1)
-Store(Zero, Local2)
-While (LLess(Local2, Local1)) {
-Store(DerefOf(Index(Local0, Local2)), DBGB)
-Increment(Local2)
-}
-Store(0x0A, DBGB)
-}
-}
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index aa7f549..55c2220 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -29,8 +29,6 @@ DefinitionBlock (
 )
 {
 
-#include "acpi-dsdt-dbug.dsl"
-
 Scope(\_SB) {
 Device(PCI0) {
 Name(_HID, EisaId("PNP0A03"))
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index e57adb8..bf3f974 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -35,8 +35,6 @@ DefinitionBlock (
 )
 {
 
-#include "acpi-dsdt-dbug.dsl"
-
 Scope(\_SB) {
 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
-- 
1.8.3.1

[Qemu-devel] [PATCH 30/74] pc: acpi: memhp: move MHPD.MPXM method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 14 ++
 hw/i386/acpi-dsdt-mem-hotplug.dsl   |  9 -
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index b76694d..92591f6 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -117,6 +117,20 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(method, aml_return(a_ret_val));
 }
 aml_append(ctrl_dev, method);
+
+method = aml_method(stringify(MEMORY_SLOT_PROXIMITY_METHOD), 1,
+AML_NOTSERIALIZED);
+{
+Aml *a_proximity = aml_name(stringify(MEMORY_SLOT_PROXIMITY));
+
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+aml_append(method, aml_store(aml_to_integer(a_slot_arg0),
+ a_slot_selector));
+aml_append(method, aml_store(a_proximity, a_ret_val));
+aml_append(method, aml_release(a_ctrl_lock));
+aml_append(method, aml_return(a_ret_val));
+}
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 13e93dc..02fecf2 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -25,7 +25,6 @@
 External(MEMORY_SLOT_ADDR_HIGH, FieldUnitObj) // read only
 External(MEMORY_SLOT_SIZE_LOW, FieldUnitObj) // read only
 External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
-External(MEMORY_SLOT_PROXIMITY, FieldUnitObj) // read only
 External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device 
eject, write only
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
 External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
@@ -96,14 +95,6 @@
 Return(MR64)
 }
 
-Method(MEMORY_SLOT_PROXIMITY_METHOD, 1) {
-Acquire(MEMORY_SLOT_LOCK, 0x)
-Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-Store(MEMORY_SLOT_PROXIMITY, Local0)
-Release(MEMORY_SLOT_LOCK)
-Return(Local0)
-}
-
 Method(MEMORY_SLOT_OST_METHOD, 4) {
 Acquire(MEMORY_SLOT_LOCK, 0x)
 Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-- 
1.8.3.1

[Qemu-devel] [PATCH 51/74] pc: acpi: move LPT device from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  6 ++
 hw/i386/acpi-dsdt-isa.dsl | 16 
 2 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2f0f2e1..bd03491 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1241,6 +1241,12 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(scope, build_eisa_device_aml(
 "FDC0", "PNP0700", crs, true, "FDEN"));
 
+crs = aml_resource_template();
+aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
+aml_append(crs, aml_irq_no_flags(7));
+aml_append(scope, build_eisa_device_aml(
+"LPT", "PNP0400", crs, true, "LPEN"));
+
 aml_append(table, scope);
 }
 
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index 64dd4ac..cc5e8f9 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,22 +16,6 @@
 /* Common legacy ISA style devices. */
 Scope(\_SB.PCI0.ISA) {
 
-Device(LPT) {
-Name(_HID, EisaId("PNP0400"))
-Method(_STA, 0, NotSerialized) {
-Store(LPEN, Local0)
-If (LEqual(Local0, 0)) {
-Return (0x00)
-} Else {
-Return (0x0F)
-}
-}
-Name(_CRS, ResourceTemplate() {
-IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
-IRQNoFlags() { 7 }
-})
-}
-
 Device(COM1) {
 Name(_HID, EisaId("PNP0501"))
 Name(_UID, 0x01)
-- 
1.8.3.1

[Qemu-devel] [PATCH 32/74] pc: acpi: memhp: move MHPD.MEJ0 method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 13 +
 hw/i386/acpi-dsdt-mem-hotplug.dsl   |  8 
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index 5dfdab7..9795a9f 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -146,6 +146,19 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(method, aml_release(a_ctrl_lock));
 }
 aml_append(ctrl_dev, method);
+
+method = aml_method(stringify(MEMORY_SLOT_EJECT_METHOD), 2,
+AML_NOTSERIALIZED);
+{
+Aml *a_eject = aml_name(stringify(MEMORY_SLOT_EJECT));
+
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+aml_append(method, aml_store(aml_to_integer(a_slot_arg0),
+ a_slot_selector));
+aml_append(method, aml_store(a_one, a_eject));
+aml_append(method, aml_release(a_ctrl_lock));
+}
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 8889eca..87d8d66 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -25,7 +25,6 @@
 External(MEMORY_SLOT_ADDR_HIGH, FieldUnitObj) // read only
 External(MEMORY_SLOT_SIZE_LOW, FieldUnitObj) // read only
 External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
-External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device 
eject, write only
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
 External(MEMORY_SLOT_LOCK, MutexObj)
 
@@ -92,12 +91,5 @@
 Release(MEMORY_SLOT_LOCK)
 Return(MR64)
 }
-
-Method(MEMORY_SLOT_EJECT_METHOD, 2) {
-Acquire(MEMORY_SLOT_LOCK, 0x)
-Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-Store(1, MEMORY_SLOT_EJECT)
-Release(MEMORY_SLOT_LOCK)
-}
 } // Device()
 } // Scope()
-- 
1.8.3.1

[Qemu-devel] [PATCH 39/74] pc: acpi: cpuhp: move CPEJ() method to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/Makefile.objs |  2 +-
 hw/acpi/cpu_hotplug_acpi_table.c  | 28 
 hw/i386/acpi-build.c  |  3 ++-
 hw/i386/acpi-dsdt-cpu-hotplug.dsl |  4 
 include/hw/acpi/cpu_hotplug.h |  5 +
 5 files changed, 36 insertions(+), 6 deletions(-)
 create mode 100644 hw/acpi/cpu_hotplug_acpi_table.c

diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index c04064e..cd09d93 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,6 +1,6 @@
 common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o
 common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o
-common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
+common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o cpu_hotplug_acpi_table.o
 common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o 
memory_hotplug_acpi_table.o
 common-obj-$(CONFIG_ACPI) += acpi_interface.o
 common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c
new file mode 100644
index 000..422e57b
--- /dev/null
+++ b/hw/acpi/cpu_hotplug_acpi_table.c
@@ -0,0 +1,28 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ */
+
+#include "hw/acpi/cpu_hotplug.h"
+
+void build_cpu_hotplug_aml(Aml *ctx)
+{
+Aml *method;
+Aml *sb_scope = aml_scope("_SB");
+
+method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED);
+aml_append(method, aml_sleep(200));
+aml_append(sb_scope, method);
+
+aml_append(ctx, sb_scope);
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f6337ca..9f8f769 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1052,6 +1052,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
+build_cpu_hotplug_aml(ssdt);
 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
  pm->mem_hp_io_len);
 
@@ -1299,7 +1300,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 
 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
 aml_append(method,
-aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
+aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
 );
 aml_append(dev, method);
 
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index 53e1389..18331be 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -48,10 +48,6 @@ Scope(\_SB) {
 Return (0x0)
 }
 }
-Method(CPEJ, 2, NotSerialized) {
-// _EJ0 method - eject callback
-Sleep(200)
-}
 
 Method(PRSC, 0) {
 // Local5 = active cpu bitmap
diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
index f6d358d..87504be 100644
--- a/include/hw/acpi/cpu_hotplug.h
+++ b/include/hw/acpi/cpu_hotplug.h
@@ -14,6 +14,7 @@
 
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/pc-hotplug.h"
+#include "hw/acpi/aml-build.h"
 
 typedef struct AcpiCpuHotplug {
 MemoryRegion io;
@@ -25,4 +26,8 @@ void acpi_cpu_plug_cb(ACPIREGS *ar, qemu_irq irq,
 
 void acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner,
AcpiCpuHotplug *gpe_cpu, uint16_t base);
+
+#define CPU_EJECT_METHOD "CPEJ"
+
+void build_cpu_hotplug_aml(Aml *ctx);
 #endif
-- 
1.8.3.1

[Qemu-devel] [PATCH 27/74] pc: acpi: memhp: move MHPD.MLCK mutex into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 2 ++
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index de51717..d389f73 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -46,6 +46,8 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 /* present, functioning, decoding, not shown in UI */
 aml_append(method, aml_return(aml_int(0xB)));
 aml_append(ctrl_dev, method);
+
+aml_append(ctrl_dev, aml_mutex(stringify(MEMORY_SLOT_LOCK), 0));
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index b4eacc9..a1e519b 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -34,8 +34,7 @@
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
 External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
 External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status 
code, write only
-
-Mutex (MEMORY_SLOT_LOCK, 0)
+External(MEMORY_SLOT_LOCK, MutexObj)
 
 Method(MEMORY_SLOT_SCAN_METHOD, 0) {
 If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 24/74] acpi: extend aml_interrupt() to support multiple irqs

[Igor Mammedov]

ASL Interrupt() macro translates to Extended Interrupt Descriptor
which supports variable number of IRQs. It will be used for
conversion of ASL code for pc/q35 machines that use it for
returning several IRQs in _PSR object.

Signed-off-by: Igor Mammedov 
---
CC: zhaoshengl...@huawei.com
CC: qemu-...@nongnu.org
---
 hw/acpi/aml-build.c | 22 +-
 hw/arm/virt-acpi-build.c| 23 ---
 include/hw/acpi/aml-build.h |  2 +-
 3 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 2ca9207..ee64d12 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -667,23 +667,27 @@ Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
 Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
AmlLevelAndEdge level_and_edge,
AmlActiveHighAndLow high_and_low, AmlShared shared,
-   uint32_t irq)
+   uint32_t *irq_list, uint8_t irq_count)
 {
+int i;
 Aml *var = aml_alloc();
 uint8_t irq_flags = con_and_pro | (level_and_edge << 1)
 | (high_and_low << 2) | (shared << 3);
+const int header_bytes_in_len = 2;
+uint16_t len = header_bytes_in_len + irq_count * sizeof(uint32_t);
+
+assert(irq_count > 0);
 
 build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
-build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
-build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
+build_append_byte(var->buf, len & 0xFF); /* Length, bits[7:0] */
+build_append_byte(var->buf, len >> 8); /* Length, bits[15:8] */
 build_append_byte(var->buf, irq_flags); /* Interrupt Vector Information. */
-build_append_byte(var->buf, 0x01);  /* Interrupt table length = 1 */
+build_append_byte(var->buf, irq_count);   /* Interrupt table length */
 
-/* Interrupt Number */
-build_append_byte(var->buf, extract32(irq, 0, 8));  /* bits[7:0] */
-build_append_byte(var->buf, extract32(irq, 8, 8));  /* bits[15:8] */
-build_append_byte(var->buf, extract32(irq, 16, 8)); /* bits[23:16] */
-build_append_byte(var->buf, extract32(irq, 24, 8)); /* bits[31:24] */
+/* Interrupt Number List */
+for (i = 0; i < irq_count; i++) {
+build_append_int_noprefix(var->buf, irq_list[i], 4);
+}
 return var;
 }
 
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 698b5f2..02ba822 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -71,7 +71,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
 }
 
 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
-   int uart_irq)
+   uint32_t uart_irq)
 {
 Aml *dev = aml_device("COM0");
 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
@@ -82,7 +82,7 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry 
*uart_memmap,
uart_memmap->size, AML_READ_WRITE));
 aml_append(crs,
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, uart_irq));
+ AML_EXCLUSIVE, &uart_irq, 1));
 aml_append(dev, aml_name_decl("_CRS", crs));
 
 /* The _ADR entry is used to link this device to the UART described
@@ -94,7 +94,7 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry 
*uart_memmap,
 }
 
 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap,
-  int rtc_irq)
+  uint32_t rtc_irq)
 {
 Aml *dev = aml_device("RTC0");
 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
@@ -105,7 +105,7 @@ static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry 
*rtc_memmap,
rtc_memmap->size, AML_READ_WRITE));
 aml_append(crs,
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, rtc_irq));
+ AML_EXCLUSIVE, &rtc_irq, 1));
 aml_append(dev, aml_name_decl("_CRS", crs));
 aml_append(scope, dev);
 }
@@ -136,11 +136,11 @@ static void acpi_dsdt_add_flash(Aml *scope, const 
MemMapEntry *flash_memmap)
 
 static void acpi_dsdt_add_virtio(Aml *scope,
  const MemMapEntry *virtio_mmio_memmap,
- int mmio_irq, int num)
+ uint32_t mmio_irq, int num)
 {
 hwaddr base = virtio_mmio_memmap->base;
 hwaddr size = virtio_mmio_memmap->size;
-int irq = mmio_irq;
+uint32_t irq = mmio_irq;
 int i;
 
 for (i = 0; i < num; i++) {
@@ -152,15 +152,15 @@ static void acpi_dsdt_add_virtio(Aml *scope,
 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
  

[Qemu-devel] [PATCH 29/74] pc: acpi: memhp: move MHPD.MRST method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 21 +
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 15 ---
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index cda05f4..b76694d 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -43,6 +43,8 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 {
 Aml *a_ctrl_lock = aml_name(stringify(MEMORY_SLOT_LOCK));
 Aml *a_slot_selector = aml_name(stringify(MEMORY_SLOT_SLECTOR));
+Aml *a_ret_val = aml_local(0);
+Aml *a_slot_arg0 = aml_arg(0);
 
 /* MHPD._STA() method */
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
@@ -96,6 +98,25 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(method, aml_return(a_one));
 }
 aml_append(ctrl_dev, method);
+
+method = aml_method(stringify(MEMORY_SLOT_STATUS_METHOD), 1,
+AML_NOTSERIALIZED);
+{
+Aml *a_slot_enabled = aml_name(stringify(MEMORY_SLOT_ENABLED));
+
+aml_append(method, aml_store(a_zero, a_ret_val));
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+aml_append(method, aml_store(aml_to_integer(a_slot_arg0),
+ a_slot_selector));
+
+ifctx = aml_if(aml_equal(a_slot_enabled, a_one));
+aml_append(ifctx, aml_store(aml_int(0xF), a_ret_val));
+aml_append(method, ifctx);
+
+aml_append(method, aml_release(a_ctrl_lock));
+aml_append(method, aml_return(a_ret_val));
+}
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index 92baf87..13e93dc 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -26,27 +26,12 @@
 External(MEMORY_SLOT_SIZE_LOW, FieldUnitObj) // read only
 External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
 External(MEMORY_SLOT_PROXIMITY, FieldUnitObj) // read only
-External(MEMORY_SLOT_ENABLED, FieldUnitObj) // 1 if enabled, read 
only
 External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device 
eject, write only
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
 External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
 External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status 
code, write only
 External(MEMORY_SLOT_LOCK, MutexObj)
 
-Method(MEMORY_SLOT_STATUS_METHOD, 1) {
-Store(Zero, Local0)
-
-Acquire(MEMORY_SLOT_LOCK, 0x)
-Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-
-If (LEqual(MEMORY_SLOT_ENABLED, One)) {
-Store(0xF, Local0)
-}
-
-Release(MEMORY_SLOT_LOCK)
-Return(Local0)
-}
-
 Method(MEMORY_SLOT_CRS_METHOD, 1, Serialized) {
 Acquire(MEMORY_SLOT_LOCK, 0x)
 Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM
-- 
1.8.3.1

[Qemu-devel] [PATCH 49/74] pc: acpi: move MOU device from DSDT to SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c  |  5 +
 hw/i386/acpi-dsdt-isa.dsl | 10 --
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c485530..e5ec6af 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1210,6 +1210,11 @@ static void build_isa_devices_aml(Aml *table)
 aml_append(scope, build_eisa_device_aml(
 "KBD", "PNP0303", crs, true));
 
+crs = aml_resource_template();
+aml_append(crs, aml_irq_no_flags(12));
+aml_append(scope, build_eisa_device_aml(
+"MOU", "PNP0F13", crs, true));
+
 aml_append(table, scope);
 }
 
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index f7a3c0a..8936271 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,16 +16,6 @@
 /* Common legacy ISA style devices. */
 Scope(\_SB.PCI0.ISA) {
 
-Device(MOU) {
-Name(_HID, EisaId("PNP0F13"))
-Method(_STA, 0, NotSerialized) {
-Return (0x0f)
-}
-Name(_CRS, ResourceTemplate() {
-IRQNoFlags() { 12 }
-})
-}
-
 Device(FDC0) {
 Name(_HID, EisaId("PNP0700"))
 Method(_STA, 0, NotSerialized) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 26/74] pc: acpi: memhp: move MHPD._STA method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 12 
 hw/i386/acpi-dsdt-mem-hotplug.dsl   |  8 
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index 25bbf5e..de51717 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -29,11 +29,23 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 {
 Aml *pci_scope;
 Aml *ctrl_dev;
+Aml *method;
+Aml *ifctx;
+Aml *a_zero = aml_int(0);
+Aml *a_slots_nr = aml_name(stringify(MEMORY_SLOTS_NUMBER));
 
 /* scope for memory hotplug controller device node */
 pci_scope = aml_scope("_SB.PCI0");
 ctrl_dev = aml_scope(stringify(MEMORY_HOTPLUG_DEVICE));
 {
+/* MHPD._STA() method */
+method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ifctx = aml_if(aml_equal(a_slots_nr, a_zero));
+aml_append(ifctx, aml_return(a_zero));
+aml_append(method, ifctx);
+/* present, functioning, decoding, not shown in UI */
+aml_append(method, aml_return(aml_int(0xB)));
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index c2bb6a1..b4eacc9 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -35,14 +35,6 @@
 External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
 External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status 
code, write only
 
-Method(_STA, 0) {
-If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) {
-Return(0x0)
-}
-/* present, functioning, decoding, not shown in UI */
-Return(0xB)
-}
-
 Mutex (MEMORY_SLOT_LOCK, 0)
 
 Method(MEMORY_SLOT_SCAN_METHOD, 0) {
-- 
1.8.3.1

[Qemu-devel] [PATCH 38/74] pc: acpi: drop unused CPU_STATUS_LEN from DSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-dsdt-cpu-hotplug.dsl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl 
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index 1aff746..53e1389 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -53,7 +53,6 @@ Scope(\_SB) {
 Sleep(200)
 }
 
-#define CPU_STATUS_LEN ACPI_GPE_PROC_LEN
 Method(PRSC, 0) {
 // Local5 = active cpu bitmap
 Store(PRS, Local5)
-- 
1.8.3.1

[Qemu-devel] [PATCH 28/74] pc: acpi: memhp: move MHPD.MSCN method into SSDT

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/memory_hotplug_acpi_table.c | 48 +
 hw/i386/acpi-dsdt-mem-hotplug.dsl   | 27 +
 2 files changed, 49 insertions(+), 26 deletions(-)

diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
index d389f73..cda05f4 100644
--- a/hw/acpi/memory_hotplug_acpi_table.c
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -31,13 +31,19 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 Aml *ctrl_dev;
 Aml *method;
 Aml *ifctx;
+Aml *else_ctx;
+Aml *while_ctx;
 Aml *a_zero = aml_int(0);
+Aml *a_one = aml_int(1);
 Aml *a_slots_nr = aml_name(stringify(MEMORY_SLOTS_NUMBER));
 
 /* scope for memory hotplug controller device node */
 pci_scope = aml_scope("_SB.PCI0");
 ctrl_dev = aml_scope(stringify(MEMORY_HOTPLUG_DEVICE));
 {
+Aml *a_ctrl_lock = aml_name(stringify(MEMORY_SLOT_LOCK));
+Aml *a_slot_selector = aml_name(stringify(MEMORY_SLOT_SLECTOR));
+
 /* MHPD._STA() method */
 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
 ifctx = aml_if(aml_equal(a_slots_nr, a_zero));
@@ -48,6 +54,48 @@ void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
 aml_append(ctrl_dev, method);
 
 aml_append(ctrl_dev, aml_mutex(stringify(MEMORY_SLOT_LOCK), 0));
+
+method = aml_method(stringify(MEMORY_SLOT_SCAN_METHOD), 0,
+AML_NOTSERIALIZED);
+{
+Aml *a_idx = aml_local(0);
+
+ifctx = aml_if(aml_equal(a_slots_nr, a_zero));
+aml_append(ifctx, aml_return(a_zero));
+aml_append(method, ifctx);
+
+aml_append(method, aml_store(aml_int(0), a_idx));
+aml_append(method, aml_acquire(a_ctrl_lock, 0x));
+while_ctx = aml_while(
+aml_lless(a_idx, a_slots_nr));
+{
+Aml *a_ins_evt = aml_name(stringify(MEMORY_SLOT_INSERT_EVENT));
+Aml *a_rm_evt = aml_name(stringify(MEMORY_SLOT_REMOVE_EVENT));
+
+aml_append(while_ctx, aml_store(a_idx, a_slot_selector));
+ifctx = aml_if(aml_equal(a_ins_evt, a_one));
+aml_append(ifctx,
+aml_call2(stringify(MEMORY_SLOT_NOTIFY_METHOD),
+  a_idx, a_one));
+aml_append(ifctx, aml_store(a_one, a_ins_evt));
+aml_append(while_ctx, ifctx);
+
+else_ctx = aml_else();
+ifctx = aml_if(aml_equal(a_rm_evt, a_one));
+aml_append(ifctx,
+aml_call2(stringify(MEMORY_SLOT_NOTIFY_METHOD),
+  a_idx, aml_int(3)));
+aml_append(ifctx, aml_store(a_one, a_rm_evt));
+aml_append(else_ctx, ifctx);
+aml_append(while_ctx, else_ctx);
+
+aml_append(while_ctx, aml_add(a_idx, a_one, a_idx));
+}
+aml_append(method, while_ctx);
+aml_append(method, aml_release(a_ctrl_lock));
+aml_append(method, aml_return(a_one));
+}
+aml_append(ctrl_dev, method);
 }
 aml_append(pci_scope, ctrl_dev);
 aml_append(ctx, pci_scope);
diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl 
b/hw/i386/acpi-dsdt-mem-hotplug.dsl
index a1e519b..92baf87 100644
--- a/hw/i386/acpi-dsdt-mem-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-mem-hotplug.dsl
@@ -13,13 +13,12 @@
  * with this program; if not, see .
  */
 
-External(MEMORY_SLOT_NOTIFY_METHOD, MethodObj)
+External(\_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD, 
MethodObj)
 
 Scope(\_SB.PCI0) {
 Device(MEMORY_HOTPLUG_DEVICE) {
 Name(_HID, "PNP0A06")
 Name(_UID, "Memory hotplug resources")
-External(MEMORY_SLOTS_NUMBER, IntObj)
 
 /* Memory hotplug IO registers */
 External(MEMORY_SLOT_ADDR_LOW, FieldUnitObj) // read only
@@ -28,36 +27,12 @@
 External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only
 External(MEMORY_SLOT_PROXIMITY, FieldUnitObj) // read only
 External(MEMORY_SLOT_ENABLED, FieldUnitObj) // 1 if enabled, read 
only
-External(MEMORY_SLOT_INSERT_EVENT, FieldUnitObj) // (read) 1 if 
has a insert event. (write) 1 to clear event
-External(MEMORY_SLOT_REMOVE_EVENT, FieldUnitObj) // (read) 1 if 
has a remove event. (write) 1 to clear event
 External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device 
eject, write only
 External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, 
write only
 External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, 
write only
 External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status 
code, write only
 External(MEMORY_SLOT_LOCK, MutexObj)
 
-Method(MEMORY_SLOT_SCAN_METHOD

[Qemu-devel] [PATCH 17/74] acpi: add aml_lgreater()

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 9 +
 include/hw/acpi/aml-build.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 8cfa65c..b22e7da 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -715,6 +715,15 @@ Aml *aml_equal(Aml *arg1, Aml *arg2)
 return var;
 }
 
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLGreater */
+Aml *aml_lgreater(Aml *arg1, Aml *arg2)
+{
+Aml *var = aml_opcode(0x94 /* LGreaterOp */);
+aml_append(var, arg1);
+aml_append(var, arg2);
+return var;
+}
+
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLGreaterEqual */
 Aml *aml_lgreater_equal(Aml *arg1, Aml *arg2)
 {
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 897e093..238a9dc 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -240,6 +240,7 @@ Aml *aml_local(int num);
 Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
 Aml *aml_lnot(Aml *arg);
 Aml *aml_equal(Aml *arg1, Aml *arg2);
+Aml *aml_lgreater(Aml *arg1, Aml *arg2);
 Aml *aml_lgreater_equal(Aml *arg1, Aml *arg2);
 Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...) GCC_FMT_ATTR(4, 5);
-- 
1.8.3.1

[Qemu-devel] [PATCH 23/74] acpi: extend aml_and() to accept target argument

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 4 ++--
 hw/arm/virt-acpi-build.c| 2 +-
 hw/i386/acpi-build.c| 8 +---
 include/hw/acpi/aml-build.h | 2 +-
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 4f62512..2ca9207 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -499,9 +499,9 @@ build_opcode_2arg_dst(uint8_t op, Aml *arg1, Aml *arg2, Aml 
*dst)
 }
 
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
-Aml *aml_and(Aml *arg1, Aml *arg2)
+Aml *aml_and(Aml *arg1, Aml *arg2, Aml *dst)
 {
-return build_opcode_2arg_dst(0x7B /* AndOp */, arg1, arg2, NULL);
+return build_opcode_2arg_dst(0x7B /* AndOp */, arg1, arg2, dst);
 }
 
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 1cc98f5..698b5f2 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -272,7 +272,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry 
*memmap, int irq,
 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
-aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
+aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
 aml_name("CTRL")));
 
 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fd8ccfc..bbd37e9 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -469,7 +469,7 @@ static void build_append_pcihp_notify_entry(Aml *method, 
int slot)
 Aml *if_ctx;
 int32_t devfn = PCI_DEVFN(slot, 0);
 
-if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
+if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
 aml_append(method, if_ctx);
 }
@@ -669,7 +669,8 @@ static Aml *build_prt(void)
aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
 /* lnk_idx = (slot + pin) & 3 */
 aml_append(while_ctx,
-aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3)), lnk_idx));
+aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
+  lnk_idx));
 
 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3  */
 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
@@ -684,7 +685,8 @@ static Aml *build_prt(void)
   aml_index(route, aml_int(0;
 /* route[1] = pin & 3 */
 aml_append(while_ctx,
-aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1;
+aml_store(aml_and(pin, aml_int(3), NULL),
+  aml_index(route, aml_int(1;
 /* res[pin] = route */
 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
 /* pin++ */
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 3be727e..ca365c9 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -231,7 +231,7 @@ Aml *aml_to_integer(Aml *arg);
 Aml *aml_to_hexstring(Aml *src, Aml *dst);
 Aml *aml_to_buffer(Aml *src, Aml *dst);
 Aml *aml_store(Aml *val, Aml *target);
-Aml *aml_and(Aml *arg1, Aml *arg2);
+Aml *aml_and(Aml *arg1, Aml *arg2, Aml *dst);
 Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst);
 Aml *aml_lor(Aml *arg1, Aml *arg2);
 Aml *aml_shiftleft(Aml *arg1, Aml *count);
-- 
1.8.3.1

[Qemu-devel] [PATCH 22/74] acpi: extend aml_or() to accept target argument

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 4 ++--
 hw/arm/virt-acpi-build.c| 6 +++---
 hw/i386/acpi-build.c| 3 ++-
 include/hw/acpi/aml-build.h | 2 +-
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 8347299..4f62512 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -505,9 +505,9 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
 }
 
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
-Aml *aml_or(Aml *arg1, Aml *arg2)
+Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst)
 {
-return build_opcode_2arg_dst(0x7D /* OrOp */, arg1, arg2, NULL);
+return build_opcode_2arg_dst(0x7D /* OrOp */, arg1, arg2, dst);
 }
 
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLOr */
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 38ab844..1cc98f5 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -276,12 +276,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const 
MemMapEntry *memmap, int irq,
 aml_name("CTRL")));
 
 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1;
-aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
+aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
  aml_name("CDW1")));
 aml_append(ifctx, ifctx1);
 
 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL";
-aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
+aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
  aml_name("CDW1")));
 aml_append(ifctx, ifctx1);
 
@@ -290,7 +290,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry 
*memmap, int irq,
 aml_append(method, ifctx);
 
 elsectx = aml_else();
-aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
+aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
   aml_name("CDW1")));
 aml_append(elsectx, aml_return(aml_arg(3)));
 aml_append(method, elsectx);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a705e96..fd8ccfc 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -679,7 +679,8 @@ static Aml *build_prt(void)
 
 /* route[0] = 0x[slot] */
 aml_append(while_ctx,
-aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), 
aml_int(0x)),
+aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0x),
+ NULL),
   aml_index(route, aml_int(0;
 /* route[1] = pin & 3 */
 aml_append(while_ctx,
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 9dd8370..3be727e 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -232,7 +232,7 @@ Aml *aml_to_hexstring(Aml *src, Aml *dst);
 Aml *aml_to_buffer(Aml *src, Aml *dst);
 Aml *aml_store(Aml *val, Aml *target);
 Aml *aml_and(Aml *arg1, Aml *arg2);
-Aml *aml_or(Aml *arg1, Aml *arg2);
+Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst);
 Aml *aml_lor(Aml *arg1, Aml *arg2);
 Aml *aml_shiftleft(Aml *arg1, Aml *count);
 Aml *aml_shiftright(Aml *arg1, Aml *count, Aml *dst);
-- 
1.8.3.1

[Qemu-devel] [PATCH 25/74] pc: acpi: memhp: prepare context in SSDT for moving memhp DSDT code

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/Makefile.objs   |  2 +-
 hw/acpi/memory_hotplug_acpi_table.c | 40 +
 hw/i386/acpi-build.c|  3 +++
 include/hw/acpi/memory_hotplug.h|  4 
 4 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 hw/acpi/memory_hotplug_acpi_table.c

diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index 7d3230c..c04064e 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,7 +1,7 @@
 common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o
 common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o
 common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
-common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
+common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o 
memory_hotplug_acpi_table.o
 common-obj-$(CONFIG_ACPI) += acpi_interface.o
 common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
 common-obj-$(CONFIG_ACPI) += aml-build.o
diff --git a/hw/acpi/memory_hotplug_acpi_table.c 
b/hw/acpi/memory_hotplug_acpi_table.c
new file mode 100644
index 000..25bbf5e
--- /dev/null
+++ b/hw/acpi/memory_hotplug_acpi_table.c
@@ -0,0 +1,40 @@
+/*
+ * Memory hotplug AML code of DSDT ACPI table
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Igor Mammedov 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ */
+
+#include 
+#include "hw/acpi/memory_hotplug.h"
+#include "include/hw/acpi/pc-hotplug.h"
+#include "hw/boards.h"
+
+void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
+  uint16_t io_base, uint16_t io_len)
+{
+Aml *pci_scope;
+Aml *ctrl_dev;
+
+/* scope for memory hotplug controller device node */
+pci_scope = aml_scope("_SB.PCI0");
+ctrl_dev = aml_scope(stringify(MEMORY_HOTPLUG_DEVICE));
+{
+}
+aml_append(pci_scope, ctrl_dev);
+aml_append(ctx, pci_scope);
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bbd37e9..1b609e6 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -928,6 +928,9 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* Reserve space for header */
 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 
+build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
+ pm->mem_hp_io_len);
+
 /* Extra PCI root buses are implemented  only for i440fx */
 bus = find_i440fx();
 if (bus) {
diff --git a/include/hw/acpi/memory_hotplug.h b/include/hw/acpi/memory_hotplug.h
index 1342adb..b6e9f50 100644
--- a/include/hw/acpi/memory_hotplug.h
+++ b/include/hw/acpi/memory_hotplug.h
@@ -4,6 +4,7 @@
 #include "hw/qdev-core.h"
 #include "hw/acpi/acpi.h"
 #include "migration/vmstate.h"
+#include "hw/acpi/aml-build.h"
 
 /**
  * MemStatus:
@@ -45,4 +46,7 @@ extern const VMStateDescription vmstate_memory_hotplug;
vmstate_memory_hotplug, MemHotplugState)
 
 void acpi_memory_ospm_status(MemHotplugState *mem_st, ACPIOSTInfoList ***list);
+
+void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
+  uint16_t io_base, uint16_t io_len);
 #endif
-- 
1.8.3.1

[Qemu-devel] [PATCH 15/74] acpi: support serialized method

[Igor Mammedov]

From: Xiao Guangrong 

Add serialized method support so that explicit Mutex can be
avoided

Signed-off-by: Xiao Guangrong 
Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 17 +++--
 hw/arm/virt-acpi-build.c| 10 +-
 hw/i386/acpi-build.c| 41 +
 include/hw/acpi/aml-build.h |  8 +++-
 4 files changed, 48 insertions(+), 28 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index e36b546..5094826 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -741,11 +741,24 @@ Aml *aml_while(Aml *predicate)
 }
 
 /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
-Aml *aml_method(const char *name, int arg_count)
+Aml *aml_method(const char *name, int arg_count, AmlSerializeFlag sflag)
 {
 Aml *var = aml_bundle(0x14 /* MethodOp */, AML_PACKAGE);
+int methodflags;
+
+/*
+ * MethodFlags:
+ *   bit 0-2: ArgCount (0-7)
+ *   bit 3: SerializeFlag
+ * 0: NotSerialized
+ * 1: Serialized
+ *   bit 4-7: reserved (must be 0)
+ */
+assert(arg_count < 8);
+methodflags = arg_count | (sflag << 3);
+
 build_append_namestring(var->buf, "%s", name);
-build_append_byte(var->buf, arg_count); /* MethodFlags: ArgCount */
+build_append_byte(var->buf, methodflags); /* MethodFlags: ArgCount */
 return var;
 }
 
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3c2c5d6..38ab844 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -212,16 +212,16 @@ static void acpi_dsdt_add_pci(Aml *scope, const 
MemMapEntry *memmap, int irq,
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  AML_EXCLUSIVE, irq + i));
 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
-method = aml_method("_SRS", 1);
+method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
 aml_append(dev_gsi, method);
 aml_append(dev, dev_gsi);
 }
 
-method = aml_method("_CBA", 0);
+method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_return(aml_int(base_ecam)));
 aml_append(dev, method);
 
-method = aml_method("_CRS", 0);
+method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
 Aml *rbuf = aml_resource_template();
 aml_append(rbuf,
 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
@@ -254,7 +254,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry 
*memmap, int irq,
 /* Declare an _OSC (OS Control Handoff) method */
 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
-method = aml_method("_OSC", 4);
+method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
 aml_append(method,
 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 
@@ -296,7 +296,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry 
*memmap, int irq,
 aml_append(method, elsectx);
 aml_append(dev, method);
 
-method = aml_method("_DSM", 4);
+method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 
 /* PCI Firmware Specification 3.0
  * 4.6.1. _DSM for PCI Express Slot Information
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 8f7b95a..62afe5a 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -487,7 +487,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
 
 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
-notify_method = aml_method("DVNT", 2);
+notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
 }
 
 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
@@ -503,7 +503,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
-method = aml_method("_EJ0", 1);
+method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
 aml_append(method,
 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
 );
@@ -546,22 +546,22 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 s3d = 0;
 }
 
-method = aml_method("_S1D", 0);
+method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_return(aml_int(0)));
 aml_append(dev, method);
 
-method = aml_method("_S2D", 0);
+method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_return(aml_int(0)));
 aml_append(dev, method);
 
-method = aml_method("_S3D", 0);
+method = aml_metho

[Qemu-devel] [PATCH 20/74] acpi: add aml_to_buffer()

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 13 +
 include/hw/acpi/aml-build.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index c025801..4b1b496 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -449,6 +449,19 @@ Aml *aml_to_hexstring(Aml *src, Aml *dst)
 return var;
 }
 
+/* ACPI 2.0a: 17.2.4.4 Type 2 Opcodes Encoding: DefToBuffer */
+Aml *aml_to_buffer(Aml *src, Aml *dst)
+{
+Aml *var = aml_opcode(0x96 /* ToBufferOp */);
+aml_append(var, src);
+if (dst) {
+aml_append(var, dst);
+} else {
+build_append_byte(var->buf, 0x00 /* NullNameOp */);
+}
+return var;
+}
+
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefStore */
 Aml *aml_store(Aml *val, Aml *target)
 {
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 77bfe0c..04ef25e 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -211,6 +211,7 @@ Aml *aml_int(const uint64_t val);
 Aml *aml_arg(int pos);
 Aml *aml_to_integer(Aml *arg);
 Aml *aml_to_hexstring(Aml *src, Aml *dst);
+Aml *aml_to_buffer(Aml *src, Aml *dst);
 Aml *aml_store(Aml *val, Aml *target);
 Aml *aml_and(Aml *arg1, Aml *arg2);
 Aml *aml_or(Aml *arg1, Aml *arg2);
-- 
1.8.3.1

[Qemu-devel] [PATCH 21/74] acpi add aml_dma()

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 14 ++
 include/hw/acpi/aml-build.h | 20 
 2 files changed, 34 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 4b1b496..8347299 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1183,6 +1183,20 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed 
min_fixed,
  addr_trans, len, flags);
 }
 
+/* ACPI 1.0b: 6.4.2.2 DMA Format/6.4.2.2.1 ASL Macro for DMA Descriptor */
+Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz,
+ uint8_t channel)
+{
+Aml *var = aml_alloc();
+uint8_t flags = sz | bm << 2 | typ << 5;
+
+assert(channel < 8);
+build_append_byte(var->buf, 0x2A);/* Byte 0: DMA Descriptor */
+build_append_byte(var->buf, 1U << channel); /* Byte 1: _DMA - DmaChannel */
+build_append_byte(var->buf, flags);   /* Byte 2 */
+return var;
+}
+
 /* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefSleep */
 Aml *aml_sleep(uint64_t msec)
 {
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 04ef25e..9dd8370 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -35,6 +35,24 @@ struct Aml {
 typedef struct Aml Aml;
 
 typedef enum {
+AML_COMPATIBILITY = 0,
+AML_TYPEA = 1,
+AML_TYPEB = 2,
+AML_TYPEF = 3,
+} AmlDmaType;
+
+typedef enum {
+AML_NOTBUSMASTER = 0,
+AML_BUSMASTER = 1,
+} AmlDmaBusMaster;
+
+typedef enum {
+AML_TRANSFER8 = 0,
+AML_TRANSFER8_16 = 1,
+AML_TRANSFER16 = 2,
+} AmlTransferSize;
+
+typedef enum {
 AML_DECODE10 = 0,
 AML_DECODE16 = 1,
 } AmlIODecode;
@@ -278,6 +296,8 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
   uint64_t addr_gran, uint64_t addr_min,
   uint64_t addr_max, uint64_t addr_trans,
   uint64_t len);
+Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz,
+ uint8_t channel);
 Aml *aml_sleep(uint64_t msec);
 
 /* Block AML object primitives */
-- 
1.8.3.1

[Qemu-devel] [PATCH 10/74] acpi: add aml_call0() helper

[Igor Mammedov]

it will help to call a method with 0 arguments

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 8 
 include/hw/acpi/aml-build.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index ee34771..50587de 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -540,6 +540,14 @@ Aml *aml_notify(Aml *arg1, Aml *arg2)
 }
 
 /* helper to call method with 1 argument */
+Aml *aml_call0(const char *method)
+{
+Aml *var = aml_alloc();
+build_append_namestring(var->buf, "%s", method);
+return var;
+}
+
+/* helper to call method with 1 argument */
 Aml *aml_call1(const char *method, Aml *arg1)
 {
 Aml *var = aml_alloc();
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 9761438..117ef46 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -210,6 +210,7 @@ Aml *aml_increment(Aml *arg);
 Aml *aml_decrement(Aml *arg);
 Aml *aml_index(Aml *arg1, Aml *idx);
 Aml *aml_notify(Aml *arg1, Aml *arg2);
+Aml *aml_call0(const char *method);
 Aml *aml_call1(const char *method, Aml *arg1);
 Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
 Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
-- 
1.8.3.1

[Qemu-devel] [PATCH 19/74] acpi: add aml_to_hexstring()

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c | 13 +
 include/hw/acpi/aml-build.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 7500474..c025801 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -436,6 +436,19 @@ Aml *aml_to_integer(Aml *arg)
 return var;
 }
 
+/* ACPI 2.0a: 17.2.4.4 Type 2 Opcodes Encoding: DefToHexString */
+Aml *aml_to_hexstring(Aml *src, Aml *dst)
+{
+Aml *var = aml_opcode(0x98 /* ToHexStringOp */);
+aml_append(var, src);
+if (dst) {
+aml_append(var, dst);
+} else {
+build_append_byte(var->buf, 0x00 /* NullNameOp */);
+}
+return var;
+}
+
 /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefStore */
 Aml *aml_store(Aml *val, Aml *target)
 {
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 679812b..77bfe0c 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -210,6 +210,7 @@ Aml *aml_return(Aml *val);
 Aml *aml_int(const uint64_t val);
 Aml *aml_arg(int pos);
 Aml *aml_to_integer(Aml *arg);
+Aml *aml_to_hexstring(Aml *src, Aml *dst);
 Aml *aml_store(Aml *val, Aml *target);
 Aml *aml_and(Aml *arg1, Aml *arg2);
 Aml *aml_or(Aml *arg1, Aml *arg2);
-- 
1.8.3.1

[Qemu-devel] [PATCH 18/74] acpi: extend aml_field() to support LockRule

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 hw/acpi/aml-build.c |  5 -
 hw/i386/acpi-build.c| 10 +-
 include/hw/acpi/aml-build.h |  8 +++-
 3 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index b22e7da..7500474 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -860,11 +860,14 @@ Aml *aml_reserved_field(unsigned length)
 }
 
 /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefField */
-Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule)
+Aml *aml_field(const char *name, AmlAccessType type, AmlLockRule lock,
+   AmlUpdateRule rule)
 {
 Aml *var = aml_bundle(0x81 /* FieldOp */, AML_EXT_PACKAGE);
 uint8_t flags = rule << 5 | type;
 
+flags |= lock << 4; /* LockRule at 4 bit offset */
+
 build_append_namestring(var->buf, "%s", name);
 build_append_byte(var->buf, flags);
 return var;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 62afe5a..a705e96 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1105,7 +1105,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 
 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
   misc->pvpanic_port, 1));
-field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE);
+field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 aml_append(field, aml_named_field("PEPT", 8));
 aml_append(dev, field);
 
@@ -1145,7 +1145,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 /* declare CPU hotplug MMIO region and PRS field to access it */
 aml_append(sb_scope, aml_operation_region(
 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
-field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE);
+field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 aml_append(field, aml_named_field("PRS", 256));
 aml_append(sb_scope, field);
 
@@ -1220,7 +1220,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 );
 
 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
-  AML_PRESERVE);
+  AML_NOLOCK, AML_PRESERVE);
 aml_append(field, /* read only */
 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
 aml_append(field, /* read only */
@@ -1234,7 +1234,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 aml_append(scope, field);
 
 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
-  AML_WRITE_AS_ZEROS);
+  AML_NOLOCK, AML_WRITE_AS_ZEROS);
 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
 aml_append(field, /* 1 if enabled, read only */
 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
@@ -1250,7 +1250,7 @@ build_ssdt(GArray *table_data, GArray *linker,
 aml_append(scope, field);
 
 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
-  AML_PRESERVE);
+  AML_NOLOCK, AML_PRESERVE);
 aml_append(field, /* DIMM selector, write only */
 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
 aml_append(field, /* _OST event code, write only */
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 238a9dc..679812b 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -49,6 +49,11 @@ typedef enum {
 } AmlAccessType;
 
 typedef enum {
+AML_NOLOCK = 0,
+AML_LOCK = 1,
+} AmlLockRule;
+
+typedef enum {
 AML_PRESERVE = 0,
 AML_WRITE_AS_ONES = 1,
 AML_WRITE_AS_ZEROS = 2,
@@ -283,7 +288,8 @@ Aml *aml_while(Aml *predicate);
 Aml *aml_package(uint8_t num_elements);
 Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
 Aml *aml_resource_template(void);
-Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
+Aml *aml_field(const char *name, AmlAccessType type, AmlLockRule lock,
+   AmlUpdateRule rule);
 Aml *aml_mutex(const char *name, uint8_t sync_level);
 Aml *aml_acquire(Aml *mutex, uint16_t timeout);
 Aml *aml_release(Aml *mutex);
-- 
1.8.3.1