[Qemu-devel] [PATCH] target/xtensa: support input from chardev console
Complete xtensa-semi chardev console implementation: allow reading input
characters from file descriptor 0 and call sys_select_one simcall on it.
Signed-off-by: Max Filippov
---
target/xtensa/xtensa-semi.c | 55 ++---
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index 7aa1d1357bda..f3c23f8625c2 100644
--- a/target/xtensa/xtensa-semi.c
+++ b/target/xtensa/xtensa-semi.c
@@ -34,8 +34,6 @@
#include "qemu/log.h"
#include "sysemu/sysemu.h"
-static CharBackend *xtensa_sim_console;
-
enum {
TARGET_SYS_exit = 1,
TARGET_SYS_read = 3,
@@ -153,12 +151,45 @@ static uint32_t errno_h2g(int host_errno)
}
}
+typedef struct SimInputBuffer {
+char buffer[16];
+size_t offset;
+} SimInputBuffer;
+
+static CharBackend *xtensa_sim_console;
+static SimInputBuffer sim_input_buffer;
+
+static IOCanReadHandler xtensa_sim_console_can_read;
+static int xtensa_sim_console_can_read(void *opaque)
+{
+SimInputBuffer *p = opaque;
+
+return sizeof(p->buffer) - p->offset;
+}
+
+static IOReadHandler xtensa_sim_console_read;
+static void xtensa_sim_console_read(void *opaque, const uint8_t *buf, int size)
+{
+SimInputBuffer *p = opaque;
+size_t copy = sizeof(p->buffer) - p->offset;
+
+if (size < copy) {
+copy = size;
+}
+memcpy(p->buffer + p->offset, buf, copy);
+p->offset += copy;
+}
+
void xtensa_sim_open_console(Chardev *chr)
{
static CharBackend console;
qemu_chr_fe_init(, chr, _abort);
-qemu_chr_fe_set_handlers(, NULL, NULL, NULL, NULL, NULL, NULL,
true);
+qemu_chr_fe_set_handlers(,
+ xtensa_sim_console_can_read,
+ xtensa_sim_console_read,
+ NULL, NULL, _input_buffer,
+ NULL, true);
xtensa_sim_console =
}
@@ -200,6 +231,22 @@ void HELPER(simcall)(CPUXtensaState *env)
io_done = qemu_chr_fe_write_all(xtensa_sim_console,
buf, io_sz);
regs[3] = errno_h2g(errno);
+} else if (!is_write && fd == 0) {
+if (sim_input_buffer.offset) {
+io_done = sim_input_buffer.offset;
+if (io_sz < io_done) {
+io_done = io_sz;
+}
+memcpy(buf, sim_input_buffer.buffer, io_done);
+memmove(sim_input_buffer.buffer,
+sim_input_buffer.buffer + io_done,
+sim_input_buffer.offset - io_done);
+sim_input_buffer.offset -= io_done;
+qemu_chr_fe_accept_input(xtensa_sim_console);
+} else {
+io_done = -1;
+regs[3] = TARGET_EAGAIN;
+}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s fd %d is not supported with
chardev console\n",
@@ -295,6 +342,8 @@ void HELPER(simcall)(CPUXtensaState *env)
if (fd < 3 && xtensa_sim_console) {
if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
regs[2] = 1;
+} else if (fd == 0 && rq == SELECT_ONE_READ) {
+regs[2] = sim_input_buffer.offset > 0;
} else {
regs[2] = 0;
}
--
2.11.0
Re: [Qemu-devel] [PATCH] linux-user: write(fd, NULL, 0) parity with linux's treatment of same
On Sat, Sep 8, 2018 at 6:04 PM Tony Garnock-Jones
wrote:
>
> Bring linux-user write(2) handling into line with linux for the case
> of a 0-byte write with a NULL buffer. Based on a patch originally
> written by Zhuowei Zhang.
>
> Addresses https://bugs.launchpad.net/qemu/+bug/1716292.
>
> From Zhuowei Zhang's patch
> (https://lists.gnu.org/archive/html/qemu-devel/2017-09/msg08073.html):
>
> Linux returns success for the special case of calling write with a
> zero-length NULL buffer: compiling and running
>
> int main() {
>ssize_t ret = write(STDOUT_FILENO, NULL, 0);
>fprintf(stderr, "write returned %ld\n", ret);
>return 0;
> }
>
> gives "write returned 0" when run directly, but "write returned
> -1" in QEMU.
>
> This commit checks for this situation and returns success if
> found.
>
> Subsequent discussion raised the following questions (and my answers):
>
> - Q. Should TARGET_NR_read pass through to safe_read in this
> situation too?
>A. I'm wary of changing unrelated code to the specific problem I'm
> addressing. TARGET_NR_read is already consistent with Linux for
> this case.
>
> - Q. Do pread64/pwrite64 need to be changed similarly?
>A. Experiment suggests not: both linux and linux-user yield -1 for
> NULL 0-length reads/writes.
>
> Signed-off-by: Tony Garnock-Jones
Reviewed-by: Philippe Mathieu-Daudé
> ---
> linux-user/syscall.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 850b72a0c7..8f46540534 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8168,6 +8168,9 @@ static abi_long do_syscall1(void *cpu_env, int num,
> abi_long arg1,
> }
> return ret;
> case TARGET_NR_write:
> +if (arg2 == 0 && arg3 == 0) {
> +return get_errno(safe_write(arg1, 0, 0));
> +}
> if (!(p = lock_user(VERIFY_READ, arg2, arg3, 1)))
> return -TARGET_EFAULT;
> if (fd_trans_target_to_host_data(arg1)) {
> --
> 2.18.0
>
>
> [University of Glasgow: The Times Scottish University of the Year 2018]
>
[Qemu-devel] [PATCH 0/2] mips: Allow more 'Chip specific instructions' flags
Hi, After noticing Fredrik patch [1] clashes with an ongoing work, I shared my concerns after the current limitations of CPUMIPSState::insn_flags, having 1 bit left to store more 'Chip specific instructions'. The first patch drop this restriction, the second simply add definitions for 2 Toshiba cores. Regards, Phil. [1] http://lists.nongnu.org/archive/html/qemu-devel/2018-07/msg01978.html [2] http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00901.html Philippe Mathieu-Daudé (2): target/mips: Increase the 'supported instructions' flags holder size target/mips: Add entries for the Toshiba's R3900 and R5900 cores target/mips/cpu.h | 2 +- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 2 ++ target/mips/translate.c | 4 ++-- 4 files changed, 6 insertions(+), 4 deletions(-) -- 2.19.0.rc2
[Qemu-devel] [PATCH 1/2] target/mips: Increase the 'supported instructions' flags holder size
Currently this holder is limited to at most 32 flags on
a 32-bit architecture, which lets an unique bit available
for another 'chip specific instructions' flag.
Relax this limit using a 64-bit integer.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 2 +-
target/mips/internal.h | 2 +-
target/mips/translate.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d191c..f2a5031fd2 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -614,7 +614,7 @@ struct CPUMIPSState {
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
-int insn_flags; /* Supported instruction set */
+uint64_t insn_flags; /* Supported instruction set */
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f8e6..bfe83ee613 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -59,7 +59,7 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask;
-int insn_flags;
+uint64_t insn_flags;
enum mips_mmu_types mmu_type;
};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb911..3b4e9ebae9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1870,7 +1870,7 @@ static inline void check_dspr2(DisasContext *ctx)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(DisasContext *ctx, int flags)
+static inline void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -1880,7 +1880,7 @@ static inline void check_insn(DisasContext *ctx, int
flags)
/* This code generates a "reserved instruction" exception if the
CPU has corresponding flag set which indicates that the instruction
has been removed. */
-static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
+static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
generate_exception_end(ctx, EXCP_RI);
--
2.19.0.rc2
[Qemu-devel] [PATCH 2/2] target/mips: Add entries for the Toshiba's R3900 and R5900 cores
Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c8e99791ad..9875bdac82 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -56,6 +56,8 @@ #defineINSN_LOONGSON2E 0x2000 #defineINSN_LOONGSON2F 0x4000 #defineINSN_VR54XX 0x8000 +#define INSN_R3900 0x1ULL +#define INSN_R5900 0x2ULL /* MIPS CPU defines. */ #defineCPU_MIPS1 (ISA_MIPS1) -- 2.19.0.rc2
[Qemu-devel] [PATCH] linux-user: write(fd, NULL, 0) parity with linux's treatment of same
Bring linux-user write(2) handling into line with linux for the case
of a 0-byte write with a NULL buffer. Based on a patch originally
written by Zhuowei Zhang.
Addresses https://bugs.launchpad.net/qemu/+bug/1716292.
>From Zhuowei Zhang's patch
>(https://lists.gnu.org/archive/html/qemu-devel/2017-09/msg08073.html):
Linux returns success for the special case of calling write with a
zero-length NULL buffer: compiling and running
int main() {
ssize_t ret = write(STDOUT_FILENO, NULL, 0);
fprintf(stderr, "write returned %ld\n", ret);
return 0;
}
gives "write returned 0" when run directly, but "write returned
-1" in QEMU.
This commit checks for this situation and returns success if
found.
Subsequent discussion raised the following questions (and my answers):
- Q. Should TARGET_NR_read pass through to safe_read in this
situation too?
A. I'm wary of changing unrelated code to the specific problem I'm
addressing. TARGET_NR_read is already consistent with Linux for
this case.
- Q. Do pread64/pwrite64 need to be changed similarly?
A. Experiment suggests not: both linux and linux-user yield -1 for
NULL 0-length reads/writes.
Signed-off-by: Tony Garnock-Jones
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 850b72a0c7..8f46540534 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8168,6 +8168,9 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
}
return ret;
case TARGET_NR_write:
+if (arg2 == 0 && arg3 == 0) {
+return get_errno(safe_write(arg1, 0, 0));
+}
if (!(p = lock_user(VERIFY_READ, arg2, arg3, 1)))
return -TARGET_EFAULT;
if (fd_trans_target_to_host_data(arg1)) {
--
2.18.0
[University of Glasgow: The Times Scottish University of the Year 2018]
[Qemu-devel] [PATCH v2 0/2] softfloat tests based on berkeley's testfloat
A few fixes since yesterday's v1: https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg00884.html - Convert copy_qemu_to_soft80 to qemu_to_soft80, just like the other conversion functions - Set fp-test as the program name as reported by itself - Fix Makefile to include .d files so that dependencies are properly tracked - Update commit log Grab this from: https://github.com/cota/qemu/tree/fp-test-v2 Thanks, Emilio
[Qemu-devel] [PATCH v2 2/2] tests: add floating point tests
By leveraging berkeley's softfloat and testfloat. fp-test.c is derived from testfloat's testsoftfloat.c. To ease the tracking of upstream changes to the latter file, fp-test.c keeps the original camel-case variable naming, and includes most new code via wrap.inc.c. Most changes to the original code are simple style changes, although a couple of not-so-subtle modifications have been made (noted with XXX in the code), namely: - We do not test ROUND_ODD, since not all of our primitives support it (e.g. fp16) - Do not test !exact in round-to-integer, since it is not implemented in QEMU (this flag was added to softfloat v3). Signed-off-by: Emilio G. Cota --- configure |2 + tests/fp/platform.h| 41 ++ tests/fp/fp-test.c | 1052 tests/fp/wrap.inc.c| 600 +++ tests/Makefile.include |3 + tests/fp/.gitignore|1 + tests/fp/Makefile | 591 ++ 7 files changed, 2290 insertions(+) create mode 100644 tests/fp/platform.h create mode 100644 tests/fp/fp-test.c create mode 100644 tests/fp/wrap.inc.c create mode 100644 tests/fp/.gitignore create mode 100644 tests/fp/Makefile diff --git a/configure b/configure index 58862d2ae8..b02da8c0b4 100755 --- a/configure +++ b/configure @@ -7451,12 +7451,14 @@ fi # build tree in object directory in case the source is not in the current directory DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos tests/qapi-schema tests/tcg/xtensa tests/qemu-iotests tests/vm" +DIRS="$DIRS tests/fp" DIRS="$DIRS docs docs/interop fsdev scsi" DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas pc-bios/s390-ccw" DIRS="$DIRS roms/seabios roms/vgabios" FILES="Makefile tests/tcg/Makefile qdict-test-data.txt" FILES="$FILES tests/tcg/cris/Makefile tests/tcg/cris/.gdbinit" FILES="$FILES tests/tcg/lm32/Makefile tests/tcg/xtensa/Makefile po/Makefile" +FILES="$FILES tests/fp/Makefile" FILES="$FILES pc-bios/optionrom/Makefile pc-bios/keymaps" FILES="$FILES pc-bios/spapr-rtas/Makefile" FILES="$FILES pc-bios/s390-ccw/Makefile" diff --git a/tests/fp/platform.h b/tests/fp/platform.h new file mode 100644 index 00..80af8a94b6 --- /dev/null +++ b/tests/fp/platform.h @@ -0,0 +1,41 @@ +#ifndef QEMU_TESTFLOAT_PLATFORM_H +#define QEMU_TESTFLOAT_PLATFORM_H +/* + * Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of + * California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions, and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions, and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the University nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE + * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "config-host.h" + +#ifndef HOST_WORDS_BIGENDIAN +#define LITTLEENDIAN 1 +/* otherwise do not define it */ +#endif + +#define INLINE static inline + +#endif /* QEMU_TESTFLOAT_PLATFORM_H */ diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c new file mode 100644 index 00..43da4e43c5 --- /dev/null +++ b/tests/fp/fp-test.c @@ -0,0 +1,1052 @@ +/* + * fp-test.c - test QEMU's softfloat implementation using Berkeley's Testfloat + * + * Derived from testfloat/source/testsoftfloat.c. + * + * Copyright (C) 2018, Emilio G. Cota + * Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the + * University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions, and the following disclaimer. + * + * 2.
[Qemu-devel] [PATCH v2 1/2] gitmodules: add berkeley's softfloat + testfloat version 3
These are BSD-licensed so we can add them as submodules. Signed-off-by: Emilio G. Cota --- .gitmodules | 6 ++ tests/fp/berkeley-softfloat-3 | 1 + tests/fp/berkeley-testfloat-3 | 1 + 3 files changed, 8 insertions(+) create mode 16 tests/fp/berkeley-softfloat-3 create mode 16 tests/fp/berkeley-testfloat-3 diff --git a/.gitmodules b/.gitmodules index d108478e0a..165c7c5286 100644 --- a/.gitmodules +++ b/.gitmodules @@ -43,3 +43,9 @@ [submodule "roms/u-boot-sam460ex"] path = roms/u-boot-sam460ex url = git://git.qemu.org/u-boot-sam460ex.git +[submodule "tests/fp/testfloat"] + path = tests/fp/berkeley-testfloat-3 + url = git://github.com/ucb-bar/berkeley-testfloat-3 +[submodule "tests/fp/berkeley-softfloat-3"] + path = tests/fp/berkeley-softfloat-3 + url = git://github.com/ucb-bar/berkeley-softfloat-3 diff --git a/tests/fp/berkeley-softfloat-3 b/tests/fp/berkeley-softfloat-3 new file mode 16 index 00..b64af41c32 --- /dev/null +++ b/tests/fp/berkeley-softfloat-3 @@ -0,0 +1 @@ +Subproject commit b64af41c3276f97f0e181920400ee056b9c88037 diff --git a/tests/fp/berkeley-testfloat-3 b/tests/fp/berkeley-testfloat-3 new file mode 16 index 00..06b20075dd --- /dev/null +++ b/tests/fp/berkeley-testfloat-3 @@ -0,0 +1 @@ +Subproject commit 06b20075dd3c1a5d0dd007a93643282832221612 -- 2.17.1
Re: [Qemu-devel] [PATCH 0/2] softfloat tests based on berkeley's testfloat
On Fri, Sep 07, 2018 at 18:07:29 -0400, Emilio G. Cota wrote: > You can pull this tree from: > https://github.com/cota/qemu/tree/fp-test I just sent a v2; please review that one instead. Thanks, Emilio
Re: [Qemu-devel] [PATCH v3] hw/ppc: on 40p machine, change default firmware to OpenBIOS
Le 08/09/2018 à 18:20, Stefan Weil a écrit :
Am 08.09.2018 um 18:14 schrieb Hervé Poussineau:
[...]
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f123b15e3e..f865822e32 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -75,12 +75,12 @@ typedef struct testdef {
static testdef_t tests[] = {
{ "alpha", "clipper", "", "PCI:" },
{ "ppc", "ppce500", "", "U-Boot" },
-{ "ppc", "40p", "-boot d", "Booting from device d" },
+{ "ppc", "40p", "-vga none -boot d", "Trying cd:," },
{ "ppc", "g3beige", "", "PowerPC,750" },
{ "ppc", "mac99", "", "PowerPC,G4" },
{ "ppc", "sam460ex", "-m 256", "DRAM: 256 MiB" },
{ "ppc64", "ppce500", "", "U-Boot" },
-{ "ppc64", "40p", "-m 192", "Memory size: 192 MB" },
+{ "ppc64", "40p", "-m 192", "Memory: 192M" },
I suggest using "Memory: 192 MiB" (like in the code for sam460ex above).
No, because OpenBIOS doesn't print the "iB" letters...
Hervé
Re: [Qemu-devel] [PATCH v3] hw/ppc: on 40p machine, change default firmware to OpenBIOS
Am 08.09.2018 um 18:14 schrieb Hervé Poussineau:
[...]
> diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
> index f123b15e3e..f865822e32 100644
> --- a/tests/boot-serial-test.c
> +++ b/tests/boot-serial-test.c
> @@ -75,12 +75,12 @@ typedef struct testdef {
> static testdef_t tests[] = {
> { "alpha", "clipper", "", "PCI:" },
> { "ppc", "ppce500", "", "U-Boot" },
> -{ "ppc", "40p", "-boot d", "Booting from device d" },
> +{ "ppc", "40p", "-vga none -boot d", "Trying cd:," },
> { "ppc", "g3beige", "", "PowerPC,750" },
> { "ppc", "mac99", "", "PowerPC,G4" },
> { "ppc", "sam460ex", "-m 256", "DRAM: 256 MiB" },
> { "ppc64", "ppce500", "", "U-Boot" },
> -{ "ppc64", "40p", "-m 192", "Memory size: 192 MB" },
> +{ "ppc64", "40p", "-m 192", "Memory: 192M" },
I suggest using "Memory: 192 MiB" (like in the code for sam460ex above).
Regards,
Stefan Weil
[Qemu-devel] [PATCH v3] hw/ppc: on 40p machine, change default firmware to OpenBIOS
OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff
Use it, instead of relying on an unmaintained and very limited firmware.
Signed-off-by: Hervé Poussineau
---
Changes v2->v3:
- rebased on dgibson/ppc-for-3.1
Changes v1->v2:
- rebased on master
- fixed tests
hw/ppc/prep.c| 2 +-
tests/boot-serial-test.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 162b27a3b8..baca1d7c04 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -651,7 +651,7 @@ static void ibm_40p_init(MachineState *machine)
/* PCI host */
dev = qdev_create(NULL, "raven-pcihost");
if (!bios_name) {
-bios_name = BIOS_FILENAME;
+bios_name = "openbios-ppc";
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f123b15e3e..f865822e32 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -75,12 +75,12 @@ typedef struct testdef {
static testdef_t tests[] = {
{ "alpha", "clipper", "", "PCI:" },
{ "ppc", "ppce500", "", "U-Boot" },
-{ "ppc", "40p", "-boot d", "Booting from device d" },
+{ "ppc", "40p", "-vga none -boot d", "Trying cd:," },
{ "ppc", "g3beige", "", "PowerPC,750" },
{ "ppc", "mac99", "", "PowerPC,G4" },
{ "ppc", "sam460ex", "-m 256", "DRAM: 256 MiB" },
{ "ppc64", "ppce500", "", "U-Boot" },
-{ "ppc64", "40p", "-m 192", "Memory size: 192 MB" },
+{ "ppc64", "40p", "-m 192", "Memory: 192M" },
{ "ppc64", "mac99", "", "PowerPC,970FX" },
{ "ppc64", "pseries", "", "Open Firmware" },
{ "ppc64", "powernv", "-cpu POWER8", "OPAL" },
--
2.11.0
Re: [Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing
Le 08/09/2018 à 11:08, Mark Cave-Ayland a écrit : According to the PReP specification section 6.1.6 "System Interrupt Assignments", all PCI interrupts are routed via IRQ 15. In the case of the 40p machine this isn't quite true in that it has a routing quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and NetBSD compare the model name presented by the firmware to "IBM PPS Model 6015", and if it matches will active this quirk. There is also a slight issue in that whilst the legacy PReP machine is still present in the codebase, the old IRQ routing must still be preserved. This is done by introducing a new "is-legacy-prep" qdev property to the raven PCI host bridge which preserves the old routing for -M prep until that code is finally removed. Reviewed-by: Hervé Poussineau Tested-by: Hervé Poussineau
Re: [Qemu-devel] [PATCH] block/file-posix: fix the wrong result of find_allocation() in macOS.
On 8 September 2018 at 15:15, Yan-Jie Wang wrote: > In macOS, lseek with SEEK_DATA behaves differently. > It seeks to the next data region even though offset is in the middle of > a data region. In addition, there may be many data regions without any > hole among them, like this: |---Data---|---Data---| > > Because of this, qemu-img convert with raw images as input may create > corrupted images in macOS especially for large files, and qemu-img > map may also report wrong things. This patch fixes this undesired > behaviors. Hi. I have two general questions here: (1) is this behaviour of SEEK_DATA specific to macOS, or do the other BSDs (FreeBSD, OpenBSD, NetBSD) also have it ? (2) is there a way to determine which flavour of SEEK_DATA we have as a configure-time test rather than having to hardcode an OS-specific #ifdef ? thanks -- PMM
[Qemu-devel] [PATCH] block/file-posix: fix the wrong result of find_allocation() in macOS.
In macOS, lseek with SEEK_DATA behaves differently.
It seeks to the next data region even though offset is in the middle of
a data region. In addition, there may be many data regions without any
hole among them, like this: |---Data---|---Data---|
Because of this, qemu-img convert with raw images as input may create
corrupted images in macOS especially for large files, and qemu-img
map may also report wrong things. This patch fixes this undesired
behaviors.
Signed-off-by: Yan-Jie Wang
---
block/file-posix.c | 59 ++
1 file changed, 59 insertions(+)
diff --git a/block/file-posix.c b/block/file-posix.c
index fe83cbf0eb..5c208580e6 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -2325,6 +2325,7 @@ static int find_allocation(BlockDriverState *bs, off_t
start,
BDRVRawState *s = bs->opaque;
off_t offs;
+#if !(defined(__APPLE__) && defined(__MACH__))
/*
* SEEK_DATA cases:
* D1. offs == start: start is in data
@@ -2395,6 +2396,64 @@ static int find_allocation(BlockDriverState *bs, off_t
start,
*hole = offs;
return 0;
}
+#else
+/*
+ * In macOS, lseek with SEEK_DATA seeks to the next data region
+ * even though the offset is in the middle of a data region.
+ * In addition, there may be many data regions without any holes among
+ * them, like this: |Data|Data|
+ *
+ * Although the behavior of lseek with SEEK_DATA is different in macOS,
+ * the behavior of lseek with SEEK_HOLE in macOS is the same as the one in
+ * Linux.
+ *
+ * Therefore, the cases D1, D2 and H2 are changed to the followings
+ * for macOS:
+ * D1. offs == start: start is at the beginning of a data region.
+ * D2. offs > start: either start is in a hole, next data at offs
+ * or start is in the middle of a data region,
+ * next data at offs.
+ * H2. offs > start: start is in data, next hole at offs
+ */
+
+offs = lseek(s->fd, start, SEEK_HOLE);
+if (offs < 0) {
+return -errno; /* H3 or H4 */
+}
+
+if (offs < start) {
+/* This is not a valid return by lseek(). We are safe to just return
+ * -EIO in this case, and we'll treat it like D4. */
+return -EIO;
+}
+
+if (offs > start) {
+/* H2: start is in data, next hole at offs */
+*data = start;
+*hole = offs;
+return 0;
+}
+
+/* H1: start is in a hole */
+offs = lseek(s->fd, start, SEEK_DATA);
+
+if (offs < 0) {
+return -errno; /* H1 and (D3 or D4) */
+}
+
+if (offs < start) {
+/* This is not a valid return by lseek(). We are safe to just return
+ * -EIO in this case, and we'll treat it like D4. */
+return -EIO;
+}
+
+if (offs > start) {
+/* H1 and D2: start is in a hole, next data at offs */
+*hole = start;
+*data = offs;
+return 0;
+}
+#endif
/* D1 and H1 */
return -EBUSY;
--
2.18.0
Re: [Qemu-devel] [PATCH v3] target/mips: Support R5900 GCC programs in user mode
Hi Aleksandar,
> Please:
>
> - rebase your changes to the latest QEMU code
Sure. V2 applied to 3.0.0 and this v3 applies to HEAD (commit 19b599f7664b).
> - organize the changes in the form of patch series
What kind of granularity do you have in mind? The patch is quite small with
79 insertions and 1 deletion in total.
> - provide links to or attach relevant documentation
The most relevant manual is probably Toshiba TX System RISC TX79 Core
Architecture:
http://www.lukasz.dk/files/tx79architecture.pdf
> - in cover letter, outline what is needed for full QEMU support of the cpu
> in question
The primary purpose of this patch is to support programs compiled by GCC for
the R5900 target. This enables QEMU to run R5900 Linux distributions, for
example Gentoo. In particular, this avoids issues with cross compilation.
R5900 hardware is typically limited to 32 MiB of RAM, which is insufficient
for running GCC in many cases.
> - describe testing and verification
This patch has been tested with Gentoo compiled for R5900, including native
compilation of several packages under QEMU. During testing of 2.12.50 I
discovered two problems which I reported and I believe are unrelated to the
patch itself:
The error
qemu: Unsupported syscall: 4352 (seccomp)
was reported during Gentoo package installations, and QEMU crashed with
qemu-mipsel: qemu/accel/tcg/cpu-exec.c:634: cpu_loop_exec_tb: Assertion
`use_icount' failed.
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
when compiling Perl under Gentoo. That crash seems to be related to the bug
https://bugs.launchpad.net/qemu/+bug/1768246
for SH4, which appears to have a fix for SH4 in
commit 5b38d0264064055255db991e29d938491f9e8a32
Author: Laurent Vivier
Date: Sat Aug 11 10:23:28 2018 +0200
sh4: fix use_icount with linux-user
This fixes java in a linux-user chroot:
$ java --version
qemu-sh4: .../accel/tcg/cpu-exec.c:634: cpu_loop_exec_tb: Assertion
`use_icount' failed.
qemu: uncaught target signal 6 (Aborted) - core dumped
Aborted (core dumped)
In gen_conditional_jump() in the GUSA_EXCLUSIVE part, we must reset
base.is_jmp to DISAS_NEXT after the gen_goto_tb() as it is done in
gen_delayed_conditional_jump() after the gen_jump().
Bug: https://bugs.launchpad.net/qemu/+bug/1768246
Fixes: 4834871bc95b67343248100e2a75ae0d287bc08b
("target/sh4: Convert to DisasJumpType")
Reported-by: John Paul Adrian Glaubitz
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Aurelien Jarno
Message-Id: <20180811082328.11268-1-laur...@vivier.eu>
> - remove the unclear word 'initial' from the title
Sure.
> - outline your plan for providing full support - can you commit enough
> resources to do the job in a reasonable timeframe?
For its intended purpose, to support R5900 GCC programs in user mode, I
believe this patch is sufficiently complete as it stands.
> Otherwise, I am generally happy with your patch.
Good!
Fredrik
Signed-off-by: Fredrik Noring
---
linux-user/mips/target_elf.h |3 ++
target/mips/mips-defs.h |2 +
target/mips/translate.c | 31 ++-
target/mips/translate_init.inc.c | 44 +++
4 files changed, 79 insertions(+), 1 deletion(-)
--- a/linux-user/mips/target_elf.h
+++ b/linux-user/mips/target_elf.h
@@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
return "mips32r6-generic";
}
+if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
+return "R5900";
+}
return "24Kf";
}
#endif
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -53,6 +53,7 @@
#define ASE_MSA 0x0100
/* Chip specific instructions. */
+#defineINSN_R5900 0x1000
#defineINSN_LOONGSON2E 0x2000
#defineINSN_LOONGSON2F 0x4000
#defineINSN_VR54XX 0x8000
@@ -63,6 +64,7 @@
#defineCPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#defineCPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#defineCPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
+#defineCPU_R5900 (CPU_MIPS4 | INSN_R5900)
#defineCPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#defineCPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3768,6 +3768,31 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
+static void gen_mul_r5900 (DisasContext *ctx, uint32_t opc,
+int rd, int rs, int rt)
+{
+TCGv t0 = tcg_temp_new();
+TCGv t1 = tcg_temp_new();
+
+gen_load_gpr(t0, rs);
+gen_load_gpr(t1, rt);
+
+switch (opc) {
+case OPC_MULT:
+
[Qemu-devel] [PATCH] clean up callback when del virtqueue
Before, we did not clear callback like handle_output when delete
the virtqueue which may result be segmentfault.
The scene is as follows:
1. Start a vm with multiqueue vhost-net,
2. then we write VIRTIO_PCI_GUEST_FEATURES in PCI configuration to
triger multiqueue disable in this vm which will delete the virtqueue.
In this step, the tx_bh is deleted but the callback virtio_net_handle_tx_bh
still exist.
3. Finally, we write VIRTIO_PCI_QUEUE_NOTIFY in PCI configuration to
notify the deleted virtqueue. In this way, virtio_net_handle_tx_bh
will be called and qemu will be crashed.
Although the way described above is uncommon, we had better reinforce it.
Signed-off-by: liujunjie
---
hw/net/virtio-net.c | 4 +++-
hw/virtio/virtio.c | 3 +++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index f154756..9bb20e3 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -1467,7 +1467,9 @@ static void virtio_net_handle_tx_bh(VirtIODevice *vdev,
VirtQueue *vq)
return;
}
virtio_queue_set_notification(vq, 0);
-qemu_bh_schedule(q->tx_bh);
+if (q->tx_bh) {
+qemu_bh_schedule(q->tx_bh);
+}
}
static void virtio_net_tx_timer(void *opaque)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index d4e4d98..7577518 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1604,6 +1604,9 @@ void virtio_del_queue(VirtIODevice *vdev, int n)
vdev->vq[n].vring.num = 0;
vdev->vq[n].vring.num_default = 0;
+vdev->vq[n].vring.align = 0;
+vdev->vq[n].handle_output = NULL;
+vdev->vq[n].handle_aio_output = NULL;
}
static void virtio_set_isr(VirtIODevice *vdev, int value)
--
1.8.3.1
Re: [Qemu-devel] [PATCH v2] target/mips: Initial support for MIPS R5900
Hi Fredrik, > Aleksandar, Aurelien, Maciej -- are you happy with this initial v2 patch? I have skimmed over and I have a couple of comments. I'll try to finalise them ASAP, however I'm currently at the GNU Tools Cauldron and much of my time is taken by the event. Maciej
Re: [Qemu-devel] [PATCH v2 0/3] scsi: replace lsi53c895a_create() and lsi53c810_create() functions
On 9/7/18 9:56 AM, Mark Cave-Ayland wrote: > As part of an upcoming 40p patchset I have a requirement to change the PCI > configuration of the LSI SCSI. However since commits a64aa5785d "hw: > Deprecate -drive > if=scsi with non-onboard HBAs" and b891538e81 "hw/ppc/prep: Fix implicit > creation of > "-drive if=scsi", the lsi53c8*_create() wrapper functions don't return the > device > state itself. > > This patchset replaces the lsi53c895a_create() and lsi53c810_create() > functions > with a single lsi53c8xx_handle_legacy_cmdline() function as suggested by > Thomas, > which makes the caller responsible for initing the LSI SCSI device and hence > allowing it to be configured as required. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé > > v2: > - Don't split LSIState into separate lsi53c895a.h header but instead use a new > lsi53c8xx_handle_legacy_cmdline() function as suggested by Thomas > > > Mark Cave-Ayland (3): > scsi: add lsi53c8xx_handle_legacy_cmdline() function > scsi: move lsi53c8xx_create() callers to > lsi53c8xx_handle_legacy_cmdline() > scsi: remove unused lsi53c895a_create() and lsi53c810_create() > functions > > hw/arm/realview.c| 3 ++- > hw/arm/versatilepb.c | 3 ++- > hw/hppa/machine.c| 4 +++- > hw/ppc/prep.c| 4 +++- > hw/scsi/lsi53c895a.c | 11 ++- > include/hw/pci/pci.h | 3 +-- > 6 files changed, 13 insertions(+), 15 deletions(-) >
Re: [Qemu-devel] [PATCH v2 1/3] raven: some minor IRQ-related tidy-ups
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> This really lays the groundwork for the upcoming patches: it renames the
> irqs PREPPCIState struct member to pci_irqs (as soon there will be a
> distinction) and then changes the raven IRQ opaque to use PREPPCIState
> instead of just irqs array.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/prep.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index 88f035c20b..9b36f19c97 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -55,7 +55,7 @@ typedef struct RavenPCIState {
> typedef struct PRePPCIState {
> PCIHostState parent_obj;
>
> -qemu_irq irq[PCI_NUM_PINS];
> +qemu_irq pci_irqs[PCI_NUM_PINS];
> PCIBus pci_bus;
> AddressSpace pci_io_as;
> MemoryRegion pci_io;
> @@ -194,9 +194,9 @@ static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
>
> static void raven_set_irq(void *opaque, int irq_num, int level)
> {
> -qemu_irq *pic = opaque;
> +PREPPCIState *s = opaque;
>
> -qemu_set_irq(pic[irq_num] , level);
> +qemu_set_irq(s->pci_irqs[irq_num], level);
> }
>
> static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -223,13 +223,12 @@ static void raven_pcihost_realizefn(DeviceState *d,
> Error **errp)
> int i;
>
> for (i = 0; i < PCI_NUM_PINS; i++) {
> -sysbus_init_irq(dev, >irq[i]);
> +sysbus_init_irq(dev, >pci_irqs[i]);
> }
>
> qdev_init_gpio_in(d, raven_change_gpio, 1);
>
> -pci_bus_irqs(>pci_bus, raven_set_irq, raven_map_irq, s->irq,
> - PCI_NUM_PINS);
> +pci_bus_irqs(>pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
>
> memory_region_init_io(>conf_mem, OBJECT(h), _host_conf_le_ops, s,
>"pci-conf-idx", 4);
>
Re: [Qemu-devel] [PATCH v2 2/3] 40p: use OR gate to wire up raven PCI interrupts
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> According to the PReP specification section 6.1.6 "System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
>
> Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
> raven PCI host bridge and then wire the single output of the OR gate to the
> interrupt controller.
Neat!
> Note that whilst the (now deprecated) PReP machine still exists we still need
> to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
> property to the raven PCI host bridge which is set to true for the PReP
> machine.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/prep.c | 25 +++--
> hw/ppc/prep.c | 4 +---
> 2 files changed, 24 insertions(+), 5 deletions(-)
>
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index 9b36f19c97..b1b6b16bad 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -32,6 +32,7 @@
> #include "hw/pci/pci_host.h"
> #include "hw/i386/pc.h"
> #include "hw/loader.h"
> +#include "hw/or-irq.h"
> #include "exec/address-spaces.h"
> #include "elf.h"
>
> @@ -55,6 +56,7 @@ typedef struct RavenPCIState {
> typedef struct PRePPCIState {
> PCIHostState parent_obj;
>
> +qemu_or_irq *or_irq;
> qemu_irq pci_irqs[PCI_NUM_PINS];
> PCIBus pci_bus;
> AddressSpace pci_io_as;
> @@ -69,6 +71,7 @@ typedef struct PRePPCIState {
> RavenPCIState pci_dev;
>
> int contiguous_map;
> +bool is_legacy_prep;
> } PREPPCIState;
>
> #define BIOS_SIZE (1 * MiB)
> @@ -222,8 +225,23 @@ static void raven_pcihost_realizefn(DeviceState *d,
> Error **errp)
> MemoryRegion *address_space_mem = get_system_memory();
> int i;
>
> -for (i = 0; i < PCI_NUM_PINS; i++) {
> -sysbus_init_irq(dev, >pci_irqs[i]);
> +if (s->is_legacy_prep) {
> +for (i = 0; i < PCI_NUM_PINS; i++) {
> +sysbus_init_irq(dev, >pci_irqs[i]);
> +}
> +} else {
> +/* According to PReP specification section 6.1.6 "System Interrupt
> + * Assignments", all PCI interrupts are routed via IRQ 15 */
> +s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
> +object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
> +_fatal);
> +object_property_set_bool(OBJECT(s->or_irq), true, "realized",
> + _fatal);
> +sysbus_init_irq(dev, >or_irq->out_irq);
> +
> +for (i = 0; i < PCI_NUM_PINS; i++) {
> +s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
> +}
> }
>
> qdev_init_gpio_in(d, raven_change_gpio, 1);
> @@ -382,6 +400,9 @@ static Property raven_pcihost_properties[] = {
> DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
> EM_NONE),
> DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
> +/* Temporary workaround until legacy prep machine is removed */
> +DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
> + false),
> DEFINE_PROP_END_OF_LIST()
> };
>
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index b0ea20416e..615865e46c 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -502,6 +502,7 @@ static void ppc_prep_init(MachineState *machine)
> }
> qdev_prop_set_string(dev, "bios-name", bios_name);
> qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
> +qdev_prop_set_bit(dev, "is-legacy-prep", true);
> pcihost = PCI_HOST_BRIDGE(dev);
> object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev),
> NULL);
> qdev_init_nofail(dev);
> @@ -669,9 +670,6 @@ static void ibm_40p_init(MachineState *machine)
> qdev_connect_gpio_out(dev, 0,
>cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
> sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> -sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
> -sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
> -sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>
> /* Memory controller */
>
Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.
>
> This is implemented using a little hack: the existing IRQ routing code uses
> (irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
> the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
>
> Rather than fix the mask to "& 3" we leave the existing routing above as-is
> and then force the LSI SCSI device to use pin C (2). This enables us to
> route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
> only user.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/prep.c | 35 +--
> hw/ppc/prep.c | 10 +++---
> 2 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index b1b6b16bad..87270605b5 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -58,6 +58,7 @@ typedef struct PRePPCIState {
>
> qemu_or_irq *or_irq;
> qemu_irq pci_irqs[PCI_NUM_PINS];
> +qemu_irq scsi_irq;
> PCIBus pci_bus;
> AddressSpace pci_io_as;
> MemoryRegion pci_io;
> @@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
>
> static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
> {
> -return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +switch (pci_dev->devfn) {
> +case PCI_DEVFN(1, 0):
> +/* Whilst legacy PReP machine exists we need to make
> + * sure that this fixed interrupt routing is 40p only */
> +if (strcmp(object_get_typename(OBJECT(pci_dev)),
> + "lsi53c810") == 0) {
> +/* LSI SCSI */
> +return 2;
> +} else {
> +/* Normal PCI IRQ mapping */
> +return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +}
> +default:
> +/* Normal PCI IRQ mapping */
> +return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +}
> }
>
> static void raven_set_irq(void *opaque, int irq_num, int level)
> {
> PREPPCIState *s = opaque;
>
> -qemu_set_irq(s->pci_irqs[irq_num], level);
> +if (s->is_legacy_prep) {
> +qemu_set_irq(s->pci_irqs[irq_num], level);
> +} else {
> +switch (irq_num) {
> +case 2:
> +/* LSI SCSI */
> +qemu_set_irq(s->scsi_irq, level);
> +break;
> +default:
> +/* Normal PCI IRQ mapping */
> +qemu_set_irq(s->pci_irqs[irq_num], level);
> +}
> +}
> }
>
> static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error
> **errp)
> for (i = 0; i < PCI_NUM_PINS; i++) {
> s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
> }
> +
> +/* 40p LSI SCSI has fixed routing via IRQ 13 */
> +sysbus_init_irq(dev, >scsi_irq);
> }
>
> qdev_init_gpio_in(d, raven_change_gpio, 1);
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 615865e46c..0412a56d98 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
> Nvram *m48t59 = NULL;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> +PCIDevice *pci;
> void *fw_cfg;
> int i;
> uint32_t kernel_base = 0, initrd_base = 0;
> @@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
> qdev_connect_gpio_out(dev, 0,
>cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
> sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> +sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>
> /* Memory controller */
> @@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
> qdev_prop_set_uint32(dev, "equipment", 0xc0);
> qdev_init_nofail(dev);
>
> -dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> - "lsi53c810"));
> -lsi53c8xx_handle_legacy_cmdline(dev);
> +pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> + "lsi53c810"));
> +/* Interrupt pin C for fixed LSI SCSI IRQ routing */
> +pci->config[PCI_INTERRUPT_PIN] = 0x3;
> +lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
>
> /* XXX: s3-trio at PCI_DEVFN(2, 0) */
> pci_vga_init(pci_bus);
>
Re: [Qemu-devel] [PATCH v2] target/mips: Initial support for MIPS R5900
》From: Fredrik Noring 》Sent: Friday, September 7, 2018 9:16 PM 》To: Richard Henderson; Aurelien Jarno; Aleksandar Markovic; Maciej W. Rozycki 》Cc: Jürgen Urban; qemu-devel@nongnu.org 》Subject: Re: [PATCH v2] target/mips: Initial support for MIPS R5900 Please: - rebase your changes to the latest QEMU code - organize the changes in the form of patch series - provide links to or attach relevant documentation - in cover letter, outline what is needed for full QEMU support of the cpu in question - describe testing and verification - remove the unclear word 'initial' from the title - outline your plan for providing full support - can you commit enough resources to do the job in a reasonable timeframe? Otherwise, I am generally happy with your patch. Thanks, Aleksandar
[Qemu-devel] [PATCH v2 2/3] 40p: use OR gate to wire up raven PCI interrupts
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
raven PCI host bridge and then wire the single output of the OR gate to the
interrupt controller.
Note that whilst the (now deprecated) PReP machine still exists we still need
to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
property to the raven PCI host bridge which is set to true for the PReP
machine.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/prep.c | 25 +++--
hw/ppc/prep.c | 4 +---
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 9b36f19c97..b1b6b16bad 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -32,6 +32,7 @@
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
#include "hw/loader.h"
+#include "hw/or-irq.h"
#include "exec/address-spaces.h"
#include "elf.h"
@@ -55,6 +56,7 @@ typedef struct RavenPCIState {
typedef struct PRePPCIState {
PCIHostState parent_obj;
+qemu_or_irq *or_irq;
qemu_irq pci_irqs[PCI_NUM_PINS];
PCIBus pci_bus;
AddressSpace pci_io_as;
@@ -69,6 +71,7 @@ typedef struct PRePPCIState {
RavenPCIState pci_dev;
int contiguous_map;
+bool is_legacy_prep;
} PREPPCIState;
#define BIOS_SIZE (1 * MiB)
@@ -222,8 +225,23 @@ static void raven_pcihost_realizefn(DeviceState *d, Error
**errp)
MemoryRegion *address_space_mem = get_system_memory();
int i;
-for (i = 0; i < PCI_NUM_PINS; i++) {
-sysbus_init_irq(dev, >pci_irqs[i]);
+if (s->is_legacy_prep) {
+for (i = 0; i < PCI_NUM_PINS; i++) {
+sysbus_init_irq(dev, >pci_irqs[i]);
+}
+} else {
+/* According to PReP specification section 6.1.6 "System Interrupt
+ * Assignments", all PCI interrupts are routed via IRQ 15 */
+s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
+object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
+_fatal);
+object_property_set_bool(OBJECT(s->or_irq), true, "realized",
+ _fatal);
+sysbus_init_irq(dev, >or_irq->out_irq);
+
+for (i = 0; i < PCI_NUM_PINS; i++) {
+s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
+}
}
qdev_init_gpio_in(d, raven_change_gpio, 1);
@@ -382,6 +400,9 @@ static Property raven_pcihost_properties[] = {
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
EM_NONE),
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
+/* Temporary workaround until legacy prep machine is removed */
+DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
+ false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index b0ea20416e..615865e46c 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -502,6 +502,7 @@ static void ppc_prep_init(MachineState *machine)
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+qdev_prop_set_bit(dev, "is-legacy-prep", true);
pcihost = PCI_HOST_BRIDGE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
qdev_init_nofail(dev);
@@ -669,9 +670,6 @@ static void ibm_40p_init(MachineState *machine)
qdev_connect_gpio_out(dev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
-sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
-sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
-sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
/* Memory controller */
--
2.11.0
[Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device
Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
15 on the interrupt controller, the real 40p machine has routing quirk in
that the LSI SCSI device is routed to IRQ 13.
This is implemented using a little hack: the existing IRQ routing code uses
(irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
Rather than fix the mask to "& 3" we leave the existing routing above as-is
and then force the LSI SCSI device to use pin C (2). This enables us to
route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
only user.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/prep.c | 35 +--
hw/ppc/prep.c | 10 +++---
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index b1b6b16bad..87270605b5 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -58,6 +58,7 @@ typedef struct PRePPCIState {
qemu_or_irq *or_irq;
qemu_irq pci_irqs[PCI_NUM_PINS];
+qemu_irq scsi_irq;
PCIBus pci_bus;
AddressSpace pci_io_as;
MemoryRegion pci_io;
@@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
{
-return (irq_num + (pci_dev->devfn >> 3)) & 1;
+switch (pci_dev->devfn) {
+case PCI_DEVFN(1, 0):
+/* Whilst legacy PReP machine exists we need to make
+ * sure that this fixed interrupt routing is 40p only */
+if (strcmp(object_get_typename(OBJECT(pci_dev)),
+ "lsi53c810") == 0) {
+/* LSI SCSI */
+return 2;
+} else {
+/* Normal PCI IRQ mapping */
+return (irq_num + (pci_dev->devfn >> 3)) & 1;
+}
+default:
+/* Normal PCI IRQ mapping */
+return (irq_num + (pci_dev->devfn >> 3)) & 1;
+}
}
static void raven_set_irq(void *opaque, int irq_num, int level)
{
PREPPCIState *s = opaque;
-qemu_set_irq(s->pci_irqs[irq_num], level);
+if (s->is_legacy_prep) {
+qemu_set_irq(s->pci_irqs[irq_num], level);
+} else {
+switch (irq_num) {
+case 2:
+/* LSI SCSI */
+qemu_set_irq(s->scsi_irq, level);
+break;
+default:
+/* Normal PCI IRQ mapping */
+qemu_set_irq(s->pci_irqs[irq_num], level);
+}
+}
}
static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
@@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error
**errp)
for (i = 0; i < PCI_NUM_PINS; i++) {
s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
}
+
+/* 40p LSI SCSI has fixed routing via IRQ 13 */
+sysbus_init_irq(dev, >scsi_irq);
}
qdev_init_gpio_in(d, raven_change_gpio, 1);
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 615865e46c..0412a56d98 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
Nvram *m48t59 = NULL;
PCIBus *pci_bus;
ISABus *isa_bus;
+PCIDevice *pci;
void *fw_cfg;
int i;
uint32_t kernel_base = 0, initrd_base = 0;
@@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
qdev_connect_gpio_out(dev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
+sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
/* Memory controller */
@@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
qdev_prop_set_uint32(dev, "equipment", 0xc0);
qdev_init_nofail(dev);
-dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
- "lsi53c810"));
-lsi53c8xx_handle_legacy_cmdline(dev);
+pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
+ "lsi53c810"));
+/* Interrupt pin C for fixed LSI SCSI IRQ routing */
+pci->config[PCI_INTERRUPT_PIN] = 0x3;
+lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
/* XXX: s3-trio at PCI_DEVFN(2, 0) */
pci_vga_init(pci_bus);
--
2.11.0
[Qemu-devel] [PATCH v2 1/3] raven: some minor IRQ-related tidy-ups
This really lays the groundwork for the upcoming patches: it renames the
irqs PREPPCIState struct member to pci_irqs (as soon there will be a
distinction) and then changes the raven IRQ opaque to use PREPPCIState
instead of just irqs array.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/prep.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 88f035c20b..9b36f19c97 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -55,7 +55,7 @@ typedef struct RavenPCIState {
typedef struct PRePPCIState {
PCIHostState parent_obj;
-qemu_irq irq[PCI_NUM_PINS];
+qemu_irq pci_irqs[PCI_NUM_PINS];
PCIBus pci_bus;
AddressSpace pci_io_as;
MemoryRegion pci_io;
@@ -194,9 +194,9 @@ static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
static void raven_set_irq(void *opaque, int irq_num, int level)
{
-qemu_irq *pic = opaque;
+PREPPCIState *s = opaque;
-qemu_set_irq(pic[irq_num] , level);
+qemu_set_irq(s->pci_irqs[irq_num], level);
}
static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
@@ -223,13 +223,12 @@ static void raven_pcihost_realizefn(DeviceState *d, Error
**errp)
int i;
for (i = 0; i < PCI_NUM_PINS; i++) {
-sysbus_init_irq(dev, >irq[i]);
+sysbus_init_irq(dev, >pci_irqs[i]);
}
qdev_init_gpio_in(d, raven_change_gpio, 1);
-pci_bus_irqs(>pci_bus, raven_set_irq, raven_map_irq, s->irq,
- PCI_NUM_PINS);
+pci_bus_irqs(>pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
memory_region_init_io(>conf_mem, OBJECT(h), _host_conf_le_ops, s,
"pci-conf-idx", 4);
--
2.11.0
[Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
In the case of the 40p machine this isn't quite true in that it has a routing
quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and
NetBSD compare the model name presented by the firmware to "IBM PPS Model
6015", and if it matches will active this quirk.
There is also a slight issue in that whilst the legacy PReP machine is still
present in the codebase, the old IRQ routing must still be preserved. This is
done by introducing a new "is-legacy-prep" qdev property to the raven PCI host
bridge which preserves the old routing for -M prep until that code is finally
removed.
In order for guest OSs to make use of the fixed IRQ routing, the model name
in the residual data must be changed in OpenBIOS using the diff below:
diff --git a/arch/ppc/qemu/context.c b/arch/ppc/qemu/context.c
index 06e0122..5815895 100644
--- a/arch/ppc/qemu/context.c
+++ b/arch/ppc/qemu/context.c
@@ -111,7 +111,7 @@ static void *
residual_build(uint32_t memsize, uint32_t load_base, uint32_t load_size)
{
residual_t *res;
-const unsigned char model[] = "Qemu\0PPC\0";
+const unsigned char model[] = "IBM PPS Model 6015\0";
int i;
res = malloc(sizeof(residual_t));
With the above OpenBIOS patch applied as well as this patchset, it is now
possible to boot the sandalfoot zImage all the way through to a working
userspace when using OpenBIOS.
(Note: this patchset requires the changes in my previous patchset "scsi:
replace lsi53c895a_create() and lsi53c810_create() functions)
Signed-off-by: Mark Cave-Ayland
Based-on: <20180907125653.5010-1-mark.cave-ayl...@ilande.co.uk>
Mark Cave-Ayland (3):
raven: some minor IRQ-related tidy-ups
40p: use OR gate to wire up raven PCI interrupts
40p: add fixed IRQ routing for LSI SCSI device
hw/pci-host/prep.c | 67 +++---
hw/ppc/prep.c | 12 ++
2 files changed, 66 insertions(+), 13 deletions(-)
--
2.11.0
Re: [Qemu-devel] [Qemu-ppc] [PATCH] 40p: fix PCI interrupt routing
On 27/08/18 18:12, BALATON Zoltan wrote:
> On Mon, 27 Aug 2018, Mark Cave-Ayland wrote:
>> According to the PReP specification section 6.1.6 "System Interrupt
>> Assignments", all PCI interrupts are routed via IRQ 15.
>>
>> With this patch applied it is now possible to boot the sandalfoot
>> zImage all the way through to a working userspace when using
>> OpenBIOS.
>>
>> Signed-off-by: Mark Cave-Ayland
>> ---
>> hw/ppc/prep.c | 9 +
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>> index 162b27a3b8..e82c1355d9 100644
>> --- a/hw/ppc/prep.c
>> +++ b/hw/ppc/prep.c
>> @@ -668,10 +668,11 @@ static void ibm_40p_init(MachineState *machine)
>> dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
>> qdev_connect_gpio_out(dev, 0,
>> cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>> - sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
>> - sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
>> - sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
>> - sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
>> + /* According to PReP specification section 6.1.6 "System Interrupt
>> + * Assignments", all PCI interrupts are routed via IRQ 15 */
>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>> + sysbus_connect_irq(pcihost, i, qdev_get_gpio_in(dev, 15));
>> + }
>
> I'm not sure but this looks similar to what we had with sam460ex:
>
> http://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00359.html
>
> I think you may not connect multiple interrupts to the same host irq
> line this way but you either need an OR gate or handle it within the
> mapping in the PCI host model (which is what we ended up with for the
> sam460ex). Peter's suggestion was to do whichever matches real hardware
> the most if you can find out that (as noted here also with more
> explanation that could be useful):
>
> http://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00360.html
>
> But I could be mistaken in this case, haven't checked it in detail.
Thanks for the pointer. I now have a follow-up patchset that implements
this, however it seems the real 40p machine has a routing quirk: the LSI
SCSI device is separately routed to IRQ 13. So while it's not quite a
pure OR of the 4 PCI IRQs, it's fairly close...
ATB,
Mark.
Re: [Qemu-devel] [PATCH v2 0/3] scsi: replace lsi53c895a_create() and lsi53c810_create() functions
Le 07/09/2018 à 14:56, Mark Cave-Ayland a écrit : As part of an upcoming 40p patchset I have a requirement to change the PCI configuration of the LSI SCSI. However since commits a64aa5785d "hw: Deprecate -drive if=scsi with non-onboard HBAs" and b891538e81 "hw/ppc/prep: Fix implicit creation of "-drive if=scsi", the lsi53c8*_create() wrapper functions don't return the device state itself. This patchset replaces the lsi53c895a_create() and lsi53c810_create() functions with a single lsi53c8xx_handle_legacy_cmdline() function as suggested by Thomas, which makes the caller responsible for initing the LSI SCSI device and hence allowing it to be configured as required. Signed-off-by: Mark Cave-Ayland v2: - Don't split LSIState into separate lsi53c895a.h header but instead use a new lsi53c8xx_handle_legacy_cmdline() function as suggested by Thomas Mark Cave-Ayland (3): scsi: add lsi53c8xx_handle_legacy_cmdline() function scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline() scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions hw/arm/realview.c| 3 ++- hw/arm/versatilepb.c | 3 ++- hw/hppa/machine.c| 4 +++- hw/ppc/prep.c| 4 +++- hw/scsi/lsi53c895a.c | 11 ++- include/hw/pci/pci.h | 3 +-- 6 files changed, 13 insertions(+), 15 deletions(-) Reviewed-by: Hervé Poussineau
