date:20190222

[Qemu-devel] [PATCH v3 13/30] hw/arm: Express dependencies of the PXA2xx machines with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the PXA2xx machines (akita, borzoi,
connex and verdex gumstix, tosa, mainstone, spitz, terrier and z2).
This patch is based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 15 +-
 hw/arm/Kconfig  | 43 +
 hw/arm/Makefile.objs|  5 -
 3 files changed, 52 insertions(+), 11 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index d6858c3..cba62ba 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -16,22 +16,20 @@ CONFIG_STELLARIS=y
 CONFIG_REALVIEW=y
 CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
+CONFIG_MAINSTONE=y
+CONFIG_GUMSTIX=y
+CONFIG_SPITZ=y
+CONFIG_TOSA=y
+CONFIG_Z2=y
 
 CONFIG_VGA=y
-CONFIG_NAND=y
-CONFIG_ECC=y
-CONFIG_SERIAL=y
-CONFIG_MAX7310=y
 CONFIG_TMP421=y
 CONFIG_PCA9552=y
-CONFIG_ADS7846=y
-CONFIG_MAX111X=y
 CONFIG_SSI_M25P80=y
 CONFIG_ALLWINNER_EMAC=y
 CONFIG_IMX_FEC=y
 CONFIG_FTGMAC100=y
 CONFIG_DS1338=y
-CONFIG_MICRODRIVE=y
 CONFIG_PLATFORM_BUS=y
 CONFIG_VIRTIO_MMIO=y
 
@@ -39,16 +37,13 @@ CONFIG_NETDUINO2=y
 
 CONFIG_PL330=y
 CONFIG_CADENCE=y
-CONFIG_PXA2XX=y
 CONFIG_FRAMEBUFFER=y
 CONFIG_XILINX_SPIPS=y
 CONFIG_ZYNQ_DEVCFG=y
 
 CONFIG_DIGIC=y
-CONFIG_MAINSTONE=y
 CONFIG_MPS2=y
 CONFIG_RASPI=y
-CONFIG_ZAURUS=y
 CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 62ab487..fd6b92c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -50,6 +50,9 @@ config INTEGRATOR
 
 config MAINSTONE
 bool
+select PXA2XX
+select PFLASH_CFI01
+select SMC91C111
 
 config MUSCA
 bool
@@ -92,6 +95,44 @@ config OMAP
 
 config PXA2XX
 bool
+select FRAMEBUFFER
+select I2C
+select PCI
+select SERIAL
+select SD
+select SSI
+select USB_OHCI
+
+config GUMSTIX
+bool
+select PFLASH_CFI01
+select SMC91C111
+select PXA2XX
+
+config TOSA
+bool
+select ZAURUS  # scoop
+select MICRODRIVE
+select PXA2XX
+
+config SPITZ
+bool
+select ADS7846 # display
+select MAX111X # A/D converter
+select WM8750  # audio codec
+select MAX7310 # GPIO expander
+select ZAURUS  # scoop
+select NAND# memory
+select ECC # Error-correcting for NAND
+select MICRODRIVE
+select PXA2XX
+
+config Z2
+bool
+select PFLASH_CFI01
+select WM8750
+select PL011 # UART
+select PXA2XX
 
 config REALVIEW
 bool
@@ -230,6 +271,8 @@ config MSF2
 
 config ZAURUS
 bool
+select NAND
+select ECC
 
 config A9MPCORE
 bool
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index bd0b45a..00328d1 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -11,7 +11,10 @@ obj-$(CONFIG_NETDUINO2) += netduino2.o
 obj-$(CONFIG_NSERIES) += nseries.o
 obj-$(CONFIG_SX1) += omap_sx1.o
 obj-$(CONFIG_CHEETAH) += palm.o
-obj-$(CONFIG_PXA2XX) += gumstix.o spitz.o tosa.o z2.o
+obj-$(CONFIG_GUMSTIX) += gumstix.o
+obj-$(CONFIG_SPITZ) += spitz.o
+obj-$(CONFIG_TOSA) += tosa.o
+obj-$(CONFIG_Z2) += z2.o
 obj-$(CONFIG_REALVIEW) += realview.o
 obj-$(CONFIG_STELLARIS) += stellaris.o
 obj-$(CONFIG_STRONGARM) += collie.o
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 15/30] hw/arm: Express dependencies of collie with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the Strongarm collie machine.
This patch is based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 3 +--
 hw/arm/Kconfig  | 7 +++
 hw/arm/Makefile.objs| 2 +-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index b9fce47..34725e1 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -22,6 +22,7 @@ CONFIG_GUMSTIX=y
 CONFIG_SPITZ=y
 CONFIG_TOSA=y
 CONFIG_Z2=y
+CONFIG_COLLIE=y
 
 CONFIG_VGA=y
 CONFIG_TMP421=y
@@ -96,5 +97,3 @@ CONFIG_GPIO_KEY=y
 CONFIG_MSF2=y
 CONFIG_FW_CFG_DMA=y
 CONFIG_PCI_EXPRESS_DESIGNWARE=y
-
-CONFIG_STRONGARM=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 78e694b..f15e433 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -175,6 +175,13 @@ config STELLARIS
 
 config STRONGARM
 bool
+select PXA2XX
+
+config COLLIE
+bool
+select PFLASH_CFI01
+select ZAURUS  # scoop
+select STRONGARM
 
 config SX1
 bool
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 00328d1..729e711 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -17,7 +17,7 @@ obj-$(CONFIG_TOSA) += tosa.o
 obj-$(CONFIG_Z2) += z2.o
 obj-$(CONFIG_REALVIEW) += realview.o
 obj-$(CONFIG_STELLARIS) += stellaris.o
-obj-$(CONFIG_STRONGARM) += collie.o
+obj-$(CONFIG_COLLIE) += collie.o
 obj-$(CONFIG_VERSATILE) += versatilepb.o
 obj-$(CONFIG_VEXPRESS) += vexpress.o
 obj-$(CONFIG_ZYNQ) += xilinx_zynq.o
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 02/30] hw/pci/pci-stub: Add msi_enabled() and msi_notify() to the pci stubs

2019-02-22 Thread Thomas Huth

Some machines have an AHCI adapter, but no PCI. To be able to
compile hw/ide/ahci.c without CONFIG_PCI, we still need the two
functions msi_enabled() and msi_notify() for linking.
This is required for the new Kconfig-like build system, if a user
wants to compile a QEMU binary with just one machine that has AHCI,
but no PCI, like the ARM "cubieboard" for example.

Reviewed-by: Michael S. Tsirkin 
Signed-off-by: Thomas Huth 
---
 hw/pci/pci-stub.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/hw/pci/pci-stub.c b/hw/pci/pci-stub.c
index b941a0e..c04a5df 100644
--- a/hw/pci/pci-stub.c
+++ b/hw/pci/pci-stub.c
@@ -53,3 +53,14 @@ uint16_t pci_requester_id(PCIDevice *dev)
 g_assert(false);
 return 0;
 }
+
+/* Required by ahci.c */
+bool msi_enabled(const PCIDevice *dev)
+{
+return false;
+}
+
+void msi_notify(PCIDevice *dev, unsigned int vector)
+{
+g_assert_not_reached();
+}
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 09/30] hw/arm: Express dependencies of musicpal with Kconfig

2019-02-22 Thread Thomas Huth

This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 6 +-
 hw/arm/Kconfig  | 6 ++
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 388a2ba..c8eafb1 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -9,13 +9,13 @@ CONFIG_EXYNOS4=y
 CONFIG_HIGHBANK=y
 CONFIG_INTEGRATOR=y
 CONFIG_FSL_IMX31=y
+CONFIG_MUSICPAL=y
 
 CONFIG_VGA=y
 CONFIG_NAND=y
 CONFIG_ECC=y
 CONFIG_SERIAL=y
 CONFIG_MAX7310=y
-CONFIG_WM8750=y
 CONFIG_TWL92230=y
 CONFIG_TSC2005=y
 CONFIG_LM832X=y
@@ -38,7 +38,6 @@ CONFIG_IMX_FEC=y
 CONFIG_FTGMAC100=y
 CONFIG_DS1338=y
 CONFIG_PFLASH_CFI01=y
-CONFIG_PFLASH_CFI02=y
 CONFIG_MICRODRIVE=y
 CONFIG_USB_MUSB=y
 CONFIG_PLATFORM_BUS=y
@@ -54,14 +53,12 @@ CONFIG_PL190=y
 CONFIG_PL330=y
 CONFIG_CADENCE=y
 CONFIG_PXA2XX=y
-CONFIG_BITBANG_I2C=y
 CONFIG_FRAMEBUFFER=y
 CONFIG_XILINX_SPIPS=y
 CONFIG_ZYNQ_DEVCFG=y
 
 CONFIG_ARM11SCU=y
 CONFIG_DIGIC=y
-CONFIG_MARVELL_88W8618=y
 CONFIG_OMAP=y
 CONFIG_TSC210X=y
 CONFIG_BLIZZARD=y
@@ -137,7 +134,6 @@ CONFIG_XILINX_AXI=y
 CONFIG_PCI_EXPRESS_DESIGNWARE=y
 
 CONFIG_STRONGARM=y
-CONFIG_MUSICPAL=y
 
 # for realview and versatilepb
 CONFIG_LSI_SCSI_PCI=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index df10a4d..ece2962 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -51,7 +51,13 @@ config MUSCA
 
 config MUSICPAL
 bool
+select BITBANG_I2C
+select MARVELL_88W8618
 select PTIMER
+select PFLASH_CFI02
+select PCI
+select SERIAL
+select WM8750
 
 config NETDUINO2
 bool
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 10/30] hw/arm: Express dependencies of the OMAP machines with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the OMAP machines (cheetah, n800, n810,
sx1 and sx1-v1).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 17 -
 hw/arm/Kconfig  | 26 ++
 hw/arm/Makefile.objs|  3 ++-
 3 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index c8eafb1..e0818f1 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -10,16 +10,16 @@ CONFIG_HIGHBANK=y
 CONFIG_INTEGRATOR=y
 CONFIG_FSL_IMX31=y
 CONFIG_MUSICPAL=y
+CONFIG_MUSCA=y
+CONFIG_CHEETAH=y
+CONFIG_SX1=y
+CONFIG_NSERIES=y
 
 CONFIG_VGA=y
 CONFIG_NAND=y
 CONFIG_ECC=y
 CONFIG_SERIAL=y
 CONFIG_MAX7310=y
-CONFIG_TWL92230=y
-CONFIG_TSC2005=y
-CONFIG_LM832X=y
-CONFIG_TMP105=y
 CONFIG_TMP421=y
 CONFIG_PCA9552=y
 CONFIG_STELLARIS=y
@@ -37,9 +37,7 @@ CONFIG_ALLWINNER_EMAC=y
 CONFIG_IMX_FEC=y
 CONFIG_FTGMAC100=y
 CONFIG_DS1338=y
-CONFIG_PFLASH_CFI01=y
 CONFIG_MICRODRIVE=y
-CONFIG_USB_MUSB=y
 CONFIG_PLATFORM_BUS=y
 CONFIG_VIRTIO_MMIO=y
 
@@ -59,15 +57,8 @@ CONFIG_ZYNQ_DEVCFG=y
 
 CONFIG_ARM11SCU=y
 CONFIG_DIGIC=y
-CONFIG_OMAP=y
-CONFIG_TSC210X=y
-CONFIG_BLIZZARD=y
-CONFIG_ONENAND=y
-CONFIG_TUSB6010=y
 CONFIG_MAINSTONE=y
 CONFIG_MPS2=y
-CONFIG_MUSCA=y
-CONFIG_NSERIES=y
 CONFIG_RASPI=y
 CONFIG_REALVIEW=y
 CONFIG_ZAURUS=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index ece2962..af559be 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,6 +1,11 @@
 config ARM_VIRT
 bool
 
+config CHEETAH
+bool
+select OMAP
+select TSC210X
+
 config DIGIC
 bool
 select PTIMER
@@ -64,9 +69,26 @@ config NETDUINO2
 
 config NSERIES
 bool
+select OMAP
+select TMP105   # tempature sensor
+select BLIZZARD # LCD/TV controller
+select ONENAND
+select TSC210X  # touchscreen/sensors/audio
+select TSC2005  # touchscreen/sensors/keypad
+select LM832X   # GPIO keyboard chip
+select TWL92230 # energy-management
+select TUSB6010
 
 config OMAP
 bool
+select FRAMEBUFFER
+select I2C
+select ECC
+select NAND
+select PFLASH_CFI01
+select PCI
+select SD
+select SERIAL
 
 config PXA2XX
 bool
@@ -80,6 +102,10 @@ config STELLARIS
 config STRONGARM
 bool
 
+config SX1
+bool
+select OMAP
+
 config VERSATILE
 bool
 
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index fa57c7c..8302b8d 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -9,7 +9,8 @@ obj-$(CONFIG_MAINSTONE) += mainstone.o
 obj-$(CONFIG_MUSICPAL) += musicpal.o
 obj-$(CONFIG_NETDUINO2) += netduino2.o
 obj-$(CONFIG_NSERIES) += nseries.o
-obj-$(CONFIG_OMAP) += omap_sx1.o palm.o
+obj-$(CONFIG_SX1) += omap_sx1.o
+obj-$(CONFIG_CHEETAH) += palm.o
 obj-$(CONFIG_PXA2XX) += gumstix.o spitz.o tosa.o z2.o
 obj-$(CONFIG_REALVIEW) += realview.o
 obj-$(CONFIG_STELLARIS) += stellaris.o
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 06/30] hw/arm: Express dependencies of the highbank machines with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the highbank machine (and the midway
machine).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak |  9 +
 hw/arm/Kconfig  | 12 
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 67fc8df..c91f526 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -6,6 +6,7 @@ CONFIG_ARM_V7M=y
 CONFIG_PCI_DEVICES=y
 
 CONFIG_EXYNOS4=y
+CONFIG_HIGHBANK=y
 
 CONFIG_VGA=y
 CONFIG_NAND=y
@@ -43,24 +44,17 @@ CONFIG_PLATFORM_BUS=y
 CONFIG_VIRTIO_MMIO=y
 
 CONFIG_ARM11MPCORE=y
-CONFIG_A15MPCORE=y
 
 CONFIG_NETDUINO2=y
 
-CONFIG_ARM_TIMER=y
-CONFIG_PL011=y
-CONFIG_PL022=y
-CONFIG_PL031=y
 CONFIG_PL041=y
 CONFIG_PL050=y
-CONFIG_PL061=y
 CONFIG_PL080=y
 CONFIG_PL110=y
 CONFIG_PL181=y
 CONFIG_PL190=y
 CONFIG_PL330=y
 CONFIG_CADENCE=y
-CONFIG_XGMAC=y
 CONFIG_PXA2XX=y
 CONFIG_BITBANG_I2C=y
 CONFIG_FRAMEBUFFER=y
@@ -150,7 +144,6 @@ CONFIG_XILINX_AXI=y
 CONFIG_PCI_EXPRESS_DESIGNWARE=y
 
 CONFIG_STRONGARM=y
-CONFIG_HIGHBANK=y
 CONFIG_MUSICPAL=y
 
 # for realview and versatilepb
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 9d86b16..aea7301 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -18,6 +18,18 @@ config EXYNOS4
 
 config HIGHBANK
 bool
+select A9MPCORE
+select A15MPCORE
+select AHCI
+select ARM_TIMER # sp804
+select ARM_V7M
+select PCI
+select PL011 # UART
+select PL022 # Serial port
+select PL031 # RTC
+select PL061 # GPIO
+select PL310 # cache controller
+select XGMAC # ethernet
 
 config INTEGRATOR
 bool
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 00/30] Kconfig dependencies for ARM machines

2019-02-22 Thread Thomas Huth

This series reworks the default-configs/arm-softmmu.mak and
default-configs/aarch64-softmmu.mak files to use the new Kconfig-style
dependencies instead.

Based-on: 1549562254-41157-1-git-send-email-pbonz...@redhat.com
  ("Support Kconfig in QEMU")

Some of the patches are slightly based on the work by Ákos Kovács:

https://lists.nongnu.org/archive/html/qemu-devel/2013-08/msg03730.html

The other patches have been created by looking at the sources and finding
out the dependencies the hard way via trial-and-error (i.e. by enabling
only one machine at a time and checking whether it can be compiled and
started).

v3:
 - Addressed review feedback from v2
 - Included patches to clean up the PCI dependencies of AHCI and SDHCI
   (so CONFIG_AHCI and CONFIG_SDHCI do not depend on CONFIG_PCI anymore)
 - Added an additional patch for the new "musca" machines

v2: Adressed review-feedback from v1
 - CONFIG_SDHCI and CONFIG_AHCI now select CONFIG_PCI
 - Added switches for MICROBIT and EMCRAFT_SF2

Thomas Huth (30):
  hw/arm/Kconfig: Add a config switch for MUSCA
  hw/pci/pci-stub: Add msi_enabled() and msi_notify() to the pci stubs
  hw/ide/ahci: Add a Kconfig switch for the AHDI-ICH9 device
  hw/sd/sdhci: Move PCI-related code into a separate file
  hw/arm: Express dependencies of the exynos machines with Kconfig
  hw/arm: Express dependencies of the highbank machines with Kconfig
  hw/arm: Express dependencies of integratorcp with Kconfig
  hw/arm: Express dependencies of the fsl-imx31 machine with Kconfig
  hw/arm: Express dependencies of musicpal with Kconfig
  hw/arm: Express dependencies of the OMAP machines with Kconfig
  hw/arm: Express dependencies of stellaris with Kconfig
  hw/arm: Express dependencies of realview, versatile and vexpress with
Kconfig
  hw/arm: Express dependencies of the PXA2xx machines with Kconfig
  hw/arm: Express dependencies of xilinx-zynq with Kconfig
  hw/arm: Express dependencies of collie with Kconfig
  hw/arm: Express dependencies of the aspeed boards with Kconfig
  hw/arm: Express dependencies of the virt machine with Kconfig
  hw/arm: Express dependencies of netduino / stm32f2xx with Kconfig
  hw/arm: Express dependencies of allwinner / cubieboard with Kconfig
  hw/arm: Express dependencies of the MPS2 boards with Kconfig
  hw/arm: Express dependencies of the raspi machines with Kconfig
  hw/arm: Express dependencies of canon-a1100 with Kconfig
  hw/arm: Express dependencies of sabrelite with Kconfig
  hw/arm: Express dependencies of the MSF2 / EMCRAFT_SF2 machine with
Kconfig
  hw/arm: Express dependencies for remaining IMX boards with Kconfig
  hw/arm: Express dependencies of the microbit / nrf51 machine with
Kconfig
  hw/arm: Express dependencies of the ZynqMP zcu102 machine with Kconfig
  hw/arm: Express dependencies of the xlnx-versal-virt machine with
Kconfig
  hw/arm: Express dependencies of the musca machines with Kconfig
  hw/arm: Remove hard-enablement of the remaining PCI devices

 default-configs/aarch64-softmmu.mak |   4 -
 default-configs/arm-softmmu.mak | 177 +++-
 hw/arm/Kconfig  | 316 
 hw/arm/Makefile.objs|  25 ++-
 hw/display/Kconfig  |   3 +
 hw/i2c/Kconfig  |   2 +-
 hw/ide/Kconfig  |   6 +-
 hw/ide/Makefile.objs|   2 +-
 hw/misc/Kconfig |   2 +
 hw/pci/pci-stub.c   |  11 ++
 hw/sd/Kconfig   |   6 +-
 hw/sd/Makefile.objs |   1 +
 hw/sd/sdhci-internal.h  |  34 
 hw/sd/sdhci-pci.c   |  87 ++
 hw/sd/sdhci.c   |  98 +--
 15 files changed, 514 insertions(+), 260 deletions(-)
 create mode 100644 hw/sd/sdhci-pci.c

-- 
1.8.3.1

[Qemu-devel] [PATCH v3 08/30] hw/arm: Express dependencies of the fsl-imx31 machine with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the fsl-imx31 / kzm machine.
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 3 +--
 hw/arm/Kconfig  | 5 +
 hw/misc/Kconfig | 2 ++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 74382cc..388a2ba 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -8,6 +8,7 @@ CONFIG_PCI_DEVICES=y
 CONFIG_EXYNOS4=y
 CONFIG_HIGHBANK=y
 CONFIG_INTEGRATOR=y
+CONFIG_FSL_IMX31=y
 
 CONFIG_VGA=y
 CONFIG_NAND=y
@@ -66,7 +67,6 @@ CONFIG_TSC210X=y
 CONFIG_BLIZZARD=y
 CONFIG_ONENAND=y
 CONFIG_TUSB6010=y
-CONFIG_IMX=y
 CONFIG_MAINSTONE=y
 CONFIG_MPS2=y
 CONFIG_MUSCA=y
@@ -115,7 +115,6 @@ CONFIG_ALLWINNER_A10_PIC=y
 CONFIG_ALLWINNER_A10=y
 
 CONFIG_FSL_IMX6=y
-CONFIG_FSL_IMX31=y
 CONFIG_FSL_IMX25=y
 CONFIG_FSL_IMX7=y
 CONFIG_FSL_IMX6UL=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 6a34ce1..df10a4d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -106,6 +106,11 @@ config FSL_IMX25
 
 config FSL_IMX31
 bool
+select SERIAL
+select IMX
+select IMX_I2C
+select LAN9118
+select PCI
 
 config FSL_IMX6
 bool
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 11d4b30..54ff9a8 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -76,6 +76,8 @@ config ECCMEMCTL
 config IMX
 bool
 select PTIMER
+select SSI
+select USB_EHCI_SYSBUS
 
 config STM32F2XX_SYSCFG
 bool
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 07/30] hw/arm: Express dependencies of integratorcp with Kconfig

2019-02-22 Thread Thomas Huth

This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 8 +---
 hw/arm/Kconfig  | 9 +
 hw/display/Kconfig  | 1 +
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index c91f526..74382cc 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -7,6 +7,7 @@ CONFIG_PCI_DEVICES=y
 
 CONFIG_EXYNOS4=y
 CONFIG_HIGHBANK=y
+CONFIG_INTEGRATOR=y
 
 CONFIG_VGA=y
 CONFIG_NAND=y
@@ -31,7 +32,6 @@ CONFIG_ADS7846=y
 CONFIG_MAX111X=y
 CONFIG_SSI_SD=y
 CONFIG_SSI_M25P80=y
-CONFIG_SMC91C111=y
 CONFIG_ALLWINNER_EMAC=y
 CONFIG_IMX_FEC=y
 CONFIG_FTGMAC100=y
@@ -48,10 +48,7 @@ CONFIG_ARM11MPCORE=y
 CONFIG_NETDUINO2=y
 
 CONFIG_PL041=y
-CONFIG_PL050=y
 CONFIG_PL080=y
-CONFIG_PL110=y
-CONFIG_PL181=y
 CONFIG_PL190=y
 CONFIG_PL330=y
 CONFIG_CADENCE=y
@@ -113,9 +110,6 @@ CONFIG_VFIO_PLATFORM=y
 CONFIG_VFIO_XGMAC=y
 CONFIG_VFIO_AMD_XGBE=y
 
-CONFIG_INTEGRATOR=y
-CONFIG_INTEGRATOR_DEBUG=y
-
 CONFIG_ALLWINNER_A10_PIT=y
 CONFIG_ALLWINNER_A10_PIC=y
 CONFIG_ALLWINNER_A10=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index aea7301..6a34ce1 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -33,6 +33,15 @@ config HIGHBANK
 
 config INTEGRATOR
 bool
+select ARM_TIMER
+select INTEGRATOR_DEBUG
+select PL011 # UART
+select PL031 # RTC
+select PL050 # keyboard/mouse
+select PL110 # pl111 LCD controller
+select PL181 # display
+select PCI
+select SMC91C111
 
 config MAINSTONE
 bool
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
index ee3acd9..34c8c12 100644
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -21,6 +21,7 @@ config JAZZ_LED
 
 config PL110
 bool
+select FRAMEBUFFER
 
 config SII9022
 bool
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 05/30] hw/arm: Express dependencies of the exynos machines with Kconfig

2019-02-22 Thread Thomas Huth

Add Kconfig dependencies for the Exynos-related boards (nuri and
smdkc210).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).

Signed-off-by: Thomas Huth 
---
 default-configs/arm-softmmu.mak | 18 ++
 hw/arm/Kconfig  | 11 +++
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ad5066b..67fc8df 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -1,7 +1,12 @@
 # Default configuration for arm-softmmu
 
-CONFIG_PCI=y
+# TODO: ARM_V7M is currently always required - make this more flexible!
+CONFIG_ARM_V7M=y
+
 CONFIG_PCI_DEVICES=y
+
+CONFIG_EXYNOS4=y
+
 CONFIG_VGA=y
 CONFIG_NAND=y
 CONFIG_ECC=y
@@ -25,7 +30,6 @@ CONFIG_ADS7846=y
 CONFIG_MAX111X=y
 CONFIG_SSI_SD=y
 CONFIG_SSI_M25P80=y
-CONFIG_LAN9118=y
 CONFIG_SMC91C111=y
 CONFIG_ALLWINNER_EMAC=y
 CONFIG_IMX_FEC=y
@@ -35,21 +39,15 @@ CONFIG_PFLASH_CFI01=y
 CONFIG_PFLASH_CFI02=y
 CONFIG_MICRODRIVE=y
 CONFIG_USB_MUSB=y
-CONFIG_USB_EHCI_SYSBUS=y
 CONFIG_PLATFORM_BUS=y
 CONFIG_VIRTIO_MMIO=y
 
 CONFIG_ARM11MPCORE=y
-CONFIG_A9MPCORE=y
 CONFIG_A15MPCORE=y
 
-CONFIG_ARM_V7M=y
 CONFIG_NETDUINO2=y
 
-CONFIG_ARM_GIC=y
 CONFIG_ARM_TIMER=y
-CONFIG_ARM_MPTIMER=y
-CONFIG_A9_GTIMER=y
 CONFIG_PL011=y
 CONFIG_PL022=y
 CONFIG_PL031=y
@@ -60,11 +58,9 @@ CONFIG_PL080=y
 CONFIG_PL110=y
 CONFIG_PL181=y
 CONFIG_PL190=y
-CONFIG_PL310=y
 CONFIG_PL330=y
 CONFIG_CADENCE=y
 CONFIG_XGMAC=y
-CONFIG_EXYNOS4=y
 CONFIG_PXA2XX=y
 CONFIG_BITBANG_I2C=y
 CONFIG_FRAMEBUFFER=y
@@ -72,7 +68,6 @@ CONFIG_XILINX_SPIPS=y
 CONFIG_ZYNQ_DEVCFG=y
 
 CONFIG_ARM11SCU=y
-CONFIG_A9SCU=y
 CONFIG_DIGIC=y
 CONFIG_MARVELL_88W8618=y
 CONFIG_OMAP=y
@@ -124,7 +119,6 @@ CONFIG_VFIO_PLATFORM=y
 CONFIG_VFIO_XGMAC=y
 CONFIG_VFIO_AMD_XGBE=y
 
-CONFIG_SDHCI=y
 CONFIG_INTEGRATOR=y
 CONFIG_INTEGRATOR_DEBUG=y
 
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index ac5faca..9d86b16 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -7,7 +7,14 @@ config DIGIC
 
 config EXYNOS4
 bool
+select A9MPCORE
+select I2C
+select LAN9118
+select PCI
+select PL310 # cache controller
 select PTIMER
+select SDHCI
+select USB_EHCI_SYSBUS
 
 config HIGHBANK
 bool
@@ -112,6 +119,10 @@ config ZAURUS
 
 config A9MPCORE
 bool
+select A9_GTIMER
+select A9SCU   # snoop control unit
+select ARM_GIC
+select ARM_MPTIMER
 
 config A15MPCORE
 bool
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 03/30] hw/ide/ahci: Add a Kconfig switch for the AHDI-ICH9 device

2019-02-22 Thread Thomas Huth

Some of our machines (like the ARM cubieboard) use CONFIG_AHCI for an AHCI
sysbus device, but do not use CONFIG_PCI since they do not feature a PCI
bus. With CONFIG_AHCI but without CONFIG_PCI, currently linking fails:

../hw/ide/ich.o: In function `pci_ich9_ahci_realize':
hw/ide/ich.c:124: undefined reference to `pci_allocate_irq'
hw/ide/ich.c:126: undefined reference to `pci_register_bar'
hw/ide/ich.c:128: undefined reference to `pci_register_bar'
hw/ide/ich.c:131: undefined reference to `pci_add_capability'
hw/ide/ich.c:147: undefined reference to `msi_init'
../hw/ide/ich.o: In function `pci_ich9_uninit':
hw/ide/ich.c:158: undefined reference to `msi_uninit'
../hw/ide/ich.o:(.data.rel+0x50): undefined reference to 
`vmstate_pci_device'

We must only compile ich.c if CONFIG_PCI is available, too, so introduce a
new config switch for this device.

Signed-off-by: Thomas Huth 
---
 hw/ide/Kconfig   | 6 +-
 hw/ide/Makefile.objs | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig
index ab47b6a..5d9106b 100644
--- a/hw/ide/Kconfig
+++ b/hw/ide/Kconfig
@@ -44,9 +44,13 @@ config MICRODRIVE
 
 config AHCI
 bool
+select IDE_QDEV
+
+config AHCI_ICH9
+bool
 default y if PCI_DEVICES
 depends on PCI
-select IDE_QDEV
+select AHCI
 
 config IDE_SII3112
 bool
diff --git a/hw/ide/Makefile.objs b/hw/ide/Makefile.objs
index a142add..faf04e0 100644
--- a/hw/ide/Makefile.objs
+++ b/hw/ide/Makefile.objs
@@ -9,6 +9,6 @@ common-obj-$(CONFIG_IDE_MMIO) += mmio.o
 common-obj-$(CONFIG_IDE_VIA) += via.o
 common-obj-$(CONFIG_MICRODRIVE) += microdrive.o
 common-obj-$(CONFIG_AHCI) += ahci.o
-common-obj-$(CONFIG_AHCI) += ich.o
+common-obj-$(CONFIG_AHCI_ICH9) += ich.o
 common-obj-$(CONFIG_ALLWINNER_A10) += ahci-allwinner.o
 common-obj-$(CONFIG_IDE_SII3112) += sii3112.o
-- 
1.8.3.1

[Qemu-devel] [PATCH v3 01/30] hw/arm/Kconfig: Add a config switch for MUSCA

2019-02-22 Thread Thomas Huth

The musca machine has been added recently, so we need now a Kconfig
switch for this, too.

Signed-off-by: Thomas Huth 
---
 I assume Paolo will add this config switch to his next iteration
 of the Kconfig patches already, so in that case this patch can be
 dropped / ignored.

 hw/arm/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3176680..ac5faca 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -18,6 +18,9 @@ config INTEGRATOR
 config MAINSTONE
 bool
 
+config MUSCA
+bool
+
 config MUSICPAL
 bool
 select PTIMER
-- 
1.8.3.1

[Qemu-devel] [RFC 6/6] target/arm: Define cortex-a76

2019-02-22 Thread Richard Henderson

Signed-off-by: Richard Henderson 
---
 hw/arm/virt.c  |  1 +
 target/arm/cpu64.c | 58 ++
 2 files changed, 59 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 06a155724c..4495ce8918 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -175,6 +175,7 @@ static const char *valid_cpus[] = {
 ARM_CPU_TYPE_NAME("cortex-a72"),
 ARM_CPU_TYPE_NAME("cortex-a73"),
 ARM_CPU_TYPE_NAME("cortex-a75"),
+ARM_CPU_TYPE_NAME("cortex-a76"),
 ARM_CPU_TYPE_NAME("host"),
 ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 325e0ecf17..4a92d7656a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -369,6 +369,63 @@ static void aarch64_a75_initfn(Object *obj)
 define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+
+cpu->dtb_compatible = "arm,cortex-a76";
+set_feature(>env, ARM_FEATURE_V8);
+set_feature(>env, ARM_FEATURE_VFP4);
+set_feature(>env, ARM_FEATURE_NEON);
+set_feature(>env, ARM_FEATURE_GENERIC_TIMER);
+set_feature(>env, ARM_FEATURE_AARCH64);
+set_feature(>env, ARM_FEATURE_CBAR_RO);
+set_feature(>env, ARM_FEATURE_EL2);
+set_feature(>env, ARM_FEATURE_EL3);
+set_feature(>env, ARM_FEATURE_PMU);
+
+/*
+ * Note that the A76 only supports AA32 at EL0, so the
+ * AA32-only EL1 id registers do not exist.
+ */
+cpu->midr = 0x413fd0b1;
+cpu->revidr = 0x;
+cpu->ctr = 0x8444C004;
+cpu->reset_sctlr = 0x30d50838;
+cpu->id_pfr0 = 0x10010131;
+cpu->id_pfr1 = 0x1001;
+cpu->id_pfr2 = 0x0011;
+cpu->id_dfr0 = 0x04010088;
+cpu->id_afr0 = 0x;
+cpu->id_mmfr0 = 0x10201105;
+cpu->id_mmfr1 = 0x4000;
+cpu->id_mmfr2 = 0x0126;
+cpu->id_mmfr3 = 0x02122211;
+cpu->isar.id_isar0 = 0x02101110;
+cpu->isar.id_isar1 = 0x13112111;
+cpu->isar.id_isar2 = 0x21232042;
+cpu->isar.id_isar3 = 0x01112131;
+cpu->isar.id_isar4 = 0x00011142;
+cpu->isar.id_isar5 = 0x00011121;
+cpu->isar.id_isar6 = 0x0010;
+cpu->isar.id_aa64pfr0 = 0x11001012ull;
+cpu->id_aa64dfr0 = 0x10305408;
+cpu->isar.id_aa64isar0 = 0x100010211120ull;
+cpu->isar.id_aa64isar1 = 0x0011;
+cpu->isar.id_aa64mmfr0 = 0x00101122;
+cpu->isar.id_aa64mmfr1 = 0x10212122;
+cpu->isar.id_aa64mmfr2 = 0x1011;
+cpu->clidr = 0x08200023;
+cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+cpu->dcz_blocksize = 4; /* 64 bytes */
+cpu->gic_num_lrs = 4;
+cpu->gic_vpribits = 5;
+cpu->gic_vprebits = 5;
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
 {
@@ -491,6 +548,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
 { .name = "cortex-a73", .initfn = aarch64_a73_initfn },
 { .name = "cortex-a75", .initfn = aarch64_a75_initfn },
+{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
 { .name = "max",.initfn = aarch64_max_initfn },
 { .name = NULL }
 };
-- 
2.17.2

[Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73

2019-02-22 Thread Richard Henderson

There are new field definitions, CSV2 and CSV3, that do not yet
appear in the main ARM ARM.  Define the ID_AA64PF0 versions,
since we already define the rest of those bits.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  2 ++
 hw/arm/virt.c  |  1 +
 target/arm/cpu64.c | 63 +++---
 3 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c57f8e9ba8..c2899f0bed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1694,6 +1694,8 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SBSS, 4, 4)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 99c2b6e60d..c69a734878 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -173,6 +173,7 @@ static const char *valid_cpus[] = {
 ARM_CPU_TYPE_NAME("cortex-a53"),
 ARM_CPU_TYPE_NAME("cortex-a57"),
 ARM_CPU_TYPE_NAME("cortex-a72"),
+ARM_CPU_TYPE_NAME("cortex-a73"),
 ARM_CPU_TYPE_NAME("host"),
 ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index eff0f164dd..d34aa3af75 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -51,7 +51,8 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const 
ARMCPRegInfo *ri)
 }
 #endif
 
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+/* These extra registers are used by (most of?) the cortex-a* series.  */
+static const ARMCPRegInfo cortex_aXX_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
@@ -149,7 +150,7 @@ static void aarch64_a57_initfn(Object *obj)
 cpu->gic_num_lrs = 4;
 cpu->gic_vpribits = 5;
 cpu->gic_vprebits = 5;
-define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -203,7 +204,7 @@ static void aarch64_a53_initfn(Object *obj)
 cpu->gic_num_lrs = 4;
 cpu->gic_vpribits = 5;
 cpu->gic_vprebits = 5;
-define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -255,7 +256,60 @@ static void aarch64_a72_initfn(Object *obj)
 cpu->gic_num_lrs = 4;
 cpu->gic_vpribits = 5;
 cpu->gic_vprebits = 5;
-define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
+static void aarch64_a73_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+
+cpu->dtb_compatible = "arm,cortex-a73";
+set_feature(>env, ARM_FEATURE_V8);
+set_feature(>env, ARM_FEATURE_VFP4);
+set_feature(>env, ARM_FEATURE_NEON);
+set_feature(>env, ARM_FEATURE_GENERIC_TIMER);
+set_feature(>env, ARM_FEATURE_AARCH64);
+set_feature(>env, ARM_FEATURE_CBAR_RO);
+set_feature(>env, ARM_FEATURE_EL2);
+set_feature(>env, ARM_FEATURE_EL3);
+set_feature(>env, ARM_FEATURE_PMU);
+cpu->midr = 0x411fd090;
+cpu->revidr = 0x;
+cpu->reset_fpsid = 0x41034091;
+cpu->isar.mvfr0 = 0x10110222;
+cpu->isar.mvfr1 = 0x1211;
+cpu->isar.mvfr2 = 0x0043;
+cpu->ctr = 0x84448004;
+cpu->reset_sctlr = 0x00c50838;
+cpu->id_pfr0 = 0x00010131;
+cpu->id_pfr1 = 0x00011011;
+cpu->id_pfr2 = 0x0001;
+cpu->id_dfr0 = 0x03010066;
+cpu->id_afr0 = 0x;
+cpu->id_mmfr0 = 0x10201105;
+cpu->id_mmfr1 = 0x4000;
+cpu->id_mmfr2 = 0x0126;
+cpu->id_mmfr3 = 0x02102211;
+cpu->isar.id_isar0 = 0x02101110;
+cpu->isar.id_isar1 = 0x13112111;
+cpu->isar.id_isar2 = 0x21232042;
+cpu->isar.id_isar3 = 0x01112131;
+cpu->isar.id_isar4 = 0x00011142;
+cpu->isar.id_isar5 = 0x00011121;
+cpu->isar.id_aa64pfr0 = 0x1100ull;
+cpu->id_aa64dfr0 = 0x10305106;
+cpu->isar.id_aa64isar0 = 0x00011120;
+cpu->isar.id_aa64mmfr0 = 0x00101122;
+cpu->dbgdidr = 0x3516d000;
+cpu->clidr = 0x0a200023;
+cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+cpu->dcz_blocksize = 4; /* 64 bytes */
+cpu->gic_num_lrs = 4;
+cpu->gic_vpribits = 5;
+cpu->gic_vprebits = 5;
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
@@ -378,6 +432,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
+{ .name = "cortex-a73", .initfn = aarch64_a73_initfn },
 { .name = "max",

[Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert

2019-02-22 Thread Richard Henderson

Only perform the assert when both registers exist.
Extract the variables from ID_AA64DFR0_EL1 for AArch64.

Signed-off-by: Richard Henderson 
---
 target/arm/helper.c | 58 +
 1 file changed, 38 insertions(+), 20 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index fbdca9324b..1d8c8998c4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu)
 /* Define v7 and v8 architectural debug registers.
  * These are just dummy implementations for now.
  */
-int i;
-int wrps, brps, ctx_cmps;
-ARMCPRegInfo dbgdidr = {
-.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
-.access = PL0_R, .accessfn = access_tda,
-.type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
-};
+int i, wrps, brps, ctx_cmps;
+bool have_aa32;
 
-/* Note that all these register fields hold "number of Xs minus 1". */
-brps = extract32(cpu->dbgdidr, 24, 4);
-wrps = extract32(cpu->dbgdidr, 28, 4);
-ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
-
-assert(ctx_cmps <= brps);
-
-/* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
+/*
+ * The DBGDIDR and ID_AA64DFR0_EL1 define various properties
  * of the debug registers such as number of breakpoints;
  * check that if they both exist then they agree.
+ *
+ * Note that all these register fields hold "number of Xs minus 1".
  */
 if (arm_feature(>env, ARM_FEATURE_AARCH64)) {
-assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
-assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
-assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
-}
+brps = extract32(cpu->id_aa64dfr0, 12, 4);
+wrps = extract32(cpu->id_aa64dfr0, 20, 4);
+ctx_cmps = extract32(cpu->id_aa64dfr0, 28, 4);
 
-define_one_arm_cp_reg(cpu, );
+/*
+ * There are cpus with aarch32 only at EL0, and which do not
+ * have the 32-bit system registers.
+ */
+have_aa32
+= (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2 ||
+   FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >= 2 ||
+   FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >= 2);
+if (have_aa32) {
+assert(extract32(cpu->dbgdidr, 24, 4) == brps);
+assert(extract32(cpu->dbgdidr, 28, 4) == wrps);
+assert(extract32(cpu->dbgdidr, 20, 4) == ctx_cmps);
+}
+} else {
+have_aa32 = true;
+brps = extract32(cpu->dbgdidr, 24, 4);
+wrps = extract32(cpu->dbgdidr, 28, 4);
+ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
+}
+assert(ctx_cmps <= brps);
+
+if (have_aa32) {
+ARMCPRegInfo dbgdidr = {
+.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
+.opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda,
+.type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
+};
+define_one_arm_cp_reg(cpu, );
+}
 define_arm_cp_regs(cpu, debug_cp_reginfo);
 
 if (arm_feature(>env, ARM_FEATURE_LPAE)) {
-- 
2.17.2

[Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2

2019-02-22 Thread Richard Henderson

This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h| 1 +
 target/arm/helper.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 84ae6849c2..c57f8e9ba8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -863,6 +863,7 @@ struct ARMCPU {
 uint32_t reset_sctlr;
 uint32_t id_pfr0;
 uint32_t id_pfr1;
+uint32_t id_pfr2;
 uint32_t id_dfr0;
 uint64_t pmceid0;
 uint64_t pmceid1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a018eb23fe..8903cc13d8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
   .access = PL1_R, .type = ARM_CP_CONST,
   .resetvalue = 0 },
-{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+{ .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
   .access = PL1_R, .type = ARM_CP_CONST,
-  .resetvalue = 0 },
+  .resetvalue = cpu->id_pfr2 },
 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
   .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.17.2

[Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2

2019-02-22 Thread Richard Henderson

This was res0 before ARMv8.2, but will shortly be used by
new processor definitions.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h| 15 +++
 target/arm/helper.c |  4 ++--
 target/arm/kvm64.c  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c2899f0bed..02642a7db3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -855,6 +855,7 @@ struct ARMCPU {
 uint64_t id_aa64pfr1;
 uint64_t id_aa64mmfr0;
 uint64_t id_aa64mmfr1;
+uint64_t id_aa64mmfr2;
 } isar;
 uint32_t midr;
 uint32_t revidr;
@@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
 
+FIELD(ID_AA64MMFR2, CNP, 0, 4)
+FIELD(ID_AA64MMFR2, UAO, 4, 4)
+FIELD(ID_AA64MMFR2, LSM, 8, 4)
+FIELD(ID_AA64MMFR2, IESB, 12, 4)
+FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
+FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
+FIELD(ID_AA64MMFR2, NV, 24, 4)
+FIELD(ID_AA64MMFR2, ST, 28, 4)
+FIELD(ID_AA64MMFR2, AT, 32, 4)
+FIELD(ID_AA64MMFR2, IDS, 36, 4)
+FIELD(ID_AA64MMFR2, FWB, 40, 4)
+FIELD(ID_AA64MMFR2, TTL, 48, 4)
+FIELD(ID_AA64MMFR2, BBM, 52, 4)
+
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
 FIELD(ID_DFR0, MMAPDBG, 8, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8903cc13d8..fbdca9324b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
   .access = PL1_R, .type = ARM_CP_CONST,
   .resetvalue = cpu->isar.id_aa64mmfr1 },
-{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+{ .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
   .access = PL1_R, .type = ARM_CP_CONST,
-  .resetvalue = 0 },
+  .resetvalue = cpu->isar.id_aa64mmfr2 },
 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
   .access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index e3ba149248..c3d421b53b 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
   ARM64_SYS_REG(3, 0, 0, 7, 0));
 err |= read_sys_reg64(fdarray[2], >isar.id_aa64mmfr1,
   ARM64_SYS_REG(3, 0, 0, 7, 1));
+err |= read_sys_reg64(fdarray[2], >isar.id_aa64mmfr2,
+  ARM64_SYS_REG(3, 0, 0, 7, 2));
 
 /*
  * Note that if AArch32 support is not present in the host,
-- 
2.17.2

[Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76}

2019-02-22 Thread Richard Henderson

There have been several announcements since the a72.

The a75 and a76 entries are RFC because, while they boot with a 3.15
kernel, they do not boot with a 5.0-rc7 kernel.  I'm really not sure
where things have gone off the rails.  It'll take some more serious
tracing to figure out what went wrong.

I post this now mostly to get feedback on patch 5.  Should we do
more to elide *all* of the aa32 system registers for that case?


r~


Richard Henderson (6):
  target/arm: Implement ID_PFR2
  target/arm: Define cortex-a73
  target/arm: Implement ID_AA64MMFR2
  target/arm: Define cortex-a75
  target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert
  target/arm: Define cortex-a76

 target/arm/cpu.h|  18 +
 hw/arm/virt.c   |   3 +
 target/arm/cpu64.c  | 179 +++-
 target/arm/helper.c |  66 ++--
 target/arm/kvm64.c  |   2 +
 5 files changed, 240 insertions(+), 28 deletions(-)

-- 
2.17.2

[Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75

2019-02-22 Thread Richard Henderson

Signed-off-by: Richard Henderson 
---
 hw/arm/virt.c  |  1 +
 target/arm/cpu64.c | 58 ++
 2 files changed, 59 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index c69a734878..06a155724c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -174,6 +174,7 @@ static const char *valid_cpus[] = {
 ARM_CPU_TYPE_NAME("cortex-a57"),
 ARM_CPU_TYPE_NAME("cortex-a72"),
 ARM_CPU_TYPE_NAME("cortex-a73"),
+ARM_CPU_TYPE_NAME("cortex-a75"),
 ARM_CPU_TYPE_NAME("host"),
 ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index d34aa3af75..325e0ecf17 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj)
 define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
+static void aarch64_a75_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+
+cpu->dtb_compatible = "arm,cortex-a75";
+set_feature(>env, ARM_FEATURE_V8);
+set_feature(>env, ARM_FEATURE_VFP4);
+set_feature(>env, ARM_FEATURE_NEON);
+set_feature(>env, ARM_FEATURE_GENERIC_TIMER);
+set_feature(>env, ARM_FEATURE_AARCH64);
+set_feature(>env, ARM_FEATURE_CBAR_RO);
+set_feature(>env, ARM_FEATURE_EL2);
+set_feature(>env, ARM_FEATURE_EL3);
+set_feature(>env, ARM_FEATURE_PMU);
+cpu->midr = 0x413fd0a1;
+cpu->revidr = 0x;
+cpu->reset_fpsid = 0x410340a2;
+cpu->isar.mvfr0 = 0x10110222;
+cpu->isar.mvfr1 = 0x1321;
+cpu->isar.mvfr2 = 0x0043;
+cpu->ctr = 0x84448004;
+cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */
+cpu->id_pfr0 = 0x00010131;
+cpu->id_pfr1 = 0x00011011;
+cpu->id_pfr2 = 0x0001;
+cpu->id_dfr0 = 0x04010088;
+cpu->id_afr0 = 0x;
+cpu->id_mmfr0 = 0x10201105;
+cpu->id_mmfr1 = 0x4000;
+cpu->id_mmfr2 = 0x0126;
+cpu->id_mmfr3 = 0x02122211;
+cpu->isar.id_isar0 = 0x02101110;
+cpu->isar.id_isar1 = 0x13112111;
+cpu->isar.id_isar2 = 0x21232042;
+cpu->isar.id_isar3 = 0x01112131;
+cpu->isar.id_isar4 = 0x00011142;
+cpu->isar.id_isar5 = 0x00011121;
+cpu->isar.id_isar6 = 0x0010;
+cpu->isar.id_aa64pfr0 = 0x11001011ull;
+cpu->id_aa64dfr0 = 0x10305408;
+cpu->isar.id_aa64isar0 = 0x10211120;
+cpu->isar.id_aa64isar1 = 0x0011;
+cpu->isar.id_aa64mmfr0 = 0x00101124;
+cpu->isar.id_aa64mmfr1 = 0x10212122;
+cpu->isar.id_aa64mmfr2 = 0x1011;
+cpu->dbgdidr = 0x3518d000;
+cpu->clidr = 0x08200023;
+cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+cpu->dcz_blocksize = 4; /* 64 bytes */
+cpu->gic_num_lrs = 4;
+cpu->gic_vpribits = 5;
+cpu->gic_vprebits = 5;
+define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
 {
@@ -433,6 +490,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
 { .name = "cortex-a73", .initfn = aarch64_a73_initfn },
+{ .name = "cortex-a75", .initfn = aarch64_a75_initfn },
 { .name = "max",.initfn = aarch64_max_initfn },
 { .name = NULL }
 };
-- 
2.17.2

[Qemu-devel] Possible ppc64le regression in master?

2019-02-22 Thread Andrew Randrianasulu

Hello again.

I was trying to set up virtual ppc64le machine with some linux inside. First 
tried with qemu-3.1 on 32-bit host. It worked, but was slow-ish.

next I tred to compile latest qemu git (up to commit 
8eb29f1bf5a974dc4c11d2d1f5e7c7f7a62be116) on 64-bit Slackware, to get MTTCG 
acceleration.

qemu was successfully compiled with those CFLAGS:


CFLAGS=-O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g -O3 -march=native 
-mtune=native -Wno-maybe-uninitialized

but then when I tried to run it - console was fine, but X inside Alpine Linux 
was all striped!

Going back to 2.12+ compiled last year fixed this issue to me, X is back to 
normal.

I was using this guide:
https://buggy.link/2018/01/31/ppc64le-on-x86_64-qemu-full-system-emulation.html

Command lines tried:

root@slax:~/src/qemu# ppc64-softmmu/qemu-system-ppc64 -m 1024 -display 
sdl,gl=on -smp 3 -hda /mnt/alpine_disk.img -> corruption in X, console ok.

ppc64-softmmu/qemu-system-ppc64 -m 1024 -display sdl,gl=on -vga virtio -smp 3 
-M 
pseries-3.1 -hda /mnt/alpine_disk.img -> even console is blue!

root@slax:~/src/qemu# ppc64-softmmu/qemu-system-ppc64 -m 1024 -display 
sdl,gl=on -vga cirrus -smp 1 -M pseries-3.1 -hda /mnt/alpine_disk.img -> same 
blue screen even on console

root@slax:~/src/qemu# ppc64-softmmu/qemu-system-ppc64 -m 1024 -smp 4 -M 
pseries-3.1 -hda /mnt/alpine_disk.img - this defaulted to gtk UI, and  X was 
corrupted anyway :/

root@slax:~/src/qemu# ppc64-softmmu/qemu-system-ppc64 -m 1024 -display 
sdl,gl=on -smp 1 -M pseries-3.1 -hda /mnt/alpine_disk.img -g 1024x768x32 - nice 
big console with correct colors, but X still corrupt!

root@slax:~/src/qemu# qemu-system-ppc64 -m 1024 -display sdl,gl=on -smp 
3  -hda /mnt/alpine_disk.img -g 1024x768x32 -> old qemu still works OK, booted 
right now and compiling stuff.

Attached are files I modified on Alpine install - custom xorg.conf, .xinitrc 
and 
ash_history (so you can install same set of packages as I)

My host CPU is:
cat /proc/cpuinfo
processor   : 0
vendor_id   : AuthenticAMD
cpu family  : 21
model   : 2
model name  : AMD FX(tm)-4300 Quad-Core Processor
stepping: 0
microcode   : 0x6000852
cpu MHz : 3222.725
cache size  : 2048 KB
physical id : 0
siblings: 4
core id : 0
cpu cores   : 2
apicid  : 16
initial apicid  : 0
fpu : yes
fpu_exception   : yes
cpuid level : 13
wp  : yes
flags   : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov 
pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb 
rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf 
pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c 
lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch 
osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core 
perfctr_nb cpb hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save 
tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold
bugs: fxsave_leak sysret_ss_attrs null_seg spectre_v1 spectre_v2 
spec_store_bypass
bogomips: 7599.87
TLB size: 1536 4K pages
clflush size: 64
cache_alignment : 64
address sizes   : 48 bits physical, 48 bits virtual
power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro

so, with avx.

I'll try to recompile with less agressive optimizations, and if this will not 
help - bisect .

Thanks for attention.
apk update
apk upgrade
mc
apk ?
apk --help
apk lsit mc
apk list mc
apk add mc
apk list xorg
apk list xserver
apk list 
apk list perl
apk add perl pythong gcc git svn 
apk add perl python gcc git svn 
apk add perl python gcc git 
top
setup-xorg=base
setup-xorg-base
setup-udev
ps axv
killall -9 apk
apk lsit subversion
apk list subversion
apk add subversion
setup-xorg-base
apk list xfce
apk list fluxbox
apk app fluxbox
apk add fluxbox
apk list xterm
apk list term
apk list *term
apk list | grep term
apk add lxterminal
apk list | grep ffmpeg
apk add ffmpeg
startx
mcedit /etc/X11/xorg.conf
startx
mcedit /etc/X11/xorg.conf
startx
startx -depth 8
lspci
dmesg 
dmesg | grep drm
dmesg | grep boch
dmesg | grep bonch
dmesg | grep fb
apk add mplayer
apk add mpg123
apk add ogg123
apk add ogg321
apk add vorbis-tools
apk add vorbis
apk list | grep vorbis
apk add libvorbis-dev
apk list | grep fbset
apk add fbset
mcedit /etc/X11/xorg.conf
startx
X -configure
apk list | grep fbdev
apk add xf86-video-fbdev
X -configure
startx
apk list | grep xinit
mcedit .xinitrc
startx
apk list | grep xterm
apk list | grep menu
apk add dmenu
apk list | grep xfce
apk add xfce4
startx
mcedit .xinitrc 
startx
uptime
apk add xrandr
xrandr 
xdpyinfo
apk add xdpyinfo
apk list *-dev
apk add *-dev
apk --help
apk add libx11-dev-1.6.6-r0
apk add libx11-dev
apk add ffmpeg-dev
apk list firefox
apk list links
apk add links
apk add imlib2-dev
apk add libxml2-dev
mkdir src
apk add a52dec-dev
ls
cd src
links

[Qemu-devel] [PATCH 0/2] target/arm: Implement ARMv8.5-FRINT

2019-02-22 Thread Richard Henderson

Based-on: the ARMv8.2-FHM patch set, although I don't know that
this is an actual dependency; it's just the tree I started with.

There is not yet support for this extension within FVP, so I've
self-tested it against my own understanding of what is supposed
to go on with the file below.


r~


Richard Henderson (2):
  target/arm: Restructure handle_fp_1src_{single,double}
  target/arm: Implement ARMv8.5-FRINT

 target/arm/cpu.h   |   5 ++
 target/arm/helper.h|   5 ++
 target/arm/cpu64.c |   1 +
 target/arm/translate-a64.c | 161 ++---
 target/arm/vfp_helper.c|  96 ++
 5 files changed, 222 insertions(+), 46 deletions(-)

-- 

#include 
#include 

asm(".arch armv8.5-a");

static const float f32_i32_z[][2] = {
{ 0, 0 },
{ -0.0, -0.0 },
{ 0.9, 0.0 },
{ 1.0, 1.0 },
{ 1.1, 1.0 },
{ 1.9, 1.0 },
{ 0x1.fep30, 0x1.fep30 },   /* 2^31 - epsilon */
{ -0x1p31, -0x1.0p31 }, /* -2^31 = INT32_MIN */
{ 0x1.0p31, -0x1.0p31 },/* overflow */
{ 0x1.0p32, -0x1.0p31 },/* overflow */
{ -0x1.0p32, -0x1.0p31 },   /* overflow */
{ __builtin_inf(), -0x1.0p31 }, /* overflow */
};

static const double f64_i32_z[][2] = {
{ 0, 0 },
{ -0.0, -0.0 },
{ 0.9, 0.0 },
{ 1.0, 1.0 },
{ 1.1, 1.0 },
{ 1.9, 1.0 },
{ 2147483647, 2147483647 }, /* 2^31 - 1 = INT32_MAX */
{ -0x1p31, -0x1.0p31 }, /* -2^31 = INT32_MIN */
{ 0x1.0p31, -0x1.0p31 },/* overflow */
{ 0x1.0p32, -0x1.0p31 },/* overflow */
{ -0x1.0p32, -0x1.0p31 },   /* overflow */
{ __builtin_inf(), -0x1.0p31 }, /* overflow */
};

static const float f32_i64_z[][2] = {
{ 0, 0 },
{ -0.0, -0.0 },
{ 0.9, 0.0 },
{ 1.0, 1.0 },
{ 1.1, 1.0 },
{ 1.9, 1.0 },
{ 0x1.fep30, 0x1.fep30 },   /* 2^31 - epsilon */
{ -0x1p31, -0x1.0p31 }, /* -2^31 = INT32_MIN */
{ 0x1.0p31, 0x1.0p31 },
{ 0x1.0p32, 0x1.0p32 },
{ -0x1.0p32, -0x1.0p32 },
{ 0x1.0p62, 0x1.0p62 },
{ 0x1.fep62, 0x1.fep62 },   /* 2^63 - epsilon */
{ -0x1.0p63, -0x1.0p63 },   /* -2^63 = INT64_MIN */
{ 0x1.0p63, -0x1.0p63 },/* overflow */
{ 0x1.0p64, -0x1.0p63 },/* overflow */
{ -0x1.0p64, -0x1.0p63 },   /* overflow */
{ __builtin_inf(), -0x1.0p63 }, /* overflow */
};

static const double f64_i64_z[][2] = {
{ 0, 0 },
{ -0.0, -0.0 },
{ 0.9, 0.0 },
{ 1.0, 1.0 },
{ 1.1, 1.0 },
{ 1.9, 1.0 },
{ 2147483647, 2147483647 }, /* 2^31 - 1 = INT32_MAX */
{ -0x1p31, -0x1.0p31 }, /* -2^31 = INT32_MIN */
{ 0x1.0p31, 0x1.0p31 },
{ 0x1.0p32, 0x1.0p32 },
{ -0x1.0p32, -0x1.0p32 },
{ 0x1.0p62, 0x1.0p62 },
{ 0x1.fp62, 0x1.fp62 }, /* 2^63 - epsilon */
{ -0x1.0p63, -0x1.0p63 },   /* -2^63 = INT64_MIN */
{ 0x1.0p63, -0x1.0p63 },/* overflow */
{ 0x1.0p64, -0x1.0p63 },/* overflow */
{ -0x1.0p64, -0x1.0p63 },   /* overflow */
{ __builtin_inf(), -0x1.0p63 }, /* overflow */
};

int main()
{
int i;

for (i = 0; i < sizeof(f32_i32_z)/sizeof(f32_i32_z[0]); i++) {
float x;
asm("frint32z %s0,%s1" : "=w"(x) : "w"(f32_i32_z[i][0]));
if (x != f32_i32_z[i][1]) {
printf("%-2d: frint(%a) -> %a != %a\n",
   i, f32_i32_z[i][0], x, f32_i32_z[i][1]);
}
}

for (i = 0; i < sizeof(f32_i64_z)/sizeof(f32_i64_z[0]); i++) {
float x;
asm("frint64z %s0,%s1" : "=w"(x) : "w"(f32_i64_z[i][0]));
if (x != f32_i64_z[i][1]) {
printf("%-2d: frint(%a) -> %a != %a\n",
   i, f32_i64_z[i][0], x, f32_i64_z[i][1]);
}
}

for (i = 0; i < sizeof(f64_i32_z)/sizeof(f64_i32_z[0]); i++) {
double x;
asm("frint32z %d0,%d1" : "=w"(x) : "w"(f64_i32_z[i][0]));
if (x != f64_i32_z[i][1]) {
printf("%-2d: frint(%a) -> %a != %a\n",
   i, f64_i32_z[i][0], x, f64_i32_z[i][1]);
}
}

for (i = 0; i < sizeof(f64_i64_z)/sizeof(f64_i64_z[0]); i++) {
double x;
asm("frint64z %d0,%d1" : "=w"(x) : "w"(f64_i64_z[i][0]));
if (x != f64_i64_z[i][1]) {
printf("%-2d: frint(%a) -> %a != %a\n",
   i, f64_i64_z[i][0], x, f64_i64_z[i][1]);
}
}

return 0;
}

[Qemu-devel] [PATCH 1/2] target/arm: Restructure handle_fp_1src_{single, double}

2019-02-22 Thread Richard Henderson

This will allow sharing code that adjusts rmode beyond
the existing users.

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 90 +-
 1 file changed, 49 insertions(+), 41 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3c8eaf089..fcbf6b16cf 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5505,55 +5505,59 @@ static void handle_fp_1src_half(DisasContext *s, int 
opcode, int rd, int rn)
 /* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
+void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);
+TCGv_i32 tcg_op, tcg_res;
 TCGv_ptr fpst;
-TCGv_i32 tcg_op;
-TCGv_i32 tcg_res;
+int rmode = -1;
 
-fpst = get_fpstatus_ptr(false);
 tcg_op = read_fp_sreg(s, rn);
 tcg_res = tcg_temp_new_i32();
 
 switch (opcode) {
 case 0x0: /* FMOV */
 tcg_gen_mov_i32(tcg_res, tcg_op);
-break;
+goto done;
 case 0x1: /* FABS */
 gen_helper_vfp_abss(tcg_res, tcg_op);
-break;
+goto done;
 case 0x2: /* FNEG */
 gen_helper_vfp_negs(tcg_res, tcg_op);
-break;
+goto done;
 case 0x3: /* FSQRT */
 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
-break;
+goto done;
 case 0x8: /* FRINTN */
 case 0x9: /* FRINTP */
 case 0xa: /* FRINTM */
 case 0xb: /* FRINTZ */
 case 0xc: /* FRINTA */
-{
-TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-gen_helper_rints(tcg_res, tcg_op, fpst);
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-tcg_temp_free_i32(tcg_rmode);
+rmode = arm_rmode_to_sf(opcode & 7);
+gen_fpst = gen_helper_rints;
 break;
-}
 case 0xe: /* FRINTX */
-gen_helper_rints_exact(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rints_exact;
 break;
 case 0xf: /* FRINTI */
-gen_helper_rints(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rints;
 break;
 default:
-abort();
+g_assert_not_reached();
 }
 
-write_fp_sreg(s, rd, tcg_res);
-
+fpst = get_fpstatus_ptr(false);
+if (rmode >= 0) {
+TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+gen_fpst(tcg_res, tcg_op, fpst);
+gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+tcg_temp_free_i32(tcg_rmode);
+} else {
+gen_fpst(tcg_res, tcg_op, fpst);
+}
 tcg_temp_free_ptr(fpst);
+
+ done:
+write_fp_sreg(s, rd, tcg_res);
 tcg_temp_free_i32(tcg_op);
 tcg_temp_free_i32(tcg_res);
 }
@@ -5561,9 +5565,10 @@ static void handle_fp_1src_single(DisasContext *s, int 
opcode, int rd, int rn)
 /* Floating-point data-processing (1 source) - double precision */
 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
 {
+void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);
+TCGv_i64 tcg_op, tcg_res;
 TCGv_ptr fpst;
-TCGv_i64 tcg_op;
-TCGv_i64 tcg_res;
+int rmode = -1;
 
 switch (opcode) {
 case 0x0: /* FMOV */
@@ -5571,48 +5576,51 @@ static void handle_fp_1src_double(DisasContext *s, int 
opcode, int rd, int rn)
 return;
 }
 
-fpst = get_fpstatus_ptr(false);
 tcg_op = read_fp_dreg(s, rn);
 tcg_res = tcg_temp_new_i64();
 
 switch (opcode) {
 case 0x1: /* FABS */
 gen_helper_vfp_absd(tcg_res, tcg_op);
-break;
+goto done;
 case 0x2: /* FNEG */
 gen_helper_vfp_negd(tcg_res, tcg_op);
-break;
+goto done;
 case 0x3: /* FSQRT */
 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
-break;
+goto done;
 case 0x8: /* FRINTN */
 case 0x9: /* FRINTP */
 case 0xa: /* FRINTM */
 case 0xb: /* FRINTZ */
 case 0xc: /* FRINTA */
-{
-TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-gen_helper_rintd(tcg_res, tcg_op, fpst);
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-tcg_temp_free_i32(tcg_rmode);
+rmode = arm_rmode_to_sf(opcode & 7);
+gen_fpst = gen_helper_rintd;
 break;
-}
 case 0xe: /* FRINTX */
-gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rintd_exact;
 break;
 case 0xf: /* FRINTI */
-gen_helper_rintd(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rintd;
 break;
 default:
-abort();
+g_assert_not_reached();
 }
 
-write_fp_dreg(s, rd, tcg_res);
-
+fpst = get_fpstatus_ptr(false);
+if (rmode >= 0) {
+TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+

[Qemu-devel] [PATCH 2/2] target/arm: Implement ARMv8.5-FRINT

2019-02-22 Thread Richard Henderson

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  5 ++
 target/arm/helper.h|  5 ++
 target/arm/cpu64.c |  1 +
 target/arm/translate-a64.c | 71 ++--
 target/arm/vfp_helper.c| 96 ++
 5 files changed, 173 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9cf439fb8d..f60a2361fe 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3391,6 +3391,11 @@ static inline bool isar_feature_aa64_pauth(const 
ARMISARegisters *id)
  FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
 }
 
+static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
+}
+
 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
 {
 /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
diff --git a/target/arm/helper.h b/target/arm/helper.h
index d363904278..c978a1d812 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -686,6 +686,11 @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #include "helper-sve.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1b0c427277..645cc20eb6 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
+t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 cpu->isar.id_aa64isar1 = t;
 
 t = cpu->isar.id_aa64pfr0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fcbf6b16cf..139e500df8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5540,6 +5540,20 @@ static void handle_fp_1src_single(DisasContext *s, int 
opcode, int rd, int rn)
 case 0xf: /* FRINTI */
 gen_fpst = gen_helper_rints;
 break;
+case 0x10: /* FRINT32Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint32_s;
+break;
+case 0x11: /* FRINT32X */
+gen_fpst = gen_helper_frint32_s;
+break;
+case 0x12: /* FRINT64Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint64_s;
+break;
+case 0x13: /* FRINT64X */
+gen_fpst = gen_helper_frint64_s;
+break;
 default:
 g_assert_not_reached();
 }
@@ -5603,6 +5617,20 @@ static void handle_fp_1src_double(DisasContext *s, int 
opcode, int rd, int rn)
 case 0xf: /* FRINTI */
 gen_fpst = gen_helper_rintd;
 break;
+case 0x10: /* FRINT32Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint32_d;
+break;
+case 0x11: /* FRINT32X */
+gen_fpst = gen_helper_frint32_d;
+break;
+case 0x12: /* FRINT64Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint64_d;
+break;
+case 0x13: /* FRINT64X */
+gen_fpst = gen_helper_frint64_d;
+break;
 default:
 g_assert_not_reached();
 }
@@ -5739,6 +5767,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
 break;
 }
+
+case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
+if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
+unallocated_encoding(s);
+return;
+}
+/* fall through */
 case 0x0 ... 0x3:
 case 0x8 ... 0xc:
 case 0xe ... 0xf:
@@ -5748,14 +5783,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t 
insn)
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_single(s, opcode, rd, rn);
 break;
 case 1:
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_double(s, opcode, rd, rn);
 break;
 case 3:
@@ -5767,13 +5800,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t 
insn)
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_half(s, opcode, rd, rn);
 break;
 default:
 unallocated_encoding(s);
 }
 break;
+
 default:
 unallocated_encoding(s);
 break;
@@ -9301,6 +9334,14 @@ static void handle_2misc_64(DisasContext *s, int opcode, 
bool u,
 case 0x59: /* FRINTX */
 gen_helper_rintd_exact(tcg_rd, tcg_rn,

[Qemu-devel] Build error with git commit 8eb29f1bf5a974dc4c11d2d1f5e7c7f7a62be116 on x86_64

2019-02-22 Thread Andrew Randrianasulu

Hello!

I just pulled latest git

up to 
commit 8eb29f1bf5a974dc4c11d2d1f5e7c7f7a62be116 (HEAD -> master, origin/master, 
origin/HEAD)
Merge: a05838cb2a 2b6326c0bf
Author: Peter Maydell 
Date:   Fri Feb 22 15:48:04 2019 +

Merge remote-tracking branch 
'remotes/awilliam/tags/vfio-updates-20190221.0' 
into staging

VFIO updates 2019-02-21

 - Workaround kernel overflow bug in vfio type1 DMA unmap
   (Alex Williamson)

 - Refactor vfio container initialization (Eric Auger)

# gpg: Signature made Fri 22 Feb 2019 05:21:07 GMT
# gpg:using RSA key 239B9B6E3BB08B22
# gpg: Good signature from "Alex Williamson " 
[full]
# gpg: aka "Alex Williamson " [full]
# gpg: aka "Alex Williamson " [full]
# gpg: aka "Alex Williamson " 
[full]
# Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B  8A90 239B 9B6E 3BB0 
8B22

* remotes/awilliam/tags/vfio-updates-20190221.0:
  hw/vfio/common: Refactor container initialization
  vfio/common: Work around kernel overflow bug in DMA unmap

Signed-off-by: Peter Maydell 
-

and default build with simple ./configure on slackware 14.2 x86-64 box failed 
like this:

root@slax:~/src/qemu# LANG=C make -j 5
CHK version_gen.h
  CC  qobject/block-qdict.o
  CC  util/thread-pool.o
  CC  util/main-loop.o
  CC  util/qemu-timer.o
  CC  util/iohandler.o
  CC  util/aio-posix.o
qobject/block-qdict.c: In function 'qdict_array_split':
qobject/block-qdict.c:259:9: error: 'subqdict' may be used uninitialized in 
this 
function [-Werror=maybe-uninitialized]
 qlist_append_obj(*dst, subqobj ?: QOBJECT(subqdict));
 ^
  CC  util/compatfd.o
  CC  util/event_notifier-posix.o
cc1: all warnings being treated as errors
/root/src/qemu/rules.mak:69: recipe for target 'qobject/block-qdict.o' failed
make: *** [qobject/block-qdict.o] Error 1
make: *** Waiting for unfinished jobs


 LANG=C gcc --version
gcc (GCC) 5.5.0
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

---

[Qemu-devel] [PATCH v2 3/4] block/dirty-bitmaps: add block_dirty_bitmap_check function

2019-02-22 Thread John Snow

Instead of checking against busy, inconsistent, or read only directly,
use a check function with permissions bits that let us streamline the
checks without reproducing them in many places.

As a side effect, this adds consistency checks to all the QMP
interfaces for bitmap manipulation.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c   | 39 ---
 blockdev.c | 49 +++---
 include/block/dirty-bitmap.h   | 13 -
 migration/block-dirty-bitmap.c | 12 +++--
 nbd/server.c   |  3 +--
 5 files changed, 54 insertions(+), 62 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 4e8f931659..2e7fd81866 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -174,7 +174,7 @@ bool bdrv_dirty_bitmap_has_successor(BdrvDirtyBitmap 
*bitmap)
 return bitmap->successor;
 }
 
-bool bdrv_dirty_bitmap_busy(BdrvDirtyBitmap *bitmap) {
+static bool bdrv_dirty_bitmap_busy(BdrvDirtyBitmap *bitmap) {
 return bitmap->busy;
 }
 
@@ -235,6 +235,33 @@ static bool bdrv_dirty_bitmap_recording(BdrvDirtyBitmap 
*bitmap)
  !bitmap->successor->disabled);
 }
 
+int bdrv_dirty_bitmap_check(BdrvDirtyBitmap *bitmap, uint32_t flags,
+Error **errp)
+{
+if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
+error_setg(errp, "Bitmap '%s' is currently in use by another"
+   " operation and cannot be used", bitmap->name);
+return -1;
+}
+
+if ((flags & BDRV_BITMAP_RO) && bdrv_dirty_bitmap_readonly(bitmap)) {
+error_setg(errp, "Bitmap '%s' is readonly and cannot be modified",
+   bitmap->name);
+return -1;
+}
+
+if ((flags & BDRV_BITMAP_INCONSISTENT) &&
+bdrv_dirty_bitmap_inconsistent(bitmap)) {
+error_setg(errp, "Bitmap '%s' is inconsistent and cannot be used",
+   bitmap->name);
+error_append_hint(errp, "Try block-dirty-bitmap-remove to delete "
+  "this bitmap from disk");
+return -1;
+}
+
+return 0;
+}
+
 /**
  * Create a successor bitmap destined to replace this bitmap after an 
operation.
  * Requires that the bitmap is not user_locked and has no successor.
@@ -792,15 +819,7 @@ void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, const 
BdrvDirtyBitmap *src,
 
 qemu_mutex_lock(dest->mutex);
 
-if (bdrv_dirty_bitmap_busy(dest)) {
-error_setg(errp, "Bitmap '%s' is currently in use by another"
-" operation and cannot be modified", dest->name);
-goto out;
-}
-
-if (bdrv_dirty_bitmap_readonly(dest)) {
-error_setg(errp, "Bitmap '%s' is readonly and cannot be modified",
-   dest->name);
+if (bdrv_dirty_bitmap_check(dest, BDRV_BITMAP_DEFAULT, errp)) {
 goto out;
 }
 
diff --git a/blockdev.c b/blockdev.c
index cbce44877d..5d74479ba7 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -2007,11 +2007,7 @@ static void 
block_dirty_bitmap_clear_prepare(BlkActionState *common,
 return;
 }
 
-if (bdrv_dirty_bitmap_busy(state->bitmap)) {
-error_setg(errp, "Cannot modify a bitmap in use by another operation");
-return;
-} else if (bdrv_dirty_bitmap_readonly(state->bitmap)) {
-error_setg(errp, "Cannot clear a readonly bitmap");
+if (bdrv_dirty_bitmap_check(state->bitmap, BDRV_BITMAP_DEFAULT, errp)) {
 return;
 }
 
@@ -2056,10 +2052,7 @@ static void 
block_dirty_bitmap_enable_prepare(BlkActionState *common,
 return;
 }
 
-if (bdrv_dirty_bitmap_busy(state->bitmap)) {
-error_setg(errp,
-   "Bitmap '%s' is currently in use by another operation"
-   " and cannot be enabled", action->name);
+if (bdrv_dirty_bitmap_check(state->bitmap, BDRV_BITMAP_ALLOW_RO, errp)) {
 return;
 }
 
@@ -2097,10 +2090,7 @@ static void 
block_dirty_bitmap_disable_prepare(BlkActionState *common,
 return;
 }
 
-if (bdrv_dirty_bitmap_busy(state->bitmap)) {
-error_setg(errp,
-   "Bitmap '%s' is currently in use by another operation"
-   " and cannot be disabled", action->name);
+if (bdrv_dirty_bitmap_check(state->bitmap, BDRV_BITMAP_ALLOW_RO, errp)) {
 return;
 }
 
@@ -2891,10 +2881,7 @@ void qmp_block_dirty_bitmap_remove(const char *node, 
const char *name,
 return;
 }
 
-if (bdrv_dirty_bitmap_busy(bitmap)) {
-error_setg(errp,
-   "Bitmap '%s' is currently in use by another operation and"
-   " cannot be removed", name);
+if (bdrv_dirty_bitmap_check(bitmap, BDRV_BITMAP_BUSY, errp)) {
 return;
 }
 
@@ -2930,13 +2917,7 @@ void qmp_block_dirty_bitmap_clear(const char *node, 
const char *name,
 return;
 }
 
-if (bdrv_dirty_bitmap_busy(bitmap)) {
-

[Qemu-devel] [PATCH v2 4/4] block/dirty-bitmaps: implement inconsistent bit

2019-02-22 Thread John Snow

Set the inconsistent bit on load instead of rejecting such bitmaps.
There is no way to un-set it; the only option is to delete it.

Obvervations:
- bitmap loading does not need to update the header for in_use bitmaps.
- inconsistent bitmaps don't need to have their data loaded; they're
  glorified corruption sentinels.
- bitmap saving does not need to save inconsistent bitmaps back to disk.
- bitmap reopening DOES need to drop the readonly flag from inconsistent
  bitmaps to allow reopening of qcow2 files with non-qemu-owned bitmaps
  being eventually flushed back to disk.

Signed-off-by: John Snow 
---
 block/qcow2-bitmap.c | 77 +++-
 1 file changed, 40 insertions(+), 37 deletions(-)

diff --git a/block/qcow2-bitmap.c b/block/qcow2-bitmap.c
index 3ee524da4b..d1cc11da88 100644
--- a/block/qcow2-bitmap.c
+++ b/block/qcow2-bitmap.c
@@ -343,9 +343,15 @@ static BdrvDirtyBitmap *load_bitmap(BlockDriverState *bs,
 uint32_t granularity;
 BdrvDirtyBitmap *bitmap = NULL;
 
+granularity = 1U << bm->granularity_bits;
+bitmap = bdrv_create_dirty_bitmap(bs, granularity, bm->name, errp);
+if (bitmap == NULL) {
+goto fail;
+}
+
 if (bm->flags & BME_FLAG_IN_USE) {
-error_setg(errp, "Bitmap '%s' is in use", bm->name);
-goto fail;
+/* Data is unusable, skip loading it */
+return bitmap;
 }
 
 ret = bitmap_table_load(bs, >table, _table);
@@ -356,12 +362,6 @@ static BdrvDirtyBitmap *load_bitmap(BlockDriverState *bs,
 goto fail;
 }
 
-granularity = 1U << bm->granularity_bits;
-bitmap = bdrv_create_dirty_bitmap(bs, granularity, bm->name, errp);
-if (bitmap == NULL) {
-goto fail;
-}
-
 ret = load_bitmap_data(bs, bitmap_table, bm->table.size, bitmap);
 if (ret < 0) {
 error_setg_errno(errp, -ret, "Could not read bitmap '%s' from image",
@@ -949,6 +949,7 @@ bool qcow2_load_dirty_bitmaps(BlockDriverState *bs, Error 
**errp)
 Qcow2Bitmap *bm;
 GSList *created_dirty_bitmaps = NULL;
 bool header_updated = false;
+bool needs_update = false;
 
 if (s->nb_bitmaps == 0) {
 /* No bitmaps - nothing to do */
@@ -962,23 +963,27 @@ bool qcow2_load_dirty_bitmaps(BlockDriverState *bs, Error 
**errp)
 }
 
 QSIMPLEQ_FOREACH(bm, bm_list, entry) {
-if (!(bm->flags & BME_FLAG_IN_USE)) {
-BdrvDirtyBitmap *bitmap = load_bitmap(bs, bm, errp);
-if (bitmap == NULL) {
-goto fail;
-}
+BdrvDirtyBitmap *bitmap = load_bitmap(bs, bm, errp);
+if (bitmap == NULL) {
+goto fail;
+}
 
-if (!(bm->flags & BME_FLAG_AUTO)) {
-bdrv_disable_dirty_bitmap(bitmap);
-}
-bdrv_dirty_bitmap_set_persistance(bitmap, true);
+if (bm->flags & BME_FLAG_IN_USE) {
+bdrv_dirty_bitmap_set_inconsistent(bitmap);
+} else {
+/* NB: updated flags only get written if can_write(bs) is true. */
 bm->flags |= BME_FLAG_IN_USE;
-created_dirty_bitmaps =
-g_slist_append(created_dirty_bitmaps, bitmap);
+needs_update = true;
 }
+if (!(bm->flags & BME_FLAG_AUTO)) {
+bdrv_disable_dirty_bitmap(bitmap);
+}
+bdrv_dirty_bitmap_set_persistance(bitmap, true);
+created_dirty_bitmaps =
+g_slist_append(created_dirty_bitmaps, bitmap);
 }
 
-if (created_dirty_bitmaps != NULL) {
+if (needs_update) {
 if (can_write(bs)) {
 /* in_use flags must be updated */
 int ret = update_ext_header_and_dir_in_place(bs, bm_list);
@@ -1112,23 +1117,21 @@ int qcow2_reopen_bitmaps_rw_hint(BlockDriverState *bs, 
bool *header_updated,
 }
 
 QSIMPLEQ_FOREACH(bm, bm_list, entry) {
-if (!(bm->flags & BME_FLAG_IN_USE)) {
-BdrvDirtyBitmap *bitmap = bdrv_find_dirty_bitmap(bs, bm->name);
-if (bitmap == NULL) {
-continue;
-}
-
-if (!bdrv_dirty_bitmap_readonly(bitmap)) {
-error_setg(errp, "Bitmap %s is not readonly but not marked"
- "'IN_USE' in the image. Something went wrong,"
- "all the bitmaps may be corrupted", bm->name);
-ret = -EINVAL;
-goto out;
-}
+BdrvDirtyBitmap *bitmap = bdrv_find_dirty_bitmap(bs, bm->name);
+if (bitmap == NULL) {
+continue;
+}
 
-bm->flags |= BME_FLAG_IN_USE;
-ro_dirty_bitmaps = g_slist_append(ro_dirty_bitmaps, bitmap);
+if (!bdrv_dirty_bitmap_readonly(bitmap)) {
+error_setg(errp, "Bitmap %s was loaded prior to rw-reopen, but was 
"
+   "not marked as readonly. This is a bug, something went "
+   "wrong. All of the bitmaps may be corrupted", bm->name);

[Qemu-devel] [PATCH v2 1/4] block/dirty-bitmaps: add inconsistent bit

2019-02-22 Thread John Snow

Add an inconsistent bit to dirty-bitmaps that allows us to report a bitmap as
persistent but potentially inconsistent, i.e. if we find bitmaps on a qcow2
that have been marked as "in use".

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c | 19 +++
 include/block/dirty-bitmap.h |  2 ++
 qapi/block-core.json |  8 ++--
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 86c3b87ab9..9042c04788 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -46,6 +46,9 @@ struct BdrvDirtyBitmap {
and this bitmap must remain unchanged while
this flag is set. */
 bool persistent;/* bitmap must be saved to owner disk image */
+bool inconsistent;  /* bitmap is persistent, but not owned by QEMU.
+ * It cannot be used at all in any way, except
+ * a QMP user can remove it. */
 bool migration; /* Bitmap is selected for migration, it should
not be stored on the next inactivation
(persistent flag doesn't matter until next
@@ -462,6 +465,8 @@ BlockDirtyInfoList 
*bdrv_query_dirty_bitmaps(BlockDriverState *bs)
 info->recording = bdrv_dirty_bitmap_recording(bm);
 info->busy = bdrv_dirty_bitmap_busy(bm);
 info->persistent = bm->persistent;
+info->has_inconsistent = bm->inconsistent;
+info->inconsistent = bm->inconsistent;
 entry->value = info;
 *plist = entry;
 plist = >next;
@@ -709,6 +714,15 @@ void bdrv_dirty_bitmap_set_persistance(BdrvDirtyBitmap 
*bitmap, bool persistent)
 qemu_mutex_unlock(bitmap->mutex);
 }
 
+/* Called with BQL taken. */
+void bdrv_dirty_bitmap_set_inconsistent(BdrvDirtyBitmap *bitmap)
+{
+qemu_mutex_lock(bitmap->mutex);
+bitmap->inconsistent = true;
+bitmap->disabled = true;
+qemu_mutex_unlock(bitmap->mutex);
+}
+
 /* Called with BQL taken. */
 void bdrv_dirty_bitmap_set_migration(BdrvDirtyBitmap *bitmap, bool migration)
 {
@@ -722,6 +736,11 @@ bool bdrv_dirty_bitmap_get_persistance(BdrvDirtyBitmap 
*bitmap)
 return bitmap->persistent && !bitmap->migration;
 }
 
+bool bdrv_dirty_bitmap_inconsistent(BdrvDirtyBitmap *bitmap)
+{
+return bitmap->inconsistent;
+}
+
 bool bdrv_has_changed_persistent_bitmaps(BlockDriverState *bs)
 {
 BdrvDirtyBitmap *bm;
diff --git a/include/block/dirty-bitmap.h b/include/block/dirty-bitmap.h
index ba8477b73f..b270773f7e 100644
--- a/include/block/dirty-bitmap.h
+++ b/include/block/dirty-bitmap.h
@@ -68,6 +68,7 @@ void bdrv_dirty_bitmap_deserialize_finish(BdrvDirtyBitmap 
*bitmap);
 void bdrv_dirty_bitmap_set_readonly(BdrvDirtyBitmap *bitmap, bool value);
 void bdrv_dirty_bitmap_set_persistance(BdrvDirtyBitmap *bitmap,
bool persistent);
+void bdrv_dirty_bitmap_set_inconsistent(BdrvDirtyBitmap *bitmap);
 void bdrv_dirty_bitmap_set_busy(BdrvDirtyBitmap *bitmap, bool busy);
 void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, const BdrvDirtyBitmap *src,
  HBitmap **backup, Error **errp);
@@ -91,6 +92,7 @@ bool bdrv_dirty_bitmap_readonly(const BdrvDirtyBitmap 
*bitmap);
 bool bdrv_has_readonly_bitmaps(BlockDriverState *bs);
 bool bdrv_dirty_bitmap_get_autoload(const BdrvDirtyBitmap *bitmap);
 bool bdrv_dirty_bitmap_get_persistance(BdrvDirtyBitmap *bitmap);
+bool bdrv_dirty_bitmap_inconsistent(BdrvDirtyBitmap *bitmap);
 bool bdrv_dirty_bitmap_busy(BdrvDirtyBitmap *bitmap);
 bool bdrv_has_changed_persistent_bitmaps(BlockDriverState *bs);
 BdrvDirtyBitmap *bdrv_dirty_bitmap_next(BlockDriverState *bs,
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 6e543594b3..a7209fce22 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -470,12 +470,16 @@
 # @persistent: true if the bitmap will eventually be flushed to persistent
 #  storage (since 4.0)
 #
+# @inconsistent: true if this is a persistent bitmap that QEMU does not own.
+#Implies @recording and @busy to be false. To reclaim
+#ownership, use @block-dirty-bitmap-remove. (since 4.0)
+#
 # Since: 1.3
 ##
 { 'struct': 'BlockDirtyInfo',
   'data': {'*name': 'str', 'count': 'int', 'granularity': 'uint32',
-   'recording': 'bool', 'busy': 'bool',
-   'status': 'DirtyBitmapStatus', 'persistent': 'bool' } }
+   'recording': 'bool', 'busy': 'bool', 'status': 'DirtyBitmapStatus',
+   'persistent': 'bool', '*inconsistent': 'bool' } }
 
 ##
 # @Qcow2BitmapInfoFlags:
-- 
2.17.2

[Qemu-devel] [PATCH v2 2/4] block/dirty-bitmap: add inconsistent status

2019-02-22 Thread John Snow

Even though the status field is deprecated, we still have to support
it for a few more releases. Since this is a very new kind of bitmap
state, it makes sense for it to have its own status field.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c | 7 ++-
 qapi/block-core.json | 7 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 9042c04788..4e8f931659 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -209,10 +209,15 @@ bool bdrv_dirty_bitmap_enabled(BdrvDirtyBitmap *bitmap)
  *   or it can be Disabled and not recording writes.
  * (4) Locked:   Whether Active or Disabled, the user cannot modify this bitmap
  *   in any way from the monitor.
+ * (5) Inconsistent: This is a persistent bitmap whose "in use" bit is set, and
+ *   is unusable by QEMU. It can be deleted to remove it from
+ *   the qcow2.
  */
 DirtyBitmapStatus bdrv_dirty_bitmap_status(BdrvDirtyBitmap *bitmap)
 {
-if (bdrv_dirty_bitmap_has_successor(bitmap)) {
+if (bdrv_dirty_bitmap_inconsistent(bitmap)) {
+return DIRTY_BITMAP_STATUS_INCONSISTENT;
+} else if (bdrv_dirty_bitmap_has_successor(bitmap)) {
 return DIRTY_BITMAP_STATUS_FROZEN;
 } else if (bdrv_dirty_bitmap_busy(bitmap)) {
 return DIRTY_BITMAP_STATUS_LOCKED;
diff --git a/qapi/block-core.json b/qapi/block-core.json
index a7209fce22..b25ca6a6c1 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -442,10 +442,15 @@
 #  recording new writes. If the bitmap was @disabled, it is not
 #  recording new writes. (Since 2.12)
 #
+# @inconsistent: This is a persistent dirty bitmap that was marked in-use on
+#disk, and is unusable by QEMU. It can only be deleted.
+#Please rely on the inconsistent field in @BlockDirtyInfo
+#instead, as the status field is deprecated. (Since 4.0)
+#
 # Since: 2.4
 ##
 { 'enum': 'DirtyBitmapStatus',
-  'data': ['active', 'disabled', 'frozen', 'locked'] }
+  'data': ['active', 'disabled', 'frozen', 'locked', 'inconsistent'] }
 
 ##
 # @BlockDirtyInfo:
-- 
2.17.2

[Qemu-devel] [PATCH v2 0/4] bitmaps: add inconsistent bit

2019-02-22 Thread John Snow

Allow QEMU to read in bitmaps that have the in-use bit set, for the
purposes of allowing users to delete those bitmaps.

This is chosen in preference to a hard error on load to minimize
impact for a non-critical error, but to force the user or management
utility to acknowledge that the bitmap is no longer viable.

Requires: [PATCH v3 00/10] dirty-bitmaps: deprecate @status field

John Snow (4):
  block/dirty-bitmaps: add inconsistent bit
  block/dirty-bitmap: add inconsistent status
  block/dirty-bitmaps: add block_dirty_bitmap_check function
  block/dirty-bitmaps: implement inconsistent bit

 block/dirty-bitmap.c   | 65 +++-
 block/qcow2-bitmap.c   | 77 ++
 blockdev.c | 49 --
 include/block/dirty-bitmap.h   | 15 ++-
 migration/block-dirty-bitmap.c | 12 ++
 nbd/server.c   |  3 +-
 qapi/block-core.json   | 15 +--
 7 files changed, 133 insertions(+), 103 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH] hw/arm/stellaris: Implement watchdog timer

2019-02-22 Thread michelheily

From: Michel Heily 

Signed-off-by: Michel Heily 
---
 hw/arm/stellaris.c | 260 -
 1 file changed, 258 insertions(+), 2 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 442529c..08baeb2 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -348,6 +348,241 @@ static void stellaris_gptm_init(Object *obj)
 }
 
 
+/* Hardware watchdog. */
+
+#define TYPE_STELLARIS_WDTIMER "stellaris-wdtimer"
+#define STELLARIS_WDTIMER(obj) \
+OBJECT_CHECK(wdtimer_state, (obj), TYPE_STELLARIS_WDTIMER)
+
+typedef struct wdtimer_state {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+uint32_t control;
+uint32_t load;
+uint32_t tick;
+uint32_t state;
+uint32_t mask;
+uint32_t stage;
+bool locked;
+bool reset;
+
+struct wdtimer_state *opaque;
+QEMUTimer *timer;
+qemu_irq irq;
+} wdtimer_state;
+
+static void wdtimer_reset(wdtimer_state *s)
+{
+s->load = 0x;
+s->tick = 0x;
+s->state = 0;
+s->mask = 0;
+s->locked = false;
+s->reset = false;
+s->stage = 1;
+}
+
+static void wdtimer_update_irq(wdtimer_state *s)
+{
+int level;
+level = (s->state & s->mask) != 0;
+qemu_set_irq(s->irq, level);
+}
+
+
+static void wdtimer_reload(wdtimer_state *s, uint32_t stage)
+{
+s->stage = stage;
+
+uint64_t tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+timer_mod(s->timer, tick + s->load * system_clock_scale);
+}
+
+static void wdtimer_expired(void *opaque)
+{
+wdtimer_state **p = (wdtimer_state **)opaque;
+wdtimer_state *s;
+
+s = *p;
+
+if (s->mask & 1) {
+s->state = 1; /* assert IRQ */
+wdtimer_update_irq(s);
+}
+
+if (s->stage == 1) {
+wdtimer_reload(s, 2);
+
+} else if (s->stage == 2) {
+if (s->reset && (s->state & s->mask) != 0) {
+qemu_log_mask(CPU_LOG_RESET,
+  "WDT: system reset on 2nd time-out\n");
+wdtimer_reset(s);
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_PANIC);
+} else {
+wdtimer_reload(s, 1);
+}
+}
+}
+
+/* WDT offsets */
+#define WDT_O_LOAD  0x
+#define WDT_O_VALUE 0x0004
+#define WDT_O_CTL   0x0008
+#define WDT_O_ICR   0x000C
+#define WDT_O_RIS   0x0010
+#define WDT_O_MIS   0x0014
+#define WDT_O_TEST  0x0418
+#define WDT_O_LOCK  0x0C00
+#define WDT_O_PeriphID4 0x0FD0
+#define WDT_O_PeriphID5 0x0FD4
+#define WDT_O_PeriphID6 0x0FD8
+#define WDT_O_PeriphID7 0x0FDC
+#define WDT_O_PeriphID0 0x0FE0
+#define WDT_O_PeriphID1 0x0FE4
+#define WDT_O_PeriphID2 0x0FE8
+#define WDT_O_PeriphID3 0x0FEC
+#define WDT_O_PCellID0  0x0FF0
+#define WDT_O_PCellID1  0x0FF4
+#define WDT_O_PCellID2  0x0FF8
+#define WDT_O_PCellID3  0x0FFC
+
+static uint64_t wdtimer_read(void *opaque, hwaddr offset,
+  unsigned size)
+{
+wdtimer_state *s = (wdtimer_state *)opaque;
+
+switch (offset) {
+case WDT_O_LOAD:
+return s->load;
+case WDT_O_VALUE:
+return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+case WDT_O_CTL:
+return s->control;
+case WDT_O_RIS:
+return s->state;
+case WDT_O_MIS:
+return s->state & s->mask;
+case WDT_O_TEST:
+qemu_log_mask(LOG_UNIMP,
+  "WDT: stall not implemented\n");
+return 0;
+case WDT_O_LOCK:
+return s->locked ? 1 : 0;
+case WDT_O_PeriphID4: /* fallthrough */
+case WDT_O_PeriphID5:
+case WDT_O_PeriphID6:
+case WDT_O_PeriphID7:
+case WDT_O_PeriphID0:
+case WDT_O_PeriphID1:
+case WDT_O_PeriphID2:
+case WDT_O_PeriphID3:
+qemu_log_mask(LOG_UNIMP,
+  "WDT: Peripheral identification not implemented\n");
+return 0;
+case WDT_O_PCellID0:
+case WDT_O_PCellID1:
+case WDT_O_PCellID2:
+case WDT_O_PCellID3:
+qemu_log_mask(LOG_UNIMP,
+  "WDT: PrimieCell identification not implemented\n");
+return 0;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "WDT: read at bad offset 0x02%" HWADDR_PRIx "\n",
+  offset);
+return 0;
+}
+}
+
+static void wdtimer_write(void *opaque, hwaddr offset,
+   uint64_t value, unsigned size)
+{
+wdtimer_state *s = (wdtimer_state *)opaque;
+
+if (s->locked) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "WDT: write to watchdog registers in locked state\n");
+wdtimer_update_irq(s);
+return;
+}
+
+switch (offset) {
+case WDT_O_LOAD:
+s->load = value;
+wdtimer_reload(s, 1);
+break;
+case

[Qemu-devel] [PATCH v3 03/10] block/dirty-bitmap: remove set/reset assertions against enabled bit

2019-02-22 Thread John Snow

bdrv_set_dirty_bitmap and bdrv_reset_dirty_bitmap are only used as an
internal API by the mirror and migration areas of our code. These
calls modify the bitmap, but do so at the behest of QEMU and not the
guest.

Presently, these bitmaps are always "enabled" anyway, but there's no
reason they have to be.

Modify these internal APIs to drop this assertion.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index aa3f86bb73..9ea5738420 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -542,7 +542,6 @@ int64_t bdrv_dirty_iter_next(BdrvDirtyBitmapIter *iter)
 void bdrv_set_dirty_bitmap_locked(BdrvDirtyBitmap *bitmap,
   int64_t offset, int64_t bytes)
 {
-assert(bdrv_dirty_bitmap_enabled(bitmap));
 assert(!bdrv_dirty_bitmap_readonly(bitmap));
 hbitmap_set(bitmap->bitmap, offset, bytes);
 }
@@ -559,7 +558,6 @@ void bdrv_set_dirty_bitmap(BdrvDirtyBitmap *bitmap,
 void bdrv_reset_dirty_bitmap_locked(BdrvDirtyBitmap *bitmap,
 int64_t offset, int64_t bytes)
 {
-assert(bdrv_dirty_bitmap_enabled(bitmap));
 assert(!bdrv_dirty_bitmap_readonly(bitmap));
 hbitmap_reset(bitmap->bitmap, offset, bytes);
 }
-- 
2.17.2

[Qemu-devel] [PATCH v3 10/10] iotests: add busy/recording bit test to 124

2019-02-22 Thread John Snow

This adds a simple test that ensures the busy bit works for push backups,
as well as doubling as bonus test for incremental backups that get interrupted
by EIO errors.

Recording bit tests are already handled sufficiently by 236.

Signed-off-by: John Snow 
---
 tests/qemu-iotests/124 | 110 +
 tests/qemu-iotests/124.out |   4 +-
 2 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/tests/qemu-iotests/124 b/tests/qemu-iotests/124
index 5aa1bf1bd6..30f12a2202 100755
--- a/tests/qemu-iotests/124
+++ b/tests/qemu-iotests/124
@@ -634,6 +634,116 @@ class 
TestIncrementalBackupBlkdebug(TestIncrementalBackupBase):
 self.vm.shutdown()
 self.check_backups()
 
+def test_incremental_pause(self):
+"""
+Test an incremental backup that errors into a pause and is resumed.
+"""
+
+drive0 = self.drives[0]
+result = self.vm.qmp('blockdev-add',
+ node_name=drive0['id'],
+ driver=drive0['fmt'],
+ file={
+ 'driver': 'blkdebug',
+ 'image': {
+ 'driver': 'file',
+ 'filename': drive0['file']
+ },
+ 'set-state': [{
+ 'event': 'flush_to_disk',
+ 'state': 1,
+ 'new_state': 2
+ },{
+ 'event': 'read_aio',
+ 'state': 2,
+ 'new_state': 3
+ }],
+ 'inject-error': [{
+ 'event': 'read_aio',
+ 'errno': 5,
+ 'state': 3,
+ 'immediately': False,
+ 'once': True
+ }],
+ })
+self.assert_qmp(result, 'return', {})
+self.create_anchor_backup(drive0)
+bitmap = self.add_bitmap('bitmap0', drive0)
+
+# Emulate guest activity
+self.hmp_io_writes(drive0['id'], (('0xab', 0, 512),
+  ('0xfe', '16M', '256k'),
+  ('0x64', '32736k', '64k')))
+
+# For the purposes of query-block visibility of bitmaps, add a drive
+# frontend after we've written data; otherwise we can't use hmp-io
+result = self.vm.qmp("device_add",
+ id="device0",
+ drive=drive0['id'],
+ driver="virtio-blk")
+self.assert_qmp(result, 'return', {})
+
+# Bitmap Status Check
+query = self.vm.qmp('query-block')
+ret = [bmap for bmap in query['return'][0]['dirty-bitmaps']
+   if bmap.get('name') == bitmap.name][0]
+self.assert_qmp(ret, 'count', 458752)
+self.assert_qmp(ret, 'granularity', 65536)
+self.assert_qmp(ret, 'status', 'active')
+self.assert_qmp(ret, 'busy', False)
+self.assert_qmp(ret, 'recording', True)
+
+# Start backup
+parent, _ = bitmap.last_target()
+target = self.prepare_backup(bitmap, parent)
+res = self.vm.qmp('drive-backup',
+  job_id=bitmap.drive['id'],
+  device=bitmap.drive['id'],
+  sync='incremental',
+  bitmap=bitmap.name,
+  format=bitmap.drive['fmt'],
+  target=target,
+  mode='existing',
+  on_source_error='stop')
+self.assert_qmp(res, 'return', {})
+
+# Wait for the error
+event = self.vm.event_wait(name="BLOCK_JOB_ERROR",
+   
match={"data":{"device":bitmap.drive['id']}})
+self.assert_qmp(event, 'data', {'device': bitmap.drive['id'],
+'action': 'stop',
+'operation': 'read'})
+
+# Bitmap Status Check
+query = self.vm.qmp('query-block')
+ret = [bmap for bmap in query['return'][0]['dirty-bitmaps']
+   if bmap.get('name') == bitmap.name][0]
+self.assert_qmp(ret, 'count', 458752)
+self.assert_qmp(ret, 'granularity', 65536)
+self.assert_qmp(ret, 'status', 'frozen')
+self.assert_qmp(ret, 'busy', True)
+self.assert_qmp(ret, 'recording', True)
+
+# Resume and check incremental backup for consistency
+res = self.vm.qmp('block-job-resume', device=bitmap.drive['id'])
+self.assert_qmp(res,

[Qemu-devel] [PATCH v3 08/10] block/dirty-bitmaps: move comment block

2019-02-22 Thread John Snow

Simply move the big status enum comment block to above the status
function, and document it as being deprecated. The whole confusing
block can get deleted in three releases time.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c | 36 +++-
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index b3627b0d8c..86c3b87ab9 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -28,22 +28,6 @@
 #include "block/block_int.h"
 #include "block/blockjob.h"
 
-/**
- * A BdrvDirtyBitmap can be in four possible user-visible states:
- * (1) Active:   successor is NULL, and disabled is false: full r/w mode
- * (2) Disabled: successor is NULL, and disabled is true: qualified r/w mode,
- *   guest writes are dropped, but monitor writes are possible,
- *   through commands like merge and clear.
- * (3) Frozen:   successor is not NULL.
- *   A frozen bitmap cannot be renamed, deleted, cleared, set,
- *   enabled, merged to, etc. A frozen bitmap can only abdicate()
- *   or reclaim().
- *   In this state, the anonymous successor bitmap may be either
- *   Active and recording writes from the guest (e.g. backup jobs),
- *   but it can be Disabled and not recording writes.
- * (4) Locked:   Whether Active or Disabled, the user cannot modify this bitmap
- *   in any way from the monitor.
- */
 struct BdrvDirtyBitmap {
 QemuMutex *mutex;
 HBitmap *bitmap;/* Dirty bitmap implementation */
@@ -204,7 +188,25 @@ bool bdrv_dirty_bitmap_enabled(BdrvDirtyBitmap *bitmap)
 return !bitmap->disabled;
 }
 
-/* Called with BQL taken.  */
+/**
+ * bdrv_dirty_bitmap_status: This API is now deprecated.
+ * Called with BQL taken.
+ *
+ * A BdrvDirtyBitmap can be in four possible user-visible states:
+ * (1) Active:   successor is NULL, and disabled is false: full r/w mode
+ * (2) Disabled: successor is NULL, and disabled is true: qualified r/w mode,
+ *   guest writes are dropped, but monitor writes are possible,
+ *   through commands like merge and clear.
+ * (3) Frozen:   successor is not NULL.
+ *   A frozen bitmap cannot be renamed, deleted, cleared, set,
+ *   enabled, merged to, etc. A frozen bitmap can only abdicate()
+ *   or reclaim().
+ *   In this state, the anonymous successor bitmap may be either
+ *   Active and recording writes from the guest (e.g. backup jobs),
+ *   or it can be Disabled and not recording writes.
+ * (4) Locked:   Whether Active or Disabled, the user cannot modify this bitmap
+ *   in any way from the monitor.
+ */
 DirtyBitmapStatus bdrv_dirty_bitmap_status(BdrvDirtyBitmap *bitmap)
 {
 if (bdrv_dirty_bitmap_has_successor(bitmap)) {
-- 
2.17.2

[Qemu-devel] [PATCH v3 09/10] blockdev: remove unused paio parameter documentation

2019-02-22 Thread John Snow

This field isn't present anymore.

Signed-off-by: John Snow 
---
 blockdev.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/blockdev.c b/blockdev.c
index 1aaadb6128..cbce44877d 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1255,7 +1255,6 @@ out_aio_context:
  * @node: The name of the BDS node to search for bitmaps
  * @name: The name of the bitmap to search for
  * @pbs: Output pointer for BDS lookup, if desired. Can be NULL.
- * @paio: Output pointer for aio_context acquisition, if desired. Can be NULL.
  * @errp: Output pointer for error information. Can be NULL.
  *
  * @return: A bitmap object on success, or NULL on failure.
-- 
2.17.2

[Qemu-devel] [PATCH v3 07/10] block/dirty-bitmaps: unify qmp_locked and user_locked calls

2019-02-22 Thread John Snow

These mean the same thing now. Unify them and rename the merged call
bdrv_dirty_bitmap_busy to indicate semantically what we are describing,
as well as help disambiguate from the various _locked and _unlocked
versions of bitmap helpers that refer to mutex locks.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c   | 40 +++---
 blockdev.c | 18 +++
 include/block/dirty-bitmap.h   |  5 ++---
 migration/block-dirty-bitmap.c |  6 ++---
 nbd/server.c   |  6 ++---
 5 files changed, 34 insertions(+), 41 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index d92a269753..b3627b0d8c 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -48,8 +48,7 @@ struct BdrvDirtyBitmap {
 QemuMutex *mutex;
 HBitmap *bitmap;/* Dirty bitmap implementation */
 HBitmap *meta;  /* Meta dirty bitmap */
-bool qmp_locked;/* Bitmap is locked, it can't be modified
-   through QMP */
+bool busy;  /* Bitmap is busy, it can't be used via QMP */
 BdrvDirtyBitmap *successor; /* Anonymous child, if any. */
 char *name; /* Optional non-empty unique ID */
 int64_t size;   /* Size of the bitmap, in bytes */
@@ -188,22 +187,17 @@ bool bdrv_dirty_bitmap_has_successor(BdrvDirtyBitmap 
*bitmap)
 return bitmap->successor;
 }
 
-bool bdrv_dirty_bitmap_user_locked(BdrvDirtyBitmap *bitmap) {
-return bdrv_dirty_bitmap_qmp_locked(bitmap);
+bool bdrv_dirty_bitmap_busy(BdrvDirtyBitmap *bitmap) {
+return bitmap->busy;
 }
 
-void bdrv_dirty_bitmap_set_qmp_locked(BdrvDirtyBitmap *bitmap, bool qmp_locked)
+void bdrv_dirty_bitmap_set_busy(BdrvDirtyBitmap *bitmap, bool busy)
 {
 qemu_mutex_lock(bitmap->mutex);
-bitmap->qmp_locked = qmp_locked;
+bitmap->busy = busy;
 qemu_mutex_unlock(bitmap->mutex);
 }
 
-bool bdrv_dirty_bitmap_qmp_locked(BdrvDirtyBitmap *bitmap)
-{
-return bitmap->qmp_locked;
-}
-
 /* Called with BQL taken.  */
 bool bdrv_dirty_bitmap_enabled(BdrvDirtyBitmap *bitmap)
 {
@@ -215,7 +209,7 @@ DirtyBitmapStatus bdrv_dirty_bitmap_status(BdrvDirtyBitmap 
*bitmap)
 {
 if (bdrv_dirty_bitmap_has_successor(bitmap)) {
 return DIRTY_BITMAP_STATUS_FROZEN;
-} else if (bdrv_dirty_bitmap_qmp_locked(bitmap)) {
+} else if (bdrv_dirty_bitmap_busy(bitmap)) {
 return DIRTY_BITMAP_STATUS_LOCKED;
 } else if (!bdrv_dirty_bitmap_enabled(bitmap)) {
 return DIRTY_BITMAP_STATUS_DISABLED;
@@ -243,7 +237,7 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
 uint64_t granularity;
 BdrvDirtyBitmap *child;
 
-if (bdrv_dirty_bitmap_user_locked(bitmap)) {
+if (bdrv_dirty_bitmap_busy(bitmap)) {
 error_setg(errp, "Cannot create a successor for a bitmap that is 
in-use "
"by an operation");
 return -1;
@@ -265,9 +259,9 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
 child->disabled = bitmap->disabled;
 bitmap->disabled = true;
 
-/* Install the successor and lock the parent */
+/* Install the successor and mark the parent as busy */
 bitmap->successor = child;
-bitmap->qmp_locked = true;
+bitmap->busy = true;
 return 0;
 }
 
@@ -289,7 +283,7 @@ void bdrv_dirty_bitmap_enable_successor(BdrvDirtyBitmap 
*bitmap)
 static void bdrv_release_dirty_bitmap_locked(BdrvDirtyBitmap *bitmap)
 {
 assert(!bitmap->active_iterators);
-assert(!bdrv_dirty_bitmap_user_locked(bitmap));
+assert(!bdrv_dirty_bitmap_busy(bitmap));
 assert(!bitmap->meta);
 QLIST_REMOVE(bitmap, list);
 hbitmap_free(bitmap->bitmap);
@@ -321,7 +315,7 @@ BdrvDirtyBitmap 
*bdrv_dirty_bitmap_abdicate(BlockDriverState *bs,
 bitmap->successor = NULL;
 successor->persistent = bitmap->persistent;
 bitmap->persistent = false;
-bitmap->qmp_locked = false;
+bitmap->busy = false;
 bdrv_release_dirty_bitmap(bs, bitmap);
 
 return successor;
@@ -330,7 +324,7 @@ BdrvDirtyBitmap 
*bdrv_dirty_bitmap_abdicate(BlockDriverState *bs,
 /**
  * In cases of failure where we can no longer safely delete the parent,
  * we may wish to re-join the parent and child/successor.
- * The merged parent will not be user_locked.
+ * The merged parent will be marked as not busy.
  * The marged parent will be enabled if and only if the successor was enabled.
  * Called within bdrv_dirty_bitmap_lock..unlock and with BQL taken.
  */
@@ -351,7 +345,7 @@ BdrvDirtyBitmap 
*bdrv_reclaim_dirty_bitmap_locked(BlockDriverState *bs,
 }
 
 parent->disabled = successor->disabled;
-parent->qmp_locked = false;
+parent->busy = false;
 bdrv_release_dirty_bitmap_locked(successor);
 parent->successor = NULL;
 
@@ -382,7 +376,7 @@ void bdrv_dirty_bitmap_truncate(BlockDriverState *bs, 
int64_t bytes)
 
 bdrv_dirty_bitmaps_lock(bs);
 QLIST_FOREACH(bitmap,

[Qemu-devel] [PATCH v3 05/10] nbd: change error checking order for bitmaps

2019-02-22 Thread John Snow

Check that the bitmap is not in use prior to it checking if it is
not enabled/recording guest writes. The bitmap being busy was likely
at the behest of the user, so this error has a greater chance of being
understood by the user.

Signed-off-by: John Snow 
---
 nbd/server.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/nbd/server.c b/nbd/server.c
index 0910d09a6d..de21c64ce3 100644
--- a/nbd/server.c
+++ b/nbd/server.c
@@ -1510,6 +1510,11 @@ NBDExport *nbd_export_new(BlockDriverState *bs, uint64_t 
dev_offset,
 goto fail;
 }
 
+if (bdrv_dirty_bitmap_user_locked(bm)) {
+error_setg(errp, "Bitmap '%s' is in use", bitmap);
+goto fail;
+}
+
 if ((nbdflags & NBD_FLAG_READ_ONLY) && bdrv_is_writable(bs) &&
 bdrv_dirty_bitmap_enabled(bm)) {
 error_setg(errp,
@@ -1518,11 +1523,6 @@ NBDExport *nbd_export_new(BlockDriverState *bs, uint64_t 
dev_offset,
 goto fail;
 }
 
-if (bdrv_dirty_bitmap_user_locked(bm)) {
-error_setg(errp, "Bitmap '%s' is in use", bitmap);
-goto fail;
-}
-
 bdrv_dirty_bitmap_set_qmp_locked(bm, true);
 exp->export_bitmap = bm;
 exp->export_bitmap_context = g_strdup_printf("qemu:dirty-bitmap:%s",
-- 
2.17.2

[Qemu-devel] [PATCH v3 06/10] block/dirty-bitmap: explicitly lock bitmaps with successors

2019-02-22 Thread John Snow

Instead of implying a user_locked/busy status, make it explicit.
Now, bitmaps in use by migration, NBD or backup operations
are all treated the same way with the same code paths.

Signed-off-by: John Snow 
Reviewed-by: Eric Blake 
---
 block/dirty-bitmap.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 976831e765..d92a269753 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -50,7 +50,7 @@ struct BdrvDirtyBitmap {
 HBitmap *meta;  /* Meta dirty bitmap */
 bool qmp_locked;/* Bitmap is locked, it can't be modified
through QMP */
-BdrvDirtyBitmap *successor; /* Anonymous child; implies user_locked state 
*/
+BdrvDirtyBitmap *successor; /* Anonymous child, if any. */
 char *name; /* Optional non-empty unique ID */
 int64_t size;   /* Size of the bitmap, in bytes */
 bool disabled;  /* Bitmap is disabled. It ignores all writes to
@@ -188,10 +188,8 @@ bool bdrv_dirty_bitmap_has_successor(BdrvDirtyBitmap 
*bitmap)
 return bitmap->successor;
 }
 
-/* Both conditions disallow user-modification via QMP. */
 bool bdrv_dirty_bitmap_user_locked(BdrvDirtyBitmap *bitmap) {
-return bdrv_dirty_bitmap_has_successor(bitmap) ||
-   bdrv_dirty_bitmap_qmp_locked(bitmap);
+return bdrv_dirty_bitmap_qmp_locked(bitmap);
 }
 
 void bdrv_dirty_bitmap_set_qmp_locked(BdrvDirtyBitmap *bitmap, bool qmp_locked)
@@ -267,8 +265,9 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
 child->disabled = bitmap->disabled;
 bitmap->disabled = true;
 
-/* Install the successor and freeze the parent */
+/* Install the successor and lock the parent */
 bitmap->successor = child;
+bitmap->qmp_locked = true;
 return 0;
 }
 
@@ -322,6 +321,7 @@ BdrvDirtyBitmap 
*bdrv_dirty_bitmap_abdicate(BlockDriverState *bs,
 bitmap->successor = NULL;
 successor->persistent = bitmap->persistent;
 bitmap->persistent = false;
+bitmap->qmp_locked = false;
 bdrv_release_dirty_bitmap(bs, bitmap);
 
 return successor;
@@ -351,6 +351,7 @@ BdrvDirtyBitmap 
*bdrv_reclaim_dirty_bitmap_locked(BlockDriverState *bs,
 }
 
 parent->disabled = successor->disabled;
+parent->qmp_locked = false;
 bdrv_release_dirty_bitmap_locked(successor);
 parent->successor = NULL;
 
-- 
2.17.2

[Qemu-devel] [PATCH v3 02/10] block/dirty-bitmaps: rename frozen predicate helper

2019-02-22 Thread John Snow

"Frozen" was a good description a long time ago, but it isn't adequate now.
Rename the frozen predicate to has_successor to make the semantics of the
predicate more clear to outside callers.

In the process, remove some calls to frozen() that no longer semantically
make sense. For bdrv_enable_dirty_bitmap_locked and
bdrv_disable_dirty_bitmap_locked, it doesn't make sense to prohibit QEMU
internals from performing this action when we only wished to prohibit QMP
users from issuing these commands. All of the QMP API commands for bitmap
manipulation already check against user_locked() to prohibit these actions.

Several other assertions really want to check that the bitmap isn't in-use
by another operation -- use the bitmap_user_locked function for this instead,
which presently also checks for has_successor. This leaves some redundant
checks of has_sucessor through different helpers that are addressed in
forthcoming patches.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c   | 32 +---
 include/block/dirty-bitmap.h   |  2 +-
 migration/block-dirty-bitmap.c |  2 +-
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 101383b3af..aa3f86bb73 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -50,7 +50,7 @@ struct BdrvDirtyBitmap {
 HBitmap *meta;  /* Meta dirty bitmap */
 bool qmp_locked;/* Bitmap is locked, it can't be modified
through QMP */
-BdrvDirtyBitmap *successor; /* Anonymous child; implies frozen status */
+BdrvDirtyBitmap *successor; /* Anonymous child; implies user_locked state 
*/
 char *name; /* Optional non-empty unique ID */
 int64_t size;   /* Size of the bitmap, in bytes */
 bool disabled;  /* Bitmap is disabled. It ignores all writes to
@@ -183,14 +183,14 @@ const char *bdrv_dirty_bitmap_name(const BdrvDirtyBitmap 
*bitmap)
 }
 
 /* Called with BQL taken.  */
-bool bdrv_dirty_bitmap_frozen(BdrvDirtyBitmap *bitmap)
+bool bdrv_dirty_bitmap_has_successor(BdrvDirtyBitmap *bitmap)
 {
 return bitmap->successor;
 }
 
 /* Both conditions disallow user-modification via QMP. */
 bool bdrv_dirty_bitmap_user_locked(BdrvDirtyBitmap *bitmap) {
-return bdrv_dirty_bitmap_frozen(bitmap) ||
+return bdrv_dirty_bitmap_has_successor(bitmap) ||
bdrv_dirty_bitmap_qmp_locked(bitmap);
 }
 
@@ -215,7 +215,7 @@ bool bdrv_dirty_bitmap_enabled(BdrvDirtyBitmap *bitmap)
 /* Called with BQL taken.  */
 DirtyBitmapStatus bdrv_dirty_bitmap_status(BdrvDirtyBitmap *bitmap)
 {
-if (bdrv_dirty_bitmap_frozen(bitmap)) {
+if (bdrv_dirty_bitmap_has_successor(bitmap)) {
 return DIRTY_BITMAP_STATUS_FROZEN;
 } else if (bdrv_dirty_bitmap_qmp_locked(bitmap)) {
 return DIRTY_BITMAP_STATUS_LOCKED;
@@ -235,7 +235,7 @@ static bool bdrv_dirty_bitmap_recording(BdrvDirtyBitmap 
*bitmap)
 
 /**
  * Create a successor bitmap destined to replace this bitmap after an 
operation.
- * Requires that the bitmap is not frozen and has no successor.
+ * Requires that the bitmap is not user_locked and has no successor.
  * Called with BQL taken.
  */
 int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
@@ -244,12 +244,16 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState 
*bs,
 uint64_t granularity;
 BdrvDirtyBitmap *child;
 
-if (bdrv_dirty_bitmap_frozen(bitmap)) {
-error_setg(errp, "Cannot create a successor for a bitmap that is "
-   "currently frozen");
+if (bdrv_dirty_bitmap_user_locked(bitmap)) {
+error_setg(errp, "Cannot create a successor for a bitmap that is 
in-use "
+   "by an operation");
+return -1;
+}
+if (bdrv_dirty_bitmap_has_successor(bitmap)) {
+error_setg(errp, "Cannot create a successor for a bitmap that already "
+   "has one");
 return -1;
 }
-assert(!bitmap->successor);
 
 /* Create an anonymous successor */
 granularity = bdrv_dirty_bitmap_granularity(bitmap);
@@ -268,7 +272,6 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
 
 void bdrv_enable_dirty_bitmap_locked(BdrvDirtyBitmap *bitmap)
 {
-assert(!bdrv_dirty_bitmap_frozen(bitmap));
 bitmap->disabled = false;
 }
 
@@ -285,7 +288,7 @@ void bdrv_dirty_bitmap_enable_successor(BdrvDirtyBitmap 
*bitmap)
 static void bdrv_release_dirty_bitmap_locked(BdrvDirtyBitmap *bitmap)
 {
 assert(!bitmap->active_iterators);
-assert(!bdrv_dirty_bitmap_frozen(bitmap));
+assert(!bdrv_dirty_bitmap_user_locked(bitmap));
 assert(!bitmap->meta);
 QLIST_REMOVE(bitmap, list);
 hbitmap_free(bitmap->bitmap);
@@ -325,7 +328,7 @@ BdrvDirtyBitmap 
*bdrv_dirty_bitmap_abdicate(BlockDriverState *bs,
 /**
  * In cases of failure where we can no longer safely delete the parent,
  * we may wish to re-join the parent and child/successor.
- *

[Qemu-devel] [PATCH v3 04/10] block/dirty-bitmap: change semantics of enabled predicate

2019-02-22 Thread John Snow

Currently, the enabled predicate means something like:
"the QAPI status of the bitmap is ACTIVE."
After this patch, it should mean exclusively:
"This bitmap is recording guest writes, and is allowed to do so."

In many places, this is how this predicate was already used.
Internal usages of the bitmap QPI can call user_locked to find out if
the bitmap is in use by an operation.

To accommodate this, modify the create_successor routine to now
explicitly disable the parent bitmap at creation time.


Justifications:

1. bdrv_dirty_bitmap_status suffers no change from the lack of
   1:1 parity with the new predicates because of the order in which
   the predicates are checked. This is now only for compatibility.

2. bdrv_set_dirty() is unchanged: pre-patch, it was skipping bitmaps that were
   disabled or had a successor, while post-patch it is only skipping bitmaps
   that are disabled. To accommodate this, create_successor now ensures that
   any bitmap with a successor is explicitly disabled.

3. qcow2_store_persistent_dirty_bitmaps: No functional change. This function
   cares only about the literal enabled bit, and makes no effort to check if
   the bitmap is in-use or not. After this patch there are still no ways to
   produce an enabled bitmap with a successor.

4. block_dirty_bitmap_enable_prepare
   block_dirty_bitmap_disable_prepare
   init_dirty_bitmap_migration
   nbd_export_new

   These functions care about the literal enabled bit,
   and already check user_locked separately.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index 9ea5738420..976831e765 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -209,7 +209,7 @@ bool bdrv_dirty_bitmap_qmp_locked(BdrvDirtyBitmap *bitmap)
 /* Called with BQL taken.  */
 bool bdrv_dirty_bitmap_enabled(BdrvDirtyBitmap *bitmap)
 {
-return !(bitmap->disabled || bitmap->successor);
+return !bitmap->disabled;
 }
 
 /* Called with BQL taken.  */
@@ -236,6 +236,7 @@ static bool bdrv_dirty_bitmap_recording(BdrvDirtyBitmap 
*bitmap)
 /**
  * Create a successor bitmap destined to replace this bitmap after an 
operation.
  * Requires that the bitmap is not user_locked and has no successor.
+ * The successor will be enabled if the parent bitmap was.
  * Called with BQL taken.
  */
 int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
@@ -264,6 +265,7 @@ int bdrv_dirty_bitmap_create_successor(BlockDriverState *bs,
 
 /* Successor will be on or off based on our current state. */
 child->disabled = bitmap->disabled;
+bitmap->disabled = true;
 
 /* Install the successor and freeze the parent */
 bitmap->successor = child;
@@ -328,7 +330,8 @@ BdrvDirtyBitmap 
*bdrv_dirty_bitmap_abdicate(BlockDriverState *bs,
 /**
  * In cases of failure where we can no longer safely delete the parent,
  * we may wish to re-join the parent and child/successor.
- * The merged parent will not be user_locked, nor explicitly re-enabled.
+ * The merged parent will not be user_locked.
+ * The marged parent will be enabled if and only if the successor was enabled.
  * Called within bdrv_dirty_bitmap_lock..unlock and with BQL taken.
  */
 BdrvDirtyBitmap *bdrv_reclaim_dirty_bitmap_locked(BlockDriverState *bs,
@@ -346,6 +349,8 @@ BdrvDirtyBitmap 
*bdrv_reclaim_dirty_bitmap_locked(BlockDriverState *bs,
 error_setg(errp, "Merging of parent and successor bitmap failed");
 return NULL;
 }
+
+parent->disabled = successor->disabled;
 bdrv_release_dirty_bitmap_locked(successor);
 parent->successor = NULL;
 
-- 
2.17.2

[Qemu-devel] [PATCH v3 01/10] block/dirty-bitmap: add recording and busy properties

2019-02-22 Thread John Snow

The current API allows us to report a single status, which we've defined as:

Frozen: has a successor, treated as qmp_locked, may or may not be enabled.
Locked: no successor, qmp_locked. may or may not be enabled.
Disabled: Not frozen or locked, disabled.
Active: Not frozen, locked, or disabled.

The problem is that both "Frozen" and "Locked" mean nearly the same thing,
and that both of them do not intuit whether they are recording guest writes
or not.

This patch deprecates that status field and introduces two orthogonal
properties instead to replace it.

Signed-off-by: John Snow 
---
 block/dirty-bitmap.c   |  9 +
 qapi/block-core.json   | 10 +-
 qemu-deprecated.texi   |  6 ++
 tests/qemu-iotests/236.out | 28 
 4 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
index c6d4acebfa..101383b3af 100644
--- a/block/dirty-bitmap.c
+++ b/block/dirty-bitmap.c
@@ -226,6 +226,13 @@ DirtyBitmapStatus bdrv_dirty_bitmap_status(BdrvDirtyBitmap 
*bitmap)
 }
 }
 
+/* Called with BQL taken.  */
+static bool bdrv_dirty_bitmap_recording(BdrvDirtyBitmap *bitmap)
+{
+return !bitmap->disabled || (bitmap->successor &&
+ !bitmap->successor->disabled);
+}
+
 /**
  * Create a successor bitmap destined to replace this bitmap after an 
operation.
  * Requires that the bitmap is not frozen and has no successor.
@@ -448,6 +455,8 @@ BlockDirtyInfoList 
*bdrv_query_dirty_bitmaps(BlockDriverState *bs)
 info->has_name = !!bm->name;
 info->name = g_strdup(bm->name);
 info->status = bdrv_dirty_bitmap_status(bm);
+info->recording = bdrv_dirty_bitmap_recording(bm);
+info->busy = bdrv_dirty_bitmap_user_locked(bm);
 info->persistent = bm->persistent;
 entry->value = info;
 *plist = entry;
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 2b8afbb924..6e543594b3 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -458,7 +458,14 @@
 #
 # @granularity: granularity of the dirty bitmap in bytes (since 1.4)
 #
-# @status: current status of the dirty bitmap (since 2.4)
+# @status: Deprecated in favor of @recording and @locked. (since 2.4)
+#
+# @recording: true if the bitmap is recording new writes from the guest.
+# Replaces `active` and `disabled` statuses. (since 4.0)
+#
+# @busy: true if the bitmap is in-use by some operation (NBD or jobs)
+#and cannot be modified via QMP or used by another operation.
+#Replaces `locked` and `frozen` statuses. (since 4.0)
 #
 # @persistent: true if the bitmap will eventually be flushed to persistent
 #  storage (since 4.0)
@@ -467,6 +474,7 @@
 ##
 { 'struct': 'BlockDirtyInfo',
   'data': {'*name': 'str', 'count': 'int', 'granularity': 'uint32',
+   'recording': 'bool', 'busy': 'bool',
'status': 'DirtyBitmapStatus', 'persistent': 'bool' } }
 
 ##
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 45c57952da..4c7ae8180f 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -67,6 +67,12 @@ topologies described with -smp include all possible cpus, 
i.e.
 "autoload" parameter is now ignored. All bitmaps are automatically loaded
 from qcow2 images.
 
+@subsection query-block result field(s) dirty-bitmaps[i].status (since 4.0)
+
+The ``status'' field of the ``BlockDirtyInfo'' structure, returned by
+the query-block command is deprecated. Two new boolean fields,
+``recording'' and ``busy'' effectively replace it.
+
 @subsection query-cpus (since 2.12.0)
 
 The ``query-cpus'' command is replaced by the ``query-cpus-fast'' command.
diff --git a/tests/qemu-iotests/236.out b/tests/qemu-iotests/236.out
index 5006f7bca1..815cd053f0 100644
--- a/tests/qemu-iotests/236.out
+++ b/tests/qemu-iotests/236.out
@@ -22,17 +22,21 @@ write -P0xcd 0x3ff 64k
   "bitmaps": {
 "drive0": [
   {
+"busy": false,
 "count": 262144,
 "granularity": 65536,
 "name": "bitmapB",
 "persistent": false,
+"recording": true,
 "status": "active"
   },
   {
+"busy": false,
 "count": 262144,
 "granularity": 65536,
 "name": "bitmapA",
 "persistent": false,
+"recording": true,
 "status": "active"
   }
 ]
@@ -84,17 +88,21 @@ write -P0xcd 0x3ff 64k
   "bitmaps": {
 "drive0": [
   {
+"busy": false,
 "count": 262144,
 "granularity": 65536,
 "name": "bitmapB",
 "persistent": false,
+"recording": true,
 "status": "active"
   },
   {
+"busy": false,
 "count": 262144,
 "granularity": 65536,
 "name": "bitmapA",
 "persistent": false,
+"recording": true,
 "status": "active"
   }
 ]
@@ -184,24 +192,30 @@ write -P0xea 0x3fe 64k
   "bitmaps": {
 "drive0": [
   {
+

[Qemu-devel] [PATCH v3 00/10] dirty-bitmaps: deprecate @status field

2019-02-22 Thread John Snow

The current internal meanings of "locked", "user_locked",
"qmp_locked", "frozen", "enabled", and "disabled" are all
a little muddled.

Deprecate the @status field in favor of two new booleans
that carry very specific meanings. Then, rename and rework
some of the internal semantics to help make the API a bit
more clear and easier to read.

Well, in my opinion.

Based on my current bitmaps branch.

V3:

[] : patches are identical
[] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively

001/10:[0002] [FC] 'block/dirty-bitmap: add recording and busy properties'
002/10:[0002] [FC] 'block/dirty-bitmaps: rename frozen predicate helper'
003/10:[down] 'block/dirty-bitmap: remove set/reset assertions against enabled 
bit'
004/10:[0006] [FC] 'block/dirty-bitmap: change semantics of enabled predicate'
005/10:[down] 'nbd: change error checking order for bitmaps'
006/10:[0002] [FC] 'block/dirty-bitmap: explicitly lock bitmaps with successors'
007/10:[0011] [FC] 'block/dirty-bitmaps: unify qmp_locked and user_locked calls'
008/10:[0002] [FC] 'block/dirty-bitmaps: move comment block'
009/10:[down] 'blockdev: remove unused paio parameter documentation'
010/10:[down] 'iotests: add busy/recording bit test to 124'

V3: (Following Vladimir's feedback)

001: Changed texi phrasing, parameter --> field
002: Commit message adjustment
 comment edit: "not locked" --> "not user_locked"
003: pulled forward out of patch 004
004: Commit message rewrite
 create_successor and abdicate doc adjustments
005: New.
006: Change successor doc comment
 Commit message adjustment
007: BdrvDirtyBitmap struct comment adjustments
 Comment change to create_successor (lock --> busy)
 Incidental changes from 004's changes
008: Grammar fix (Eric)
009: New, trivial, unrelated fix tagging along.
010: iotest 124 added.

John Snow (10):
  block/dirty-bitmap: add recording and busy properties
  block/dirty-bitmaps: rename frozen predicate helper
  block/dirty-bitmap: remove set/reset assertions against enabled bit
  block/dirty-bitmap: change semantics of enabled predicate
  nbd: change error checking order for bitmaps
  block/dirty-bitmap: explicitly lock bitmaps with successors
  block/dirty-bitmaps: unify qmp_locked and user_locked calls
  block/dirty-bitmaps: move comment block
  blockdev: remove unused paio parameter documentation
  iotests: add busy/recording bit test to 124

 block/dirty-bitmap.c   | 111 ++---
 blockdev.c |  19 +++---
 include/block/dirty-bitmap.h   |   7 +--
 migration/block-dirty-bitmap.c |   8 +--
 nbd/server.c   |  14 ++---
 qapi/block-core.json   |  10 ++-
 qemu-deprecated.texi   |   6 ++
 tests/qemu-iotests/124 | 110 
 tests/qemu-iotests/124.out |   4 +-
 tests/qemu-iotests/236.out |  28 +
 10 files changed, 239 insertions(+), 78 deletions(-)

-- 
2.17.2

Re: [Qemu-devel] [PATCH v3 1/2] CODING_STYLE: specify the indent rule for multiline code

2019-02-22 Thread Wei Yang

On Thu, Feb 21, 2019 at 03:55:19PM +0100, Igor Mammedov wrote:
>On Wed, 20 Feb 2019 11:15:56 +0800
>Wei Yang  wrote:
>
>> We didn't specify the indent rule for multiline code here, which may
>> mislead users. And in current code, the code use different rules.
>> 
>> Add this rule in CODING_STYLE to make sure this is clear to every one.
>> 
>> Signed-off-by: Wei Yang 
>> Suggested-by: Igor Mammedov 
>> Reviewed-by: Eric Blake 
>> 
>> ---
>> v3:
>>* misleading -> mislead
>>* add comma after arg2 in example
>> v2:
>>* rephrase changelog suggested by Eric Blake
>>  - remove one redundant line
>>  - fix some awkward grammar
>>  - add { ; at the end of example
>> 
>> c1
>> ---
>>  CODING_STYLE | 23 +++
>>  1 file changed, 23 insertions(+)
>> 
>> diff --git a/CODING_STYLE b/CODING_STYLE
>> index ec075dedc4..1359f9ab81 100644
>> --- a/CODING_STYLE
>> +++ b/CODING_STYLE
>> @@ -29,6 +29,29 @@ Spaces of course are superior to tabs because:
>>  
>>  Do not leave whitespace dangling off the ends of lines.
>>  
>> +1.1 Multiline Indent
>> +
>> +There are several places where indent is necessary:
>> +
>> + - struct definition
>> + - if/else
>> + - while/for
>> + - function definition & call
>> +
>> +When breaking up a long line to fit within line widths, align the secondary
>s/widths/width/
>
>> +lines just after the opening parenthesis of the first.
>> +
>> +For example:
>> +
>> +if (a == 1 &&
>> +b == 2) {
>> +
>> +while (a == 1 &&
>> +   b == 2) {
>> +
>> +do_something(arg1, arg2,
>> + arg3);
>> +
>
>there is also another widely used acceptable pattern
>  func_name(arg1, arg2,
>  arg3)
>
>where we indent relative to function name start
>(sound weird to me but I'm not sure how to word it properly)
>

Hmm... we may need to add this exception case.

>>  2. Line width
>>  
>>  Lines should be 80 characters; try not to make them longer.
>

-- 
Wei Yang
Help you, Help me

Re: [Qemu-devel] [PATCH v2 0/3] PCDIMM cleanup

2019-02-22 Thread Wei Yang

On Thu, Feb 21, 2019 at 03:50:04PM +0100, Igor Mammedov wrote:
>On Wed, 20 Feb 2019 08:51:21 +0800
>Wei Yang  wrote:
>
>> Three trivial cleanup for pc-dimm.
>> 
>> Patch [1] remove the check on class->hotpluggable since pc-dimm is always
>> hotpluggable.
>> Patch [2] remove nvdimm_realize
>> Patch [2] remove pcdimm realize-callback
>even though this series doesn't break anything, I disagree with it
>conceptually as it makes device less abstracted and make it more
>dependent on how existing machine code uses it.
>I'd drop whole series.
>

Is Patch [1] also make device more dependent on existing implementation?

For example, when we look at the counterpart of acpi_memory_plug_cb():

acpi_pcihp_device_plug_cb

which handle the pci device hotplug. We don't check the hotpluggable
property for pci devices.

To me, this is a general rule for PCDIMM, they are hotpluggable.

For Patch[2][3], I agree with you.

-- 
Wei Yang
Help you, Help me

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-22 Thread Richard Henderson

On 2/22/19 8:25 AM, amagdy.af...@gmail.com wrote:
> @@ -373,9 +373,10 @@ static int write_misa(CPURISCVState *env, int csrno, 
> target_ulong val)
>  }
>  
>  /* Suppress 'C' if next instruction is not aligned
> -   TODO: this should check next_pc */
> -if ((val & RVC) && (GETPC() & ~3) != 0) {
> +   check next target pc */
> +if ((val & RVC) && (env->pc_next & 3) != 0) {
>  val &= ~RVC;
> +env->pending_rvc = 1;
>  }
>  
>  /* misa.MXL writes are not supported by QEMU */
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2321bba..c9d84ea 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1999,20 +1999,26 @@ static void decode_RV32_64G(DisasContext *ctx)
>  }
>  }
>  
> -static void decode_opc(DisasContext *ctx)
> +static void decode_opc(DisasContext *ctx, CPUState *cpu)
>  {
> +CPURISCVState *env = cpu->env_ptr;
>  /* check for compressed insn */
>  if (extract32(ctx->opcode, 0, 2) != 3) {
>  if (!has_ext(ctx, RVC)) {
>  gen_exception_illegal(ctx);
>  } else {
> -ctx->pc_succ_insn = ctx->base.pc_next + 2;
> +env->pc_next = ctx->pc_succ_insn = ctx->base.pc_next + 2;
>  decode_RV32_64C(ctx);
>  }
>  } else {
> -ctx->pc_succ_insn = ctx->base.pc_next + 4;
> +env->pc_next = ctx->pc_succ_insn = ctx->base.pc_next + 4;
>  decode_RV32_64G(ctx);
>  }
> +/* check pending RVC */
> +if (env->pending_rvc && ((env->pc_next & 3) != 0)) {
> +env->misa |= RVC;
> +env->pending_rvc = 0;

You cannot manipulate env like this during translation.

Neither the write to env->pc_next nor the read from env->pending_rvc here will
be in any synchronization with the execution of write_misa.

What semantics are you attempting to implement wrt setting/clearing RVC from 
MISA?

> @@ -2061,7 +2067,7 @@ static void riscv_tr_translate_insn
>  CPURISCVState *env = cpu->env_ptr;
>  
>  ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
> -decode_opc(ctx);
> +decode_opc(ctx, cpu);

This is exactly the reason why cpu is *not* passed down to decode_opc, so that
you cannot make this kind of mistake.


r~

Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree

2019-02-22 Thread Alistair Francis

On Fri, Feb 22, 2019 at 6:31 AM Bastian Koppelmann
 wrote:
>
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in four major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-15]:
> Many of the gen_* functions are called by the decode functions for 16-bit
> and 32-bit functions. If we move translation code from the gen_*
> functions to the generated trans_* functions of decode-tree, we get a lot 
> of
> duplication. Therefore, we mostly generate calls to the old gen_* function
> which are properly replaced after step 2).
>
> Each of the trans_ functions are grouped into files corresponding to their
> ISA extension, e.g. addi which is in RV32I is translated in the file
> 'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 16-18]:
> All 16 bit instructions have a direct mapping to a 32 bit instruction. 
> Thus,
> we convert the arguments in the 16 bit trans_ function to the arguments of
> the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 19-29]:
> this move all manual translation code into the trans_* instructions of
> decode tree, such that we can remove the old decode_* functions.
>
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as 
> suggested
>by Richard. [Patch 30-34]
>
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v8
>
> Cheers,
> Bastian

Tested-by: Alistair Francis 

I haven't run any strenuous tests, but it boots 32 and 64-bit
Linux/openSBI with no issues.

Alistair

>
> v7 -> v8:
> - add REQUIRE_EXT macro
> - add missing RVM checks
> - add missing RVA checks
> - add missing RVF checks
> - add missing RVF checks
> - add missing RVD checks
> - add missing RVD checks
> - riscv_has_ext -> has_ext
> - env->ctx->priv_version -> ctx->priv_version
> - fixed wrongly inserted #ifdef TARGET_RISCV64 that lead to a compile 
> error
>
>
> Bastian Koppelmann (34):
>   target/riscv: Activate decodetree and implemnt LUI & AUIPC
>   target/riscv: Convert RVXI branch insns to decodetree
>   target/riscv: Convert RV32I load/store insns to decodetree
>   target/riscv: Convert RV64I load/store insns to decodetree
>   target/riscv: Convert RVXI arithmetic insns to decodetree
>   target/riscv: Convert RVXI fence insns to decodetree
>   target/riscv: Convert RVXI csr insns to decodetree
>   target/riscv: Convert RVXM insns to decodetree
>   target/riscv: Convert RV32A insns to decodetree
>   target/riscv: Convert RV64A insns to decodetree
>   target/riscv: Convert RV32F insns to decodetree
>   target/riscv: Convert RV64F insns to decodetree
>   target/riscv: Convert RV32D insns to decodetree
>   target/riscv: Convert RV64D insns to decodetree
>   target/riscv: Convert RV priv insns to decodetree
>   target/riscv: Convert quadrant 0 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 1 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 2 of RVXC insns to decodetree
>   target/riscv: Remove gen_jalr()
>   target/riscv: Remove manual decoding from gen_branch()
>   target/riscv: Remove manual decoding from gen_load()
>   target/riscv: Remove manual decoding from gen_store()
>   target/riscv: Move gen_arith_imm() decoding into trans_* functions
>   target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
>   target/riscv: Remove shift and slt insn manual decoding
>   target/riscv: Remove manual decoding of RV32/64M insn
>   target/riscv: Rename trans_arith to gen_arith
>   target/riscv: Remove gen_system()
>   target/riscv: Remove decode_RV32_64G()
>   target/riscv: Convert @cs_2 insns to share translation functions
>   target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
>   target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
>   target/riscv: Splice remaining compressed insn pairs for riscv32 vs
> riscv64
>   target/riscv: Remaining rvc insn reuse 32 bit translators
>
>  target/riscv/Makefile.objs|   22 +
>  target/riscv/insn16-32.decode |   31 +
>  target/riscv/insn16-64.decode |   33 +
>  target/riscv/insn16.decode|  114 +
>  target/riscv/insn32-64.decode |   72 +
>  target/riscv/insn32.decode|  203 ++
>  .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
>  target/riscv/insn_trans/trans_rva.inc.c   |  218 ++
>  target/riscv/insn_trans/trans_rvc.inc.c   |  149 ++
>  target/riscv/insn_trans/trans_rvd.inc.c   |  442 
>  target/riscv/insn_trans/trans_rvf.inc.c   |  439 
>  target/riscv/insn_trans/trans_rvi.inc.c   |  568 +
>  target/riscv/insn_trans/trans_rvm.inc.c   |  120 +
>  target/riscv/translate.c  | 1948 ++---
>  14 files changed, 2740 insertions(+), 1729 deletions(-)
>  create mode 100644 target/riscv/insn16-32.decode
>

[Qemu-devel] [PATCH 1/2] usb-mtp: return incomplete transfer on a lstat failure

2019-02-22 Thread Bandan Das

MTP writes objects in small chunks and at the end gets the
real file size to update the object metadata. If this fails for
any reason, return an INCOMPLETE_TRANSFER to the initiator

Spotted by Coverity: CID 1398651

Signed-off-by: Bandan Das 
---
 hw/usb/dev-mtp.c | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index f1d20fa1b9..79f2cb8743 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -1644,14 +1644,18 @@ done:
 return ret;
 }
 
-static void usb_mtp_update_object(MTPObject *parent, char *name)
+static int usb_mtp_update_object(MTPObject *parent, char *name)
 {
+int ret = -1;
+
 MTPObject *o =
 usb_mtp_object_lookup_name(parent, name, strlen(name));
 
 if (o) {
-lstat(o->path, >stat);
+ret = lstat(o->path, >stat);
 }
+
+return ret;
 }
 
 static void usb_mtp_write_data(MTPState *s)
@@ -1708,14 +1712,19 @@ static void usb_mtp_write_data(MTPState *s)
 if (d->write_status != WRITE_END) {
 return;
 } else {
-/* Only for < 4G file sizes */
-if (s->dataset.size != 0x && d->offset != s->dataset.size) 
{
+/*
+ * Return an incomplete transfer if file size doesn't match
+ * for < 4G file or if lstat fails which will result in an 
incorrect
+ * file size
+ */
+if ((s->dataset.size != 0x &&
+ d->offset != s->dataset.size) ||
+usb_mtp_update_object(parent, s->dataset.filename)) {
 usb_mtp_queue_result(s, RES_INCOMPLETE_TRANSFER, d->trans,
  0, 0, 0, 0);
 goto done;
 }
-usb_mtp_update_object(parent, s->dataset.filename);
+
 }
 }
 
-- 
2.19.2

[Qemu-devel] [PATCH 0/2] usb-mtp coverity fixes

2019-02-22 Thread Bandan Das

Fix some coverity issues and a few others pointed out by Peter

Bandan Das (2):
  usb-mtp: return incomplete transfer on a lstat failure
  usb-mtp: fix some usb_mtp_write_data return paths

 hw/usb/dev-mtp.c | 38 +-
 1 file changed, 25 insertions(+), 13 deletions(-)

-- 
2.19.2

[Qemu-devel] [PATCH 2/2] usb-mtp: fix some usb_mtp_write_data return paths

2019-02-22 Thread Bandan Das

During a write, free up the "path" before getting more data.
Also, while we at it, remove the confusing usage of d->fd for
storing mkdir status

Spotted by Coverity: CID 1398642

Signed-off-by: Bandan Das 
---
 hw/usb/dev-mtp.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 79f2cb8743..4c1c53d330 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -1658,7 +1658,7 @@ static int usb_mtp_update_object(MTPObject *parent, char 
*name)
 return ret;
 }
 
-static void usb_mtp_write_data(MTPState *s)
+static int usb_mtp_write_data(MTPState *s)
 {
 MTPData *d = s->data_out;
 MTPObject *parent =
@@ -1666,6 +1666,7 @@ static void usb_mtp_write_data(MTPState *s)
 char *path = NULL;
 uint64_t rc;
 mode_t mask = 0644;
+int ret = 0;
 
 assert(d != NULL);
 
@@ -1674,13 +1675,13 @@ static void usb_mtp_write_data(MTPState *s)
 if (!parent || !s->write_pending) {
 usb_mtp_queue_result(s, RES_INVALID_OBJECTINFO, d->trans,
 0, 0, 0, 0);
-return;
+return 1;
 }
 
 if (s->dataset.filename) {
 path = g_strdup_printf("%s/%s", parent->path, s->dataset.filename);
 if (s->dataset.format == FMT_ASSOCIATION) {
-d->fd = mkdir(path, mask);
+ret = mkdir(path, mask);
 goto free;
 }
 d->fd = open(path, O_CREAT | O_WRONLY |
@@ -1710,7 +1711,8 @@ static void usb_mtp_write_data(MTPState *s)
 goto done;
 }
 if (d->write_status != WRITE_END) {
-return;
+g_free(path);
+return ret;
 } else {
 /*
  * Return an incomplete transfer if file size doesn't match
@@ -1739,12 +1741,14 @@ done:
  */
 if (d->fd != -1) {
 close(d->fd);
+d->fd = -1;
 }
 free:
 g_free(s->dataset.filename);
 s->dataset.size = 0;
 g_free(path);
 s->write_pending = false;
+return ret;
 }
 
 static void usb_mtp_write_metadata(MTPState *s, uint64_t dlen)
@@ -1781,14 +1785,12 @@ static void usb_mtp_write_metadata(MTPState *s, 
uint64_t dlen)
 s->write_pending = true;
 
 if (s->dataset.format == FMT_ASSOCIATION) {
-usb_mtp_write_data(s);
-/* next_handle will be allocated to the newly created dir */
-if (d->fd == -1) {
+if (usb_mtp_write_data(s)) {
+/* next_handle will be allocated to the newly created dir */
 usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
  0, 0, 0, 0);
 return;
 }
-d->fd = -1;
 }
 
 usb_mtp_queue_result(s, RES_OK, d->trans, 3, QEMU_STORAGE_ID,
-- 
2.19.2

[Qemu-devel] Add proper alignment check and pending 'C' extension for riscv

2019-02-22 Thread amagdy . afifi



Dear All,

I'm submiting this patch to properly check the next instruction alignment and 
scheduale compression extenstion enable upon 'MISA' register writes to later 
aligned instruction through exporting next instruction 'pc' to riscv cpu state

Thanks,
Ahmed

[Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-22 Thread amagdy . afifi

From: ahmed_magdy 

Signed-off-by: ahmed_magdy 
---
 target/riscv/cpu.h   |  2 ++
 target/riscv/csr.c   |  5 +++--
 target/riscv/translate.c | 14 ++
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a269c07..b49bdb3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -109,6 +109,8 @@ struct CPURISCVState {
 target_ulong gpr[32];
 uint64_t fpr[32]; /* assume both F and D extensions */
 target_ulong pc;
+target_ulong pc_next; /* next target pc */
+int pending_rvc;
 target_ulong load_res;
 target_ulong load_val;
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 90f6866..b0886f0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -373,9 +373,10 @@ static int write_misa(CPURISCVState *env, int csrno, 
target_ulong val)
 }
 
 /* Suppress 'C' if next instruction is not aligned
-   TODO: this should check next_pc */
-if ((val & RVC) && (GETPC() & ~3) != 0) {
+   check next target pc */
+if ((val & RVC) && (env->pc_next & 3) != 0) {
 val &= ~RVC;
+env->pending_rvc = 1;
 }
 
 /* misa.MXL writes are not supported by QEMU */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2321bba..c9d84ea 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1999,20 +1999,26 @@ static void decode_RV32_64G(DisasContext *ctx)
 }
 }
 
-static void decode_opc(DisasContext *ctx)
+static void decode_opc(DisasContext *ctx, CPUState *cpu)
 {
+CPURISCVState *env = cpu->env_ptr;
 /* check for compressed insn */
 if (extract32(ctx->opcode, 0, 2) != 3) {
 if (!has_ext(ctx, RVC)) {
 gen_exception_illegal(ctx);
 } else {
-ctx->pc_succ_insn = ctx->base.pc_next + 2;
+env->pc_next = ctx->pc_succ_insn = ctx->base.pc_next + 2;
 decode_RV32_64C(ctx);
 }
 } else {
-ctx->pc_succ_insn = ctx->base.pc_next + 4;
+env->pc_next = ctx->pc_succ_insn = ctx->base.pc_next + 4;
 decode_RV32_64G(ctx);
 }
+/* check pending RVC */
+if (env->pending_rvc && ((env->pc_next & 3) != 0)) {
+env->misa |= RVC;
+env->pending_rvc = 0;
+}
 }
 
 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState 
*cpu)
@@ -2061,7 +2067,7 @@ static void riscv_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 CPURISCVState *env = cpu->env_ptr;
 
 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
-decode_opc(ctx);
+decode_opc(ctx, cpu);
 ctx->base.pc_next = ctx->pc_succ_insn;
 
 if (ctx->base.is_jmp == DISAS_NEXT) {
-- 
1.9.1

Re: [Qemu-devel] [PATCH 2/2] target/arm: Gate "miscellaneous FP" insns by ID register field

2019-02-22 Thread Richard Henderson

On 2/22/19 9:36 AM, Peter Maydell wrote:
> On Fri, 22 Feb 2019 at 17:09, Peter Maydell  wrote:
>>
>> There is a set of VFP instructions which we implement in
>> disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
>> These were all first introduced in v8 for A-profile, but in
>> M-profile they appeared in v7M. Gate them on the MVFR2
>> FPMisc field instead, and rename the function appropriately.
> 
>> diff --git a/target/arm/translate.c b/target/arm/translate.c
>> index b7702fb49f7..af8f9e669b8 100644
>> --- a/target/arm/translate.c
>> +++ b/target/arm/translate.c
>> @@ -3357,7 +3357,7 @@ static const uint8_t fp_decode_rm[] = {
>>  FPROUNDING_NEGINF,
>>  };
>>
>> -static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
>> +static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
>>  {
>>  uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
>>
> 
> Oops, I forgot to commit this part of the change:
> 
> @@ -3361,10 +3361,6 @@ static int disas_vfp_misc_insn(DisasContext *s,
> uint32_t insn)
>  {
>  uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
> 
> -if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
> -return 1;
> -}
> -
>  if (dp) {
>  VFP_DREG_D(rd, insn);
>  VFP_DREG_N(rn, insn);

With the addition,
Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH 1/2] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions

2019-02-22 Thread Richard Henderson

On 2/22/19 9:09 AM, Peter Maydell wrote:
> Instead of gating the A32/T32 FP16 conversion instructions on
> the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
> looking at ID register bits. In this case MVFR1 fields FPHP
> and SIMDHP indicate the presence of these insns.
> 
> This change doesn't alter behaviour for any of our CPUs.
> 
> Signed-off-by: Peter Maydell 
> ---
>  target/arm/cpu.h   | 37 -
>  target/arm/cpu.c   |  2 --
>  target/arm/kvm32.c |  3 ---
>  target/arm/translate.c | 26 ++
>  4 files changed, 54 insertions(+), 14 deletions(-)

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v2 1/7] ui/cocoa: Ensure we have the iothread lock when calling into QEMU

2019-02-22 Thread Roman Bolshakov

On Fri, Feb 22, 2019 at 03:41:05PM +, Peter Maydell wrote:
> On Fri, 22 Feb 2019 at 15:19, Roman Bolshakov  wrote:
> >
> > On Thu, Feb 14, 2019 at 10:28:10AM +, Peter Maydell wrote:
> > > The Cocoa UI should run on the main thread; this is enforced
> > > in OSX Mojave. In order to be able to run on the main thread,
> > > we need to make sure we hold the iothread lock whenever we
> > > call into various QEMU UI midlayer functions.
> > >
> >
> > I also think it's better to clarify that the reason of the commit is not
> > Mojave enforcing usage of event loop in main thread but an improvement
> > of event processing in Cocoa UI, because Cocoa UI works on Mojave.
> 
> Hmm? The point of this patchset is exactly that Mojave enforces
> that things go on the main thread, where previous OSX versions
> did not, and so in some situations QEMU will crash on Mojave
> where it did not on older versions. So I'm not sure what you're
> suggesting should be clarified here.
> 

I'm not exactly sure there's an issue with QEMU on Mojave. But I lean
towards the opinion because I haven't seen it :)

> > As of now qemu main loop and Cocoa events processing is done in the same
> > thread. And you can see from below that invocation of the qemu_main blocks
> > Cocoa event loop [NSApp run] in applicationDidFinishLaunching as qemu_main
> > doesn't quit.
> 
> Yes, indeed. This is how we've traditionally done the Cocoa
> event handling. It's worked OK for everything up to Mojave...
> 

Oh, you also mention that in the cover letter. I somehow skipped it.

> > Each millisecond cocoa_refresh gets called by display handler. The function
> > extracts all available events from the cocoa event queue and dispatches 
> > them to
> > handleEvent:
> >
> > event = [NSApp nextEventMatchingMask:NSEventMaskAny 
> > untilDate:distantPast
> > inMode: NSDefaultRunLoopMode dequeue:YES];
> > if (event != nil) {
> > [cocoaView handleEvent:event];
> > }
> >
> > handleEvent enqueues keyboard and mouse events into ps2 queue and the
> > other events are enqueued to Cocoa event queue. I'm curious what happens
> > to the events that are enqueued with:
> > [NSApp sendEvent:event];
> 
> As I understand it, this sendEvent method doesn't queue anything.
> It just hands the event to the usual OSX event handling chain,
> which will either use it (for example, if it's a menu-item
> key accelerator event) or drop it on the floor. The logic is
> basically "QEMU-specific code gets first chance to decide whether
> to consume the event; the default (and a few other odd cases)
> if it does not is that we let the OSX framework code do whatever
> it wants to do with it".
> 

Thanks, I see! I should have consulted apple reference before raising
the issue. FWIW there's a method to post an event to the event queue but
sendEvent is used to dispatch an event within an app and the event that
is already taken from the queue.

Besides qmp_stop and qmp_cont not being called under iothread lock,
Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Thanks,
Roman

Re: [Qemu-devel] [PATCH v1 6/6] softfloat: Support float_round_to_odd more places

2019-02-22 Thread Richard Henderson

On 2/22/19 12:45 PM, Alex Bennée wrote:
> @@ -3526,6 +3551,8 @@ static float32 roundAndPackFloat32(flag zSign, int 
> zExp, uint32_t zSig,
>  case float_round_down:
>  roundIncrement = zSign ? 0x7f : 0;
>  break;
> +case float_round_to_odd:
> +roundIncrement = zSig & 0x80 ? 0 : 0x7f;
>  default:
>  abort();

I clearly missed a break here.

Since this didn't kill fp-test, are we missing a float128_to_float32 test?


r~

Re: [Qemu-devel] [PATCH v1 5/6] tests/fp: enable f128_to_ui[32/64] tests in float-to-uint

2019-02-22 Thread Richard Henderson

On 2/22/19 12:44 PM, Alex Bennée wrote:
> We've just added f128_to_ui32 and we missed out the f128_to_ui64 tests
> last time.
> 
> Signed-off-by: Alex Bennée 
> ---
>  tests/Makefile.include | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v1 4/6] tests/fp: add wrapping for f128_to_ui32

2019-02-22 Thread Richard Henderson

On 2/22/19 12:44 PM, Alex Bennée wrote:
> Needed to test: softfloat: add float128_is_{normal,denormal}

Eh?

> 
> Signed-off-by: Alex Bennée 
> ---
>  tests/fp/fp-test.c  | 3 ++-
>  tests/fp/wrap.inc.c | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)

But the rest of the patch matches $SUBJECT, so
Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v2 7/7] ui/cocoa: Perform UI operations only on the main thread

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:16AM +, Peter Maydell wrote:
> The OSX Mojave release is more picky about enforcing the Cocoa API
> restriction that only the main thread may perform UI calls. To
> accommodate this we need to restructure the Cocoa code:
>  * the special OSX main() creates a second thread and uses
>that to call the vl.c qemu_main(); the original main
>thread goes into the OSX event loop
>  * the refresh, switch and update callbacks asynchronously
>tell the main thread to do the necessary work
>  * the refresh callback no longer does the "get events from the
>UI event queue and handle them" loop, since we now use
>the stock OSX event loop. Instead our NSApplication sendEvent
>method will either deal with them or pass them on to OSX
> 
> All these things have to be changed in one commit, to avoid
> breaking bisection.
> 
> Note that since we use dispatch_get_main_queue(), this bumps
> our minimum version requirement to OSX 10.10 Yosemite (released
> in 2014, unsupported by Apple since 2017).
> 
> Signed-off-by: Peter Maydell 
> ---
> v2 changes: call handleEvent from sendEvent
> ---
>  ui/cocoa.m | 191 +++--
>  1 file changed, 113 insertions(+), 78 deletions(-)
> 
> diff --git a/ui/cocoa.m b/ui/cocoa.m
> index 184fbd877d..201a294ed4 100644
> --- a/ui/cocoa.m
> +++ b/ui/cocoa.m
> @@ -129,6 +129,9 @@
>  NSTextField *pauseLabel;
>  NSArray * supportedImageFileTypes;
>  
> +QemuSemaphore display_init_sem;
> +QemuSemaphore app_started_sem;
> +

They might have file scope.

> @@ -535,13 +539,16 @@ - (void) switchSurface:(pixman_image_t *)image
>  }
>  
>  // update screenBuffer
> -if (dataProviderRef)
> +if (dataProviderRef) {
>  CGDataProviderRelease(dataProviderRef);
> +pixman_image_unref(pixman_image);
> +}

pixman_image also needs to be unreferenced in dealloc.

> @@ -1485,7 +1482,9 @@ @implementation QemuApplication
>  - (void)sendEvent:(NSEvent *)event
>  {
>  COCOA_DEBUG("QemuApplication: sendEvent\n");
> -[super sendEvent: event];
> +if (!cocoaView || ![cocoaView handleEvent:event]) {
> +[super sendEvent: event];
> +}
>  }
>  @end
>  

if (!cocoaView || ![cocoaView handleEvent:event]) {

can be written as

if (![cocoaView handleEvent:event]) {

It's valid to send a message to nil and it will return 0/false/NO.

Thank you for working on the patch series. It definitely improves UI event
handling.

Besides the pixman_image leak,

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Roman

[Qemu-devel] [PATCH v1 2/6] softfloat: add float128_is_{normal, denormal}

2019-02-22 Thread Alex Bennée

From: David Hildenbrand 

Needed on s390x, to test for the data class of a number. So it will
gain soon a user.

A number is considered normal if the exponent is neither 0 nor all 1's.
That can be checked by adding 1 to the exponent, and comparing against
>= 2 after dropping an eventual overflow into the sign bit.

While at it, convert the other floatXX_is_normal functions to use a
similar, less error prone calculation, as suggested by Richard H.

Signed-off-by: David Hildenbrand 
Reviewed-by: Richard Henderson 
Signed-off-by: Alex Bennée 
---
 include/fpu/softfloat.h | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 38a5e99cf3..3ff5215b81 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -466,7 +466,7 @@ static inline int float32_is_zero_or_denormal(float32 a)
 
 static inline bool float32_is_normal(float32 a)
 {
-return ((float32_val(a) + 0x0080) & 0x7fff) >= 0x0100;
+return (((float32_val(a) >> 23) + 1) & 0xff) >= 2;
 }
 
 static inline bool float32_is_denormal(float32 a)
@@ -622,7 +622,7 @@ static inline int float64_is_zero_or_denormal(float64 a)
 
 static inline bool float64_is_normal(float64 a)
 {
-return ((float64_val(a) + (1ULL << 52)) & -1ULL >> 1) >= 1ULL << 53;
+return (((float64_val(a) >> 52) + 1) & 0x7ff) >= 2;
 }
 
 static inline bool float64_is_denormal(float64 a)
@@ -940,6 +940,16 @@ static inline int float128_is_zero_or_denormal(float128 a)
 return (a.high & 0x7fffLL) == 0;
 }
 
+static inline bool float128_is_normal(float128 a)
+{
+return (((a.high >> 48) + 1) & 0x7fff) >= 2;
+}
+
+static inline bool float128_is_denormal(float128 a)
+{
+return float128_is_zero_or_denormal(a) && !float128_is_zero(a);
+}
+
 static inline int float128_is_any_nan(float128 a)
 {
 return ((a.high >> 48) & 0x7fff) == 0x7fff &&
-- 
2.20.1

[Qemu-devel] [PATCH v1 4/6] tests/fp: add wrapping for f128_to_ui32

2019-02-22 Thread Alex Bennée

Needed to test: softfloat: add float128_is_{normal,denormal}

Signed-off-by: Alex Bennée 
---
 tests/fp/fp-test.c  | 3 ++-
 tests/fp/wrap.inc.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
index 2a35ef601d..4114f346a9 100644
--- a/tests/fp/fp-test.c
+++ b/tests/fp/fp-test.c
@@ -622,7 +622,8 @@ static void do_testfloat(int op, int rmode, bool exact)
 test_ab_extF80_z_bool(true_ab_extF80M_z_bool, subj_ab_extF80M_z_bool);
 break;
 case F128_TO_UI32:
-not_implemented();
+test_a_f128_z_ui32_rx(slow_f128M_to_ui32, qemu_f128M_to_ui32, rmode,
+  exact);
 break;
 case F128_TO_UI64:
 test_a_f128_z_ui64_rx(slow_f128M_to_ui64, qemu_f128M_to_ui64, rmode,
diff --git a/tests/fp/wrap.inc.c b/tests/fp/wrap.inc.c
index d3bf600cd0..0cbd20013e 100644
--- a/tests/fp/wrap.inc.c
+++ b/tests/fp/wrap.inc.c
@@ -367,6 +367,7 @@ WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag,
 WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t)
 WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t)
 
+WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t)
 WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t)
 #undef WRAP_128_TO_INT
 
-- 
2.20.1

[Qemu-devel] [PATCH v1 0/6] fpu/next, mostly bits s390x tcg will need

2019-02-22 Thread Alex Bennée

Hi,

Here is the current status of fpu/next. I intend to send the PR in
next week as there are bits in it blocking work for s390. This is the
last chance to pipe up with any objections.

The following patches need review
  0004/tests fp add wrapping for f128_to_ui32.patch
  0005/tests fp enable f128_to_ui 32 64 tests in float t.patch

Alex Bennée (2):
  tests/fp: add wrapping for f128_to_ui32
  tests/fp: enable f128_to_ui[32/64] tests in float-to-uint

David Hildenbrand (2):
  softfloat: add float128_is_{normal,denormal}
  softfloat: Implement float128_to_uint32

Eric Blake (1):
  tests: Ignore fp test outputs

Richard Henderson (1):
  softfloat: Support float_round_to_odd more places

 fpu/softfloat.c | 93 ++---
 include/fpu/softfloat.h | 15 ++-
 tests/.gitignore|  1 +
 tests/Makefile.include  |  7 ++--
 tests/fp/fp-test.c  | 46 +++-
 tests/fp/wrap.inc.c |  1 +
 6 files changed, 143 insertions(+), 20 deletions(-)

-- 
2.20.1

[Qemu-devel] [PATCH v1 1/6] tests: Ignore fp test outputs

2019-02-22 Thread Alex Bennée

From: Eric Blake 

Commit 2cade3d wired up new tests, but did not exclude the
new *.out files produced by running the tests.

Signed-off-by: Eric Blake 
Reviewed-by: Emilio G. Cota 
Signed-off-by: Alex Bennée 
---
 tests/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/.gitignore b/tests/.gitignore
index 72c18aaab0..f2bf85c8c4 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -5,6 +5,7 @@ benchmark-crypto-hmac
 check-*
 !check-*.c
 !check-*.sh
+fp/*.out
 qht-bench
 rcutorture
 test-*
-- 
2.20.1

[Qemu-devel] [PATCH v1 3/6] softfloat: Implement float128_to_uint32

2019-02-22 Thread Alex Bennée

From: David Hildenbrand 

Handling it just like float128_to_uint32_round_to_zero, that hopefully
is free of bugs :)

Documentation basically copied from float128_to_uint64

Signed-off-by: David Hildenbrand 
Reviewed-by: Richard Henderson 
Signed-off-by: Alex Bennée 
---
 fpu/softfloat.c | 29 +
 include/fpu/softfloat.h |  1 +
 2 files changed, 30 insertions(+)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 9132d7a0b0..c69cd6b5d1 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6792,6 +6792,35 @@ uint32_t float128_to_uint32_round_to_zero(float128 a, 
float_status *status)
 return res;
 }
 
+/*
+| Returns the result of converting the quadruple-precision floating-point value
+| `a' to the 32-bit unsigned integer format.  The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode.  If `a' is a NaN, the largest
+| positive integer is returned.  If the conversion overflows, the
+| largest unsigned integer is returned.  If 'a' is negative, the value is
+| rounded and zero is returned; negative values that do not round to zero
+| will raise the inexact exception.
+**/
+
+uint32_t float128_to_uint32(float128 a, float_status *status)
+{
+uint64_t v;
+uint32_t res;
+int old_exc_flags = get_float_exception_flags(status);
+
+v = float128_to_uint64(a, status);
+if (v > 0x) {
+res = 0x;
+} else {
+return v;
+}
+set_float_exception_flags(old_exc_flags, status);
+float_raise(float_flag_invalid, status);
+return res;
+}
+
 /*
 | Returns the result of converting the quadruple-precision floating-point
 | value `a' to the single-precision floating-point format.  The conversion
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 3ff5215b81..3ff3fa5224 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -878,6 +878,7 @@ int64_t float128_to_int64(float128, float_status *status);
 int64_t float128_to_int64_round_to_zero(float128, float_status *status);
 uint64_t float128_to_uint64(float128, float_status *status);
 uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+uint32_t float128_to_uint32(float128, float_status *status);
 uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
 float32 float128_to_float32(float128, float_status *status);
 float64 float128_to_float64(float128, float_status *status);
-- 
2.20.1

[Qemu-devel] [PATCH v1 5/6] tests/fp: enable f128_to_ui[32/64] tests in float-to-uint

2019-02-22 Thread Alex Bennée

We've just added f128_to_ui32 and we missed out the f128_to_ui64 tests
last time.

Signed-off-by: Alex Bennée 
---
 tests/Makefile.include | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/tests/Makefile.include b/tests/Makefile.include
index 3741f8f6dd..060f765b0e 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -909,8 +909,7 @@ test-softfloat = $(call quiet-command, \
 
 # Conversion Routines:
 # FIXME: i32_to_extF80 (broken), i64_to_extF80 (broken)
-#ui32_to_f128 (not implemented), f128_to_ui32 (not implemented)
-#extF80_roundToInt (broken)
+#ui32_to_f128 (not implemented), extF80_roundToInt (broken)
 #
 check-softfloat-conv: $(FP_TEST_BIN)
$(call test-softfloat, \
@@ -939,9 +938,11 @@ check-softfloat-conv: $(FP_TEST_BIN)
f16_to_ui32 f16_to_ui32_r_minMag \
f32_to_ui32 f32_to_ui32_r_minMag \
f64_to_ui32 f64_to_ui32_r_minMag \
+   f128_to_ui32 f128_to_ui32_r_minMag \
f16_to_ui64 f16_to_ui64_r_minMag \
f32_to_ui64 f32_to_ui64_r_minMag \
-   f64_to_ui64 f64_to_ui64_r_minMag, \
+   f64_to_ui64 f64_to_ui64_r_minMag \
+   f128_to_ui64 f128_to_ui64_r_minMag, \
float-to-uint)
$(call test-softfloat, \
f16_roundToInt f32_roundToInt \
-- 
2.20.1

[Qemu-devel] [PATCH v1 6/6] softfloat: Support float_round_to_odd more places

2019-02-22 Thread Alex Bennée

From: Richard Henderson 

Previously this was only supported for roundAndPackFloat64.

New support in round_canonical, round_to_int, float128_round_to_int,
roundAndPackFloat32, roundAndPackInt32, roundAndPackInt64,
roundAndPackUint64.  This does not include any of the floatx80 routines,
as we do not have users for that rounding mode there.

Signed-off-by: Richard Henderson 
Message-Id: <20190215170225.15537-1-richard.hender...@linaro.org>
Tested-by: David Hildenbrand 
Signed-off-by: Alex Bennée 
---
 fpu/softfloat.c| 64 ++
 tests/fp/fp-test.c | 43 ---
 2 files changed, 93 insertions(+), 14 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c69cd6b5d1..99c7cc2c3d 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -696,6 +696,7 @@ static FloatParts sf_canonicalize(FloatParts part, const 
FloatFmt *parm,
 static FloatParts round_canonical(FloatParts p, float_status *s,
   const FloatFmt *parm)
 {
+const uint64_t frac_lsb = parm->frac_lsb;
 const uint64_t frac_lsbm1 = parm->frac_lsbm1;
 const uint64_t round_mask = parm->round_mask;
 const uint64_t roundeven_mask = parm->roundeven_mask;
@@ -731,6 +732,10 @@ static FloatParts round_canonical(FloatParts p, 
float_status *s,
 inc = p.sign ? round_mask : 0;
 overflow_norm = !p.sign;
 break;
+case float_round_to_odd:
+overflow_norm = true;
+inc = frac & frac_lsb ? 0 : round_mask;
+break;
 default:
 g_assert_not_reached();
 }
@@ -778,9 +783,14 @@ static FloatParts round_canonical(FloatParts p, 
float_status *s,
 shift64RightJamming(frac, 1 - exp, );
 if (frac & round_mask) {
 /* Need to recompute round-to-even.  */
-if (s->float_rounding_mode == float_round_nearest_even) {
+switch (s->float_rounding_mode) {
+case float_round_nearest_even:
 inc = ((frac & roundeven_mask) != frac_lsbm1
? frac_lsbm1 : 0);
+break;
+case float_round_to_odd:
+inc = frac & frac_lsb ? 0 : round_mask;
+break;
 }
 flags |= float_flag_inexact;
 frac += inc;
@@ -1988,6 +1998,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
 case float_round_down:
 one = a.sign;
 break;
+case float_round_to_odd:
+one = true;
+break;
 default:
 g_assert_not_reached();
 }
@@ -2021,6 +2034,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
 case float_round_down:
 inc = a.sign ? rnd_mask : 0;
 break;
+case float_round_to_odd:
+inc = a.frac & frac_lsb ? 0 : rnd_mask;
+break;
 default:
 g_assert_not_reached();
 }
@@ -3314,6 +3330,9 @@ static int32_t roundAndPackInt32(flag zSign, uint64_t 
absZ, float_status *status
 case float_round_down:
 roundIncrement = zSign ? 0x7f : 0;
 break;
+case float_round_to_odd:
+roundIncrement = absZ & 0x80 ? 0 : 0x7f;
+break;
 default:
 abort();
 }
@@ -3368,6 +3387,9 @@ static int64_t roundAndPackInt64(flag zSign, uint64_t 
absZ0, uint64_t absZ1,
 case float_round_down:
 increment = zSign && absZ1;
 break;
+case float_round_to_odd:
+increment = !(absZ0 & 1) && absZ1;
+break;
 default:
 abort();
 }
@@ -3424,6 +3446,9 @@ static int64_t roundAndPackUint64(flag zSign, uint64_t 
absZ0,
 case float_round_down:
 increment = zSign && absZ1;
 break;
+case float_round_to_odd:
+increment = !(absZ0 & 1) && absZ1;
+break;
 default:
 abort();
 }
@@ -3526,6 +3551,8 @@ static float32 roundAndPackFloat32(flag zSign, int zExp, 
uint32_t zSig,
 case float_round_down:
 roundIncrement = zSign ? 0x7f : 0;
 break;
+case float_round_to_odd:
+roundIncrement = zSig & 0x80 ? 0 : 0x7f;
 default:
 abort();
 break;
@@ -3536,8 +3563,10 @@ static float32 roundAndPackFloat32(flag zSign, int zExp, 
uint32_t zSig,
  || (( zExp == 0xFD )
   && ( (int32_t) ( zSig + roundIncrement ) < 0 ) )
) {
+bool overflow_to_inf = roundingMode != float_round_to_odd &&
+   roundIncrement != 0;
 float_raise(float_flag_overflow | float_flag_inexact, status);
-return packFloat32( zSign, 0xFF, - ( roundIncrement == 0 ));
+return packFloat32(zSign, 0xFF, -!overflow_to_inf);
 }
 if ( zExp < 0 ) {
 if

Re: [Qemu-devel] [PATCH v2] softfloat: Support float_round_to_odd more places

2019-02-22 Thread Alex Bennée



Richard Henderson  writes:

> Previously this was only supported for roundAndPackFloat64.
>
> New support in round_canonical, round_to_int, float128_round_to_int,
> roundAndPackFloat32, roundAndPackInt32, roundAndPackInt64,
> roundAndPackUint64.  This does not include any of the floatx80 routines,
> as we do not have users for that rounding mode there.
>
> Signed-off-by: Richard Henderson 

Queued to fpu/next, thanks.

> ---
> v2: Convert float128_round_to_int as well.  Add fp-test support.
> ---
>  fpu/softfloat.c| 64 ++
>  tests/fp/fp-test.c | 43 ---
>  2 files changed, 93 insertions(+), 14 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 9132d7a0b0..76132d4cd5 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -696,6 +696,7 @@ static FloatParts sf_canonicalize(FloatParts part, const 
> FloatFmt *parm,
>  static FloatParts round_canonical(FloatParts p, float_status *s,
>const FloatFmt *parm)
>  {
> +const uint64_t frac_lsb = parm->frac_lsb;
>  const uint64_t frac_lsbm1 = parm->frac_lsbm1;
>  const uint64_t round_mask = parm->round_mask;
>  const uint64_t roundeven_mask = parm->roundeven_mask;
> @@ -731,6 +732,10 @@ static FloatParts round_canonical(FloatParts p, 
> float_status *s,
>  inc = p.sign ? round_mask : 0;
>  overflow_norm = !p.sign;
>  break;
> +case float_round_to_odd:
> +overflow_norm = true;
> +inc = frac & frac_lsb ? 0 : round_mask;
> +break;
>  default:
>  g_assert_not_reached();
>  }
> @@ -778,9 +783,14 @@ static FloatParts round_canonical(FloatParts p, 
> float_status *s,
>  shift64RightJamming(frac, 1 - exp, );
>  if (frac & round_mask) {
>  /* Need to recompute round-to-even.  */
> -if (s->float_rounding_mode == float_round_nearest_even) {
> +switch (s->float_rounding_mode) {
> +case float_round_nearest_even:
>  inc = ((frac & roundeven_mask) != frac_lsbm1
> ? frac_lsbm1 : 0);
> +break;
> +case float_round_to_odd:
> +inc = frac & frac_lsb ? 0 : round_mask;
> +break;
>  }
>  flags |= float_flag_inexact;
>  frac += inc;
> @@ -1988,6 +1998,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
>  case float_round_down:
>  one = a.sign;
>  break;
> +case float_round_to_odd:
> +one = true;
> +break;
>  default:
>  g_assert_not_reached();
>  }
> @@ -2021,6 +2034,9 @@ static FloatParts round_to_int(FloatParts a, int rmode,
>  case float_round_down:
>  inc = a.sign ? rnd_mask : 0;
>  break;
> +case float_round_to_odd:
> +inc = a.frac & frac_lsb ? 0 : rnd_mask;
> +break;
>  default:
>  g_assert_not_reached();
>  }
> @@ -3314,6 +3330,9 @@ static int32_t roundAndPackInt32(flag zSign, uint64_t 
> absZ, float_status *status
>  case float_round_down:
>  roundIncrement = zSign ? 0x7f : 0;
>  break;
> +case float_round_to_odd:
> +roundIncrement = absZ & 0x80 ? 0 : 0x7f;
> +break;
>  default:
>  abort();
>  }
> @@ -3368,6 +3387,9 @@ static int64_t roundAndPackInt64(flag zSign, uint64_t 
> absZ0, uint64_t absZ1,
>  case float_round_down:
>  increment = zSign && absZ1;
>  break;
> +case float_round_to_odd:
> +increment = !(absZ0 & 1) && absZ1;
> +break;
>  default:
>  abort();
>  }
> @@ -3424,6 +3446,9 @@ static int64_t roundAndPackUint64(flag zSign, uint64_t 
> absZ0,
>  case float_round_down:
>  increment = zSign && absZ1;
>  break;
> +case float_round_to_odd:
> +increment = !(absZ0 & 1) && absZ1;
> +break;
>  default:
>  abort();
>  }
> @@ -3526,6 +3551,8 @@ static float32 roundAndPackFloat32(flag zSign, int 
> zExp, uint32_t zSig,
>  case float_round_down:
>  roundIncrement = zSign ? 0x7f : 0;
>  break;
> +case float_round_to_odd:
> +roundIncrement = zSig & 0x80 ? 0 : 0x7f;
>  default:
>  abort();
>  break;
> @@ -3536,8 +3563,10 @@ static float32 roundAndPackFloat32(flag zSign, int 
> zExp, uint32_t zSig,
>   || (( zExp == 0xFD )
>&& ( (int32_t) ( zSig + roundIncrement ) < 0 ) )
> ) {
> +bool overflow_to_inf = roundingMode != float_round_to_odd &&
> +   roundIncrement != 0;
>

[Qemu-devel] [Bug 1813165] Re: KVM internal error. Suberror: 1 emulation failure

2019-02-22 Thread Albert Damen

The patch works fine for me too, many thanks!

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1813165

Title:
  KVM internal error. Suberror: 1 emulation failure

Status in QEMU:
  New

Bug description:
  Hello Devs.

  Having problems getting VM to run with qemu 3.1.0. I should mention
  it's a nested configuration.

  2019-01-24 13:46:08.648+: starting up libvirt version: 4.10.0, qemu 
version: 3.1.0, kernel: 4.14.94, hostname: one
  LC_ALL=C 
PATH=/bin:/sbin:/bin:/sbin:/usr/bin:/usr/sbin:/usr/bin:/usr/sbin:/usr/local/bin:/usr/local/sbin:/opt/bin
 HOME=/root USER=root QEMU_AUDIO_DRV=none /usr/bin/kvm -name 
guest=one-266,debug-threads=on -S -object 
secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-1-one-266/master-key.aes
 -machine pc-i440fx-2.9,accel=kvm,usb=off,dump-guest-core=off -cpu 
Skylake-Client-IBRS,ss=on,hypervisor=on,tsc_adjust=on,clflushopt=on,ssbd=on,xsaves=on,pdpe1gb=on
 -m 1024 -realtime mlock=off -smp 2,sockets=2,cores=1,threads=1 -uuid 
b219b45d-a2f0-4128-a948-8673a7abf968 -no-user-config -nodefaults -chardev 
socket,id=charmonitor,fd=21,server,nowait -mon 
chardev=charmonitor,id=monitor,mode=control -rtc base=utc -no-shutdown -boot 
strict=on -device piix3-usb-uhci,id=usb,bus=pci.0,addr=0x1.0x2 -drive 
file=/var/lib/one//datastores/0/266/disk.0,format=qcow2,if=none,id=drive-virtio-disk0,cache=none
 -device 
virtio-blk-pci,scsi=off,bus=pci.0,addr=0x4,drive=drive-virtio-disk0,id=virtio-disk0,bootindex=1,write-cache=on
 -drive 
file=/var/lib/one//datastores/0/266/disk.1,format=raw,if=none,id=drive-ide0-0-0,readonly=on
 -device ide-cd,bus=ide.0,unit=0,drive=drive-ide0-0-0,id=ide0-0-0 -netdev 
tap,fd=23,id=hostnet0 -device 
rtl8139,netdev=hostnet0,id=net0,mac=02:00:00:76:69:85,bus=pci.0,addr=0x3 
-chardev pty,id=charserial0 -device isa-serial,chardev=charserial0,id=serial0 
-vnc 0.0.0.0:266 -device cirrus-vga,id=video0,bus=pci.0,addr=0x2 -device 
virtio-balloon-pci,id=balloon0,bus=pci.0,addr=0x5 -sandbox 
on,obsolete=deny,elevateprivileges=deny,spawn=deny,resourcecontrol=deny -msg 
timestamp=on
  char device redirected to /dev/pts/1 (label charserial0)
  KVM internal error. Suberror: 1
  emulation failure
  EAX=0001 EBX=000f7c2c ECX=0001 EDX=0001
  ESI=6a26 EDI=3ffbdc48 EBP=69e6 ESP=000a8000
  EIP=000fd057 EFL=00010016 [AP-] CPL=0 II=0 A20=1 SMM=1 HLT=0
  ES =0010   00c09300
  CS =  0fff 00809b00
  SS =0010   00c09300
  DS =0010   00c09300
  FS =0010   00c09300
  GS =0010   00c09300
  LDT=   8200
  TR =   8b00
  GDT= 10387cfe fe6c
  IDT= 0010387c 3810
  CR0=0010 CR2= CR3= CR4=
  DR0= DR1= DR2= 
DR3=
  DR6=fffecffc DR7=0e1e0400
  EFER=
  Code=cb 66 ba 4d d0 0f 00 e9 c8 fe bc 00 80 0a 00 e8 31 3a ff ff <0f> aa fa 
fc 66 ba 66 d0 0f 00 e9 b1 fe f3 90 f0 0f ba 2d ac 3b 0f 00 00 72 f3 8b 25 a8 3b
  2019-01-24T13:47:39.383366Z kvm: terminating on signal 15 from pid 2708 
(/usr/sbin/libvirtd)

  Someone has an idea whats going wrong here?

  thanks and cheers
  t.

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Re: [Qemu-devel] [PATCH] tcg/ppc: Add vector opcodes

2019-02-22 Thread Richard Henderson

On 2/22/19 9:13 AM, Mark Cave-Ayland wrote:
> On 22/02/2019 05:59, Richard Henderson wrote:
> 
>> This requires VSX, not just Altivec, so Power7 or later.
>>
>> Signed-off-by: Richard Henderson 
>> ---
>>
>> At present there are no tunables that can avoid the 64-bit element
>> load/store requirement.  As with requiring AVX1 for x86 hosts, I'm
>> not sure it's worth inventing such a tunable for pre-power7 hosts.
>>
>> Tested vs aarch64 risu test cases.  It's probably worth testing
>> this vs Mark's target/ppc conversion.
> 
> Oooh this looks really exciting! However... I only have a G4 Mac Mini around 
> that I
> use for testing which is Altivec-only :(  Is it much work to support non-VSX 
> hosts?

Hmm, dunno.  I'll think about it.

> This leads me to a related point that came up when Howard and I were testing 
> the PPC
> vector patches - how do we know at runtime which optimisations were being 
> used, e.g.
> what is the value of have_avx2 on a particular CPU running QEMU?

There is no way from within qemu itself.

> Under Linux this isn't too bad since you can just do "cat /proc/cpuinfo | 
> grep avx2"
> but it becomes more tricky when getting bug reports from Windows users who 
> aren't
> particularly technical...

Something like:
https://www.intel.com/content/www/us/en/support/articles/05651/processors.html

or any one of several other utilities that can display cpuid information.


r~

Re: [Qemu-devel] [PATCH v2 6/7] ui/cocoa: Subclass NSApplication so we can implement sendEvent

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:15AM +, Peter Maydell wrote:
> When we switch away from our custom event handling, we still want to
> be able to have first go at any events our application receives,
> because in full-screen mode we want to send key events to the guest,
> even if they would be menu item activation events. There are several
> ways we could do that, but one simple approach is to subclass
> NSApplication so we can implement a custom sendEvent method.
> Do that, but for the moment have our sendEvent just invoke the
> superclass method.
> 
> Signed-off-by: Peter Maydell 
> ---
> New patch in v2
> ---
>  ui/cocoa.m | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Thanks,
Roman

Re: [Qemu-devel] [PATCH v3 15/20] Boot Linux Console Test: add a test for mips64el + malta

2019-02-22 Thread Aleksandar Markovic

> From: Cleber Rosa 
> Subject: [PATCH v3 15/20] Boot Linux Console Test: add a test for mips64el + 
> malta
> 
> Similar to the x86_64 + pc test, it boots a Linux kernel on a Malta
> board and verify the serial is working.
> 

Reviewed-by: Aleksandar Markovic

Re: [Qemu-devel] [PATCH v3 14/20] Boot Linux Console Test: add a test for mips + malta

2019-02-22 Thread Aleksandar Markovic

> From: Cleber Rosa 
> Subject: [PATCH v3 14/20] Boot Linux Console Test: add a test for mips + malta
> 
> From: Philippe Mathieu-Daudé 
> 
> Similar to the x86_64 + pc test, it boots a Linux kernel on a Malta
> board and verify the serial is working.  Also, it relies on the serial
> device set by the machine itself.

Reviewed-by: Aleksandar Markovic

[Qemu-devel] [PULL 7/7] Acceptance tests: expect boot to extract 2GiB+ initrd with linux-v4.16

2019-02-22 Thread Cleber Rosa

From: Li Zhijian 

XLF_CAN_BE_LOADED_ABOVE_4G is set on vmlinuz shipped by Fedora-28 so that
it's allowed to be loaded below 4 GB address.

timeout is updated to 5 minutes as well since we need more time to load a
large initrd to the guest

CC: Wainer dos Santos Moschetta 
CC: Caio Carrara 
CC: Cleber Rosa 
CC: Eduardo Habkost 
CC: Philippe Mathieu-Daudé 
Signed-off-by: Li Zhijian 
Reviewed-by: Wainer dos Santos Moschetta 
Reviewed-by: Cleber Rosa 
Message-Id: <1548638112-31101-2-git-send-email-lizhij...@cn.fujitsu.com>
Signed-off-by: Cleber Rosa 
---
 tests/acceptance/linux_initrd.py | 37 +++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/tests/acceptance/linux_initrd.py b/tests/acceptance/linux_initrd.py
index e33b5dcec0..fbdb48e43f 100644
--- a/tests/acceptance/linux_initrd.py
+++ b/tests/acceptance/linux_initrd.py
@@ -8,6 +8,7 @@
 # This work is licensed under the terms of the GNU GPL, version 2 or
 # later.  See the COPYING file in the top-level directory.
 
+import logging
 import tempfile
 from avocado.utils.process import run
 
@@ -21,7 +22,7 @@ class LinuxInitrd(Test):
 :avocado: tags=x86_64
 """
 
-timeout = 60
+timeout = 300
 
 def test_with_2gib_file_should_exit_error_msg_with_linux_v3_6(self):
 """
@@ -47,3 +48,37 @@ class LinuxInitrd(Test):
 expected_msg = r'.*initrd is too large.*max: \d+, need %s.*' % (
 max_size + 1)
 self.assertRegex(res.stderr_text, expected_msg)
+
+def test_with_2gib_file_should_work_with_linux_v4_16(self):
+"""
+QEMU has supported up to 4 GiB initrd for recent kernel
+Expect guest can reach 'Unpacking initramfs...'
+"""
+kernel_url = ('https://mirrors.kernel.org/fedora/releases/28/'
+  'Everything/x86_64/os/images/pxeboot/vmlinuz')
+kernel_hash = '238e083e114c48200f80d889f7e32eeb2793e02a'
+kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+max_size = 2 * (1024 ** 3) + 1
+
+with tempfile.NamedTemporaryFile() as initrd:
+initrd.seek(max_size)
+initrd.write(b'\0')
+initrd.flush()
+
+self.vm.set_machine('pc')
+self.vm.set_console()
+kernel_command_line = 'console=ttyS0'
+self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line,
+ '-initrd', initrd.name,
+ '-m', '5120')
+self.vm.launch()
+console = self.vm.console_socket.makefile()
+console_logger = logging.getLogger('console')
+while True:
+msg = console.readline()
+console_logger.debug(msg.strip())
+if 'Unpacking initramfs...' in msg:
+break
+if 'Kernel panic - not syncing' in msg:
+self.fail("Kernel panic reached")
-- 
2.20.1

[Qemu-devel] [PULL 5/7] tests.acceptance: adds simple migration test

2019-02-22 Thread Cleber Rosa

From: Caio Carrara 

This change adds the simplest possible migration test. Beyond the test
purpose itself it's also useful to exercise the multi virtual machines
capabilities from base avocado qemu test class.

Signed-off-by: Cleber Rosa 
Signed-off-by: Caio Carrara 
Reviewed-by: Cleber Rosa 
Reviewed-by: Wainer dos Santos Moschetta 
Message-Id: <20190212193855.13223-3-ccarr...@redhat.com>
Signed-off-by: Cleber Rosa 
---
 tests/acceptance/migration.py | 53 +++
 1 file changed, 53 insertions(+)
 create mode 100644 tests/acceptance/migration.py

diff --git a/tests/acceptance/migration.py b/tests/acceptance/migration.py
new file mode 100644
index 00..6115cf6c24
--- /dev/null
+++ b/tests/acceptance/migration.py
@@ -0,0 +1,53 @@
+# Migration test
+#
+# Copyright (c) 2019 Red Hat, Inc.
+#
+# Authors:
+#  Cleber Rosa 
+#  Caio Carrara 
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later.  See the COPYING file in the top-level directory.
+
+
+from avocado_qemu import Test
+
+from avocado.utils import network
+from avocado.utils import wait
+
+
+class Migration(Test):
+"""
+:avocado: enable
+"""
+
+timeout = 10
+
+@staticmethod
+def migration_finished(vm):
+return vm.command('query-migrate')['status'] in ('completed', 'failed')
+
+def _get_free_port(self):
+port = network.find_free_port()
+if port is None:
+self.cancel('Failed to find a free port')
+return port
+
+
+def test_migration_with_tcp_localhost(self):
+source_vm = self.get_vm()
+dest_uri = 'tcp:localhost:%u' % self._get_free_port()
+dest_vm = self.get_vm('-incoming', dest_uri)
+dest_vm.launch()
+source_vm.launch()
+source_vm.qmp('migrate', uri=dest_uri)
+wait.wait_for(
+self.migration_finished,
+timeout=self.timeout,
+step=0.1,
+args=(source_vm,)
+)
+self.assertEqual(dest_vm.command('query-migrate')['status'], 
'completed')
+self.assertEqual(source_vm.command('query-migrate')['status'], 
'completed')
+self.assertEqual(dest_vm.command('query-status')['status'], 'running')
+self.assertEqual(source_vm.command('query-status')['status'], 
'postmigrate')
-- 
2.20.1

[Qemu-devel] [PULL 2/7] Introduce a Python module structure

2019-02-22 Thread Cleber Rosa

This is a simple move of Python code that wraps common QEMU
functionality, and are used by a number of different tests
and scripts.

By treating that code as a real Python module, we can more easily:
 * reuse code
 * have a proper place for the module's own unittests
 * apply a more consistent style
 * generate documentation

Signed-off-by: Cleber Rosa 
Reviewed-by: Caio Carrara 
Reviewed-by: Stefan Hajnoczi 
Message-Id: <20190206162901.19082-2-cr...@redhat.com>
Signed-off-by: Cleber Rosa 
---
 configure  |  1 +
 scripts/qemu.py => python/qemu/__init__.py | 11 ++-
 {scripts/qmp => python/qemu}/qmp.py|  0
 {scripts => python/qemu}/qtest.py  |  5 +++--
 scripts/device-crash-test  |  2 ++
 scripts/qmp/__init__.py|  0
 scripts/qmp/qemu-ga-client |  5 -
 scripts/qmp/qmp-shell  |  4 +++-
 scripts/render_block_graph.py  |  2 ++
 tests/acceptance/avocado_qemu/__init__.py  |  5 ++---
 tests/acceptance/virtio_version.py |  2 +-
 tests/migration/guestperf/engine.py|  7 ---
 tests/qemu-iotests/235 |  2 +-
 tests/qemu-iotests/238 |  2 +-
 tests/qemu-iotests/iotests.py  |  4 ++--
 tests/vm/basevm.py |  2 +-
 16 files changed, 33 insertions(+), 21 deletions(-)
 rename scripts/qemu.py => python/qemu/__init__.py (98%)
 rename {scripts/qmp => python/qemu}/qmp.py (100%)
 rename {scripts => python/qemu}/qtest.py (98%)
 delete mode 100644 scripts/qmp/__init__.py

diff --git a/configure b/configure
index a61682c3c7..343dd004e9 100755
--- a/configure
+++ b/configure
@@ -7604,6 +7604,7 @@ LINKS="$LINKS pc-bios/qemu-icon.bmp"
 LINKS="$LINKS .gdbinit scripts" # scripts needed by relative path in .gdbinit
 LINKS="$LINKS tests/acceptance tests/data"
 LINKS="$LINKS tests/qemu-iotests/check"
+LINKS="$LINKS python"
 for bios_file in \
 $source_path/pc-bios/*.bin \
 $source_path/pc-bios/*.lid \
diff --git a/scripts/qemu.py b/python/qemu/__init__.py
similarity index 98%
rename from scripts/qemu.py
rename to python/qemu/__init__.py
index 32b00af5cc..38de3e9177 100644
--- a/scripts/qemu.py
+++ b/python/qemu/__init__.py
@@ -16,12 +16,13 @@ import errno
 import logging
 import os
 import subprocess
-import qmp.qmp
 import re
 import shutil
 import socket
 import tempfile
 
+from . import qmp
+
 
 LOG = logging.getLogger(__name__)
 
@@ -66,7 +67,7 @@ class QEMUMachineAddDeviceError(QEMUMachineError):
 failures reported by the QEMU binary itself.
 """
 
-class MonitorResponseError(qmp.qmp.QMPError):
+class MonitorResponseError(qmp.QMPError):
 """
 Represents erroneous QMP monitor reply
 """
@@ -267,8 +268,8 @@ class QEMUMachine(object):
 self._qemu_log_path = os.path.join(self._temp_dir, self._name + ".log")
 self._qemu_log_file = open(self._qemu_log_path, 'wb')
 
-self._qmp = qmp.qmp.QEMUMonitorProtocol(self._vm_monitor,
-server=True)
+self._qmp = qmp.QEMUMonitorProtocol(self._vm_monitor,
+server=True)
 
 def _post_launch(self):
 self._qmp.accept()
@@ -384,7 +385,7 @@ class QEMUMachine(object):
 """
 reply = self.qmp(cmd, conv_keys, **args)
 if reply is None:
-raise qmp.qmp.QMPError("Monitor is closed")
+raise qmp.QMPError("Monitor is closed")
 if "error" in reply:
 raise MonitorResponseError(reply)
 return reply["return"]
diff --git a/scripts/qmp/qmp.py b/python/qemu/qmp.py
similarity index 100%
rename from scripts/qmp/qmp.py
rename to python/qemu/qmp.py
diff --git a/scripts/qtest.py b/python/qemu/qtest.py
similarity index 98%
rename from scripts/qtest.py
rename to python/qemu/qtest.py
index afac3fe900..eb45824dd0 100644
--- a/scripts/qtest.py
+++ b/python/qemu/qtest.py
@@ -13,7 +13,8 @@
 
 import socket
 import os
-import qemu
+
+from . import QEMUMachine
 
 
 class QEMUQtestProtocol(object):
@@ -79,7 +80,7 @@ class QEMUQtestProtocol(object):
 self._sock.settimeout(timeout)
 
 
-class QEMUQtestMachine(qemu.QEMUMachine):
+class QEMUQtestMachine(QEMUMachine):
 '''A QEMU VM'''
 
 def __init__(self, binary, args=None, name=None, test_dir="/var/tmp",
diff --git a/scripts/device-crash-test b/scripts/device-crash-test
index 2a13fa4f84..a6748910ad 100755
--- a/scripts/device-crash-test
+++ b/scripts/device-crash-test
@@ -25,6 +25,7 @@ check for crashes and unexpected errors.
 """
 from __future__ import print_function
 
+import os
 import sys
 import glob
 import logging
@@ -34,6 +35,7 @@ import random
 import argparse
 from itertools import chain
 
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', 'python'))
 from qemu import QEMUMachine
 
 logger = logging.getLogger('device-crash-test')
diff --git a/scripts/qmp/__init__.py

[Qemu-devel] [PULL 3/7] scripts/qemu.py: log QEMU launch command line

2019-02-22 Thread Cleber Rosa

Even when the launch of QEMU succeeds, it's useful to have the command
line recorded.

Reviewed-by: Caio Carrara 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Alex Bennée 
Signed-off-by: Cleber Rosa 
Message-Id: <20190202005610.24048-2-cr...@redhat.com>
Signed-off-by: Cleber Rosa 
---
 python/qemu/__init__.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/python/qemu/__init__.py b/python/qemu/__init__.py
index 38de3e9177..585cd2a1a3 100644
--- a/python/qemu/__init__.py
+++ b/python/qemu/__init__.py
@@ -321,6 +321,7 @@ class QEMUMachine(object):
 self._pre_launch()
 self._qemu_full_args = (self._wrapper + [self._binary] +
 self._base_args() + self._args)
+LOG.debug('VM launch command: %r', ' '.join(self._qemu_full_args))
 self._popen = subprocess.Popen(self._qemu_full_args,
stdin=devnull,
stdout=self._qemu_log_file,
-- 
2.20.1

[Qemu-devel] [PULL 0/7] Python queue, 2019-02-22

2019-02-22 Thread Cleber Rosa

The following changes since commit 8eb29f1bf5a974dc4c11d2d1f5e7c7f7a62be116:

  Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20190221.0' 
into staging (2019-02-22 15:48:04 +)

are available in the Git repository at:

  git://github.com/clebergnu/qemu.git tags/python-next-pull-request

for you to fetch changes up to 8f1c89ec7443e4fa2cf106d8fa1c1c97b6ddeffb:

  Acceptance tests: expect boot to extract 2GiB+ initrd with linux-v4.16 
(2019-02-22 14:07:01 -0500)


Python queue, 2019-02-22

Python:
* introduce "python" directory with module namespace
* log QEMU launch command line on qemu.QEMUMachine

Acceptance Tests:
* initrd 4GiB+ test
* migration test
* multi vm support in test class
* bump Avocado version and drop ":avocado: enable"



Caio Carrara (2):
  tests.acceptance: adds multi vm capability for acceptance tests
  tests.acceptance: adds simple migration test

Cleber Rosa (3):
  Acceptance tests: drop usage of ":avocado: enable"
  Introduce a Python module structure
  scripts/qemu.py: log QEMU launch command line

Li Zhijian (2):
  Acceptance tests: use linux-3.6 and set vm memory to 4GiB
  Acceptance tests: expect boot to extract 2GiB+ initrd with linux-v4.16

 configure  |  1 +
 docs/devel/testing.rst | 42 -
 scripts/qemu.py => python/qemu/__init__.py | 12 +++--
 {scripts/qmp => python/qemu}/qmp.py|  0
 {scripts => python/qemu}/qtest.py  |  5 +-
 scripts/device-crash-test  |  2 +
 scripts/qmp/__init__.py|  0
 scripts/qmp/qemu-ga-client |  5 +-
 scripts/qmp/qmp-shell  |  4 +-
 scripts/render_block_graph.py  |  2 +
 tests/acceptance/avocado_qemu/__init__.py  | 30 +---
 tests/acceptance/boot_linux_console.py |  1 -
 tests/acceptance/linux_initrd.py   | 52 +
 tests/acceptance/migration.py  | 53 ++
 tests/acceptance/version.py|  1 -
 tests/acceptance/virtio_version.py |  3 +-
 tests/acceptance/vnc.py|  1 -
 tests/migration/guestperf/engine.py|  7 +--
 tests/qemu-iotests/235 |  2 +-
 tests/qemu-iotests/238 |  2 +-
 tests/qemu-iotests/iotests.py  |  4 +-
 tests/requirements.txt |  2 +-
 tests/vm/basevm.py |  2 +-
 23 files changed, 193 insertions(+), 40 deletions(-)
 rename scripts/qemu.py => python/qemu/__init__.py (98%)
 rename {scripts/qmp => python/qemu}/qmp.py (100%)
 rename {scripts => python/qemu}/qtest.py (98%)
 delete mode 100644 scripts/qmp/__init__.py
 create mode 100644 tests/acceptance/migration.py

-- 
2.20.1

[Qemu-devel] [PULL 6/7] Acceptance tests: use linux-3.6 and set vm memory to 4GiB

2019-02-22 Thread Cleber Rosa

From: Li Zhijian 

QEMU have already supported to load up to 4G initrd if the sepcified memory is
enough and XLF_CAN_BE_LOADED_ABOVE_4G is set by guest kernel

linux-3.6 kernel shipped by Fedora-18 cannot support xldflags so that it
cannot support loading more than 2GiB initrd

CC: Wainer dos Santos Moschetta 
CC: Caio Carrara 
CC: Cleber Rosa 
CC: Eduardo Habkost 
CC: Philippe Mathieu-Daudé 
Signed-off-by: Li Zhijian 
Reviewed-by: Wainer dos Santos Moschetta 
Reviewed-by: Cleber Rosa 
Message-Id: <1548638112-31101-1-git-send-email-lizhij...@cn.fujitsu.com>
Signed-off-by: Cleber Rosa 
---
 tests/acceptance/linux_initrd.py | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/tests/acceptance/linux_initrd.py b/tests/acceptance/linux_initrd.py
index 5a15fc4347..e33b5dcec0 100644
--- a/tests/acceptance/linux_initrd.py
+++ b/tests/acceptance/linux_initrd.py
@@ -23,14 +23,16 @@ class LinuxInitrd(Test):
 
 timeout = 60
 
-def test_with_2gib_file_should_exit_error_msg(self):
+def test_with_2gib_file_should_exit_error_msg_with_linux_v3_6(self):
 """
 Pretends to boot QEMU with an initrd file with size of 2GiB
 and expect it exits with error message.
+Fedora-18 shipped with linux-3.6 which have not supported xloadflags
+cannot support more than 2GiB initrd.
 """
-kernel_url = ('https://mirrors.kernel.org/fedora/releases/28/'
-  'Everything/x86_64/os/images/pxeboot/vmlinuz')
-kernel_hash = '238e083e114c48200f80d889f7e32eeb2793e02a'
+kernel_url = 
('https://archives.fedoraproject.org/pub/archive/fedora/li'
+  
'nux/releases/18/Fedora/x86_64/os/images/pxeboot/vmlinuz')
+kernel_hash = '41464f68efe42b9991250bed86c7081d2ccdbb21'
 kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 max_size = 2 * (1024 ** 3) - 1
 
@@ -38,8 +40,8 @@ class LinuxInitrd(Test):
 initrd.seek(max_size)
 initrd.write(b'\0')
 initrd.flush()
-cmd = "%s -kernel %s -initrd %s" % (self.qemu_bin, kernel_path,
-initrd.name)
+cmd = "%s -kernel %s -initrd %s -m 4096" % (
+  self.qemu_bin, kernel_path, initrd.name)
 res = run(cmd, ignore_status=True)
 self.assertEqual(res.exit_status, 1)
 expected_msg = r'.*initrd is too large.*max: \d+, need %s.*' % (
-- 
2.20.1

[Qemu-devel] [PULL 4/7] tests.acceptance: adds multi vm capability for acceptance tests

2019-02-22 Thread Cleber Rosa

From: Caio Carrara 

This change adds the possibility to write acceptance tests with multi
virtual machine support. It's done keeping the virtual machines objects
stored in a test attribute (dictionary). This dictionary shouldn't be
accessed directly but through the new method added `get_vm`. This new
method accept a list of args (that will be added as virtual machine
arguments) and an optional name argument. The name is the key that
identify a single virtual machine along the test machines available. If
a name without a machine is informed a new machine will be instantiated.

The current usage of vm in tests will not be broken by this change since
it keeps a property called vm in the base test class. This property only
calls the new method `get_vm` with default parameters (no args and
'default' as machine name).

Signed-off-by: Caio Carrara 
Reviewed-by: Cleber Rosa 
Reviewed-by: Wainer dos Santos Moschetta 
Message-Id: <20190212193855.13223-2-ccarr...@redhat.com>
Signed-off-by: Cleber Rosa 
---
 docs/devel/testing.rst| 41 ++-
 tests/acceptance/avocado_qemu/__init__.py | 25 +++---
 2 files changed, 61 insertions(+), 5 deletions(-)

diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst
index 3ce171829d..60f897d915 100644
--- a/docs/devel/testing.rst
+++ b/docs/devel/testing.rst
@@ -633,7 +633,46 @@ instance, available at ``self.vm``.  Because many tests 
will tweak the
 QEMU command line, launching the QEMUMachine (by using ``self.vm.launch()``)
 is left to the test writer.
 
-At test "tear down", ``avocado_qemu.Test`` handles the QEMUMachine
+The base test class has also support for tests with more than one
+QEMUMachine. The way to get machines is through the ``self.get_vm()``
+method which will return a QEMUMachine instance. The ``self.get_vm()``
+method accepts arguments that will be passed to the QEMUMachine creation
+and also an optional `name` attribute so you can identify a specific
+machine and get it more than once through the tests methods. A simple
+and hypothetical example follows:
+
+.. code::
+
+  from avocado_qemu import Test
+
+
+  class MultipleMachines(Test):
+  """
+  :avocado: enable
+  """
+  def test_multiple_machines(self):
+  first_machine = self.get_vm()
+  second_machine = self.get_vm()
+  self.get_vm(name='third_machine').launch()
+
+  first_machine.launch()
+  second_machine.launch()
+
+  first_res = first_machine.command(
+  'human-monitor-command',
+  command_line='info version')
+
+  second_res = second_machine.command(
+  'human-monitor-command',
+  command_line='info version')
+
+  third_res = self.get_vm(name='third_machine').command(
+  'human-monitor-command',
+  command_line='info version')
+
+  self.assertEquals(first_res, second_res, third_res)
+
+At test "tear down", ``avocado_qemu.Test`` handles all the QEMUMachines
 shutdown.
 
 QEMUMachine
diff --git a/tests/acceptance/avocado_qemu/__init__.py 
b/tests/acceptance/avocado_qemu/__init__.py
index 28bfb8e9d3..a66ec72daa 100644
--- a/tests/acceptance/avocado_qemu/__init__.py
+++ b/tests/acceptance/avocado_qemu/__init__.py
@@ -10,6 +10,7 @@
 
 import os
 import sys
+import uuid
 
 import avocado
 
@@ -41,13 +42,29 @@ def pick_default_qemu_bin():
 
 class Test(avocado.Test):
 def setUp(self):
-self.vm = None
+self._vms = {}
 self.qemu_bin = self.params.get('qemu_bin',
 default=pick_default_qemu_bin())
 if self.qemu_bin is None:
 self.cancel("No QEMU binary defined or found in the source tree")
-self.vm = QEMUMachine(self.qemu_bin)
+
+def _new_vm(self, *args):
+vm = QEMUMachine(self.qemu_bin)
+if args:
+vm.add_args(*args)
+return vm
+
+@property
+def vm(self):
+return self.get_vm(name='default')
+
+def get_vm(self, *args, name=None):
+if not name:
+name = str(uuid.uuid4())
+if self._vms.get(name) is None:
+self._vms[name] = self._new_vm(*args)
+return self._vms[name]
 
 def tearDown(self):
-if self.vm is not None:
-self.vm.shutdown()
+for vm in self._vms.values():
+vm.shutdown()
-- 
2.20.1

[Qemu-devel] [PULL 1/7] Acceptance tests: drop usage of ":avocado: enable"

2019-02-22 Thread Cleber Rosa

The Avocado test runner attemps to find its INSTRUMENTED (that is,
Python based tests) in a manner that is as safe as possible to the
user.  Different from plain Python unittest, it won't load or
execute test code on an operation such as:

 $ avocado list tests/acceptance/

Before version 68.0, the logic implemented to identify INSTRUMENTED
tests would require either the ":avocado: enable" or ":avocado:
recursive" statement as a flag for tests that would not inherit
directly from "avocado.Test".  This is not necessary anymore,
and because of that the boiler plate statements can now be removed.

Reference: 
https://avocado-framework.readthedocs.io/en/68.0/release_notes/68_0.html#users-test-writers
Signed-off-by: Cleber Rosa 
Reviewed-by: Caio Carrara 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Wainer dos Santos Moschetta 
Message-Id: <20190218173723.26120-1-cr...@redhat.com>
Signed-off-by: Cleber Rosa 
---
 docs/devel/testing.rst | 1 -
 tests/acceptance/boot_linux_console.py | 1 -
 tests/acceptance/linux_initrd.py   | 1 -
 tests/acceptance/version.py| 1 -
 tests/acceptance/virtio_version.py | 1 -
 tests/acceptance/vnc.py| 1 -
 tests/requirements.txt | 2 +-
 7 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst
index 135743a2bf..3ce171829d 100644
--- a/docs/devel/testing.rst
+++ b/docs/devel/testing.rst
@@ -600,7 +600,6 @@ the ``avocado_qemu.Test`` class.  Here's a simple usage 
example:
 
   class Version(Test):
   """
-  :avocado: enable
   :avocado: tags=quick
   """
   def test_qmp_human_info_version(self):
diff --git a/tests/acceptance/boot_linux_console.py 
b/tests/acceptance/boot_linux_console.py
index 98324f7591..beeb1e59e8 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -18,7 +18,6 @@ class BootLinuxConsole(Test):
 Boots a x86_64 Linux kernel and checks that the console is operational
 and the kernel command line is properly passed from QEMU to the kernel
 
-:avocado: enable
 :avocado: tags=x86_64
 """
 
diff --git a/tests/acceptance/linux_initrd.py b/tests/acceptance/linux_initrd.py
index 737355c2ef..5a15fc4347 100644
--- a/tests/acceptance/linux_initrd.py
+++ b/tests/acceptance/linux_initrd.py
@@ -18,7 +18,6 @@ class LinuxInitrd(Test):
 """
 Checks QEMU evaluates correctly the initrd file passed as -initrd option.
 
-:avocado: enable
 :avocado: tags=x86_64
 """
 
diff --git a/tests/acceptance/version.py b/tests/acceptance/version.py
index 13b0a7440d..67c2192c93 100644
--- a/tests/acceptance/version.py
+++ b/tests/acceptance/version.py
@@ -14,7 +14,6 @@ from avocado_qemu import Test
 
 class Version(Test):
 """
-:avocado: enable
 :avocado: tags=quick
 """
 def test_qmp_human_info_version(self):
diff --git a/tests/acceptance/virtio_version.py 
b/tests/acceptance/virtio_version.py
index ce990250d8..464d75aa4e 100644
--- a/tests/acceptance/virtio_version.py
+++ b/tests/acceptance/virtio_version.py
@@ -61,7 +61,6 @@ class VirtioVersionCheck(Test):
 same device tree created by `disable-modern` and
 `disable-legacy`.
 
-:avocado: enable
 :avocado: tags=x86_64
 """
 
diff --git a/tests/acceptance/vnc.py b/tests/acceptance/vnc.py
index b1ef9d71b1..064ceabcc1 100644
--- a/tests/acceptance/vnc.py
+++ b/tests/acceptance/vnc.py
@@ -13,7 +13,6 @@ from avocado_qemu import Test
 
 class Vnc(Test):
 """
-:avocado: enable
 :avocado: tags=vnc,quick
 """
 def test_no_vnc(self):
diff --git a/tests/requirements.txt b/tests/requirements.txt
index 64c6e27a94..002ded6a22 100644
--- a/tests/requirements.txt
+++ b/tests/requirements.txt
@@ -1,4 +1,4 @@
 # Add Python module requirements, one per line, to be installed
 # in the tests/venv Python virtual environment. For more info,
 # refer to: https://pip.pypa.io/en/stable/user_guide/#id1
-avocado-framework==65.0
+avocado-framework==68.0
-- 
2.20.1

Re: [Qemu-devel] [Bug 1813165] Re: KVM internal error. Suberror: 1 emulation failure

2019-02-22 Thread Bruce Rogers

>>> On 2/22/2019 at 9:50 AM, Vitaly Kuznetsov <1813...@bugs.launchpad.net> 
>>> wrote:
> I sent a patch which is supposed to fix the issue:
> https://marc.info/?l=kvm=155085391830663=2 
> 
> it would be great if someone could give it a spin!
> 

I've been trying to get down to the bottom of this.
It looks like you've got it.
I can confirm that this fixes the issue for me. Thanks!

Tested-by: Bruce Rogers 


> -- 
> You received this bug notification because you are a member of qemu-
> devel-ml, which is subscribed to QEMU.
> https://bugs.launchpad.net/bugs/1813165 
> 
> Title:
>   KVM internal error. Suberror: 1 emulation failure
> 
> Status in QEMU:
>   New
> 
> Bug description:
>   Hello Devs.
> 
>   Having problems getting VM to run with qemu 3.1.0. I should mention
>   it's a nested configuration.
> 
>   2019-01-24 13:46:08.648+: starting up libvirt version: 4.10.0, qemu 
> version: 3.1.0, kernel: 4.14.94, hostname: one
>   LC_ALL=C 
> PATH=/bin:/sbin:/bin:/sbin:/usr/bin:/usr/sbin:/usr/bin:/usr/sbin:/usr/local/b
> in:/usr/local/sbin:/opt/bin HOME=/root USER=root QEMU_AUDIO_DRV=none 
> /usr/bin/kvm -name guest=one-266,debug-threads=on -S -object 
> secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-1-one-266/m
> aster-key.aes -machine pc-i440fx-2.9,accel=kvm,usb=off,dump-guest-core=off 
> -cpu 
> Skylake-Client-IBRS,ss=on,hypervisor=on,tsc_adjust=on,clflushopt=on,ssbd=on,x
> saves=on,pdpe1gb=on -m 1024 -realtime mlock=off -smp 
> 2,sockets=2,cores=1,threads=1 -uuid b219b45d-a2f0-4128-a948-8673a7abf968 
> -no-user-config -nodefaults -chardev 
> socket,id=charmonitor,fd=21,server,nowait -mon 
> chardev=charmonitor,id=monitor,mode=control -rtc base=utc -no-shutdown -boot 
> strict=on -device piix3-usb-uhci,id=usb,bus=pci.0,addr=0x1.0x2 -drive 
> file=/var/lib/one//datastores/0/266/disk.0,format=qcow2,if=none,id=drive-virt
> io-disk0,cache=none -device 
> virtio-blk-pci,scsi=off,bus=pci.0,addr=0x4,drive=drive-virtio-disk0,id=virtio
> -disk0,bootindex=1,write-cache=on -drive 
> file=/var/lib/one//datastores/0/266/disk.1,format=raw,if=none,id=drive-ide0-0
> -0,readonly=on -device 
> ide-cd,bus=ide.0,unit=0,drive=drive-ide0-0-0,id=ide0-0-0 -netdev 
> tap,fd=23,id=hostnet0 -device 
> rtl8139,netdev=hostnet0,id=net0,mac=02:00:00:76:69:85,bus=pci.0,addr=0x3 
> -chardev pty,id=charserial0 -device isa-serial,chardev=charserial0,id=serial0 
> -vnc 0.0.0.0:266 -device cirrus-vga,id=video0,bus=pci.0,addr=0x2 -device 
> virtio-balloon-pci,id=balloon0,bus=pci.0,addr=0x5 -sandbox 
> on,obsolete=deny,elevateprivileges=deny,spawn=deny,resourcecontrol=deny -msg 
> timestamp=on
>   char device redirected to /dev/pts/1 (label charserial0)
>   KVM internal error. Suberror: 1
>   emulation failure
>   EAX=0001 EBX=000f7c2c ECX=0001 EDX=0001
>   ESI=6a26 EDI=3ffbdc48 EBP=69e6 ESP=000a8000
>   EIP=000fd057 EFL=00010016 [AP-] CPL=0 II=0 A20=1 SMM=1 HLT=0
>   ES =0010   00c09300
>   CS =  0fff 00809b00
>   SS =0010   00c09300
>   DS =0010   00c09300
>   FS =0010   00c09300
>   GS =0010   00c09300
>   LDT=   8200
>   TR =   8b00
>   GDT= 10387cfe fe6c
>   IDT= 0010387c 3810
>   CR0=0010 CR2= CR3= CR4=
>   DR0= DR1= DR2= 
> DR3=
>   DR6=fffecffc DR7=0e1e0400
>   EFER=
>   Code=cb 66 ba 4d d0 0f 00 e9 c8 fe bc 00 80 0a 00 e8 31 3a ff ff <0f> aa fa 
> fc 66 ba 66 d0 0f 00 e9 b1 fe f3 90 f0 0f ba 2d ac 3b 0f 00 00 72 f3 8b 25 a8 
> 3b
>   2019-01-24T13:47:39.383366Z kvm: terminating on signal 15 from pid 2708 
> (/usr/sbin/libvirtd)
> 
>   Someone has an idea whats going wrong here?
> 
>   thanks and cheers
>   t.
> 
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/qemu/+bug/1813165/+subscriptions

[Qemu-devel] [PATCH v3 6/8] qemu-doc: Add section on MIPS' Boston board

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Add section on MIPS' Boston board in QEMU user documentation.

Signed-off-by: Aleksandar Markovic 
---
 qemu-doc.texi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/qemu-doc.texi b/qemu-doc.texi
index 18e383c..ae3c3f9 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -2049,6 +2049,15 @@ Malta FPGA serial device
 Cirrus (default) or any other PCI VGA graphics card
 @end itemize
 
+The Boston board emulation supports the following devices:
+
+@itemize @minus
+@item
+Xilinx FPGA, which includes a PCIe root port and an UART
+@item
+Intel EG20T PCH connects the I/O peripherals, but only the SATA bus is emulated
+@end itemize
+
 The ACER Pica emulation supports:
 
 @itemize @minus
-- 
2.7.4

[Qemu-devel] [PATCH v3 3/8] disas: nanoMIPS: Fix a function misnomer

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Rename function extract_ac_13_12() to extract_ac_15_14().

Signed-off-by: Aleksandar Markovic 
---
 disas/nanomips.cpp | 96 +++---
 disas/nanomips.h   |  2 +-
 2 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index 08abfc9..10f6d96 100644
--- a/disas/nanomips.cpp
+++ b/disas/nanomips.cpp
@@ -1058,7 +1058,7 @@ uint64 NMD::extract_stripe_6(uint64 instruction)
 }
 
 
-uint64 NMD::extract_ac_13_12(uint64 instruction)
+uint64 NMD::extract_ac_15_14(uint64 instruction)
 {
 uint64 value = 0;
 value |= extract_bits(instruction, 14, 2);
@@ -6375,7 +6375,7 @@ std::string NMD::DPA_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6399,7 +6399,7 @@ std::string NMD::DPAQ_SA_L_W(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6423,7 +6423,7 @@ std::string NMD::DPAQ_S_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6447,7 +6447,7 @@ std::string NMD::DPAQX_SA_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6471,7 +6471,7 @@ std::string NMD::DPAQX_S_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6495,7 +6495,7 @@ std::string NMD::DPAU_H_QBL(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6519,7 +6519,7 @@ std::string NMD::DPAU_H_QBR(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6543,7 +6543,7 @@ std::string NMD::DPAX_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6567,7 +6567,7 @@ std::string NMD::DPS_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6591,7 +6591,7 @@ std::string NMD::DPSQ_SA_L_W(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs = GPR(copy(rs_value));
@@ -6615,7 +6615,7 @@ std::string NMD::DPSQ_S_W_PH(uint64 instruction)
 {
 uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
 uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
-uint64 ac_value = extract_ac_13_12(instruction);
+uint64 ac_value = extract_ac_15_14(instruction);
 
 std::string ac = AC(copy(ac_value));
 std::string rs =

[Qemu-devel] [PATCH v3 7/8] tests/tcg: target/mips: Add wrappers for MSA integer max/min instructions

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Add wrappers for MSA integer max/min instructions.

Signed-off-by: Aleksandar Markovic 
---
 tests/tcg/mips/include/wrappers_msa.h | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/tests/tcg/mips/include/wrappers_msa.h 
b/tests/tcg/mips/include/wrappers_msa.h
index 3280f9b..302f0ab 100644
--- a/tests/tcg/mips/include/wrappers_msa.h
+++ b/tests/tcg/mips/include/wrappers_msa.h
@@ -122,5 +122,35 @@ DO_MSA__WD__WS_WT(CLT_U_H, clt_u.h)
 DO_MSA__WD__WS_WT(CLT_U_W, clt_u.w)
 DO_MSA__WD__WS_WT(CLT_U_D, clt_u.d)
 
+DO_MSA__WD__WS_WT(MAX_A_B, max_a.b)
+DO_MSA__WD__WS_WT(MAX_A_H, max_a.h)
+DO_MSA__WD__WS_WT(MAX_A_W, max_a.w)
+DO_MSA__WD__WS_WT(MAX_A_D, max_a.d)
+
+DO_MSA__WD__WS_WT(MIN_A_B, min_a.b)
+DO_MSA__WD__WS_WT(MIN_A_H, min_a.h)
+DO_MSA__WD__WS_WT(MIN_A_W, min_a.w)
+DO_MSA__WD__WS_WT(MIN_A_D, min_a.d)
+
+DO_MSA__WD__WS_WT(MAX_S_B, max_s.b)
+DO_MSA__WD__WS_WT(MAX_S_H, max_s.h)
+DO_MSA__WD__WS_WT(MAX_S_W, max_s.w)
+DO_MSA__WD__WS_WT(MAX_S_D, max_s.d)
+
+DO_MSA__WD__WS_WT(MIN_S_B, min_s.b)
+DO_MSA__WD__WS_WT(MIN_S_H, min_s.h)
+DO_MSA__WD__WS_WT(MIN_S_W, min_s.w)
+DO_MSA__WD__WS_WT(MIN_S_D, min_s.d)
+
+DO_MSA__WD__WS_WT(MAX_U_B, max_u.b)
+DO_MSA__WD__WS_WT(MAX_U_H, max_u.h)
+DO_MSA__WD__WS_WT(MAX_U_W, max_u.w)
+DO_MSA__WD__WS_WT(MAX_U_D, max_u.d)
+
+DO_MSA__WD__WS_WT(MIN_U_B, min_u.b)
+DO_MSA__WD__WS_WT(MIN_U_H, min_u.h)
+DO_MSA__WD__WS_WT(MIN_U_W, min_u.w)
+DO_MSA__WD__WS_WT(MIN_U_D, min_u.d)
+
 
 #endif
-- 
2.7.4

[Qemu-devel] [PATCH v3 5/8] qemu-doc: Add section on MIPS' Fulong 2E board

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Add section on MIPS' Fulong 2E board in QEMU user documentation.

Signed-off-by: Aleksandar Markovic 
---
 qemu-doc.texi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/qemu-doc.texi b/qemu-doc.texi
index 4c5577f..18e383c 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -2077,6 +2077,19 @@ SCSI controller
 G364 framebuffer
 @end itemize
 
+The Fulong 2E emulation supports:
+
+@itemize @minus
+@item
+Loongson 2E CPU
+@item
+Bonito64 system controller as North Bridge
+@item
+VT82C686 chipset as South Bridge
+@item
+RTL8139D as a network card chipset
+@end itemize
+
 The mipssim pseudo board emulation provides an environment similar
 to what the proprietary MIPS emulator uses for running Linux.
 It supports:
-- 
2.7.4

[Qemu-devel] [PATCH v3 2/8] disas: nanoMIPS: Correct comments to handlers of some DSP instructions

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Correct comments to handlers of some DSP instructions.

Signed-off-by: Aleksandar Markovic 
---
 disas/nanomips.cpp | 285 -
 1 file changed, 150 insertions(+), 135 deletions(-)

diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index f90f1a9..08abfc9 100644
--- a/disas/nanomips.cpp
+++ b/disas/nanomips.cpp
@@ -10183,14 +10183,13 @@ std::string NMD::MFHGC0(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MFHI rs, ac - Move from HI register
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   x111101
+ *  001000 x  000111
  * rt -
- *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MFHI_DSP_(uint64 instruction)
 {
@@ -10231,14 +10230,13 @@ std::string NMD::MFHTR(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MFLO rs, ac - Move from HI register
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   x111101
+ *  001000 x  010111
  * rt -
- *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MFLO_DSP_(uint64 instruction)
 {
@@ -10399,7 +10397,7 @@ std::string NMD::MOD(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
  *
  *   3 2 1
  *  10987654321098765432109876543210
@@ -10427,7 +10425,7 @@ std::string NMD::MODSUB(uint64 instruction)
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   x111101
+ *  001000   x1010010101
  * rt -
  *  rs -
  *   rd -
@@ -10639,14 +10637,14 @@ std::string NMD::MOVZ(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
+ *  0010001010101011
  * rt -
  *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MSUB_DSP_(uint64 instruction)
 {
@@ -10711,14 +10709,14 @@ std::string NMD::MSUBF_S(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
+ *  0010001110101011
  * rt -
  *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MSUBU_DSP_(uint64 instruction)
 {
@@ -10919,14 +10917,13 @@ std::string NMD::MTHGC0(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MTHI rs, ac - Move to HI register
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
- * rt -
+ *  001000x   100111
  *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MTHI_DSP_(uint64 instruction)
 {
@@ -10941,14 +10938,13 @@ std::string NMD::MTHI_DSP_(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
- * rt -
+ *  001000x   100111
  *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MTHLIP(uint64 instruction)
 {
@@ -10989,14 +10985,13 @@ std::string NMD::MTHTR(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MTLO rs, ac - Move to LO register
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
- * rt -
+ *  001000x   110111
  *  rs -
- *   rd -
+ *   ac --
  */
 std::string NMD::MTLO_DSP_(uint64 instruction)
 {
@@ -11155,11 +11150,12 @@ std::string NMD::MUL_D(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
+ *   products
  *
  *   3 2 1
  *  10987654321098765432109876543210
- *  001000   00010001101
+ *  001000   0101101
  * rt -
  *  rs -
  *   rd -
@@ -11179,11 +11175,12 @@ std::string NMD::MUL_PH(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
+ *

[Qemu-devel] [PATCH v3 0/8] Misc target/mips fixes and improvements

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

A collection of misc target/mips fixes and improvements for
February 2019.

v2->v3:

  - added a patches on documenting Boston board
  - added two patches on testing integer max/min MSA instructions
  - removed four patches that had been accepted
  - amended patch on DSP-related comments

v1->v2:

  - added two patches on updating end user documentation
  - minor updates to commit messages

Aleksandar Markovic (8):
  tests/tcg: target/mips: Add tests for MSA integer compare instructions
  disas: nanoMIPS: Correct comments to handlers of some DSP instructions
  disas: nanoMIPS: Fix a function misnomer
  qemu-doc: Move section on MIPS' mipssim pseudo board
  qemu-doc: Add section on MIPS' Fulong 2E board
  qemu-doc: Add section on MIPS' Boston board
  tests/tcg: target/mips: Add wrappers for MSA integer max/min
instructions
  tests/tcg: target/mips: Add tests for MSA integer max/min instructions

 disas/nanomips.cpp | 381 +++--
 disas/nanomips.h   |   2 +-
 qemu-doc.texi  |  46 ++-
 tests/tcg/mips/include/wrappers_msa.h  |  30 ++
 .../mips/user/ase/msa/int-compare/test_msa_ceq_b.c | 153 +
 .../mips/user/ase/msa/int-compare/test_msa_ceq_d.c | 153 +
 .../mips/user/ase/msa/int-compare/test_msa_ceq_h.c | 153 +
 .../mips/user/ase/msa/int-compare/test_msa_ceq_w.c | 153 +
 .../user/ase/msa/int-compare/test_msa_cle_s_b.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_s_d.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_s_h.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_s_w.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_u_b.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_u_d.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_u_h.c| 153 +
 .../user/ase/msa/int-compare/test_msa_cle_u_w.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_s_b.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_s_d.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_s_h.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_s_w.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_u_b.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_u_d.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_u_h.c| 153 +
 .../user/ase/msa/int-compare/test_msa_clt_u_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_a_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_a_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_a_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_a_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_s_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_s_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_s_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_s_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_u_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_u_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_u_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_max_u_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_a_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_a_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_a_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_a_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_s_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_s_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_s_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_s_w.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_u_b.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_u_d.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_u_h.c| 153 +
 .../user/ase/msa/int-max-min/test_msa_min_u_w.c| 153 +
 48 files changed, 6995 insertions(+), 196 deletions(-)
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_ceq_b.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_ceq_d.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_ceq_h.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_ceq_w.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_cle_s_b.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_cle_s_d.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_cle_s_h.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_cle_s_w.c
 create mode 100644 tests/tcg/mips/user/ase/msa/int-compare/test_msa_cle_u_b.c
 create mode 100644

[Qemu-devel] [PATCH v3 4/8] qemu-doc: Move section on MIPS' mipssim pseudo board

2019-02-22 Thread Aleksandar Markovic

From: Aleksandar Markovic 

Move section on MIPS' mipssim pseudo board to the more
appropriate place.

Signed-off-by: Aleksandar Markovic 
---
 qemu-doc.texi | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/qemu-doc.texi b/qemu-doc.texi
index 83be010..4c5577f 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -2062,19 +2062,6 @@ PC Keyboard
 IDE controller
 @end itemize
 
-The mipssim pseudo board emulation provides an environment similar
-to what the proprietary MIPS emulator uses for running Linux.
-It supports:
-
-@itemize @minus
-@item
-A range of MIPS CPUs, default is the 24Kf
-@item
-PC style serial port
-@item
-MIPSnet network emulation
-@end itemize
-
 The MIPS Magnum R4000 emulation supports:
 
 @itemize @minus
@@ -2090,6 +2077,19 @@ SCSI controller
 G364 framebuffer
 @end itemize
 
+The mipssim pseudo board emulation provides an environment similar
+to what the proprietary MIPS emulator uses for running Linux.
+It supports:
+
+@itemize @minus
+@item
+A range of MIPS CPUs, default is the 24Kf
+@item
+PC style serial port
+@item
+MIPSnet network emulation
+@end itemize
+
 @node nanoMIPS System emulator
 @subsection nanoMIPS System emulator
 @cindex system emulation (nanoMIPS)
-- 
2.7.4

Re: [Qemu-devel] [PATCH 2/2] qcow2: mark image as corrupt if failing during create

2019-02-22 Thread Max Reitz

On 19.02.19 13:50, Daniel P. Berrangé wrote:
> During creation we write a minimal qcow2 header and then update it with
> extra features. If the updating fails for some reason we might still be
> left with a valid qcow2 image that will be mistakenly used for I/O. We
> cannot delete the image, since we don't know if we created the
> underlying storage or not. Thus we mark the header as corrupt to
> prevents its later usage.
> 
> Signed-off-by: Daniel P. Berrangé 
> ---
>  block/qcow2.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/block/qcow2.c b/block/qcow2.c
> index ecc577175f..338513e652 100644
> --- a/block/qcow2.c
> +++ b/block/qcow2.c
> @@ -3104,6 +3104,9 @@ qcow2_co_create(BlockdevCreateOptions *create_options, 
> Error **errp)
>  
>  ret = 0;
>  out:
> +if (ret < 0) {
> +qcow2_mark_corrupt(blk_bs(blk));

First, blk_bs(blk) may be the qcow2 BDS, or it may the protocol BDS here
(it is the latter before the first blk_new_open() call).  Calling
qcow2_mark_corrupt() unconditionally may mean an invalid access to
bs->opaque (which is not going to be of type BDRVQcow2State if the BDS
is not a qcow2 BDS).

Second, blk may be NULL (at various points, e.g. after blk_new_open()
failed).  Then this would yield a segfault in in blk_bs().

Third, blk_bs(blk) may be NULL (if blk_insert_bs() failed).  Then this
would yield a segfault in qcow2_mark_corrupt().

On a minor note, it is rather probably that blk_new_open() fails.  In
that case, there is currently no way to mark the image corrupt.  Would
it be useful and possible to have a function to mark a qcow2 image
corrupt without relying on qcow2 features, i.e. by writing directly to
the protocol layer (which is always @bs)?  This would be unsafe to use
as long as the protocol layer is opened by the qcow2 driver in some
other node, but we could invoke this function safely after @blk has been
freed.

Or maybe Eric's suggestion really is for the best, i.e. mark the image
corrupt from the start and then clean that after we're all done.  You
don't need a new flag for that, we already have BDRV_O_CHECK.

Max

> +}
>  blk_unref(blk);
>  bdrv_unref(bs);
>  return ret;
> 

signature.asc
Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH v2 5/7] ui/cocoa: Don't call NSApp sendEvent directly from handleEvent

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:14AM +, Peter Maydell wrote:
> Currently the handleEvent method will directly call the NSApp
> sendEvent method for any events that we want to let OSX deal
> with. When we rearrange the event handling code, the way that
> we say "let OSX have this event" is going to change. Prepare
> for that by refactoring so that handleEvent returns a flag
> indicating whether it consumed the event.
> 
> Suggested-by: BALATON Zoltan 
> Signed-off-by: Peter Maydell 
> ---
> New patch in v2
> ---
>  ui/cocoa.m | 49 ++---
>  1 file changed, 34 insertions(+), 15 deletions(-)
> 
> @@ -1749,7 +1766,9 @@ static void cocoa_refresh(DisplayChangeListener *dcl)
>  event = [NSApp nextEventMatchingMask:NSEventMaskAny 
> untilDate:distantPast
>  inMode: NSDefaultRunLoopMode dequeue:YES];
>  if (event != nil) {
> -[cocoaView handleEvent:event];
> +if (![cocoaView handleEvent:event]) {
> +[NSApp sendEvent:event];
> +}
>  }
>  } while(event != nil);
>  [pool release];
> -- 
> 2.17.2 (Apple Git-113)
> 

I like the patch. It makes clear that cocoa_refresh performs the work
of [NSApp run].

Besides the trailing whitespace issue,

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Thanks,
Roman

Re: [Qemu-devel] [PATCH 1/2] qcow2: fail if encryption opts are provided to non-encrypted image

2019-02-22 Thread Max Reitz

On 19.02.19 13:50, Daniel P. Berrangé wrote:
> If the qcow2 image does not have any encryption method specified in its
> header, the user should not be providing any encryption options when
> opening it. We already detect this if the user had set "encrypt.format"
> but this field is optional so must consider any "encrypt.*" option to be
> an error.
> 
> Signed-off-by: Daniel P. Berrangé 
> ---
>  block/qcow2.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/block/qcow2.c b/block/qcow2.c
> index 65a54c9ac6..ecc577175f 100644
> --- a/block/qcow2.c
> +++ b/block/qcow2.c
> @@ -1045,6 +1045,12 @@ static int 
> qcow2_update_options_prepare(BlockDriverState *bs,
>  ret = -EINVAL;
>  goto fail;
>  }
> +if (encryptopts && qdict_size(encryptopts)) {
> +error_setg(errp, "No encryption in image header, but encryption "
> +   "options provided");
> +ret = -EINVAL;
> +goto fail;
> +}

Doesn't this make the block right before this one a bit superfluous?

Max

>  break;
>  
>  case QCOW_CRYPT_AES:
> 




signature.asc
Description: OpenPGP digital signature

Re: [Qemu-devel] [RFC PATCH 0/4] ARM virt: ACPI memory hotplug support

2019-02-22 Thread Laszlo Ersek

On 02/22/19 17:03, Auger Eric wrote:
> Hi Shameer,
> 
> On 1/28/19 12:05 PM, Shameer Kolothum wrote:
>> This series is an attempt to provide hotplug support to both
>> pc-dimm and nvdimm device memory on ARM virt platform. This is
>> based on Eric's recent works to support PCDIMM/NVDIMM device memory[1].
>> The kernel support for arm64 memory hot add was added only
>> recently by Robin[2] and hence the guest kernel should be => 5.0-rc1.
>>
>> This makes use of PL061 GPIO controller to sent related ACPI events
> s/sent/send
>> to the Guest. The only reference I could find with respect to the GPIO
>> pins usage is here[3] which says, "use PIN 3 for system_powerdown,
>> reserving PIN 0, 1, 2 for PCI hotplug, CPU hotplug and memory hotplug".
>> Hence Pin 2 is used for PCDIMM and pin 4 for NVDIMM.
>>
>> This is sanity tested on a HiSilicon ARM64 platform and appreciate
>> any further testing.
> 
> I did some testing on another platform and I got the exactly the same
> results as yours: PCDIMM hot plug works fine. Also after system_reset I
> still can see the slots.
> Hot-unplug is not supported though.
> For NVDIMM, hot-add works fine and and I can see the slots using ndctl
> on guest. But after system_reset, the guest does not boot properly.
> 
>>
>> This series can be applied on top of Eric's branch here[4]
>>
>> Test:
>> --
>> Please use a Guest kernel image >5.0-rc1 with all the mem/nvdimm
>> hotplug related CONFIGs enabled.
>>
>> ./qemu-system-aarch64 \
>> -machine virt,gic-version=3,nvdimm \
>> -m 1G,maxmem=4G,slots=4 \
>> -cpu host \
>> -kernel Image \
>> -initrd rootfs-iperf.cpio \
>> -bios QEMU_EFI.fd \
>> -numa node,nodeid=0 \
>> -net none \
>> -nographic -enable-kvm \
>> -append "console=ttyAMA0 acpi=force earlycon=pl011,0x900"
>>
>> Enter Qemu monitor,
>> Add pc-dimm:
>> object_add memory-backend-ram,id=mem1,size=1G
>> device_add pc-dimm,id=dimm1,memdev=mem1
>>
>> Add nvdimm:
>> object_add memory-backend-ram,id=mem2,size=1G
>> device_add nvdimm,id=dimm2,memdev=mem2
>>
>> Known Issue:
>>
>> It is observed that hot adding nvdimm will results in guest reboot
>> failure. EDK2 fails to build the ACPI tables on reboot. Please find
>> below EDK2 log on Guest reboot after nvdimm hot-add,
>>
>> ProcessCmdAddChecksum: invalid checksum range in "etc/acpi/tables"
>> OnRootBridgesConnected: InstallAcpiTables: Protocol Error
>>
>> The root cause seems to be EDK2 ACPI table checksum failure
>> as NFIT table is getting updated on hot-add. This needs further
>> investigation.
> + Ard, Leif, Laszlo if they have any idea of what is missing/wrong.

Huh, very interesting; I usually don't expect my sanity checks to fire
in practice. :)

The message

  ProcessCmdAddChecksum: invalid checksum range in "etc/acpi/tables"

is logged by OVMF's and ArmVirtQemu's ACPI Platform DXE Driver when it
finds an invalid COMMAND_ADD_CHECKSUM command in QEMU's ACPI
linker/loader script.

Please see the command definition in QEMU's
"hw/acpi/bios-linker-loader.c". In particular, please refer to the
function bios_linker_loader_add_checksum(), which builds the command
structure, and documents the fields.

(You may also refer to QEMU_LOADER_ADD_CHECKSUM in file
"OvmfPkg/AcpiPlatformDxe/QemuLoader.h" in the edk2 source tree, for the
same information.)

The error message is logged if:
- the offset at which the checksum should be stored falls outside of the
size of the fw_cfg blob, or
- the range over which the checksum should be calculated falls outside
(at least in part) of the fw_cfg blob.

To me this suggests that QEMU generates an invalid COMMAND_ADD_CHECKSUM
command for the firmware.

... I've tried to skim the patches briefly. I think there must be an
error in the DSDT building logic that is only active on reboot if an
nvdimm module was hot-added before the reboot.

Thanks,
Laszlo


>> [1]https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg05740.html
>> [2]https://patchwork.kernel.org/patch/10724455/
>> [3]https://lists.gnu.org/archive/html/qemu-arm/2015-12/msg00095.html
>> [4]https://github.com/eauger/qemu/tree/v3.1.0-dimm-v5
>>
>> Shameer Kolothum (4):
>>   hw:acpi: Make ACPI IO address space configurable
>>   hw/arm/virt: Add GPIO based pcdimm hotplug ACPI event support
>>   hw/arm/virt: Enable pc-dimm hotplug support
>>   hw/arm/virt: Add nvdimm hotplug support
>>
>>  default-configs/arm-softmmu.mak  |   1 +
>>  hw/acpi/memory_hotplug.c |  13 +++--
>>  hw/arm/virt-acpi-build.c |  45 +++--
>>  hw/arm/virt.c| 105 
>> ---
>>  hw/i386/acpi-build.c |   3 +-
>>  include/hw/acpi/memory_hotplug.h |   6 ++-
>>  include/hw/arm/virt.h|  15 ++
>>  7 files changed, 168 insertions(+), 20 deletions(-)
>>

Re: [Qemu-devel] [PATCH v4] hw/block: better reporting on pflash backing file mismatch

2019-02-22 Thread Laszlo Ersek

Two trivial comments:

On 02/22/19 16:44, Alex Bennée wrote:
> It looks like there was going to be code to check we had some sort of
> alignment so lets replace it with an actual check. This is a bit more
> useful than the enigmatic "failed to read the initial flash content"
> when we attempt to read the number of bytes the device should have.
> 
> This is a potential confusing stumbling block when you move from using
> -bios to using -drive if=pflash,file=blob,format=raw,readonly for
> loading your firmware code. To mitigate that we automatically pad in
> the read-only case and warn the user when we have performed magic to
> enable things to Just Work (tm).
> 
> Signed-off-by: Alex Bennée 
> 
> ---
> v3
>   - tweak commit title/commentary
>   - use total_len instead of device_len for checks
>   - if the device is read-only do the padding for them
>   - accept baking_len > total_len (how to warn_report with NULL *errp?)
> v4
>   - error check blk_getlength
>   - optimise memset and use NOR erase pattern
>   - restore singular device (overly confusing)
>   - add warn_report for when we do magic
> ---
>  hw/block/pflash_cfi01.c | 40 +---
>  1 file changed, 33 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
> index 00c2efd0d7..c69ecc20a0 100644
> --- a/hw/block/pflash_cfi01.c
> +++ b/hw/block/pflash_cfi01.c
> @@ -45,6 +45,7 @@
>  #include "qemu/bitops.h"
>  #include "qemu/host-utils.h"
>  #include "qemu/log.h"
> +#include "qemu/error-report.h"
>  #include "hw/sysbus.h"
>  #include "sysemu/sysemu.h"
>  #include "trace.h"
> @@ -714,13 +715,6 @@ static void pflash_cfi01_realize(DeviceState *dev, Error 
> **errp)
>  }
>  device_len = sector_len_per_device * blocks_per_device;
>  
> -/* XXX: to be fixed */
> -#if 0
> -if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
> -total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
> -return NULL;
> -#endif
> -
>  memory_region_init_rom_device(
>  >mem, OBJECT(dev),
>  _cfi01_ops,
> @@ -747,6 +741,38 @@ static void pflash_cfi01_realize(DeviceState *dev, Error 
> **errp)
>  }
>  
>  if (pfl->blk) {
> +/*
> + * Validate the backing store is the right size for pflash
> + * devices. It should be padded to a multiple of the flash
> + * block size. If the device is read-only we can elide the
> + * check and just null pad the region first. If the user

(1) We no longer null-pad, but one-pad (bit-wise). I don't think it's
too confusing though.

> + * supplies a larger file we ignore the tail.
> + */
> +int64_t backing_len = blk_getlength(pfl->blk);
> +if (backing_len < 0) {
> +error_setg(errp, "unable to check size of backing file");
> +return;
> +}
> +
> +if (backing_len < total_len) {
> +if (pfl->ro) {
> +size_t pad_bytes = total_len - backing_len;
> +/* pad with NOR erase pattern */
> +memset((uint8_t*)pfl->storage + backing_len, 0xff, 
> pad_bytes);
> +warn_report("device needs %" PRIu64
> +" bytes, padded with %zd 0xff bytes",

(2) I think %zu would be more appropriate for size_t, but it's not a
showstopper.

> +total_len, pad_bytes);
> +total_len = backing_len;
> +} else {
> +error_setg(errp, "device needs %" PRIu64 " bytes, "
> +   "backing file provides only %" PRIu64 " bytes",
> +   total_len, backing_len);
> +return;
> +}
> +} else if (backing_len > total_len) {
> +warn_report("device needs %" PRIu64 " bytes, rest ignored", 
> total_len);
> +}
> +
>  /* read the initial flash content */
>  ret = blk_pread(pfl->blk, 0, pfl->storage, total_len);
>  
> 

No need to repost just because of these.

Reviewed-by: Laszlo Ersek 

Thanks!
Laszlo

Re: [Qemu-devel] [PATCH v2 4/7] ui/cocoa: Move console/device menu creation code up in file

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:13AM +, Peter Maydell wrote:
> Move the console/device menu creation code functions
> further up in the source file, next to the code which
> creates the initial menus. We're going to want to
> change the location we call these functions from in
> the next patch.
> 
> This commit is a pure code move with no other changes.
> 
> Signed-off-by: Peter Maydell 
> ---
>  ui/cocoa.m | 184 ++---
>  1 file changed, 92 insertions(+), 92 deletions(-)
> 

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Thanks,
Roman

Re: [Qemu-devel] [PATCH v2 14/25] hw/arm: Express dependencies of netduino / stm32f2xx with Kconfig

2019-02-22 Thread Alistair Francis

On Wed, Feb 13, 2019 at 1:11 AM Thomas Huth  wrote:
>
> Netduino only depends on the stm32f205 SoC which in turn depends on
> its components.
>
> Signed-off-by: Thomas Huth 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  default-configs/arm-softmmu.mak | 9 +
>  hw/arm/Kconfig  | 7 +++
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 9db6808..3279fb5 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -24,25 +24,18 @@ CONFIG_TOSA=y
>  CONFIG_Z2=y
>  CONFIG_COLLIE=y
>  CONFIG_ASPEED_SOC=y
> +CONFIG_NETDUINO2=y
>
>  CONFIG_VGA=y
>  CONFIG_SSI_M25P80=y
>  CONFIG_ALLWINNER_EMAC=y
>  CONFIG_IMX_FEC=y
>
> -CONFIG_NETDUINO2=y
> -
>  CONFIG_FRAMEBUFFER=y
>
>  CONFIG_DIGIC=y
>  CONFIG_MPS2=y
>  CONFIG_RASPI=y
> -CONFIG_STM32F2XX_TIMER=y
> -CONFIG_STM32F2XX_USART=y
> -CONFIG_STM32F2XX_SYSCFG=y
> -CONFIG_STM32F2XX_ADC=y
> -CONFIG_STM32F2XX_SPI=y
> -CONFIG_STM32F205_SOC=y
>  CONFIG_NRF51_SOC=y
>
>  CONFIG_CMSDK_APB_TIMER=y
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 3d580fa..5d7dafb 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -81,6 +81,7 @@ config MUSICPAL
>
>  config NETDUINO2
>  bool
> +select STM32F205_SOC
>
>  config NSERIES
>  bool
> @@ -262,6 +263,12 @@ config RASPI
>
>  config STM32F205_SOC
>  bool
> +select ARM_V7M
> +select STM32F2XX_TIMER
> +select STM32F2XX_USART
> +select STM32F2XX_SYSCFG
> +select STM32F2XX_ADC
> +select STM32F2XX_SPI
>
>  config XLNX_ZYNQMP_ARM
>  bool
> --
> 1.8.3.1
>
>

[Qemu-devel] [Bug 1815445] Re: change and eject commands are not working on an overlay

2019-02-22 Thread John Snow

Can you please provide your QEMU version, command line, and any QMP/HMP
commands you issued, and the expected/desired effect?

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1815445

Title:
  change and eject commands are not working on an overlay

Status in QEMU:
  New

Bug description:
  From qemu monitor, 'change' and 'eject' commands are not working on a CD 
overlay.
  'info block' returns:
cd0-overlay0: /home/guillaume/test/cd0-overlay0 (qcow2)
  Attached to:  cd0-device
  Removable device: not locked, tray closed
  Cache mode:   writeback, ignore flushes
  Backing file: /home/guillaume/test.iso (chain depth: 1)

  But 'eject cd0-overlay0' returns:
Device 'cd0-overlay0' not found
  I also tried 'cd0-device' and 'cd0'.

  Same problem with 'change' command.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1815445/+subscriptions

Re: [Qemu-devel] [PATCH v2 3/7] ui/cocoa: Factor out initial menu creation

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:12AM +, Peter Maydell wrote:
> Factor out the long code sequence in main() which creates
> the initial set of menus. This will make later patches
> which move initialization code around a bit clearer.
> 
> Signed-off-by: Peter Maydell 
> ---
>  ui/cocoa.m | 78 --
>  1 file changed, 41 insertions(+), 37 deletions(-)
> 

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

--
Roman

Re: [Qemu-devel] [PATCH 2/2] target/arm: Gate "miscellaneous FP" insns by ID register field

2019-02-22 Thread Peter Maydell

On Fri, 22 Feb 2019 at 17:09, Peter Maydell  wrote:
>
> There is a set of VFP instructions which we implement in
> disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
> These were all first introduced in v8 for A-profile, but in
> M-profile they appeared in v7M. Gate them on the MVFR2
> FPMisc field instead, and rename the function appropriately.

> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index b7702fb49f7..af8f9e669b8 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -3357,7 +3357,7 @@ static const uint8_t fp_decode_rm[] = {
>  FPROUNDING_NEGINF,
>  };
>
> -static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
> +static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
>  {
>  uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
>

Oops, I forgot to commit this part of the change:

@@ -3361,10 +3361,6 @@ static int disas_vfp_misc_insn(DisasContext *s,
uint32_t insn)
 {
 uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);

-if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
-return 1;
-}
-
 if (dp) {
 VFP_DREG_D(rd, insn);
 VFP_DREG_N(rn, insn);

thanks
-- PMM

Re: [Qemu-devel] [PATCH v7 00/17] ARM virt: Initial RAM expansion and PCDIMM/NVDIMM support

2019-02-22 Thread Auger Eric

Hi Igor,

On 2/22/19 5:27 PM, Igor Mammedov wrote:
> On Wed, 20 Feb 2019 23:39:46 +0100
> Eric Auger  wrote:
> 
>> This series aims to bump the 255GB RAM limit in machvirt and to
>> support device memory in general, and especially PCDIMM/NVDIMM.
>>
>> In machvirt versions < 4.0, the initial RAM starts at 1GB and can
>> grow up to 255GB. From 256GB onwards we find IO regions such as the
>> additional GICv3 RDIST region, high PCIe ECAM region and high PCIe
>> MMIO region. The address map was 1TB large. This corresponded to
>> the max IPA capacity KVM was able to manage.
>>
>> Since 4.20, the host kernel is able to support a larger and dynamic
>> IPA range. So the guest physical address can go beyond the 1TB. The
>> max GPA size depends on the host kernel configuration and physical CPUs.
>>
>> In this series we use this feature and allow the RAM to grow without
>> any other limit than the one put by the host kernel.
>>
>> The RAM still starts at 1GB. First comes the initial ram (-m) of size
>> ram_size and then comes the device memory (,maxmem) of size
>> maxram_size - ram_size. The device memory is potentially hotpluggable
>> depending on the instantiated memory objects.
>>
>> IO regions previously located between 256GB and 1TB are moved after
>> the RAM. Their offset is dynamically computed, depends on ram_size
>> and maxram_size. Size alignment is enforced.
>>
>> In case maxmem value is inferior to 255GB, the legacy memory map
>> still is used. The change of memory map becomes effective from 4.0
>> onwards.
>>
>> As we keep the initial RAM at 1GB base address, we do not need to do
>> invasive changes in the EDK2 FW. It seems nobody is eager to do
>> that job at the moment.
>>
>> Device memory being put just after the initial RAM, it is possible
>> to get access to this feature while keeping a 1TB address map.
>>
>> This series reuses/rebases patches initially submitted by Shameer
>> in [1] and Kwangwoo in [2] for the PC-DIMM and NV-DIMM parts.
>>
>> Functionally, the series is split into 3 parts:
>> 1) bump of the initial RAM limit [1 - 9] and change in
>>the memory map
> 
>> 2) Support of PC-DIMM [10 - 13]
> Is this part complete ACPI wise (for coldplug)? I haven't noticed
> DSDT AML here no E820 changes, so ACPI wise pc-dimm shouldn't be
> visible to the guest. It might be that DT is masking problem
> but well, that won't work on ACPI only guests.

guest /proc/meminfo or "lshw -class memory" reflects the amount of mem
added with the DIMM slots. So it looks fine to me. Isn't E820 a pure x86
matter? What else would you expect in the dsdt? I understand hotplug
would require extra modifications but I don't see anything else missing
for coldplug.
> Even though I've tried make mem hotplug ACPI parts not x86 specific,
> I'm afraid it might be tightly coupled with hotplug support.
> So here are 2 options make DSDT part work without hotplug or
> implement hotplug here. I think the former is just a waste of time
> and we should just add hotplug. It should take relatively minor effort
> since you already implemented most of boiler plate here.

Shameer sent an RFC series for supporting hotplug.

[RFC PATCH 0/4] ARM virt: ACPI memory hotplug support
https://patchwork.kernel.org/cover/10783589/

I tested PCDIMM hotplug (with ACPI) this afternoon and it seemed to be
OK, even after system_reset.

Note the hotplug kernel support on ARM is very recent. I would prefer to
dissociate both efforts if we want to get a chance making coldplug for
4.0. Also we have an issue for NVDIMM since on reboot the guest does not
boot properly.

> 
> As for how to implement ACPI HW part, I suggest to borrow GED
> device that NEMU guys trying to use instead of GPIO route,
> like we do now for ACPI_POWER_BUTTON_DEVICE to deliver event.
> So that it would be easier to share this with their virt-x86
> machine eventually.
Sounds like a different approach than the one initiated by Shameer?

Thanks

Eric
> 
> 
>> 3) Support of NV-DIMM [14 - 17]
> The same might be true for NUMA but I haven't dug this deep in to
> that part.
> 
>>
>> 1) can be upstreamed before 2 and 2 can be upstreamed before 3.
>>
>> Work is ongoing to transform the whole memory as device memory.
>> However this move is not trivial and to me, is independent on
>> the improvements brought by this series:
>> - if we were to use DIMM for initial RAM, those DIMMs would use
>>   use slots. Although they would not be part of the ones provided
>>   using the ",slots" options, they are ACPI limited resources.
>> - DT and ACPI description needs to be reworked
>> - NUMA integration needs special care
>> - a special device memory object may be required to avoid consuming
>>   slots and easing the FW description.
>>
>> So I preferred to separate the concerns. This new implementation
>> based on device memory could be candidate for another virt
>> version.
>>
>> Best Regards
>>
>> Eric
>>
>> References:
>>
>> [0] [RFC v2 0/6] hw/arm: Add support for non-contiguous iova regions
>>

Re: [Qemu-devel] [PULL 0/2] vfio updates 2019-02-21

2019-02-22 Thread Peter Maydell

On Fri, 22 Feb 2019 at 05:35, Alex Williamson
 wrote:
>
> The following changes since commit fc3dbb90f2eb069801bfb4cfe9cbc83cf9c5f4a9:
>
>   Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' 
> into staging (2019-02-21 13:09:33 +)
>
> are available in the Git repository at:
>
>   git://github.com/awilliam/qemu-vfio.git tags/vfio-updates-20190221.0
>
> for you to fetch changes up to 2b6326c0bf2c686ae83d6904899cb80e9ad7a6fb:
>
>   hw/vfio/common: Refactor container initialization (2019-02-21 21:07:03 
> -0700)
>
> 
> VFIO updates 2019-02-21
>
>  - Workaround kernel overflow bug in vfio type1 DMA unmap
>(Alex Williamson)
>
>  - Refactor vfio container initialization (Eric Auger)
>
> 

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM

Re: [Qemu-devel] [PATCH v2 2/2] Acceptance tests: expect boot to extract 2GiB+ initrd with linux-v4.16

2019-02-22 Thread Cleber Rosa




On 1/27/19 8:15 PM, Li Zhijian wrote:
> XLF_CAN_BE_LOADED_ABOVE_4G is set on vmlinuz shipped by Fedora-28 so that
> it's allowed to be loaded below 4 GB address.
> 
> timeout is updated to 5 minutes as well since we need more time to load a
> large initrd to the guest
> 
> CC: Wainer dos Santos Moschetta 
> CC: Caio Carrara 
> CC: Cleber Rosa 
> CC: Eduardo Habkost 
> CC: Philippe Mathieu-Daudé 
> Signed-off-by: Li Zhijian 
> 

Reviewed-by: Cleber Rosa

Re: [Qemu-devel] [PATCH v2 2/7] ui/cocoa: Use the pixman image directly in switchSurface

2019-02-22 Thread Roman Bolshakov

On Thu, Feb 14, 2019 at 10:28:11AM +, Peter Maydell wrote:
> Currently the switchSurface method takes a DisplaySurface. We want
> to change our DisplayChangeListener's dpy_gfx_switch callback
> to do this work asynchronously on a different thread. The caller
> of the switch callback will free the old DisplaySurface
> immediately the callback returns, so to ensure that the
> other thread doesn't access freed data we need to switch
> to using the underlying pixman image instead. The pixman
> image is reference counted, so we will be able to take
> a reference to it to avoid it vanishing too early.
> 
> In this commit we only change the switchSurface method
> to take a pixman image, and keep the flow of control
> synchronous for now.
> 
> Signed-off-by: Peter Maydell 
> ---
>  ui/cocoa.m | 17 +
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 

Reviewed-by: Roman Bolshakov 
Tested-by: Roman Bolshakov 

Thanks,
Roman

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