[Qemu-devel] [PATCH] decodetree: Add DisasContext to function part

[Yoshinori Sato]

OK. RX decoder works fine.

Since it is necessary to read additional bytes in the function
of the operand, we need to have DisasContext passed as an argument.

> %b2_li_2  18:2 !function=li
"li" read more extra byte. It use cpu_env in DisasContext.

Signed-off-by: Yoshinori Sato 
---
 scripts/decodetree.py | 32 +---
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index e23d43e354..fa9a75ccad 100755
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -387,7 +387,11 @@ class FunctionField:
 return self.func + '(' + str(self.base) + ')'
 
 def str_extract(self):
-return self.func + '(' + self.base.str_extract() + ')'
+if variablewidth:
+ctx = 'ctx, '
+else:
+ctx = ''
+return self.func + '(' + ctx + self.base.str_extract() + ')'
 
 def __eq__(self, other):
 return self.func == other.func and self.base == other.base
@@ -454,7 +458,11 @@ class Format(General):
 return 'extract_' + self.name
 
 def output_extract(self):
-output('static void ', self.extract_name(), '(',
+if variablewidth:
+ctx_p = 'DisasContext *ctx, '
+else:
+ctx_p = ''
+output('static void ', self.extract_name(), '(' + ctx_p,
self.base.struct_name(), ' *a, ', insntype, ' insn)\n{\n')
 for n, f in self.fields.items():
 output('a->', n, ' = ', f.str_extract(), ';\n')
@@ -468,10 +476,14 @@ class Pattern(General):
 def output_decl(self):
 global translate_scope
 global translate_prefix
+if variablewidth:
+ctx_p = 'DisasContext *ctx, '
+else:
+ctx_p = ''
 output('typedef ', self.base.base.struct_name(),
' arg_', self.name, ';\n')
 output(translate_scope, 'bool ', translate_prefix, '_', self.name,
-   '(DisasContext *ctx, arg_', self.name, ' *a);\n')
+   '(', ctx_p, 'arg_', self.name, ' *a);\n')
 
 def output_code(self, i, extracted, outerbits, outermask):
 global translate_prefix
@@ -479,7 +491,8 @@ class Pattern(General):
 arg = self.base.base.name
 output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n')
 if not extracted:
-output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n')
+output(ind, self.base.extract_name(),
+   '(ctx, &u.f_', arg, ', insn);\n')
 for n, f in self.fields.items():
 output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
 output(ind, 'return ', translate_prefix, '_', self.name,
@@ -890,11 +903,16 @@ class Tree:
 def output_code(self, i, extracted, outerbits, outermask):
 ind = str_indent(i)
 
+if variablewidth:
+ctx = 'ctx, '
+else:
+ctx = ''
 # If we identified all nodes below have the same format,
 # extract the fields now.
 if not extracted and self.base:
 output(ind, self.base.extract_name(),
-   '(&u.f_', self.base.base.name, ', insn);\n')
+   '(', ctx, '&u.f_', self.base.base.name,
+   ', insn);\n')
 extracted = True
 
 # Attempt to aid the compiler in producing compact switch statements.
@@ -994,7 +1012,7 @@ class SizeTree:
 # If we need to load more bytes to test, do so now.
 if extracted < self.width:
 output(ind, 'insn = ', decode_function,
-   '_load_bytes(s, insn, {0}, {1});\n'
+   '_load_bytes(ctx, insn, {0}, {1});\n'
.format(extracted / 8, self.width / 8));
 extracted = self.width
 
@@ -1048,7 +1066,7 @@ class SizeLeaf:
 # If we need to load more bytes, do so now.
 if extracted < self.width:
 output(ind, 'insn = ', decode_function,
-   '_load_bytes(s, insn, {0}, {1});\n'
+   '_load_bytes(ctx, insn, {0}, {1});\n'
.format(extracted / 8, self.width / 8));
 extracted = self.width
 output(ind, 'return insn;\n')
-- 
2.11.0

Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20190302062138.10713-1-ys...@users.sourceforge.jp/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190302062138.10713-1-ys...@users.sourceforge.jp
Subject: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]   
patchew/20190302062138.10713-1-ys...@users.sourceforge.jp -> 
patchew/20190302062138.10713-1-ys...@users.sourceforge.jp
Switched to a new branch 'test'
e60fbb35e6 MAINTAINERS: Add RX entry.
3bdc16f591 Add rx-softmmu
38c0424e72 RX Target hardware definition
a6ec852164 RX62N internal serial communication interface
179739cb93 RX62N internal timer modules
52c62d9d30 RX62N interrupt contorol uint
cee296b1c3 target/rx: miscellaneous functions
d2050c0e82 target/rx: RX disassembler
823a75d919 target/rx: CPU definition
d5927fc378 target/rx: TCG helper
6c80d5cc68 target/rx: TCG Translation

=== OUTPUT BEGIN ===
1/11 Checking commit 6c80d5cc686a (target/rx: TCG Translation)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
new file mode 100644

ERROR: spaces required around that '*' (ctx:WxV)
#2089: FILE: target/rx/translate.c:1728:
+static bool trans_FCMP_ri(DisasContext *ctx, arg_FCMP_ri *a)
  ^

ERROR: spaces required around that '*' (ctx:WxV)
#2111: FILE: target/rx/translate.c:1750:
+static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a)
^

ERROR: spaces required around that '*' (ctx:WxV)
#2232: FILE: target/rx/translate.c:1871:
+static bool trans_BNOT_lr(DisasContext *ctx, arg_BNOT_lr *a)
  ^

total: 3 errors, 1 warnings, 2556 lines checked

Patch 1/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/11 Checking commit d5927fc378e5 (target/rx: TCG helper)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 893 lines checked

Patch 2/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/11 Checking commit 823a75d91989 (target/rx: CPU definition)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 490 lines checked

Patch 3/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/11 Checking commit d2050c0e8217 (target/rx: RX disassembler)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

total: 0 errors, 1 warnings, 1587 lines checked

Patch 4/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/11 Checking commit cee296b1c31c (target/rx: miscellaneous functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 162 lines checked

Patch 5/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/11 Checking commit 52c62d9d30d9 (RX62N interrupt contorol uint)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

total: 0 errors, 1 warnings, 376 lines checked

Patch 6/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/11 Checking commit 179739cb93ee (RX62N internal timer modules)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

total: 0 errors, 1 warnings, 730 lines checked

Patch 7/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/11 Checking commit a6ec852164ae (RX62N internal serial communication 
interface)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 338 lines checked

Patch 8/11 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/11 Checking commit 38c0424e72dd (RX Target hardware definition)
WARNING: added, moved

[Qemu-devel] [PATCH RFC v3 05/11] target/rx: miscellaneous functions

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 target/rx/Makefile.objs |  11 +
 target/rx/gdbstub.c | 113 
 target/rx/monitor.c |  38 
 3 files changed, 162 insertions(+)
 create mode 100644 target/rx/Makefile.objs
 create mode 100644 target/rx/gdbstub.c
 create mode 100644 target/rx/monitor.c

diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs
new file mode 100644
index 00..f63e1ca43f
--- /dev/null
+++ b/target/rx/Makefile.objs
@@ -0,0 +1,11 @@
+obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
+obj-$(CONFIG_SOFTMMU) += monitor.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/rx/decode.inc.c: \
+  $(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
+   $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", 
$(TARGET_DIR)$@)
+
+target/rx/translate.o: target/rx/decode.inc.c
diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c
new file mode 100644
index 00..d1d484a612
--- /dev/null
+++ b/target/rx/gdbstub.c
@@ -0,0 +1,113 @@
+/*
+ * RX gdb server stub
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "exec/gdbstub.h"
+
+int rx_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+RXCPU *cpu = RXCPU(cs);
+CPURXState *env = &cpu->env;
+
+switch (n) {
+case 0 ... 15:
+return gdb_get_regl(mem_buf, env->regs[n]);
+case 16:
+return gdb_get_regl(mem_buf, (env->psw_u) ? env->regs[0] : env->usp);
+case 17:
+return gdb_get_regl(mem_buf, (!env->psw_u) ? env->regs[0] : env->isp);
+case 18:
+update_psw_o(env);
+return gdb_get_regl(mem_buf, pack_psw(env));
+case 19:
+return gdb_get_regl(mem_buf, env->pc);
+case 20:
+return gdb_get_regl(mem_buf, env->intb);
+case 21:
+return gdb_get_regl(mem_buf, env->bpsw);
+case 22:
+return gdb_get_regl(mem_buf, env->bpc);
+case 23:
+return gdb_get_regl(mem_buf, env->fintv);
+case 24:
+return gdb_get_regl(mem_buf, env->fpsw);
+case 25:
+return 0;
+}
+return 0;
+}
+
+int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+RXCPU *cpu = RXCPU(cs);
+CPURXState *env = &cpu->env;
+
+switch (n) {
+case 0 ... 15:
+env->regs[n] = ldl_p(mem_buf);
+if (n == 0) {
+if (env->psw_u) {
+env->usp = env->regs[0];
+} else {
+env->isp = env->regs[0];
+}
+}
+break;
+case 16:
+env->usp = ldl_p(mem_buf);
+if (env->psw_u) {
+env->regs[0] = ldl_p(mem_buf);
+}
+break;
+case 17:
+env->isp = ldl_p(mem_buf);
+if (!env->psw_u) {
+env->regs[0] = ldl_p(mem_buf);
+}
+break;
+case 18:
+env->psw = ldl_p(mem_buf);
+rx_cpu_unpack_psw(env, 1);
+break;
+case 19:
+env->pc = ldl_p(mem_buf);
+break;
+case 20:
+env->intb = ldl_p(mem_buf);
+break;
+case 21:
+env->bpsw = ldl_p(mem_buf);
+break;
+case 22:
+env->bpc = ldl_p(mem_buf);
+break;
+case 23:
+env->fintv = ldl_p(mem_buf);
+break;
+case 24:
+env->fpsw = ldl_p(mem_buf);
+break;
+case 25:
+return 8;
+default:
+return 0;
+}
+
+return 4;
+}
diff --git a/target/rx/monitor.c b/target/rx/monitor.c
new file mode 100644
index 00..5d7a1e58b5
--- /dev/null
+++ b/target/rx/monitor.c
@@ -0,0 +1,38 @@
+/*
+ * QEMU monitor
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFT

[Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support

[Yoshinori Sato]

Hello.
This patch series is added Renesas RX target emulation.

My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git

Since my understanding is not enough,
I want many comments to make this a good one.

Thanks.

Changes v2
Rewrite translate. using decodetree.py

Yoshinori Sato (11):
  target/rx: TCG Translation
  target/rx: TCG helper
  target/rx: CPU definition
  target/rx: RX disassembler
  target/rx: miscellaneous functions
  RX62N interrupt contorol uint
  RX62N internal timer modules
  RX62N internal serial communication interface
  RX Target hardware definition
  Add rx-softmmu
  MAINTAINERS: Add RX entry.

 MAINTAINERS|   20 +
 arch_init.c|2 +
 configure  |8 +
 default-configs/rx-softmmu.mak |7 +
 hw/char/Makefile.objs  |2 +-
 hw/char/renesas_sci.c  |  288 ++
 hw/intc/Makefile.objs  |1 +
 hw/intc/rx_icu.c   |  323 ++
 hw/rx/Makefile.objs|1 +
 hw/rx/rx62n.c  |  227 
 hw/rx/rxqemu.c |  100 ++
 hw/timer/Makefile.objs |2 +
 hw/timer/renesas_cmt.c |  235 +
 hw/timer/renesas_tmr.c |  412 
 include/disas/bfd.h|5 +
 include/hw/char/renesas_sci.h  |   42 +
 include/hw/intc/rx_icu.h   |   49 +
 include/hw/rx/rx.h |7 +
 include/hw/rx/rx62n.h  |   54 +
 include/hw/timer/renesas_cmt.h |   33 +
 include/hw/timer/renesas_tmr.h |   42 +
 include/sysemu/arch_init.h |1 +
 target/rx/Makefile.objs|   11 +
 target/rx/cpu-qom.h|   52 +
 target/rx/cpu.c|  224 
 target/rx/cpu.h|  214 
 target/rx/disas.c  | 1570 
 target/rx/gdbstub.c|  113 ++
 target/rx/helper.c |  252 +
 target/rx/helper.h |   39 +
 target/rx/insns.decode |  336 ++
 target/rx/monitor.c|   38 +
 target/rx/op_helper.c  |  602 +++
 target/rx/translate.c  | 2220 
 34 files changed, 7531 insertions(+), 1 deletion(-)
 create mode 100644 default-configs/rx-softmmu.mak
 create mode 100644 hw/char/renesas_sci.c
 create mode 100644 hw/intc/rx_icu.c
 create mode 100644 hw/rx/Makefile.objs
 create mode 100644 hw/rx/rx62n.c
 create mode 100644 hw/rx/rxqemu.c
 create mode 100644 hw/timer/renesas_cmt.c
 create mode 100644 hw/timer/renesas_tmr.c
 create mode 100644 include/hw/char/renesas_sci.h
 create mode 100644 include/hw/intc/rx_icu.h
 create mode 100644 include/hw/rx/rx.h
 create mode 100644 include/hw/rx/rx62n.h
 create mode 100644 include/hw/timer/renesas_cmt.h
 create mode 100644 include/hw/timer/renesas_tmr.h
 create mode 100644 target/rx/Makefile.objs
 create mode 100644 target/rx/cpu-qom.h
 create mode 100644 target/rx/cpu.c
 create mode 100644 target/rx/cpu.h
 create mode 100644 target/rx/disas.c
 create mode 100644 target/rx/gdbstub.c
 create mode 100644 target/rx/helper.c
 create mode 100644 target/rx/helper.h
 create mode 100644 target/rx/insns.decode
 create mode 100644 target/rx/monitor.c
 create mode 100644 target/rx/op_helper.c
 create mode 100644 target/rx/translate.c

-- 
2.11.0

[Qemu-devel] [PATCH RFC v3 11/11] MAINTAINERS: Add RX entry.

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 MAINTAINERS | 20 
 1 file changed, 20 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5040d9dfb1..141c4994b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -270,6 +270,14 @@ F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/
 
+RX
+M: Yoshinori Sato 
+S: Maintained
+F: target/rx/
+F: hw/rx/
+F: include/hw/rx/
+F: disas/rx.c
+
 S390
 M: Richard Henderson 
 M: David Hildenbrand 
@@ -1084,6 +1092,18 @@ F: pc-bios/canyonlands.dt[sb]
 F: pc-bios/u-boot-sam460ex-20100605.bin
 F: roms/u-boot-sam460ex
 
+RX Machines
+---
+RX-QEMU
+M: Yoshinori Sato 
+S: Maintained
+F: hw/rx/rxqemu.c
+F: hw/intc/rx_icu.c
+F: hw/timer/renesas_*.c
+F: hw/char/renesas_sci.c
+F: include/hw/timer/renesas_*.h
+F: include/hw/char/renesas_sci.h
+
 SH4 Machines
 
 R2D
-- 
2.11.0

[Qemu-devel] [PATCH RFC v3 09/11] RX Target hardware definition

[Yoshinori Sato]

rx62n -  RX62N cpu.
rxqemu - QEMU virtual target.

Signed-off-by: Yoshinori Sato 
---
 hw/rx/Makefile.objs   |   1 +
 hw/rx/rx62n.c | 227 ++
 hw/rx/rxqemu.c| 100 ++
 include/hw/rx/rx.h|   7 ++
 include/hw/rx/rx62n.h |  54 
 5 files changed, 389 insertions(+)
 create mode 100644 hw/rx/Makefile.objs
 create mode 100644 hw/rx/rx62n.c
 create mode 100644 hw/rx/rxqemu.c
 create mode 100644 include/hw/rx/rx.h
 create mode 100644 include/hw/rx/rx62n.h

diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs
new file mode 100644
index 00..e2edbb527e
--- /dev/null
+++ b/hw/rx/Makefile.objs
@@ -0,0 +1 @@
+obj-y += rx62n.o rxqemu.o
diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c
new file mode 100644
index 00..bab1a4ad8f
--- /dev/null
+++ b/hw/rx/rx62n.c
@@ -0,0 +1,227 @@
+/*
+ * RX62N device
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/rx/rx62n.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/address-spaces.h"
+
+static const int ipr_table[] = {
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */
+0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02,
+0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */
+0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */
+0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */
+0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */
+0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */
+0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
+0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */
+0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59,
+0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */
+0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f,
+0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */
+0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66,
+0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */
+0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b,
+0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71,
+0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80,
+0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */
+0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff,
+0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */
+0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89,
+0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */
+};
+
+static const uint32_t levelirq[] = {
+ 16,  21,  32,  44,  47,  48,  51,  64,  65,  66,
+ 67,  68,  69,  70,  71,  72,  73,  74,  75,  76,
+ 77,  78,  79,  90,  91, 170, 171, 172, 173, 214,
+217, 218, 221, 222, 225, 226, 229, 234, 237, 238,
+241, 246, 249, 250, 253,
+};
+
+static RXICUState *register_icu(RX62NState *s)
+{
+SysBusDevice *icu;
+int i;
+
+icu = SYS_BUS_DEVICE(qdev_create(NULL, TYPE_RXICU));
+sysbus_mmio_map(icu, 0, 0x00087000);
+qdev_prop_set_string(DEVICE(icu), "icutype", "icua");
+qdev_prop_set_uint32(DEVICE(icu), "len-ipr-map", 256);
+for (i = 0; i < 256; i++) {
+char propname[32];
+snprintf(propname, sizeof(propname), "ipr-map[%d]", i);
+qdev_prop_set_uint32(DEVICE(icu), propname, ipr_table[i]);
+}
+qdev_prop_set_uint32(DEVICE(icu), "len-trigger-level", 256);
+for (i = 0; i < ARRAY_SIZE(levelirq); i++) {
+char propname[32];
+snprintf(propname, sizeof(propname), "trigger-level[%d]", i);
+qdev_prop_set_uint32(DEVICE(icu), propname, levelirq[i]);
+}
+for (i = 0; i < 256; i++) {
+s->irq[i] = qdev_get_gpio_in(DEVICE(icu), i);
+}
+
+qdev_init_nofail(DEVICE(icu));
+sysbus_connect_irq(SYS_BUS_DEVICE(icu), 0,
+ 

[Qemu-devel] [PATCH RFC v3 10/11] Add rx-softmmu

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 arch_init.c| 2 ++
 configure  | 8 
 default-configs/rx-softmmu.mak | 7 +++
 include/sysemu/arch_init.h | 1 +
 4 files changed, 18 insertions(+)
 create mode 100644 default-configs/rx-softmmu.mak

diff --git a/arch_init.c b/arch_init.c
index f4f3f610c8..cc25ddd7ca 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -74,6 +74,8 @@ int graphic_depth = 32;
 #define QEMU_ARCH QEMU_ARCH_PPC
 #elif defined(TARGET_RISCV)
 #define QEMU_ARCH QEMU_ARCH_RISCV
+#elif defined(TARGET_RX)
+#define QEMU_ARCH QEMU_ARCH_RX
 #elif defined(TARGET_S390X)
 #define QEMU_ARCH QEMU_ARCH_S390X
 #elif defined(TARGET_SH4)
diff --git a/configure b/configure
index 540bee19ba..6bae0d4e97 100755
--- a/configure
+++ b/configure
@@ -7306,6 +7306,11 @@ case "$target_name" in
 mttcg=yes
 target_compiler=$cross_cc_riscv64
   ;;
+  rx)
+TARGET_ARCH=rx
+bflt="yes"
+target_compiler=$cross_cc_rx
+  ;;
   sh4|sh4eb)
 TARGET_ARCH=sh4
 bflt="yes"
@@ -7526,6 +7531,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
   riscv*)
 disas_config "RISCV"
   ;;
+  rx)
+disas_config "RX"
+  ;;
   s390*)
 disas_config "S390"
   ;;
diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak
new file mode 100644
index 00..0aaa8d4332
--- /dev/null
+++ b/default-configs/rx-softmmu.mak
@@ -0,0 +1,7 @@
+# Default configuration for rx-softmmu
+
+CONFIG_SERIAL=y
+CONFIG_PTIMER=y
+CONFIG_RX=y
+CONFIG_RENESAS_SCI=y
+CONFIG_RX_DIS=y
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 10cbafe970..3f4f844f7b 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -25,6 +25,7 @@ enum {
 QEMU_ARCH_NIOS2 = (1 << 17),
 QEMU_ARCH_HPPA = (1 << 18),
 QEMU_ARCH_RISCV = (1 << 19),
+QEMU_ARCH_RX = (1 << 20),
 };
 
 extern const uint32_t arch_type;
-- 
2.11.0

[Qemu-devel] [PATCH RFC v3 03/11] target/rx: CPU definition

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 target/rx/cpu-qom.h |  52 
 target/rx/cpu.c | 224 
 target/rx/cpu.h | 214 +
 3 files changed, 490 insertions(+)
 create mode 100644 target/rx/cpu-qom.h
 create mode 100644 target/rx/cpu.c
 create mode 100644 target/rx/cpu.h

diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
new file mode 100644
index 00..bad6d2c75d
--- /dev/null
+++ b/target/rx/cpu-qom.h
@@ -0,0 +1,52 @@
+/*
+ * QEMU RX CPU
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef QEMU_RX_CPU_QOM_H
+#define QEMU_RX_CPU_QOM_H
+
+#include "qom/cpu.h"
+
+#define TYPE_RXCPU "rxcpu"
+
+#define RXCPU_CLASS(klass) \
+OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RXCPU)
+#define RXCPU(obj) \
+OBJECT_CHECK(RXCPU, (obj), TYPE_RXCPU)
+#define RXCPU_GET_CLASS(obj) \
+OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RXCPU)
+
+/*
+ * RXCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A RX CPU model.
+ */
+typedef struct RXCPUClass {
+/*< private >*/
+CPUClass parent_class;
+/*< public >*/
+
+DeviceRealize parent_realize;
+void (*parent_reset)(CPUState *cpu);
+
+} RXCPUClass;
+
+typedef struct RXCPU RXCPU;
+
+#endif
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
new file mode 100644
index 00..1d0a2ff03b
--- /dev/null
+++ b/target/rx/cpu.c
@@ -0,0 +1,224 @@
+/*
+ * QEMU RX CPU
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "qemu-common.h"
+#include "migration/vmstate.h"
+#include "exec/exec-all.h"
+#include "hw/loader.h"
+
+static void rx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+RXCPU *cpu = RXCPU(cs);
+
+cpu->env.pc = value;
+}
+
+static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+RXCPU *cpu = RXCPU(cs);
+
+cpu->env.pc = tb->pc;
+}
+
+static bool rx_cpu_has_work(CPUState *cs)
+{
+return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+static void rx_cpu_reset(CPUState *s)
+{
+RXCPU *cpu = RXCPU(s);
+RXCPUClass *rcc = RXCPU_GET_CLASS(cpu);
+CPURXState *env = &cpu->env;
+uint32_t *resetvec;
+
+rcc->parent_reset(s);
+
+memset(env, 0, offsetof(CPURXState, end_reset_fields));
+
+resetvec = rom_ptr(0xfffc, 4);
+if (resetvec) {
+/* In the case of kernel, it is ignored because it is not set. */
+env->pc = ldl_p(resetvec);
+}
+env->psw = 0x;
+}
+
+typedef struct RXCPUListState {
+fprintf_function cpu_fprintf;
+FILE *file;
+} RXCPUListState;
+
+static void rx_cpu_list_entry(gpointer data, gpointer user_data)
+{
+RXCPUListState *s = user_data;
+const char *typename = object_class_get_name(OBJECT_CLASS(data));
+int len = strlen(typename) - strlen(RX_CPU_TYPE_SUFFIX);
+
+(*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
+}
+
+void rx_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+RXCPUListState s = {
+.cpu_fprintf = cpu_fprintf,
+.file = f,
+};
+GSList *list;
+
+list = object_class_get_list_sorted(TYPE_RXCPU, false);
+g_slist_foreach(list, rx_cpu_list_entry, &s);
+g_slist_free(list);
+}
+
+static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
+{
+ObjectClass *oc;
+char *typename = NULL;
+
+typename = g_strdup_printf(RX_CPU_TYPE_NAME(""));
+oc = object_class_by_name(typename);
+if (oc != NULL && object_class_is_abstract(oc)) {
+oc = NULL;
+}
+
+g_free(typename);
+return oc;
+}
+
+static void rx_cpu_realize(DeviceState *dev, Error **errp)

[Qemu-devel] [PATCH RFC v3 01/11] target/rx: TCG Translation

[Yoshinori Sato]

This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf

Signed-off-by: Yoshinori Sato 
---
 target/rx/insns.decode |  336 
 target/rx/translate.c  | 2220 
 2 files changed, 2556 insertions(+)
 create mode 100644 target/rx/insns.decode
 create mode 100644 target/rx/translate.c

diff --git a/target/rx/insns.decode b/target/rx/insns.decode
new file mode 100644
index 00..59de4566e0
--- /dev/null
+++ b/target/rx/insns.decode
@@ -0,0 +1,336 @@
+&bcnd  cd dsp
+&jdsp  dsp
+&jreg  rs
+&rrrd rs
+&rird imm
+&rrr   rd rs rs2
+&rri   rd imm rs2 len
+&rrli  rd rs2 imm
+&rmrd rs ld mi
+&mirs ld mi imm
+&mrrs ld mi rs2
+
+
+
+%b2_r_016:4
+%b2_li_2   18:2 !function=li
+%b2_li_8   24:2 !function=li
+%b2_dsp5_3 23:4 19:1
+
+@b2_rds   rd:4 &rr rs=255
+@b2_rds_li    rd:4 &rrli rs2=%b2_r_0 imm=%b2_li_8
+@b2_rds_uimm4    imm:4 rd:4&rri rs2=255 len=2
+@b2_rds_imm5    ... imm:5 rd:4 &rri rs2=255 len=2
+@b2_rd_rs_li     rs2:4 rd:4&rrli imm=%b2_li_8
+@b2_rd_ld_ub    .. ld:2 rs:4 rd:4  &rm mi=4
+@b2_ld_imm3 .. ld:2 rs:4 . imm:3   &mi mi=4
+
+
+
+%b3_r_08:4
+%b3_li_10  18:2 !function=li
+%b3_dsp5_8 23:1 16:4
+
+@b3_rd_rs      rs:4 rd:4   &rr
+@b3_rd_li       rd:4 \
+   &rrli rs2=%b3_r_0 imm=%b3_li_10
+@b3_rd_ld    mi:2  ld:2 rs:4 rd:4  &rm
+@b3_rd_ld_ub      .. ld:2 rs:4 rd:4&rm mi=4
+@b3_rd_ld_ul      .. ld:2 rs:4 rd:4&rm mi=2
+@b3_rd_rs_rs2     rd:4 rs:4 rs2:4  &rrr
+@b3_ld_rs2    .. ld:2 rs:4 rs2:4   &mr
+@b3_rds_imm5     ... imm:5 rd:4&rri rs2=%b3_r_0 len=2
+@b3_rd_rs_imm5   ... imm:5 rs2:4 rd:4  &rri len=2
+
+
+
+%b4_li_18  18:2 !function=li
+
+@b4_rd_ldmi  mi:2  ld:2   rs:4 rd:4&rm
+
+
+
+ABS_rr 0111 1110 0010  @b2_rds
+ABS_rr  1100       @b3_rd_rs
+
+ADC_rli 1101 0111 ..00 0010    @b3_rd_li
+ADC_rr  1100  1011     @b3_rd_rs
+# Note only mi==2 allowed.
+ADC_rl  0110 ..10 00..  0010   @b4_rd_ldmi
+
+ADD_rri0110 0010   @b2_rds_uimm4
+ADD_rrli   0111 00..   @b2_rd_rs_li
+ADD_rl 0100 10..   @b2_rd_ld_ub
+ADD_rl  0110 ..00 10..     @b3_rd_ld
+ADD_rrr  0010      @b3_rd_rs_rs2
+
+AND_ri 0110 0100   @b2_rds_uimm4
+AND_rli0111 01.. 0010  @b2_rds_li
+AND_rl 0101 00..   @b2_rd_ld_ub
+AND_rl  0110 ..01 00..     @b3_rd_ld
+AND_rrr  0100      @b3_rd_rs_rs2
+
+BCLR_li 00..  1... @b2_ld_imm3
+BCLR_ri0111 101.   @b2_rds_imm5
+BCLR_lr 1100 0110 01..     @b3_ld_rs2 mi=4
+
+BCnd_s 0001 cd:1 dsp:3 &bcnd
+BCnd_b 0010 cd:4 dsp:8 &bcnd
+BCnd_w 0011 101 cd:1 dsp:16&bcnd
+
+# Note that BNOT has cd = 15
+BMCnd_BNOT_mi   1100 111 imm:3 ld:2 rd:4 cd:4
+BMCnd_BNOT_ri   1101 111 imm:5 cd:4 rd:4
+
+BNOT_lr 1100 0110 11..     @b3_ld_rs2 mi=2
+
+BRA_s   1 dsp:3&jdsp
+#BRA_b 0010 1110 dsp:8 # overlaps BCnd_b
+BRA_w  0011 1000 dsp:16&jdsp
+BRA_a   0100 dsp:24&jdsp
+BRA_l  0111  0100 rd:4
+
+BRK 
+
+BSET_li 00..  0... @b2_ld_imm3
+BSET_ri0111 100.   @b2_rds_imm5
+BSET_lr 1100 0110 00..     @b3_ld_rs2 mi=4
+
+BSR_w  0011 1001 dsp:16&jdsp
+BSR_a   0101 dsp:24&jdsp
+BSR_l  0111  0101 rd:4
+
+BTST_li 01..  0... @b2_ld_imm3
+BTST_ri0111 110.   @b2_rds_imm5
+BTST_lr 1100 0110 10..     @b3_ld_rs2 mi=4
+
+

[Qemu-devel] [PATCH RFC v3 07/11] RX62N internal timer modules

[Yoshinori Sato]

renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3

Signed-off-by: Yoshinori Sato 
---
 hw/timer/Makefile.objs |   2 +
 hw/timer/renesas_cmt.c | 235 +++
 hw/timer/renesas_tmr.c | 412 +
 include/hw/timer/renesas_cmt.h |  33 
 include/hw/timer/renesas_tmr.h |  42 +
 5 files changed, 724 insertions(+)
 create mode 100644 hw/timer/renesas_cmt.c
 create mode 100644 hw/timer/renesas_tmr.c
 create mode 100644 include/hw/timer/renesas_cmt.h
 create mode 100644 include/hw/timer/renesas_tmr.h

diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 0e9a4530f8..e11aaf5bf5 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -40,6 +40,8 @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
 
 obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
 
+obj-$(CONFIG_RX) += renesas_tmr.o renesas_cmt.o
+
 common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
 
diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c
new file mode 100644
index 00..3d4a7d6ca6
--- /dev/null
+++ b/hw/timer/renesas_cmt.c
@@ -0,0 +1,235 @@
+/*
+ * Renesas 16bit Compare-match timer
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/timer/renesas_cmt.h"
+#include "qemu/error-report.h"
+
+#define freq_to_ns(freq) (10LL / freq)
+static const int clkdiv[] = {8, 32, 128, 512};
+
+static void update_events(RCMTState *cmt, int ch)
+{
+uint16_t diff;
+
+if ((cmt->cmstr & (1 << ch)) != 0) {
+diff = cmt->cmcor[ch] - cmt->cmcnt[ch];
+timer_mod(cmt->timer[ch],
+  qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+  diff * freq_to_ns(cmt->input_freq) *
+  clkdiv[cmt->cmcr[ch] & 3]);
+}
+}
+
+static uint64_t read_cmcnt(RCMTState *cmt, int ch)
+{
+int64_t delta, now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+if (cmt->cmstr & (1 << ch)) {
+delta = (now - cmt->tick[ch]) / freq_to_ns(cmt->input_freq);
+delta /= clkdiv[cmt->cmcr[ch] & 0x03];
+return cmt->cmcnt[ch] + delta;
+} else {
+return cmt->cmcnt[ch];
+}
+}
+
+static uint64_t cmt_read(void *opaque, hwaddr addr, unsigned size)
+{
+hwaddr offset = addr & 0x0f;
+RCMTState *cmt = opaque;
+int ch = offset / 0x08;
+int error = 1;
+
+if (offset == 0) {
+return cmt->cmstr;
+error = 0;
+} else {
+offset &= 0x07;
+if (ch == 0) {
+offset -= 0x02;
+}
+error = 0;
+switch (offset) {
+case 0:
+return cmt->cmcr[ch];
+case 2:
+return read_cmcnt(cmt, ch);
+case 4:
+return cmt->cmcor[ch];
+default:
+error = 1;
+}
+}
+if (error) {
+error_report("rcmt: unsupported read request to %08lx", addr);
+}
+return 0xUL;
+}
+
+static void start_stop(RCMTState *cmt, int ch, int st)
+{
+if (st) {
+update_events(cmt, ch);
+} else {
+timer_del(cmt->timer[ch]);
+}
+}
+
+static void cmt_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+hwaddr offset = addr & 0x0f;
+RCMTState *cmt = opaque;
+int ch = offset / 0x08;
+int error = 1;
+
+if (offset == 0) {
+cmt->cmstr = val;
+start_stop(cmt, 0, cmt->cmstr & 1);
+start_stop(cmt, 1, (cmt->cmstr >> 1) & 1);
+error = 0;
+} else {
+offset &= 0x07;
+if (ch == 0) {
+offset -= 0x02;
+}
+error = 0;
+switch (offset) {
+case 0:
+cmt->cmcr[ch] = val;
+break;
+case 2:
+cmt->cmcnt[ch] = val;
+break;
+case 4:
+cmt->cmcor[ch] = val;
+break;
+default:
+error = 1;
+}
+if (error == 0 && cmt->cmstr & (1 << ch)) {
+update_events(cmt, ch);
+}
+}
+if (error) {
+   

[Qemu-devel] [PATCH RFC v3 06/11] RX62N interrupt contorol uint

[Yoshinori Sato]

This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3

Signed-off-by: Yoshinori Sato 
---
 hw/intc/Makefile.objs|   1 +
 hw/intc/rx_icu.c | 323 +++
 include/hw/intc/rx_icu.h |  49 +++
 3 files changed, 373 insertions(+)
 create mode 100644 hw/intc/rx_icu.c
 create mode 100644 include/hw/intc/rx_icu.h

diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 301a8e972d..ff79edb54b 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -48,3 +48,4 @@ obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
 obj-$(CONFIG_MIPS_CPS) += mips_gic.o
 obj-$(CONFIG_NIOS2) += nios2_iic.o
 obj-$(CONFIG_OMPIC) += ompic.o
+obj-$(CONFIG_RX) += rx_icu.o
diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c
new file mode 100644
index 00..573cb144c6
--- /dev/null
+++ b/hw/intc/rx_icu.c
@@ -0,0 +1,323 @@
+/*
+ * RX Interrupt control unit
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/intc/rx_icu.h"
+#include "qemu/error-report.h"
+
+#define request(icu, n) (icu->ipr[icu->map[n]] << 8 | n)
+
+static qemu_irq *rxicu_pin(RXICUState *icu, int n_IRQ)
+{
+if ((icu->fir & 0x8000) && (icu->fir & 0xff) == n_IRQ) {
+return &icu->_fir;
+} else {
+return &icu->_irq;
+}
+}
+
+static void rxicu_request(RXICUState *icu, int n_IRQ)
+{
+int enable;
+
+enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
+if (enable != 0 && icu->req_irq < 0) {
+qemu_set_irq(*rxicu_pin(icu, n_IRQ), 0x1000 | request(icu, n_IRQ));
+icu->req_irq = n_IRQ;
+}
+}
+
+static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
+{
+RXICUState *icu = opaque;
+struct IRQSource *src;
+int issue;
+
+if (n_IRQ >= 256) {
+error_report("%s: IRQ %d out of range", __func__, n_IRQ);
+return;
+}
+
+src = &icu->src[n_IRQ];
+
+level = (level != 0);
+switch (src->sense) {
+case TRG_LEVEL:
+/* level-sensitive irq */
+issue = level;
+src->level = level;
+break;
+case TRG_NEDGE:
+issue = (level == 0 && src->level == 1);
+src->level = level;
+break;
+case TRG_PEDGE:
+issue = (level == 1 && src->level == 0);
+src->level = level;
+break;
+case TRG_BEDGE:
+issue = ((level ^ src->level) & 1);
+src->level = level;
+break;
+}
+if (issue == 0 && src->sense == TRG_LEVEL) {
+icu->ir[n_IRQ] = 0;
+if (icu->req_irq == n_IRQ) {
+qemu_set_irq(*rxicu_pin(icu, n_IRQ), request(icu, n_IRQ));
+icu->req_irq = -1;
+}
+return;
+}
+if (issue) {
+rxicu_request(icu, n_IRQ);
+}
+}
+
+static void rxicu_ack_irq(void *opaque, int no, int level)
+{
+RXICUState *icu = opaque;
+int i;
+int n_IRQ;
+int max_pri;
+
+if (icu->req_irq < 0) {
+return;
+}
+if (icu->src[icu->req_irq].sense != TRG_LEVEL) {
+icu->ir[icu->req_irq] = 0;
+}
+icu->req_irq = -1;
+
+max_pri = 0;
+n_IRQ = -1;
+for (i = 0; i < 256; i++) {
+if (icu->ir[i]) {
+if (max_pri < icu->ipr[icu->map[i]]) {
+n_IRQ = i;
+max_pri = icu->ipr[icu->map[i]];
+}
+}
+}
+if (n_IRQ >= 0) {
+rxicu_request(icu, n_IRQ);
+}
+}
+
+static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size)
+{
+hwaddr offset = addr & 0xfff;
+RXICUState *icu = opaque;
+int reg = addr & 0xff;
+int error;
+
+error = (!(offset == 0x2f0 && size == 2) &&
+ !(offset != 0x2f0 && size == 1));
+if (!error) {
+switch (offset) {
+case 0x000 ... 0x0ff:
+return icu->ir[reg] & 1;
+case 0x100 ... 0x1ff:
+return icu->dtcer[reg] & 1;
+case 0x200 ... 0x21f:
+return icu->ier[reg];
+case 0x2e0:
+return 0;
+case 0x2f0:
+return icu->fir & 0x80ff;
+case 0x300 ... 0x38f:
+return icu->ipr[reg] & 0x0f;
+case 0x400:
+case 0x404:
+case 0x408:
+   

[Qemu-devel] [PATCH RFC v3 02/11] target/rx: TCG helper

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 target/rx/helper.c| 252 +
 target/rx/helper.h|  39 
 target/rx/op_helper.c | 602 ++
 3 files changed, 893 insertions(+)
 create mode 100644 target/rx/helper.c
 create mode 100644 target/rx/helper.h
 create mode 100644 target/rx/op_helper.c

diff --git a/target/rx/helper.c b/target/rx/helper.c
new file mode 100644
index 00..9b0d0eacb4
--- /dev/null
+++ b/target/rx/helper.c
@@ -0,0 +1,252 @@
+/*
+ *  RX emulation
+ *
+ *  Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "exec/log.h"
+#include "exec/cpu_ldst.h"
+#include "sysemu/sysemu.h"
+
+uint32_t update_psw_o(CPURXState *env)
+{
+int o;
+
+switch (env->psw_op) {
+case RX_PSW_OP_NONE:
+return env->psw_o;
+case RX_PSW_OP_ADD: {
+uint32_t r1, r2;
+r1 = ~(env->psw_v[0] ^ env->psw_v[1]);
+r2 = (env->psw_v[0] ^ env->psw_v[2]);
+o = (r1 & r2) >> 31;
+break;
+}
+case RX_PSW_OP_SUB: {
+uint32_t r1, r2;
+r1 = (env->psw_v[0] ^ env->psw_v[1]);
+r2 = (env->psw_v[0] ^ env->psw_v[2]);
+o = (r1 & r2) >> 31;
+break;
+}
+case RX_PSW_OP_SHLL: {
+uint32_t m, v;
+m = (1 << env->psw_v[1]) - 1;
+v = env->psw_v[0] >> (32 - env->psw_v[1]);
+o = (v == 0) || (v == m);
+break;
+}
+default:
+g_assert_not_reached();
+return -1;
+}
+env->psw_o = o;
+env->psw_op = RX_PSW_OP_NONE;
+return o;
+}
+
+uint32_t rx_get_psw_low(CPURXState *env)
+{
+return (update_psw_o(env) << 3) |
+(env->psw_s << 2) |
+(env->psw_z << 1) |
+(env->psw_c << 0);
+}
+
+uint32_t psw_cond(CPURXState *env, uint32_t cond)
+{
+uint32_t c, z, s, o;
+
+switch (cond) {
+case 0: /* z */
+return env->psw_z != 0;
+case 1: /* nz */
+return env->psw_z == 0;
+case 2: /* c */
+return env->psw_c != 0;
+case 3: /* nc */
+return env->psw_c == 0;
+case 4: /* gtu (C&^Z) == 1 */
+case 5: /* leu (C&^Z) == 0 */
+c = env->psw_c != 0;
+z = env->psw_z != 0;
+return (c && !z) == (5 - cond);
+case 6: /* pz (S == 0) */
+return env->psw_s == 0;
+case 7: /* n (S == 1) */
+return env->psw_s != 0;
+case 8: /* ge (S^O)==0 */
+case 9: /* lt (S^O)==1 */
+s = env->psw_s != 0;
+o = update_psw_o(env);
+return (s | o) == (cond - 8);
+case 10: /* gt ((S^O)|Z)==0 */
+case 11: /* le ((S^O)|Z)==1 */
+s = env->psw_s != 0;
+o = update_psw_o(env);
+z = env->psw_z != 0;
+return ((s ^ o) | z) == (cond - 10);
+case 12: /* o */
+return update_psw_o(env) != 0;
+case 13: /* no */
+return update_psw_o(env) == 0;
+case 14: /* always true */
+return 1;
+case 15:
+return 0;
+default:
+g_assert_not_reached();
+return -1;
+}
+}
+
+void rx_cpu_unpack_psw(CPURXState *env, int all)
+{
+if (env->psw_pm == 0) {
+env->psw_ipl = (env->psw >> 24) & 15;
+if (all) {
+env->psw_pm = (env->psw >> 20) & 1;
+}
+env->psw_u =  (env->psw >> 17) & 1;
+env->psw_i =  (env->psw >> 16) & 1;
+}
+env->psw_o =  (env->psw >> 3) & 1;
+env->psw_s =  (env->psw >> 2) & 1;
+env->psw_z =  (env->psw >> 1) & 1;
+env->psw_c =  (env->psw >> 0) & 1;
+env->psw_op = RX_PSW_OP_NONE;
+}
+
+void rx_cpu_do_interrupt(CPUState *cs)
+{
+RXCPU *cpu = RXCPU(cs);
+CPURXState *env = &cpu->env;
+int do_irq = cs->interrupt_request &
+(CPU_INTERRUPT_HARD | CPU_INTERRUPT_SOFT | CPU_INTERRUPT_FIR);
+int irq_vector = -1;
+
+env->in_sleep = 0;
+
+if (do_irq & CPU_INTERRUPT_HARD) {
+irq_vector = env->irq;
+cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+}
+if (irq_vector == -1 && do_irq & CPU_INTERRUPT_SOFT) {
+irq_vector = env->sirq;
+cs->interrupt_request &= ~CPU_INTERRUPT_SOFT;
+}
+
+if (qemu_loglevel_mask(CPU_LOG_INT)) {
+if (cs->exception_index < 0x100) {
+const char *expname;
+switch (cs->exception_index) {
+case 20:
+expname = "previlage_violation";
+   

[Qemu-devel] [PATCH RFC v3 04/11] target/rx: RX disassembler

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato 
---
 include/disas/bfd.h |5 +
 target/rx/disas.c   | 1570 +++
 2 files changed, 1575 insertions(+)
 create mode 100644 target/rx/disas.c

diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 41b61c85f9..b2c34274dd 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -228,6 +228,10 @@ enum bfd_architecture
 #define bfd_mach_nios2r22
   bfd_arch_lm32,   /* Lattice Mico32 */
 #define bfd_mach_lm32 1
+  bfd_arch_rx,   /* Renesas RX */
+#define bfd_mach_rx0x75
+#define bfd_mach_rx_v2 0x76
+#define bfd_mach_rx_v3 0x77
   bfd_arch_last
   };
 #define bfd_mach_s390_31 31
@@ -432,6 +436,7 @@ int print_insn_little_nios2 (bfd_vma, 
disassemble_info*);
 int print_insn_xtensa   (bfd_vma, disassemble_info*);
 int print_insn_riscv32  (bfd_vma, disassemble_info*);
 int print_insn_riscv64  (bfd_vma, disassemble_info*);
+int print_insn_rx(bfd_vma, disassemble_info *);
 
 #if 0
 /* Fetch the disassembler for a given BFD, if that support is available.  */
diff --git a/target/rx/disas.c b/target/rx/disas.c
new file mode 100644
index 00..737fd425b6
--- /dev/null
+++ b/target/rx/disas.c
@@ -0,0 +1,1570 @@
+/*
+ * Renesas RX Disassembler
+ *
+ * Copyright (c) 2019 Yoshinori Sato 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "disas/bfd.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+
+typedef struct DisasContext {
+disassemble_info *dis;
+uint32_t addr;
+} DisasContext;
+
+
+static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
+   int i, int n)
+{
+bfd_byte buf;
+while (++i <= n) {
+ctx->dis->read_memory_func(ctx->addr++, &buf, 1, ctx->dis);
+insn |= buf << (32 - i * 8);
+}
+return insn;
+}
+
+static int32_t li(DisasContext *ctx, int sz)
+{
+int32_t addr;
+bfd_byte buf[4];
+addr = ctx->addr;
+
+switch (sz) {
+case 1:
+ctx->addr += 1;
+ctx->dis->read_memory_func(addr, buf, 1, ctx->dis);
+return buf[0];
+case 2:
+ctx->addr += 2;
+ctx->dis->read_memory_func(addr, buf, 2, ctx->dis);
+return buf[1] << 8 | buf[0];
+case 3:
+ctx->addr += 3;
+ctx->dis->read_memory_func(addr, buf, 3, ctx->dis);
+return buf[2] << 16 | buf[1] << 8 | buf[0];
+case 0:
+ctx->addr += 4;
+ctx->dis->read_memory_func(addr, buf, 4, ctx->dis);
+return buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0];
+default:
+g_assert_not_reached();
+}
+}
+
+/* Include the auto-generated decoder.  */
+#include "decode.inc.c"
+
+#define prt(...) (ctx->dis->fprintf_func)((ctx->dis->stream), __VA_ARGS__)
+
+#define RX_MEMORY_BYTE 0
+#define RX_MEMORY_WORD 1
+#define RX_MEMORY_LONG 2
+
+#define RX_MI_BYTE 0
+#define RX_MI_WORD 1
+#define RX_MI_LONG 2
+#define RX_MI_UWORD 3
+
+static const char size[] = {'b', 'w', 'l'};
+static const char *cond[] = {
+"eq", "ne", "c", "nc", "gtu", "leu", "pz", "n",
+"ge", "lt", "gt", "le", "o", "no", "ra", "f"
+};
+static const char *cr[] = {
+"psw", "", "usp", "fpsw", "", "", "", "",
+"bpsw", "bpc", "isp", "fintv", "intb", "", "", "",
+};
+static const char *msize[] = {
+"b", "w", "l", "ub", "uw",
+};
+
+static const char psw[] = {
+'c', 'z', 's', 'o', 0, 0, 0, 0,
+'i', 'u', 0, 0, 0, 0, 0, 0,
+};
+
+static uint32_t rx_index_addr(int ld, int size, DisasContext *ctx)
+{
+bfd_byte buf[2];
+switch (ld) {
+case 0:
+return 0;
+case 1:
+ctx->dis->read_memory_func(ctx->addr, buf, 1, ctx->dis);
+ctx->addr += 1;
+return buf[0];
+case 2:
+ctx->dis->read_memory_func(ctx->addr, buf, 2, ctx->dis);
+ctx->addr += 2;
+return buf[1] << 8 | buf[0];
+}
+g_assert_not_reached();
+}
+
+static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd)
+{
+int dsp;
+const char *mis;
+static const char *sizes[] = {".b", ".w", ".l"};
+if (ld < 3) {
+switch (mi) {
+case 4:
+/* dsp[rs].ub */
+dsp = rx_index_addr(ld, RX_MEMORY_BYTE, ctx);
+mis = ".ub";
+break;
+case 3:
+/* dsp[rs].uw */
+dsp = rx_index_addr(ld, RX_MEMORY_BYTE, ctx);
+mis = ".uw";

[Qemu-devel] [PATCH RFC v3 08/11] RX62N internal serial communication interface

[Yoshinori Sato]

This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3

Signed-off-by: Yoshinori Sato 
---
 hw/char/Makefile.objs |   2 +-
 hw/char/renesas_sci.c | 288 ++
 include/hw/char/renesas_sci.h |  42 ++
 3 files changed, 331 insertions(+), 1 deletion(-)
 create mode 100644 hw/char/renesas_sci.c
 create mode 100644 include/hw/char/renesas_sci.h

diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index c4947d7ae7..68eae7b9a5 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -15,7 +15,7 @@ common-obj-$(CONFIG_CADENCE) += cadence_uart.o
 obj-$(CONFIG_EXYNOS4) += exynos4210_uart.o
 obj-$(CONFIG_COLDFIRE) += mcf_uart.o
 obj-$(CONFIG_OMAP) += omap_uart.o
-obj-$(CONFIG_SH4) += sh_serial.o
+obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o
 obj-$(CONFIG_PSERIES) += spapr_vty.o
 obj-$(CONFIG_DIGIC) += digic-uart.o
 obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c
new file mode 100644
index 00..56d070a329
--- /dev/null
+++ b/hw/char/renesas_sci.c
@@ -0,0 +1,288 @@
+/*
+ * Renesas Serial Communication Interface
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/char/renesas_sci.h"
+#include "qemu/error-report.h"
+
+#define freq_to_ns(freq) (10LL / freq)
+
+static int can_receive(void *opaque)
+{
+RSCIState *sci = RSCI(opaque);
+if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
+return 0;
+} else {
+return sci->scr & 0x10;
+}
+}
+
+static void receive(void *opaque, const uint8_t *buf, int size)
+{
+RSCIState *sci = RSCI(opaque);
+sci->rdr = buf[0];
+if (sci->ssr & 0x40 || size > 1) {
+sci->ssr |= 0x20;
+if (sci->scr & 0x40) {
+qemu_set_irq(sci->irq[ERI], 1);
+}
+} else {
+sci->ssr |= 0x40;
+sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
+if (sci->scr & 0x40) {
+qemu_set_irq(sci->irq[RXI], 1);
+qemu_set_irq(sci->irq[RXI], 0);
+}
+}
+}
+
+static void send_byte(RSCIState *sci)
+{
+if (qemu_chr_fe_backend_connected(&sci->chr)) {
+qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
+}
+timer_mod(sci->timer,
+  qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime);
+sci->ssr &= ~0x04;
+sci->ssr |= 0x80;
+qemu_set_irq(sci->irq[TEI], 0);
+if (sci->scr & 0x80) {
+qemu_set_irq(sci->irq[TXI], 1);
+qemu_set_irq(sci->irq[TXI], 0);
+}
+}
+
+static void txend(void *opaque)
+{
+RSCIState *sci = RSCI(opaque);
+if ((sci->ssr & 0x80) == 0) {
+send_byte(sci);
+} else {
+sci->ssr |= 0x04;
+if (sci->scr & 0x04) {
+qemu_set_irq(sci->irq[TEI], 1);
+}
+}
+}
+
+static void update_trtime(RSCIState *sci)
+{
+static const int div[] = {1, 4, 16, 64};
+int w;
+
+w = (sci->smr & 0x40) ? 7 : 8;  /* CHR */
+w += (sci->smr >> 5) & 1;   /* PE */
+w += (sci->smr & 0x08) ? 2 : 1; /* STOP */
+sci->trtime = w * freq_to_ns(sci->input_freq) *
+32 * div[sci->smr & 0x03] * sci->brr;
+}
+
+static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+hwaddr offset = addr & 0x07;
+RSCIState *sci = RSCI(opaque);
+int error = 0;
+
+switch (offset) {
+case 0: /* SMR */
+if ((sci->scr & 0x30) == 0) {
+sci->smr = val;
+update_trtime(sci);
+}
+break;
+case 1: /* BRR */
+if ((sci->scr & 0x30) == 0) {
+sci->brr = val;
+update_trtime(sci);
+}
+break;
+case 2: /* SCR */
+sci->scr = val;
+if (sci->scr & 0x20) {
+sci->ssr |= 0x84;
+qemu_set_irq(sci->irq[TXI], 1);
+qemu_set_irq(sci->irq[TXI], 0);
+}
+if ((sci->scr & 0x04) == 0) {
+qemu_set_irq(sci->irq[TEI], 0);
+}
+if ((sci->scr & 0x40) == 0) {
+qemu_set_irq(sci->irq[ERI], 0);
+}
+break;
+case 3: /* TDR */
+sci->

[Qemu-devel] [Bug 1492649] Re: QEMU soundhw HDA huge microphone lag

[Jonathan Rubenstein]

I've got this issue too on windows 10 with QEMU emulator version 3.1.0
(Debian 1:3.1+dfsg-4). It seems to only occur when the device isn't used
in the windows host for a while by any application. If an application
opens the capture device, the delay slowly gets smaller until it's only
a 4th of a second.

My uneducated guess is that the pa/hda driver isn't dequeuing the buffer
unless the device is opened and being used by an application. This
should not be happening, it should move the read pointer to the sample
length even if the device isn't being used.

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https://bugs.launchpad.net/bugs/1492649

Title:
  QEMU soundhw HDA huge microphone lag

Status in QEMU:
  New

Bug description:
  I use a Windows 7 x86_64 guest with VGA passthrough and -soundhw hda.
  The audio plays fine, but the microphone input is delayed by more than
  20 seconds.

  -soundhw ac97 does not have this delay but it has choppy sound
  playback and input.

  System:
  Arch linux
  Kernel: 4.1.6-1-ARCH
  Audio hardware: 00:1b.0 Audio device: Intel Corporation 82801JI (ICH10 
Family) HD Audio Controller
  Audio system: Pulseaudio 6.0

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[Qemu-devel] [Bug 1492649] Re: QEMU soundhw HDA huge microphone lag

[Jonathan Rubenstein]

Proofread your comments, guys... oops

So it's a debian HOST and windows GUEST, not windows host. :-l

Sorry for the double post.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1492649

Title:
  QEMU soundhw HDA huge microphone lag

Status in QEMU:
  New

Bug description:
  I use a Windows 7 x86_64 guest with VGA passthrough and -soundhw hda.
  The audio plays fine, but the microphone input is delayed by more than
  20 seconds.

  -soundhw ac97 does not have this delay but it has choppy sound
  playback and input.

  System:
  Arch linux
  Kernel: 4.1.6-1-ARCH
  Audio hardware: 00:1b.0 Audio device: Intel Corporation 82801JI (ICH10 
Family) HD Audio Controller
  Audio system: Pulseaudio 6.0

To manage notifications about this bug go to:
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[Qemu-devel] [PATCH] slirp: fix big/little endian conversion in ident protocol

[Samuel Thibault]

Signed-off-by: Samuel Thibault 
---
 slirp/tcp_subr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
index ef9d99c154..1d7e72dca7 100644
--- a/slirp/tcp_subr.c
+++ b/slirp/tcp_subr.c
@@ -660,10 +660,12 @@ tcp_emu(struct socket *so, struct mbuf *m)
tmpso->so_fport == n1) {
if 
(getsockname(tmpso->s,
(struct 
sockaddr *)&addr, &addrlen) == 0)
-  n2 = 
ntohs(addr.sin_port);
+  n2 = addr.sin_port;
break;
}
}
+   NTOHS(n1);
+   NTOHS(n2);
so_rcv->sb_cc = 
snprintf(so_rcv->sb_data,
 
so_rcv->sb_datalen,
 "%d,%d\r\n", 
n1, n2);
-- 
2.20.1

Re: [Qemu-devel] [PATCH] slirp: check sscanf result when emulating ident

[Samuel Thibault]

William Bowling, le ven. 01 mars 2019 21:45:56 +, a ecrit:
> When emulating ident in tcp_emu, if the strchr checks passed but the
> sscanf check failed, two uninitialized variables would be copied and
> sent in the reply.
> 
> Signed-off-by: William Bowling 

Applied to my tree, thanks!

> ---
>  slirp/tcp_subr.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
> index 262a42d6c8..73a160ba16 100644
> --- a/slirp/tcp_subr.c
> +++ b/slirp/tcp_subr.c
> @@ -664,12 +664,12 @@ tcp_emu(struct socket *so, struct mbuf *m)
>   break;
>   }
>   }
> - }
> -so_rcv->sb_cc = snprintf(so_rcv->sb_data,
> - so_rcv->sb_datalen,
> - "%d,%d\r\n", n1, 
> n2);
> - so_rcv->sb_rptr = so_rcv->sb_data;
> - so_rcv->sb_wptr = so_rcv->sb_data + 
> so_rcv->sb_cc;
> +so_rcv->sb_cc = snprintf(so_rcv->sb_data,
> + so_rcv->sb_datalen,
> + "%d,%d\r\n", n1, n2);
> +so_rcv->sb_rptr = so_rcv->sb_data;
> +so_rcv->sb_wptr = so_rcv->sb_data + so_rcv->sb_cc;
> +}
>   }
>   m_free(m);
>   return 0;
> -- 
> 2.15.1
> 
> 

-- 
Samuel
What's this script do?
unzip ; touch ; finger ; mount ; gasp ; yes ; umount ; sleep
Hint for the answer: not everything is computer-oriented. Sometimes you're
in a sleeping bag, camping out.
(Contributed by Frans van der Zande.)

Re: [Qemu-devel] [PATCH v3 0/3] target/arm: Reduce overhead of cpu_get_tb_cpu_state

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20190222024106.9167-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190222024106.9167-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH v3 0/3] target/arm: Reduce overhead of 
cpu_get_tb_cpu_state

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190222024106.9167-1-richard.hender...@linaro.org -> 
patchew/20190222024106.9167-1-richard.hender...@linaro.org
Switched to a new branch 'test'
9819e46d70 target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
a0f765dba8 target/arm: Rebuild hflags at el changes and MSR writes
d65ebaa1a8 target/arm: Split out recompute_hflags et al

=== OUTPUT BEGIN ===
1/3 Checking commit d65ebaa1a826 (target/arm: Split out recompute_hflags et al)
WARNING: Block comments use a leading /* on a separate line
#127: FILE: target/arm/helper.c:12837:
+/* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is

WARNING: Block comments use a leading /* on a separate line
#172: FILE: target/arm/helper.c:12882:
+/* If SVE is disabled, but FP is enabled,

total: 0 errors, 2 warnings, 368 lines checked

Patch 1/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/3 Checking commit a0f765dba8a1 (target/arm: Rebuild hflags at el changes and 
MSR writes)
3/3 Checking commit 9819e46d702e (target/arm: Rely on hflags correct in 
cpu_get_tb_cpu_state)
ERROR: Use g_assert or g_assert_not_reached
#76: FILE: target/arm/helper.c:12959:
+g_assert_cmphex(flags, ==, check_flags);

total: 1 errors, 0 warnings, 34 lines checked

Patch 3/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190222024106.9167-1-richard.hender...@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[Qemu-devel] [PATCH] slirp: check sscanf result when emulating ident

[William Bowling]

When emulating ident in tcp_emu, if the strchr checks passed but the
sscanf check failed, two uninitialized variables would be copied and
sent in the reply.

Signed-off-by: William Bowling 
---
 slirp/tcp_subr.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
index 262a42d6c8..73a160ba16 100644
--- a/slirp/tcp_subr.c
+++ b/slirp/tcp_subr.c
@@ -664,12 +664,12 @@ tcp_emu(struct socket *so, struct mbuf *m)
break;
}
}
-   }
-so_rcv->sb_cc = snprintf(so_rcv->sb_data,
- so_rcv->sb_datalen,
- "%d,%d\r\n", n1, n2);
-   so_rcv->sb_rptr = so_rcv->sb_data;
-   so_rcv->sb_wptr = so_rcv->sb_data + 
so_rcv->sb_cc;
+so_rcv->sb_cc = snprintf(so_rcv->sb_data,
+ so_rcv->sb_datalen,
+ "%d,%d\r\n", n1, n2);
+so_rcv->sb_rptr = so_rcv->sb_data;
+so_rcv->sb_wptr = so_rcv->sb_data + so_rcv->sb_cc;
+}
}
m_free(m);
return 0;
-- 
2.15.1

Re: [Qemu-devel] [PATCH v3 0/3] target/arm: Reduce overhead of cpu_get_tb_cpu_state

[Emilio G. Cota]

On Thu, Feb 21, 2019 at 18:41:03 -0800, Richard Henderson wrote:
> Changes since v2:
>   * Do not cache VECLEN, VECSTRIDE, VFPEN.
> These variables come from VFP_FPSCR and VFP_FPEXC, not from
> system control registers.
>   * Move HANDLER and STACKCHECK to rebuild_hflags_a32,
> instead of building them in rebuild_hflags_common.

Tested-by: Emilio G. Cota 

You might want to add these numbers (I re-ran the benchmarks for v3)
to patch 3's commit log:

aarch64-linux-user SPEC06int (train set)
 Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz
 2.2 +--+
 |  |
 |after |
   2 |-+.+-+..+-|
 || |
 |   *|*|
 |   *|*  +-+   |
 1.8 |-+..+-++-+...|..+-|
 | | * *   ||
 |   **|*   +-+ *+-+ * *  *|*   |
 1.6 |-+.*+-+..**|*.*..*.*.*.*+-+.*|*.+-|
 |   *  *  *+-+ *  * * * *+-+ *|*   |
 |   *  *  *  * *  * * * *  * +-+   |
 1.4 |-+.*..*..+-+.*..*.*..*.*.*.*..*.*.*.*+-++-|
 |   *  * **|* *  * *  * * * *  * * * *+-+  |
 |  *+-+ *  * *+-+ *  * *  * * * *  * * * *  *  |
 1.2 |-+*+-+.*..*.*..*.*..*.*..*.*.*.*..*.*.*.*..*+-|
 |  *  * +-+ *  * *  * +-+ *  * *  * * * *  * * * *  *  |
 |  *  *  |  *  * +-+ *  * +-+ *  * +-+ *  * * * *  * * * *  *  |
 |  *  * *|* *  * *|* *  * * * *  * +-+ *  * * * *  * * * *  *  |
   1 |++*++*++-++*++*++-++*++*+*+*+*++*+*+*+*++*+*+*+*++*+*+*+*++*++|
 |  *  * * * *  * * * *  * * * *  * * * *  * * * *  * * * *  *  |
 |  *  * * * *  * * * *  * * * *  * * * *  * * * *  * * * *  *  |
 0.8 +--+
 400.perl401.bzi403.429445.456.462.libq464.471.omn483.xalancbgeomean
  png: https://imgur.com/wr4ODMw

Thanks,

Emilio

Re: [Qemu-devel] [PATCH v2] slirp: check for ioctlsocket error and 0-length udp payload.

[Samuel Thibault]

Vic Lee, le ven. 01 mars 2019 14:48:09 +0800, a ecrit:
> Sometimes sorecvfrom() is called from slirp.c because revents == G_IO_IN,
> but there is 0 bytes available and recvfrom could be blocking indefinitely.
> This is likely due to 0-length udp payload. This also adds an error
> checking for ioctlsocket.
> 
> Signed-off-by: Vic Lee 

Applied to my tree, thanks!

Samuel

Re: [Qemu-devel] [PATCH v2] slirp: Fix build with gcc 9

[Samuel Thibault]

Peter Maydell, le ven. 01 mars 2019 09:49:26 +, a ecrit:
> On Fri, 1 Mar 2019 at 09:39, Greg Kurz  wrote:
> >
> > Build fails with gcc 9:
> >
> >   CC  slirp/ndp_table.o
> > slirp/ndp_table.c: In function ‘ndp_table_add’:
> > slirp/ndp_table.c:31:23: error: taking address of packed member of ‘struct 
> > ndpentry’ may result in an unaligned pointer value 
> > [-Werror=address-of-packed-member]
> >31 | if (in6_equal(&ndp_table->table[i].ip_addr, &ip_addr)) {
> >   |   ^~~~
> > slirp/ndp_table.c: In function ‘ndp_table_search’:
> > slirp/ndp_table.c:75:23: error: taking address of packed member of ‘struct 
> > ndpentry’ may result in an unaligned pointer value 
> > [-Werror=address-of-packed-member]
> >75 | if (in6_equal(&ndp_table->table[i].ip_addr, &ip_addr)) {
> >   |   ^~~~
> > cc1: all warnings being treated as errors
> >
> > The ndpentry structure isn't used to model on-the-wire data or anything
> > else that would care for the struct layout. It doesn't need to be packed
> > actually. Just drop SLIRP_PACKED.
> >
> > Signed-off-by: Greg Kurz 
> > ---
> > v2: - don't check the struct size at compile time
> > ---
> >  slirp/slirp.h |2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/slirp/slirp.h b/slirp/slirp.h
> > index 752a4cd8c81c..8068ba1d1e9e 100644
> > --- a/slirp/slirp.h
> > +++ b/slirp/slirp.h
> > @@ -106,7 +106,7 @@ bool arp_table_search(Slirp *slirp, uint32_t ip_addr,
> >  struct ndpentry {
> >  unsigned char   eth_addr[ETH_ALEN]; /* sender hardware address */
> >  struct in6_addr ip_addr;/* sender IP address   */
> > -} SLIRP_PACKED;
> > +};
> >
> >  #define NDP_TABLE_SIZE 16
> 
> Reviewed-by: Peter Maydell 

Applied to my tree, thanks!

Samuel

Re: [Qemu-devel] [PATCH 2/2] spapr: Simulate CAS for qtest

[Michael Roth]

Quoting Greg Kurz (2019-03-01 13:32:37)
> The RTAS event hotplug code for machine types 2.8 and newer depends on
> the CAS negotiated ov5 in order to work properly. However, there's no
> CAS when running under qtest. There has been a tentative to trick the
> code by faking the OV5_HP_EVT bit, but it turned out to break other
> assumptions in the code and the change got reverted.
> 
> Go for a more general approach and simulate a CAS when running under
> qtest. For simplicity, this pseudo CAS simple simulates the case where
> the guest supports the same features as the machine. It is done at
> reset time, just before we reset the DRCs, which could potentially
> exercise the unplug code.
> 
> This allows to test unplug on spapr with both older and newer machine
> types.
> 
> Suggested-by: Michael Roth 
> Signed-off-by: Greg Kurz 

Tested-by: Michael Roth 
Reviewed-by: Michael Roth 

Thanks for sending this!

Just now realizing we should probably apply the revert after this patch
however, since the commit we're reverting fixes a `make check` test that
is run by default, whereas this patch fixes one that only gets run if we
run the tests with -m=slow specified.

Maybe David can do that on his end?

> ---
>  hw/ppc/spapr.c |   11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index b6a571b6f184..6da64ef7ee2b 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -29,6 +29,7 @@
>  #include "qapi/visitor.h"
>  #include "sysemu/sysemu.h"
>  #include "sysemu/numa.h"
> +#include "sysemu/qtest.h"
>  #include "hw/hw.h"
>  #include "qemu/log.h"
>  #include "hw/fw-path-provider.h"
> @@ -1711,6 +1712,16 @@ static void spapr_machine_reset(void)
>   */
>  spapr_irq_reset(spapr, &error_fatal);
> 
> +/*
> + * There is no CAS under qtest. Simulate one to please the code that
> + * depends on spapr->ov5_cas. This is especially needed to test device
> + * unplug, so we do that before resetting the DRCs.
> + */
> +if (qtest_enabled()) {
> +spapr_ovec_cleanup(spapr->ov5_cas);
> +spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> +}
> +
>  /* DRC reset may cause a device to be unplugged. This will cause troubles
>   * if this device is used by another device (eg, a running vhost backend
>   * will crash QEMU if the DIMM holding the vring goes away). To avoid 
> such
> 

[Qemu-devel] [PULL 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

[Palmer Dabbelt]

From: Bastian Koppelmann 

only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn16.decode  | 37 +--
 target/riscv/insn_trans/trans_rvc.inc.c | 48 -
 2 files changed, 17 insertions(+), 68 deletions(-)

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 98dd672c7f59..d88a0c78ab5d 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -46,19 +46,15 @@
 &i imm rs1 rd   !extern
 &s imm rs1 rs2  !extern
 &j imm rd   !extern
+&b imm rs2 rs1  !extern
 
 # Argument sets:
 &ciimmrd
 &ciw   nzuimm rd
 &cs_dw uimm   rs1 rs2
-&cbimmrs1
 &cr   rd  rs2
-&c_j   imm
 &c_shift   shamt  rd
 
-&c_ld  uimm  rd
-&c_sd  uimm  rs2
-
 &c_addi16sp_lui  imm_lui imm_addi16sp rd
 
 # Formats 16:
@@ -70,20 +66,21 @@
 @cs_2  ... ... ... .. ... .. &r  rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
 @cs_d  ... ... ... .. ... .. &s  imm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
 @cs_w  ... ... ... .. ... .. &s  imm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
-@cb... ... ... .. ... .. &cb imm=%imm_cb  rs1=%rs1_3
-@cj...... .. &c_jimm=%imm_cj
+@cb... ... ... .. ... .. &b  imm=%imm_cb  rs1=%rs1_3 rs2=0
+@cj...... .. &j  imm=%imm_cj rd=0
 
-@c_ld  ... . .  . .. &c_ld uimm=%uimm_6bit_ld  %rd
-@c_lw  ... . .  . .. &c_ld uimm=%uimm_6bit_lw  %rd
-@c_sd  ... . .  . .. &c_sd uimm=%uimm_6bit_sd  rs2=%rs2_5
-@c_sw  ... . .  . .. &c_sd uimm=%uimm_6bit_sw  rs2=%rs2_5
+@c_ld  ... . .  . .. &i  imm=%uimm_6bit_ld  %rd rs1=2
+@c_lw  ... . .  . .. &i  imm=%uimm_6bit_lw  %rd rs1=2
+@c_sd  ... . .  . .. &s  imm=%uimm_6bit_sd  rs1=2 rs2=%rs2_5
+@c_sw  ... . .  . .. &s  imm=%uimm_6bit_sw  rs1=2 rs2=%rs2_5
 
 @c_addi16sp_lui ... .  . . .. &c_addi16sp_lui %imm_lui %imm_addi16sp 
%rd
 
 @c_shift... . .. ... . .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
 @c_shift2   ... . .. ... . .. &c_shift rd=%rdshamt=%nzuimm_6bit
 
-@c_andi ... . .. ... . .. &ci imm=%imm_ci rd=%rs1_3
+@c_andi ... . .. ... . .. &i imm=%imm_ci rd=%rs1_3 rs1=%rs1_3
+
 
 # *** RV64C Standard Extension (Quadrant 0) ***
 c_addi4spn000 ... 00 @ciw
@@ -98,20 +95,20 @@ c_li  010 .  .  . 01 @ci
 c_addi16sp_lui011 .  .  . 01 @c_addi16sp_lui # shares opc with 
C.LUI
 c_srli100 . 00 ...  . 01 @c_shift
 c_srai100 . 01 ...  . 01 @c_shift
-c_andi100 . 10 ...  . 01 @c_andi
+andi  100 . 10 ...  . 01 @c_andi
 sub   100 0 11 ... 00 ... 01 @cs_2
 xor   100 0 11 ... 01 ... 01 @cs_2
 or100 0 11 ... 10 ... 01 @cs_2
 and   100 0 11 ... 11 ... 01 @cs_2
-c_j   101 ... 01 @cj
-c_beqz110  ... ...  . 01 @cb
-c_bnez111  ... ...  . 01 @cb
+jal   101 ... 01 @cj # c_j
+beq   110  ... ...  . 01 @cb # c_beqz
+bne   111  ... ...  . 01 @cb # c_bnez
 
 # *** RV64C Standard Extension (Quadrant 2) ***
 c_slli000 .  .  . 10 @c_shift2
-c_fldsp   001 .  .  . 10 @c_ld
-c_lwsp010 .  .  . 10 @c_lw
+fld   001 .  .  . 10 @c_ld # fldsp
+lw010 .  .  . 10 @c_lw # lwsp
 c_jr_mv   100 0  .  . 10 @cr
 c_ebreak_jalr_add 100 1  .  . 10 @cr
-c_fsdsp   101   ..  . 10 @c_sd
-c_swsp110 .  .  . 10 @c_sw
+fsd   101   ..  . 10 @c_sd # fsdsp
+sw110 .  .  . 10 @c_sw # swsp
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index db9119ec9b17..631e72c8b585 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -98,30 +98,6 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
 return trans_srai(ctx, &arg);
 }
 
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
-arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
-return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
-arg_jal arg = { .rd = 0, .imm = a->imm };
-return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
-arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
-return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
-arg_bne arg = { .rs1 = a->r

[Qemu-devel] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvm.inc.c |  55 ++--
 target/riscv/translate.c| 320 ++--
 2 files changed, 164 insertions(+), 211 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvm.inc.c 
b/target/riscv/insn_trans/trans_rvm.inc.c
index 69631c9e3783..d2bf2f171904 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -22,92 +22,99 @@
 static bool trans_mul(DisasContext *ctx, arg_mul *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_mul_tl);
 }
 
 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 = tcg_temp_new();
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
+tcg_temp_free(source2);
 return true;
 }
 
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_mulhsu);
 }
 
 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 = tcg_temp_new();
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
+tcg_temp_free(source2);
 return true;
 }
 
 static bool trans_div(DisasContext *ctx, arg_div *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_div);
 }
 
 static bool trans_divu(DisasContext *ctx, arg_divu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_divu);
 }
 
 static bool trans_rem(DisasContext *ctx, arg_rem *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_rem);
 }
 
 static bool trans_remu(DisasContext *ctx, arg_remu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_remu);
 }
 
 #ifdef TARGET_RISCV64
 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_mulw);
 }
 
 static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
-return true;
+return gen_arith_div_w(ctx, a, &gen_div);
 }
 
 static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
-return true;
+return gen_arith_div_w(ctx, a, &gen_divu);
 }
 
 static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
-return true;
+return gen_arith_div_w(ctx, a, &gen_rem);
 }
 
 static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
-return true;
+return gen_arith_div_w(ctx, a, &gen_remu);
 }
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9ae40f65096f..3cd7e16c63cf 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -188,193 +188,112 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 tcg_temp_free(rh);
 }
 
-static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-int rs2)
-{
-TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
-source1 = tcg_temp_new();
-source2 = tcg_temp_new();
-gen_get_gpr(source1, rs1);
-gen_get_gpr(source2, rs2);
-
-switch (opc) {
-CASE_OP_32_64(OPC_RISC_MUL):
-if (!has_ext(ctx, RVM)) {
-goto do_illegal;
-}
-tcg_gen_mul_tl(source1, source1, source2);
-break;
-case OPC_RISC_MULH:
-if (!has_ext(ctx, RVM)) {
-goto do_illegal;
-}
-tcg_gen_muls2_tl(source2, source1, source1, source2);
-break;
-case OPC_RISC_MULHSU:
-if (!has_ext(ctx, RVM)) {
-goto do_illegal;
-}
-gen_mulhsu(source1, source1, source2

[Qemu-devel] [PULL 13/34] target/riscv: Convert RV32D insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  28 ++
 target/riscv/insn_trans/trans_rvd.inc.c | 360 
 target/riscv/translate.c|   1 +
 3 files changed, 389 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e40836bf032f..e64b2b5e3458 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -154,3 +154,31 @@ fclass_s   111  0 . 001 . 1010011 @r2
 fcvt_s_w   1101000  0 . ... . 1010011 @r2_rm
 fcvt_s_wu  1101000  1 . ... . 1010011 @r2_rm
 fmv_w_x000  0 . 000 . 1010011 @r2
+
+# *** RV32D Standard Extension ***
+fld   . 011 . 111 @i
+fsd... .  . 011 . 0100111 @s
+fmadd_d. 01 . . ... . 111 @r4_rm
+fmsub_d. 01 . . ... . 1000111 @r4_rm
+fnmsub_d   . 01 . . ... . 1001011 @r4_rm
+fnmadd_d   . 01 . . ... . 100 @r4_rm
+fadd_d 001  . . ... . 1010011 @r_rm
+fsub_d 101  . . ... . 1010011 @r_rm
+fmul_d 0001001  . . ... . 1010011 @r_rm
+fdiv_d 0001101  . . ... . 1010011 @r_rm
+fsqrt_d0101101  0 . ... . 1010011 @r2_rm
+fsgnj_d0010001  . . 000 . 1010011 @r
+fsgnjn_d   0010001  . . 001 . 1010011 @r
+fsgnjx_d   0010001  . . 010 . 1010011 @r
+fmin_d 0010101  . . 000 . 1010011 @r
+fmax_d 0010101  . . 001 . 1010011 @r
+fcvt_s_d   010  1 . ... . 1010011 @r2_rm
+fcvt_d_s   011  0 . ... . 1010011 @r2_rm
+feq_d  1010001  . . 010 . 1010011 @r
+flt_d  1010001  . . 001 . 1010011 @r
+fle_d  1010001  . . 000 . 1010011 @r
+fclass_d   1110001  0 . 001 . 1010011 @r2
+fcvt_w_d   111  0 . ... . 1010011 @r2_rm
+fcvt_wu_d  111  1 . ... . 1010011 @r2_rm
+fcvt_d_w   1101001  0 . ... . 1010011 @r2_rm
+fcvt_d_wu  1101001  1 . ... . 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c 
b/target/riscv/insn_trans/trans_rvd.inc.c
new file mode 100644
index ..98fc1cdc5a20
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -0,0 +1,360 @@
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a)
+{
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+tcg_gen_addi_tl(t0, t0, a->imm);
+
+tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+mark_fs_dirty(ctx);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+{
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+tcg_gen_addi_tl(t0, t0, a->imm);
+
+tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+mark_fs_dirty(ctx);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+gen_set_rm(ctx, a->rm);
+gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+   cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+mark_fs_dirty(ctx);
+return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+gen_set_rm(ctx, a->rm);
+gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+   cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+mark_fs_dirty(ctx);
+return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+gen_set_rm(ctx, a->rm);
+gen_helper_fnmsub_d(cpu

[Qemu-devel] [PULL 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn16.decode  |  31 
 target/riscv/insn_trans/trans_rvc.inc.c | 101 
 target/riscv/translate.c|  83 +--
 3 files changed, 134 insertions(+), 81 deletions(-)

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 29dade0fa1ae..0829e3bc592d 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -20,6 +20,7 @@
 %rd7:5
 %rs1_3 7:3!function=ex_rvc_register
 %rs2_3 2:3!function=ex_rvc_register
+%rs2_5 2:5
 
 # Immediates:
 %imm_ci12:s1 2:5
@@ -30,6 +31,10 @@
 %imm_cj12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
 
 %nzuimm_6bit   12:1 2:5
+%uimm_6bit_ld 2:3 12:1 5:2   !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3   !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3   !function=ex_shift_3
+%uimm_6bit_sw 7:2 9:4!function=ex_shift_2
 
 %imm_addi16sp  12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
 %imm_lui   12:s1 2:5 !function=ex_shift_12
@@ -48,10 +53,15 @@
 &c_j   imm
 &c_shift   shamt  rd
 
+&c_ld  uimm  rd
+&c_sd  uimm  rs2
 
 &c_addi16sp_lui  imm_lui imm_addi16sp rd
+&c_flwsp_ldspuimm_flwsp uimm_ldsp rd
+&c_fswsp_sdspuimm_fswsp uimm_sdsp rs2
 
 # Formats 16:
+@cr  . .  .. &cr  rs2=%rs2_5  %rd
 @ci... . . .  .. &ci imm=%imm_ci  %rd
 @ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
 @cl_d  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
@@ -64,9 +74,19 @@
 @cb... ... ... .. ... .. &cb imm=%imm_cb  rs1=%rs1_3
 @cj...... .. &c_jimm=%imm_cj
 
+@c_ld  ... . .  . .. &c_ld uimm=%uimm_6bit_ld  %rd
+@c_lw  ... . .  . .. &c_ld uimm=%uimm_6bit_lw  %rd
+@c_sd  ... . .  . .. &c_sd uimm=%uimm_6bit_sd  rs2=%rs2_5
+@c_sw  ... . .  . .. &c_sd uimm=%uimm_6bit_sw  rs2=%rs2_5
+
 @c_addi16sp_lui ... .  . . .. &c_addi16sp_lui %imm_lui %imm_addi16sp 
%rd
+@c_flwsp_ldsp   ... .  . . .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp   ... .  . . .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
+uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
 
 @c_shift... . .. ... . .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2   ... . .. ... . .. &c_shift rd=%rdshamt=%nzuimm_6bit
 
 @c_andi ... . .. ... . .. &ci imm=%imm_ci rd=%rs1_3
 
@@ -96,3 +116,14 @@ c_addw100 1 11 ... 01 ... 01 @cs_2
 c_j   101 ... 01 @cj
 c_beqz110  ... ...  . 01 @cb
 c_bnez111  ... ...  . 01 @cb
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+c_slli000 .  .  . 10 @c_shift2
+c_fldsp   001 .  .  . 10 @c_ld
+c_lwsp010 .  .  . 10 @c_lw
+c_flwsp_ldsp  011 .  .  . 10 @c_flwsp_ldsp 
#C.LDSP:RV64;C.FLWSP:RV32
+c_jr_mv   100 0  .  . 10 @cr
+c_ebreak_jalr_add 100 1  .  . 10 @cr
+c_fsdsp   101   ..  . 10 @c_sd
+c_swsp110 .  .  . 10 @c_sw
+c_fswsp_sdsp  111 .  .  . 10 @c_fswsp_sdsp 
#C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index b06c435c9800..bcdf64d3b705 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
 arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
 return trans_bne(ctx, &arg);
 }
+
+static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
+{
+int shamt = a->shamt;
+if (shamt == 0) {
+/* For RV128 a shamt of 0 means a shift by 64 */
+shamt = 64;
+}
+/* Ensure, that shamt[5] is zero for RV32 */
+if (shamt >= TARGET_LONG_BITS) {
+return false;
+}
+
+arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
+return trans_slli(ctx, &arg);
+}
+
+static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
+{
+arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+return trans_fld(ctx, &arg);
+}
+
+static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
+{
+arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
+return trans_lw(ctx, &arg);
+}
+
+static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
+{
+#ifdef TARGET_RISCV32
+/* C.FLWSP */
+arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
+return trans_flw(ctx, &arg_flw);
+#else
+/* C.LDSP */
+arg_ld arg_ld =

[Qemu-devel] [PULL 21/34] target/riscv: Remove manual decoding from gen_load()

[Palmer Dabbelt]

From: Bastian Koppelmann 

With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 35 +++--
 target/riscv/translate.c|  6 +++--
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index ae4b0a2bcb78..cc361ed4d151 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 return gen_branch(ctx, a, TCG_COND_GEU);
 }
 
-static bool trans_lb(DisasContext *ctx, arg_lb *a)
+static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
 {
-gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+TCGv t0 = tcg_temp_new();
+TCGv t1 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+tcg_gen_addi_tl(t0, t0, a->imm);
+
+tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+gen_set_gpr(a->rd, t1);
+tcg_temp_free(t0);
+tcg_temp_free(t1);
 return true;
 }
 
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+return gen_load(ctx, a, MO_SB);
+}
+
 static bool trans_lh(DisasContext *ctx, arg_lh *a)
 {
-gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_TESW);
 }
 
 static bool trans_lw(DisasContext *ctx, arg_lw *a)
 {
-gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_TESL);
 }
 
 static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
 {
-gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_UB);
 }
 
 static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 {
-gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_TEUW);
 }
 
 static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
 #ifdef TARGET_RISCV64
 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
 {
-gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_TEUL);
 }
 
 static bool trans_ld(DisasContext *ctx, arg_ld *a)
 {
-gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
-return true;
+return gen_load(ctx, a, MO_TEQ);
 }
 
 static bool trans_sd(DisasContext *ctx, arg_sd *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a3d5cdbad82d..99d6d3b4ae91 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,7 +531,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong 
imm)
 ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+#ifdef TARGET_RISCV64
+static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 target_long imm)
 {
 TCGv t0 = tcg_temp_new();
@@ -550,6 +551,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int 
rd, int rs1,
 tcg_temp_free(t0);
 tcg_temp_free(t1);
 }
+#endif
 
 static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 target_long imm)
@@ -723,7 +725,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
 case 3:
 #if defined(TARGET_RISCV64)
 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
-gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
+gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
  GET_C_LD_IMM(ctx->opcode));
 #else
 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
-- 
2.18.1

[Qemu-devel] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 93 +
 target/riscv/translate.c| 59 +---
 2 files changed, 81 insertions(+), 71 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 8879f2da35c7..88ef0003ec17 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
 return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
 }
 
-static bool trans_slti(DisasContext *ctx, arg_slti *a)
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
 {
-TCGv source1;
-source1 = tcg_temp_new();
-gen_get_gpr(source1, a->rs1);
+tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
 
-tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
 
-gen_set_gpr(a->rd, source1);
-tcg_temp_free(source1);
-return true;
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+return gen_arith_imm(ctx, a, &gen_slt);
 }
 
 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 {
-TCGv source1;
-source1 = tcg_temp_new();
-gen_get_gpr(source1, a->rs1);
-
-tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
-
-gen_set_gpr(a->rd, source1);
-tcg_temp_free(source1);
-return true;
+return gen_arith_imm(ctx, a, &gen_sltu);
 }
 
 static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
 
 static bool trans_sll(DisasContext *ctx, arg_sll *a)
 {
-gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
-return true;
+return gen_shift(ctx, a, &tcg_gen_shl_tl);
 }
 
 static bool trans_slt(DisasContext *ctx, arg_slt *a)
 {
-gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_slt);
 }
 
 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 {
-gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_sltu);
 }
 
 static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
 
 static bool trans_srl(DisasContext *ctx, arg_srl *a)
 {
-gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
-return true;
+return gen_shift(ctx, a, &tcg_gen_shr_tl);
 }
 
 static bool trans_sra(DisasContext *ctx, arg_sra *a)
 {
-gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
-return true;
+return gen_shift(ctx, a, &tcg_gen_sar_tl);
 }
 
 static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
-gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 = tcg_temp_new();
+
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+tcg_gen_andi_tl(source2, source2, 0x1F);
+tcg_gen_shl_tl(source1, source1, source2);
+
+tcg_gen_ext32s_tl(source1, source1);
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
+tcg_temp_free(source2);
 return true;
 }
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
-gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 = tcg_temp_new();
+
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+/* clear upper 32 */
+tcg_gen_ext32u_tl(source1, source1);
+tcg_gen_andi_tl(source2, source2, 0x1F);
+tcg_gen_shr_tl(source1, source1, source2);
+
+tcg_gen_ext32s_tl(source1, source1);
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
+tcg_temp_free(source2);
 return true;
 }
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
-gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 = tcg_temp_new();
+
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+/*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+tcg_gen_ext32s_tl(source1, source1);
+tcg_gen_andi_tl(source2, source2, 0x1F);
+tcg_gen_sar_tl(source1, source1, source2);
+
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
+tcg_temp_free(source2);
+
 return true;
 }
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8eb883463322..9ae40f65096f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -198,47 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int 

[Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G()

[Palmer Dabbelt]

From: Bastian Koppelmann 

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/translate.c | 21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 92be090bc7bb..049fa65c6611 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,24 +651,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
 
-static void decode_RV32_64G(DisasContext *ctx)
-{
-uint32_t op;
-
-/* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
-op = MASK_OP_MAJOR(ctx->opcode);
-
-switch (op) {
-default:
-gen_exception_illegal(ctx);
-break;
-}
-}
-
 static void decode_opc(DisasContext *ctx)
 {
 /* check for compressed insn */
@@ -685,8 +667,7 @@ static void decode_opc(DisasContext *ctx)
 } else {
 ctx->pc_succ_insn = ctx->base.pc_next + 4;
 if (!decode_insn32(ctx, ctx->opcode)) {
-/* fallback to old decoder */
-decode_RV32_64G(ctx);
+gen_exception_illegal(ctx);
 }
 }
 }
-- 
2.18.1

[Qemu-devel] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn16.decode  | 20 ++--
 target/riscv/insn32.decode  |  3 ++-
 target/riscv/insn_trans/trans_rvc.inc.c | 24 
 3 files changed, 12 insertions(+), 35 deletions(-)

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c7a58d80e5ae..c215867ff947 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -43,14 +43,14 @@
 
 # Argument sets imported from insn32.decode:
 &r rd rs1 rs2   !extern
+&i imm rs1 rd   !extern
+&s imm rs1 rs2  !extern
 
 # Argument sets:
 &cl   rs1 rd
-&cl_dw uimm   rs1 rd
 &ciimmrd
 &ciw   nzuimm rd
 &cs   rs1 rs2
-&cs_dw uimm   rs1 rs2
 &cbimmrs1
 &cr   rd  rs2
 &c_j   imm
@@ -67,13 +67,13 @@
 @cr  . .  .. &cr  rs2=%rs2_5  %rd
 @ci... . . .  .. &ci imm=%imm_ci  %rd
 @ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
-@cl_d  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
-@cl_w  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
+@cl_d  ... ... ... .. ... .. &i  imm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
+@cl_w  ... ... ... .. ... .. &i  imm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
 @cl... ... ... .. ... .. &cl  rs1=%rs1_3  rd=%rs2_3
 @cs... ... ... .. ... .. &cs  rs1=%rs1_3  
rs2=%rs2_3
 @cs_2  ... ... ... .. ... .. &r  rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
-@cs_d  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  
rs2=%rs2_3
-@cs_w  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  
rs2=%rs2_3
+@cs_d  ... ... ... .. ... .. &s  imm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
+@cs_w  ... ... ... .. ... .. &s  imm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
 @cb... ... ... .. ... .. &cb imm=%imm_cb  rs1=%rs1_3
 @cj...... .. &c_jimm=%imm_cj
 
@@ -95,11 +95,11 @@
 
 # *** RV64C Standard Extension (Quadrant 0) ***
 c_addi4spn000 ... 00 @ciw
-c_fld 001  ... ... .. ... 00 @cl_d
-c_lw  010  ... ... .. ... 00 @cl_w
+fld   001  ... ... .. ... 00 @cl_d
+lw010  ... ... .. ... 00 @cl_w
 c_flw_ld  011  --- ... -- ... 00 @cl#Note: Must parse uimm manually
-c_fsd 101  ... ... .. ... 00 @cs_d
-c_sw  110  ... ... .. ... 00 @cs_w
+fsd   101  ... ... .. ... 00 @cs_d
+sw110  ... ... .. ... 00 @cs_w
 c_fsw_sd  111  --- ... -- ... 00 @cs#Note: Must parse uimm manually
 
 # *** RV64C Standard Extension (Quadrant 1) ***
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52d3..b59a00cc429f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -37,6 +37,7 @@
 &bimm rs2 rs1
 &iimm rs1 rd
 &rrd rs1 rs2
+&simm rs2 rs1
 &shift shamt rs1 rd
 &atomicaq rl rs2 rs1 rd
 
@@ -44,7 +45,7 @@
 @r   ...   . . ... . ... &r%rs2 %rs1 
%rd
 @i   . ... . ... &i  imm=%imm_i %rs1 
%rd
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
-@s   ...   . . ... . ... imm=%imm_s %rs2 %rs1
+@s   ...   . . ... . ... &s  imm=%imm_s %rs2 %rs1
 @u     . ... imm=%imm_u  
%rd
 @j     . ... imm=%imm_j  
%rd
 
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index 639c381edfc0..d932bfd3e0cc 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, 
arg_c_addi4spn *a)
 return trans_addi(ctx, &arg);
 }
 
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
-arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
-return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
-arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
-return trans_lw(ctx, &arg);
-}
-
 static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
 {
 #ifdef TARGET_RISCV32
@@ -51,18 +39,6 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld 
*a)
 #endif
 }
 
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
-arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
-return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
-arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };

[Qemu-devel] [PULL 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64

[Palmer Dabbelt]

From: Bastian Koppelmann 

it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn16-32.decode   |  7 +
 target/riscv/insn16-64.decode   |  5 
 target/riscv/insn16.decode  | 12 ++--
 target/riscv/insn32.decode  |  3 +-
 target/riscv/insn_trans/trans_rvc.inc.c | 40 -
 5 files changed, 16 insertions(+), 51 deletions(-)

diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
index e21a701056f1..978b8d5834ee 100644
--- a/target/riscv/insn16-32.decode
+++ b/target/riscv/insn16-32.decode
@@ -22,3 +22,10 @@
 # *** RV32C Standard Extension (Quadrant 0) ***
 flw 011 ... ... .. ... 00   @cl_w
 fsw 111 ... ... .. ... 00   @cs_w
+
+# *** RV32C Standard Extension (Quadrant 1) ***
+jal 001 ..   . 01   &j imm=%imm_cj rd=1
+
+# *** RV32C Standard Extension (Quadrant 2) ***
+flw 011 . .  . 10   &i imm=%uimm_6bit_lw %rd rs1=2
+fsw 111 ..   . 10   &s imm=%uimm_6bit_sw rs2=2 rs1=%rs2_5
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index de97a45acf4b..d43055837a79 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -24,5 +24,10 @@ ld  011  ... ... .. ... 00 @cl_d
 sd  111  ... ... .. ... 00 @cs_d
 
 # *** RV64C Standard Extension (Quadrant 1) ***
+addiw 001 .  .  . 01 @ci
 subw  100 1 11 ... 00 ... 01 @cs_2
 addw  100 1 11 ... 01 ... 01 @cs_2
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+ld  011 .  .  . 10 &i imm=%uimm_6bit_ld %rd rs1=2
+sd  111 ... 10 &s imm=%uimm_6bit_sd rs2=%rs2_5 rs1=2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index b0753360626b..98dd672c7f59 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -45,6 +45,7 @@
 &r rd rs1 rs2   !extern
 &i imm rs1 rd   !extern
 &s imm rs1 rs2  !extern
+&j imm rd   !extern
 
 # Argument sets:
 &ciimmrd
@@ -59,12 +60,10 @@
 &c_sd  uimm  rs2
 
 &c_addi16sp_lui  imm_lui imm_addi16sp rd
-&c_flwsp_ldspuimm_flwsp uimm_ldsp rd
-&c_fswsp_sdspuimm_fswsp uimm_sdsp rs2
 
 # Formats 16:
 @cr  . .  .. &cr  rs2=%rs2_5  %rd
-@ci... . . .  .. &ci imm=%imm_ci  %rd
+@ci... . . .  .. &i  imm=%imm_ci %rd rs1=%rd
 @ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
 @cl_d  ... ... ... .. ... .. &i  imm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
 @cl_w  ... ... ... .. ... .. &i  imm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
@@ -80,10 +79,6 @@
 @c_sw  ... . .  . .. &c_sd uimm=%uimm_6bit_sw  rs2=%rs2_5
 
 @c_addi16sp_lui ... .  . . .. &c_addi16sp_lui %imm_lui %imm_addi16sp 
%rd
-@c_flwsp_ldsp   ... .  . . .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
-uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp   ... .  . . .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
-uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
 
 @c_shift... . .. ... . .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
 @c_shift2   ... . .. ... . .. &c_shift rd=%rdshamt=%nzuimm_6bit
@@ -99,7 +94,6 @@ sw110  ... ... .. ... 00 @cs_w
 
 # *** RV64C Standard Extension (Quadrant 1) ***
 c_addi000 .  .  . 01 @ci
-c_jal_addiw   001 .  .  . 01 @ci #Note: parse rd and/or imm 
manually
 c_li  010 .  .  . 01 @ci
 c_addi16sp_lui011 .  .  . 01 @c_addi16sp_lui # shares opc with 
C.LUI
 c_srli100 . 00 ...  . 01 @c_shift
@@ -117,9 +111,7 @@ c_bnez111  ... ...  . 01 @cb
 c_slli000 .  .  . 10 @c_shift2
 c_fldsp   001 .  .  . 10 @c_ld
 c_lwsp010 .  .  . 10 @c_lw
-c_flwsp_ldsp  011 .  .  . 10 @c_flwsp_ldsp 
#C.LDSP:RV64;C.FLWSP:RV32
 c_jr_mv   100 0  .  . 10 @cr
 c_ebreak_jalr_add 100 1  .  . 10 @cr
 c_fsdsp   101   ..  . 10 @c_sd
 c_swsp110 .  .  . 10 @c_sw
-c_fswsp_sdsp  111 .  .  . 10 @c_fswsp_sdsp 
#C.SDSP:RV64;C.FSWSP:RV32
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b59a00cc429f..0e098e05fe78 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -38,6 +38,7 @@
 &iimm rs1 rd
 &rrd rs1 rs2
 &simm rs2 rs1
+&jimm rd
 &shift shamt rs1 rd
 &atomicaq rl rs2 rs1 rd
 
@@ -47,7 +48,7 @@
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
 @s   ...   . . ... . ... &s  imm=%imm_s %rs2 %rs1
 @u     . ... imm=%imm

[Qemu-devel] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64

[Palmer Dabbelt]

From: Bastian Koppelmann 

this finally removes the old decoder functions that we carried along
with it.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs  |   1 +
 target/riscv/insn16-32.decode   |  24 
 target/riscv/insn16-64.decode   |   4 +
 target/riscv/insn16.decode  |   7 +-
 target/riscv/insn_trans/trans_rvc.inc.c |  22 ---
 target/riscv/translate.c| 181 +---
 6 files changed, 31 insertions(+), 208 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 990bd8901623..a31a9ea061dd 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -6,6 +6,7 @@ decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
 decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
 
 decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
 decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
 
 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index ..e21a701056f1
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+#Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see .
+
+# This is concatenated with insn16.decode for risc32 targets.
+# All of the fields and formats are there.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00   @cl_w
+fsw 111 ... ... .. ... 00   @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 5af2e2b0728d..de97a45acf4b 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -19,6 +19,10 @@
 # This is concatenated with insn16.decode for risc64 targets.
 # All of the fields and formats are there.
 
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld  011  ... ... .. ... 00 @cl_d
+sd  111  ... ... .. ... 00 @cs_d
+
 # *** RV64C Standard Extension (Quadrant 1) ***
 subw  100 1 11 ... 00 ... 01 @cs_2
 addw  100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index c215867ff947..b0753360626b 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -47,10 +47,9 @@
 &s imm rs1 rs2  !extern
 
 # Argument sets:
-&cl   rs1 rd
 &ciimmrd
 &ciw   nzuimm rd
-&cs   rs1 rs2
+&cs_dw uimm   rs1 rs2
 &cbimmrs1
 &cr   rd  rs2
 &c_j   imm
@@ -69,8 +68,6 @@
 @ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
 @cl_d  ... ... ... .. ... .. &i  imm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
 @cl_w  ... ... ... .. ... .. &i  imm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
-@cl... ... ... .. ... .. &cl  rs1=%rs1_3  rd=%rs2_3
-@cs... ... ... .. ... .. &cs  rs1=%rs1_3  
rs2=%rs2_3
 @cs_2  ... ... ... .. ... .. &r  rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
 @cs_d  ... ... ... .. ... .. &s  imm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
 @cs_w  ... ... ... .. ... .. &s  imm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
@@ -97,10 +94,8 @@
 c_addi4spn000 ... 00 @ciw
 fld   001  ... ... .. ... 00 @cl_d
 lw010  ... ... .. ... 00 @cl_w
-c_flw_ld  011  --- ... -- ... 00 @cl#Note: Must parse uimm manually
 fsd   101  ... ... .. ... 00 @cs_d
 sw110  ... ... .. ... 00 @cs_w
-c_fsw_sd  111  --- ... -- ... 00 @cs#Note: Must parse uimm manually
 
 # *** RV64C Standard Extension (Quadrant 1) ***
 c_addi000 .  .  . 01 @ci
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index d932bfd3e0cc..f521daf32e55 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, 
arg_c_addi4spn *a)
 return trans_addi(ctx, &ar

[Qemu-devel] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions

[Palmer Dabbelt]

From: Bastian Koppelmann 

These all expand simply to R format instructions.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs  | 10 +++---
 target/riscv/insn16-64.decode   | 24 ++
 target/riscv/insn16.decode  | 15 +
 target/riscv/insn_trans/trans_rvc.inc.c | 44 -
 target/riscv/translate.c| 20 ---
 5 files changed, 54 insertions(+), 59 deletions(-)
 create mode 100644 target/riscv/insn16-64.decode

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c1093271e..990bd8901623 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -5,16 +5,18 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
 decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
 
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
  "GEN", $(TARGET_DIR)$@)
 
-target/riscv/decode_insn16.inc.c: \
-  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 
$<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 \
+ $(decode16-y), "GEN", $(TARGET_DIR)$@)
 
 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
new file mode 100644
index ..5af2e2b0728d
--- /dev/null
+++ b/target/riscv/insn16-64.decode
@@ -0,0 +1,24 @@
+#
+# RISC-V translation routines for the RVC Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+#Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see .
+
+# This is concatenated with insn16.decode for risc64 targets.
+# All of the fields and formats are there.
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+subw  100 1 11 ... 00 ... 01 @cs_2
+addw  100 1 11 ... 01 ... 01 @cs_2
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc592d..c7a58d80e5ae 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -41,6 +41,9 @@
 
 
 
+# Argument sets imported from insn32.decode:
+&r rd rs1 rs2   !extern
+
 # Argument sets:
 &cl   rs1 rd
 &cl_dw uimm   rs1 rd
@@ -68,7 +71,7 @@
 @cl_w  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
 @cl... ... ... .. ... .. &cl  rs1=%rs1_3  rd=%rs2_3
 @cs... ... ... .. ... .. &cs  rs1=%rs1_3  
rs2=%rs2_3
-@cs_2  ... ... ... .. ... .. &cr  rd=%rs1_3   
rs2=%rs2_3
+@cs_2  ... ... ... .. ... .. &r  rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
 @cs_d  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  
rs2=%rs2_3
 @cs_w  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  
rs2=%rs2_3
 @cb... ... ... .. ... .. &cb imm=%imm_cb  rs1=%rs1_3
@@ -107,12 +110,10 @@ c_addi16sp_lui011 .  .  . 01 @c_addi16sp_lui 
# shares opc with C.LUI
 c_srli100 . 00 ...  . 01 @c_shift
 c_srai100 . 01 ...  . 01 @c_shift
 c_andi100 . 10 ...  . 01 @c_andi
-c_sub 100 0 11 ... 00 ... 01 @cs_2
-c_xor 100 0 11 ... 01 ... 01 @cs_2
-c_or  100 0 11 ... 10 ... 01 @cs_2
-c_and 100 0 11 ... 11 ... 01 @cs_2
-c_subw100 1 11 ... 00 ... 01 @cs_2
-c_addw100 1 11 ... 01 ... 01 @cs_2
+sub   100 0 11 ... 00 ... 01 @cs_2
+xor   100 0 11 ... 01 ... 01 @cs_2
+or100 0 11 ... 10 ... 01 @cs_2
+and   100 0 11 ... 11 ... 01 @cs_2
 c_j   101 ... 01 @cj
 c_beqz110  ... ...  . 01 @cb
 c_bnez111  ... ...  . 01 @cb
diff --git a/target/riscv/

[Qemu-devel] [PULL 19/34] target/riscv: Remove gen_jalr()

[Palmer Dabbelt]

From: Bastian Koppelmann 

trans_jalr() is the only caller, so move the code into trans_jalr().

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 28 +-
 target/riscv/translate.c| 38 -
 2 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 4a23372cb823..631a88906bce 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
 
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
-gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+/* no chaining with JALR */
+TCGLabel *misaligned = NULL;
+TCGv t0 = tcg_temp_new();
+
+
+gen_get_gpr(cpu_pc, a->rs1);
+tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+if (!has_ext(ctx, RVC)) {
+misaligned = gen_new_label();
+tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+}
+
+if (a->rd != 0) {
+tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+}
+tcg_gen_lookup_and_goto_ptr();
+
+if (misaligned) {
+gen_set_label(misaligned);
+gen_exception_inst_addr_mis(ctx);
+}
+ctx->base.is_jmp = DISAS_NORETURN;
+
+tcg_temp_free(t0);
 return true;
 }
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 80afa2c1e62b..9dee2ec24287 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,44 +531,6 @@ static void gen_jal(DisasContext *ctx, int rd, 
target_ulong imm)
 ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
-/* no chaining with JALR */
-TCGLabel *misaligned = NULL;
-TCGv t0 = tcg_temp_new();
-
-switch (opc) {
-case OPC_RISC_JALR:
-gen_get_gpr(cpu_pc, rs1);
-tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
-tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
-if (!has_ext(ctx, RVC)) {
-misaligned = gen_new_label();
-tcg_gen_andi_tl(t0, cpu_pc, 0x2);
-tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
-}
-
-if (rd != 0) {
-tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
-}
-tcg_gen_lookup_and_goto_ptr();
-
-if (misaligned) {
-gen_set_label(misaligned);
-gen_exception_inst_addr_mis(ctx);
-}
-ctx->base.is_jmp = DISAS_NORETURN;
-break;
-
-default:
-gen_exception_illegal(ctx);
-break;
-}
-tcg_temp_free(t0);
-}
-
 static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm)
 {
-- 
2.18.1

[Qemu-devel] [PULL 28/34] target/riscv: Remove gen_system()

[Palmer Dabbelt]

From: Bastian Koppelmann 

with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/translate.c | 34 --
 1 file changed, 34 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index dedf4189d5b7..92be090bc7bb 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -473,33 +473,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
 tcg_temp_free_i32(t0);
 }
 
-static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-   int csr)
-{
-tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
-switch (opc) {
-case OPC_RISC_ECALL:
-switch (csr) {
-case 0x0: /* ECALL */
-/* always generates U-level ECALL, fixed in do_interrupt handler */
-generate_exception(ctx, RISCV_EXCP_U_ECALL);
-tcg_gen_exit_tb(NULL, 0); /* no chaining */
-ctx->base.is_jmp = DISAS_NORETURN;
-break;
-case 0x1: /* EBREAK */
-generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-tcg_gen_exit_tb(NULL, 0); /* no chaining */
-ctx->base.is_jmp = DISAS_NORETURN;
-break;
-default:
-gen_exception_illegal(ctx);
-break;
-}
-break;
-}
-}
-
 static void decode_RV32_64C0(DisasContext *ctx)
 {
 uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -680,7 +653,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
 
 static void decode_RV32_64G(DisasContext *ctx)
 {
-int rs1, rd;
 uint32_t op;
 
 /* We do not do misaligned address check here: the address should never be
@@ -689,14 +661,8 @@ static void decode_RV32_64G(DisasContext *ctx)
  * perform the misaligned instruction fetch */
 
 op = MASK_OP_MAJOR(ctx->opcode);
-rs1 = GET_RS1(ctx->opcode);
-rd = GET_RD(ctx->opcode);
 
 switch (op) {
-case OPC_RISC_SYSTEM:
-gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
-   (ctx->opcode & 0xFFF0) >> 20);
-break;
 default:
 gen_exception_illegal(ctx);
 break;
-- 
2.18.1

[Qemu-devel] [PULL 22/34] target/riscv: Remove manual decoding from gen_store()

[Palmer Dabbelt]

From: Bastian Koppelmann 

With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 27 +
 target/riscv/translate.c|  8 +---
 2 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index cc361ed4d151..5a09c6335ae0 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 return gen_load(ctx, a, MO_TEUW);
 }
 
-static bool trans_sb(DisasContext *ctx, arg_sb *a)
+static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
 {
-gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+TCGv t0 = tcg_temp_new();
+TCGv dat = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+tcg_gen_addi_tl(t0, t0, a->imm);
+gen_get_gpr(dat, a->rs2);
+
+tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+tcg_temp_free(t0);
+tcg_temp_free(dat);
 return true;
 }
 
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+return gen_store(ctx, a, MO_SB);
+}
+
 static bool trans_sh(DisasContext *ctx, arg_sh *a)
 {
-gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
-return true;
+return gen_store(ctx, a, MO_TESW);
 }
 
 static bool trans_sw(DisasContext *ctx, arg_sw *a)
 {
-gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
-return true;
+return gen_store(ctx, a, MO_TESL);
 }
 
 #ifdef TARGET_RISCV64
@@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
 
 static bool trans_sd(DisasContext *ctx, arg_sd *a)
 {
-gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
-return true;
+return gen_store(ctx, a, MO_TEQ);
 }
 #endif
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 99d6d3b4ae91..cdc08b1bff20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
 int frm;
 } DisasContext;
 
+#ifdef TARGET_RISCV64
 /* convert riscv funct3 to qemu memop for load/store */
 static const int tcg_memop_lookup[8] = {
 [0 ... 7] = -1,
@@ -69,6 +70,7 @@ static const int tcg_memop_lookup[8] = {
 [6] = MO_TEUL,
 #endif
 };
+#endif
 
 #ifdef TARGET_RISCV64
 #define CASE_OP_32_64(X) case X: case glue(X, W)
@@ -551,9 +553,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int 
rd, int rs1,
 tcg_temp_free(t0);
 tcg_temp_free(t1);
 }
-#endif
 
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 target_long imm)
 {
 TCGv t0 = tcg_temp_new();
@@ -572,6 +573,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int 
rs1, int rs2,
 tcg_temp_free(t0);
 tcg_temp_free(dat);
 }
+#endif
 
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
@@ -736,7 +738,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
 case 7:
 #if defined(TARGET_RISCV64)
 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
-gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
   GET_C_LD_IMM(ctx->opcode));
 #else
 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
-- 
2.18.1

[Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
 target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
 target/riscv/translate.c|  4 ++--
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 88ef0003ec17..d420a4d8b2e9 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
 {
-return trans_arith(ctx, a, &tcg_gen_add_tl);
+return gen_arith(ctx, a, &tcg_gen_add_tl);
 }
 
 static bool trans_sub(DisasContext *ctx, arg_sub *a)
 {
-return trans_arith(ctx, a, &tcg_gen_sub_tl);
+return gen_arith(ctx, a, &tcg_gen_sub_tl);
 }
 
 static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
 
 static bool trans_slt(DisasContext *ctx, arg_slt *a)
 {
-return trans_arith(ctx, a, &gen_slt);
+return gen_arith(ctx, a, &gen_slt);
 }
 
 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 {
-return trans_arith(ctx, a, &gen_sltu);
+return gen_arith(ctx, a, &gen_sltu);
 }
 
 static bool trans_xor(DisasContext *ctx, arg_xor *a)
 {
-return trans_arith(ctx, a, &tcg_gen_xor_tl);
+return gen_arith(ctx, a, &tcg_gen_xor_tl);
 }
 
 static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
 
 static bool trans_or(DisasContext *ctx, arg_or *a)
 {
-return trans_arith(ctx, a, &tcg_gen_or_tl);
+return gen_arith(ctx, a, &tcg_gen_or_tl);
 }
 
 static bool trans_and(DisasContext *ctx, arg_and *a)
 {
-return trans_arith(ctx, a, &tcg_gen_and_tl);
+return gen_arith(ctx, a, &tcg_gen_and_tl);
 }
 
 #ifdef TARGET_RISCV64
@@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
-return trans_arith(ctx, a, &gen_addw);
+return gen_arith(ctx, a, &gen_addw);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
-return trans_arith(ctx, a, &gen_subw);
+return gen_arith(ctx, a, &gen_subw);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c 
b/target/riscv/insn_trans/trans_rvm.inc.c
index d2bf2f171904..204af225f8f3 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -22,7 +22,7 @@
 static bool trans_mul(DisasContext *ctx, arg_mul *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &tcg_gen_mul_tl);
+return gen_arith(ctx, a, &tcg_gen_mul_tl);
 }
 
 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -44,7 +44,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_mulhsu);
+return gen_arith(ctx, a, &gen_mulhsu);
 }
 
 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -66,32 +66,32 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
 static bool trans_div(DisasContext *ctx, arg_div *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_div);
+return gen_arith(ctx, a, &gen_div);
 }
 
 static bool trans_divu(DisasContext *ctx, arg_divu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_divu);
+return gen_arith(ctx, a, &gen_divu);
 }
 
 static bool trans_rem(DisasContext *ctx, arg_rem *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_rem);
+return gen_arith(ctx, a, &gen_rem);
 }
 
 static bool trans_remu(DisasContext *ctx, arg_remu *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_remu);
+return gen_arith(ctx, a, &gen_remu);
 }
 
 #ifdef TARGET_RISCV64
 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
 REQUIRE_EXT(ctx, RVM);
-return trans_arith(ctx, a, &gen_mulw);
+return gen_arith(ctx, a, &gen_mulw);
 }
 
 static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3cd7e16c63cf..dedf4189d5b7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -629,8 +629,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
 
 #endif
 
-static bool trans_arith(DisasContext *ctx, arg_r *a,
-void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+  void(*func)(TCGv, TCGv, TCGv))
 {
 TCGv source1, source2;
 source1 = tcg_temp_new();
-- 
2.18.1

[Qemu-devel] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode|  15 +++
 .../riscv/insn_trans/trans_privileged.inc.c   | 110 ++
 target/riscv/translate.c  |  57 +
 3 files changed, 126 insertions(+), 56 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e64b2b5e3458..ecc46a50cc27 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -57,6 +57,21 @@
 @r2_rm   ...   . . ... . ... %rs1 %rm %rd
 @r2  ...   . . ... . ... %rs1 %rd
 
+@sfence_vma ... . .   ... . ... %rs2 %rs1
+@sfence_vm  ... . .   ... . ... %rs1
+
+
+# *** Privileged Instructions ***
+ecall   0 000 0 1110011
+ebreak 0001 0 000 0 1110011
+uret   00000010 0 000 0 1110011
+sret   000100000010 0 000 0 1110011
+hret   00100010 0 000 0 1110011
+mret   001100000010 0 000 0 1110011
+wfi000100000101 0 000 0 1110011
+sfence_vma 0001001. . 000 0 1110011 @sfence_vma
+sfence_vm  000100000100 . 000 0 1110011 @sfence_vm
+
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
 auipc   . 0010111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c 
b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index ..acb605923e68
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,110 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+/* always generates U-level ECALL, fixed in do_interrupt handler */
+generate_exception(ctx, RISCV_EXCP_U_ECALL);
+tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ctx->base.is_jmp = DISAS_NORETURN;
+return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ctx->base.is_jmp = DISAS_NORETURN;
+return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+if (has_ext(ctx, RVS)) {
+gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ctx->base.is_jmp = DISAS_NORETURN;
+} else {
+return false;
+}
+return true;
+#else
+return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a)
+{
+return false;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ctx->base.is_jmp = DISAS_NORETURN;
+return true;
+#else
+return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+gen_helper_wfi(cpu_env);
+return true;
+#else
+return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+gen_helper_tlb_flush(cpu_env);
+return true;
+}
+#endif
+return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+#ifndef CONFIG_USER_ONLY
+if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
+gen_helper_tlb_flush(cpu_env);
+return true;
+}
+#endif
+return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com -> 
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Switched to a new branch 'test'
73739b0cc6 s390-bios: dasd-ipl: Use control unit type to customize error data
870492 s390-bios: Support booting from real dasd device
5a5c4b01ef s390-bios: Add channel command codes/structs needed for dasd-ipl
d23ff47a3d s390-bios: Use control unit type to determine boot method
2af24581b4 s390-bios: Refactor virtio to run channel programs via cio
631002c644 s390-bios: cio error handling
44d5259870 s390-bios: Support for running format-0/1 channel programs
7244df5a79 s390-bios: ptr2u32 and u32toptr
af222f5618 s390-bios: Map low core memory
281f64b37a s390-bios: Decouple channel i/o logic from virtio
4ac96c2c10 s390-bios: Clean up cio.h
06ea714695 s390-bios: Factor finding boot device out of virtio code path
a99947c33d s390-bios: Extend find_dev() for non-virtio devices
9b82cabb3b s390-bios: decouple common boot logic from virtio
2e4c88a8ae s390-bios: decouple cio setup from virtio
648c3648c7 s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit 648c3648c73b (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit 2e4c88a8ae84 (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 9b82cabb3b40 (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit a99947c33d4a (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit 06ea71469510 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit 4ac96c2c105e (s390-bios: Clean up cio.h)
7/16 Checking commit 281f64b37a69 (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit af222f561810 (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit 7244df5a79fa (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit 44d52598706f (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit 631002c64417 (s390-bios: cio error handling)
12/16 Checking commit 2af24581b441 (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit d23ff47a3d3c (s390-b

[Qemu-devel] [PULL 14/34] target/riscv: Convert RV64D insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32-64.decode   |   8 +
 target/riscv/insn_trans/trans_rvd.inc.c |  82 
 target/riscv/translate.c| 601 +---
 3 files changed, 91 insertions(+), 600 deletions(-)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6319f872ac1d..380bf791bcdc 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -62,3 +62,11 @@ fcvt_l_s   110  00010 . ... . 1010011 @r2_rm
 fcvt_lu_s  110  00011 . ... . 1010011 @r2_rm
 fcvt_s_l   1101000  00010 . ... . 1010011 @r2_rm
 fcvt_s_lu  1101000  00011 . ... . 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d   111  00010 . ... . 1010011 @r2_rm
+fcvt_lu_d  111  00011 . ... . 1010011 @r2_rm
+fmv_x_d1110001  0 . 000 . 1010011 @r2
+fcvt_d_l   1101001  00010 . ... . 1010011 @r2_rm
+fcvt_d_lu  1101001  00011 . ... . 1010011 @r2_rm
+fmv_d_x001  0 . 000 . 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c 
b/target/riscv/insn_trans/trans_rvd.inc.c
index 98fc1cdc5a20..393fa0248ce9 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -358,3 +358,85 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, 
arg_fcvt_d_wu *a)
 mark_fs_dirty(ctx);
 return true;
 }
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+TCGv t0 = tcg_temp_new();
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+gen_set_gpr(a->rd, t0);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+TCGv t0 = tcg_temp_new();
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+gen_set_gpr(a->rd, t0);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+tcg_temp_free(t0);
+mark_fs_dirty(ctx);
+return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+tcg_temp_free(t0);
+mark_fs_dirty(ctx);
+return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVD);
+
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+
+tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+tcg_temp_free(t0);
+mark_fs_dirty(ctx);
+return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c201985ef37b..2e36deee82f4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -186,44 +186,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 tcg_temp_free(rh);
 }
 
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
-uint32_t rs2, int rm, uint64_t min)
-{
-switch (rm) {
-case 0: /* fsgnj */
-if (rs1 == rs2) { /* FMOV */
-tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
-} else {
-tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
-0, min == INT32_MIN ? 31 : 63);
-}
-break;
-case 1: /* fsgnjn */
-if (rs1 == rs2) { /* FNEG */
-tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
-} else {
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_not_i64(t0, cpu_fpr[rs2]);
-tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
-0, min == INT32_MIN ? 31 : 63);
-tcg_temp_free_i64(t0);
-}
-break;
-case 2: /* fsgnjx */
-if (rs1 == rs2) { /* FABS */
-tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
-} else {
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
-tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
-tcg_temp_free_i64(t0);
-}
-break;
-default:
-gen_exception_illegal(ctx);
-}
-}
-
 static void gen_arith(Di

[Qemu-devel] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

[Palmer Dabbelt]

From: Bastian Koppelmann 

manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  3 +-
 target/riscv/insn_trans/trans_rvi.inc.c | 21 +
 target/riscv/translate.c| 40 +++--
 3 files changed, 34 insertions(+), 30 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6b4197841f5..6f3ab7aa52d3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,11 +36,12 @@
 # Argument sets:
 &bimm rs2 rs1
 &iimm rs1 rd
+&rrd rs1 rs2
 &shift shamt rs1 rd
 &atomicaq rl rs2 rs1 rd
 
 # Formats 32:
-@r   ...   . . ... . ...   %rs2 %rs1 
%rd
+@r   ...   . . ... . ... &r%rs2 %rs1 
%rd
 @i   . ... . ... &i  imm=%imm_i %rs1 
%rd
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
 @s   ...   . . ... . ... imm=%imm_s %rs2 %rs1
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 0265740bdb69..8879f2da35c7 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
 {
-gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_add_tl);
 }
 
 static bool trans_sub(DisasContext *ctx, arg_sub *a)
 {
-gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_sub_tl);
 }
 
 static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 
 static bool trans_xor(DisasContext *ctx, arg_xor *a)
 {
-gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_xor_tl);
 }
 
 static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
 
 static bool trans_or(DisasContext *ctx, arg_or *a)
 {
-gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_or_tl);
 }
 
 static bool trans_and(DisasContext *ctx, arg_and *a)
 {
-gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &tcg_gen_and_tl);
 }
 
 #ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
-gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_addw);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
-gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
-return true;
+return trans_arith(ctx, a, &gen_subw);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0157758a160a..8eb883463322 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -198,12 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int 
rd, int rs1,
 gen_get_gpr(source2, rs2);
 
 switch (opc) {
-CASE_OP_32_64(OPC_RISC_ADD):
-tcg_gen_add_tl(source1, source1, source2);
-break;
-CASE_OP_32_64(OPC_RISC_SUB):
-tcg_gen_sub_tl(source1, source1, source2);
-break;
 #if defined(TARGET_RISCV64)
 case OPC_RISC_SLLW:
 tcg_gen_andi_tl(source2, source2, 0x1F);
@@ -220,9 +214,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int 
rd, int rs1,
 case OPC_RISC_SLTU:
 tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
 break;
-case OPC_RISC_XOR:
-tcg_gen_xor_tl(source1, source1, source2);
-break;
 #if defined(TARGET_RISCV64)
 case OPC_RISC_SRLW:
 /* clear upper 32 */
@@ -248,12 +239,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int 
rd, int rs1,
 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
 tcg_gen_sar_tl(source1, source1, source2);
 break;
-case OPC_RISC_OR:
-tcg_gen_or_tl(source1, source1, source2);
-break;
-case OPC_RISC_AND:
-tcg_gen_and_tl(source1, source1, source2);
-break;
 CASE_OP_32_64(OPC_RISC_MUL):
 if (!has_ext(ctx, RVM)) {
 goto do_illegal;
@@ -730,8 +715,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 tcg

[Qemu-devel] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32-64.decode   |  6 +++
 target/riscv/insn_trans/trans_rvf.inc.c | 60 +
 2 files changed, 66 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c9840d..6319f872ac1d 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d   1 . . . . 011 . 010 @atom_st
 amomax_d   10100 . . . . 011 . 010 @atom_st
 amominu_d  11000 . . . . 011 . 010 @atom_st
 amomaxu_d  11100 . . . . 011 . 010 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s   110  00010 . ... . 1010011 @r2_rm
+fcvt_lu_s  110  00011 . ... . 1010011 @r2_rm
+fcvt_s_l   1101000  00010 . ... . 1010011 @r2_rm
+fcvt_s_lu  1101000  00011 . ... . 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c 
b/target/riscv/insn_trans/trans_rvf.inc.c
index 0f837903491b..172dbfa919b6 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -377,3 +377,63 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x 
*a)
 
 return true;
 }
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+TCGv t0 = tcg_temp_new();
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+gen_set_gpr(a->rd, t0);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+TCGv t0 = tcg_temp_new();
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+gen_set_gpr(a->rd, t0);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+mark_fs_dirty(ctx);
+tcg_temp_free(t0);
+return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+
+gen_set_rm(ctx, a->rm);
+gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+mark_fs_dirty(ctx);
+tcg_temp_free(t0);
+return true;
+}
+#endif
-- 
2.18.1

[Qemu-devel] [PULL 11/34] target/riscv: Convert RV32F insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  35 +++
 target/riscv/insn_trans/trans_rvf.inc.c | 379 
 target/riscv/translate.c|   1 +
 3 files changed, 415 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 00b9e2d9a508..e40836bf032f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,12 +17,14 @@
 # this program.  If not, see .
 
 # Fields:
+%rs3   27:5
 %rs2   20:5
 %rs1   15:5
 %rd7:5
 
 %sh1020:10
 %csr20:12
+%rm 12:3
 
 # immediates:
 %imm_i20:s12
@@ -50,6 +52,11 @@
 @atom_ld . aq:1 rl:1 .  . ... &atomic rs2=0 %rs1 
%rd
 @atom_st . aq:1 rl:1 .  . ... &atomic %rs2  %rs1 
%rd
 
+@r4_rm   . ..  . . ... . ... %rs3 %rs2 %rs1 %rm %rd
+@r_rm...   . . ... . ... %rs2 %rs1 %rm %rd
+@r2_rm   ...   . . ... . ... %rs1 %rm %rd
+@r2  ...   . . ... . ... %rs1 %rd
+
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
 auipc   . 0010111 @u
@@ -119,3 +126,31 @@ amomin_w   1 . . . . 010 . 010 @atom_st
 amomax_w   10100 . . . . 010 . 010 @atom_st
 amominu_w  11000 . . . . 010 . 010 @atom_st
 amomaxu_w  11100 . . . . 010 . 010 @atom_st
+
+# *** RV32F Standard Extension ***
+flw   . 010 . 111 @i
+fsw...  . . 010 . 0100111 @s
+fmadd_s. 00 . . ... . 111 @r4_rm
+fmsub_s. 00 . . ... . 1000111 @r4_rm
+fnmsub_s   . 00 . . ... . 1001011 @r4_rm
+fnmadd_s   . 00 . . ... . 100 @r4_rm
+fadd_s 000  . . ... . 1010011 @r_rm
+fsub_s 100  . . ... . 1010011 @r_rm
+fmul_s 0001000  . . ... . 1010011 @r_rm
+fdiv_s 0001100  . . ... . 1010011 @r_rm
+fsqrt_s0101100  0 . ... . 1010011 @r2_rm
+fsgnj_s001  . . 000 . 1010011 @r
+fsgnjn_s   001  . . 001 . 1010011 @r
+fsgnjx_s   001  . . 010 . 1010011 @r
+fmin_s 0010100  . . 000 . 1010011 @r
+fmax_s 0010100  . . 001 . 1010011 @r
+fcvt_w_s   110  0 . ... . 1010011 @r2_rm
+fcvt_wu_s  110  1 . ... . 1010011 @r2_rm
+fmv_x_w111  0 . 000 . 1010011 @r2
+feq_s  101  . . 010 . 1010011 @r
+flt_s  101  . . 001 . 1010011 @r
+fle_s  101  . . 000 . 1010011 @r
+fclass_s   111  0 . 001 . 1010011 @r2
+fcvt_s_w   1101000  0 . ... . 1010011 @r2_rm
+fcvt_s_wu  1101000  1 . ... . 1010011 @r2_rm
+fmv_w_x000  0 . 000 . 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c 
b/target/riscv/insn_trans/trans_rvf.inc.c
new file mode 100644
index ..0f837903491b
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -0,0 +1,379 @@
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#define REQUIRE_FPU do {\
+if (ctx->mstatus_fs == 0) \
+return false;   \
+} while (0)
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a)
+{
+TCGv t0 = tcg_temp_new();
+gen_get_gpr(t0, a->rs1);
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+tcg_gen_addi_tl(t0, t0, a->imm);
+
+tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+/* RISC-V requires NaN-boxing of narrower width floating point values */
+tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xULL);
+
+tcg_temp_free(t0);
+mark_fs_dirty(ctx);
+return true;
+}
+
+static bo

[Qemu-devel] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions

[Palmer Dabbelt]

From: Bastian Koppelmann 

gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |   3 +-
 target/riscv/insn_trans/trans_rvi.inc.c |  98 +-
 target/riscv/translate.c| 107 ++--
 3 files changed, 108 insertions(+), 100 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ecc46a50cc27..d6b4197841f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,12 +35,13 @@
 
 # Argument sets:
 &bimm rs2 rs1
+&iimm rs1 rd
 &shift shamt rs1 rd
 &atomicaq rl rs2 rs1 rd
 
 # Formats 32:
 @r   ...   . . ... . ...   %rs2 %rs1 
%rd
-@i   . ... . ... imm=%imm_i %rs1 
%rd
+@i   . ... . ... &i  imm=%imm_i %rs1 
%rd
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
 @s   ...   . . ... . ... imm=%imm_s %rs2 %rs1
 @u     . ... imm=%imm_u  
%rd
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 5a09c6335ae0..0265740bdb69 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -217,52 +217,96 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
 
 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 {
-gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
-return true;
+return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
 }
 
 static bool trans_slti(DisasContext *ctx, arg_slti *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+TCGv source1;
+source1 = tcg_temp_new();
+gen_get_gpr(source1, a->rs1);
+
+tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
 return true;
 }
 
 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+TCGv source1;
+source1 = tcg_temp_new();
+gen_get_gpr(source1, a->rs1);
+
+tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+gen_set_gpr(a->rd, source1);
+tcg_temp_free(source1);
 return true;
 }
 
 static bool trans_xori(DisasContext *ctx, arg_xori *a)
 {
-gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
-return true;
+return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
 }
 static bool trans_ori(DisasContext *ctx, arg_ori *a)
 {
-gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
-return true;
+return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
 }
 static bool trans_andi(DisasContext *ctx, arg_andi *a)
 {
-gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
-return true;
+return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
 }
 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+if (a->shamt >= TARGET_LONG_BITS) {
+return false;
+}
+
+if (a->rd != 0) {
+TCGv t = tcg_temp_new();
+gen_get_gpr(t, a->rs1);
+
+tcg_gen_shli_tl(t, t, a->shamt);
+
+gen_set_gpr(a->rd, t);
+tcg_temp_free(t);
+} /* NOP otherwise */
 return true;
 }
 
 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+if (a->shamt >= TARGET_LONG_BITS) {
+return false;
+}
+
+if (a->rd != 0) {
+TCGv t = tcg_temp_new();
+gen_get_gpr(t, a->rs1);
+
+tcg_gen_shri_tl(t, t, a->shamt);
+gen_set_gpr(a->rd, t);
+tcg_temp_free(t);
+} /* NOP otherwise */
 return true;
 }
 
 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 
0x400);
+if (a->shamt >= TARGET_LONG_BITS) {
+return false;
+}
+
+if (a->rd != 0) {
+TCGv t = tcg_temp_new();
+gen_get_gpr(t, a->rs1);
+
+tcg_gen_sari_tl(t, t, a->shamt);
+gen_set_gpr(a->rd, t);
+tcg_temp_free(t);
+} /* NOP otherwise */
 return true;
 }
 
@@ -329,26 +373,42 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
 #ifdef TARGET_RISCV64
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
-gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
-return true;
+return gen_arith_imm(ctx, a, &gen_addw);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
-gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+TCGv source1;
+source1 = tcg_temp_new();
+  

[Qemu-devel] [PULL 20/34] target/riscv: Remove manual decoding from gen_branch()

[Palmer Dabbelt]

From: Bastian Koppelmann 

We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn_trans/trans_rvi.inc.c | 46 +---
 target/riscv/translate.c| 47 -
 2 files changed, 33 insertions(+), 60 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 631a88906bce..ae4b0a2bcb78 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 return true;
 }
 
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 {
-gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+TCGLabel *l = gen_new_label();
+TCGv source1, source2;
+source1 = tcg_temp_new();
+source2 = tcg_temp_new();
+gen_get_gpr(source1, a->rs1);
+gen_get_gpr(source2, a->rs2);
+
+tcg_gen_brcond_tl(cond, source1, source2, l);
+gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+gen_set_label(l); /* branch taken */
+
+if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+/* misaligned */
+gen_exception_inst_addr_mis(ctx);
+} else {
+gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+}
+ctx->base.is_jmp = DISAS_NORETURN;
+
+tcg_temp_free(source1);
+tcg_temp_free(source2);
+
 return true;
 }
 
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
 static bool trans_bne(DisasContext *ctx, arg_bne *a)
 {
-gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
-return true;
+return gen_branch(ctx, a, TCG_COND_NE);
 }
 
 static bool trans_blt(DisasContext *ctx, arg_blt *a)
 {
-gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
-return true;
+return gen_branch(ctx, a, TCG_COND_LT);
 }
 
 static bool trans_bge(DisasContext *ctx, arg_bge *a)
 {
-gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
-return true;
+return gen_branch(ctx, a, TCG_COND_GE);
 }
 
 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
 {
-gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
-return true;
+return gen_branch(ctx, a, TCG_COND_LTU);
 }
 
 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 {
-
-gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
-return true;
+return gen_branch(ctx, a, TCG_COND_GEU);
 }
 
 static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9dee2ec24287..a3d5cdbad82d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,53 +531,6 @@ static void gen_jal(DisasContext *ctx, int rd, 
target_ulong imm)
 ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
-   target_long bimm)
-{
-TCGLabel *l = gen_new_label();
-TCGv source1, source2;
-source1 = tcg_temp_new();
-source2 = tcg_temp_new();
-gen_get_gpr(source1, rs1);
-gen_get_gpr(source2, rs2);
-
-switch (opc) {
-case OPC_RISC_BEQ:
-tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
-break;
-case OPC_RISC_BNE:
-tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
-break;
-case OPC_RISC_BLT:
-tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
-break;
-case OPC_RISC_BGE:
-tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
-break;
-case OPC_RISC_BLTU:
-tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
-break;
-case OPC_RISC_BGEU:
-tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
-break;
-default:
-gen_exception_illegal(ctx);
-return;
-}
-tcg_temp_free(source1);
-tcg_temp_free(source2);
-
-gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
-gen_set_label(l); /* branch taken */
-if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
-/* misaligned */
-gen_exception_inst_addr_mis(ctx);
-} else {
-gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
-}
-ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
 target_long imm)
 {
-- 
2.18.1

[Qemu-devel] [PULL 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs  |  9 ++-
 target/riscv/insn16.decode  | 55 ++
 target/riscv/insn_trans/trans_rvc.inc.c | 75 +
 target/riscv/translate.c| 53 ++---
 4 files changed, 154 insertions(+), 38 deletions(-)
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 05087a91bb85..9c6c1093271e 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
  "GEN", $(TARGET_DIR)$@)
 
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c
+target/riscv/decode_insn16.inc.c: \
+  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+   $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 
$<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+   target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
new file mode 100644
index ..558c0c41f0b5
--- /dev/null
+++ b/target/riscv/insn16.decode
@@ -0,0 +1,55 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+#Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see .
+
+# Fields:
+%rd7:5
+%rs1_3 7:3!function=ex_rvc_register
+%rs2_3 2:3!function=ex_rvc_register
+
+# Immediates:
+%nzuimm_ciw7:4 11:2 5:1 6:1   !function=ex_shift_2
+%uimm_cl_d 5:2 10:3   !function=ex_shift_3
+%uimm_cl_w 5:1 10:3 6:1   !function=ex_shift_2
+
+
+# Argument sets:
+&cl   rs1 rd
+&cl_dw uimm   rs1 rd
+&ciw   nzuimm rd
+&cs   rs1 rs2
+&cs_dw uimm   rs1 rs2
+
+
+# Formats 16:
+@ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
+@cl_d  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
+@cl_w  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
+@cl... ... ... .. ... .. &cl  rs1=%rs1_3  rd=%rs2_3
+@cs... ... ... .. ... .. &cs  rs1=%rs1_3  
rs2=%rs2_3
+@cs_d  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  
rs2=%rs2_3
+@cs_w  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  
rs2=%rs2_3
+
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+c_addi4spn000 ... 00 @ciw
+c_fld 001  ... ... .. ... 00 @cl_d
+c_lw  010  ... ... .. ... 00 @cl_w
+c_flw_ld  011  --- ... -- ... 00 @cl#Note: Must parse uimm manually
+c_fsd 101  ... ... .. ... 00 @cs_d
+c_sw  110  ... ... .. ... 00 @cs_w
+c_fsw_sd  111  --- ... -- ... 00 @cs#Note: Must parse uimm manually
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
new file mode 100644
index ..93ec8aa30b95
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the RVC Compressed Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see 

[Qemu-devel] [PULL 08/34] target/riscv: Convert RVXM insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32-64.decode   |   7 ++
 target/riscv/insn32.decode  |  10 +++
 target/riscv/insn_trans/trans_rvm.inc.c | 113 
 target/riscv/translate.c|  16 ++--
 4 files changed, 137 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 9a35f2aa1920..008f1005469e 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -36,3 +36,10 @@ subw 010 .  . 000 . 0111011 @r
 sllw 000 .  . 001 . 0111011 @r
 srlw 000 .  . 101 . 0111011 @r
 sraw 010 .  . 101 . 0111011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 001 .  . 000 . 0111011 @r
+divw 001 .  . 100 . 0111011 @r
+divuw001 .  . 101 . 0111011 @r
+remw 001 .  . 110 . 0111011 @r
+remuw001 .  . 111 . 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 977b1b10a330..e53944bf0e40 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -92,3 +92,13 @@ csrrc . 011 . 1110011 @csr
 csrrwi    . 101 . 1110011 @csr
 csrrsi    . 110 . 1110011 @csr
 csrrci    . 111 . 1110011 @csr
+
+# *** RV32M Standard Extension ***
+mul  001 .  . 000 . 0110011 @r
+mulh 001 .  . 001 . 0110011 @r
+mulhsu   001 .  . 010 . 0110011 @r
+mulhu001 .  . 011 . 0110011 @r
+div  001 .  . 100 . 0110011 @r
+divu 001 .  . 101 . 0110011 @r
+rem  001 .  . 110 . 0110011 @r
+remu 001 .  . 111 . 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c 
b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index ..69631c9e3783
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,113 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+REQUIRE_EXT(ctx, RVM);
+gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_

[Qemu-devel] [PULL 10/34] target/riscv: Convert RV64A insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32-64.decode   |  13 +++
 target/riscv/insn_trans/trans_rva.inc.c |  58 ++
 target/riscv/translate.c| 144 
 3 files changed, 71 insertions(+), 144 deletions(-)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 008f1005469e..0bee95c9840d 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -43,3 +43,16 @@ divw 001 .  . 100 . 0111011 @r
 divuw001 .  . 101 . 0111011 @r
 remw 001 .  . 110 . 0111011 @r
 remuw001 .  . 111 . 0111011 @r
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d   00010 . . 0 . 011 . 010 @atom_ld
+sc_d   00011 . . . . 011 . 010 @atom_st
+amoswap_d  1 . . . . 011 . 010 @atom_st
+amoadd_d   0 . . . . 011 . 010 @atom_st
+amoxor_d   00100 . . . . 011 . 010 @atom_st
+amoand_d   01100 . . . . 011 . 010 @atom_st
+amoor_d01000 . . . . 011 . 010 @atom_st
+amomin_d   1 . . . . 011 . 010 @atom_st
+amomax_d   10100 . . . . 011 . 010 @atom_st
+amominu_d  11000 . . . . 011 . 010 @atom_st
+amomaxu_d  11100 . . . . 011 . 010 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c 
b/target/riscv/insn_trans/trans_rva.inc.c
index 5d3c853ca504..f6dbbc065e15 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -158,3 +158,61 @@ static bool trans_amomaxu_w(DisasContext *ctx, 
arg_amomaxu_w *a)
 REQUIRE_EXT(ctx, RVA);
 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | 
MO_TESL));
 }
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b0de062a4fd1..c2791459993e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -794,143 +794,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, 
int rs1,
 tcg_temp_free(t0);
 }
 
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
-  int rd, int rs1, int rs2)
-{
-TCGv src1, src2, dat;
-TCGLabel *l1, *l2;
-TCGMemOp mop;
-bool aq, rl;
-
-/* Extract the size of the atomic operation.  */
-switch (extract32(opc, 12, 3)) {
-case 2: /* 32-bit */
-mop = MO_ALIGN | MO_TESL;
-break;
-#if defined(TARGET_RISCV64)
-case 3: /* 64-bit */
-mop = MO_ALIGN | MO_TEQ;
-break;
-#endif
-default:
-gen_exception_illegal(ctx);
-return;
-}
-rl = extract32(opc, 25, 1);
-aq = extract32(opc, 26, 1);
-
-src1 = tcg_temp_new();
-src2 = tcg_temp_new();
-
-switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
-case OPC_RISC_LR:
-/* Put addr in load_res, data in load_val.  */
-gen_get_gpr(src1, rs1);
-if (rl) {
-tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
-}
-tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
-if (aq) {
-tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
-}
-tcg_gen_mov_tl

[Qemu-devel] [PULL 04/34] target/riscv: Convert RV64I load/store insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs  |  8 +---
 target/riscv/insn32-64.decode   | 25 +
 target/riscv/insn_trans/trans_rvi.inc.c | 20 
 target/riscv/translate.c|  7 ---
 4 files changed, 50 insertions(+), 10 deletions(-)
 create mode 100644 target/riscv/insn32-64.decode

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index bf0a268033a0..05087a91bb85 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -2,10 +2,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o 
fpu_helper.o gdbstub.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/riscv/decode_insn32.inc.c: \
-  $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
+decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+
+target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
  "GEN", $(TARGET_DIR)$@)
 
 target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
new file mode 100644
index ..439d4e2c587b
--- /dev/null
+++ b/target/riscv/insn32-64.decode
@@ -0,0 +1,25 @@
+#
+# RISC-V translation routines for the RV Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+#Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see .
+
+# This is concatenated with insn32.decode for risc64 targets.
+# Most of the fields and formats are there.
+
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu     . 110 . 011 @i
+ld      . 011 . 011 @i
+sd   ... .  . 011 . 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index d13b7b2b6d8f..61f708dba144 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
 gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
 return true;
 }
+
+#ifdef TARGET_RISCV64
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a)
+{
+gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
+return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb284a5e08d6..2e35142ca2a4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1908,13 +1908,6 @@ static void decode_RV32_64G(DisasContext *ctx)
 imm = GET_IMM(ctx->opcode);
 
 switch (op) {
-case OPC_RISC_LOAD:
-gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
-break;
-case OPC_RISC_STORE:
-gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
-  GET_STORE_IMM(ctx->opcode));
-break;
 case OPC_RISC_ARITH_IMM:
 #if defined(TARGET_RISCV64)
 case OPC_RISC_ARITH_IMM_W:
-- 
2.18.1

[Qemu-devel] [PULL 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn16.decode  |  43 +++
 target/riscv/insn_trans/trans_rvc.inc.c | 151 
 target/riscv/translate.c| 118 +-
 3 files changed, 195 insertions(+), 117 deletions(-)

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 558c0c41f0b5..29dade0fa1ae 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -22,28 +22,53 @@
 %rs2_3 2:3!function=ex_rvc_register
 
 # Immediates:
+%imm_ci12:s1 2:5
 %nzuimm_ciw7:4 11:2 5:1 6:1   !function=ex_shift_2
 %uimm_cl_d 5:2 10:3   !function=ex_shift_3
 %uimm_cl_w 5:1 10:3 6:1   !function=ex_shift_2
+%imm_cb12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
+%imm_cj12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+%nzuimm_6bit   12:1 2:5
+
+%imm_addi16sp  12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
+%imm_lui   12:s1 2:5 !function=ex_shift_12
+
 
 
 # Argument sets:
 &cl   rs1 rd
 &cl_dw uimm   rs1 rd
+&ciimmrd
 &ciw   nzuimm rd
 &cs   rs1 rs2
 &cs_dw uimm   rs1 rs2
+&cbimmrs1
+&cr   rd  rs2
+&c_j   imm
+&c_shift   shamt  rd
+
 
+&c_addi16sp_lui  imm_lui imm_addi16sp rd
 
 # Formats 16:
+@ci... . . .  .. &ci imm=%imm_ci  %rd
 @ciw   ...    ... .. &ciwnzuimm=%nzuimm_ciw   rd=%rs2_3
 @cl_d  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
 @cl_w  ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
 @cl... ... ... .. ... .. &cl  rs1=%rs1_3  rd=%rs2_3
 @cs... ... ... .. ... .. &cs  rs1=%rs1_3  
rs2=%rs2_3
+@cs_2  ... ... ... .. ... .. &cr  rd=%rs1_3   
rs2=%rs2_3
 @cs_d  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  
rs2=%rs2_3
 @cs_w  ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  
rs2=%rs2_3
+@cb... ... ... .. ... .. &cb imm=%imm_cb  rs1=%rs1_3
+@cj...... .. &c_jimm=%imm_cj
 
+@c_addi16sp_lui ... .  . . .. &c_addi16sp_lui %imm_lui %imm_addi16sp 
%rd
+
+@c_shift... . .. ... . .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
+
+@c_andi ... . .. ... . .. &ci imm=%imm_ci rd=%rs1_3
 
 # *** RV64C Standard Extension (Quadrant 0) ***
 c_addi4spn000 ... 00 @ciw
@@ -53,3 +78,21 @@ c_flw_ld  011  --- ... -- ... 00 @cl#Note: Must 
parse uimm manually
 c_fsd 101  ... ... .. ... 00 @cs_d
 c_sw  110  ... ... .. ... 00 @cs_w
 c_fsw_sd  111  --- ... -- ... 00 @cs#Note: Must parse uimm manually
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+c_addi000 .  .  . 01 @ci
+c_jal_addiw   001 .  .  . 01 @ci #Note: parse rd and/or imm 
manually
+c_li  010 .  .  . 01 @ci
+c_addi16sp_lui011 .  .  . 01 @c_addi16sp_lui # shares opc with 
C.LUI
+c_srli100 . 00 ...  . 01 @c_shift
+c_srai100 . 01 ...  . 01 @c_shift
+c_andi100 . 10 ...  . 01 @c_andi
+c_sub 100 0 11 ... 00 ... 01 @cs_2
+c_xor 100 0 11 ... 01 ... 01 @cs_2
+c_or  100 0 11 ... 10 ... 01 @cs_2
+c_and 100 0 11 ... 11 ... 01 @cs_2
+c_subw100 1 11 ... 00 ... 01 @cs_2
+c_addw100 1 11 ... 01 ... 01 @cs_2
+c_j   101 ... 01 @cj
+c_beqz110  ... ...  . 01 @cb
+c_bnez111  ... ...  . 01 @cb
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index 93ec8aa30b95..b06c435c9800 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -73,3 +73,154 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd 
*a)
 return false;
 #endif
 }
+
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
+{
+if (a->imm == 0) {
+/* Hint: insn is valid but does not affect state */
+return true;
+}
+arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+return trans_addi(ctx, &arg);
+}
+
+static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
+{
+#ifdef TARGET_RISCV32
+/* C.JAL */
+arg_jal arg = { .rd = 1, .imm = a->imm };
+return trans_jal(ctx, &arg);
+#else
+/* C.ADDIW */
+arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
+return trans_addiw(ctx, &arg);
+#endif
+}
+
+static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
+{
+if (a->rd == 0) {
+/* Hint: insn is valid but does not affect state */
+return true;
+}
+arg_addi arg = { .rd = a->r

[Qemu-devel] [PULL 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC

[Palmer Dabbelt]

From: Bastian Koppelmann 

for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.

Reviewed-by: Richard Henderson 
Acked-by: Alistair Francis 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs  | 10 +++
 target/riscv/insn32.decode  | 30 +
 target/riscv/insn_trans/trans_rvi.inc.c | 35 +
 target/riscv/translate.c| 31 --
 4 files changed, 92 insertions(+), 14 deletions(-)
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 4072abe3e45c..bf0a268033a0 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,11 @@
 obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/riscv/decode_insn32.inc.c: \
+  $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
+   $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
+ "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
new file mode 100644
index ..44d4e922b6fa
--- /dev/null
+++ b/target/riscv/insn32.decode
@@ -0,0 +1,30 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+#Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see .
+
+# Fields:
+%rd7:5
+
+# immediates:
+%imm_u12:s20 !function=ex_shift_12
+
+# Formats 32:
+@u     . ... imm=%imm_u  
%rd
+
+# *** RV32I Base Instruction Set ***
+lui     . 0110111 @u
+auipc   . 0010111 @u
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
new file mode 100644
index ..9885a8d27551
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -0,0 +1,35 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a)
+{
+if (a->rd != 0) {
+tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+}
+return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
+{
+if (a->rd != 0) {
+tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+}
+return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b7176cbf98e1..a273ac827448 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1874,6 +1874,19 @@ static void decode_RV32_64C(DisasContext *ctx)
 }
 }
 
+#define EX_SH(amount) \
+static int ex_shift_##amount(int imm) \
+{ \
+return imm << amount; \
+}
+EX_SH(12)
+
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
+/* Include the auto-generated decoder for 32 bit insn */
+#include "decode_insn32.inc.c"
+/* Include insn module translation function */
+#include "insn_trans/trans_rvi.inc.c"
+
 static void decode_RV32_64G(DisasContext *ctx)
 {
 int rs1;
@@ -1894,19 +1907,6 @@ static void decode_RV32_64G(DisasContext *ctx)
 imm

[Qemu-devel] [PULL 09/34] target/riscv: Convert RV32A insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  17 +++
 target/riscv/insn_trans/trans_rva.inc.c | 160 
 target/riscv/translate.c|   1 +
 3 files changed, 178 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e53944bf0e40..00b9e2d9a508 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,6 +34,7 @@
 # Argument sets:
 &bimm rs2 rs1
 &shift shamt rs1 rd
+&atomicaq rl rs2 rs1 rd
 
 # Formats 32:
 @r   ...   . . ... . ...   %rs2 %rs1 
%rd
@@ -46,6 +47,9 @@
 @sh  ..  .. .  ... . ... &shift  shamt=%sh10  %rs1 
%rd
 @csr    .  ... . ...   %csr %rs1 
%rd
 
+@atom_ld . aq:1 rl:1 .  . ... &atomic rs2=0 %rs1 
%rd
+@atom_st . aq:1 rl:1 .  . ... &atomic %rs2  %rs1 
%rd
+
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
 auipc   . 0010111 @u
@@ -102,3 +106,16 @@ div  001 .  . 100 . 0110011 @r
 divu 001 .  . 101 . 0110011 @r
 rem  001 .  . 110 . 0110011 @r
 remu 001 .  . 111 . 0110011 @r
+
+# *** RV32A Standard Extension ***
+lr_w   00010 . . 0 . 010 . 010 @atom_ld
+sc_w   00011 . . . . 010 . 010 @atom_st
+amoswap_w  1 . . . . 010 . 010 @atom_st
+amoadd_w   0 . . . . 010 . 010 @atom_st
+amoxor_w   00100 . . . . 010 . 010 @atom_st
+amoand_w   01100 . . . . 010 . 010 @atom_st
+amoor_w01000 . . . . 010 . 010 @atom_st
+amomin_w   1 . . . . 010 . 010 @atom_st
+amomax_w   10100 . . . . 010 . 010 @atom_st
+amominu_w  11000 . . . . 010 . 010 @atom_st
+amomaxu_w  11100 . . . . 010 . 010 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c 
b/target/riscv/insn_trans/trans_rva.inc.c
new file mode 100644
index ..5d3c853ca504
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -0,0 +1,160 @@
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+TCGv src1 = tcg_temp_new();
+/* Put addr in load_res, data in load_val.  */
+gen_get_gpr(src1, a->rs1);
+if (a->rl) {
+tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+}
+tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+if (a->aq) {
+tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+}
+tcg_gen_mov_tl(load_res, src1);
+gen_set_gpr(a->rd, load_val);
+
+tcg_temp_free(src1);
+return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)
+{
+TCGv src1 = tcg_temp_new();
+TCGv src2 = tcg_temp_new();
+TCGv dat = tcg_temp_new();
+TCGLabel *l1 = gen_new_label();
+TCGLabel *l2 = gen_new_label();
+
+gen_get_gpr(src1, a->rs1);
+tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+gen_get_gpr(src2, a->rs2);
+/*
+ * Note that the TCG atomic primitives are SC,
+ * so we can ignore AQ/RL along this path.
+ */
+tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+  ctx->mem_idx, mop);
+tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+gen_set_gpr(a->rd, dat);
+tcg_gen_br(l2);
+
+gen_set_label(l1);
+/*
+ * Address comparion failure.  However, we still need to
+ * provide the memory barrier implied by AQ/RL.
+ */
+tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+tcg_gen_movi_tl(dat, 1);
+gen_set_gpr(a->rd, dat);
+
+gen_set_label(l2);
+tcg_temp_free(dat);
+

[Qemu-devel] [PULL 07/34] target/riscv: Convert RVXI csr insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  8 +++
 target/riscv/insn_trans/trans_rvi.inc.c | 79 +
 target/riscv/translate.c| 43 +-
 3 files changed, 88 insertions(+), 42 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 804b721ca51e..977b1b10a330 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,6 +22,7 @@
 %rd7:5
 
 %sh1020:10
+%csr20:12
 
 # immediates:
 %imm_i20:s12
@@ -43,6 +44,7 @@
 @j     . ... imm=%imm_j  
%rd
 
 @sh  ..  .. .  ... . ... &shift  shamt=%sh10  %rs1 
%rd
+@csr    .  ... . ...   %csr %rs1 
%rd
 
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
@@ -84,3 +86,9 @@ or   000 .. 110 . 0110011 @r
 and  000 .. 111 . 0110011 @r
 fence pred:4 succ:4 - 000 - 000
 fence_i         - 001 - 000
+csrrw . 001 . 1110011 @csr
+csrrs . 010 . 1110011 @csr
+csrrc . 011 . 1110011 @csr
+csrrwi    . 101 . 1110011 @csr
+csrrsi    . 110 . 1110011 @csr
+csrrci    . 111 . 1110011 @csr
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 973d6371df85..4a23372cb823 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -337,3 +337,82 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i 
*a)
 ctx->base.is_jmp = DISAS_NORETURN;
 return true;
 }
+
+#define RISCV_OP_CSR_PRE do {\
+source1 = tcg_temp_new(); \
+csr_store = tcg_temp_new(); \
+dest = tcg_temp_new(); \
+rs1_pass = tcg_temp_new(); \
+gen_get_gpr(source1, a->rs1); \
+tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+tcg_gen_movi_tl(rs1_pass, a->rs1); \
+tcg_gen_movi_tl(csr_store, a->csr); \
+gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+gen_io_end(); \
+gen_set_gpr(a->rd, dest); \
+tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+tcg_gen_exit_tb(NULL, 0); \
+ctx->base.is_jmp = DISAS_NORETURN; \
+tcg_temp_free(source1); \
+tcg_temp_free(csr_store); \
+tcg_temp_free(dest); \
+tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+RISCV_OP_CSR_POST;
+return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+RISCV_OP_CSR_POST;
+return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+RISCV_OP_CSR_POST;
+return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+RISCV_OP_CSR_POST;
+return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+RISCV_OP_CSR_POST;
+return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+{
+TCGv source1, csr_store, dest, rs1_pass;
+RISCV_OP_CSR_PRE;
+gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+RISCV_OP_CSR_POST;
+return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f720746cb791..18555000af35 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1476,16 +1476,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t 
opc, int rd,
 static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int csr)
 {
-TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
+TCGv source1, dest;
 source1 = tcg_temp_new();
-csr_store = tcg_temp_new();
 dest = tcg_temp_new();
-rs1_pass = tcg_temp_new();
-imm_rs1 = tcg_temp_new();
 gen_get_gpr(source1, rs1);
 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-tcg_gen_movi_tl(rs1_pass, rs1);
-tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */
 
 #ifnde

[Qemu-devel] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  |  2 ++
 target/riscv/insn_trans/trans_rvi.inc.c | 19 +++
 target/riscv/translate.c| 12 
 3 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1f5bf1f6f97d..804b721ca51e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -82,3 +82,5 @@ srl  000 .. 101 . 0110011 @r
 sra  010 .. 101 . 0110011 @r
 or   000 .. 110 . 0110011 @r
 and  000 .. 111 . 0110011 @r
+fence pred:4 succ:4 - 000 - 000
+fence_i         - 001 - 000
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 136fa54d0655..973d6371df85 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 return true;
 }
 #endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+/* FENCE is a full memory barrier. */
+tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+/*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+tcg_gen_exit_tb(NULL, 0);
+ctx->base.is_jmp = DISAS_NORETURN;
+return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1ae84dcd5992..f720746cb791 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1950,18 +1950,6 @@ static void decode_RV32_64G(DisasContext *ctx)
 gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
  GET_RM(ctx->opcode));
 break;
-case OPC_RISC_FENCE:
-if (ctx->opcode & 0x1000) {
-/* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
-tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-tcg_gen_exit_tb(NULL, 0);
-ctx->base.is_jmp = DISAS_NORETURN;
-} else {
-/* FENCE is a full memory barrier. */
-tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
-}
-break;
 case OPC_RISC_SYSTEM:
 gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF0) >> 20);
-- 
2.18.1

[Qemu-devel] [PULL] target/riscv: Convert to decodetree

[Palmer Dabbelt]

merged tag 'i2c-for-release-20190228'
Primary key fingerprint: FD0D 5CE6 7CE0 F59A 6688  2686 61F3 8C90 919B FF81
The following changes since commit 20b084c4b1401b7f8fbc385649d48c67b6f43d44:

  Merge remote-tracking branch 'remotes/cminyard/tags/i2c-for-release-20190228' 
into staging (2019-03-01 11:20:49 +)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf2

for you to fetch changes up to 0bcba29464ea9969fc69cd729e4c8bddfb2e18e3:

  target/riscv: Remaining rvc insn reuse 32 bit translators (2019-03-01 
13:16:18 -0800)


target/riscv: Convert to decodetree

Bastian: this patchset converts the RISC-V decoder to decodetree in four major 
steps:

1) Convert 32-bit instructions to decodetree [Patch 1-15]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).

Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 16-18]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 19-29]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 30-34]

Palmer: This passed Alistar's testing on rv32 and rv64 as well as my
testing on rv64, so I think it's good to go.  Thanks for the cleanup!


Bastian Koppelmann (34):
  target/riscv: Activate decodetree and implemnt LUI & AUIPC
  target/riscv: Convert RVXI branch insns to decodetree
  target/riscv: Convert RV32I load/store insns to decodetree
  target/riscv: Convert RV64I load/store insns to decodetree
  target/riscv: Convert RVXI arithmetic insns to decodetree
  target/riscv: Convert RVXI fence insns to decodetree
  target/riscv: Convert RVXI csr insns to decodetree
  target/riscv: Convert RVXM insns to decodetree
  target/riscv: Convert RV32A insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Remove gen_jalr()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove gen_system()
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Convert @cs_2 insns to share translation functions
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
  target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
  target/riscv: Remaining rvc insn reuse 32 bit translators

 target/riscv/Makefile.objs |   22 +
 target/riscv/insn16-32.decode  |   31 +
 target/riscv/insn16-64.decode  |   33 +
 target/riscv/insn16.decode |  114 ++
 target/riscv/insn32-64.decode  |   72 +
 target/riscv/insn32.decode |  203 +++
 target/riscv/insn_trans/trans_privileged.inc.c |  110 ++
 target/riscv/insn_trans/trans_rva.inc.c|  218 +++
 target/riscv/insn_trans/trans_rvc.inc.c|  149 ++
 target/riscv/insn_trans/trans_rvd.inc.c|  442 ++
 target/riscv/insn_trans/trans_rvf.inc.c|  439 ++
 target/riscv/insn_trans/trans_rvi.inc.c|  568 +++
 target/riscv/insn_trans/trans_rvm.inc.c

[Qemu-devel] [PULL 03/34] target/riscv: Convert RV32I load/store insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  | 10 ++
 target/riscv/insn_trans/trans_rvi.inc.c | 48 +
 2 files changed, 58 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81f56c16b45f..076de873c4f1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
 
 # immediates:
 %imm_i20:s12
+%imm_s25:s7 7:5
 %imm_b31:s1 7:1 25:6 8:4 !function=ex_shift_1
 %imm_j31:s1 12:8 20:1 21:10  !function=ex_shift_1
 %imm_u12:s20 !function=ex_shift_12
@@ -33,6 +34,7 @@
 # Formats 32:
 @i   . ... . ... imm=%imm_i %rs1 
%rd
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
+@s   ...   . . ... . ... imm=%imm_s %rs2 %rs1
 @u     . ... imm=%imm_u  
%rd
 @j     . ... imm=%imm_j  
%rd
 
@@ -47,3 +49,11 @@ blt  ... .. 100 . 1100011 @b
 bge  ... .. 101 . 1100011 @b
 bltu ... .. 110 . 1100011 @b
 bgeu ... .. 111 . 1100011 @b
+lb    . 000 . 011 @i
+lh    . 001 . 011 @i
+lw    . 010 . 011 @i
+lbu   . 100 . 011 @i
+lhu   . 101 . 011 @i
+sb   ...  .   . 000 . 0100011 @s
+sh   ...  .   . 001 . 0100011 @s
+sw   ...  .   . 010 . 0100011 @s
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index bcf20def50eb..d13b7b2b6d8f 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
 return true;
 }
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
+return true;
+}
-- 
2.18.1

[Qemu-devel] [PULL 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.

Acked-by: Alistair Francis 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32-64.decode   |  13 ++
 target/riscv/insn32.decode  |  25 
 target/riscv/insn_trans/trans_rvi.inc.c | 168 
 target/riscv/translate.c|   9 --
 4 files changed, 206 insertions(+), 9 deletions(-)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 439d4e2c587b..9a35f2aa1920 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -19,7 +19,20 @@
 # This is concatenated with insn32.decode for risc64 targets.
 # Most of the fields and formats are there.
 
+%sh520:5
+
+@sh5 ...  . .  ... . ... &shift  shamt=%sh5  %rs1 
%rd
+
 # *** RV64I Base Instruction Set (in addition to RV32I) ***
 lwu     . 110 . 011 @i
 ld      . 011 . 011 @i
 sd   ... .  . 011 . 0100011 @s
+addiw   . 000 . 0011011 @i
+slliw000 .  . 001 . 0011011 @sh5
+srliw000 .  . 101 . 0011011 @sh5
+sraiw010 .  . 101 . 0011011 @sh5
+addw 000 .  . 000 . 0111011 @r
+subw 010 .  . 000 . 0111011 @r
+sllw 000 .  . 001 . 0111011 @r
+srlw 000 .  . 101 . 0111011 @r
+sraw 010 .  . 101 . 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 076de873c4f1..1f5bf1f6f97d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,8 @@
 %rs1   15:5
 %rd7:5
 
+%sh1020:10
+
 # immediates:
 %imm_i20:s12
 %imm_s25:s7 7:5
@@ -30,14 +32,18 @@
 
 # Argument sets:
 &bimm rs2 rs1
+&shift shamt rs1 rd
 
 # Formats 32:
+@r   ...   . . ... . ...   %rs2 %rs1 
%rd
 @i   . ... . ... imm=%imm_i %rs1 
%rd
 @b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
 @s   ...   . . ... . ... imm=%imm_s %rs2 %rs1
 @u     . ... imm=%imm_u  
%rd
 @j     . ... imm=%imm_j  
%rd
 
+@sh  ..  .. .  ... . ... &shift  shamt=%sh10  %rs1 
%rd
+
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
 auipc   . 0010111 @u
@@ -57,3 +63,22 @@ lhu   . 101 . 011 @i
 sb   ...  .   . 000 . 0100011 @s
 sh   ...  .   . 001 . 0100011 @s
 sw   ...  .   . 010 . 0100011 @s
+addi  . 000 . 0010011 @i
+slti  . 010 . 0010011 @i
+sltiu . 011 . 0010011 @i
+xori  . 100 . 0010011 @i
+ori   . 110 . 0010011 @i
+andi  . 111 . 0010011 @i
+slli 00 ... 001 . 0010011 @sh
+srli 00 ... 101 . 0010011 @sh
+srai 01 ... 101 . 0010011 @sh
+add  000 .. 000 . 0110011 @r
+sub  010 .. 000 . 0110011 @r
+sll  000 .. 001 . 0110011 @r
+slt  000 .. 010 . 0110011 @r
+sltu 000 .. 011 . 0110011 @r
+xor  000 .. 100 . 0110011 @r
+srl  000 .. 101 . 0110011 @r
+sra  010 .. 101 . 0110011 @r
+or   000 .. 110 . 0110011 @r
+and  000 .. 111 . 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 61f708dba144..136fa54d0655 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -150,3 +150,171 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
 return true;
 }
 #endif
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
+{
+gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a)
+{
+gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
+return true;
+}
+static boo

[Qemu-devel] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree

[Palmer Dabbelt]

From: Bastian Koppelmann 

Acked-by: Alistair Francis 
Reviewed-by: Palmer Dabbelt 
Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/insn32.decode  | 19 ++
 target/riscv/insn_trans/trans_rvi.inc.c | 49 +
 target/riscv/translate.c| 12 +-
 3 files changed, 69 insertions(+), 11 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d4e922b6fa..81f56c16b45f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,14 +17,33 @@
 # this program.  If not, see .
 
 # Fields:
+%rs2   20:5
+%rs1   15:5
 %rd7:5
 
 # immediates:
+%imm_i20:s12
+%imm_b31:s1 7:1 25:6 8:4 !function=ex_shift_1
+%imm_j31:s1 12:8 20:1 21:10  !function=ex_shift_1
 %imm_u12:s20 !function=ex_shift_12
 
+# Argument sets:
+&bimm rs2 rs1
+
 # Formats 32:
+@i   . ... . ... imm=%imm_i %rs1 
%rd
+@b   ...   . . ... . ... &b  imm=%imm_b %rs2 %rs1
 @u     . ... imm=%imm_u  
%rd
+@j     . ... imm=%imm_j  
%rd
 
 # *** RV32I Base Instruction Set ***
 lui     . 0110111 @u
 auipc   . 0010111 @u
+jal     . 110 @j
+jalr  . 000 . 1100111 @i
+beq  ... .. 000 . 1100011 @b
+bne  ... .. 001 . 1100011 @b
+blt  ... .. 100 . 1100011 @b
+bge  ... .. 101 . 1100011 @b
+bltu ... .. 110 . 1100011 @b
+bgeu ... .. 111 . 1100011 @b
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
b/target/riscv/insn_trans/trans_rvi.inc.c
index 9885a8d27551..bcf20def50eb 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
 }
 return true;
 }
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a)
+{
+gen_jal(ctx, a->rd, a->imm);
+return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+{
+gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
+return true;
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+
+gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
+return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a273ac827448..fb284a5e08d6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1879,6 +1879,7 @@ static void decode_RV32_64C(DisasContext *ctx)
 { \
 return imm << amount; \
 }
+EX_SH(1)
 EX_SH(12)
 
 bool decode_insn32(DisasContext *ctx, uint32_t insn);
@@ -1907,17 +1908,6 @@ static void decode_RV32_64G(DisasContext *ctx)
 imm = GET_IMM(ctx->opcode);
 
 switch (op) {
-case OPC_RISC_JAL:
-imm = GET_JAL_IMM(ctx->opcode);
-gen_jal(ctx, rd, imm);
-break;
-case OPC_RISC_JALR:
-gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
-break;
-case OPC_RISC_BRANCH:
-gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
-   GET_B_IMM(ctx->opcode));
-break;
 case OPC_RISC_LOAD:
 gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
 break;
-- 
2.18.1

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com -> 
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Switched to a new branch 'test'
30a1fa38c4 s390-bios: dasd-ipl: Use control unit type to customize error data
2989c319fd s390-bios: Support booting from real dasd device
b2085c405e s390-bios: Add channel command codes/structs needed for dasd-ipl
f35324 s390-bios: Use control unit type to determine boot method
c6f03bc84f s390-bios: Refactor virtio to run channel programs via cio
65864585c0 s390-bios: cio error handling
097bccecd0 s390-bios: Support for running format-0/1 channel programs
c8b8481de0 s390-bios: ptr2u32 and u32toptr
2b710b5d43 s390-bios: Map low core memory
16d1882b5f s390-bios: Decouple channel i/o logic from virtio
7a28a2573e s390-bios: Clean up cio.h
b18ab082b0 s390-bios: Factor finding boot device out of virtio code path
67e5e992d6 s390-bios: Extend find_dev() for non-virtio devices
5f215da4ce s390-bios: decouple common boot logic from virtio
b76737ee14 s390-bios: decouple cio setup from virtio
e2d6b7499a s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit e2d6b7499af4 (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit b76737ee14b7 (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 5f215da4ce76 (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit 67e5e992d625 (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit b18ab082b084 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit 7a28a2573eba (s390-bios: Clean up cio.h)
7/16 Checking commit 16d1882b5f7d (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit 2b710b5d436c (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit c8b8481de0ac (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit 097bccecd0e1 (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit 65864585c097 (s390-bios: cio error handling)
12/16 Checking commit c6f03bc84fcb (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit f3532490 (s390-b

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com -> 
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Switched to a new branch 'test'
f500a324be s390-bios: dasd-ipl: Use control unit type to customize error data
61683f31fd s390-bios: Support booting from real dasd device
59e5199d22 s390-bios: Add channel command codes/structs needed for dasd-ipl
9add6dde7e s390-bios: Use control unit type to determine boot method
45b1810ae5 s390-bios: Refactor virtio to run channel programs via cio
f7fff67468 s390-bios: cio error handling
88f0121304 s390-bios: Support for running format-0/1 channel programs
c689028ed0 s390-bios: ptr2u32 and u32toptr
6753adcac4 s390-bios: Map low core memory
13ab2fb569 s390-bios: Decouple channel i/o logic from virtio
634aaae0e9 s390-bios: Clean up cio.h
983db7d6f6 s390-bios: Factor finding boot device out of virtio code path
37c8283d8b s390-bios: Extend find_dev() for non-virtio devices
986462d0c6 s390-bios: decouple common boot logic from virtio
6eecc37451 s390-bios: decouple cio setup from virtio
bab9fd0907 s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit bab9fd090720 (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit 6eecc3745137 (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 986462d0c69c (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit 37c8283d8bde (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit 983db7d6f6e6 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit 634aaae0e93d (s390-bios: Clean up cio.h)
7/16 Checking commit 13ab2fb56962 (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit 6753adcac48a (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit c689028ed00a (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit 88f012130413 (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit f7fff67468f5 (s390-bios: cio error handling)
12/16 Checking commit 45b1810ae5c8 (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit 9add6dde7e5b (s390-b

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com -> 
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Switched to a new branch 'test'
9b84ebcc24 s390-bios: dasd-ipl: Use control unit type to customize error data
c9372490a1 s390-bios: Support booting from real dasd device
47171b2cdd s390-bios: Add channel command codes/structs needed for dasd-ipl
6f2050908e s390-bios: Use control unit type to determine boot method
0f97bb921e s390-bios: Refactor virtio to run channel programs via cio
d2c9f6cce7 s390-bios: cio error handling
f298cecd8f s390-bios: Support for running format-0/1 channel programs
dfdc554721 s390-bios: ptr2u32 and u32toptr
1b096b1bf8 s390-bios: Map low core memory
3be0b00270 s390-bios: Decouple channel i/o logic from virtio
e6032c6187 s390-bios: Clean up cio.h
12d9848de1 s390-bios: Factor finding boot device out of virtio code path
db71bdf357 s390-bios: Extend find_dev() for non-virtio devices
80c8b669bd s390-bios: decouple common boot logic from virtio
cdd504e999 s390-bios: decouple cio setup from virtio
bc57bb5989 s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit bc57bb598935 (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit cdd504e99929 (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 80c8b669bd0a (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit db71bdf3578b (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit 12d9848de1f4 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit e6032c61879f (s390-bios: Clean up cio.h)
7/16 Checking commit 3be0b0027017 (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit 1b096b1bf8e3 (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit dfdc55472161 (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit f298cecd8f83 (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit d2c9f6cce7ce (s390-bios: cio error handling)
12/16 Checking commit 0f97bb921e27 (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit 6f2050908e93 (s390-b

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com -> 
patchew/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Switched to a new branch 'test'
0a9e3c7c9c s390-bios: dasd-ipl: Use control unit type to customize error data
7ef97319b7 s390-bios: Support booting from real dasd device
ba2ef41e10 s390-bios: Add channel command codes/structs needed for dasd-ipl
33263b448e s390-bios: Use control unit type to determine boot method
24fc2d1e7d s390-bios: Refactor virtio to run channel programs via cio
b1dca5b66a s390-bios: cio error handling
5a87891a44 s390-bios: Support for running format-0/1 channel programs
c1e4f88640 s390-bios: ptr2u32 and u32toptr
2cc70e81c6 s390-bios: Map low core memory
62a450c7a8 s390-bios: Decouple channel i/o logic from virtio
d907f80f02 s390-bios: Clean up cio.h
0dda9ad2ae s390-bios: Factor finding boot device out of virtio code path
d91d27f0bf s390-bios: Extend find_dev() for non-virtio devices
8d085339e8 s390-bios: decouple common boot logic from virtio
f698064311 s390-bios: decouple cio setup from virtio
7a8011e385 s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit 7a8011e38589 (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit f6980643114b (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 8d085339e8d1 (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit d91d27f0bf15 (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit 0dda9ad2aee5 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit d907f80f026e (s390-bios: Clean up cio.h)
7/16 Checking commit 62a450c7a85d (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit 2cc70e81c6ae (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit c1e4f886404f (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit 5a87891a44c6 (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit b1dca5b66a3e (s390-bios: cio error handling)
12/16 Checking commit 24fc2d1e7d93 (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit 33263b448e9e (s390-b

Re: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel] [PATCH v3 00/16] s390: vfio-ccw dasd ipl support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
2b789b1c10 s390-bios: dasd-ipl: Use control unit type to customize error data
f91457aeef s390-bios: Support booting from real dasd device
3071ef3fd7 s390-bios: Add channel command codes/structs needed for dasd-ipl
bd9ebd495d s390-bios: Use control unit type to determine boot method
72c5351cf3 s390-bios: Refactor virtio to run channel programs via cio
48463c91d1 s390-bios: cio error handling
5a6410ee3c s390-bios: Support for running format-0/1 channel programs
87b21a627b s390-bios: ptr2u32 and u32toptr
6b4c168d0b s390-bios: Map low core memory
1579052645 s390-bios: Decouple channel i/o logic from virtio
6ed6d43be1 s390-bios: Clean up cio.h
49cafd73b0 s390-bios: Factor finding boot device out of virtio code path
9bcc2ca566 s390-bios: Extend find_dev() for non-virtio devices
9baff8187e s390-bios: decouple common boot logic from virtio
8ea363fa83 s390-bios: decouple cio setup from virtio
8ddaab89e7 s390 vfio-ccw: Add bootindex property and IPLB data

=== OUTPUT BEGIN ===
1/16 Checking commit 8ddaab89e767 (s390 vfio-ccw: Add bootindex property and 
IPLB data)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#205: 
new file mode 100644

total: 0 errors, 1 warnings, 181 lines checked

Patch 1/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/16 Checking commit 8ea363fa8353 (s390-bios: decouple cio setup from virtio)
3/16 Checking commit 9baff8187ec5 (s390-bios: decouple common boot logic from 
virtio)
ERROR: externs should be avoided in .c files
#31: FILE: pc-bios/s390-ccw/main.c:19:
+IplParameterBlock iplb __attribute__((__aligned__(PAGE_SIZE)));

total: 1 errors, 0 warnings, 65 lines checked

Patch 3/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/16 Checking commit 9bcc2ca566bc (s390-bios: Extend find_dev() for non-virtio 
devices)
5/16 Checking commit 49cafd73b044 (s390-bios: Factor finding boot device out of 
virtio code path)
6/16 Checking commit 6ed6d43be161 (s390-bios: Clean up cio.h)
7/16 Checking commit 1579052645a0 (s390-bios: Decouple channel i/o logic from 
virtio)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 122 lines checked

Patch 7/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/16 Checking commit 6b4c168d0bba (s390-bios: Map low core memory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 116 lines checked

Patch 8/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/16 Checking commit 87b21a627bda (s390-bios: ptr2u32 and u32toptr)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 16 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit 5a6410ee3ce0 (s390-bios: Support for running format-0/1 
channel programs)
11/16 Checking commit 48463c91d1ab (s390-bios: cio error handling)
12/16 Checking commit 72c5351cf34d (s390-bios: Refactor virtio to run channel 
programs via cio)
WARNING: line over 80 characters
#103: FILE: pc-bios/s390-ccw/virtio.c:298:
+run_ccw(vdev, CCW_CMD_READ_VQ_CONF, &config, sizeof(config), 
false) == 0,

WARNING: line over 80 characters
#116: FILE: pc-bios/s390-ccw/virtio.c:308:
+run_ccw(vdev, CCW_CMD_WRITE_STATUS, &status, sizeof(status), false) == 
0,

total: 0 errors, 2 warnings, 107 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit bd9ebd495d0b (s390-bios: Use control unit type to 
determine boot method)
14/16 Checking commit 3071ef3fd73d (s390-bios: Add channel command 
codes/structs needed for dasd-ipl)
15/16 Checking commit f91457aeef9b (s390-bios: S

Re: [Qemu-devel] [PATCH v2 00/32] s390x/tcg: Vector Instruction Support Part 1

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190301115413.27153-1-da...@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190301115413.27153-1-da...@redhat.com
Subject: [Qemu-devel] [PATCH v2 00/32] s390x/tcg: Vector Instruction Support 
Part 1

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]patchew/20190301163518.20702-1-stefa...@redhat.com 
-> patchew/20190301163518.20702-1-stefa...@redhat.com
Switched to a new branch 'test'
84850ebbe5 s390x/tcg: Implement VECTOR UNPACK *
4a4475ac0e s390x/tcg: Implement VECTOR STORE WITH LENGTH
ec74de772b s390x/tcg: Implement VECTOR STORE MULTIPLE
5e3a3ea905 s390x/tcg: Implement VECTOR STORE ELEMENT
e3db4b961f s390x/tcg: Implement VECTOR STORE
099c3b979c s390x/tcg: Provide probe_write helper
9fa21c4255 s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
70120ed4af s390x/tcg: Implement VECTOR SELECT
b0a62b201e s390x/tcg: Implement VECTOR SCATTER ELEMENT
3db62903ba s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
01235266a7 s390x/tcg: Implement VECTOR REPLICATE
ca3a745319 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
bf493cb73c s390x/tcg: Implement VECTOR PERMUTE
093ba1a6ff s390x/tcg: Implement VECTOR PACK *
5e6bf1f928 s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
d473c40eab s390x/tcg: Implement VECTOR LOAD WITH LENGTH
46210eab13 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
d07ab92ed5 s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
231b505f97 s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
728a1ef5b4 s390x/tcg: Implement VECTOR LOAD MULTIPLE
7cb070298d s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
96bd2799d1 s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
bb4dfe8dff s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
305d58aff1 s390x/tcg: Implement VECTOR LOAD ELEMENT
e7e51bb4e4 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
8b2082138f s390x/tcg: Implement VECTOR LOAD
b3fb39d42c s390x/tcg: Implement VECTOR GENERATE MASK
7ab6a198f6 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
8d65a412c5 s390x/tcg: Implement VECTOR GATHER ELEMENT
3f2a134615 s390x/tcg: Utilities for vector instruction helpers
6270c25595 s390x/tcg: Check vector register instructions at central point
5cd350e99f s390x/tcg: Define vector instruction formats

=== OUTPUT BEGIN ===
1/32 Checking commit 5cd350e99f98 (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 6270c2559553 (s390x/tcg: Check vector register 
instructions at central point)
3/32 Checking commit 3f2a134615d7 (s390x/tcg: Utilities for vector instruction 
helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

total: 0 errors, 1 warnings, 128 lines checked

Patch 3/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 8d65a412c5dd (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56: 
new file mode 100644

total: 0 errors, 1 warnings, 155 lines checked

Patch 4/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit 7ab6a198f644 (s390x/tcg: Implement VECTOR GENERATE BYTE 
MASK)
6/32 Checking commit b3fb39d42caf (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit 8b2082138f01 (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit e7e51bb4e48e (s390x/tcg: Implement VECTOR LOAD AND 
REPLICATE)
9/32 Checking commit 305d58aff1d0 (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit bb4dfe8dff05 (s390x/tcg: Implement VECTOR LOAD ELEMENT 
IMMEDIATE)
11/32 Checking commit 96bd2799d11a (s390x/tcg: Implement VECTOR LOAD GR FROM VR 
ELEMENT)
12/32 Checking commit 7cb070298dba (s390x/tcg: Implement VECTOR LOAD LOGICAL 
ELEMENT AND ZERO)
13/32 Checking commit 728a1ef5b4da (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 231b505f974f (s390x/tcg: Implement VECTOR LOAD TO BLOCK 
BOUNDARY)
15/32 Checking commit d07ab92ed56c (s390x/tcg: Implement VECTOR LOAD VR ELEMENT 
FROM GR)
16/32 Checking commit 46210eab13ff (s390x/tcg: Implement VECTOR LOAD VR FROM 
GRS DISJOINT)
17/32 Checking commit d473c40eab43 (s390x/tcg: Implement VECTOR LOAD WITH 
LENGTH)
18/32 Checking commit 5e6bf1f92827 (s390x/tcg: Implement VECTOR MERGE 
(HIGH|LOW))
19/32 Checking commit 093ba1a6fffc (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:1

Re: [Qemu-devel] [PATCH] usb-mtp: Fix build with gcc 9

[Bandan Das]

Greg Kurz  writes:
...
>> 
>> I think there's an underlying problem with this code which we
>> should deal with differently. The 'dataset' local in this
>> file is (I think) pointing at on-the-wire information from
>> the USB device, but we're treating it as an array of
>> host-order uint16_t values. Is this really correct on a
>> big-endian host ?
>
> I don't know much about usb-mtp and the MTP spec says:
>
> https://theta360blog.files.wordpress.com/2016/04/mtpforusb-ifv1-1.pdf
>
> 3.1.1 Multi-byte Data
>
> The standard format for multi-byte data in this specification is
> big-endian. That is, the bits within a byte will be read such that
> the most significant byte is read first. The actual multi-byte data
> sent over the transport may not necessarily adhere to this same
> format, and the actual multi-byte data used on the devices may also
> use a different multi-byte format. The big-endian convention only
> applies within this document, except where otherwise stated.
>
> So I'm not sure about what the code should really do here... :-\
>

If I remember correctly, with USB transport, multibyte values are
little endian and it supersedes the MTP spec? (which is why the code works
as expected on a little endian host). As Peter said, some byte swapping
is probably needed for this to work on big endian hosts.

>> Do we do the right thing if we are
>> passed a malicious USB packet that ends halfway through a
>> utf16_t character, or do we index off the end of the packet
>> data ?
>> 
>
> Can you elaborate ?
>
>> I think that we should define the "filename" field in
>> ObjectInfo to be a uint8_t array, make utf16_to_str()
>> take a uint8_t* for its data array, and have it do the
>> reading of data from the array with lduw_he_p(), which
>> can handle accessing unaligned data.
>> 
>> We should also check what the endianness of other fields in
>> the ObjectInfo struct is (eg "format" and "size" and see
>> whether we should be doing byte swapping here.
>> 
>
> I don't have any idea on that... the code just seems to assume
> everything is host endian.
>
>> PS: it is a bit confusing that in this function the local
>> variable "dataset" is a pointer to a struct of entirely
>> different type to the one that s->dataset is.
>> 
>
> Maybe Gerd or Bandan can comment on that.
>
>> thanks
>> -- PMM

[Qemu-devel] [PATCH] target/arm: Fix PC test for LDM (exception return)

[Richard Henderson]

Found by inspection: Rn is the base register against which the
load began; I is the register within the mask being processed.
The exception return should of course be procesed from the loaded PC.

Signed-off-by: Richard Henderson 
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f7f5b95aa..ad879e3480 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10612,7 +10612,7 @@ static void disas_arm_insn(DisasContext *s, unsigned 
int insn)
 } else if (i == rn) {
 loaded_var = tmp;
 loaded_base = 1;
-} else if (rn == 15 && exc_return) {
+} else if (i == 15 && exc_return) {
 store_pc_exc_ret(s, tmp);
 } else {
 store_reg_from_load(s, i, tmp);
-- 
2.17.2

Re: [Qemu-devel] [PATCH v11 01/10] hw/arm/boot: introduce fdt_add_memory_node helper

[Richard Henderson]

On 3/1/19 5:47 AM, Eric Auger wrote:
> From: Shameer Kolothum 
> 
> We introduce an helper to create a memory node.
> 
> Signed-off-by: Eric Auger 
> Signed-off-by: Shameer Kolothum 
> Reviewed-by: Igor Mammedov 
> 
> ---
> v7 -> v8:
> - Added Igor's R-b
> 
> v6 -> v7:
> - msg error in the caller
> - add comment about NUMA ID
> ---
>  hw/arm/boot.c | 54 ---
>  1 file changed, 34 insertions(+), 20 deletions(-)

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v2 3/5] contrib: gitdm: add more individual contributors

[Richard Henderson]

On 3/1/19 2:03 AM, Alex Bennée wrote:
> I know Richard's is right because I asked him in the pub. I'm guessing
> Fredrik's based on the fact I vaguely remember an Atari demo. The
> others I attributed to academic institutions last time I posted so
> have moved them to individuals as requested.
> 
> Cc: Richard Henderson 
> Cc: Fredrik Noring 
> Cc: Samuel Thibault 
> Cc: Aurelien Jarno 
> Cc: BALATON Zoltan 
> Signed-off-by: Alex Bennée 
> ---
>  contrib/gitdm/group-map-individuals | 5 +
>  1 file changed, 5 insertions(+)

Acked-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v3 3/7] block/dirty-bitmaps: add block_dirty_bitmap_check function

[Eric Blake]

On 3/1/19 2:03 PM, Eric Blake wrote:
> On 3/1/19 1:57 PM, John Snow wrote:
> 
 +if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
 +error_setg(errp, "Bitmap '%s' is currently in use by another"
 +   " operation and cannot be used", bitmap->name);
>>>
>>> Split before space,
>>>
> 
 +error_setg(errp, "Bitmap '%s' is inconsistent and cannot be used",
 +   bitmap->name);
 +error_append_hint(errp, "Try block-dirty-bitmap-remove to delete "
 +  "this bitmap from disk");
>>>
>>> split after space.  Looks inconsistent within a single function (pardon
>>> the pun :)
>>>
>>
>> Ah... I've never known how to split strings. In fact, does anyone?
>> I'll address this either in staging or as a follow-up, as I assume
>> Vladimir will have some comments for me.
> 
> I don't care which way you go. git says we have both styles with enough
> frequency that I wouldn't rule out the other style in HACKING.  But it
> also says split after space seems more common, if you trust my regex:
> 

Shoot, I was in the wrong directory when I counted. Trying again, this
time on qemu.git:

$ git grep '"[^"]* "$' | wc
   1566   13019  135245
$ git grep '^[[:space:]]*" [^"]*"' | wc
   1714   11772  130881

and now the numbers favor split before space.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH v3 03/10] target/arm: Implement ARMv8.0-PredInv

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h| 13 ++-
 target/arm/cpu.c|  1 +
 target/arm/cpu64.c  |  2 ++
 target/arm/helper.c | 55 +
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 361e51143c..c822f94236 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_R   (1U << 9) /* up to v6; RAZ in v7 */
 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
 #define SCTLR_F   (1U << 10) /* up to v6 */
-#define SCTLR_SW  (1U << 10) /* v7, RES0 in v8 */
+#define SCTLR_SW  (1U << 10) /* v7 */
+#define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */
 #define SCTLR_Z   (1U << 11) /* in v7, RES1 in v8 */
 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
 #define SCTLR_I   (1U << 12)
@@ -3312,6 +3313,11 @@ static inline bool isar_feature_aa32_sb(const 
ARMISARegisters *id)
 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
 }
 
+static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
+{
+return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
 /*
@@ -3455,6 +3461,11 @@ static inline bool isar_feature_aa64_sb(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
 }
 
+static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
+}
+
 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
 {
 /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ef069c268d..96f0ff0ec7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2022,6 +2022,7 @@ static void arm_max_initfn(Object *obj)
 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 cpu->isar.id_isar6 = t;
 
 t = cpu->id_mmfr4;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6788c0f6ff..87337b6385 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -319,6 +319,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
+t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 cpu->isar.id_aa64isar1 = t;
 
 t = cpu->isar.id_aa64pfr0;
@@ -351,6 +352,7 @@ static void aarch64_max_initfn(Object *obj)
 u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 u = FIELD_DP32(u, ID_ISAR6, SB, 1);
+u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 cpu->isar.id_isar6 = u;
 
 /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 49ff79a146..2607d39ad1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5719,6 +5719,50 @@ static const ARMCPRegInfo pauth_reginfo[] = {
 };
 #endif
 
+static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+int el = arm_current_el(env);
+
+if (el == 0) {
+uint64_t sctlr = arm_sctlr(env, el);
+if (!(sctlr & SCTLR_EnRCTX)) {
+return CP_ACCESS_TRAP;
+}
+} else if (el == 1) {
+uint64_t hcr = arm_hcr_el2_eff(env);
+if (hcr & HCR_NV) {
+return CP_ACCESS_TRAP_EL2;
+}
+}
+return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo predinv_reginfo[] = {
+{ .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
+  .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+{ .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
+  .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+{ .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
+  .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+/*
+ * Note the AArch32 opcodes have a different OPC1.
+ */
+{ .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
+  .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+{ .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
+  .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+{ .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
+  .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
+  .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
+REGINFO_SENTIN

Re: [Qemu-devel] [PATCH v3 6/7] block/dirty-bitmaps: disallow busy bitmaps as merge source

[John Snow]

On 3/1/19 2:57 PM, Eric Blake wrote:
> On 3/1/19 1:48 PM, John Snow wrote:
> 
>>> I understand forbidding inconsistent sources (because if the source is
>>> potentially missing bits, then the merge destination will also be
>>> missing bits and thus be inconsistent), but why forbid busy?  If I've
>>> associated a bitmap with an NBD server (making it busy), it is still
>>> readable, and so I should still be able to merge its bits into another copy.
>>>
>>
>> True, do you rely on this, though?
> 
> Not in my current libvirt code (as I create a temporary bitmap to hand
> to NBD, since it may be the merge of one or more disabled bitmaps in a
> differential backup case), so being tighter for now and relaxing later
> if we DO come up with a use is acceptable.
> 
>>
>> I was working from a space of "busy" meant "actively in-use by an
>> operation, and COULD change" so I was forbidding it out of good hygiene.
>>
>> Clearly the ones in-use by NBD are actually static and unchanging, so
>> it's safer -- but that might not be true for push backups, where you
>> might not actually be getting what you think you are, because of the
>> bifurcated nature of those bitmaps.
> 
> Oh, good point, especially after you worked so hard to merge
> locked/frozen into a single status - you WILL miss the bits from the
> successor (unless we teach the merge algorithm to pull in the busy
> bitmap's bits AND all the bits of its successors - but that feels like a
> lot of work if we don't have a client needing it now).  Okay, with the
> extra justification mentioned in the commit message,
> 

(Though I am being a little fast and loose here: when we split a bitmap,
the top-level one that retains the name actually stays unchanging and
the child bitmap is the one that starts accruing writes from a blank
canvas, but that STILL may not be what you expect when you choose it as
a merge source, however.)

>>
>> If this causes a problem for you in the short-term I will simply roll
>> this back, but it stands out to me.
>>
>> (I can't stop myself from trying to protect the user from themselves.
>> It's clearly a recurring theme in my design and reviews.)
>>
 diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
 index 769668ccdc..8403c9981d 100644
 --- a/block/dirty-bitmap.c
 +++ b/block/dirty-bitmap.c
 @@ -825,6 +825,9 @@ void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, 
 const BdrvDirtyBitmap *src,
  goto out;
  }
  
 +if (bdrv_dirty_bitmap_check(src, BDRV_BITMAP_ALLOW_RO, errp)) {
>>>
>>> Thus, I think this should be BDRV_BITMAP_INCONSISTENT.
> 
> then I retract my complaint, and the code is acceptable for now.
> 
> Reviewed-by: Eric Blake 
> 

We could always split it back out later, but in basic terms for
permissions and user perspective, "in use" seems robust enough of a
resolution. (It might be safe to read, it might not be, who knows --
it's in use.)

If it really comes to a point, we can always re-add a new status bit to
let the end-user know if they're working with a bifurcated (I have to
use weird vocabulary words sometimes) bitmap but at the moment it seems
very safely an implementation detail.

You can also check that for "enabled" bitmap as reported back to user
via QAPI I check to see if the parent OR child is enabled and report
that cumulatively as "enabled", because together they are "effectively"
enabled.

--js

[Qemu-devel] [PATCH v3 04/10] target/arm: Split helper_msr_i_pstate into 3

[Richard Henderson]

The EL0+UMA check is unique to DAIF.  While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA.  Avoid
the unconditional write to pc and use raise_exception_ra to unwind.

Signed-off-by: Richard Henderson 
---
 target/arm/helper-a64.h|  3 +++
 target/arm/helper.h|  1 -
 target/arm/internals.h | 15 ++
 target/arm/helper-a64.c| 30 +++
 target/arm/op_helper.c | 42 --
 target/arm/translate-a64.c | 41 ++---
 6 files changed, 73 insertions(+), 59 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index aff8d6c9f3..a915c1247f 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -19,6 +19,9 @@
 DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
 DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_2(msr_i_spsel, void, env, i32)
+DEF_HELPER_2(msr_i_daifset, void, env, i32)
+DEF_HELPER_2(msr_i_daifclear, void, env, i32)
 DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
 DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
 DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index d363904278..6f0f386926 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
 DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
 DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
 
-DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)
 DEF_HELPER_1(clear_pstate_ss, void, env)
 
 DEF_HELPER_2(get_r13_banked, i32, env, i32)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a4bd1becb7..587a1ddf58 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, 
uint64_t va,
 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data);
 
+static inline int exception_target_el(CPUARMState *env)
+{
+int target_el = MAX(1, arm_current_el(env));
+
+/*
+ * No such thing as secure EL1 if EL3 is aarch32,
+ * so update the target EL to EL3 in this case.
+ */
+if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
+target_el = 3;
+}
+
+return target_el;
+}
+
 #endif
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 70850e564d..796ef34b55 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x)
 return revbit64(x);
 }
 
+void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
+{
+update_spsel(env, imm);
+}
+
+static void daif_check(CPUARMState *env, uint32_t op,
+   uint32_t imm, uintptr_t ra)
+{
+/* DAIF update to PSTATE. This is OK from EL0 only if UMA is set.  */
+if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
+raise_exception_ra(env, EXCP_UDEF,
+   syn_aa64_sysregtrap(0, extract32(op, 0, 3),
+   extract32(op, 3, 3), 4,
+   imm, 0x1f, 0),
+   exception_target_el(env), ra);
+}
+}
+
+void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm)
+{
+daif_check(env, 0x1e, imm, GETPC());
+env->daif |= (imm << 6) & PSTATE_DAIF;
+}
+
+void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm)
+{
+daif_check(env, 0x1f, imm, GETPC());
+env->daif &= ~((imm << 6) & PSTATE_DAIF);
+}
+
 /* Convert a softfloat float_relation_ (as returned by
  * the float*_compare functions) to the correct ARM
  * NZCV flag state.
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index c998eadfaa..c5721a866d 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, 
uint32_t syndrome,
 cpu_loop_exit_restore(cs, ra);
 }
 
-static int exception_target_el(CPUARMState *env)
-{
-int target_el = MAX(1, arm_current_el(env));
-
-/* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
- * to EL3 in this case.
- */
-if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
-target_el = 3;
-}
-
-return target_el;
-}
-
 uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
   uint32_t maxindex)
 {
@@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 return res;
 }
 
-void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
-{
-/* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
- * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
- * to catch that case

[Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM

[Richard Henderson]

Tested-by: Laurent Desnogues 
Signed-off-by: Richard Henderson 
---
v2: Update ID_AA64ISAR0.TS.
---
 target/arm/cpu.h   |  5 
 target/arm/cpu64.c |  2 +-
 target/arm/translate-a64.c | 58 ++
 3 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fc2909ea6d..a7aaec63d7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
 }
 
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+}
+
 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
 {
 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fcf79321e2..9fe0844a82 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
+t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 cpu->isar.id_aa64isar0 = t;
 
 t = cpu->isar.id_aa64isar1;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 49a09b58e3..c2b9e800c8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t insn,
 }
 }
 
+static void gen_xaflag(void)
+{
+TCGv_i32 z = tcg_temp_new_i32();
+
+tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
+
+/*
+ * (!C & !Z) << 31
+ * (!(C | Z)) << 31
+ * ~((C | Z) << 31)
+ * ~-(C | Z)
+ * (C | Z) - 1
+ */
+tcg_gen_or_i32(cpu_NF, cpu_CF, z);
+tcg_gen_subi_i32(cpu_NF, cpu_NF, 1);
+
+/* !(Z & C) */
+tcg_gen_and_i32(cpu_ZF, z, cpu_CF);
+tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1);
+
+/* (!C & Z) << 31 -> -(Z & ~C) */
+tcg_gen_andc_i32(cpu_VF, z, cpu_CF);
+tcg_gen_neg_i32(cpu_VF, cpu_VF);
+
+/* C | Z */
+tcg_gen_or_i32(cpu_CF, cpu_CF, z);
+
+tcg_temp_free_i32(z);
+}
+
+static void gen_axflag(void)
+{
+tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
+tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
+
+/* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
+tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF);
+
+tcg_gen_movi_i32(cpu_NF, 0);
+tcg_gen_movi_i32(cpu_VF, 0);
+}
+
 /* MSR (immediate) - move immediate to processor state field */
 static void handle_msr_i(DisasContext *s, uint32_t insn,
  unsigned int op1, unsigned int op2, unsigned int crm)
@@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
 s->base.is_jmp = DISAS_NEXT;
 break;
 
+case 0x01: /* XAFlag */
+if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+goto do_unallocated;
+}
+gen_xaflag();
+s->base.is_jmp = DISAS_NEXT;
+break;
+
+case 0x02: /* AXFlag */
+if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+goto do_unallocated;
+}
+gen_axflag();
+s->base.is_jmp = DISAS_NEXT;
+break;
+
 case 0x05: /* SPSel */
 if (s->current_el == 0) {
 goto do_unallocated;
-- 
2.17.2

[Qemu-devel] [PATCH v3 10/10] target/arm: Implement ARMv8.5-FRINT

[Richard Henderson]

Tested-by: Laurent Desnogues 
Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  5 ++
 target/arm/helper.h|  5 ++
 target/arm/cpu64.c |  1 +
 target/arm/translate-a64.c | 71 ++--
 target/arm/vfp_helper.c| 96 ++
 5 files changed, 173 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a7aaec63d7..5f23c62132 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3476,6 +3476,11 @@ static inline bool isar_feature_aa64_predinv(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
 }
 
+static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
+}
+
 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
 {
 /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 583adba9b0..a09566f795 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -683,6 +683,11 @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #include "helper-sve.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9fe0844a82..228906f267 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -321,6 +321,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
+t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 cpu->isar.id_aa64isar1 = t;
 
 t = cpu->isar.id_aa64pfr0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 94184ea5af..8907cc950a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5721,6 +5721,20 @@ static void handle_fp_1src_single(DisasContext *s, int 
opcode, int rd, int rn)
 case 0xf: /* FRINTI */
 gen_fpst = gen_helper_rints;
 break;
+case 0x10: /* FRINT32Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint32_s;
+break;
+case 0x11: /* FRINT32X */
+gen_fpst = gen_helper_frint32_s;
+break;
+case 0x12: /* FRINT64Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint64_s;
+break;
+case 0x13: /* FRINT64X */
+gen_fpst = gen_helper_frint64_s;
+break;
 default:
 g_assert_not_reached();
 }
@@ -5784,6 +5798,20 @@ static void handle_fp_1src_double(DisasContext *s, int 
opcode, int rd, int rn)
 case 0xf: /* FRINTI */
 gen_fpst = gen_helper_rintd;
 break;
+case 0x10: /* FRINT32Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint32_d;
+break;
+case 0x11: /* FRINT32X */
+gen_fpst = gen_helper_frint32_d;
+break;
+case 0x12: /* FRINT64Z */
+rmode = float_round_to_zero;
+gen_fpst = gen_helper_frint64_d;
+break;
+case 0x13: /* FRINT64X */
+gen_fpst = gen_helper_frint64_d;
+break;
 default:
 g_assert_not_reached();
 }
@@ -5920,6 +5948,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
 break;
 }
+
+case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
+if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
+unallocated_encoding(s);
+return;
+}
+/* fall through */
 case 0x0 ... 0x3:
 case 0x8 ... 0xc:
 case 0xe ... 0xf:
@@ -5929,14 +5964,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t 
insn)
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_single(s, opcode, rd, rn);
 break;
 case 1:
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_double(s, opcode, rd, rn);
 break;
 case 3:
@@ -5948,13 +5981,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t 
insn)
 if (!fp_access_check(s)) {
 return;
 }
-
 handle_fp_1src_half(s, opcode, rd, rn);
 break;
 default:
 unallocated_encoding(s);
 }
 break;
+
 default:
 unallocated_encoding(s);
 break;
@@ -9482,6 +9515,14 @@ static void handle_2misc_64(DisasContext *s, int opcode, 
bool u,
 case 0x59: /* FRINTX */
 

[Qemu-devel] [PATCH v3 06/10] target/arm: Rearrange disas_data_proc_reg

[Richard Henderson]

This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.

In particular, op2 == 0 is now more than just Add/sub (with carry).

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 98 ++
 1 file changed, 57 insertions(+), 41 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index eaeb43577d..12d2649c20 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4494,11 +4494,10 @@ static void disas_data_proc_3src(DisasContext *s, 
uint32_t insn)
 }
 
 /* Add/subtract (with carry)
- *  31 30 29 28 27 26 25 24 23 22 21  20  16  15   10  95 4   0
- * +--+--+--++--+-+--+-+
- * |sf|op| S| 1  1  0  1  0  0  0  0 |  rm  | opcode2 |  Rn  |  Rd |
- * +--+--+--++--+-+--+-+
- *[00]
+ *  31 30 29 28 27 26 25 24 23 22 21  20  16  15   10  95 4   0
+ * +--+--+--++--+-+--+-+
+ * |sf|op| S| 1  1  0  1  0  0  0  0 |  rm  | 0 0 0 0 0 0 |  Rn  |  Rd |
+ * +--+--+--++--+-+--+-+
  */
 
 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
@@ -4506,11 +4505,6 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
 unsigned int sf, op, setflags, rm, rn, rd;
 TCGv_i64 tcg_y, tcg_rn, tcg_rd;
 
-if (extract32(insn, 10, 6) != 0) {
-unallocated_encoding(s);
-return;
-}
-
 sf = extract32(insn, 31, 1);
 op = extract32(insn, 30, 1);
 setflags = extract32(insn, 29, 1);
@@ -5164,47 +5158,69 @@ static void disas_data_proc_2src(DisasContext *s, 
uint32_t insn)
 }
 }
 
-/* Data processing - register */
+/*
+ * Data processing - register
+ *  31  30 29  28  2521  20  16  10 0
+ * +--+---+--+---+---+-+---+---+-+
+ * |  |op0|  |op1| 1 0 1 | op2 |   |  op3  | |
+ * +--+---+--+---+---+-+---+---+-+
+ */
 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
 {
-switch (extract32(insn, 24, 5)) {
-case 0x0a: /* Logical (shifted register) */
-disas_logic_reg(s, insn);
-break;
-case 0x0b: /* Add/subtract */
-if (insn & (1 << 21)) { /* (extended register) */
-disas_add_sub_ext_reg(s, insn);
+int op0 = extract32(insn, 30, 1);
+int op1 = extract32(insn, 28, 1);
+int op2 = extract32(insn, 21, 4);
+int op3 = extract32(insn, 10, 6);
+
+if (!op1) {
+if (op2 & 8) {
+if (op2 & 1) {
+/* Add/sub (extended register) */
+disas_add_sub_ext_reg(s, insn);
+} else {
+/* Add/sub (shifted register) */
+disas_add_sub_reg(s, insn);
+}
 } else {
-disas_add_sub_reg(s, insn);
+/* Logical (shifted register) */
+disas_logic_reg(s, insn);
 }
-break;
-case 0x1b: /* Data-processing (3 source) */
-disas_data_proc_3src(s, insn);
-break;
-case 0x1a:
-switch (extract32(insn, 21, 3)) {
-case 0x0: /* Add/subtract (with carry) */
+return;
+}
+
+switch (op2) {
+case 0x0:
+switch (op3) {
+case 0x00: /* Add/subtract (with carry) */
 disas_adc_sbc(s, insn);
 break;
-case 0x2: /* Conditional compare */
-disas_cc(s, insn); /* both imm and reg forms */
-break;
-case 0x4: /* Conditional select */
-disas_cond_select(s, insn);
-break;
-case 0x6: /* Data-processing */
-if (insn & (1 << 30)) { /* (1 source) */
-disas_data_proc_1src(s, insn);
-} else {/* (2 source) */
-disas_data_proc_2src(s, insn);
-}
-break;
+
 default:
-unallocated_encoding(s);
-break;
+goto do_unallocated;
 }
 break;
+
+case 0x2: /* Conditional compare */
+disas_cc(s, insn); /* both imm and reg forms */
+break;
+
+case 0x4: /* Conditional select */
+disas_cond_select(s, insn);
+break;
+
+case 0x6: /* Data-processing */
+if (op0) {/* (1 source) */
+disas_data_proc_1src(s, insn);
+} else {  /* (2 source) */
+disas_data_proc_2src(s, insn);
+}
+break;
+case 0x8 ... 0xf: /* (3 source) */
+disas_data_proc_3src(s, insn);
+break;
+
 default:
+do_unallocated:
 unallocated_encoding(s);
 break;
 }
-- 
2.17.2

[Qemu-devel] [PATCH v3 09/10] target/arm: Restructure handle_fp_1src_{single, double}

[Richard Henderson]

This will allow sharing code that adjusts rmode beyond
the existing users.

Tested-by: Laurent Desnogues 
Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 90 +-
 1 file changed, 49 insertions(+), 41 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c2b9e800c8..94184ea5af 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5686,55 +5686,59 @@ static void handle_fp_1src_half(DisasContext *s, int 
opcode, int rd, int rn)
 /* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
+void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);
+TCGv_i32 tcg_op, tcg_res;
 TCGv_ptr fpst;
-TCGv_i32 tcg_op;
-TCGv_i32 tcg_res;
+int rmode = -1;
 
-fpst = get_fpstatus_ptr(false);
 tcg_op = read_fp_sreg(s, rn);
 tcg_res = tcg_temp_new_i32();
 
 switch (opcode) {
 case 0x0: /* FMOV */
 tcg_gen_mov_i32(tcg_res, tcg_op);
-break;
+goto done;
 case 0x1: /* FABS */
 gen_helper_vfp_abss(tcg_res, tcg_op);
-break;
+goto done;
 case 0x2: /* FNEG */
 gen_helper_vfp_negs(tcg_res, tcg_op);
-break;
+goto done;
 case 0x3: /* FSQRT */
 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
-break;
+goto done;
 case 0x8: /* FRINTN */
 case 0x9: /* FRINTP */
 case 0xa: /* FRINTM */
 case 0xb: /* FRINTZ */
 case 0xc: /* FRINTA */
-{
-TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-gen_helper_rints(tcg_res, tcg_op, fpst);
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-tcg_temp_free_i32(tcg_rmode);
+rmode = arm_rmode_to_sf(opcode & 7);
+gen_fpst = gen_helper_rints;
 break;
-}
 case 0xe: /* FRINTX */
-gen_helper_rints_exact(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rints_exact;
 break;
 case 0xf: /* FRINTI */
-gen_helper_rints(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rints;
 break;
 default:
-abort();
+g_assert_not_reached();
 }
 
-write_fp_sreg(s, rd, tcg_res);
-
+fpst = get_fpstatus_ptr(false);
+if (rmode >= 0) {
+TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+gen_fpst(tcg_res, tcg_op, fpst);
+gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+tcg_temp_free_i32(tcg_rmode);
+} else {
+gen_fpst(tcg_res, tcg_op, fpst);
+}
 tcg_temp_free_ptr(fpst);
+
+ done:
+write_fp_sreg(s, rd, tcg_res);
 tcg_temp_free_i32(tcg_op);
 tcg_temp_free_i32(tcg_res);
 }
@@ -5742,9 +5746,10 @@ static void handle_fp_1src_single(DisasContext *s, int 
opcode, int rd, int rn)
 /* Floating-point data-processing (1 source) - double precision */
 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
 {
+void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);
+TCGv_i64 tcg_op, tcg_res;
 TCGv_ptr fpst;
-TCGv_i64 tcg_op;
-TCGv_i64 tcg_res;
+int rmode = -1;
 
 switch (opcode) {
 case 0x0: /* FMOV */
@@ -5752,48 +5757,51 @@ static void handle_fp_1src_double(DisasContext *s, int 
opcode, int rd, int rn)
 return;
 }
 
-fpst = get_fpstatus_ptr(false);
 tcg_op = read_fp_dreg(s, rn);
 tcg_res = tcg_temp_new_i64();
 
 switch (opcode) {
 case 0x1: /* FABS */
 gen_helper_vfp_absd(tcg_res, tcg_op);
-break;
+goto done;
 case 0x2: /* FNEG */
 gen_helper_vfp_negd(tcg_res, tcg_op);
-break;
+goto done;
 case 0x3: /* FSQRT */
 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
-break;
+goto done;
 case 0x8: /* FRINTN */
 case 0x9: /* FRINTP */
 case 0xa: /* FRINTM */
 case 0xb: /* FRINTZ */
 case 0xc: /* FRINTA */
-{
-TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-gen_helper_rintd(tcg_res, tcg_op, fpst);
-
-gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-tcg_temp_free_i32(tcg_rmode);
+rmode = arm_rmode_to_sf(opcode & 7);
+gen_fpst = gen_helper_rintd;
 break;
-}
 case 0xe: /* FRINTX */
-gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rintd_exact;
 break;
 case 0xf: /* FRINTI */
-gen_helper_rintd(tcg_res, tcg_op, fpst);
+gen_fpst = gen_helper_rintd;
 break;
 default:
-abort();
+g_assert_not_reached();
 }
 
-write_fp_dreg(s, rd, tcg_res);
-
+fpst = get_fpstatus_ptr(false);
+if (rmode >= 0) {
+TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+

[Qemu-devel] [PATCH v3 01/10] target/arm: Split out arm_sctlr

[Richard Henderson]

Minimize the number of places that will need updating when
the virtual host extensions are added.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h| 26 --
 target/arm/helper.c |  8 ++--
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 36cd365efa..67b06bfad0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3042,11 +3042,20 @@ static inline bool arm_sctlr_b(CPUARMState *env)
 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
 }
 
+static inline uint64_t arm_sctlr(CPUARMState *env, int el)
+{
+if (el == 0) {
+/* FIXME: ARMv8.1-VHE S2 translation regime.  */
+return env->cp15.sctlr_el[1];
+} else {
+return env->cp15.sctlr_el[el];
+}
+}
+
+
 /* Return true if the processor is in big-endian mode. */
 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
 {
-int cur_el;
-
 /* In 32bit endianness is determined by looking at CPSR's E bit */
 if (!is_a64(env)) {
 return
@@ -3065,15 +3074,12 @@ static inline bool 
arm_cpu_data_is_big_endian(CPUARMState *env)
 arm_sctlr_b(env) ||
 #endif
 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
+} else {
+int cur_el = arm_current_el(env);
+uint64_t sctlr = arm_sctlr(env, cur_el);
+
+return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
 }
-
-cur_el = arm_current_el(env);
-
-if (cur_el == 0) {
-return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
-}
-
-return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 }
 
 #include "exec/cpu-all.h"
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1fa282a7fc..49ff79a146 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12854,12 +12854,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, 
target_ulong *pc,
 flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
 }
 
-if (current_el == 0) {
-/* FIXME: ARMv8.1-VHE S2 translation regime.  */
-sctlr = env->cp15.sctlr_el[1];
-} else {
-sctlr = env->cp15.sctlr_el[current_el];
-}
+sctlr = arm_sctlr(env, current_el);
+
 if (cpu_isar_feature(aa64_pauth, cpu)) {
 /*
  * In order to save space in flags, we record only whether
-- 
2.17.2

[Qemu-devel] [PATCH v3 02/10] target/arm: Implement ARMv8.0-SB

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   | 10 ++
 linux-user/elfload.c   |  1 +
 target/arm/cpu.c   |  1 +
 target/arm/cpu64.c |  2 ++
 target/arm/translate-a64.c | 14 ++
 target/arm/translate.c | 22 ++
 6 files changed, 50 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 67b06bfad0..361e51143c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3307,6 +3307,11 @@ static inline bool isar_feature_aa32_fhm(const 
ARMISARegisters *id)
 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
 }
 
+static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
+{
+return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
 /*
@@ -3445,6 +3450,11 @@ static inline bool isar_feature_aa64_pauth(const 
ARMISARegisters *id)
  FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
 }
 
+static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
+}
+
 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
 {
 /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index b9f7cbbdc1..6cfebe1446 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -604,6 +604,7 @@ static uint32_t get_elf_hwcap(void)
 GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
 GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
 GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
+GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
 
 #undef GET_FEATURE_ID
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 54b61f917b..ef069c268d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2021,6 +2021,7 @@ static void arm_max_initfn(Object *obj)
 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 cpu->isar.id_isar6 = t;
 
 t = cpu->id_mmfr4;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1b0c427277..6788c0f6ff 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
+t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 cpu->isar.id_aa64isar1 = t;
 
 t = cpu->isar.id_aa64pfr0;
@@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj)
 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
+u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 cpu->isar.id_isar6 = u;
 
 /*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3c8eaf089..4aa5a307e4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t insn,
 reset_btype(s);
 gen_goto_tb(s, 0, s->pc);
 return;
+
+case 7: /* SB */
+if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {
+goto do_unallocated;
+}
+/*
+ * TODO: There is no speculation barrier opcode for TCG;
+ * MB and end the TB instead.
+ */
+tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+gen_goto_tb(s, 0, s->pc);
+return;
+
 default:
+do_unallocated:
 unallocated_encoding(s);
 return;
 }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f7f5b95aa..61adefb328 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9282,6 +9282,17 @@ static void disas_arm_insn(DisasContext *s, unsigned int 
insn)
  */
 gen_goto_tb(s, 0, s->pc & ~1);
 return;
+case 7: /* sb */
+if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
+goto illegal_op;
+}
+/*
+ * TODO: There is no speculation barrier opcode
+ * for TCG; MB and end the TB instead.
+ */
+tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+gen_goto_tb(s, 0, s->pc & ~1);
+return;
 default:
 goto illegal_op;
 }
@@ -11900,6 +11911,17 @@ static void disas_thumb2_insn(DisasContext *s, 
uint32_t insn)
  */
 gen_goto_tb(s, 0, s->pc & ~1);
 break;
+case 7: /* sb */
+if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
+goto illegal_op;
+  

[Qemu-devel] [PATCH v3 07/10] target/arm: Implement ARMv8.4-CondM

[Richard Henderson]

Tested-by: Laurent Desnogues 
Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  5 ++
 linux-user/elfload.c   |  1 +
 target/arm/cpu64.c |  1 +
 target/arm/translate-a64.c | 97 +-
 4 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c822f94236..fc2909ea6d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3431,6 +3431,11 @@ static inline bool isar_feature_aa64_fhm(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
 }
 
+static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
+}
+
 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
 {
 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 6cfebe1446..6e8762b40d 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -605,6 +605,7 @@ static uint32_t get_elf_hwcap(void)
 GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
 GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
 GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
+GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
 
 #undef GET_FEATURE_ID
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 87337b6385..fcf79321e2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -309,6 +309,7 @@ static void aarch64_max_initfn(Object *obj)
 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
+t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
 cpu->isar.id_aa64isar0 = t;
 
 t = cpu->isar.id_aa64isar1;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 12d2649c20..49a09b58e3 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1657,6 +1657,14 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
 s->base.is_jmp = DISAS_TOO_MANY;
 
 switch (op) {
+case 0x00: /* CFINV */
+if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
+goto do_unallocated;
+}
+tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
+s->base.is_jmp = DISAS_NEXT;
+break;
+
 case 0x05: /* SPSel */
 if (s->current_el == 0) {
 goto do_unallocated;
@@ -1710,7 +1718,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt)
 }
 
 static void gen_set_nzcv(TCGv_i64 tcg_rt)
-
 {
 TCGv_i32 nzcv = tcg_temp_new_i32();
 
@@ -4529,6 +4536,82 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
 }
 }
 
+/* Rotate right into flags
+ *  31 30 2921   15  10  5  4  0
+ * +--+--+--+-++---+--+--+--+
+ * |sf|op| S| 1 1 0 1 0 0 0 0 |  imm6  | 0 0 0 0 1 |  Rn  |o2| mask |
+ * +--+--+--+-++---+--+--+--+
+ */
+static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
+{
+int mask = extract32(insn, 0, 4);
+int o2 = extract32(insn, 4, 1);
+int rn = extract32(insn, 5, 5);
+int imm6 = extract32(insn, 15, 6);
+int sf_op_s = extract32(insn, 29, 3);
+TCGv_i64 tcg_rn;
+TCGv_i32 nzcv;
+
+if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {
+unallocated_encoding(s);
+return;
+}
+
+tcg_rn = read_cpu_reg(s, rn, 1);
+tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6);
+
+nzcv = tcg_temp_new_i32();
+tcg_gen_extrl_i64_i32(nzcv, tcg_rn);
+
+if (mask & 8) { /* N */
+tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3);
+}
+if (mask & 4) { /* Z */
+tcg_gen_not_i32(cpu_ZF, nzcv);
+tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4);
+}
+if (mask & 2) { /* C */
+tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1);
+}
+if (mask & 1) { /* V */
+tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0);
+}
+
+tcg_temp_free_i32(nzcv);
+}
+
+/* Evaluate into flags
+ *  31 30 292115   1410  5  4  0
+ * +--+--+--+-+-++-+--+--+--+
+ * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 |  Rn  |o3| mask |
+ * +--+--+--+-+-++-+--+--+--+
+ */
+static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
+{
+int o3_mask = extract32(insn, 0, 5);
+int rn = extract32(insn, 5, 5);
+int o2 = extract32(insn, 15, 6);
+int sz = extract32(insn, 14, 1);
+int sf_op_s = extract32(insn, 29, 3);
+TCGv_i32 tmp;
+int shift;
+
+if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
+!dc_isar_feature(aa64_condm_4, s)) {
+unallocated_encoding(s);
+return;
+}
+shift = sz ? 16 : 24;  /* SETF16 or SETF8 */
+
+tmp = tcg_temp_new_i32();
+tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));
+tcg_gen_shli_i32(cpu_NF, t

[Qemu-devel] [PATCH v3 00/10] target/arm: SB, PredInv, CondM, FRINT extensions

[Richard Henderson]

These 5 extensions are small, and all previous editions have
minor patch conflicts with master.  Therefore, rebase them all
together for simplicity.


r~


Richard Henderson (10):
  target/arm: Split out arm_sctlr
  target/arm: Implement ARMv8.0-SB
  target/arm: Implement ARMv8.0-PredInv
  target/arm: Split helper_msr_i_pstate into 3
  target/arm: Add set/clear_pstate_bits, share gen_ss_advance
  target/arm: Rearrange disas_data_proc_reg
  target/arm: Implement ARMv8.4-CondM
  target/arm: Implement ARMv8.5-CondM
  target/arm: Restructure handle_fp_1src_{single,double}
  target/arm: Implement ARMv8.5-FRINT

 target/arm/cpu.h   |  64 -
 target/arm/helper-a64.h|   3 +
 target/arm/helper.h|   8 +-
 target/arm/internals.h |  15 ++
 target/arm/translate.h |  34 +++
 linux-user/elfload.c   |   2 +
 target/arm/cpu.c   |   2 +
 target/arm/cpu64.c |   6 +
 target/arm/helper-a64.c|  30 +++
 target/arm/helper.c|  63 -
 target/arm/op_helper.c |  47 
 target/arm/translate-a64.c | 476 -
 target/arm/translate.c |  33 ++-
 target/arm/vfp_helper.c|  96 
 14 files changed, 688 insertions(+), 191 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH v3 05/10] target/arm: Add set/clear_pstate_bits, share gen_ss_advance

[Richard Henderson]

We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Signed-off-by: Richard Henderson 
---
v3: Assert no manual change to CACHED_PSTATE_BITS,
merged in from a previously separate patch.
---
 target/arm/helper.h|  2 --
 target/arm/translate.h | 34 ++
 target/arm/op_helper.c |  5 -
 target/arm/translate-a64.c | 11 ---
 target/arm/translate.c | 11 ---
 5 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index 6f0f386926..583adba9b0 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
 DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
 DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
 
-DEF_HELPER_1(clear_pstate_ss, void, env)
-
 DEF_HELPER_2(get_r13_banked, i32, env, i32)
 DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
 
diff --git a/target/arm/translate.h b/target/arm/translate.h
index f25fe75685..912cc2a4a5 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -202,6 +202,40 @@ static inline TCGv_i32 get_ahp_flag(void)
 return ret;
 }
 
+/* Set bits within PSTATE.  */
+static inline void set_pstate_bits(uint32_t bits)
+{
+TCGv_i32 p = tcg_temp_new_i32();
+
+tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
+
+tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+tcg_gen_ori_i32(p, p, bits);
+tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+tcg_temp_free_i32(p);
+}
+
+/* Clear bits within PSTATE.  */
+static inline void clear_pstate_bits(uint32_t bits)
+{
+TCGv_i32 p = tcg_temp_new_i32();
+
+tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
+
+tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+tcg_gen_andi_i32(p, p, ~bits);
+tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+tcg_temp_free_i32(p);
+}
+
+/* If the singlestep state is Active-not-pending, advance to Active-pending. */
+static inline void gen_ss_advance(DisasContext *s)
+{
+if (s->ss_active) {
+s->pstate_ss = 0;
+clear_pstate_bits(PSTATE_SS);
+}
+}
 
 /* Vector operations shared between ARM and AArch64.  */
 extern const GVecGen3 bsl_op;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index c5721a866d..8698b4dc83 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 return res;
 }
 
-void HELPER(clear_pstate_ss)(CPUARMState *env)
-{
-env->pstate &= ~PSTATE_SS;
-}
-
 void HELPER(pre_hvc)(CPUARMState *env)
 {
 ARMCPU *cpu = arm_env_get_cpu(env);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1e49d33365..eaeb43577d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int 
offset,
 s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_ss_advance(DisasContext *s)
-{
-/* If the singlestep state is Active-not-pending, advance to
- * Active-pending.
- */
-if (s->ss_active) {
-s->pstate_ss = 0;
-gen_helper_clear_pstate_ss(cpu_env);
-}
-}
-
 static void gen_step_complete_exception(DisasContext *s)
 {
 /* We just completed step of an insn. Move from Active-not-pending
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 61adefb328..57b1b20287 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome, 
uint32_t target_el)
 tcg_temp_free_i32(tcg_excp);
 }
 
-static void gen_ss_advance(DisasContext *s)
-{
-/* If the singlestep state is Active-not-pending, advance to
- * Active-pending.
- */
-if (s->ss_active) {
-s->pstate_ss = 0;
-gen_helper_clear_pstate_ss(cpu_env);
-}
-}
-
 static void gen_step_complete_exception(DisasContext *s)
 {
 /* We just completed step of an insn. Move from Active-not-pending
-- 
2.17.2

Re: [Qemu-devel] [PATCH v3 3/7] block/dirty-bitmaps: add block_dirty_bitmap_check function

[Eric Blake]

On 3/1/19 1:57 PM, John Snow wrote:

>>> +if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
>>> +error_setg(errp, "Bitmap '%s' is currently in use by another"
>>> +   " operation and cannot be used", bitmap->name);
>>
>> Split before space,
>>

>>> +error_setg(errp, "Bitmap '%s' is inconsistent and cannot be used",
>>> +   bitmap->name);
>>> +error_append_hint(errp, "Try block-dirty-bitmap-remove to delete "
>>> +  "this bitmap from disk");
>>
>> split after space.  Looks inconsistent within a single function (pardon
>> the pun :)
>>
> 
> Ah... I've never known how to split strings. In fact, does anyone?
> I'll address this either in staging or as a follow-up, as I assume
> Vladimir will have some comments for me.

I don't care which way you go. git says we have both styles with enough
frequency that I wouldn't rule out the other style in HACKING.  But it
also says split after space seems more common, if you trust my regex:

$ git grep '"[^"]* "$' | wc
  11597  120619 1261416
$ git grep '^[[:space:]]*" [^"]*"' | wc
   4070   19423  271036

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH v3 3/7] block/dirty-bitmaps: add block_dirty_bitmap_check function

[John Snow]

On 3/1/19 2:36 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> Instead of checking against busy, inconsistent, or read only directly,
>> use a check function with permissions bits that let us streamline the
>> checks without reproducing them in many places.
>>
>> Included in this patch are permissions changes that simply add the
>> inconsistent check to existing permissions call spots, without
>> addressing existing bugs.
>>
>> In general, this means that busy+readonly checks become BDRV_BITMAP_DEFAULT,
>> which checks against all three conditions. busy-only checks become
>> BDRV_BITMAP_ALLOW_RO.
>>
>> Notably, remove allows inconsistent bitmaps, so it doesn't follow the 
>> pattern.
>>
>> Signed-off-by: John Snow 
>> ---
>>  include/block/dirty-bitmap.h   | 13 -
>>  block/dirty-bitmap.c   | 38 +++---
>>  blockdev.c | 49 +++---
>>  migration/block-dirty-bitmap.c | 12 +++--
>>  nbd/server.c   |  3 +--
>>  5 files changed, 54 insertions(+), 61 deletions(-)
>>
> 
> Diffstat proves its a win, even with the extra documentation for the new
> function. Nice.
> 

It would have been even more obvious if I had added the individual
"inconsistent" checks before conversion, so that it's even close to
breaking even seems like a win.

>> +int bdrv_dirty_bitmap_check(const BdrvDirtyBitmap *bitmap, uint32_t flags,
>> +Error **errp)
>> +{
>> +if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
>> +error_setg(errp, "Bitmap '%s' is currently in use by another"
>> +   " operation and cannot be used", bitmap->name);
> 
> Split before space,
> 
>> +return -1;
>> +}
>> +
>> +if ((flags & BDRV_BITMAP_RO) && bdrv_dirty_bitmap_readonly(bitmap)) {
>> +error_setg(errp, "Bitmap '%s' is readonly and cannot be modified",
>> +   bitmap->name);
>> +return -1;
>> +}
>> +
>> +if ((flags & BDRV_BITMAP_INCONSISTENT) &&
>> +bdrv_dirty_bitmap_inconsistent(bitmap)) {
>> +error_setg(errp, "Bitmap '%s' is inconsistent and cannot be used",
>> +   bitmap->name);
>> +error_append_hint(errp, "Try block-dirty-bitmap-remove to delete "
>> +  "this bitmap from disk");
> 
> split after space.  Looks inconsistent within a single function (pardon
> the pun :)
> 

Ah... I've never known how to split strings. In fact, does anyone?
I'll address this either in staging or as a follow-up, as I assume
Vladimir will have some comments for me.

--js

> That's minor,
> Reviewed-by: Eric Blake 
> 

Thanks!

Re: [Qemu-devel] [PATCH v3 6/7] block/dirty-bitmaps: disallow busy bitmaps as merge source

[Eric Blake]

On 3/1/19 1:48 PM, John Snow wrote:

>> I understand forbidding inconsistent sources (because if the source is
>> potentially missing bits, then the merge destination will also be
>> missing bits and thus be inconsistent), but why forbid busy?  If I've
>> associated a bitmap with an NBD server (making it busy), it is still
>> readable, and so I should still be able to merge its bits into another copy.
>>
> 
> True, do you rely on this, though?

Not in my current libvirt code (as I create a temporary bitmap to hand
to NBD, since it may be the merge of one or more disabled bitmaps in a
differential backup case), so being tighter for now and relaxing later
if we DO come up with a use is acceptable.

> 
> I was working from a space of "busy" meant "actively in-use by an
> operation, and COULD change" so I was forbidding it out of good hygiene.
> 
> Clearly the ones in-use by NBD are actually static and unchanging, so
> it's safer -- but that might not be true for push backups, where you
> might not actually be getting what you think you are, because of the
> bifurcated nature of those bitmaps.

Oh, good point, especially after you worked so hard to merge
locked/frozen into a single status - you WILL miss the bits from the
successor (unless we teach the merge algorithm to pull in the busy
bitmap's bits AND all the bits of its successors - but that feels like a
lot of work if we don't have a client needing it now).  Okay, with the
extra justification mentioned in the commit message,

> 
> If this causes a problem for you in the short-term I will simply roll
> this back, but it stands out to me.
> 
> (I can't stop myself from trying to protect the user from themselves.
> It's clearly a recurring theme in my design and reviews.)
> 
>>> diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
>>> index 769668ccdc..8403c9981d 100644
>>> --- a/block/dirty-bitmap.c
>>> +++ b/block/dirty-bitmap.c
>>> @@ -825,6 +825,9 @@ void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, 
>>> const BdrvDirtyBitmap *src,
>>>  goto out;
>>>  }
>>>  
>>> +if (bdrv_dirty_bitmap_check(src, BDRV_BITMAP_ALLOW_RO, errp)) {
>>
>> Thus, I think this should be BDRV_BITMAP_INCONSISTENT.

then I retract my complaint, and the code is acceptable for now.

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PULL 09/13] MAINTAINERS: Add maintainer to the TCG/i386 subsystem

[Richard Henderson]

On 2/28/19 9:41 AM, Thomas Huth wrote:
> Ok ... shall I resend the PULL request or could you maybe send a
> follow-up patch later?

The pr has been merged, so I'll do it later.


r~

Re: [Qemu-devel] [PATCH v3 7/7] block/dirty-bitmaps: implement inconsistent bit

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> Set the inconsistent bit on load instead of rejecting such bitmaps.
> There is no way to un-set it; the only option is to delete it.
> 
> Obvervations:
> - bitmap loading does not need to update the header for in_use bitmaps.
> - inconsistent bitmaps don't need to have their data loaded; they're
>   glorified corruption sentinels.
> - bitmap saving does not need to save inconsistent bitmaps back to disk.
> - bitmap reopening DOES need to drop the readonly flag from inconsistent
>   bitmaps to allow reopening of qcow2 files with non-qemu-owned bitmaps
>   being eventually flushed back to disk.
> 
> Signed-off-by: John Snow 
> ---
>  block/qcow2-bitmap.c | 103 ++-
>  1 file changed, 53 insertions(+), 50 deletions(-)
> 

> @@ -962,35 +963,39 @@ bool qcow2_load_dirty_bitmaps(BlockDriverState *bs, 
> Error **errp)
>  }
>  
>  QSIMPLEQ_FOREACH(bm, bm_list, entry) {

> +BdrvDirtyBitmap *bitmap = load_bitmap(bs, bm, errp);
> +if (bitmap == NULL) {
> +goto fail;
>  }

> +if (bm->flags & BME_FLAG_IN_USE) {
> +bdrv_dirty_bitmap_set_inconsistent(bitmap);

If you take my suggestion of an assertion in 1/7, then this line...

>  } else {
> -g_slist_foreach(created_dirty_bitmaps, set_readonly_helper,
> -(gpointer)true);
> +/* NB: updated flags only get written if can_write(bs) is true. 
> */
> +bm->flags |= BME_FLAG_IN_USE;
> +needs_update = true;
>  }
> +if (!(bm->flags & BME_FLAG_AUTO)) {
> +bdrv_disable_dirty_bitmap(bitmap);
> +}
> +bdrv_dirty_bitmap_set_persistance(bitmap, true);

...and this line need to swap order.

Also, can we have a preliminary patch to s/persistance/persistence/ and
fix our typo?

> @@ -1112,23 +1117,21 @@ int qcow2_reopen_bitmaps_rw_hint(BlockDriverState 
> *bs, bool *header_updated,
>  }
>  
>  QSIMPLEQ_FOREACH(bm, bm_list, entry) {
> -if (!(bm->flags & BME_FLAG_IN_USE)) {
> -BdrvDirtyBitmap *bitmap = bdrv_find_dirty_bitmap(bs, bm->name);
> -if (bitmap == NULL) {
> -continue;
> -}
> -
> -if (!bdrv_dirty_bitmap_readonly(bitmap)) {
> -error_setg(errp, "Bitmap %s is not readonly but not marked"
> - "'IN_USE' in the image. Something went 
> wrong,"
> - "all the bitmaps may be corrupted", 
> bm->name);

Nice - you're fixingthemissing spaces.

> -ret = -EINVAL;
> -goto out;
> -}
> +BdrvDirtyBitmap *bitmap = bdrv_find_dirty_bitmap(bs, bm->name);
> +if (bitmap == NULL) {
> +continue;
> +}
>  
> -bm->flags |= BME_FLAG_IN_USE;
> -ro_dirty_bitmaps = g_slist_append(ro_dirty_bitmaps, bitmap);
> +if (!bdrv_dirty_bitmap_readonly(bitmap)) {
> +error_setg(errp, "Bitmap %s was loaded prior to rw-reopen, but 
> was "
> +   "not marked as readonly. This is a bug, something 
> went "
> +   "wrong. All of the bitmaps may be corrupted", 
> bm->name);

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH v4] thunk: fix of malloc to g_new

[Aarushi Mehta]

>From 3c1cba63dc5070ab559a126e206557f27fbaea59 Mon Sep 17 00:00:00 2001
From: Aarushi Mehta 
Date: Sat, 2 Mar 2019 01:11:42 +0530
Subject: [PATCH v4] thunk: fix of malloc to g_new

Note that since thunking occurs throughout the lifetime of the QEMU
instance, there is no matching 'free' to correct.

Signed-off-by: Aarushi Mehta 
Reviewed-by: Eric Blake 
Reviewed-by: Stefan Hajnoczi 
---
 thunk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/thunk.c b/thunk.c
index d5d8645cd4..17f3d320bb 100644
--- a/thunk.c
+++ b/thunk.c
@@ -89,7 +89,7 @@ void thunk_register_struct(int id, const char *name, const 
argtype *types)
 for(i = 0;i < 2; i++) {
 offset = 0;
 max_align = 1;
-se->field_offsets[i] = malloc(nb_fields * sizeof(int));
+se->field_offsets[i] = g_new(int, nb_fields);
 type_ptr = se->field_types;
 for(j = 0;j < nb_fields; j++) {
 size = thunk_type_size(type_ptr, i);
-- 
2.17.1

Re: [Qemu-devel] [PATCH v3 6/7] block/dirty-bitmaps: disallow busy bitmaps as merge source

[John Snow]

On 3/1/19 2:44 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> We didn't do any state checking on source bitmaps at all,
>> so this adds inconsistent and busy checks. readonly is
>> allowed, so you can still copy a readonly bitmap to a new
>> destination to use it for operations like drive-backup.
>>
>> Signed-off-by: John Snow 
>> ---
>>  block/dirty-bitmap.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
> 
> I understand forbidding inconsistent sources (because if the source is
> potentially missing bits, then the merge destination will also be
> missing bits and thus be inconsistent), but why forbid busy?  If I've
> associated a bitmap with an NBD server (making it busy), it is still
> readable, and so I should still be able to merge its bits into another copy.
> 

True, do you rely on this, though?

I was working from a space of "busy" meant "actively in-use by an
operation, and COULD change" so I was forbidding it out of good hygiene.

Clearly the ones in-use by NBD are actually static and unchanging, so
it's safer -- but that might not be true for push backups, where you
might not actually be getting what you think you are, because of the
bifurcated nature of those bitmaps.

If this causes a problem for you in the short-term I will simply roll
this back, but it stands out to me.

(I can't stop myself from trying to protect the user from themselves.
It's clearly a recurring theme in my design and reviews.)

>> diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
>> index 769668ccdc..8403c9981d 100644
>> --- a/block/dirty-bitmap.c
>> +++ b/block/dirty-bitmap.c
>> @@ -825,6 +825,9 @@ void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, 
>> const BdrvDirtyBitmap *src,
>>  goto out;
>>  }
>>  
>> +if (bdrv_dirty_bitmap_check(src, BDRV_BITMAP_ALLOW_RO, errp)) {
> 
> Thus, I think this should be BDRV_BITMAP_INCONSISTENT.
> 

Re: [Qemu-devel] [PATCH v3 6/7] block/dirty-bitmaps: disallow busy bitmaps as merge source

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> We didn't do any state checking on source bitmaps at all,
> so this adds inconsistent and busy checks. readonly is
> allowed, so you can still copy a readonly bitmap to a new
> destination to use it for operations like drive-backup.
> 
> Signed-off-by: John Snow 
> ---
>  block/dirty-bitmap.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

I understand forbidding inconsistent sources (because if the source is
potentially missing bits, then the merge destination will also be
missing bits and thus be inconsistent), but why forbid busy?  If I've
associated a bitmap with an NBD server (making it busy), it is still
readable, and so I should still be able to merge its bits into another copy.

> diff --git a/block/dirty-bitmap.c b/block/dirty-bitmap.c
> index 769668ccdc..8403c9981d 100644
> --- a/block/dirty-bitmap.c
> +++ b/block/dirty-bitmap.c
> @@ -825,6 +825,9 @@ void bdrv_merge_dirty_bitmap(BdrvDirtyBitmap *dest, const 
> BdrvDirtyBitmap *src,
>  goto out;
>  }
>  
> +if (bdrv_dirty_bitmap_check(src, BDRV_BITMAP_ALLOW_RO, errp)) {

Thus, I think this should be BDRV_BITMAP_INCONSISTENT.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH v3 1/7] block/dirty-bitmaps: add inconsistent bit

[John Snow]

On 3/1/19 2:32 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> Add an inconsistent bit to dirty-bitmaps that allows us to report a bitmap as
>> persistent but potentially inconsistent, i.e. if we find bitmaps on a qcow2
>> that have been marked as "in use".
>>
>> Signed-off-by: John Snow 
>> ---
>>  qapi/block-core.json | 13 +
>>  include/block/dirty-bitmap.h |  2 ++
>>  block/dirty-bitmap.c | 19 +++
>>  3 files changed, 30 insertions(+), 4 deletions(-)
>>
>> diff --git a/qapi/block-core.json b/qapi/block-core.json
>> index 6e543594b3..e639ef6d1c 100644
>> --- a/qapi/block-core.json
>> +++ b/qapi/block-core.json
>> @@ -467,15 +467,20 @@
>>  #and cannot be modified via QMP or used by another operation.
>>  #Replaces `locked` and `frozen` statuses. (since 4.0)
>>  #
>> -# @persistent: true if the bitmap will eventually be flushed to persistent
>> -#  storage (since 4.0)
>> +# @persistent: true if the bitmap was stored on disk, is scheduled to be 
>> stored
>> +#  on disk, or both. (since 4.0)
>> +#
>> +# @inconsistent: true if this is a persistent bitmap that was improperly
>> +#stored. Implies @persistent to be true; @recording and
>> +#@busy to be false. This bitmap cannot be used. To remove
>> +#it, use @block-dirty-bitmap-remove. (Since 4.0)
>>  #
> 
> I know we waffled on word-smithing this, but this turned out nicely.
> 

Yes, I think so too.

> 
>>  
>> +/* Called with BQL taken. */
>> +void bdrv_dirty_bitmap_set_inconsistent(BdrvDirtyBitmap *bitmap)
>> +{
>> +qemu_mutex_lock(bitmap->mutex);
>> +bitmap->inconsistent = true;
>> +bitmap->disabled = true;
>> +qemu_mutex_unlock(bitmap->mutex);
> 
> Worth an assert that persistent is true?  Either way,
> 

Won't hurt.

> Reviewed-by: Eric Blake 
> 

Re: [Qemu-devel] [PATCH v3 4/7] block/dirty-bitmaps: prohibit readonly bitmaps for backups

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> drive and blockdev backup cannot use readonly bitmaps, because the
> sync=incremental mechanism actually edits the bitmaps on success.
> 
> If you really want to do this operation, use a copied bitmap.

In fact, that's what I ended up doing in my libvirt patches, always
running sync=incremental on a temporary copy.

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH v3 5/7] block/dirty-bitmaps: prohibit removing readonly bitmaps

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> Remove is an inherently RW operation, so this will fail anyway, but
> we can fail it very quickly instead of trying and failing, so do so.
> 
> Signed-off-by: John Snow 
> ---
>  blockdev.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Eric Blake 

> 
> diff --git a/blockdev.c b/blockdev.c
> index c8255dda0b..a9a059c570 100644
> --- a/blockdev.c
> +++ b/blockdev.c
> @@ -2881,7 +2881,8 @@ void qmp_block_dirty_bitmap_remove(const char *node, 
> const char *name,
>  return;
>  }
>  
> -if (bdrv_dirty_bitmap_check(bitmap, BDRV_BITMAP_BUSY, errp)) {
> +if (bdrv_dirty_bitmap_check(bitmap, BDRV_BITMAP_BUSY | BDRV_BITMAP_RO,
> +errp)) {
>  return;
>  }
>  
> 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH v3 3/7] block/dirty-bitmaps: add block_dirty_bitmap_check function

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> Instead of checking against busy, inconsistent, or read only directly,
> use a check function with permissions bits that let us streamline the
> checks without reproducing them in many places.
> 
> Included in this patch are permissions changes that simply add the
> inconsistent check to existing permissions call spots, without
> addressing existing bugs.
> 
> In general, this means that busy+readonly checks become BDRV_BITMAP_DEFAULT,
> which checks against all three conditions. busy-only checks become
> BDRV_BITMAP_ALLOW_RO.
> 
> Notably, remove allows inconsistent bitmaps, so it doesn't follow the pattern.
> 
> Signed-off-by: John Snow 
> ---
>  include/block/dirty-bitmap.h   | 13 -
>  block/dirty-bitmap.c   | 38 +++---
>  blockdev.c | 49 +++---
>  migration/block-dirty-bitmap.c | 12 +++--
>  nbd/server.c   |  3 +--
>  5 files changed, 54 insertions(+), 61 deletions(-)
> 

Diffstat proves its a win, even with the extra documentation for the new
function. Nice.

> +int bdrv_dirty_bitmap_check(const BdrvDirtyBitmap *bitmap, uint32_t flags,
> +Error **errp)
> +{
> +if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
> +error_setg(errp, "Bitmap '%s' is currently in use by another"
> +   " operation and cannot be used", bitmap->name);

Split before space,

> +return -1;
> +}
> +
> +if ((flags & BDRV_BITMAP_RO) && bdrv_dirty_bitmap_readonly(bitmap)) {
> +error_setg(errp, "Bitmap '%s' is readonly and cannot be modified",
> +   bitmap->name);
> +return -1;
> +}
> +
> +if ((flags & BDRV_BITMAP_INCONSISTENT) &&
> +bdrv_dirty_bitmap_inconsistent(bitmap)) {
> +error_setg(errp, "Bitmap '%s' is inconsistent and cannot be used",
> +   bitmap->name);
> +error_append_hint(errp, "Try block-dirty-bitmap-remove to delete "
> +  "this bitmap from disk");

split after space.  Looks inconsistent within a single function (pardon
the pun :)

That's minor,
Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH 2/2] spapr: Simulate CAS for qtest

[Greg Kurz]

The RTAS event hotplug code for machine types 2.8 and newer depends on
the CAS negotiated ov5 in order to work properly. However, there's no
CAS when running under qtest. There has been a tentative to trick the
code by faking the OV5_HP_EVT bit, but it turned out to break other
assumptions in the code and the change got reverted.

Go for a more general approach and simulate a CAS when running under
qtest. For simplicity, this pseudo CAS simple simulates the case where
the guest supports the same features as the machine. It is done at
reset time, just before we reset the DRCs, which could potentially
exercise the unplug code.

This allows to test unplug on spapr with both older and newer machine
types.

Suggested-by: Michael Roth 
Signed-off-by: Greg Kurz 
---
 hw/ppc/spapr.c |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b6a571b6f184..6da64ef7ee2b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -29,6 +29,7 @@
 #include "qapi/visitor.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/numa.h"
+#include "sysemu/qtest.h"
 #include "hw/hw.h"
 #include "qemu/log.h"
 #include "hw/fw-path-provider.h"
@@ -1711,6 +1712,16 @@ static void spapr_machine_reset(void)
  */
 spapr_irq_reset(spapr, &error_fatal);
 
+/*
+ * There is no CAS under qtest. Simulate one to please the code that
+ * depends on spapr->ov5_cas. This is especially needed to test device
+ * unplug, so we do that before resetting the DRCs.
+ */
+if (qtest_enabled()) {
+spapr_ovec_cleanup(spapr->ov5_cas);
+spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
+}
+
 /* DRC reset may cause a device to be unplugged. This will cause troubles
  * if this device is used by another device (eg, a running vhost backend
  * will crash QEMU if the DIMM holding the vring goes away). To avoid such

Re: [Qemu-devel] [PATCH v3 1/7] block/dirty-bitmaps: add inconsistent bit

[Eric Blake]

On 3/1/19 1:15 PM, John Snow wrote:
> Add an inconsistent bit to dirty-bitmaps that allows us to report a bitmap as
> persistent but potentially inconsistent, i.e. if we find bitmaps on a qcow2
> that have been marked as "in use".
> 
> Signed-off-by: John Snow 
> ---
>  qapi/block-core.json | 13 +
>  include/block/dirty-bitmap.h |  2 ++
>  block/dirty-bitmap.c | 19 +++
>  3 files changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/qapi/block-core.json b/qapi/block-core.json
> index 6e543594b3..e639ef6d1c 100644
> --- a/qapi/block-core.json
> +++ b/qapi/block-core.json
> @@ -467,15 +467,20 @@
>  #and cannot be modified via QMP or used by another operation.
>  #Replaces `locked` and `frozen` statuses. (since 4.0)
>  #
> -# @persistent: true if the bitmap will eventually be flushed to persistent
> -#  storage (since 4.0)
> +# @persistent: true if the bitmap was stored on disk, is scheduled to be 
> stored
> +#  on disk, or both. (since 4.0)
> +#
> +# @inconsistent: true if this is a persistent bitmap that was improperly
> +#stored. Implies @persistent to be true; @recording and
> +#@busy to be false. This bitmap cannot be used. To remove
> +#it, use @block-dirty-bitmap-remove. (Since 4.0)
>  #

I know we waffled on word-smithing this, but this turned out nicely.


>  
> +/* Called with BQL taken. */
> +void bdrv_dirty_bitmap_set_inconsistent(BdrvDirtyBitmap *bitmap)
> +{
> +qemu_mutex_lock(bitmap->mutex);
> +bitmap->inconsistent = true;
> +bitmap->disabled = true;
> +qemu_mutex_unlock(bitmap->mutex);

Worth an assert that persistent is true?  Either way,

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH v3 0/7] bitmaps: add inconsistent bit

[John Snow]

Allow QEMU to read in bitmaps that have the in-use bit set, for the
purposes of allowing users to delete those bitmaps.

This is chosen in preference to a hard error on load to minimize
impact for a non-critical error, but to force the user or management
utility to acknowledge that the bitmap is no longer viable.

1. Changed wording of meaning of persistent bit, inconsistent bit
   Declining to optimize to avoid allocations for this revision.

2. Add Reviewed-by from Eric.

3. Split into several patches that are more single-purpose, which
   highlights the individual fixes more clearly;

   - Prohibit BUSY or INCONSISTENT bitmaps from being merge sources.

4. Declining feedback to prohibit disabling or enabling readonly bitmaps,
   on the basis that users may wish to enable/disable them prior to
   remounting their backing storage RW.

   Decided to prohibit attempting to remove readonly bitmaps, so the
   failure happens earlier.

   Prohibit sync=incremental backups using readonly bitmaps, because
   they're not capable of clearing the bitmap on success.
   sync=differential would be acceptable here. (Good spot, Vladimir.)

John Snow (7):
  block/dirty-bitmaps: add inconsistent bit
  block/dirty-bitmap: add inconsistent status
  block/dirty-bitmaps: add block_dirty_bitmap_check function
  block/dirty-bitmaps: prohibit readonly bitmaps for backups
  block/dirty-bitmaps: prohibit removing readonly bitmaps
  block/dirty-bitmaps: disallow busy bitmaps as merge source
  block/dirty-bitmaps: implement inconsistent bit

 qapi/block-core.json   |  20 +--
 include/block/dirty-bitmap.h   |  15 -
 block/dirty-bitmap.c   |  63 +---
 block/qcow2-bitmap.c   | 103 +
 blockdev.c |  50 
 migration/block-dirty-bitmap.c |  12 +---
 nbd/server.c   |   3 +-
 7 files changed, 151 insertions(+), 115 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH 1/2] Revert "spapr: support memory unplug for qtest"

[Greg Kurz]

Commit b8165118f52c broke CPU hotplug tests for old machine types:

$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test 
-m=slow
/ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-3.0/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.10/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.11/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.9/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.7/device-add/2x3x1&maxcpus=6: **
ERROR:/home/thuth/devel/qemu/hw/ppc/spapr_events.c:313:rtas_event_log_to_source:
 assertion failed: (source->enabled)
Broken pipe
/home/thuth/devel/qemu/tests/libqtest.c:143: kill_qemu() detected QEMU death 
from signal 6 (Aborted) (core dumped)
Aborted (core dumped)

The approach of faking the availability of OV5_HP_EVT causes the
code to assume the hotplug event source is enabled, which is wrong
for older machines.

This reverts commit b8165118f52ce5ee88565d3cec83d30374efdc96.

A subsequent patch will address the problem of CAS under qtest from
a different angle.

Reported-by: Thomas Huth 
Signed-off-by: Greg Kurz 
---
 hw/ppc/spapr_ovec.c |6 --
 1 file changed, 6 deletions(-)

diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c
index 12510b236a95..318bf33de4b1 100644
--- a/hw/ppc/spapr_ovec.c
+++ b/hw/ppc/spapr_ovec.c
@@ -16,7 +16,6 @@
 #include "qemu/bitmap.h"
 #include "exec/address-spaces.h"
 #include "qemu/error-report.h"
-#include "sysemu/qtest.h"
 #include "trace.h"
 #include 
 
@@ -132,11 +131,6 @@ bool spapr_ovec_test(sPAPROptionVector *ov, long bitnr)
 g_assert(ov);
 g_assert(bitnr < OV_MAXBITS);
 
-/* support memory unplug for qtest */
-if (qtest_enabled() && bitnr == OV5_HP_EVT) {
-return true;
-}
-
 return test_bit(bitnr, ov->bitmap) ? true : false;
 }
 

[Qemu-devel] [PATCH v5 10/10] tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions

[Aleksandar Markovic]

From: Aleksandar Markovic 

Add tests for MIPS64R6 bit swap instructions.

Signed-off-by: Aleksandar Markovic 
---
 .../isa/mips64r6/bit-swap/test_mips64r6_bitswap.c  | 144 +
 .../isa/mips64r6/bit-swap/test_mips64r6_dbitswap.c | 144 +
 2 files changed, 288 insertions(+)
 create mode 100644 
tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_bitswap.c
 create mode 100644 
tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_dbitswap.c

diff --git a/tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_bitswap.c 
b/tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_bitswap.c
new file mode 100644
index 000..639850d
--- /dev/null
+++ b/tests/tcg/mips/user/isa/mips64r6/bit-swap/test_mips64r6_bitswap.c
@@ -0,0 +1,144 @@
+/*
+ *  Test program for MIPS64R6 instruction BITSWAP
+ *
+ *  Copyright (C) 2019  Wave Computing, Inc.
+ *  Copyright (C) 2019  Aleksandar Markovic 
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see .
+ *
+ */
+
+#include 
+#include 
+
+#include "../../../../include/wrappers_mips64r6.h"
+#include "../../../../include/test_inputs_64.h"
+#include "../../../../include/test_utils_64.h"
+
+#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
+
+
+int32_t main(void)
+{
+char *instruction_name = "BITSWAP";
+int32_t ret;
+uint32_t i;
+struct timeval start, end;
+double elapsed_time;
+
+uint64_t b64_result[TEST_COUNT_TOTAL];
+uint64_t b64_expect[TEST_COUNT_TOTAL] = {
+0xULL,/*   0  */
+0xULL,
+0xULL,
+0xULL,
+0xULL,
+0xULL,
+0x711cc771ULL,
+0x8ee3388eULL,
+0x0f0f0f0fULL,/*   8  */
+0xf0f0f0f0ULL,
+0x071f7cf0ULL,
+0xf8e0830fULL,
+0xf0033ff0ULL,
+0x0ffcc00fULL,
+0x07fc017fULL,
+0xf803fe80ULL,
+0xff00ff00ULL,/*  16  */
+0x00ff00ffULL,
+0xf01fc07fULL,
+0x0fe03f80ULL,
+0x00ff03f0ULL,
+0xff00fc0fULL,
+0x01f07f00ULL,
+0xfe0f80ffULL,
+0x0f00ff0fULL,/*  24  */
+0xf0ff00f0ULL,
+0x7f00f0ffULL,
+0x80ff0f00ULL,
+0xff0300ffULL,
+0x00fcff00ULL,
+0xff1f00f0ULL,
+0x00e0ff0fULL,
+0xULL,/*  32  */
+0xULL,
+0xfcff0700ULL,
+0x0300f8ffULL,
+0xf0ff3f00ULL,
+0x0f00c0ffULL,
+0xc001ULL,
+0x3ffeULL,
+0x000fULL,/*  40  */
+0xfff0ULL,
+0x00fcff7fULL,
+0xff030080ULL,
+0x00f0ULL,
+0xff0fULL,
+0x00c0ULL,
+0xff3fULL,
+0xULL,/*  48  */
+0xULL,
+0xfcffULL,
+0x0300ULL,
+0xf0ffULL,
+0x0f00ULL,
+0xc0ffULL,
+0x3f00ULL,
+0x00ffULL,/*  56  */
+0xff00ULL,
+0x00fcULL,
+0xff03ULL,
+0x00f0ULL,
+0xff0fULL,
+0x00c0ULL,
+0xff3fULL,
+0x1446aa02ULL,/*  64  */
+0xb2c9e310ULL,
+0x9df3d101ULL,
+0x7a8c4772ULL,
+0xbef5421aULL,
+0xff50749fULL,
+0xa6533d52ULL,
+0x5965ed41ULL,
+0x6a756792ULL,/*  72  */
+0xa69ba7ebULL,
+0x93d363d8ULL,
+0x8c152675ULL,
+0x654a5750ULL,
+0x98c48615ULL,
+0x447def39ULL,
+0x4f9a7bb5ULL,
+};
+
+