[Qemu-devel] [PATCH v2 3/4] Introduce dump of hot TBs
Adding a function to dump the Nth hottest TBs.
The block PC, execution count and ops is dump to the log.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/translate-all.c | 45 +++
include/exec/exec-all.h | 2 ++
2 files changed, 47 insertions(+)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f7e99f90e0..c3d9ecb2c4 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1240,6 +1240,27 @@ static gboolean tb_host_size_iter(gpointer key, gpointer
value, gpointer data)
return false;
}
+static void tb_dump_statistics(TBStatistics *tbs)
+{
+uint32_t cflags = curr_cflags() | CF_NOCACHE;
+int old_log_flags = qemu_loglevel;
+
+qemu_set_log(CPU_LOG_TB_OP_OPT);
+
+qemu_log("\n--\n");
+qemu_log("Translation Block PC: \t0x"TARGET_FMT_lx "\n", tbs->pc);
+qemu_log("Execution Count: \t%lu\n\n", (uint64_t) (tbs->exec_count +
tbs->exec_count_overflows*0x));
+
+mmap_lock();
+TranslationBlock *tb = tb_gen_code(current_cpu, tbs->pc, tbs->cs_base,
tbs->flags, cflags);
+tb_phys_invalidate(tb, -1);
+mmap_unlock();
+
+qemu_set_log(old_log_flags);
+
+tcg_tb_remove(tb);
+}
+
/* flush all the translation blocks */
static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
{
@@ -1276,6 +1297,30 @@ done:
mmap_unlock();
}
+static gint inverse_sort_tbs(gconstpointer p1, gconstpointer p2)
+{
+const TBStatistics *tbs1 = (TBStatistics *) p1;
+const TBStatistics *tbs2 = (TBStatistics *) p2;
+uint64_t p1_count = (uint64_t) (tbs1->exec_count +
tbs1->exec_count_overflows*0x);
+uint64_t p2_count = (uint64_t) (tbs2->exec_count +
tbs2->exec_count_overflows*0x);
+
+return p1_count < p2_count ? 1 : p1_count == p2_count ? 0 : -1;
+}
+
+void tb_dump_exec_freq(uint32_t max_tbs_to_print)
+{
+tb_ctx.tb_statistics = g_list_sort(tb_ctx.tb_statistics, inverse_sort_tbs);
+
+uint32_t tbs_printed = 0;
+for (GList *i = tb_ctx.tb_statistics; i != NULL; i = i->next) {
+tbs_printed++;
+ tb_dump_statistics((TBStatistics *) i->data);
+if (max_tbs_to_print != 0 && tbs_printed >= max_tbs_to_print) {
+break;
+}
+}
+}
+
void tb_flush(CPUState *cpu)
{
if (tcg_enabled()) {
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 359100ef3b..0547db0271 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -533,4 +533,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,
/* vl.c */
extern int singlestep;
+void tb_dump_exec_freq(uint32_t);
+
#endif
--
2.22.0
[Qemu-devel] [PATCH v2 2/4] Adding an optional tb execution counter.
We collect the number of times each TB is executed
and store it in the its TBStatistics.
We also count the number of times the execution counter overflows.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/tcg-runtime.c | 10 ++
accel/tcg/tcg-runtime.h | 2 ++
accel/tcg/translator.c| 1 +
include/exec/gen-icount.h | 9 +
4 files changed, 22 insertions(+)
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 8a1e408e31..9888a7fce8 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -167,3 +167,13 @@ void HELPER(exit_atomic)(CPUArchState *env)
{
cpu_loop_exit_atomic(env_cpu(env), GETPC());
}
+
+void HELPER(inc_exec_freq)(void *ptr)
+{
+TranslationBlock *tb = (TranslationBlock*) ptr;
+// if overflows, then reset the execution counter and increment the
overflow counter
+if (atomic_cmpxchg(>tb_stats->exec_count, 0x, 0) ==
0x) {
+atomic_inc(>tb_stats->exec_count_overflows);
+}
+atomic_inc(>tb_stats->exec_count);
+}
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 4fa61b49b4..bf0b75dbe8 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -28,6 +28,8 @@ DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env)
DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
+DEF_HELPER_FLAGS_1(inc_exec_freq, TCG_CALL_NO_RWG, void, ptr)
+
#ifdef CONFIG_SOFTMMU
DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 9226a348a3..cc06070e7e 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -54,6 +54,7 @@ void translator_loop(const TranslatorOps *ops,
DisasContextBase *db,
gen_tb_start(db->tb);
ops->tb_start(db, cpu);
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
+gen_tb_exec_count(tb);
while (true) {
db->num_insns++;
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index f7669b6841..6d38b6e1fb 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -7,6 +7,15 @@
static TCGOp *icount_start_insn;
+static inline void gen_tb_exec_count(TranslationBlock *tb)
+{
+ if (qemu_loglevel_mask(CPU_LOG_HOT_TBS)) {
+TCGv_ptr tb_ptr = tcg_const_ptr(tb);
+gen_helper_inc_exec_freq(tb_ptr);
+tcg_temp_free_ptr(tb_ptr);
+ }
+}
+
static inline void gen_tb_start(TranslationBlock *tb)
{
TCGv_i32 count, imm;
--
2.22.0
[Qemu-devel] [PATCH v2 0/4] dumping hot TBs
It adds a new structure which is linked with each TBs and stores its statistics. We collect the execution count of the TBs and store in this new structure. The information stored in this new struct is then used to support a new command line -d hot_tbs:N which dumps information of the N most hot TBs. Different from v1 now the execution count is being updated directly from the TBStatistics so we do not need to copy the data when flushing. [PATCH v2 1/4] add and link a statistic struct to TBs [PATCH v2 2/4] Adding an optional tb execution counter. [PATCH v2 3/4] Introduce dump of hot TBs [PATCH v2 4/4] adding -d hot_tbs:limit command line option
[Qemu-devel] [PATCH v2 1/4] add and link a statistic struct to TBs
We want to store statistics for each TB even after flushes.
We do not want to modify or grow the TB struct.
So we create a new struct to contain this statistics and
link it to each TB while they are created.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/translate-all.c | 40 +++
include/exec/exec-all.h | 21
include/exec/tb-context.h | 1 +
include/qemu/log.h| 1 +
4 files changed, 63 insertions(+)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 5d1e08b169..f7e99f90e0 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1118,6 +1118,18 @@ static inline void code_gen_alloc(size_t tb_size)
}
}
+static gint statistics_cmp(gconstpointer p1, gconstpointer p2)
+{
+const TBStatistics *a = (TBStatistics *) p1;
+const TBStatistics *b = (TBStatistics *) p2;
+
+return (a->pc == b->pc &&
+ a->cs_base == b->cs_base &&
+ a->flags == b->flags &&
+ a->page_addr[0] == b->page_addr[0] &&
+ a->page_addr[1] == b->page_addr[1]) ? 0 : 1;
+}
+
static bool tb_cmp(const void *ap, const void *bp)
{
const TranslationBlock *a = ap;
@@ -1586,6 +1598,29 @@ static inline void tb_page_add(PageDesc *p,
TranslationBlock *tb,
#endif
}
+static void tb_insert_statistics_structure(TranslationBlock *tb) {
+TBStatistics *new_stats = g_new0(TBStatistics, 1);
+new_stats->pc = tb->pc;
+new_stats->cs_base = tb->cs_base;
+new_stats->flags = tb->flags;
+new_stats->page_addr[0] = tb->page_addr[0];
+new_stats->page_addr[1] = tb->page_addr[1];
+
+ GList *lookup_result = g_list_find_custom(tb_ctx.tb_statistics,
new_stats, statistics_cmp);
+
+ if (lookup_result) {
+ /* If there is already a TBStatistic for this TB from a
previous flush
+ * then just make the new TB point to the older TBStatistic
+ */
+ free(new_stats);
+ tb->tb_stats = lookup_result->data;
+ } else {
+ /* If not, then points to the new tb_statistics and add it to
the hash */
+ tb->tb_stats = new_stats;
+ tb_ctx.tb_statistics = g_list_prepend(tb_ctx.tb_statistics, new_stats);
+ }
+}
+
/* add a new TB and link it to the physical page tables. phys_page2 is
* (-1) to indicate that only one page contains the TB.
*
@@ -1636,6 +1671,11 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t
phys_pc,
void *existing_tb = NULL;
uint32_t h;
+if (qemu_loglevel_mask(CPU_LOG_HOT_TBS)) {
+ /* create and link to its TB a structure to store statistics */
+ tb_insert_statistics_structure(tb);
+ }
+
/* add in the hash table */
h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
tb->trace_vcpu_dstate);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 16034ee651..359100ef3b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,6 +324,24 @@ static inline void
tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
#define CODE_GEN_AVG_BLOCK_SIZE 150
#endif
+typedef struct TBStatistics TBStatistics;
+
+/*
+ * This struct stores statistics such as execution count of the
TranslationBlocks.
+ * Each TB has its own TBStatistics. TBStatistics is suppose to live even
after
+ * flushes.
+ */
+struct TBStatistics {
+target_ulong pc;
+target_ulong cs_base;
+uint32_t flags;
+tb_page_addr_t page_addr[2];
+
+// total number of times that the related TB have being executed
+uint32_t exec_count;
+uint32_t exec_count_overflows;
+};
+
/*
* Translation Cache-related fields of a TB.
* This struct exists just for convenience; we keep track of TB's in a binary
@@ -403,6 +421,9 @@ struct
[Qemu-devel] [PATCH] memory: warning on out of scope notification
if an entry has parts out of scope of notifier's range, print warning
message.
Out of scope mapping/unmapping would cause problem, as in below case:
1. initially there are two notifiers with ranges
0-0xfedf, 0xfef0-0x,
IOVAs from 0x3c00 - 0x3c1f is in shadow page table.
2. in vfio, memory_region_register_iommu_notifier() is followed by
memory_region_iommu_replay(), which will first call address space
unmap,
and walk and add back all entries in vtd shadow page table. e.g.
(1) for notifier 0-0xfedf,
IOVAs from 0 - 0x get unmapped,
and IOVAs from 0x3c00 - 0x3c1f get mapped
(2) for notifier 0xfef0-0x
IOVAs from 0 - 0x7f get unmapped,
but IOVAs from 0x3c00 - 0x3c1f cannot get mapped back.
Cc: Auger Eric
Signed-off-by: Yan Zhao
---
memory.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/memory.c b/memory.c
index 0a089a7..18927f2 100644
--- a/memory.c
+++ b/memory.c
@@ -1953,6 +1953,16 @@ void memory_region_notify_one(IOMMUNotifier *notifier,
request_flags = IOMMU_NOTIFIER_UNMAP;
}
+if (entry->iova < notifier->start ||
+entry->iova + entry->addr_mask > notifier->end) {
+warn_report("%s IOMMUTLBEntry %lx-%lx outside of "
+"notifier scope %lx-%lx",
+(request_flags == IOMMU_NOTIFIER_MAP) ?
+"Mapping" : "Unmapping",
+entry->iova, entry->iova + entry->addr_mask,
+notifier->start, notifier->end);
+}
+
if (notifier->notifier_flags & request_flags) {
notifier->notify(notifier, entry);
}
--
2.7.4
Re: [Qemu-devel] [PATCH] memory: do not do out of bound notification
On Thu, Jun 20, 2019 at 09:04:43PM +0800, Peter Xu wrote:
> On Thu, Jun 20, 2019 at 08:59:55PM +0800, Peter Xu wrote:
> > On Thu, Jun 20, 2019 at 10:35:29AM +0200, Paolo Bonzini wrote:
> > > On 20/06/19 06:02, Peter Xu wrote:
> > > > Seems workable, to be explicit - we can even cut it into chunks with
> > > > different size to be efficient.
> > >
> > > Yes, this is not hard (completely untested):
> > >
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 44b1231157..541538bc6c 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -3388,39 +3388,34 @@ static void
> > > vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
> > > }
> > >
> > > assert(start <= end);
> > > -size = end - start;
> > > +while (end > start) {
> > > +size = end - start;
> > > +/* Only keep the lowest bit of either size or start. */
> > > +size = MIN(size & -size, start & -start);
> >
> > I feel like this can be problematic. I'm imaging:
> >
> > start=0x1000_, size=0x1000_1000
> >
> > This will get size=0x1000 but actually we can do size=0x1000_ as
> > the first.
> >
> > > +/* Should not happen, but limit to address width too just in
> > > case */
> > > +size = MIN(size, 1ULL << s->aw_bits);
> > >
> > > -if (ctpop64(size) != 1) {
> > > -/*
> > > - * This size cannot format a correct mask. Let's enlarge it to
> > > - * suite the minimum available mask.
> > > - */
> > > -int n = 64 - clz64(size);
> > > -if (n > s->aw_bits) {
> > > -/* should not happen, but in case it happens, limit it */
> > > -n = s->aw_bits;
> > > -}
> > > -size = 1ULL << n;
> > > -}
> > > +assert((start & (size - 1)) == 0);
> > >
> > > -entry.target_as = _space_memory;
> > > -/* Adjust iova for the size */
> > > -entry.iova = n->start & ~(size - 1);
> > > -/* This field is meaningless for unmap */
> > > -entry.translated_addr = 0;
> > > -entry.perm = IOMMU_NONE;
> > > -entry.addr_mask = size - 1;
> > > +entry.target_as = _space_memory;
> > > +entry.iova = start;
> > > +/* This field is meaningless for unmap */
> > > +entry.translated_addr = 0;
> > > +entry.perm = IOMMU_NONE;
> > > +entry.addr_mask = size - 1;
> >
> > (some of the fields can be moved out of loop because they are
> > constants)
> >
> > >
> > > -trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
> > > - VTD_PCI_SLOT(as->devfn),
> > > - VTD_PCI_FUNC(as->devfn),
> > > - entry.iova, size);
> > > +trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
> > > + VTD_PCI_SLOT(as->devfn),
> > > + VTD_PCI_FUNC(as->devfn),
> > > + entry.iova, size);
> >
> > Can move this out because this is a trace only so we don't have
> > restriction on mask?
> >
> > >
> > > -map.iova = entry.iova;
> > > -map.size = entry.addr_mask;
> > > -iova_tree_remove(as->iova_tree, );
> > > +map.iova = entry.iova;
> > > +map.size = entry.addr_mask;
> > > +iova_tree_remove(as->iova_tree, );
> >
> > Same here?
> >
> > >
> > > -memory_region_notify_one(n, );
> > > +memory_region_notify_one(n, );
> > > +start += size;
> > > +}
> > > }
> > >
> > > static void vtd_address_space_unmap_all(IntelIOMMUState *s)
> > >
> > >
> > > Yan,
> > >
> > > if something like this works for you, let me know and I will submit it
> > > as a proper patch.
> > >
> > > Paolo
> >
> > Since during review I'm thinking how to generate a correct sequence of
> > these masks... here's my try below with above issues fixed... :)
> >
> > I've tried compile but not tested. Yan can test it, or I can do it
> > too tomorrow after I find some machines.
> >
> > Thanks,
> >
> >
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 44b1231157..cfbd225f0a 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -3363,11 +3363,32 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState
> > *s, PCIBus *bus, int devfn)
> > return vtd_dev_as;
> > }
> >
> > +static uint64_t vtd_get_next_mask(uint64_t start, uint64_t size, int gaw)
> > +{
> > +/* Tries to find smallest mask from start first */
> > +uint64_t rmask = start & -start, max_mask = 1ULL << gaw;
> > +
> > +assert(size && gaw > 0 && gaw < 64);
> > +
> > +/* Zero start, or too big */
> > +if (!rmask || rmask > max_mask) {
> > +rmask = max_mask;
> > +}
> > +
> > +/* If the start mask worked, then use it */
> > +if (rmask <= size) {
> > +return rmask;
> > +}
> > +
> > +/* Find the largest page
[Qemu-devel] [Bug 1577937] Re: netbeans not working with std graphic driver
[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1577937 Title: netbeans not working with std graphic driver Status in QEMU: Expired Bug description: Qemu Version: QEMU emulator version 2.5.1, Copyright (c) 2003-2008 Fabrice Bellard Launching VM with: sudo qemu-system-x86_64 -enable-kvm -m 1024M ~/guest.vm -usb -vga std Guest: Kali Linux 2016.1 Kernel: 4.4.0-kali1-amd64 Affected Arch: 64bit & 32bit Netbeans failing to start after netbeans splash comes up. No netbeans window is being drawn. Problem can be reproduced. It IS working with -vga qxl, so maybe there's a bug in std emulation. output from netbeans log (more in attachement): SEVERE [global] java.lang.RuntimeException: failed to load system cursor: DnD.Cursor.CopyDrop : cannot load system cursor: CopyDrop.32x32 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1577937/+subscriptions
Re: [Qemu-devel] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter
Patchew URL:
https://patchew.org/QEMU/20190624013921.11944-1-sjitindarsi...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads
parameter to ibm, get_system_parameter
Type: series
Message-id: 20190624013921.11944-1-sjitindarsi...@gmail.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
* [new tag]
patchew/20190624013921.11944-1-sjitindarsi...@gmail.com ->
patchew/20190624013921.11944-1-sjitindarsi...@gmail.com
Switched to a new branch 'test'
285da11abd powerpc/spapr: Add host threads parameter to ibm,
get_system_parameter
=== OUTPUT BEGIN ===
ERROR: braces {} are necessary for all arms of this statement
#36: FILE: hw/ppc/spapr_rtas.c:238:
+if (!kvm_enabled())
[...]
ERROR: braces {} are necessary for all arms of this statement
#40: FILE: hw/ppc/spapr_rtas.c:242:
+if (!dir)
[...]
total: 2 errors, 0 warnings, 56 lines checked
Commit 285da11abde5 (powerpc/spapr: Add host threads parameter to ibm,
get_system_parameter) has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190624013921.11944-1-sjitindarsi...@gmail.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com
[Qemu-devel] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter
The ibm,get_system_parameter rtas call is used by the guest to retrieve
data relating to certain parameters of the system. The SPLPAR
characteristics option (token 20) is used to determin characteristics of
the environment in which the lpar will run.
It may be useful for a guest to know the number of physical host threads
present on the underlying system where it is being run. Add the
characteristic "HostThrs" to the SPLPAR Characteristics
ibm,get_system_parameter rtas call to expose this information to a
guest and provide an implementation which determines this information
based on the number of interrupt servers present in the device tree.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr_rtas.c | 44
1 file changed, 44 insertions(+)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 5bc1a93271..a33d87794c 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -229,6 +229,40 @@ static inline int sysparm_st(target_ulong addr,
target_ulong len,
return RTAS_OUT_SUCCESS;
}
+static int rtas_get_num_host_threads(void)
+{
+const char *entry, *name = "/proc/device-tree/cpus/";
+int num_threads = -1;
+GDir *dir;
+
+if (!kvm_enabled())
+return 1;
+
+dir = g_dir_open(name, 0, NULL);
+if (!dir)
+return -1;
+
+while ((entry = g_dir_read_name(dir))) {
+if (!strncmp(entry, "PowerPC,POWER", strlen("PowerPC,POWER"))) {
+unsigned long len;
+char *path, *buf;
+
+path = g_strconcat(name, entry, "/ibm,ppc-interrupt-server#s",
+ NULL);
+if (g_file_get_contents(path, , , NULL)) {
+num_threads = len / sizeof(int);
+g_free(buf);
+}
+
+g_free(path);
+break;
+}
+}
+
+g_dir_close(dir);
+return num_threads;
+}
+
static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
SpaprMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -250,6 +284,16 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
current_machine->ram_size / MiB,
smp_cpus,
max_cpus);
+int num_host_threads = rtas_get_num_host_threads();
+
+if (num_host_threads > 0) {
+char *hostthr_val, *old = param_val;
+
+hostthr_val = g_strdup_printf(",HostThrs=%d", num_host_threads);
+param_val = g_strconcat(param_val, hostthr_val, NULL);
+g_free(hostthr_val);
+g_free(old);
+}
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
--
2.13.6
[Qemu-devel] [Bug 1833871] Re: qemu-img convert file.vmdk: Invalid footer
Probably my image was corrupt since it works with another image. So this bug can be closed. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1833871 Title: qemu-img convert file.vmdk: Invalid footer Status in QEMU: New Bug description: Steps to reproduce - Open ESXi 6.5 Web UI - Export OVF - qemu-img convert disk.vmdk disk.qcow2 Error: qemu-img: Could not open './disk-1.vmdk': Invalid footer I found another person having this problem here: https://forum.proxmox.com/threads/error-converting-vmdk-file-to-qcow2-file.38264/ As I guess from the answer, the guy went over to manually copy the flat file from the datastore instead of using the ovf-exported file. Nevertheless, I think this bug should be investigated further and closed. Probably it is just some metadata issue and should not be too hard to fix once the root of the problem is found. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1833871/+subscriptions
[Qemu-devel] [Bug 1833871] Re: qemu-img convert file.vmdk: Invalid footer
I just compiled the version in the master branch and the same error occurred. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1833871 Title: qemu-img convert file.vmdk: Invalid footer Status in QEMU: New Bug description: Steps to reproduce - Open ESXi 6.5 Web UI - Export OVF - qemu-img convert disk.vmdk disk.qcow2 Error: qemu-img: Could not open './disk-1.vmdk': Invalid footer I found another person having this problem here: https://forum.proxmox.com/threads/error-converting-vmdk-file-to-qcow2-file.38264/ As I guess from the answer, the guy went over to manually copy the flat file from the datastore instead of using the ovf-exported file. Nevertheless, I think this bug should be investigated further and closed. Probably it is just some metadata issue and should not be too hard to fix once the root of the problem is found. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1833871/+subscriptions
[Qemu-devel] [Bug 1833871] [NEW] qemu-img convert file.vmdk: Invalid footer
Public bug reported: Steps to reproduce - Open ESXi 6.5 Web UI - Export OVF - qemu-img convert disk.vmdk disk.qcow2 Error: qemu-img: Could not open './disk-1.vmdk': Invalid footer I found another person having this problem here: https://forum.proxmox.com/threads/error-converting-vmdk-file-to-qcow2-file.38264/ As I guess from the answer, the guy went over to manually copy the flat file from the datastore instead of using the ovf-exported file. Nevertheless, I think this bug should be investigated further and closed. Probably it is just some metadata issue and should not be too hard to fix once the root of the problem is found. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1833871 Title: qemu-img convert file.vmdk: Invalid footer Status in QEMU: New Bug description: Steps to reproduce - Open ESXi 6.5 Web UI - Export OVF - qemu-img convert disk.vmdk disk.qcow2 Error: qemu-img: Could not open './disk-1.vmdk': Invalid footer I found another person having this problem here: https://forum.proxmox.com/threads/error-converting-vmdk-file-to-qcow2-file.38264/ As I guess from the answer, the guy went over to manually copy the flat file from the datastore instead of using the ovf-exported file. Nevertheless, I think this bug should be investigated further and closed. Probably it is just some metadata issue and should not be too hard to fix once the root of the problem is found. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1833871/+subscriptions
Re: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes
Patchew URL: https://patchew.org/QEMU/1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Type: series Message-id: 1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com -> patchew/1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com Switched to a new branch 'test' 22d133b7d3 tcg/ppc: Update vector support to v3.00 90bbf51163 tcg/ppc: Update vector support to v2.07 b5335688c8 tcg/ppc: Update vector support to v2.06 b521901488 tcg/ppc: Support vector dup2 8924e68f97 tcg/ppc: Support vector multiply e293fff80b tcg/ppc: Support vector shift by immediate f690223722 tcg/ppc: Add empty file tcg-target.opc.h e4e6419f8c tcg/ppc: Prepare case for vector multiply 7957f8f41c tcg/ppc: Add support for vector saturated add/subtract fe805396ae tcg/ppc: Add support for vector add/subtract 5cb6cd0fc0 tcg/ppc: Add support for vector maximum/minimum 4747cecdb1 tcg/ppc: Add support for load/store/logic/comparison 421bc6d7d3 tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() 0379705f8d tcg/ppc: Introduce macro VX4() 7fc4554647 tcg/ppc: Introduce flag have_isa_altivec 29c55ddd9f tcg/ppc: Introduce Altivec registers === OUTPUT BEGIN === 1/16 Checking commit 29c55ddd9f2e (tcg/ppc: Introduce Altivec registers) 2/16 Checking commit 7fc455464789 (tcg/ppc: Introduce flag have_isa_altivec) 3/16 Checking commit 0379705f8d31 (tcg/ppc: Introduce macro VX4()) ERROR: spaces required around that '|' (ctx:VxV) #21: FILE: tcg/ppc/tcg-target.inc.c:323: +#define VX4(opc) (OPCD(4)|(opc)) ^ total: 1 errors, 0 warnings, 7 lines checked Patch 3/16 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 4/16 Checking commit 421bc6d7d308 (tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()) 5/16 Checking commit 4747cecdb1b0 (tcg/ppc: Add support for load/store/logic/comparison) 6/16 Checking commit 5cb6cd0fc043 (tcg/ppc: Add support for vector maximum/minimum) 7/16 Checking commit fe805396aee3 (tcg/ppc: Add support for vector add/subtract) 8/16 Checking commit 7957f8f41c63 (tcg/ppc: Add support for vector saturated add/subtract) 9/16 Checking commit e4e6419f8c88 (tcg/ppc: Prepare case for vector multiply) 10/16 Checking commit f69022372202 (tcg/ppc: Add empty file tcg-target.opc.h) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #14: new file mode 100644 WARNING: Block comments use a leading /* on a separate line #19: FILE: tcg/ppc/tcg-target.opc.h:1: +/* Target-specific opcodes for host vector expansion. These will be WARNING: Block comments use * on subsequent lines #20: FILE: tcg/ppc/tcg-target.opc.h:2: +/* Target-specific opcodes for host vector expansion. These will be + emitted by tcg_expand_vec_op. For those familiar with GCC internals, WARNING: Block comments use a trailing */ on a separate line #21: FILE: tcg/ppc/tcg-target.opc.h:3: + consider these to be UNSPEC with names. */ total: 0 errors, 4 warnings, 3 lines checked Patch 10/16 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 11/16 Checking commit e293fff80b39 (tcg/ppc: Support vector shift by immediate) 12/16 Checking commit 8924e68f97c6 (tcg/ppc: Support vector multiply) ERROR: code indent should never use tabs #133: FILE: tcg/ppc/tcg-target.inc.c:3219: +^Ibreak;$ total: 1 errors, 0 warnings, 185 lines checked Patch 12/16 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 13/16 Checking commit b52190148845 (tcg/ppc: Support vector dup2) 14/16 Checking commit b5335688c827 (tcg/ppc: Update vector support to v2.06) 15/16 Checking commit 90bbf5116349 (tcg/ppc: Update vector support to v2.07) 16/16 Checking commit 22d133b7d326 (tcg/ppc: Update vector support to v3.00) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-de...@redhat.com
[Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply
From: Richard Henderson
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 112 ++-
tcg/ppc/tcg-target.opc.h | 8
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 766706f..a130192 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -154,7 +154,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 3eb18cb..3005c51 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -526,6 +526,25 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VRLB VX4(4)
+#define VRLH VX4(68)
+#define VRLW VX4(132)
+
+#define VMULEUBVX4(520)
+#define VMULEUHVX4(584)
+#define VMULOUBVX4(8)
+#define VMULOUHVX4(72)
+#define VMSUMUHM VX4(38)
+
+#define VMRGHB VX4(12)
+#define VMRGHH VX4(76)
+#define VMRGHW VX4(140)
+#define VMRGLB VX4(268)
+#define VMRGLH VX4(332)
+#define VMRGLW VX4(396)
+
+#define VPKUHUMVX4(14)
+#define VPKUWUMVX4(78)
#define VAND VX4(1028)
#define VANDC VX4(1092)
@@ -2876,6 +2895,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+case INDEX_op_mul_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
@@ -2989,7 +3009,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
-sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
+sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
+mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
+mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
+muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
+mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
+pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
+rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3078,6 +3104,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+case INDEX_op_ppc_mrgh_vec:
+insn = mrgh_op[vece];
+break;
+case INDEX_op_ppc_mrgl_vec:
+insn = mrgl_op[vece];
+break;
+case INDEX_op_ppc_muleu_vec:
+insn = muleu_op[vece];
+break;
+case INDEX_op_ppc_mulou_vec:
+insn = mulou_op[vece];
+break;
+case INDEX_op_ppc_pkum_vec:
+insn = pkum_op[vece];
+break;
+case INDEX_op_ppc_rotl_vec:
+insn = rotl_op[vece];
+break;
+case INDEX_op_ppc_msum_vec:
+tcg_debug_assert(vece == MO_16);
+tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
+return;
+
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
@@ -3147,6 +3196,53 @@ static void expand_vec_cmp(TCGType type, unsigned vece,
TCGv_vec v0,
}
}
+static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2)
+{
+TCGv_vec t1 = tcg_temp_new_vec(type);
+TCGv_vec t2 = tcg_temp_new_vec(type);
+TCGv_vec t3, t4;
+
+switch (vece) {
+case MO_8:
+case MO_16:
+vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1));
+ break;
+
+case MO_32:
+t3 = tcg_temp_new_vec(type);
+t4 = tcg_temp_new_vec(type);
+tcg_gen_dupi_vec(MO_8, t4, -16);
+vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32,
Re: [Qemu-devel] [Qemu-discuss] qemu-io-cmds does not compile on macOS
On Sun, 23 Jun 2019 at 16:22, Juan Rafael García Blanco wrote: > I think the latest changes to qemu-io-cmds.c make it impossible to compile > under macOS. It now uses clock_gettime, which is not available in this OS. > I’m using 10.9.5; I think this function is now included in 10.12. > > I would step up to try to prepare a patch that uses a replacement in case it > is being compiled in a macOS version that does not include that function. But > I do not know if you want to support these ‘old' macOS versions… Hi; thanks for this report. (This kind of bug report is better sent to qemu-devel or to the launchpad bug tracker -- qemu-discuss is mostly user-to-user conversations, and developers tend to be on -devel; I've cc'd -devel on this.) Our official support policy is that we support building with the two most recent versions of macOS; in practice we might support building with some earlier versions; as of commit 5588840ff77800e839 we definitely dropped support for anything earlier than 10.10. So in theory we don't strongly care about anything before 10.13 at the moment; but if it's easy to avoid the problem it might be worth doing that. Alex, it looks like the relevant commit was one of yours. Could you have a look at how easy it would be to support systems without clock_gettime/CLOCK_MONOTONIC ? I notice that other places in QEMU have #ifdeffery for a lack of CLOCK_MONOTONIC, so we should ideally be consistent, and either support systems without it, or else say we require it and remove the remaining legacy ifdefs... thanks -- PMM
[Qemu-devel] [PATCH v5 15/16] tcg/ppc: Update vector support to v2.07
From: Richard Henderson
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 111 +--
2 files changed, 91 insertions(+), 23 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 40544f9..b8355d0 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -61,6 +61,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
+extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -147,7 +148,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_andc_vec 1
-#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 0c2ad8d..badbe2c 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_2_06_vsx;
+bool have_isa_2_07_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -473,10 +474,12 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LVEWX XO31(71)
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
+#define LXSIWZXXO31(12) /* v2.07 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
+#define STXSIWXXO31(140) /* v2.07 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -487,6 +490,7 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VADDSWSVX4(896)
#define VADDUWSVX4(640)
#define VADDUWMVX4(128)
+#define VADDUDMVX4(192) /* v2.07 */
#define VSUBSBSVX4(1792)
#define VSUBUBSVX4(1536)
@@ -497,47 +501,62 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSUBSWSVX4(1920)
#define VSUBUWSVX4(1664)
#define VSUBUWMVX4(1152)
+#define VSUBUDMVX4(1216) /* v2.07 */
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
+#define VMAXSD VX4(450) /* v2.07 */
#define VMAXUB VX4(2)
#define VMAXUH VX4(66)
#define VMAXUW VX4(130)
+#define VMAXUD VX4(194) /* v2.07 */
#define VMINSB VX4(770)
#define VMINSH VX4(834)
#define VMINSW VX4(898)
+#define VMINSD VX4(962) /* v2.07 */
#define VMINUB VX4(514)
#define VMINUH VX4(578)
#define VMINUW VX4(642)
+#define VMINUD VX4(706) /* v2.07 */
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
+#define VCMPEQUD VX4(199) /* v2.07 */
#define VCMPGTSB VX4(774)
#define VCMPGTSH VX4(838)
#define VCMPGTSW VX4(902)
+#define VCMPGTSD VX4(967) /* v2.07 */
#define VCMPGTUB VX4(518)
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VCMPGTUD VX4(711) /* v2.07 */
#define VSLB VX4(260)
#define VSLH VX4(324)
#define VSLW VX4(388)
+#define VSLD VX4(1476) /* v2.07 */
#define VSRB VX4(516)
#define VSRH VX4(580)
#define VSRW VX4(644)
+#define VSRD VX4(1732) /* v2.07 */
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VSRAD VX4(964) /* v2.07 */
#define VRLB VX4(4)
#define VRLH VX4(68)
#define VRLW VX4(132)
+#define VRLD VX4(196) /* v2.07 */
#define VMULEUBVX4(520)
#define VMULEUHVX4(584)
+#define VMULEUWVX4(648) /* v2.07 */
#define VMULOUBVX4(8)
#define VMULOUHVX4(72)
+#define VMULOUWVX4(136) /* v2.07 */
+#define VMULUWMVX4(137) /* v2.07 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
@@ -555,6 +574,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VNOR VX4(1284)
#define VORVX4(1156)
#define VXOR VX4(1220)
+#define VEQV VX4(1668) /* v2.07 */
+#define VNAND VX4(1412) /* v2.07 */
+#define VORC VX4(1348) /* v2.07 */
#define VSPLTB VX4(524)
#define VSPLTH VX4(588)
@@ -568,6 +590,11 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+#define MFVSRD XO31(51) /* v2.07 */
+#define MFVSRWZXO31(115) /* v2.07 */
+#define MTVSRD XO31(179) /* v2.07
Re: [Qemu-devel] [PULL 0/8] Block patches
On Fri, 21 Jun 2019 at 14:23, Max Reitz wrote: > > The following changes since commit 33d609990621dea6c7d056c86f707b8811320ac1: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging > (2019-06-18 17:00:52 +0100) > > are available in the Git repository at: > > https://github.com/XanClic/qemu.git tags/pull-block-2019-06-21 > > for you to fetch changes up to e2a76186f7948b8b75d1b2b52638de7c2f7f7472: > > iotests: Fix 205 for concurrent runs (2019-06-21 14:40:28 +0200) > > > Block patches: > - The SSH block driver now uses libssh instead of libssh2 > - The VMDK block driver gets read-only support for the seSparse > subformat > - Various fixes > Hi; this failed to build on my s390 box: /home/linux1/qemu/block/ssh.c: In function ‘check_host_key_knownhosts’: /home/linux1/qemu/block/ssh.c:367:27: error: implicit declaration of function ‘ssh_get_fingerprint_hash’ [-Werror=implicit-function-declaration] fingerprint = ssh_get_fingerprint_hash(SSH_PUBLICKEY_HASH_SHA1, ^ /home/linux1/qemu/block/ssh.c:367:13: error: nested extern declaration of ‘ssh_get_fingerprint_hash’ [-Werror=nested-externs] fingerprint = ssh_get_fingerprint_hash(SSH_PUBLICKEY_HASH_SHA1, ^ /home/linux1/qemu/block/ssh.c:367:25: error: assignment makes pointer from integer without a cast [-Werror=int-conversion] fingerprint = ssh_get_fingerprint_hash(SSH_PUBLICKEY_HASH_SHA1, ^ It looks like that function was introduced in libssh 0.8.3, and this box has 0.6.3. (configure has correctly not defined HAVE_LIBSSH_0_8 but this usage is inside a bit of code that's compiled even when that is not defined.) thanks -- PMM
Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes
On Sat, Jun 22, 2019 at 5:02 PM Mark Cave-Ayland wrote: > > On 22/06/2019 15:20, Mark Cave-Ayland wrote: > > > I've just given your tcg-ppc-vsx branch a spin here, and like Howard I'm > > getting > > segfaults trying to launch my MacOS images :( The segfault is weird: it > > doesn't get > > caught by an attached gdb and the qemu-system-ppc process seems to hang > > around like a > > zombie which makes me think that it's probably an illegal instruction of > > some kind, > > but the PPC kernel can't handle it as well as x86 does. > > > > With a bit more work I bisected it down to the first commit in the patchset > > (d8dcbb57e9: "tcg/ppc: Initial backend support for Altivec") and then as an > > experiment I hacked tcg_can_emit_vec_op() to always return 0 to see if that > > made a > > difference, but the segfault still appears. > > > > The commit message mentions that the load and store helpers are also > > improved, so I > > wonder if they are what is causing the error rather than the vector parts? > > Also in > > the kernel log I see the following messages appearing: > > > > [3639669.374942] qemu-system-ppc[28591]: segfault (11) at 64b8 nip f87280 > > lr f8723c > > code 1 in qemu-system-ppc[94e000+aa] > > [3639669.380015] qemu-system-ppc[28591]: code: 93c10038 91810020 90010044 > > 7fc802a6 > > 3fde0059 2e03 3bde6c18 7c9d2378 > > [3639669.385056] qemu-system-ppc[28591]: code: 813e80a0 7cbb2b78 7cda3378 > > 7cf93b78 > > <81428ff8> 9141001c 3940 8129 > > > > Does that help at all? If not let me know if there are any other tests that > > you'd > > like me to try to help debug this. > > One more hint: if I try a build of d8dcbb57e9 along with my > tcg_can_emit_vec_op() > hack and pass --enable-debug-tcg to configure then I get an assert on startup: > > qemu-system-ppc: /home/mca/src/qemu/tcg/tcg.c:2207: process_op_defs: > Assertion `tdefs > != ((void *)0)' failed. > Aborted > Mark, Richard, Howard, David, I just sent v5 of the series, that is (in the sense of net-result of code changes) equivalent to v4, but the patch 1/7 from v4 is now split into ten smaller patches. This was done mainly to enable Mark to perhaps try v5 and bisect, in order to at least somewhat narrow down the culprit. Most likely it will be patch 5 from v5, that is still sizeable, but even if this is the case, we can eliminate other smaller things from consideration. Sincerely, Aleksandar > > ATB, > > Mark. >
[Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec
From: Richard Henderson
Detect during initialization if the emulated CPU supports Altivec,
and store the result in the flag have_isa_altivec. The definition
of Altivec SIMD instructions set evolved over time. Different
generations of Altivec will be distinguished by other flags in TCG,
and they are currently have_isa_2_06 and have_isa_3_00.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 25 +
tcg/ppc/tcg-target.inc.c | 8
2 files changed, 33 insertions(+)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 690fa74..f6283f4 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -58,6 +58,7 @@ typedef enum {
TCG_AREG0 = TCG_REG_R27
} TCGReg;
+extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_3_00;
@@ -135,6 +136,30 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mulsh_i641
#endif
+/*
+ * While technically Altivec could support V64, it has no 64-bit store
+ * instruction and substituting two 32-bit stores makes the generated
+ * code quite large.
+ */
+#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v128 have_isa_altivec
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_cmpsel_vec 0
+
void flush_icache_range(uintptr_t start, uintptr_t stop);
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8e1bba7..26892de 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -64,6 +64,7 @@
static tcg_insn_unit *tb_ret_addr;
+bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_3_00;
@@ -2781,6 +2782,9 @@ static void tcg_target_init(TCGContext *s)
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
+if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
+have_isa_altivec = true;
+}
if (hwcap & PPC_FEATURE_ARCH_2_06) {
have_isa_2_06 = true;
}
@@ -2792,6 +2796,10 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = 0x;
tcg_target_available_regs[TCG_TYPE_I64] = 0x;
+if (have_isa_altivec) {
+tcg_target_available_regs[TCG_TYPE_V64] = 0xull;
+tcg_target_available_regs[TCG_TYPE_V128] = 0xull;
+}
tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
--
2.7.4
[Qemu-devel] [PATCH v5 16/16] tcg/ppc: Update vector support to v3.00
From: Richard Henderson
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++-
2 files changed, 94 insertions(+), 12 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b8355d0..533f0ef 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@ extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
+extern bool have_isa_3_00_vsx;
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i320 /* andi */
@@ -150,7 +151,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
-#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_neg_vec have_isa_3_00_vsx
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index badbe2c..6cc56cf 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -69,6 +69,7 @@ bool have_isa_2_06;
bool have_isa_2_06_vsx;
bool have_isa_2_07_vsx;
bool have_isa_3_00;
+bool have_isa_3_00_vsx;
#define HAVE_ISA_2_06 have_isa_2_06
#define HAVE_ISEL have_isa_2_06
@@ -475,11 +476,16 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
#define LXSIWZXXO31(12) /* v2.07 */
+#define LXV(OPCD(61) | 1) /* v3.00 */
+#define LXSD (OPCD(57) | 2) /* v3.00 */
+#define LXVWSX XO31(364) /* v3.00 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
#define STXSIWXXO31(140) /* v2.07 */
+#define STXV (OPCD(61) | 5) /* v3.00 */
+#define STXSD (OPCD(61) | 2) /* v3.00 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -503,6 +509,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSUBUWMVX4(1152)
#define VSUBUDMVX4(1216) /* v2.07 */
+#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
+#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -532,6 +541,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
#define VCMPGTUD VX4(711) /* v2.07 */
+#define VCMPNEBVX4(7) /* v3.00 */
+#define VCMPNEHVX4(71)/* v3.00 */
+#define VCMPNEWVX4(135) /* v3.00 */
#define VSLB VX4(260)
#define VSLH VX4(324)
@@ -589,11 +601,14 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+#define XXSPLTIB (OPCD(60) | (360 << 1)) /* v3.00 */
#define MFVSRD XO31(51) /* v2.07 */
#define MFVSRWZXO31(115) /* v2.07 */
#define MTVSRD XO31(179) /* v2.07 */
#define MTVSRWZXO31(179) /* v2.07 */
+#define MTVSRDDXO31(435) /* v3.00 */
+#define MTVSRWSXO31(403) /* v3.00 */
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
@@ -917,6 +932,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret,
return;
}
}
+if (have_isa_3_00_vsx && val == (tcg_target_long)dup_const(MO_8, val)) {
+tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11) | 1);
+return;
+}
/*
* Otherwise we must load the value from the constant pool.
@@ -1105,7 +1124,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
TCGReg base, tcg_target_long offset)
{
tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
-bool is_store = false;
+bool is_int_store = false;
TCGReg rs = TCG_REG_TMP1;
switch (opi) {
@@ -1118,11 +1137,20 @@ static void tcg_out_mem_long(TCGContext *s, int opi,
int opx, TCGReg rt,
break;
}
break;
+case LXSD:
+case STXSD:
+align = 3;
+break;
+case LXV: case LXV | 8:
+case STXV: case STXV | 8:
+/* The |8 cases force altivec registers. */
+align = 15;
+break;
case STD:
align = 3;
/* FALLTHRU */
case STB: case STH: case STW:
-is_store = true;
+is_int_store = true;
break;
}
@@ -1131,7 +1159,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx,
[Qemu-devel] [PATCH v5 03/16] tcg/ppc: Introduce macro VX4()
From: Richard Henderson Introduce macro VX4() used for coding/decoding Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 26892de..8c67c99 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -320,6 +320,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) +#define VX4(opc) (OPCD(4)|(opc)) #define B OPCD( 18) #define BC OPCD( 16) -- 2.7.4
[Qemu-devel] [PATCH v5 05/16] tcg/ppc: Add support for load/store/logic/comparison
From: Richard Henderson
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 6 +-
tcg/ppc/tcg-target.inc.c | 506 ---
2 files changed, 484 insertions(+), 28 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index f6283f4..b66a808 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -145,15 +145,15 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
-#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 0fe96bf..d3e4557 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -233,6 +233,10 @@ static const char
*target_parse_constraint(TCGArgConstraint *ct,
ct->ct |= TCG_CT_REG;
ct->u.regs = 0x;
break;
+case 'v':
+ct->ct |= TCG_CT_REG;
+ct->u.regs = 0xull;
+break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0x;
@@ -462,6 +466,39 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define NOPORI /* ori 0,0,0 */
+#define LVXXO31(103)
+#define LVEBX XO31(7)
+#define LVEHX XO31(39)
+#define LVEWX XO31(71)
+
+#define STVX XO31(231)
+#define STVEWX XO31(199)
+
+#define VCMPEQUB VX4(6)
+#define VCMPEQUH VX4(70)
+#define VCMPEQUW VX4(134)
+#define VCMPGTSB VX4(774)
+#define VCMPGTSH VX4(838)
+#define VCMPGTSW VX4(902)
+#define VCMPGTUB VX4(518)
+#define VCMPGTUH VX4(582)
+#define VCMPGTUW VX4(646)
+
+#define VAND VX4(1028)
+#define VANDC VX4(1092)
+#define VNOR VX4(1284)
+#define VORVX4(1156)
+#define VXOR VX4(1220)
+
+#define VSPLTB VX4(524)
+#define VSPLTH VX4(588)
+#define VSPLTW VX4(652)
+#define VSPLTISB VX4(780)
+#define VSPLTISH VX4(844)
+#define VSPLTISW VX4(908)
+
+#define VSLDOI VX4(44)
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -535,6 +572,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
tcg_insn_unit *target;
+int16_t lo;
+int32_t hi;
value += addend;
target = (tcg_insn_unit *)value;
@@ -556,6 +595,20 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
}
*code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
break;
+case R_PPC_ADDR32:
+/*
+ * We are abusing this relocation type. Again, this points to
+ * a pair of insns, lis + load. This is an absolute address
+ * relocation for PPC32 so the lis cannot be removed.
+ */
+lo = value;
+hi = value - lo;
+if (hi + lo != value) {
+return false;
+}
+code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
+code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
+break;
default:
g_assert_not_reached();
}
@@ -567,9 +620,29 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
-tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-if (ret != arg) {
-tcg_out32(s, OR | SAB(arg, ret, arg));
+if (ret == arg) {
+return true;
+}
+switch (type) {
+case TCG_TYPE_I64:
+tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+/* fallthru */
+case TCG_TYPE_I32:
+if (ret < 32 && arg < 32) {
+tcg_out32(s, OR | SAB(arg, ret, arg));
+break;
+} else if (ret < 32 || arg < 32) {
+/* Altivec does not support vector/integer moves. */
+return false;
+}
+/* fallthru */
+case TCG_TYPE_V64:
+case TCG_TYPE_V128:
+tcg_debug_assert(ret >= 32 && arg >= 32);
+tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
+break;
+default:
+
[Qemu-devel] [PATCH v5 13/16] tcg/ppc: Support vector dup2
From: Richard Henderson This is only used for 32-bit hosts. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 9 + 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 3005c51..61732c1 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3104,6 +3104,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } break; +case INDEX_op_dup2_vec: +assert(TCG_TARGET_REG_BITS == 32); +/* With inputs a1 = xLxx, a2 = xHxx */ +tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ +tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ +tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ +return; + case INDEX_op_ppc_mrgh_vec: insn = mrgh_op[vece]; break; @@ -3482,6 +3490,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_ppc_rotl_vec: +case INDEX_op_dup2_vec: return _v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: -- 2.7.4
[Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate
From: Richard Henderson
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 368c250..766706f 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -152,7 +152,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 1
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 03a48c9..3eb18cb 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VSLB VX4(260)
+#define VSLH VX4(324)
+#define VSLW VX4(388)
+#define VSRB VX4(516)
+#define VSRH VX4(580)
+#define VSRW VX4(644)
+#define VSRAB VX4(772)
+#define VSRAH VX4(836)
+#define VSRAW VX4(900)
+
#define VAND VX4(1028)
#define VANDC VX4(1092)
#define VNOR VX4(1284)
@@ -2861,8 +2871,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+case INDEX_op_shli_vec:
+case INDEX_op_shri_vec:
+case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
default:
return 0;
@@ -2970,7 +2986,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
-smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
+smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
+shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
+shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
+sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3017,6 +3036,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_umax_vec:
insn = umax_op[vece];
break;
+case INDEX_op_shlv_vec:
+insn = shlv_op[vece];
+break;
+case INDEX_op_shrv_vec:
+insn = shrv_op[vece];
+break;
+case INDEX_op_sarv_vec:
+insn = sarv_op[vece];
+break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3061,6 +3089,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
}
+static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGArg imm, TCGOpcode opci)
+{
+TCGv_vec t1 = tcg_temp_new_vec(type);
+
+/* Splat w/bytes for xxspltib. */
+tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
+vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+tcg_temp_free_vec(t1);
+}
+
static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGCond cond)
{
@@ -3112,14 +3152,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
{
va_list va;
TCGv_vec v0, v1, v2;
+TCGArg a2;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
-v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+a2 = va_arg(va, TCGArg);
switch (opc) {
+case INDEX_op_shli_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
+break;
+case INDEX_op_shri_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
+break;
+case INDEX_op_sari_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
+break;
case INDEX_op_cmp_vec:
+v2 = temp_tcgv_vec(arg_temp(a2));
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
default:
@@ -3320,6 +3371,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
return _v_v;
case INDEX_op_not_vec:
case
[Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract
From: Richard Henderson
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 20
1 file changed, 20 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index e1142e7..e254fa4 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,14 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDUBMVX4(0)
+#define VADDUHMVX4(64)
+#define VADDUWMVX4(128)
+
+#define VSUBUBMVX4(1024)
+#define VSUBUHMVX4(1088)
+#define VSUBUWMVX4(1152)
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -2831,6 +2839,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+case INDEX_op_add_vec:
+case INDEX_op_sub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
@@ -2932,6 +2942,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
static const uint32_t
+add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
+sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
@@ -2955,6 +2967,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+case INDEX_op_add_vec:
+insn = add_op[vece];
+break;
+case INDEX_op_sub_vec:
+insn = sub_op[vece];
+break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3253,6 +3271,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
return (TCG_TARGET_REG_BITS == 64 ? _S
: TARGET_LONG_BITS == 32 ? _S_S : _S_S_S);
+case INDEX_op_add_vec:
+case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
--
2.7.4
[Qemu-devel] [PATCH v5 10/16] tcg/ppc: Add empty file tcg-target.opc.h
From: Richard Henderson Add empty file tcg-target.opc.h to be used in future. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.opc.h | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 tcg/ppc/tcg-target.opc.h diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h new file mode 100644 index 000..4816a6c --- /dev/null +++ b/tcg/ppc/tcg-target.opc.h @@ -0,0 +1,3 @@ +/* Target-specific opcodes for host vector expansion. These will be + emitted by tcg_expand_vec_op. For those familiar with GCC internals, + consider these to be UNSPEC with names. */ -- 2.7.4
[Qemu-devel] [PATCH v5 04/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
From: Richard Henderson Introduce macros VRT(), VRA(), VRB(), VRC() used for coding/decoding elements of Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8c67c99..0fe96bf 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -474,6 +474,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define MB64(b) ((b)<<5) #define FXM(b) (1 << (19 - (b))) +#define VRT(r) (((r) & 31) << 21) +#define VRA(r) (((r) & 31) << 16) +#define VRB(r) (((r) & 31) << 11) +#define VRC(r) (((r) & 31) << 6) + #define LK1 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) -- 2.7.4
[Qemu-devel] [PATCH v5 06/16] tcg/ppc: Add support for vector maximum/minimum
From: Richard Henderson
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 40 +++-
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b66a808..a86ed57 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -156,7 +156,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index d3e4557..e1142e7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,19 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VMAXSB VX4(258)
+#define VMAXSH VX4(322)
+#define VMAXSW VX4(386)
+#define VMAXUB VX4(2)
+#define VMAXUH VX4(66)
+#define VMAXUW VX4(130)
+#define VMINSB VX4(770)
+#define VMINSH VX4(834)
+#define VMINSW VX4(898)
+#define VMINUB VX4(514)
+#define VMINUH VX4(578)
+#define VMINUW VX4(642)
+
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
@@ -2818,6 +2831,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
+return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
default:
@@ -2916,7 +2934,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
-gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 };
+gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
+smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
+umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
+smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -2933,6 +2955,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+case INDEX_op_smin_vec:
+insn = smin_op[vece];
+break;
+case INDEX_op_umin_vec:
+insn = umin_op[vece];
+break;
+case INDEX_op_smax_vec:
+insn = smax_op[vece];
+break;
+case INDEX_op_umax_vec:
+insn = umax_op[vece];
+break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3225,6 +3259,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
return _v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.7.4
[Qemu-devel] [PATCH v5 14/16] tcg/ppc: Update vector support to v2.06
From: Richard Henderson
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 5 +++--
tcg/ppc/tcg-target.inc.c | 51
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a130192..40544f9 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -60,6 +60,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
+extern bool have_isa_2_06_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -141,7 +142,7 @@ extern bool have_isa_3_00;
* instruction and substituting two 32-bit stores makes the generated
* code quite large.
*/
-#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v64 have_isa_2_06_vsx
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
@@ -157,7 +158,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec have_isa_2_06_vsx
#define TCG_TARGET_HAS_cmpsel_vec 0
void flush_icache_range(uintptr_t start, uintptr_t stop);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 61732c1..0c2ad8d 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -66,6 +66,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
+bool have_isa_2_06_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -470,9 +471,12 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LVEBX XO31(7)
#define LVEHX XO31(39)
#define LVEWX XO31(71)
+#define LXSDX XO31(588) /* v2.06 */
+#define LXVDSX XO31(332) /* v2.06 */
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define STXSDX XO31(716) /* v2.06 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -561,6 +565,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSLDOI VX4(44)
+#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
+#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -887,11 +894,21 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret,
add = 0;
}
-load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
-if (TCG_TARGET_REG_BITS == 64) {
-new_pool_l2(s, rel, s->code_ptr, add, val, val);
+if (have_isa_2_06_vsx) {
+load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
+load_insn |= VRT(ret) | RB(TCG_REG_TMP1) | 1;
+if (TCG_TARGET_REG_BITS == 64) {
+new_pool_label(s, val, rel, s->code_ptr, add);
+} else {
+new_pool_l2(s, rel, s->code_ptr, add, val, val);
+}
} else {
-new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
+if (TCG_TARGET_REG_BITS == 64) {
+new_pool_l2(s, rel, s->code_ptr, add, val, val);
+} else {
+new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+}
}
if (USE_REG_TB) {
@@ -1138,6 +1155,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type,
TCGReg ret,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(ret >= 32);
+if (have_isa_2_06_vsx) {
+tcg_out_mem_long(s, 0, LXSDX | 1, ret & 31, base, offset);
+break;
+}
assert((offset & 7) == 0);
tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset & -16);
if (offset & 8) {
@@ -1181,6 +1202,10 @@ static void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(arg >= 32);
+if (have_isa_2_06_vsx) {
+tcg_out_mem_long(s, 0, STXSDX | 1, arg & 31, base, offset);
+break;
+}
assert((offset & 7) == 0);
if (offset & 8) {
tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
@@ -2900,6 +2925,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
+case INDEX_op_bitsel_vec:
+return have_isa_2_06_vsx;
default:
return 0;
}
@@ -2926,6 +2953,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
break;
case MO_64:
+if
[Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract
From: Richard Henderson
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 36
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a86ed57..368c250 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -155,7 +155,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index e254fa4..108882f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,12 +474,24 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDSBSVX4(768)
+#define VADDUBSVX4(512)
#define VADDUBMVX4(0)
+#define VADDSHSVX4(832)
+#define VADDUHSVX4(576)
#define VADDUHMVX4(64)
+#define VADDSWSVX4(896)
+#define VADDUWSVX4(640)
#define VADDUWMVX4(128)
+#define VSUBSBSVX4(1792)
+#define VSUBUBSVX4(1536)
#define VSUBUBMVX4(1024)
+#define VSUBSHSVX4(1856)
+#define VSUBUHSVX4(1600)
#define VSUBUHMVX4(1088)
+#define VSUBSWSVX4(1920)
+#define VSUBUWSVX4(1664)
#define VSUBUWMVX4(1152)
#define VMAXSB VX4(258)
@@ -2845,6 +2857,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
@@ -2947,6 +2963,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
+usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
+sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
+ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
@@ -2973,6 +2993,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+case INDEX_op_ssadd_vec:
+insn = ssadd_op[vece];
+break;
+case INDEX_op_sssub_vec:
+insn = sssub_op[vece];
+break;
+case INDEX_op_usadd_vec:
+insn = usadd_op[vece];
+break;
+case INDEX_op_ussub_vec:
+insn = ussub_op[vece];
+break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3279,6 +3311,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
--
2.7.4
[Qemu-devel] [PATCH v5 09/16] tcg/ppc: Prepare case for vector multiply
From: Richard Henderson This line is just preparation for full vector multiply support in some of subsequent patches. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 108882f..03a48c9 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3305,6 +3305,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_add_vec: case INDEX_op_sub_vec: +case INDEX_op_mul_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: -- 2.7.4
[Qemu-devel] [PATCH v5 01/16] tcg/ppc: Introduce Altivec registers
From: Richard Henderson
Altivec (in all its versions) supports 32 128-bit vector registers,
whase names are by convention v0, v1,..., and v32.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 11 +-
tcg/ppc/tcg-target.inc.c | 88 ++--
2 files changed, 65 insertions(+), 34 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 7627fb6..690fa74 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -31,7 +31,7 @@
# define TCG_TARGET_REG_BITS 32
#endif
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -45,6 +45,15 @@ typedef enum {
TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
+TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
TCG_REG_CALL_STACK = TCG_REG_R1,
TCG_AREG0 = TCG_REG_R27
} TCGReg;
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 852b894..8e1bba7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -42,6 +42,9 @@
# define TCG_REG_TMP1 TCG_REG_R12
#endif
+#define TCG_VEC_TMP1TCG_REG_V0
+#define TCG_VEC_TMP2TCG_REG_V1
+
#define TCG_REG_TB TCG_REG_R31
#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
@@ -72,39 +75,15 @@ bool have_isa_3_00;
#endif
#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-"r0",
-"r1",
-"r2",
-"r3",
-"r4",
-"r5",
-"r6",
-"r7",
-"r8",
-"r9",
-"r10",
-"r11",
-"r12",
-"r13",
-"r14",
-"r15",
-"r16",
-"r17",
-"r18",
-"r19",
-"r20",
-"r21",
-"r22",
-"r23",
-"r24",
-"r25",
-"r26",
-"r27",
-"r28",
-"r29",
-"r30",
-"r31"
+static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
+"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
};
#endif
@@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
+
+/* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
+TCG_REG_V2, /* call clobbered, vectors */
+TCG_REG_V3,
+TCG_REG_V4,
+TCG_REG_V5,
+TCG_REG_V6,
+TCG_REG_V7,
+TCG_REG_V8,
+TCG_REG_V9,
+TCG_REG_V10,
+TCG_REG_V11,
+TCG_REG_V12,
+TCG_REG_V13,
+TCG_REG_V14,
+TCG_REG_V15,
+TCG_REG_V16,
+TCG_REG_V17,
+TCG_REG_V18,
+TCG_REG_V19,
};
static const int tcg_target_call_iarg_regs[] = {
@@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+
[Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes
From: Aleksandar Markovic Changes since v4: * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into ten smaller patches. * The net result (code-wise) is not changed between former patch 1 and ten new patches. * Remaining (2-7) patches from v4 are applied verbatim. * This means that code-wise v5 and v4 do not differ. * v5 is devised to help debugging, and to better organize the code. Changes since v3: * Add support for bitsel, with the vsx xxsel insn. * Rely on the new relocation overflow handling, so we don't require 3 insns for a vector load. Changes since v2: * Several generic tcg patches to improve dup vs dupi vs dupm. In particular, if a global temp (like guest r10) is not in a host register, we should duplicate from memory instead of loading to an integer register, spilling to stack, loading to a vector register, and then duplicating. * I have more confidence that 32-bit ppc host should work this time around. No testing on that front yet, but I've unified some code sequences with 64-bit ppc host. * Base altivec now supports V128 only. Moved V64 support to Power7 (v2.06), which has 64-bit load/store. * Dropped support for 64-bit vector multiply using Power8. The expansion was too large compared to using integer regs. Richard Henderson (16): tcg/ppc: Introduce Altivec registers tcg/ppc: Introduce flag have_isa_altivec tcg/ppc: Introduce macro VX4() tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() tcg/ppc: Add support for load/store/logic/comparison tcg/ppc: Add support for vector maximum/minimum tcg/ppc: Add support for vector add/subtract tcg/ppc: Add support for vector saturated add/subtract tcg/ppc: Prepare case for vector multiply tcg/ppc: Add empty file tcg-target.opc.h tcg/ppc: Support vector shift by immediate tcg/ppc: Support vector multiply tcg/ppc: Support vector dup2 tcg/ppc: Update vector support to v2.06 tcg/ppc: Update vector support to v2.07 tcg/ppc: Update vector support to v3.00 tcg/ppc/tcg-target.h | 39 +- tcg/ppc/tcg-target.inc.c | 1073 +++--- tcg/ppc/tcg-target.opc.h | 11 + 3 files changed, 1061 insertions(+), 62 deletions(-) create mode 100644 tcg/ppc/tcg-target.opc.h -- 2.7.4
Re: [Qemu-devel] [PATCH v3 2/6] target/arm: Allow setting M mode entry and sp
On Fri, Jun 21, 2019 at 9:38 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Alistair,
>
> On 6/19/19 6:54 AM, Alistair Francis wrote:
> > Add M mode initial entry PC and SP properties.
> >
> > Signed-off-by: Alistair Francis
> > ---
> > target/arm/cpu.c | 47 +++
> > target/arm/cpu.h | 3 +++
> > 2 files changed, 50 insertions(+)
> >
> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> > index 376db154f0..1d83972ab1 100644
> > --- a/target/arm/cpu.c
> > +++ b/target/arm/cpu.c
> > @@ -301,6 +301,9 @@ static void arm_cpu_reset(CPUState *s)
> > */
> > initial_msp = ldl_p(rom);
> > initial_pc = ldl_p(rom + 4);
> > +} else if (cpu->init_sp || cpu->init_entry) {
> > +initial_msp = cpu->init_sp;
> > +initial_pc = cpu->init_entry;
> > } else {
> > /* Address zero not covered by a ROM blob, or the ROM blob
> > * is in non-modifiable memory and this is a second reset after
> > @@ -801,6 +804,38 @@ static void arm_set_init_svtor(Object *obj, Visitor
> > *v, const char *name,
> > visit_type_uint32(v, name, >init_svtor, errp);
> > }
> >
> > +static void arm_get_init_sp(Object *obj, Visitor *v, const char *name,
> > +void *opaque, Error **errp)
> > +{
> > +ARMCPU *cpu = ARM_CPU(obj);
> > +
> > +visit_type_uint32(v, name, >init_sp, errp);
> > +}
> > +
> > +static void arm_set_init_sp(Object *obj, Visitor *v, const char *name,
> > +void *opaque, Error **errp)
> > +{
> > +ARMCPU *cpu = ARM_CPU(obj);
> > +
> > +visit_type_uint32(v, name, >init_sp, errp);
> > +}
> > +
> > +static void arm_get_init_entry(Object *obj, Visitor *v, const char *name,
> > +void *opaque, Error **errp)
> > +{
> > +ARMCPU *cpu = ARM_CPU(obj);
> > +
> > +visit_type_uint32(v, name, >init_entry, errp);
> > +}
> > +
> > +static void arm_set_init_entry(Object *obj, Visitor *v, const char *name,
> > +void *opaque, Error **errp)
> > +{
> > +ARMCPU *cpu = ARM_CPU(obj);
> > +
> > +visit_type_uint32(v, name, >init_entry, errp);
> > +}
> > +
> > void arm_cpu_post_init(Object *obj)
> > {
> > ARMCPU *cpu = ARM_CPU(obj);
> > @@ -913,6 +948,18 @@ void arm_cpu_post_init(Object *obj)
> > object_property_add(obj, "init-svtor", "uint32",
> > arm_get_init_svtor, arm_set_init_svtor,
> > NULL, NULL, _abort);
> > +} else {
> > +/*
> > + * M profile: initial value of the SP and entry. We can't just use
> > + * a simple DEFINE_PROP_UINT32 for this because we want to permit
> > + * the property to be set after realize.
> > + */
>
> This comment is mostly a copy of the other if() branch, maybe you can
> extract one generic comment for the 2 cases.
Good point, I have updated it.
>
> > +object_property_add(obj, "init-sp", "uint32",
> > +arm_get_init_sp, arm_set_init_sp,
> > +NULL, NULL, _abort);
> > +object_property_add(obj, "init-entry", "uint32",
> > +arm_get_init_entry, arm_set_init_entry,
> > +NULL, NULL, _abort);
>
> I'm having difficulties to test your patch :( I tried:
>
> $ arm-softmmu/qemu-system-arm -M emcraft-sf2 \
> -device loader,file=/networking.uImage,cpu-num=0 \
> -d in_asm,int,mmu \
> -global cpu.init-sp=0x2000fff0 \
> -global cpu.init-entry=0xa0008001
> PMSA MPU lookup for execute at 0xa0008000 mmu_idx 65 -> Miss (prot rw-)
> Taking exception 3 [Prefetch Abort]
> ...with CFSR.IACCVIOL
> PMSA MPU lookup for writing at 0x2000ffd0 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffd4 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffd8 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffdc mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffe0 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffe4 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffe8 mmu_idx 65 -> Hit (prot rwx)
> PMSA MPU lookup for writing at 0x2000ffec mmu_idx 65 -> Hit (prot rwx)
> ...taking pending nonsecure exception 3
> PMSA MPU lookup for execute at 0x mmu_idx 67 -> Hit (prot rwx)
>
> IN:
> PMSA MPU lookup for reading at 0x mmu_idx 67 -> Hit (prot rwx)
> 0x: andeqr0, r0, r0
>
> Taking exception 18 [v7M INVSTATE UsageFault]
> qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
>
> R00= R01= R02= R03=
> R04= R05= R06= R07=
> R08= R09= R10= R11=
> R12= R13=2000ffd0 R14=fff9 R15=
> XPSR=4003 -Z-- A handler
> FPSCR:
> Aborted (core
Re: [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions
On Fri, 21 Jun 2019 17:23:44 PDT (-0700), alistai...@gmail.com wrote: On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt wrote: On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote: > On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote: >> >> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote: >> > Based-on: >> > >> > Now that the RISC-V spec has started to be ratified let's update our >> > QEMU implementation. There are a few things going on here: >> > - Add priv version 1.11.0 to QEMU >> > - This is the ratified version of the Privledge spec >> > - There are almost no changes to 1.10 >> > - Mark the 1.09.1 privledge spec as depreated >> > - Let's aim to remove it in two releases >> > - Set priv version 1.11.0 as the default >> > - Remove the user_spec version >> > - This doesn't really mean anything so let's remove it >> > - Add support for the "Counters" extension >> > - Add command line options for Zifencei and Zicsr >> >> Thanks! I'll look at the code, but I've currently got this queued up behind >> your hypervisor patches so it might take a bit. LMK if you want me to invert >> the priority on these. I'll probably be buried until the start of July. > > Let's move the Hypervisor patches to the back then. There is a new > spec version now anyway so I'll have to update them for that. OK. Do you want me to just drop them and wait for a v2 / draft 0.4? I haven't looked at the 0.4 yet, but I think there are still lots of similarities so let's just put Hypervisor patches at the back of the list and see if you get there. It would still be nice to have comments on the v1. Works for me. I'm in Taiwan this week but I'm at the office, so with any luck I'll have some time to actually work. Alistair > > Alistair > >> >> > We can remove the spec version as it's unused and has never been exposed >> > to users. The idea is to match the specs in specifying the version. To >> > handle versions in the future we can extend the extension props to >> > handle version information. >> > >> > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11 >> > >> > NOTE: This isn't supported today as we only have one of each version. >> > >> > This will be a future change if we decide to support multiple versions >> > of extensions. >> > >> > The "priv_spec" string doesn't really match, but I don't have a better >> > way to say "Machine ISA" and "Supervisor ISA" which is what is included >> > in "priv_spec". >> > >> > For completeness I have also added the Counters, Zifencei and Zicsr >> > extensions. >> > >> > Everything else seems to match the spec names/style. >> > >> > Please let me know if I'm missing something. QEMU 4.1 is the first >> > release to support the extensions from the command line, so we can >> > easily change it until then. After that it'll take more work to change >> > the command line interface. >> > >> > Alistair Francis (9): >> > target/riscv: Restructure deprecatd CPUs >> > target/riscv: Add the privledge spec version 1.11.0 >> > target/riscv: Comment in the mcountinhibit CSR >> > target/riscv: Set privledge spec 1.11.0 as default >> > qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 >> > target/riscv: Require either I or E base extension >> > target/riscv: Remove user version information >> > target/riscv: Add support for disabling/enabling Counters >> > target/riscv: Add Zifencei and Zicsr as command line options >> > >> > qemu-deprecated.texi | 8 +++ >> > target/riscv/cpu.c| 72 ++- >> > target/riscv/cpu.h| 19 ++--- >> > target/riscv/cpu_bits.h | 1 + >> > target/riscv/csr.c| 13 +++- >> > .../riscv/insn_trans/trans_privileged.inc.c | 2 +- >> > 6 files changed, 71 insertions(+), 44 deletions(-)
Re: [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
On Thu, 20 Jun 2019 22:40:24 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Jun 21, 2019 at 10:53 AM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Alistair,
>
> On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
>>
>> On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote:
>> >
>> > This adds a reset opcode for sifive_test device to trigger a system
>> > reset for testing purpose.
>> >
>> > Signed-off-by: Bin Meng
>> > ---
>> >
>> > hw/riscv/sifive_test.c | 4
>> > include/hw/riscv/sifive_test.h | 3 ++-
>> > 2 files changed, 6 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
>> > index 24a04d7..cd86831 100644
>> > --- a/hw/riscv/sifive_test.c
>> > +++ b/hw/riscv/sifive_test.c
>> > @@ -21,6 +21,7 @@
>> > #include "qemu/osdep.h"
>> > #include "hw/sysbus.h"
>> > #include "qemu/module.h"
>> > +#include "sysemu/sysemu.h"
>> > #include "target/riscv/cpu.h"
>> > #include "hw/riscv/sifive_test.h"
>> >
>> > @@ -40,6 +41,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
>> > exit(code);
>> > case FINISHER_PASS:
>> > exit(0);
>> > +case FINISHER_RESET:
>> > +qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
>> > +return;
>> > default:
>> > break;
>> > }
>> > diff --git a/include/hw/riscv/sifive_test.h
b/include/hw/riscv/sifive_test.h
>> > index 71d4c9f..c186a31 100644
>> > --- a/include/hw/riscv/sifive_test.h
>> > +++ b/include/hw/riscv/sifive_test.h
>> > @@ -34,7 +34,8 @@ typedef struct SiFiveTestState {
>> >
>> > enum {
>> > FINISHER_FAIL = 0x,
>> > -FINISHER_PASS = 0x
>> > +FINISHER_PASS = 0x,
>> > +FINISHER_RESET = 0x
>>
>> Do you mind sharing where you got this value from? I can't find
>> details on this device in the SiFive manuals.
>>
>
> I don't think this is a device that actually exists on SiFive's
> chipset. It's hypothetical.
The device actually does exist in the hardware, but that's just an
implementation quirk. Essentially what's going on here is that the RTL
contains this device, which has a register and then a behavioral verilog block
that causes simulations to terminate. This is how we exit from tests in RTL
simulation, and we've just gone ahead and implemented the same device in QEMU
in order to make it easy to have compatibility with those bare-metal tests.
Due to how our design flow is set up we end up with exactly the same block in
the ASIC. The register is still there, but the behavioral code to exit
simulations doesn't do anything so it's essentially just a useless device.
Since it's useless we don't bother writing it up in the ASIC documentation, but
it should be in the RTL documentation.
I'm not opposed to extending the interface in the suggested fashion, but I
wanted to check with the hardware team first to see if they're doing anything
with the other numbers. I'm out of the office (and somewhat backed up on code
review) until July, so it might take a bit to dig through this.
Thanks for the clarification. The main reason of adding this
functionality is to provide software a way of rebooting the whole
system. Please provide update after you consult SiFive hardware guys
:)
Ya, it makes sense. My only worry here is that we have some way of doing this
already, in which case I'd just want to make sure it matches.
Re: [Qemu-devel] [Qemu-block] [PATCH v5 00/12] Add support for io_uring
On Sat, Jun 22, 2019 at 4:13 PM Stefan Hajnoczi wrote: > On Tue, Jun 11, 2019 at 10:57 AM Stefan Hajnoczi wrote: > > On Mon, Jun 10, 2019 at 07:18:53PM +0530, Aarushi Mehta wrote: > > > This patch series adds support for the newly developed io_uring Linux AIO > > > interface. Linux io_uring is faster than Linux's AIO asynchronous I/O > > > code, > > > offers efficient buffered asynchronous I/O support, the ability to do I/O > > > without performing a system call via polled I/O, and other efficiency > > > enhancements. > > > > > > Testing it requires a host kernel (5.1+) and the liburing library. > > > Use the option -drive aio=io_uring to enable it. > > > > > > v5: > > > - Adds completion polling > > > - Extends qemu-io > > > - Adds qemu-iotest > > > > Flush is not hooked up. Please use the io_uring IOURING_OP_FSYNC that > > you've already written and connect it to file-posix.c. > > IOURING_OP_FSYNC is in fact synchronous. This means io_uring_enter() > blocks until this operation completes. This is not desirable since > the AIO engine should not block the QEMU thread it's running from for > a long time (e.g. network file system that is not responding). > > I think it's best *not* to use io_uring for fsync. Instead we can > continue to use the thread pool, just like Linux AIO. Looking more closely, this is wrong. Although fsync is synchronous, io_uring takes care to bounce it to the workqueue when submitted via io_uring_enter(). Therefore it appears asynchronous to userspace and we can and should use io_uring for fsync. Stefan
Re: [Qemu-devel] [PATCH] vfio-common.h: Remove inaccurate comment
On Fri, Jun 21, 2019 at 07:01:20PM -0300, Fabiano Rosas wrote:
> This is a left-over from "f4ec5e26ed vfio: Add host side DMA window
> capabilities", which added support to more than one DMA window.
>
> Signed-off-by: Fabiano Rosas
Acked-by: David Gibson
> ---
> include/hw/vfio/vfio-common.h | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
> index a88b69b675..9107bd41c0 100644
> --- a/include/hw/vfio/vfio-common.h
> +++ b/include/hw/vfio/vfio-common.h
> @@ -74,11 +74,6 @@ typedef struct VFIOContainer {
> int error;
> bool initialized;
> unsigned long pgsizes;
> -/*
> - * This assumes the host IOMMU can support only a single
> - * contiguous IOVA window. We may need to generalize that in
> - * future
> - */
> QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
> QLIST_HEAD(, VFIOHostDMAWindow) hostwin_list;
> QLIST_HEAD(, VFIOGroup) group_list;
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [Qemu-devel] [PATCH 0/2] target/i386: kvm: Fix treatment of AMD SVM in nested migration
Patchew URL: https://patchew.org/QEMU/20190621213712.16222-1-liran.a...@oracle.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash make docker-image-fedora V=1 NETWORK=1 time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1 === TEST SCRIPT END === Configure options: --enable-werror --target-list=x86_64-softmmu --prefix=/tmp/qemu-test/install --python=/usr/bin/python3 --enable-debug --enable-sanitizers --cxx=clang++ --cc=clang --host-cc=clang ERROR: "clang" either does not exist or does not work # QEMU configure log Sun Jun 23 08:35:11 UTC 2019 # Configured with: '/tmp/qemu-test/src/configure' '--enable-werror' '--target-list=x86_64-softmmu' '--prefix=/tmp/qemu-test/install' '--python=/usr/bin/python3' '--enable-debug' '--enable-sanitizers' '--cxx=clang++' '--cc=clang' '--host-cc=clang' --- funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 638 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 640 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 642 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 644 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 646 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 648 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 650 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 652 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create temporary file for /var/tmp/ccache/tmp/qemu-conf.stdout: Permission denied funcs: do_compiler do_cc compile_object check_define main lines: 92 122 621 654 0 clang -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o config-temp/qemu-conf.o config-temp/qemu-conf.c ccache: error: Failed to create
