Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing
On Wed, Feb 13, 2019 at 10:12 AM Palmer Dabbelt wrote: > > On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote: > > > > Good catch! > > > > Reviewed-by: Alistair Francis > > Ya, thanks -- that's a somewhat embarrassing bug, as someone else just fixed > one on the line below :). I'll target this for my next PR. > Is there any chance this patch could make it in the next PR? Thanks, - Luke
Re: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
On 29/06/2019 13.53, Philippe Mathieu-Daudé wrote:
> Hi Thomas,
>
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
>> a fixed resolution of 1120 * 832.
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
>
> Please use SHA1 for reference (unlikely case of Bryce pushing a new
> version to his repo):
>
> https://github.com/blanham/qemu-NeXT/blob/34f4323/hw/next-fb.c
But if Bryce ever pushes a new version to his branch, the old SHA IDs
won't be part of a branch anymore, so they will be garbage collected
after a while and the links will become invalid. I think it's better to
refer to the "next-cube" branch.
>> and altered to fit the latest interface of the current QEMU (e.g.
>> the device has been "qdev"-ified etc.).
>>
>> Signed-off-by: Thomas Huth
>> ---
[...]
>> diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
>> new file mode 100644
>> index 00..740102d7e9
>> --- /dev/null
>> +++ b/hw/display/next-fb.c
>> @@ -0,0 +1,157 @@
>> +/*
>> + * NeXT Cube/Station Framebuffer Emulation
>> + *
>> + * Copyright (c) 2011 Bryce Lanham
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> copy
>> + * of this software and associated documentation files (the "Software"), to
>> deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "ui/console.h"
>> +#include "hw/hw.h"
>> +#include "hw/boards.h"
>> +#include "hw/loader.h"
>> +#include "hw/display/framebuffer.h"
>> +#define BITS 8
>
> 'BITS' is not used, remove?
Seems unused, indeed. I'll remove it.
>> +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
>> + int width, int pitch)
>> +{
>> +NeXTFbState *nfbstate = NEXTFB(opaque);
>> +static const uint32_t pal[4] = {
>> +0x, 0xFFAA, 0xFF55, 0xFF00
>> +};
>> +uint32_t *buf = (uint32_t *)d;
>> +int i = 0;
>> +
>> +for (i = 0; i < nfbstate->cols / 4; i++) {
>> +int j = i * 4;
>> +uint8_t src = s[i];
>> +buf[j + 3] = pal[src & 0x3];
>
> 0x3 -> 3?
I prefer the "0x" for bit-wise logical operations.
> or 0b11 :)
Hmm, does that work with all compiler versions that we currently
support? I remember it was not working with older versions of GCC...
Anyway, Bryce used 0x3 in his original code, so I'd like to keep it
close to his original code for the first commit. We can rework stuff
like this in later patches if we like, but for the initial commit, it
would be adequate that you can still recognize the original code, I think.
>> +src >>= 2;
>> +buf[j + 2] = pal[src & 0x3];
>> +src >>= 2;
>> +buf[j + 1] = pal[src & 0x3];
>> +src >>= 2;
>> +buf[j + 0] = pal[src & 0x3];
>> +}
>> +}
>> +
>> +static void nextfb_update(void *opaque)
>> +{
>> +NeXTFbState *s = NEXTFB(opaque);
>> +int dest_width = 4;
>> +int src_width;
>> +int first = 0;
>> +int last = 0;
>> +DisplaySurface *surface = qemu_console_surface(s->con);
>> +
>> +src_width = s->cols / 4 + 8;
>> +dest_width = s->cols * 4;
>
> Since those are currently const, should we move them to NeXTFbState
> and initialize them in nextfb_realize()?
Should not matter much ... I think I'll also keep the original code here
for now.
>> +
>> +if (s->invalidate) {
>> +framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0,
>> + s->cols, src_width);
>> +s->invalidate = 0;
>> +}
>> +
>> +framebuffer_update_display(surface, &s->fbsection, 1120, 832,
>
> 1120 -> s->cols?
> 832 -> s->rows?
>
>> + src_width, dest_width, 0, 1,
>> nextfb_draw_line,
>> + s, &first, &last);
>> +
>> +dpy_gfx_update(s->con, 0, 0, 1120, 832);
>
> Ditto.
Ok.
>> +}
>> +
Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception
On Sat, Jun 29, 2019 at 12:15:44PM +0200, Richard Henderson wrote:
> On 6/28/19 5:50 PM, Lucien Murray-Pitts wrote:
> > op_helper.c
> >static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
> >...
> > if (cs->exception_index == EXCP_ACCESS) {
> > ...
> > do_stack_frame(env, &sp, 7, oldsr, 0, retaddr /*LMP: BROKEN - needs
> > PC NEXT*/);
> >
> > Actually according to the MC68000 manuals the "return address" (the PC
> > saved on
> > the stack) can be upto 5 instructions later due to prefetch. So some pc_next
> > would best be used here.
>
> The way I read it from the 68040 manual, it's "the pc of the instruction
> executing at the time the fault was detected". Well, we did in fact detect
> the
> fault at "retaddr", so that seems to be the right answer. The fact that real
> hardware has a different pipeline and detects the fault later seems
> immaterial,
> and largely irrelevant, since the programmer wasn't given any guarantees for
> what sort of value appears in that slot.
>
I was reading the 68000/68020, and based on your suggestion now the 68060 manual
The 68000 is pretty rough, but I agree you could expect it to more likely be the
next or even upto 5 or so instructions away.
MC68000UM.pdf, 5.4.1 Bus Error Operation
the following information is placed on the supervisor stack:
1. Status register
2. Program counter (two words, which may be up to five words past the
instruction being executed)
MC68000UM.pdf, 6.3.9.1 BUS ERROR.
...value saved for the program counter is advanced 2–10 bytes beyond the
address of the first word of the instruction that made the reference causing
the bus error. If the bus error occurred during the fetch of the next
instruction, the saved program counter has a value in the vicinity of the
current instruction, even if the current instruction is a branch, a jump, or
a return instruction ...
MC68020UM.pdf, 6.1.2 Bus Error Exception
The saved PC value is the logical address of the instruction that was
executing at the time the fault was detected. This is not necessarily the
instruction that initiated the bus cycle since the processor overlaps
execution of instructions
(See 6.4 Bus Fault REcovery and 6.3.11 Return From Exception)
MC68060UM.pdf, 8.4.4.1 Program Counter (PC).
On read access faults, the PC points to the instruction that caused the
access error. This instruction is restarted when an RTE is executed, hence,
the read cycle is re-executed. On read access errors on the second or later
of misaligned reads, the read cycles that are successful prior to the access
error are re-executed since the processor uses a restart model for recovery
from exceptions.
So it would seem the m68k was rather rough, but with the introduction
of MMUs the 68010 and beyond handle it differently. 68010/20 have
pipeline stage retries, and 68060 just returns to retry the instruction.
In my case I think the original firmware expects to return after the
faulting instruction, and the retry of the bus io is to be ignored
(this is a memory map probe routine).
So I think it would take significant work to fake the pipeline retry
in the RTE instruction - so I will hack somethign into the memory region
so it passes the second time the instruciton is exected.
What are your thoughts?
> > I am triggering this from inside my device by doing the following, since
> > that memory address
> > should dynamically cause a bus error (I hope this is the right way to do it)
> >cpuclass->do_unassigned_access( s->cpu, /*addr*/0x0, /*is_write*/1,
> > /*is_exec*/0, opaque, /*size*/4);
>
>
> For a device to raise a bus error, it should return MEMTX_ERROR (or
> something).
> This eventually reaches cpu_transaction_failed, which has all of the data
> that
> you seem to be missing above.
>
I was originally using this but it wasnt doing anything, now that you recommend
it I see why -
thank you for your help.
qemu/accel/tcg/cputlb.c
...
r = memory_region_dispatch_read(mr, mr_offset,
&val, size, iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
section->offset_within_address_space -
section->offset_within_region;
cpu_transaction_failed(cpu, physaddr, addr, size, access_type,
mmu_idx, iotlbentry->attrs, r, retaddr);
}
...
As you say this call directly flows through to CPUClass->transaction_failed
( as found in the struct for CPUClass in qemu/include/qom/cpu.h )
However for the m68k the do_transaction_failed function pointer field
has not been implemented.
I implemented it in a rudamentary fashion copying from already existing
m68k_cpu_unassigned_access. I really dont know if this is the right way.
void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
[Qemu-devel] [PATCH 2/2] .travis.yml: Let the avocado job run the NeXTcube tests
Signed-off-by: Philippe Mathieu-Daudé --- .travis.yml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index aeb9b211cd..16907b5a78 100644 --- a/.travis.yml +++ b/.travis.yml @@ -231,7 +231,7 @@ matrix: # Acceptance (Functional) tests - env: -- CONFIG="--python=/usr/bin/python3 --target-list=x86_64-softmmu,mips-softmmu,mips64el-softmmu,aarch64-softmmu,arm-softmmu,s390x-softmmu,alpha-softmmu" +- CONFIG="--python=/usr/bin/python3 --target-list=x86_64-softmmu,mips-softmmu,mips64el-softmmu,aarch64-softmmu,arm-softmmu,s390x-softmmu,alpha-softmmu,m68k-softmmu" - TEST_CMD="make check-acceptance" after_failure: - cat tests/results/latest/job.log @@ -240,6 +240,9 @@ matrix: packages: - python3-pip - python3.5-venv +- tesseract-ocr + + # Using newer GCC with sanitizers - addons: apt: -- 2.19.1
[Qemu-devel] [PATCH 1/2] tests/acceptance: Add test of NeXTcube framebuffer using OCR
Add a test of the NeXTcube framebuffer using the Tesseract OCR
engine on a screenshot of the framebuffer device.
The test is very quick:
$ avocado --show=app,ocr run tests/acceptance/machine_m68k_nextcube.py
JOB ID : f7d3c27976047036dc568183baf64c04863d9985
JOB LOG: ~/avocado/job-results/job-2019-06-29T16.18-f7d3c27/job.log
(1/1)
tests/acceptance/machine_m68k_nextcube.py:NextCubeMachine.test_bootrom_framebuffer:
|ocr:
ue r pun Honl'flx ; 5‘ 55‘
avg nca 25 MHZ, memary jag m
Backplane slat «a
Ethernet address a a r a r3 2
Memgry sackets aea canflqured far 16MB Darlly page made stMs but have 16MB
page made stMs )nstalled
Memgry sackets a and 1 canflqured far 16MB Darlly page made stMs but have
16MB page made stMs )nstalled
[...]
Yestlnq the rpu, 5::
system test raneg Errar egge 51
Egg: cammand
Default pggc devlce nut fauna
NEXY>I
PASS (3.59 s)
RESULTS: PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 3.97 s
Documentation on how to install tesseract:
https://github.com/tesseract-ocr/tesseract/wiki#installation
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/machine_m68k_nextcube.py | 50 +++
1 file changed, 50 insertions(+)
create mode 100644 tests/acceptance/machine_m68k_nextcube.py
diff --git a/tests/acceptance/machine_m68k_nextcube.py
b/tests/acceptance/machine_m68k_nextcube.py
new file mode 100644
index 00..cf061292a7
--- /dev/null
+++ b/tests/acceptance/machine_m68k_nextcube.py
@@ -0,0 +1,50 @@
+# Functional test that boots a VM and run OCR on the framebuffer
+#
+# Copyright (c) Philippe Mathieu-Daudé
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import logging
+import time
+import distutils.spawn
+
+from avocado import skipUnless
+from avocado_qemu import Test
+from avocado.utils import process
+
+
+class NextCubeMachine(Test):
+
+timeout = 15
+
+@skipUnless(distutils.spawn.find_executable('tesseract'),
+'tesseract OCR tool not installed')
+def test_bootrom_framebuffer(self):
+"""
+:avocado: tags=arch:m68k
+:avocado: tags=machine:next-cube
+:avocado: tags=device:framebuffer
+"""
+rom_url = ('http://www.nextcomputers.org/NeXTfiles/Software/ROM_Files/'
+ '68040_Non-Turbo_Chipset/Rev_2.5_v66.BIN')
+rom_hash = 'b3534796abae238a0111299fc406a9349f7fee24'
+rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash)
+
+self.vm.set_machine('next-cube')
+self.vm.add_args('-bios', rom_path)
+self.vm.launch()
+
+self.log.info('VM launched, waiting for display')
+# FIXME how to catch the 'displaysurface_create 1120x832' trace-event?
+time.sleep(2)
+
+screenshot_path = self.workdir + "dump"
+self.vm.command('human-monitor-command',
+command_line='screendump %s' % screenshot_path)
+
+console_logger = logging.getLogger('ocr')
+proc = process.run("tesseract %s stdout" % screenshot_path)
+console_logger.debug(proc.stdout_text)
+self.assertIn('Backplane', proc.stdout_text)
+self.assertIn('Ethernet address', proc.stdout_text)
--
2.19.1
[Qemu-devel] [PATCH 0/2] tests/acceptance: Add test of NeXTcube framebuffer using OCR
Hi, I was looking at Thomas' last series [*] where he adds the NeXTcube machine, thinking about enforcing a new rule "new machines must have tests". Then I realized the UART is not yet implemented, so our current sample tests are not helpful. Since the framebuffer is working, I gave a try at dumping the screen content via the HMP 'screendump' command, then parsing the screenshot with an OCR tool. The default ROM dump the bootlog to a console. Using the old good tesseract tool we can recover some useful words to be sure the guest is sane, its framebuffer is definitively working. This test takes less than 6s on Travis-CI: https://travis-ci.org/philmd/qemu/builds/552174983#L1836 AVOCADO tests/acceptance (3/9) /home/travis/build/philmd/qemu/tests/acceptance/machine_m68k_nextcube.py:NextCubeMachine.test_bootrom_framebuffer: PASS (5.69 s) Regards, Phil. Based-on: 20190628181536.13729-1-h...@tuxfamily.org [*] "m68k: Add basic support for the NeXTcube machine" https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06393.html Philippe Mathieu-Daudé (2): tests/acceptance: Add test of NeXTcube framebuffer using OCR .travis.yml: Let the avocado job run the NeXTcube tests .travis.yml | 5 ++- tests/acceptance/machine_m68k_nextcube.py | 50 +++ 2 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 tests/acceptance/machine_m68k_nextcube.py -- 2.19.1
Re: [Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine
On 6/28/19 8:15 PM, Thomas Huth wrote: > Bryce apparently never got around to work on this again, so I'll have > another try now ... > > During Google Summer of Code 2011, Bryce Lanham added the possibility to > emulate the NeXTcube machine in QEMU, e.g. see this URL for some details: > > https://wiki.qemu.org/Google_Summer_of_Code_2011#NeXT_machines_system_emulation I'm not sure you used the correct URL, the GSoC entry is not very useful. I found this one more helpful (v1): https://lists.gnu.org/archive/html/qemu-devel/2011-08/msg02158.html > But since the machine requires a 68040 CPU and this was not included in > upstream QEMU in 2011 yet, the patches have never been merged to upstream. > > Then, during the last years, Laurent completed the full 680x0 support in > upstream QEMU, so we could finally merge the NeXTcube support, too. > > The QEMU interfaces changed a lot since 2011, so I had to modify the > sources quite a bit, but with the attached patches, it is now possible > to boot up to the firmware monitor again. > > Note that boot device emulation is either still missing (network and SCSI), > so you can not boot any operating systems with this machine yet. I have > the patches for these devices in my brach here: > > https://gitlab.com/huth/qemu/commits/next-cube > > ... but they are not quite working yet, so I'll submit them later once > they have been fixed and the basic support patches of this series have > been merged. > > v2: > - Don't use memory_region_allocate_system_memory() for the framebuffer >device anymore > - Turn the keyboard device into a proper QOM device > - Put the global variables in the third patch into the machine state >structure > - Got rid of the "//" C++ comments
[Qemu-devel] [PATCH] tcg: Fix expansion of INDEX_op_not_vec
This operation can always be emitted, even if we need to
fall back to xor. Adjust the assertions to match.
Signed-off-by: Richard Henderson
---
While expanding the AA64 vector ORC, Altivec needs a bare NOT operation.
This failure does not appear for aa64 or power8 hosts because we have a
native vector orc and so do not go down this path. It also does not
appear for x86_64 because we don't have a native vector not, and so go
down a different path to expand not via xor with -1.
r~
---
tcg/tcg-op-vec.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index c8fdc24f56..6714991bf4 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -90,6 +90,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
case INDEX_op_bitsel_vec:
/* These opcodes are mandatory and should not be listed. */
g_assert_not_reached();
+case INDEX_op_not_vec:
+/* These opcodes have generic expansions using the above. */
+g_assert_not_reached();
default:
break;
}
@@ -438,11 +441,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a,
TCGOpcode opc)
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
{
+const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
TCGv_vec t = tcg_const_ones_vec_matching(r);
tcg_gen_xor_vec(0, r, a, t);
tcg_temp_free_vec(t);
}
+tcg_swap_vecop_list(hold_list);
}
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
--
2.17.1
Re: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes
Patchew URL:
https://patchew.org/QEMU/20190629130017.2973-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes
Message-id: 20190629130017.2973-1-richard.hender...@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
735e428 tcg/ppc: Update vector support to v3.00
d5df8ce tcg/ppc: Update vector support to v2.07
70bae8c tcg/ppc: Update vector support to v2.06
cdcb6fd tcg/ppc: Enable Altivec detection
5eca04a tcg/ppc: Support vector dup2
9a92a5b tcg/ppc: Support vector multiply
9dcbbb5 tcg/ppc: Support vector shift by immediate
5707cff tcg/ppc: Prepare case for vector multiply
4e8c856 tcg/ppc: Add support for vector saturated add/subtract
8542349 tcg/ppc: Add support for vector add/subtract
09dcca3 tcg/ppc: Add support for vector maximum/minimum
940d802 tcg/ppc: Add support for load/store/logic/comparison
1354b48 tcg/ppc: Enable tcg backend vector compilation
ce65dc7 tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
c15e076 tcg/ppc: Introduce macro VX4()
a351796 tcg/ppc: Introduce Altivec registers
=== OUTPUT BEGIN ===
1/16 Checking commit a35179674cf2 (tcg/ppc: Introduce Altivec registers)
2/16 Checking commit c15e076c7d0f (tcg/ppc: Introduce macro VX4())
ERROR: spaces required around that '|' (ctx:VxV)
#21: FILE: tcg/ppc/tcg-target.inc.c:322:
+#define VX4(opc) (OPCD(4)|(opc))
^
total: 1 errors, 0 warnings, 7 lines checked
Patch 2/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/16 Checking commit ce65dc76f743 (tcg/ppc: Introduce macros VRT(), VRA(),
VRB(), VRC())
4/16 Checking commit 1354b48a4dce (tcg/ppc: Enable tcg backend vector
compilation)
WARNING: Block comments use a leading /* on a separate line
#155: FILE: tcg/ppc/tcg-target.inc.c:2842:
+if (hwcap & /* PPC_FEATURE_HAS_ALTIVEC -- NOT YET */ 0) {
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#173:
new file mode 100644
total: 0 errors, 2 warnings, 138 lines checked
Patch 4/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/16 Checking commit 940d8027994d (tcg/ppc: Add support for
load/store/logic/comparison)
6/16 Checking commit 09dcca3c9f87 (tcg/ppc: Add support for vector
maximum/minimum)
7/16 Checking commit 8542349a45f4 (tcg/ppc: Add support for vector add/subtract)
8/16 Checking commit 4e8c8565186d (tcg/ppc: Add support for vector saturated
add/subtract)
9/16 Checking commit 5707cff60faf (tcg/ppc: Prepare case for vector multiply)
10/16 Checking commit 9dcbbb561046 (tcg/ppc: Support vector shift by immediate)
11/16 Checking commit 9a92a5bffebd (tcg/ppc: Support vector multiply)
ERROR: code indent should never use tabs
#133: FILE: tcg/ppc/tcg-target.inc.c:3220:
+^Ibreak;$
total: 1 errors, 0 warnings, 185 lines checked
Patch 11/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/16 Checking commit 5eca04a86aea (tcg/ppc: Support vector dup2)
13/16 Checking commit cdcb6fdbe190 (tcg/ppc: Enable Altivec detection)
14/16 Checking commit 70bae8c6b3df (tcg/ppc: Update vector support to v2.06)
15/16 Checking commit d5df8cec3718 (tcg/ppc: Update vector support to v2.07)
16/16 Checking commit 735e428f5f2a (tcg/ppc: Update vector support to v3.00)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190629130017.2973-1-richard.hender...@linaro.org/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-de...@redhat.com
[Qemu-devel] [PATCH v6 05/16] tcg/ppc: Add support for load/store/logic/comparison
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 6 +-
tcg/ppc/tcg-target.inc.c | 472 ---
2 files changed, 442 insertions(+), 36 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index f6283f468b..b66a808259 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -145,15 +145,15 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
-#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index b938e9aac5..87c418ebf4 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -233,6 +233,10 @@ static const char
*target_parse_constraint(TCGArgConstraint *ct,
ct->ct |= TCG_CT_REG;
ct->u.regs = 0x;
break;
+case 'v':
+ct->ct |= TCG_CT_REG;
+ct->u.regs = 0xull;
+break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0x;
@@ -462,6 +466,39 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define NOPORI /* ori 0,0,0 */
+#define LVXXO31(103)
+#define LVEBX XO31(7)
+#define LVEHX XO31(39)
+#define LVEWX XO31(71)
+
+#define STVX XO31(231)
+#define STVEWX XO31(199)
+
+#define VCMPEQUB VX4(6)
+#define VCMPEQUH VX4(70)
+#define VCMPEQUW VX4(134)
+#define VCMPGTSB VX4(774)
+#define VCMPGTSH VX4(838)
+#define VCMPGTSW VX4(902)
+#define VCMPGTUB VX4(518)
+#define VCMPGTUH VX4(582)
+#define VCMPGTUW VX4(646)
+
+#define VAND VX4(1028)
+#define VANDC VX4(1092)
+#define VNOR VX4(1284)
+#define VORVX4(1156)
+#define VXOR VX4(1220)
+
+#define VSPLTB VX4(524)
+#define VSPLTH VX4(588)
+#define VSPLTW VX4(652)
+#define VSPLTISB VX4(780)
+#define VSPLTISH VX4(844)
+#define VSPLTISW VX4(908)
+
+#define VSLDOI VX4(44)
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -535,6 +572,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
tcg_insn_unit *target;
+int16_t lo;
+int32_t hi;
value += addend;
target = (tcg_insn_unit *)value;
@@ -556,6 +595,20 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
}
*code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
break;
+case R_PPC_ADDR32:
+/*
+ * We are abusing this relocation type. Again, this points to
+ * a pair of insns, lis + load. This is an absolute address
+ * relocation for PPC32 so the lis cannot be removed.
+ */
+lo = value;
+hi = value - lo;
+if (hi + lo != value) {
+return false;
+}
+code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
+code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
+break;
default:
g_assert_not_reached();
}
@@ -567,9 +620,29 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
-tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-if (ret != arg) {
-tcg_out32(s, OR | SAB(arg, ret, arg));
+if (ret == arg) {
+return true;
+}
+switch (type) {
+case TCG_TYPE_I64:
+tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+/* fallthru */
+case TCG_TYPE_I32:
+if (ret < TCG_REG_V0 && arg < TCG_REG_V0) {
+tcg_out32(s, OR | SAB(arg, ret, arg));
+break;
+} else if (ret < TCG_REG_V0 || arg < TCG_REG_V0) {
+/* Altivec does not support vector/integer moves. */
+return false;
+}
+/* fallthru */
+case TCG_TYPE_V64:
+case TCG_TYPE_V128:
+tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
+tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
+break;
+
[Qemu-devel] [PATCH v6 16/16] tcg/ppc: Update vector support to v3.00
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++-
2 files changed, 94 insertions(+), 12 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b8355d0a56..533f0ef510 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@ extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
+extern bool have_isa_3_00_vsx;
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i320 /* andi */
@@ -150,7 +151,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
-#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_neg_vec have_isa_3_00_vsx
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index af86ab07dd..6715f29d4a 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -69,6 +69,7 @@ bool have_isa_2_06;
bool have_isa_2_06_vsx;
bool have_isa_2_07_vsx;
bool have_isa_3_00;
+bool have_isa_3_00_vsx;
#define HAVE_ISA_2_06 have_isa_2_06
#define HAVE_ISEL have_isa_2_06
@@ -475,11 +476,16 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
#define LXSIWZXXO31(12) /* v2.07 */
+#define LXV(OPCD(61) | 1) /* v3.00 */
+#define LXSD (OPCD(57) | 2) /* v3.00 */
+#define LXVWSX XO31(364) /* v3.00 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
#define STXSIWXXO31(140) /* v2.07 */
+#define STXV (OPCD(61) | 5) /* v3.00 */
+#define STXSD (OPCD(61) | 2) /* v3.00 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -503,6 +509,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSUBUWMVX4(1152)
#define VSUBUDMVX4(1216) /* v2.07 */
+#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
+#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -532,6 +541,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
#define VCMPGTUD VX4(711) /* v2.07 */
+#define VCMPNEBVX4(7) /* v3.00 */
+#define VCMPNEHVX4(71)/* v3.00 */
+#define VCMPNEWVX4(135) /* v3.00 */
#define VSLB VX4(260)
#define VSLH VX4(324)
@@ -589,11 +601,14 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+#define XXSPLTIB (OPCD(60) | (360 << 1)) /* v3.00 */
#define MFVSRD XO31(51) /* v2.07 */
#define MFVSRWZXO31(115) /* v2.07 */
#define MTVSRD XO31(179) /* v2.07 */
#define MTVSRWZXO31(179) /* v2.07 */
+#define MTVSRDDXO31(435) /* v3.00 */
+#define MTVSRWSXO31(403) /* v3.00 */
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
@@ -924,6 +939,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret,
return;
}
}
+if (have_isa_3_00_vsx && val == (tcg_target_long)dup_const(MO_8, val)) {
+tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11) | 1);
+return;
+}
/*
* Otherwise we must load the value from the constant pool.
@@ -1112,7 +1131,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
TCGReg base, tcg_target_long offset)
{
tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
-bool is_store = false;
+bool is_int_store = false;
TCGReg rs = TCG_REG_TMP1;
switch (opi) {
@@ -1125,11 +1144,20 @@ static void tcg_out_mem_long(TCGContext *s, int opi,
int opx, TCGReg rt,
break;
}
break;
+case LXSD:
+case STXSD:
+align = 3;
+break;
+case LXV: case LXV | 8:
+case STXV: case STXV | 8:
+/* The |8 cases force altivec registers. */
+align = 15;
+break;
case STD:
align = 3;
/* FALLTHRU */
case STB: case STH: case STW:
-is_store = true;
+is_int_store = true;
break;
}
@@ -1138,7 +1166,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
if (r
[Qemu-devel] [PATCH v6 06/16] tcg/ppc: Add support for vector maximum/minimum
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 40 +++-
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b66a808259..a86ed57303 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -156,7 +156,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 87c418ebf4..9c5630dc8a 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,19 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VMAXSB VX4(258)
+#define VMAXSH VX4(322)
+#define VMAXSW VX4(386)
+#define VMAXUB VX4(2)
+#define VMAXUH VX4(66)
+#define VMAXUW VX4(130)
+#define VMINSB VX4(770)
+#define VMINSH VX4(834)
+#define VMINSW VX4(898)
+#define VMINUB VX4(514)
+#define VMINUH VX4(578)
+#define VMINUW VX4(642)
+
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
@@ -2820,6 +2833,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
+return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
default:
@@ -2917,7 +2935,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
-gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 };
+gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
+smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
+umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
+smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -2934,6 +2956,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+case INDEX_op_smin_vec:
+insn = smin_op[vece];
+break;
+case INDEX_op_umin_vec:
+insn = umin_op[vece];
+break;
+case INDEX_op_smax_vec:
+insn = smax_op[vece];
+break;
+case INDEX_op_umax_vec:
+insn = umax_op[vece];
+break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3226,6 +3260,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+case INDEX_op_smax_vec:
+case INDEX_op_smin_vec:
+case INDEX_op_umax_vec:
+case INDEX_op_umin_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.17.1
[Qemu-devel] [PATCH v6 14/16] tcg/ppc: Update vector support to v2.06
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 5 ++--
tcg/ppc/tcg-target.inc.c | 51
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a130192cbd..40544f996d 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -60,6 +60,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
+extern bool have_isa_2_06_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -141,7 +142,7 @@ extern bool have_isa_3_00;
* instruction and substituting two 32-bit stores makes the generated
* code quite large.
*/
-#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v64 have_isa_2_06_vsx
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
@@ -157,7 +158,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec have_isa_2_06_vsx
#define TCG_TARGET_HAS_cmpsel_vec 0
void flush_icache_range(uintptr_t start, uintptr_t stop);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index c6defd4df7..50d1b5612c 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -66,6 +66,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
+bool have_isa_2_06_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -470,9 +471,12 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LVEBX XO31(7)
#define LVEHX XO31(39)
#define LVEWX XO31(71)
+#define LXSDX XO31(588) /* v2.06 */
+#define LXVDSX XO31(332) /* v2.06 */
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define STXSDX XO31(716) /* v2.06 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -561,6 +565,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSLDOI VX4(44)
+#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
+#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -887,11 +894,21 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret,
add = 0;
}
-load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
-if (TCG_TARGET_REG_BITS == 64) {
-new_pool_l2(s, rel, s->code_ptr, add, val, val);
+if (have_isa_2_06_vsx) {
+load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
+load_insn |= VRT(ret) | RB(TCG_REG_TMP1) | 1;
+if (TCG_TARGET_REG_BITS == 64) {
+new_pool_label(s, val, rel, s->code_ptr, add);
+} else {
+new_pool_l2(s, rel, s->code_ptr, add, val, val);
+}
} else {
-new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
+if (TCG_TARGET_REG_BITS == 64) {
+new_pool_l2(s, rel, s->code_ptr, add, val, val);
+} else {
+new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+}
}
if (USE_REG_TB) {
@@ -1139,6 +1156,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type,
TCGReg ret,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(ret >= TCG_REG_V0);
+if (have_isa_2_06_vsx) {
+tcg_out_mem_long(s, 0, LXSDX | 1, ret, base, offset);
+break;
+}
assert((offset & 7) == 0);
tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
if (offset & 8) {
@@ -1183,6 +1204,10 @@ static void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(arg >= TCG_REG_V0);
+if (have_isa_2_06_vsx) {
+tcg_out_mem_long(s, 0, STXSDX | 1, arg, base, offset);
+break;
+}
assert((offset & 7) == 0);
if (offset & 8) {
tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
@@ -2902,6 +2927,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
+case INDEX_op_bitsel_vec:
+return have_isa_2_06_vsx;
default:
return 0;
}
@@ -2928,6 +2955,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
break;
case MO_64:
+if (have_isa_2_06_vsx) {
+
[Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 128 ++-
2 files changed, 103 insertions(+), 28 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 40544f996d..b8355d0a56 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -61,6 +61,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
+extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -147,7 +148,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_andc_vec 1
-#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 50d1b5612c..af86ab07dd 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_2_06_vsx;
+bool have_isa_2_07_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -473,10 +474,12 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define LVEWX XO31(71)
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
+#define LXSIWZXXO31(12) /* v2.07 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
+#define STXSIWXXO31(140) /* v2.07 */
#define VADDSBSVX4(768)
#define VADDUBSVX4(512)
@@ -487,6 +490,7 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VADDSWSVX4(896)
#define VADDUWSVX4(640)
#define VADDUWMVX4(128)
+#define VADDUDMVX4(192) /* v2.07 */
#define VSUBSBSVX4(1792)
#define VSUBUBSVX4(1536)
@@ -497,47 +501,62 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSUBSWSVX4(1920)
#define VSUBUWSVX4(1664)
#define VSUBUWMVX4(1152)
+#define VSUBUDMVX4(1216) /* v2.07 */
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
+#define VMAXSD VX4(450) /* v2.07 */
#define VMAXUB VX4(2)
#define VMAXUH VX4(66)
#define VMAXUW VX4(130)
+#define VMAXUD VX4(194) /* v2.07 */
#define VMINSB VX4(770)
#define VMINSH VX4(834)
#define VMINSW VX4(898)
+#define VMINSD VX4(962) /* v2.07 */
#define VMINUB VX4(514)
#define VMINUH VX4(578)
#define VMINUW VX4(642)
+#define VMINUD VX4(706) /* v2.07 */
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
+#define VCMPEQUD VX4(199) /* v2.07 */
#define VCMPGTSB VX4(774)
#define VCMPGTSH VX4(838)
#define VCMPGTSW VX4(902)
+#define VCMPGTSD VX4(967) /* v2.07 */
#define VCMPGTUB VX4(518)
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VCMPGTUD VX4(711) /* v2.07 */
#define VSLB VX4(260)
#define VSLH VX4(324)
#define VSLW VX4(388)
+#define VSLD VX4(1476) /* v2.07 */
#define VSRB VX4(516)
#define VSRH VX4(580)
#define VSRW VX4(644)
+#define VSRD VX4(1732) /* v2.07 */
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VSRAD VX4(964) /* v2.07 */
#define VRLB VX4(4)
#define VRLH VX4(68)
#define VRLW VX4(132)
+#define VRLD VX4(196) /* v2.07 */
#define VMULEUBVX4(520)
#define VMULEUHVX4(584)
+#define VMULEUWVX4(648) /* v2.07 */
#define VMULOUBVX4(8)
#define VMULOUHVX4(72)
+#define VMULOUWVX4(136) /* v2.07 */
+#define VMULUWMVX4(137) /* v2.07 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
@@ -555,6 +574,9 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VNOR VX4(1284)
#define VORVX4(1156)
#define VXOR VX4(1220)
+#define VEQV VX4(1668) /* v2.07 */
+#define VNAND VX4(1412) /* v2.07 */
+#define VORC VX4(1348) /* v2.07 */
#define VSPLTB VX4(524)
#define VSPLTH VX4(588)
@@ -568,6 +590,11 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4))/* v2.06 */
+#define MFVSRD XO31(51) /* v2.07 */
+#define MFVSRWZXO31(115) /* v2.07 */
+#define MTVSRD XO31(179) /* v2.07 */
+#define MTVSRWZ
[Qemu-devel] [PATCH v6 04/16] tcg/ppc: Enable tcg backend vector compilation
Introduce all of the flags required to enable tcg backend vector support,
and a runtime flag to indicate the host supports Altivec instructions.
For now, do not actually set have_isa_altivec to true, because we have not
yet added all of the code to actually generate all of the required insns.
However, we must define these flags in order to disable ifndefs that create
stub versions of the functions added here.
The change to tcg_out_movi works around a buglet in tcg.c wherein if we
do not define tcg_out_dupi_vec we get a declared but not defined Werror,
but if we only declare it we get a defined but not used Werror. We need
to this change to tcg_out_movi eventually anyway, so it's no biggie.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 25
tcg/ppc/tcg-target.opc.h | 5
tcg/ppc/tcg-target.inc.c | 65 ++--
3 files changed, 92 insertions(+), 3 deletions(-)
create mode 100644 tcg/ppc/tcg-target.opc.h
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 690fa744e1..f6283f468b 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -58,6 +58,7 @@ typedef enum {
TCG_AREG0 = TCG_REG_R27
} TCGReg;
+extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_3_00;
@@ -135,6 +136,30 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mulsh_i641
#endif
+/*
+ * While technically Altivec could support V64, it has no 64-bit store
+ * instruction and substituting two 32-bit stores makes the generated
+ * code quite large.
+ */
+#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v128 have_isa_altivec
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_cmpsel_vec 0
+
void flush_icache_range(uintptr_t start, uintptr_t stop);
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
new file mode 100644
index 00..fa680dd6a0
--- /dev/null
+++ b/tcg/ppc/tcg-target.opc.h
@@ -0,0 +1,5 @@
+/*
+ * Target-specific opcodes for host vector expansion. These will be
+ * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index cfbd7ff12c..b938e9aac5 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -64,6 +64,7 @@
static tcg_insn_unit *tb_ret_addr;
+bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_3_00;
@@ -717,10 +718,31 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
-tcg_target_long arg)
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long val)
{
-tcg_out_movi_int(s, type, ret, arg, false);
+g_assert_not_reached();
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg)
+{
+switch (type) {
+case TCG_TYPE_I32:
+case TCG_TYPE_I64:
+tcg_debug_assert(ret < TCG_REG_V0);
+tcg_out_movi_int(s, type, ret, arg, false);
+break;
+
+case TCG_TYPE_V64:
+case TCG_TYPE_V128:
+tcg_debug_assert(ret >= TCG_REG_V0);
+tcg_out_dupi_vec(s, type, ret, arg);
+break;
+
+default:
+g_assert_not_reached();
+}
}
static bool mask_operand(uint32_t c, int *mb, int *me)
@@ -2605,6 +2627,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
}
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+g_assert_not_reached();
+}
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+TCGReg dst, TCGReg src)
+{
+g_assert_not_reached();
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg out, TCGReg base, intptr_t offset)
+{
+g_assert_not_reached();
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+g_assert_not_reached();
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGT
[Qemu-devel] [PATCH v6 07/16] tcg/ppc: Add support for vector add/subtract
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 20
1 file changed, 20 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9c5630dc8a..c31694cc78 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,14 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDUBMVX4(0)
+#define VADDUHMVX4(64)
+#define VADDUWMVX4(128)
+
+#define VSUBUBMVX4(1024)
+#define VSUBUHMVX4(1088)
+#define VSUBUWMVX4(1152)
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -2833,6 +2841,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+case INDEX_op_add_vec:
+case INDEX_op_sub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
@@ -2933,6 +2943,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
static const uint32_t
+add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
+sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
@@ -2956,6 +2968,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+case INDEX_op_add_vec:
+insn = add_op[vece];
+break;
+case INDEX_op_sub_vec:
+insn = sub_op[vece];
+break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3254,6 +3272,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
return (TCG_TARGET_REG_BITS == 64 ? &S_S
: TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+case INDEX_op_add_vec:
+case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
--
2.17.1
[Qemu-devel] [PATCH v6 09/16] tcg/ppc: Prepare case for vector multiply
This line is just preparation for full vector multiply support in some of subsequent patches. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 307e809fad..e19400609c 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3306,6 +3306,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_add_vec: case INDEX_op_sub_vec: +case INDEX_op_mul_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: -- 2.17.1
[Qemu-devel] [PATCH v6 08/16] tcg/ppc: Add support for vector saturated add/subtract
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 36
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a86ed57303..368c250c6a 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -155,7 +155,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index c31694cc78..307e809fad 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,12 +474,24 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDSBSVX4(768)
+#define VADDUBSVX4(512)
#define VADDUBMVX4(0)
+#define VADDSHSVX4(832)
+#define VADDUHSVX4(576)
#define VADDUHMVX4(64)
+#define VADDSWSVX4(896)
+#define VADDUWSVX4(640)
#define VADDUWMVX4(128)
+#define VSUBSBSVX4(1792)
+#define VSUBUBSVX4(1536)
#define VSUBUBMVX4(1024)
+#define VSUBSHSVX4(1856)
+#define VSUBUHSVX4(1600)
#define VSUBUHMVX4(1088)
+#define VSUBSWSVX4(1920)
+#define VSUBUWSVX4(1664)
#define VSUBUWMVX4(1152)
#define VMAXSB VX4(258)
@@ -2847,6 +2859,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
@@ -2948,6 +2964,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
+usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
+sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
+ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
@@ -2974,6 +2994,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+case INDEX_op_ssadd_vec:
+insn = ssadd_op[vece];
+break;
+case INDEX_op_sssub_vec:
+insn = sssub_op[vece];
+break;
+case INDEX_op_usadd_vec:
+insn = usadd_op[vece];
+break;
+case INDEX_op_ussub_vec:
+insn = ussub_op[vece];
+break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3280,6 +3312,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+case INDEX_op_ssadd_vec:
+case INDEX_op_sssub_vec:
+case INDEX_op_usadd_vec:
+case INDEX_op_ussub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
--
2.17.1
[Qemu-devel] [PATCH v6 10/16] tcg/ppc: Support vector shift by immediate
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 368c250c6a..766706fd30 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -152,7 +152,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 1
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index e19400609c..7ddef950f7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VSLB VX4(260)
+#define VSLH VX4(324)
+#define VSLW VX4(388)
+#define VSRB VX4(516)
+#define VSRH VX4(580)
+#define VSRW VX4(644)
+#define VSRAB VX4(772)
+#define VSRAH VX4(836)
+#define VSRAW VX4(900)
+
#define VAND VX4(1028)
#define VANDC VX4(1092)
#define VNOR VX4(1284)
@@ -2863,8 +2873,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+case INDEX_op_shli_vec:
+case INDEX_op_shri_vec:
+case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
default:
return 0;
@@ -2971,7 +2987,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
-smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
+smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
+shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
+shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
+sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3018,6 +3037,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_umax_vec:
insn = umax_op[vece];
break;
+case INDEX_op_shlv_vec:
+insn = shlv_op[vece];
+break;
+case INDEX_op_shrv_vec:
+insn = shrv_op[vece];
+break;
+case INDEX_op_sarv_vec:
+insn = sarv_op[vece];
+break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3062,6 +3090,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
}
+static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGArg imm, TCGOpcode opci)
+{
+TCGv_vec t1 = tcg_temp_new_vec(type);
+
+/* Splat w/bytes for xxspltib. */
+tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
+vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+tcg_temp_free_vec(t1);
+}
+
static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGCond cond)
{
@@ -3113,14 +3153,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
{
va_list va;
TCGv_vec v0, v1, v2;
+TCGArg a2;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
-v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+a2 = va_arg(va, TCGArg);
switch (opc) {
+case INDEX_op_shli_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
+break;
+case INDEX_op_shri_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
+break;
+case INDEX_op_sari_vec:
+expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
+break;
case INDEX_op_cmp_vec:
+v2 = temp_tcgv_vec(arg_temp(a2));
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
default:
@@ -3321,6 +3372,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.17.1
[Qemu-devel] [PATCH v6 01/16] tcg/ppc: Introduce Altivec registers
Altivec supports 32 128-bit vector registers, whose names are
by convention v0 through v31.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 11 -
tcg/ppc/tcg-target.inc.c | 88 +---
2 files changed, 65 insertions(+), 34 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 7627fb62d3..690fa744e1 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -31,7 +31,7 @@
# define TCG_TARGET_REG_BITS 32
#endif
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -45,6 +45,15 @@ typedef enum {
TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
+TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
TCG_REG_CALL_STACK = TCG_REG_R1,
TCG_AREG0 = TCG_REG_R27
} TCGReg;
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 852b8940fb..8e1bba7824 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -42,6 +42,9 @@
# define TCG_REG_TMP1 TCG_REG_R12
#endif
+#define TCG_VEC_TMP1TCG_REG_V0
+#define TCG_VEC_TMP2TCG_REG_V1
+
#define TCG_REG_TB TCG_REG_R31
#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
@@ -72,39 +75,15 @@ bool have_isa_3_00;
#endif
#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-"r0",
-"r1",
-"r2",
-"r3",
-"r4",
-"r5",
-"r6",
-"r7",
-"r8",
-"r9",
-"r10",
-"r11",
-"r12",
-"r13",
-"r14",
-"r15",
-"r16",
-"r17",
-"r18",
-"r19",
-"r20",
-"r21",
-"r22",
-"r23",
-"r24",
-"r25",
-"r26",
-"r27",
-"r28",
-"r29",
-"r30",
-"r31"
+static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
+"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
};
#endif
@@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
+
+/* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
+TCG_REG_V2, /* call clobbered, vectors */
+TCG_REG_V3,
+TCG_REG_V4,
+TCG_REG_V5,
+TCG_REG_V6,
+TCG_REG_V7,
+TCG_REG_V8,
+TCG_REG_V9,
+TCG_REG_V10,
+TCG_REG_V11,
+TCG_REG_V12,
+TCG_REG_V13,
+TCG_REG_V14,
+TCG_REG_V15,
+TCG_REG_V16,
+TCG_REG_V17,
+TCG_REG_V18,
+TCG_REG_V19,
};
static const int tcg_target_call_iarg_regs[] = {
@@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
[Qemu-devel] [PATCH v6 02/16] tcg/ppc: Introduce macro VX4()
Introduce macro VX4() used for encoding Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8e1bba7824..9e560db993 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -319,6 +319,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) +#define VX4(opc) (OPCD(4)|(opc)) #define B OPCD( 18) #define BC OPCD( 16) -- 2.17.1
[Qemu-devel] [PATCH v6 11/16] tcg/ppc: Support vector multiply
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 112 ++-
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 766706fd30..a130192cbd 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -154,7 +154,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
index fa680dd6a0..db24a11987 100644
--- a/tcg/ppc/tcg-target.opc.h
+++ b/tcg/ppc/tcg-target.opc.h
@@ -3,3 +3,11 @@
* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
* consider these to be UNSPEC with names.
*/
+
+DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
+DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 7ddef950f7..cb604b76a3 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -526,6 +526,25 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VRLB VX4(4)
+#define VRLH VX4(68)
+#define VRLW VX4(132)
+
+#define VMULEUBVX4(520)
+#define VMULEUHVX4(584)
+#define VMULOUBVX4(8)
+#define VMULOUHVX4(72)
+#define VMSUMUHM VX4(38)
+
+#define VMRGHB VX4(12)
+#define VMRGHH VX4(76)
+#define VMRGHW VX4(140)
+#define VMRGLB VX4(268)
+#define VMRGLH VX4(332)
+#define VMRGLW VX4(396)
+
+#define VPKUHUMVX4(14)
+#define VPKUWUMVX4(78)
#define VAND VX4(1028)
#define VANDC VX4(1092)
@@ -2878,6 +2897,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+case INDEX_op_mul_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
@@ -2990,7 +3010,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
-sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
+sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
+mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
+mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
+muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
+mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
+pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
+rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3079,6 +3105,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+case INDEX_op_ppc_mrgh_vec:
+insn = mrgh_op[vece];
+break;
+case INDEX_op_ppc_mrgl_vec:
+insn = mrgl_op[vece];
+break;
+case INDEX_op_ppc_muleu_vec:
+insn = muleu_op[vece];
+break;
+case INDEX_op_ppc_mulou_vec:
+insn = mulou_op[vece];
+break;
+case INDEX_op_ppc_pkum_vec:
+insn = pkum_op[vece];
+break;
+case INDEX_op_ppc_rotl_vec:
+insn = rotl_op[vece];
+break;
+case INDEX_op_ppc_msum_vec:
+tcg_debug_assert(vece == MO_16);
+tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
+return;
+
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
@@ -3148,6 +3197,53 @@ static void expand_vec_cmp(TCGType type, unsigned vece,
TCGv_vec v0,
}
}
+static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2)
+{
+TCGv_vec t1 = tcg_temp_new_vec(type);
+TCGv_vec t2 = tcg_temp_new_vec(type);
+TCGv_vec t3, t4;
+
+switch (vece) {
+case MO_8:
+case MO_16:
+vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_ar
[Qemu-devel] [PATCH v6 03/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
Introduce macros VRT(), VRA(), VRB(), VRC() used for encoding elements of Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 9e560db993..cfbd7ff12c 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -473,6 +473,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define MB64(b) ((b)<<5) #define FXM(b) (1 << (19 - (b))) +#define VRT(r) (((r) & 31) << 21) +#define VRA(r) (((r) & 31) << 16) +#define VRB(r) (((r) & 31) << 11) +#define VRC(r) (((r) & 31) << 6) + #define LK1 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) -- 2.17.1
[Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes
Changes since v5: * Disable runtime altivec detection until all of the required opcodes are implemented. Because dup2 was last, that really means all of the pure altivec bits, so the initial patches are not bisectable in any meaningful sense. I thought about reshuffling dup2 earlier, but that created too many conflicts and I was too lazy. * Rearranged the patches a little bit to make sure that each one actually builds, which was not the case before. * Folded in the fix to tcg_out_mem_long, as discussed in the followup within the v4 thread. Changes since v4: * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into ten smaller patches. * The net result (code-wise) is not changed between former patch 1 and ten new patches. * Remaining (2-7) patches from v4 are applied verbatim. * This means that code-wise v5 and v4 do not differ. * v5 is devised to help debugging, and to better organize the code. Changes since v3: * Add support for bitsel, with the vsx xxsel insn. * Rely on the new relocation overflow handling, so we don't require 3 insns for a vector load. Changes since v2: * Several generic tcg patches to improve dup vs dupi vs dupm. In particular, if a global temp (like guest r10) is not in a host register, we should duplicate from memory instead of loading to an integer register, spilling to stack, loading to a vector register, and then duplicating. * I have more confidence that 32-bit ppc host should work this time around. No testing on that front yet, but I've unified some code sequences with 64-bit ppc host. * Base altivec now supports V128 only. Moved V64 support to Power7 (v2.06), which has 64-bit load/store. * Dropped support for 64-bit vector multiply using Power8. The expansion was too large compared to using integer regs. Richard Henderson (16): tcg/ppc: Introduce Altivec registers tcg/ppc: Introduce macro VX4() tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() tcg/ppc: Enable tcg backend vector compilation tcg/ppc: Add support for load/store/logic/comparison tcg/ppc: Add support for vector maximum/minimum tcg/ppc: Add support for vector add/subtract tcg/ppc: Add support for vector saturated add/subtract tcg/ppc: Prepare case for vector multiply tcg/ppc: Support vector shift by immediate tcg/ppc: Support vector multiply tcg/ppc: Support vector dup2 tcg/ppc: Enable Altivec detection tcg/ppc: Update vector support to v2.06 tcg/ppc: Update vector support to v2.07 tcg/ppc: Update vector support to v3.00 tcg/ppc/tcg-target.h | 39 +- tcg/ppc/tcg-target.opc.h | 13 + tcg/ppc/tcg-target.inc.c | 1091 +++--- 3 files changed, 1076 insertions(+), 67 deletions(-) create mode 100644 tcg/ppc/tcg-target.opc.h -- 2.17.1
[Qemu-devel] [PATCH v6 13/16] tcg/ppc: Enable Altivec detection
Now that we have implemented the required tcg operations,
we can enable detection of host vector support.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9a44670180..c6defd4df7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -3513,7 +3513,7 @@ static void tcg_target_init(TCGContext *s)
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
-if (hwcap & /* PPC_FEATURE_HAS_ALTIVEC -- NOT YET */ 0) {
+if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
have_isa_altivec = true;
}
if (hwcap & PPC_FEATURE_ARCH_2_06) {
--
2.17.1
[Qemu-devel] [PATCH v6 12/16] tcg/ppc: Support vector dup2
This is only used for 32-bit hosts. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.inc.c | 9 + 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index cb604b76a3..9a44670180 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3105,6 +3105,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } break; +case INDEX_op_dup2_vec: +assert(TCG_TARGET_REG_BITS == 32); +/* With inputs a1 = xLxx, a2 = xHxx */ +tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ +tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ +tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ +return; + case INDEX_op_ppc_mrgh_vec: insn = mrgh_op[vece]; break; @@ -3483,6 +3491,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_ppc_rotl_vec: +case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: -- 2.17.1
Re: [Qemu-devel] [RFC 1/1] hw/pvrdma: Add live migration support
On Fri, 28 Jun 2019 at 16:56, Dr. David Alan Gilbert
wrote:
>
> * Yuval Shaia (yuval.sh...@oracle.com) wrote:
> > On Fri, Jun 21, 2019 at 08:15:41PM +0530, Sukrit Bhatnagar wrote:
> > > Define and register SaveVMHandlers pvrdma_save and
> > > pvrdma_load for saving and loading the device state,
> > > which currently includes only the dma, command slot
> > > and response slot addresses.
> > >
> > > Remap the DSR, command slot and response slot upon
> > > loading the addresses in the pvrdma_load function.
> > >
> > > Cc: Marcel Apfelbaum
> > > Cc: Yuval Shaia
> > > Signed-off-by: Sukrit Bhatnagar
> > > ---
> > > hw/rdma/vmw/pvrdma_main.c | 56 +++
> > > 1 file changed, 56 insertions(+)
> > >
> > > diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
> > > index adcf79cd63..cd8573173c 100644
> > > --- a/hw/rdma/vmw/pvrdma_main.c
> > > +++ b/hw/rdma/vmw/pvrdma_main.c
> > > @@ -28,6 +28,7 @@
> > > #include "sysemu/sysemu.h"
> > > #include "monitor/monitor.h"
> > > #include "hw/rdma/rdma.h"
> > > +#include "migration/register.h"
> > >
> > > #include "../rdma_rm.h"
> > > #include "../rdma_backend.h"
> > > @@ -592,9 +593,62 @@ static void pvrdma_shutdown_notifier(Notifier *n,
> > > void *opaque)
> > > pvrdma_fini(pci_dev);
> > > }
> > >
> > > +static void pvrdma_save(QEMUFile *f, void *opaque)
> > > +{
> > > +PVRDMADev *dev = PVRDMA_DEV(opaque);
> > > +
> > > +qemu_put_be64(f, dev->dsr_info.dma);
> > > +qemu_put_be64(f, dev->dsr_info.dsr->cmd_slot_dma);
> > > +qemu_put_be64(f, dev->dsr_info.dsr->resp_slot_dma);
> > > +}
> > > +
> > > +static int pvrdma_load(QEMUFile *f, void *opaque, int version_id)
> > > +{
> > > +PVRDMADev *dev = PVRDMA_DEV(opaque);
> > > +PCIDevice *pci_dev = PCI_DEVICE(dev);
> > > +
> > > +// Remap DSR
> > > +dev->dsr_info.dma = qemu_get_be64(f);
> > > +dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
> > > +sizeof(struct
> > > pvrdma_device_shared_region));
> > > +if (!dev->dsr_info.dsr) {
> > > +rdma_error_report("Failed to map to DSR");
> > > +return -1;
> > > +}
> > > +qemu_log("pvrdma_load: successfully remapped to DSR\n");
> > > +
> > > +// Remap cmd slot
> > > +dev->dsr_info.dsr->cmd_slot_dma = qemu_get_be64(f);
> > > +dev->dsr_info.req = rdma_pci_dma_map(pci_dev,
> > > dev->dsr_info.dsr->cmd_slot_dma,
> > > + sizeof(union pvrdma_cmd_req));
> > > +if (!dev->dsr_info.req) {
> >
> > So this is where you hit the error, right?
> > All looks good to me, i wonder why the first pci_dma_map works fine but
> > second fails where the global BounceBuffer is marked as used.
> >
> > Anyone?
>
> I've got a few guesses:
> a) My reading of address_space_map is that it gives a bounce buffer
> pointer and then it has to be freed; so if it's going wrong and using a
> bounce buffer, then the 1st call would work and only the 2nd would fail.
In the scenario without any migration, the device is init and load_dsr()
is called when the guest writes to DSR in BAR1 of pvrdma.
Inside the load_dsr(), there are similar calls to rdma_pci_dma_map().
The difference is that when the address_space_map() is called there,
!memory_access_is_direct() condition is FALSE.
So, there is no use for BounceBuffer.
In the migration scenario, when the device at dest calls load and
subsequently rdma_pci_dma_map(), the !memory_access_is_direct()
condition is TRUE.
So, the first rdma_pci_dma_map() will set BounceBuffer from FALSE to
TRUE and succeed. But, the subsequent calls will fail at atomic_xchg().
This BounceBuffer is only freed when address_space_unmap() is called.
I am guessing that when the address is translated to one in FlatView,
the MemoryRegion returned at dest is causing the issue.
To be honest, at this point I am not sure how FlatView translations works.
I tried adding qemu_log to memory_access_is_direct(), but I guess it is
called too many times, so the vm stalls before it even starts.
> b) Perhaps the dma address read from the stream is bad, and isn't
> pointing into RAM properly - and that's why you're getting a bounce
> buffer.
I have logged the addresses saved in pvrdma_save(), and the ones
loaded in pvrdma_load(). They are same. So, there is no problem in the
stream itself, I suppose.
> c) Do you have some ordering problems? i.e. is this code happening
> before some other device has been loaded/initialised? If you're relying
> on some other state, then perhaps the right thing is to perform these
> mappings later, at the end of migration, not during the loading itself.
The device which is saved/loaded before pvrdma is vmxnet3, on which
the pvrdma depends.
I have included the last few lines of my traces during migration below.
The pvrdma migration is performed in this last part of migration.
I had added some debug messages at various places to see which parts
of the
Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
On 6/29/19 2:26 PM, Philippe Mathieu-Daudé wrote:
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> It is still quite incomplete (no SCSI, no floppy emulation, no network,
>> etc.), but the firmware already shows up the debug monitor prompt in the
>> framebuffer display, so at least the very basics are already working.
>>
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
>>
>> and altered quite a bit to fit the latest interface and coding conventions
>> of the current QEMU.
>>
>> Signed-off-by: Thomas Huth
>> ---
>> hw/m68k/Makefile.objs | 2 +-
>> hw/m68k/next-cube.c | 988
>> include/hw/m68k/next-cube.h | 38 ++
>> 3 files changed, 1027 insertions(+), 1 deletion(-)
>> create mode 100644 hw/m68k/next-cube.c
>>
>> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
>> index 688002cac1..f25854730d 100644
>> --- a/hw/m68k/Makefile.objs
>> +++ b/hw/m68k/Makefile.objs
>> @@ -1,3 +1,3 @@
>> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
>> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
>> -obj-$(CONFIG_NEXTCUBE) += next-kbd.o
>> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
>> diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
>> new file mode 100644
>> index 00..700d386fb9
>> --- /dev/null
>> +++ b/hw/m68k/next-cube.c
>> @@ -0,0 +1,988 @@
>> +/*
>> + * NeXT Cube System Driver
>> + *
>> + * Copyright (c) 2011 Bryce Lanham
>> + *
>> + * This code is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published
>> + * by the Free Software Foundation; either version 2 of the License,
>> + * or (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "exec/hwaddr.h"
>> +#include "exec/address-spaces.h"
>> +#include "sysemu/sysemu.h"
>> +#include "sysemu/qtest.h"
>> +#include "hw/hw.h"
>> +#include "hw/m68k/next-cube.h"
>> +#include "hw/boards.h"
>> +#include "hw/loader.h"
>> +#include "hw/scsi/esp.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
>> +#include "hw/block/fdc.h"
>> +#include "qapi/error.h"
>> +#include "ui/console.h"
>> +#include "target/m68k/cpu.h"
>> +
>> +/* #define DEBUG_NEXT */
>> +#ifdef DEBUG_NEXT
>> +#define DPRINTF(fmt, ...) \
>> +do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
>> +#else
>> +#define DPRINTF(fmt, ...) do { } while (0)
>> +#endif
>> +
>> +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
>> +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
>> +
>> +#define ENTRY 0x011e
>> +#define RAM_SIZE0x400
>> +#define ROM_FILE"rom66.bin"
>
> Where can we find this file to test your work?
I found one:
http://www.nextcomputers.org/NeXTfiles/Software/ROM_Files/68040_Non-Turbo_Chipset/
I have to say I'm impressed :)
Let me share this comment from
http://old-computers.com/museum/computer.asp?c=277
"did you know the 040 nextcube was actually used for graphics design at
id software at the time doom was made?"
=)
Re: [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file
On 6/28/19 8:15 PM, Thomas Huth wrote: > I don't have much clue about the NeXT hardware, but at least I know now > the source files a little bit, so I volunteer to pick up patches and send > PULL requests for them until someone else with more knowledge steps up > to do this job instead. > > Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé > --- > MAINTAINERS | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index cad58b9487..6b4fa7221f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -900,6 +900,13 @@ F: hw/char/mcf_uart.c > F: hw/net/mcf_fec.c > F: include/hw/m68k/mcf*.h > > +NeXTcube > +M: Thomas Huth > +S: Odd Fixes > +F: hw/m68k/next-*.c > +F: hw/display/next-fb.c > +F: include/hw/m68k/next-cube.h > + > MicroBlaze Machines > --- > petalogix_s3adsp1800 >
Re: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is still quite incomplete (no SCSI, no floppy emulation, no network,
> etc.), but the firmware already shows up the debug monitor prompt in the
> framebuffer display, so at least the very basics are already working.
>
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c
>
> and altered quite a bit to fit the latest interface and coding conventions
> of the current QEMU.
>
> Signed-off-by: Thomas Huth
> ---
> hw/m68k/Makefile.objs | 2 +-
> hw/m68k/next-cube.c | 988
> include/hw/m68k/next-cube.h | 38 ++
> 3 files changed, 1027 insertions(+), 1 deletion(-)
> create mode 100644 hw/m68k/next-cube.c
>
> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
> index 688002cac1..f25854730d 100644
> --- a/hw/m68k/Makefile.objs
> +++ b/hw/m68k/Makefile.objs
> @@ -1,3 +1,3 @@
> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
> -obj-$(CONFIG_NEXTCUBE) += next-kbd.o
> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o
> diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
> new file mode 100644
> index 00..700d386fb9
> --- /dev/null
> +++ b/hw/m68k/next-cube.c
> @@ -0,0 +1,988 @@
> +/*
> + * NeXT Cube System Driver
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * This code is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published
> + * by the Free Software Foundation; either version 2 of the License,
> + * or (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/qtest.h"
> +#include "hw/hw.h"
> +#include "hw/m68k/next-cube.h"
> +#include "hw/boards.h"
> +#include "hw/loader.h"
> +#include "hw/scsi/esp.h"
> +#include "hw/sysbus.h"
> +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
> +#include "hw/block/fdc.h"
> +#include "qapi/error.h"
> +#include "ui/console.h"
> +#include "target/m68k/cpu.h"
> +
> +/* #define DEBUG_NEXT */
> +#ifdef DEBUG_NEXT
> +#define DPRINTF(fmt, ...) \
> +do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do { } while (0)
> +#endif
> +
> +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
> +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
> +
> +#define ENTRY 0x011e
> +#define RAM_SIZE0x400
> +#define ROM_FILE"rom66.bin"
Where can we find this file to test your work?
> +
> +typedef struct next_dma {
> +uint32_t csr;
> +
> +uint32_t saved_next;
> +uint32_t saved_limit;
> +uint32_t saved_start;
> +uint32_t saved_stop;
> +
> +uint32_t next;
> +uint32_t limit;
> +uint32_t start;
> +uint32_t stop;
> +
> +uint32_t next_initbuf;
> +uint32_t size;
> +} next_dma;
> +
> +typedef struct {
> +MachineState parent;
> +
> +uint32_t int_mask;
> +uint32_t int_status;
> +
> +uint8_t scsi_csr_1;
> +uint8_t scsi_csr_2;
> +next_dma dma[10];
> +qemu_irq *scsi_irq;
> +qemu_irq scsi_dma;
> +qemu_irq scsi_reset;
> +qemu_irq *fd_irq;
> +
> +uint32_t scr1;
> +uint32_t scr2;
> +
> +uint8_t rtc_ram[32];
> +} NeXTState;
> +
> +/* Thanks to NeXT forums for this */
> +/*
> +static const uint8_t rtc_ram3[32] = {
> +0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
> +0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
> +};
> +*/
> +static const uint8_t rtc_ram2[32] = {
> +0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
> +0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
> +};
> +
> +#define SCR2_RTCLK 0x2
> +#define SCR2_RTDATA 0x4
> +#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
> +
> +static void nextscr2_write(NeXTState *s, uint32_t val, int size)
> +{
> +static int led;
> +static int phase;
> +static uint8_t old_scr2;
> +static uint8_t rtc_command;
> +static uint8_t rtc_value;
> +static uint8_t rtc_status = 0x90;
> +static uint8_t rtc_return;
> +uint8_t scr2_2;
> +
> +if (size == 4) {
> +scr2_2 = (val >> 8) & 0xFF;
> +} else {
> +scr2_2 = val & 0xFF;
> +}
> +
> +if (val & 0x1) {
> +DPRINTF("fault!\n");
> +led++;
> +if (led == 10) {
> +DPRINTF("LED flashing, possible fault!\n");
> +led = 0;
> +}
> +}
> +
> +if (scr2_2 & 0x1) {
> +/* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */
> +if (phase == -1) {
> +phase = 0;
> +}
> +/* If we are in going down clock...
Re: [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: add module
On 6/28/19 7:06 PM, Jan Bobek wrote:
> That's true. (Although not in all cases; see Table 2-5 in the Intel Manual,
> Volume 2, Chapter 2, Section 2.2.1 "REX Prefixes" for some cases when REX.B
> is not decoded.) This is a compromise that I've accepted, at least for v1
> of the patch series. Note that this problem is also present in config entries
> such as
>
> PMOVMSKBSSE 11010111 !emit { modrm(mod => MOD_DIRECT,
> reg => ~REG_ESP); }
>
> Here, we force MODRM.REG != 4, but this avoids not only ESP/RSP, but
> also R12.
>
> Hmmm... I suppose I have some ideas on how to do it better. I'll try
> to fix this, though I suspect getting it 100 % right might be
> difficult and time-consuming.
I wonder if it might be better to do the randomization at a higher level:
* Pick full registers, either 3 bits for 32-bit or 4 bits for 64-bit,
and eventually 5 bits for avx512 z-regs for evex encoding. Let
risugen_x86_asm encode those depending on the chosen encoding.
* Pick only register vs memory for MODRM.MOD. If memory, randomize
base + index + shift + disp. Let risugen_x86_asm encode those
values into the modrm+sib+offset.
r~
Re: [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is likely still quite incomplete (e.g. mouse and interrupts are not
> implemented yet), but it is good enough for keyboard input at the firmware
> monitor.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-kbd.c
Please use commit sha1 in link.
> and altered to fit the latest interface of the current QEMU (e.g. to use
> memory_region_init_io() instead of cpu_register_physical_memory()).
>
> Signed-off-by: Thomas Huth
> ---
> hw/m68k/Makefile.objs | 1 +
> hw/m68k/next-kbd.c | 320
> include/hw/m68k/next-cube.h | 3 +
> 3 files changed, 324 insertions(+)
> create mode 100644 hw/m68k/next-kbd.c
>
> diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
> index 482f8477b4..688002cac1 100644
> --- a/hw/m68k/Makefile.objs
> +++ b/hw/m68k/Makefile.objs
> @@ -1,2 +1,3 @@
> obj-$(CONFIG_AN5206) += an5206.o mcf5206.o
> obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o
> +obj-$(CONFIG_NEXTCUBE) += next-kbd.o
> diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c
> new file mode 100644
> index 00..73e90f9b62
> --- /dev/null
> +++ b/hw/m68k/next-kbd.c
> @@ -0,0 +1,320 @@
> +/*
> + * QEMU NeXT Keyboard/Mouse emulation
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +/*
> + * This is admittedly hackish, but works well enough for basic input. Mouse
> + * support will be added once we can boot something that needs the mouse.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "exec/address-spaces.h"
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/m68k/next-cube.h"
> +#include "ui/console.h"
> +#include "sysemu/sysemu.h"
> +
> +#define TYPE_NEXTKBD "next-kbd"
> +#define NEXTKBD(obj) OBJECT_CHECK(NextKBDState, (obj), TYPE_NEXTKBD)
> +
> +/* following defintions from next68k netbsd */
> +#define CSR_INT 0x0080
> +#define CSR_DATA 0x0040
> +
> +#define KD_KEYMASK0x007f
> +#define KD_DIRECTION 0x0080 /* pressed or released */
> +#define KD_CNTL 0x0100
> +#define KD_LSHIFT 0x0200
> +#define KD_RSHIFT 0x0400
> +#define KD_LCOMM 0x0800
> +#define KD_RCOMM 0x1000
> +#define KD_LALT 0x2000
> +#define KD_RALT 0x4000
> +#define KD_VALID 0x8000 /* only set for scancode keys ? */
> +#define KD_MODS 0x4f00
> +
> +#define KBD_QUEUE_SIZE 256
> +
> +typedef struct {
> +uint8_t data[KBD_QUEUE_SIZE];
> +int rptr, wptr, count;
> +} KBDQueue;
> +
> +
> +typedef struct NextKBDState {
> +SysBusDevice sbd;
> +MemoryRegion mr;
> +KBDQueue queue;
> +uint16_t shift;
> +} NextKBDState;
> +
> +static void queue_code(void *opaque, int code);
> +
> +/* lots of magic numbers here */
> +static uint32_t kbd_read_byte(void *opaque, hwaddr addr)
> +{
> +switch (addr & 0x3) {
> +case 0x0: /* 0xe000 */
> +return 0x80 | 0x20;
> +
> +case 0x1: /* 0xe001 */
> +return 0x80 | 0x40 | 0x20 | 0x10;
> +
> +case 0x2: /* 0xe002 */
> +/* returning 0x40 caused mach to hang */
> +return 0x10 | 0x2 | 0x1;
> +
> +default:
> +qemu_log_mask(LOG_UNIMP, "NeXT kbd read byte %"HWADDR_PRIx"\n",
> addr);
> +}
> +
> +return 0;
> +}
> +
> +static uint32_t kbd_read_word(void *opaque, hwaddr addr)
> +{
> +qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr);
This sounds odd... a bus working in 32-bit/8-bit but not 16...
> +return 0;
> +}
> +
> +/* even more magic numbers */
> +static uint32_t kbd_read_long(void *opaque, hwaddr addr)
> +{
> +int key = 0;
> +NextKBDState *s = NEXTKBD(opaque);
> +KBDQueue *q = &s->queue;
> +
> +switch (addr & 0xf) {
> +case 0x0: /* 0xe000 */
> +return 0xA0F09300;
> +
> +case
Re: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation
Hi Thomas,
On 6/28/19 8:15 PM, Thomas Huth wrote:
> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
> a fixed resolution of 1120 * 832.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
Please use SHA1 for reference (unlikely case of Bryce pushing a new
version to his repo):
https://github.com/blanham/qemu-NeXT/blob/34f4323/hw/next-fb.c
>
> and altered to fit the latest interface of the current QEMU (e.g.
> the device has been "qdev"-ified etc.).
>
> Signed-off-by: Thomas Huth
> ---
> default-configs/m68k-softmmu.mak | 1 +
> hw/display/Makefile.objs | 1 +
> hw/display/next-fb.c | 157 +++
> hw/m68k/Kconfig | 4 +
> include/hw/m68k/next-cube.h | 8 ++
> 5 files changed, 171 insertions(+)
> create mode 100644 hw/display/next-fb.c
> create mode 100644 include/hw/m68k/next-cube.h
>
> diff --git a/default-configs/m68k-softmmu.mak
> b/default-configs/m68k-softmmu.mak
> index 4049a8f2ba..d67ab8b96d 100644
> --- a/default-configs/m68k-softmmu.mak
> +++ b/default-configs/m68k-softmmu.mak
> @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=y
> #
> CONFIG_AN5206=y
> CONFIG_MCF5208=y
> +CONFIG_NEXTCUBE=y
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index a64998fc7b..8d1c71026d 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -38,6 +38,7 @@ obj-$(CONFIG_RASPI) += bcm2835_fb.o
> obj-$(CONFIG_SM501) += sm501.o
> obj-$(CONFIG_TCX) += tcx.o
> obj-$(CONFIG_CG3) += cg3.o
> +obj-$(CONFIG_NEXTCUBE) += next-fb.o
>
> obj-$(CONFIG_VGA) += vga.o
>
> diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c
> new file mode 100644
> index 00..740102d7e9
> --- /dev/null
> +++ b/hw/display/next-fb.c
> @@ -0,0 +1,157 @@
> +/*
> + * NeXT Cube/Station Framebuffer Emulation
> + *
> + * Copyright (c) 2011 Bryce Lanham
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "ui/console.h"
> +#include "hw/hw.h"
> +#include "hw/boards.h"
> +#include "hw/loader.h"
> +#include "hw/display/framebuffer.h"
> +#define BITS 8
'BITS' is not used, remove?
> +#include "ui/pixel_ops.h"
> +#include "hw/m68k/next-cube.h"
> +
> +#define TYPE_NEXTFB "next-fb"
> +#define NEXTFB(obj) OBJECT_CHECK(NeXTFbState, (obj), TYPE_NEXTFB)
> +
> +struct NeXTFbState {
> +SysBusDevice parent_obj;
> +
> +MemoryRegion fb_mr;
> +MemoryRegionSection fbsection;
> +QemuConsole *con;
> +
> +uint32_t pitch;
> +uint32_t cols;
> +uint32_t rows;
> +int invalidate;
> +};
> +typedef struct NeXTFbState NeXTFbState;
> +
> +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s,
> + int width, int pitch)
> +{
> +NeXTFbState *nfbstate = NEXTFB(opaque);
> +static const uint32_t pal[4] = {
> +0x, 0xFFAA, 0xFF55, 0xFF00
> +};
> +uint32_t *buf = (uint32_t *)d;
> +int i = 0;
> +
> +for (i = 0; i < nfbstate->cols / 4; i++) {
> +int j = i * 4;
> +uint8_t src = s[i];
> +buf[j + 3] = pal[src & 0x3];
0x3 -> 3?
or 0b11 :)
> +src >>= 2;
> +buf[j + 2] = pal[src & 0x3];
> +src >>= 2;
> +buf[j + 1] = pal[src & 0x3];
> +src >>= 2;
> +buf[j + 0] = pal[src & 0x3];
> +}
> +}
> +
> +static void nextfb_update(void *opaque)
> +{
> +NeXTFbState *s = NEXTFB(opaque);
> +int dest_width = 4;
> +int src_width;
> +int first = 0;
> +int last = 0;
> +DisplaySurface *surface = qemu_console_surface(s->con);
> +
> +src_width = s->cols / 4 + 8;
> +dest_width = s->cols * 4;
Since those are currently const, should we move them to NeXTFbState
and initialize them in nextfb_realize()?
> +
> +i
Re: [Qemu-devel] [PATCH v4 5/5] 9p: Use variable length suffixes for inode remapping
On Freitag, 28. Juni 2019 16:56:15 CEST Christian Schoenebeck via Qemu-devel
> > > + */
> > > +#define EXP_GOLOMB_K0
> > > +
> > > +# if !EXP_GOLOMB_K
> > > +
> > > +/** @brief Exponential Golomb algorithm limited to the case k=0.
> > > + *
> >
> > This doesn't really help to have a special implementation for k=0. The
> > resulting function is nearly identical to the general case. It is likely
> > that the compiler can optimize it and generate the same code.
>
> I don't think the compiler's optimizer would really drop all the
> instructions automatically of the generalized variant of that particular
> function. Does it matter in practice? No, I actually just provided that
> optimized variant for the special case k=0 because I think k=0 will be the
> default value for that parameter and because you were already picky about a
> simple
>
> if (pdu->s->dev_id == 0)
>
> to be optimized. In practice users won't feel the runtime difference either
> one of the two optimization scenarios.
I just checked my assmption made here with a simple C test unit:
// Use manually optimized function for case k=0.
VariLenAffix implK0(uint64_t n) {
return expGolombEncodeK0(n);
}
// Rely on compiler to optimize generalized function for k=0
VariLenAffix implGenK(uint64_t n) {
return expGolombEncode(n, 0);
}
And : gcc -S -O3 -ffast-math k.c
Like expected the generated 2 functions are almost identical, except that the
manually optimized variant saves the following 3 instructions:
movl$0, %eax
...
testl %edx, %edx
cmovns %edx, %eax
But like I said, it is a tiny difference of course. Not really relevant in
practice.
Best regards,
Christian Schoenebeck
Re: [Qemu-devel] patch to swap SIGRTMIN + 1 and SIGRTMAX - 1
Hi Marlies, On 6/29/19 1:26 AM, Marlies Ruck wrote: > Hi, > > I just wanted to follow up since I sent this patch a week ago to make sure > it was a received. An ack would be appreciated. You did not Cc'ed the maintainer, so he likely missed it. See: https://wiki.qemu.org/Contribute/SubmitAPatch#CC_the_relevant_maintainer $ ./scripts/get_maintainer.pl -f linux-user/signal.c Riku Voipio (maintainer:Linux user) Laurent Vivier (reviewer:Linux user) BTW you should also look at the next paragraph in this wiki page: https://wiki.qemu.org/Contribute/SubmitAPatch#Do_not_send_as_an_attachment Since you credit Peter Maydell, it would be kind to Cc him too. I Cc'ed Riku/Laurent/Peter for you now. Regards, Phil. > On Fri, Jun 21, 2019 at 3:58 PM Marlies Ruck wrote: > >> Hi, >> >> Attached is a patch to let guest programs use SIGRTMIN + 1 by swapping >> with SIGRTMAX - 1. Since QEMU links against glibc, it reserves the signal >> for itself and returns EINVAL (as noted in the commit message). This means >> various applications that use SIGRTMIN + 1 cannot run on QEMU, including >> G-WAN web server and Open TFTP. >> >> Thanks, >> Marli >>
Re: [Qemu-devel] [PATCH] pc: Move compat_apic_id_mode variable to PCMachineClass
On 6/28/19 10:02 PM, Eduardo Habkost wrote:
> Replace the static variable with a PCMachineClass field. This
> will help us eventually get rid of the pc_compat_*() init
> functions.
>
> Signed-off-by: Eduardo Habkost
> ---
> include/hw/i386/pc.h | 3 +++
> hw/i386/pc.c | 22 +-
> hw/i386/pc_piix.c| 3 ++-
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index c54cc54a47..853502f277 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -134,6 +134,9 @@ typedef struct PCMachineClass {
>
> /* use PVH to load kernels that support this feature */
> bool pvh_enabled;
> +
> +/* Enables contiguous-apic-ID mode */
> +bool compat_apic_id_mode;
> } PCMachineClass;
>
> #define TYPE_PC_MACHINE "generic-pc-machine"
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index e96360b47a..3983621f1c 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -913,14 +913,6 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t
> *address, uint64_t *length)
> return false;
> }
>
> -/* Enables contiguous-apic-ID mode, for compatibility */
> -static bool compat_apic_id_mode;
> -
> -void enable_compat_apic_id_mode(void)
> -{
> -compat_apic_id_mode = true;
> -}
> -
> /* Calculates initial APIC ID for a specific CPU index
> *
> * Currently we need to be able to calculate the APIC ID from the CPU index
> @@ -928,13 +920,15 @@ void enable_compat_apic_id_mode(void)
> * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID
> of
> * all CPUs up to max_cpus.
> */
> -static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
> +static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
> + unsigned int cpu_index)
> {
> +PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
> uint32_t correct_id;
> static bool warned;
>
> correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
> -if (compat_apic_id_mode) {
> +if (pcmc->compat_apic_id_mode) {
> if (cpu_index != correct_id && !warned && !qtest_enabled()) {
> error_report("APIC IDs set in compatibility mode, "
> "CPU topology won't match the configuration");
> @@ -1533,7 +1527,8 @@ static void pc_new_cpu(const char *typename, int64_t
> apic_id, Error **errp)
> void pc_hot_add_cpu(const int64_t id, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> -int64_t apic_id = x86_cpu_apic_id_from_index(id);
> +PCMachineState *pcms = PC_MACHINE(ms);
> +int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
> Error *local_err = NULL;
>
> if (id < 0) {
> @@ -1569,7 +1564,7 @@ void pc_cpus_init(PCMachineState *pcms)
> *
> * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
> */
> -pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
> +pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, max_cpus - 1) + 1;
> possible_cpus = mc->possible_cpu_arch_ids(ms);
> for (i = 0; i < smp_cpus; i++) {
> pc_new_cpu(possible_cpus->cpus[i].type,
> possible_cpus->cpus[i].arch_id,
> @@ -2660,6 +2655,7 @@ static int64_t pc_get_default_cpu_node_id(const
> MachineState *ms, int idx)
>
> static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
> {
> +PCMachineState *pcms = PC_MACHINE(ms);
> int i;
>
> if (ms->possible_cpus) {
> @@ -2679,7 +2675,7 @@ static const CPUArchIdList
> *pc_possible_cpu_arch_ids(MachineState *ms)
>
> ms->possible_cpus->cpus[i].type = ms->cpu_type;
> ms->possible_cpus->cpus[i].vcpus_count = 1;
> -ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
> +ms->possible_cpus->cpus[i].arch_id =
> x86_cpu_apic_id_from_index(pcms, i);
> x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> smp_cores, smp_threads, &topo);
> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index c07c4a5b38..f29de58636 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -358,7 +358,6 @@ static void pc_compat_1_4_fn(MachineState *machine)
> static void pc_compat_1_3(MachineState *machine)
> {
> pc_compat_1_4_fn(machine);
> -enable_compat_apic_id_mode();
> }
>
> /* PC compat function for pc-0.14 to pc-1.2 */
> @@ -708,6 +707,7 @@ DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4",
> pc_compat_1_4_fn,
>
> static void pc_i440fx_1_3_machine_options(MachineClass *m)
> {
> +PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
> static GlobalProperty compat[] = {
> PC_CPU_MODEL_IDS("1.3.0")
> { "usb-tablet", "usb_version", "1" },
> @@ -718,6 +718,7 @@ static void pc_i440fx_1_3_machine_options(MachineClass *m)
>
> pc_i440fx_1_4_machin
Re: [Qemu-devel] [PATCH v4 3/5] 9p: Added virtfs option "remap_inodes"
On Freitag, 28. Juni 2019 16:23:08 CEST Greg Kurz wrote: > > > This feature applies to all backends IIUC. We don't really care for the > > > synth backend since it generates non-colliding inode numbers by design, > > > but the proxy backend has the same issue as local. So... > > > > Yeah, I was not sure about these, because I did not even know what these > > two were for exactly. :) [ lazyness disclaimer end] > > "proxy" is a backend where all I/O accesses are performed by a separate > process running the virtfs-proxy-helper command. It runs with root > privileges, which provides the same level of functionality as "local" > with security_model=passthrough. It also chroot() into the shared > folder for extra security. But it is slower since it all requests > still go through the virtio-9p device in QEMU. This would call > for a vhost-9p implementation, but it's yet another story. > > "synth" is a software pseudo-backend, currently used to test 9pfs > with QTest (see tests/virtio-9p-test.c). Thanks for the clarification! So the proxy backend sounds like an idea that has not been implemented fully to its end. I guess it is not really used in production environments, right? What is the actual motivation for this proxy backend? And now that I look at it, I am a bit surprised that there is this pure Unix pipe socket based proxy variant, but no TCPIP network socket variant. I mean the latter is AFAIK the original idea behind the 9p protocol and IMO might be interesting to physical separate pure storage backends that way. Best regards, Christian Schoenebeck
Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception
On 6/28/19 5:50 PM, Lucien Murray-Pitts wrote:
> op_helper.c
>static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
>...
> if (cs->exception_index == EXCP_ACCESS) {
> ...
> do_stack_frame(env, &sp, 7, oldsr, 0, retaddr /*LMP: BROKEN - needs PC
> NEXT*/);
>
> Actually according to the MC68000 manuals the "return address" (the PC saved
> on
> the stack) can be upto 5 instructions later due to prefetch. So some pc_next
> would best be used here.
The way I read it from the 68040 manual, it's "the pc of the instruction
executing at the time the fault was detected". Well, we did in fact detect the
fault at "retaddr", so that seems to be the right answer. The fact that real
hardware has a different pipeline and detects the fault later seems immaterial,
and largely irrelevant, since the programmer wasn't given any guarantees for
what sort of value appears in that slot.
> I am triggering this from inside my device by doing the following, since that
> memory address
> should dynamically cause a bus error (I hope this is the right way to do it)
>cpuclass->do_unassigned_access( s->cpu, /*addr*/0x0, /*is_write*/1,
> /*is_exec*/0, opaque, /*size*/4);
For a device to raise a bus error, it should return MEMTX_ERROR (or something).
This eventually reaches cpu_transaction_failed, which has all of the data that
you seem to be missing above.
r~
