[Qemu-devel] [PULL v2 12/15] linux-user: Add support for FIOGETOWN and FIOSETOWN ioctls

[Laurent Vivier]

From: Aleksandar Markovic 

FIOGETOWN and FIOSETOWN ioctls have platform-specific definitions,
hence non-standard definition in QEMU too.

Other than that, they both have a single integer argument, and their
functionality is emulated in a straightforward way.

Signed-off-by: Aleksandar Markovic 
Reviewed-by: Laurent Vivier 
Message-Id: <1567601968-26946-4-git-send-email-aleksandar.marko...@rt-rk.com>
Signed-off-by: Laurent Vivier 
---
 linux-user/ioctls.h   | 2 ++
 linux-user/syscall_defs.h | 4 
 2 files changed, 6 insertions(+)

diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index cd9b6f9a8d45..1830de96e12b 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -177,6 +177,8 @@
 #endif
 #endif /* CONFIG_USBFS */
 
+  IOCTL(FIOGETOWN, IOC_R, MK_PTR(TYPE_INT))
+  IOCTL(FIOSETOWN, IOC_W, MK_PTR(TYPE_INT))
   IOCTL(SIOCATMARK, IOC_R, MK_PTR(TYPE_INT))
   IOCTL(SIOCGIFNAME, IOC_RW, MK_PTR(MK_STRUCT(STRUCT_int_ifreq)))
   IOCTL(SIOCGIFFLAGS, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_short_ifreq)))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 19a1d39cbc82..498223b77787 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -758,10 +758,14 @@ struct target_pollfd {
 
 #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) ||
\
defined(TARGET_XTENSA)
+#define TARGET_FIOGETOWN   TARGET_IOR('f', 123, int)
+#define TARGET_FIOSETOWN   TARGET_IOW('f', 124, int)
 #define TARGET_SIOCATMARK  TARGET_IOR('s', 7, int)
 #define TARGET_SIOCSPGRP   TARGET_IOW('s', 8, pid_t)
 #define TARGET_SIOCGPGRP   TARGET_IOR('s', 9, pid_t)
 #else
+#define TARGET_FIOGETOWN   0x8903
+#define TARGET_FIOSETOWN   0x8901
 #define TARGET_SIOCATMARK  0x8905
 #define TARGET_SIOCSPGRP   0x8902
 #define TARGET_SIOCGPGRP   0x8904
-- 
2.21.0

[Qemu-devel] [PULL v2 07/15] linux-user/arm: Adjust MAX_RESERVED_VA for M-profile

[Laurent Vivier]

From: Richard Henderson 

Limit the virtual address space for M-profile cpus to 2GB,
so that we avoid all of the magic addresses in the top half
of the M-profile system map.

Signed-off-by: Richard Henderson 
Reviewed-by: Peter Maydell 
Message-Id: <20190822185929.16891-3-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier 
---
 linux-user/arm/target_cpu.h | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h
index 279ea532d5b7..3f79356a07fc 100644
--- a/linux-user/arm/target_cpu.h
+++ b/linux-user/arm/target_cpu.h
@@ -19,9 +19,27 @@
 #ifndef ARM_TARGET_CPU_H
 #define ARM_TARGET_CPU_H
 
-/* We need to be able to map the commpage.
-   See validate_guest_space in linux-user/elfload.c.  */
-#define MAX_RESERVED_VA(CPU)  0xul
+static inline unsigned long arm_max_reserved_va(CPUState *cs)
+{
+ARMCPU *cpu = ARM_CPU(cs);
+
+if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
+/*
+ * There are magic return addresses above 0xfe00,
+ * and in general a lot of M-profile system stuff in
+ * the high addresses.  Restrict linux-user to the
+ * cached write-back RAM in the system map.
+ */
+return 0x8000ul;
+} else {
+/*
+ * We need to be able to map the commpage.
+ * See validate_guest_space in linux-user/elfload.c.
+ */
+return 0xul;
+}
+}
+#define MAX_RESERVED_VA  arm_max_reserved_va
 
 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 {
-- 
2.21.0

[Qemu-devel] [PULL v2 01/15] linux-user: remove useless variable

[Laurent Vivier]

filename is only used to open the file if AT_EXECFD is not provided.
But exec_path already contains the path of the file to open.
Remove filename as it is only used in main.c whereas exec_path is
also used in syscall.c.

Fixes: d088d664f201 ("linux-user: identify running binary in /proc/self/exe")
Signed-off-by: Laurent Vivier 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Stefano Garzarella 
Message-Id: <20190714134028.315-1-laur...@vivier.eu>
Signed-off-by: Laurent Vivier 
---
 linux-user/main.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 47917bbb20fc..28f0065b6ddf 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -49,7 +49,6 @@
 char *exec_path;
 
 int singlestep;
-static const char *filename;
 static const char *argv0;
 static int gdbstub_port;
 static envlist_t *envlist;
@@ -586,7 +585,6 @@ static int parse_args(int argc, char **argv)
 exit(EXIT_FAILURE);
 }
 
-filename = argv[optind];
 exec_path = argv[optind];
 
 return optind;
@@ -657,9 +655,9 @@ int main(int argc, char **argv, char **envp)
 
 execfd = qemu_getauxval(AT_EXECFD);
 if (execfd == 0) {
-execfd = open(filename, O_RDONLY);
+execfd = open(exec_path, O_RDONLY);
 if (execfd < 0) {
-printf("Error while loading %s: %s\n", filename, strerror(errno));
+printf("Error while loading %s: %s\n", exec_path, strerror(errno));
 _exit(EXIT_FAILURE);
 }
 }
@@ -784,10 +782,10 @@ int main(int argc, char **argv, char **envp)
 cpu->opaque = ts;
 task_settid(ts);
 
-ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
+ret = loader_exec(execfd, exec_path, target_argv, target_environ, regs,
 info, &bprm);
 if (ret != 0) {
-printf("Error while loading %s: %s\n", filename, strerror(-ret));
+printf("Error while loading %s: %s\n", exec_path, strerror(-ret));
 _exit(EXIT_FAILURE);
 }
 
-- 
2.21.0

[Qemu-devel] [PULL v2 06/15] linux-user: Pass CPUState to MAX_RESERVED_VA

[Laurent Vivier]

From: Richard Henderson 

Turn the scalar macro into a functional macro.  Move the creation
of the cpu up a bit within main() so that we can pass it to the
invocation of MAX_RESERVED_VA.  Delay the validation of the -R
parameter until MAX_RESERVED_VA is computed.

So far no changes to any of the MAX_RESERVED_VA macros to actually
use the cpu in any way, but ARM will need it.

Signed-off-by: Richard Henderson 
Reviewed-by: Peter Maydell 
Message-Id: <20190822185929.16891-2-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivier 
---
 linux-user/arm/target_cpu.h |  2 +-
 linux-user/main.c   | 43 +
 2 files changed, 26 insertions(+), 19 deletions(-)

diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h
index 8a3764919ad9..279ea532d5b7 100644
--- a/linux-user/arm/target_cpu.h
+++ b/linux-user/arm/target_cpu.h
@@ -21,7 +21,7 @@
 
 /* We need to be able to map the commpage.
See validate_guest_space in linux-user/elfload.c.  */
-#define MAX_RESERVED_VA  0xul
+#define MAX_RESERVED_VA(CPU)  0xul
 
 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 {
diff --git a/linux-user/main.c b/linux-user/main.c
index c257b063dbc1..24cb24f0bf8f 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -77,12 +77,12 @@ int have_guest_base;
   (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32))
 /* There are a number of places where we assign reserved_va to a variable
of type abi_ulong and expect it to fit.  Avoid the last page.  */
-#   define MAX_RESERVED_VA  (0xul & TARGET_PAGE_MASK)
+#   define MAX_RESERVED_VA(CPU)  (0xul & TARGET_PAGE_MASK)
 #  else
-#   define MAX_RESERVED_VA  (1ul << TARGET_VIRT_ADDR_SPACE_BITS)
+#   define MAX_RESERVED_VA(CPU)  (1ul << TARGET_VIRT_ADDR_SPACE_BITS)
 #  endif
 # else
-#  define MAX_RESERVED_VA  0
+#  define MAX_RESERVED_VA(CPU)  0
 # endif
 #endif
 
@@ -356,8 +356,7 @@ static void handle_arg_reserved_va(const char *arg)
 unsigned long unshifted = reserved_va;
 p++;
 reserved_va <<= shift;
-if (reserved_va >> shift != unshifted
-|| (MAX_RESERVED_VA && reserved_va > MAX_RESERVED_VA)) {
+if (reserved_va >> shift != unshifted) {
 fprintf(stderr, "Reserved virtual address too big\n");
 exit(EXIT_FAILURE);
 }
@@ -605,6 +604,7 @@ int main(int argc, char **argv, char **envp)
 int i;
 int ret;
 int execfd;
+unsigned long max_reserved_va;
 
 error_init(argv[0]);
 module_call_init(MODULE_INIT_TRACE);
@@ -670,24 +670,31 @@ int main(int argc, char **argv, char **envp)
 /* init tcg before creating CPUs and to get qemu_host_page_size */
 tcg_exec_init(0);
 
-/* Reserving *too* much vm space via mmap can run into problems
-   with rlimits, oom due to page table creation, etc.  We will still try 
it,
-   if directed by the command-line option, but not by default.  */
-if (HOST_LONG_BITS == 64 &&
-TARGET_VIRT_ADDR_SPACE_BITS <= 32 &&
-reserved_va == 0) {
-/* reserved_va must be aligned with the host page size
- * as it is used with mmap()
- */
-reserved_va = MAX_RESERVED_VA & qemu_host_page_mask;
-}
-
 cpu = cpu_create(cpu_type);
 env = cpu->env_ptr;
 cpu_reset(cpu);
-
 thread_cpu = cpu;
 
+/*
+ * Reserving too much vm space via mmap can run into problems
+ * with rlimits, oom due to page table creation, etc.  We will
+ * still try it, if directed by the command-line option, but
+ * not by default.
+ */
+max_reserved_va = MAX_RESERVED_VA(cpu);
+if (reserved_va != 0) {
+if (max_reserved_va && reserved_va > max_reserved_va) {
+fprintf(stderr, "Reserved virtual address too big\n");
+exit(EXIT_FAILURE);
+}
+} else if (HOST_LONG_BITS == 64 && TARGET_VIRT_ADDR_SPACE_BITS <= 32) {
+/*
+ * reserved_va must be aligned with the host page size
+ * as it is used with mmap()
+ */
+reserved_va = max_reserved_va & qemu_host_page_mask;
+}
+
 if (getenv("QEMU_STRACE")) {
 do_strace = 1;
 }
-- 
2.21.0

[Qemu-devel] [PULL v2 15/15] linux-user: Add support for FDRESET, FDRAWCMD, FDTWADDLE, and FDEJECT ioctls

[Laurent Vivier]

From: Aleksandar Markovic 

FDRESET, FDRAWCMD, FDTWADDLE, and FDEJECT ioctls are misc commands
for controlling a floppy drive.

Signed-off-by: Aleksandar Markovic 
Reviewed-by: Laurent Vivier 
Message-Id: <1567601968-26946-7-git-send-email-aleksandar.marko...@rt-rk.com>
Signed-off-by: Laurent Vivier 
---
 linux-user/ioctls.h   | 4 
 linux-user/syscall_defs.h | 4 
 2 files changed, 8 insertions(+)

diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index b25346ee..c6b9d6ad6653 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -115,6 +115,10 @@
  IOCTL(FDMSGON, 0, TYPE_NULL)
  IOCTL(FDMSGOFF, 0, TYPE_NULL)
  IOCTL(FDFLUSH, 0, TYPE_NULL)
+ IOCTL(FDRESET, 0, TYPE_NULL)
+ IOCTL(FDRAWCMD, 0, TYPE_NULL)
+ IOCTL(FDTWADDLE, 0, TYPE_NULL)
+ IOCTL(FDEJECT, 0, TYPE_NULL)
 
 #ifdef FIBMAP
  IOCTL(FIBMAP, IOC_W | IOC_R, MK_PTR(TYPE_LONG))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 4e33ef396be4..fa69c6ab8d01 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -893,6 +893,10 @@ struct target_pollfd {
 #define TARGET_FDMSGONTARGET_IO(2, 0x45)
 #define TARGET_FDMSGOFF   TARGET_IO(2, 0x46)
 #define TARGET_FDFLUSHTARGET_IO(2, 0x4b)
+#define TARGET_FDRESETTARGET_IO(2, 0x54)
+#define TARGET_FDRAWCMD   TARGET_IO(2, 0x58)
+#define TARGET_FDTWADDLE  TARGET_IO(2, 0x59)
+#define TARGET_FDEJECTTARGET_IO(2, 0x5a)
 
 #define TARGET_FIBMAP TARGET_IO(0x00,1)  /* bmap access */
 #define TARGET_FIGETBSZ   TARGET_IO(0x00,2)  /* get the block size used for 
bmap */
-- 
2.21.0

[Qemu-devel] [PULL v2 08/15] linux-user: Support gdb 'qOffsets' query for ELF

[Laurent Vivier]

From: Josh Kunz 

This is needed to support debugging PIE ELF binaries running under QEMU
user mode. Currently, `code_offset` and `data_offset` remain unset for
all ELF binaries, so GDB is unable to correctly locate the position of
the binary's text and data.

The fields `code_offset`, and `data_offset` were originally added way
back in 2006 to support debugging of bFMT executables (978efd6aac6),
and support was just never added for ELF. Since non-PIE binaries are
loaded at exactly the address specified in the binary, GDB does not need
to relocate any symbols, so the buggy behavior is not normally observed.

http://sourceware.org/gdb/onlinedocs/gdb/General-Query-Packets.html#index-qOffsets-packet

Buglink: https://bugs.launchpad.net/qemu/+bug/1528239
Signed-off-by: Josh Kunz 
Reviewed-by: Laurent Vivier 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20190816233422.16715-1-...@google.com>
[lv: added link to documentation]
Signed-off-by: Laurent Vivier 
---
 linux-user/elfload.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 43c16a846d33..f6693e576098 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2403,6 +2403,8 @@ static void load_elf_image(const char *image_name, int 
image_fd,
 }
 
 info->load_bias = load_bias;
+info->code_offset = load_bias;
+info->data_offset = load_bias;
 info->load_addr = load_addr;
 info->entry = ehdr->e_entry + load_bias;
 info->start_code = -1;
-- 
2.21.0

[Qemu-devel] [PULL v2 10/15] linux-user: drop redundant handling of environment variables

[Laurent Vivier]

From: Max Filippov 

QEMU_STRACE and QEMU_RAND_SEED are handled by the parse_args, no need to
do it again in main.

Signed-off-by: Max Filippov 
Reviewed-by: Laurent Vivier 
Message-Id: <20190906165736.5612-1-jcmvb...@gmail.com>
Signed-off-by: Laurent Vivier 
---
 linux-user/main.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 27d9a87bc83d..560d053f7249 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -706,13 +706,6 @@ int main(int argc, char **argv, char **envp)
 reserved_va = max_reserved_va & qemu_host_page_mask;
 }
 
-if (getenv("QEMU_STRACE")) {
-do_strace = 1;
-}
-
-if (seed_optarg == NULL) {
-seed_optarg = getenv("QEMU_RAND_SEED");
-}
 {
 Error *err = NULL;
 if (seed_optarg != NULL) {
-- 
2.21.0

Re: [Qemu-devel] [PATCH v6 22/42] block: Fix bdrv_get_allocated_file_size's fallback

[Kevin Wolf]

Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
> On 10.09.19 16:52, Kevin Wolf wrote:
> > Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
> >> If the driver does not implement bdrv_get_allocated_file_size(), we
> >> should fall back to cumulating the allocated size of all non-COW
> >> children instead of just bs->file.
> >>
> >> Suggested-by: Vladimir Sementsov-Ogievskiy 
> >> Signed-off-by: Max Reitz 
> > 
> > This smells like an overgeneralisation, but if we want to count all vmdk
> > extents, the qcow2 external data file, etc. it's an improvement anyway.
> > A driver that has a child that should not be counted must just remember
> > to implement the callback.
> > 
> > Let me think of an example... How about quorum, for a change? :-)
> > Or the second blkverify child.
> > 
> > Or eventually the block job filter nodes.
> 
> I actually think it makes sense for all of these nodes to report the sum
> of all of their children’s allocated sizes.

Hm... Yes, in a way. But not much more than it would make sense to
report the sum of the sizes of all images in the whole backing chain
(this is a useful thing to ask for, just maybe not the right thing to
return for a low-level interface). But I can accept that it's maybe a
bit more expected for quorum and blkverify than for COW images.

If you include the block job filter nodes, I have to disagree, though.
If mirror_top_bs (or any other job filter) sits in the middle of the
source chain, then I certainly don't want to see the target size added
to it.

> If a quorum node has three children with allocated sizes of 3 MB, 1 MB,
> and 2 MB, respectively (totally possible if some have explicit zeroes
> and others don’t; it may also depend on the protocol, the filesystem,
> etc.), then I think it makes most sense to report indeed 6 MB for the
> quorum subtree as a whole.  What would you report?  3 MB?

Do it's the quorum way: Just vote!

No, you're right, of course. -ENOTSUP is probably the only other thing
you could do then.

> > Ehm... Maybe I should just take back what I said first. It almost feels
> > like it would be better if qcow2 and vmdk explicitly used a handler that
> > counts all children (could still be a generic one in block.c) rather
> > than having to remember to disable the functionality everywhere where we
> > don't want to have it.
> 
> I don’t, because everywhere we don’t want this functionality, we still
> need to choose a child.  This has to be done by the driver anyway.

Well, by default the primary child, which should cover like 90% of the
drivers?

Kevin


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Re: [Qemu-devel] [RFC] docs: vhost-user: add in-band kick/call messages

[Stefan Hajnoczi]

On Tue, Sep 10, 2019 at 05:34:57PM +0200, Johannes Berg wrote:
> On Tue, 2019-09-10 at 11:33 -0400, Michael S. Tsirkin wrote:
> > On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> > > Is any of you familiar with the process of getting a virtio device ID
> > > assigned, and if so, do you think it'd be feasible? Without that, it'd
> > > probably be difficult to upstream the patch to support this protocol to
> > > user-mode Linux.
> > 
> > Sure, subscribe then send a patch to virtio-comm...@lists.oasis-open.org
> 
> Ok, great.
> 
> > We do expect people to eventually get around to documenting the device
> > and upstreaming it though. If there's no plan to do it at all, you might
> > still be able to reuse the virtio code, in that case let's talk.
> 
> Right, no, I do want to and am working on the code now, but it's a bit
> of a chicken & egg - without an ID I can't really send any code upstream
> :-)
> 
> I can accompany the request for a new ID with working patches.
> 
> What kind of documentation beyond the header file should be added, and
> where?

You can reserve the device ID without any header files or documentation.
Just a patch like this one will suffice:

  
https://github.com/oasis-tcs/virtio-spec/commit/9454b568c29baab7f3e4b1a384627d0061f71eba

I have checked that device ID 29 appears to be free so you could use it.

For the actual VIRTIO device specification, please follow the same
format as the other devices.  Here is the virtio-net section in the
VIRTIO spec:

  
https://docs.oasis-open.org/virtio/virtio/v1.1/cs01/virtio-v1.1-cs01.html#x1-1940001

It documents the virtqueues, configuration space layout, theory of
operation, and also includes normative statements that compliant drivers
and devices are expected to follow.

The goal of the spec is to provide all the information needed by driver
and device emulation authors to create an implementation from scratch
(without studying existing code in Linux, QEMU, etc).

The VIRTIO spec contains pseudo-C struct and constant definitions, but
not a real header file.  The header file for a Linux driver would live
in include/uapi/linux/virtio_foo.h (see existing devices for examples).
This would be part of your Linux patches and separate from the virtio
spec.

Stefan


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[Qemu-devel] [PULL v2 14/15] linux-user: Add support for FDMSGON and FDMSGOFF ioctls

[Laurent Vivier]

From: Aleksandar Markovic 

FDMSGON and FDMSGOFF switch informational messages of floppy drives
on and off.

Signed-off-by: Aleksandar Markovic 
Reviewed-by: Laurent Vivier 
Reviewed-by: Laurent Vivier 
Message-Id: <1567601968-26946-6-git-send-email-aleksandar.marko...@rt-rk.com>
Signed-off-by: Laurent Vivier 
---
 linux-user/ioctls.h   | 2 ++
 linux-user/syscall_defs.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index bc1944804220..b25346ee 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -112,6 +112,8 @@
  IOCTL(BLKZEROOUT, IOC_W, MK_PTR(MK_ARRAY(TYPE_ULONGLONG, 2)))
 #endif
 
+ IOCTL(FDMSGON, 0, TYPE_NULL)
+ IOCTL(FDMSGOFF, 0, TYPE_NULL)
  IOCTL(FDFLUSH, 0, TYPE_NULL)
 
 #ifdef FIBMAP
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 917202a2035d..4e33ef396be4 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -890,6 +890,8 @@ struct target_pollfd {
 
 /* From  */
 
+#define TARGET_FDMSGONTARGET_IO(2, 0x45)
+#define TARGET_FDMSGOFF   TARGET_IO(2, 0x46)
 #define TARGET_FDFLUSHTARGET_IO(2, 0x4b)
 
 #define TARGET_FIBMAP TARGET_IO(0x00,1)  /* bmap access */
-- 
2.21.0

Re: [Qemu-devel] [Qemu-block] [PATCH v2 3/7] curl: Check completion in curl_multi_do()

[Max Reitz]

On 10.09.19 18:11, Maxim Levitsky wrote:
> On Tue, 2019-09-10 at 14:41 +0200, Max Reitz wrote:
>> While it is more likely that transfers complete after some file
>> descriptor has data ready to read, we probably should not rely on it.
>> Better be safe than sorry and call curl_multi_check_completion() in
>> curl_multi_do(), too, just like it is done in curl_multi_read().
>>
>> With this change, curl_multi_do() and curl_multi_read() are actually the
>> same, so drop curl_multi_read() and use curl_multi_do() as the sole FD
>> handler.
> 
> I understand the reasoning, but I still a bit worry that this
> could paper over some bug/race in the future.
> If curl asks us only to deal with write, that would mean
> that it doesn't expect any data to be received.

I can imagine that maybe it wants to send some data first (to close the
connection) before it really marks the request as done.

> Do you by a chance have an example, of this patch
> affecting the code? Maybe when a unexpected error reply
> is received from the server?

No, I don’t.  As John said, this is just to ensure that we always call
curl_multi_check_completion() after the read_cb might have been invoked
(and once the request is marked as “done”).

> I don't really know the CURL library, so I probably missed
> something important.

I’d wager a guess that nobody really does because otherwise block/curl.c
wouldn’t be in the “Odd Fixes” category (with no dedicated maintainer).

Max

> Other than that,
> Reviewed-by: Maxim Levitsky 
> 
> 
> Best regards,
>   Maxim Levitsky
> 
> 
>>
>> Signed-off-by: Max Reitz 
>> ---
>>  block/curl.c | 14 ++
>>  1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/block/curl.c b/block/curl.c
>> index 95d7b77dc0..5838afef99 100644
>> --- a/block/curl.c
>> +++ b/block/curl.c
>> @@ -139,7 +139,6 @@ typedef struct BDRVCURLState {
>>  
>>  static void curl_clean_state(CURLState *s);
>>  static void curl_multi_do(void *arg);
>> -static void curl_multi_read(void *arg);
>>  
>>  #ifdef NEED_CURL_TIMER_CALLBACK
>>  /* Called from curl_multi_do_locked, with s->mutex held.  */
>> @@ -186,7 +185,7 @@ static int curl_sock_cb(CURL *curl, curl_socket_t fd, 
>> int action,
>>  switch (action) {
>>  case CURL_POLL_IN:
>>  aio_set_fd_handler(s->aio_context, fd, false,
>> -   curl_multi_read, NULL, NULL, state);
>> +   curl_multi_do, NULL, NULL, state);
>>  break;
>>  case CURL_POLL_OUT:
>>  aio_set_fd_handler(s->aio_context, fd, false,
>> @@ -194,7 +193,7 @@ static int curl_sock_cb(CURL *curl, curl_socket_t fd, 
>> int action,
>>  break;
>>  case CURL_POLL_INOUT:
>>  aio_set_fd_handler(s->aio_context, fd, false,
>> -   curl_multi_read, curl_multi_do, NULL, state);
>> +   curl_multi_do, curl_multi_do, NULL, state);
>>  break;
>>  case CURL_POLL_REMOVE:
>>  aio_set_fd_handler(s->aio_context, fd, false,
>> @@ -416,15 +415,6 @@ static void curl_multi_do(void *arg)
>>  {
>>  CURLState *s = (CURLState *)arg;
>>  
>> -qemu_mutex_lock(&s->s->mutex);
>> -curl_multi_do_locked(s);
>> -qemu_mutex_unlock(&s->s->mutex);
>> -}
>> -
>> -static void curl_multi_read(void *arg)
>> -{
>> -CURLState *s = (CURLState *)arg;
>> -
>>  qemu_mutex_lock(&s->s->mutex);
>>  curl_multi_do_locked(s);
>>  curl_multi_check_completion(s->s);
> 
> 




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Re: [Qemu-devel] qemu_futex_wait() lockups in ARM64: 2 possible issues

[Rafael David Tinoco]

Quick update...

> value INT_MAX (4294967295) seems WRONG for qemu_futex_wait():
> 
> - EV_BUSY, being -1, and passed as an argument qemu_futex_wait(void *,
> unsigned), is a two's complement, making argument into a INT_MAX when
> that's not what is expected (unless I missed something).
> 
> *** If that is the case, unsure if you, Paolo, prefer declaring
> *(QemuEvent)->value as an integer or changing EV_BUSY to "2" would okay
> here ***
> 
> BUG: description:
> https://bugs.launchpad.net/qemu/+bug/1805256/comments/15

I realized this might be intentional, but, still, I tried:

https://pastebin.ubuntu.com/p/6rkkY6fJdm/

looking for anything that could have misbehaved in arm64 (specially
concerned on casting and type conversions between the functions).

> QUESTION:
> 
> - Should qemu_event_set() check return code from
> qemu_futex_wake()->qemu_futex()->syscall() in order to know if ANY
> waiter was ever woken up ? Maybe even loop until at least 1 is awaken ?

And I also tried:

-qemu_futex(f, FUTEX_WAKE, n, NULL, NULL, 0);
+while(qemu_futex(pval, FUTEX_WAKE, val, NULL, NULL, 0) == 0)
+continue;

and it made little difference (took way more time for me to reproduce
the issue though):

"""
(gdb) run
Starting program: /usr/bin/qemu-img convert -f qcow2 -O qcow2
./disk01.ext4.qcow2 ./output.qcow2

[New Thread 0xbec5ad90 (LWP 72839)]
[New Thread 0xbe459d90 (LWP 72840)]
[New Thread 0xbdb57d90 (LWP 72841)]
[New Thread 0xacac9d90 (LWP 72859)]
[New Thread 0xa7ffed90 (LWP 72860)]
[New Thread 0xa77fdd90 (LWP 72861)]
[New Thread 0xa6ffcd90 (LWP 72862)]
[New Thread 0xa67fbd90 (LWP 72863)]
[New Thread 0xa5ffad90 (LWP 72864)]

[Thread 0xa5ffad90 (LWP 72864) exited]
[Thread 0xa6ffcd90 (LWP 72862) exited]
[Thread 0xa77fdd90 (LWP 72861) exited]
[Thread 0xbdb57d90 (LWP 72841) exited]
[Thread 0xa67fbd90 (LWP 72863) exited]
[Thread 0xacac9d90 (LWP 72859) exited]
[Thread 0xa7ffed90 (LWP 72860) exited]


"""

All the tasks left are blocked in a system call, so no task left to call
qemu_futex_wake() to unblock thread #2 (in futex()), which would unblock
thread #1 (doing poll() in a pipe with thread #2).

Those 7 threads exit before disk conversion is complete (sometimes in
the beginning, sometimes at the end).

I'll try to check why those tasks exited.

Any thoughts ?

Tks

Re: [Qemu-devel] [Qemu-block] [PATCH 0/7] Move qtests to a separate folder

[Kevin Wolf]

Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
> On 9/10/19 1:58 PM, Thomas Huth wrote:
> > Our "tests" directory is very overcrowded - we store the qtests,
> > unit test and other files there. That makes it difficult to
> > determine which file belongs to each test subsystem, and the
> > wildcards in the MAINTAINERS file are inaccurate, too.
> > 
> > Let's clean up this mess. The first patches disentangle some
> > dependencies, and the last three patches then move the qtests
> > and libqos (which is a subsystem of the qtests) to a new folder
> > called "tests/qtest/".
> 
> I'd also welcome a rename of tests/qemu-iotests to tests/iotests.

I might prefer if the directory were named "iotests" rather than
"qemu-iotests" if we were only adding the code now.

However, I'm not so sure if I'd like a rename now because a rename
always comes with a cost and the benefits are rather limited in this
case.

Kevin


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Re: [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension

[Aleksandar Markovic]

11.09.2019. 08.35, "liuzhiwei"  је написао/ла:
>
> Features:
>   * support specification riscv-v-spec-0.7.1(
https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf
).

Hi, Zhivei.

The linked document is a presentation, outlining general concepts of the
instruction set in question, which is certainly useful and nice to have,
but, for review process, we need *specifications* (especially given that
they are in draft phase, and therefore "moving target"). Please provide
such link.

I also noticed lack of commit messages, and was really disappointed by
that. It looks to me you did not honor in entirety our guidlines for
submitting patches.

Yours,
Aleksandar

>   * support basic vector extension.

>   * support Zvlsseg.

>   * support Zvamo.

>   * not support Zvediv as it is changing.
>   * fixed VLEN 128bit.
>   * fixed SLEN 128bit.
>   * ELEN support 8bit, 16bit, 32bit, 64bit.
>
> Todo:
>   * support VLEN configure from qemu command line.
>   * move check code from execution-time to translation-time
>
> Changelog:
> V2
>   * use float16_compare{_quiet}
>   * only use GETPC() in outer most helper
>   * add ctx.ext_v Property
>
>
> LIU Zhiwei (17):
>   RISC-V: add vfp field in CPURISCVState
>   RISC-V: turn on vector extension from command line by cfg.ext_v
> Property
>   RISC-V: support vector extension csr
>   RISC-V: add vector extension configure instruction
>   RISC-V: add vector extension load and store instructions
>   RISC-V: add vector extension fault-only-first implementation
>   RISC-V: add vector extension atomic instructions
>   RISC-V: add vector extension integer instructions part1,
> add/sub/adc/sbc
>   RISC-V: add vector extension integer instructions part2, bit/shift
>   RISC-V: add vector extension integer instructions part3, cmp/min/max
>   RISC-V: add vector extension integer instructions part4, mul/div/merge
>   RISC-V: add vector extension fixed point instructions
>   RISC-V: add vector extension float instruction part1, add/sub/mul/div
>   RISC-V: add vector extension float instructions part2,
> sqrt/cmp/cvt/others
>   RISC-V: add vector extension reduction instructions
>   RISC-V: add vector extension mask instructions
>   RISC-V: add vector extension premutation instructions
>
>  linux-user/riscv/cpu_loop.c | 7 +
>  target/riscv/Makefile.objs  | 2 +-
>  target/riscv/cpu.c  | 6 +-
>  target/riscv/cpu.h  |30 +
>  target/riscv/cpu_bits.h |15 +
>  target/riscv/cpu_helper.c   | 7 +
>  target/riscv/csr.c  |65 +-
>  target/riscv/helper.h   |   358 +
>  target/riscv/insn32.decode  |   373 +
>  target/riscv/insn_trans/trans_rvv.inc.c |   490 +
>  target/riscv/translate.c| 1 +
>  target/riscv/vector_helper.c| 25701
++
>  12 files changed, 27049 insertions(+), 6 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
>  create mode 100644 target/riscv/vector_helper.c
>
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v2 04/24] dsoundaudio: port to the new audio backend api

[Gerd Hoffmann]

> +static void *dsound_get_buffer_in(HWVoiceIn *hw, size_t *size)
>  {

> +int err;
> +void *ret;
> +n
> +hr = IDirectSoundCaptureBuffer_GetCurrentPosition(dscb, &cpos, NULL);

Huh?  Stray 'n' here.  That can hardly survived a build test ...

Removed it.  Builds now.  Continuing testing.

cheers,
  Gerd

Re: [Qemu-devel] [PATCH 1/7] spapr: Simplify handling of pre ISA 3.0 guest workaround handling

[Cédric Le Goater]

On 11/09/2019 06:04, David Gibson wrote:
> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time.  We workaround this in qemu by explicitly excluding the radix
> (and other ISA 3.0 linked) options if the guest doesn't explicitly note
> support for ISA 3.0.
> 
> This is handled by the 'cas_legacy_guest_workaround' flag, which is pretty
> vague.  Rename it to 'cas_pre_isa3_guest' to be clearer about what it's for.
> 
> In addition, we unnecessarily call spapr_populate_pa_features() with
> different options when initially constructing the device tree and when
> adjusting it at CAS time.  At the initial construct time cas_pre_isa3_guest
> is already false, so we can still use the flag, rather than explicitly
> overriding it to be false at the callsite.
> 
> Signed-off-by: David Gibson 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  hw/ppc/spapr.c | 10 --
>  hw/ppc/spapr_hcall.c   |  3 +--
>  include/hw/ppc/spapr.h |  2 +-
>  3 files changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 7124053b43..c551001f86 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -218,8 +218,7 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, 
> PowerPCCPU *cpu)
>  /* Populate the "ibm,pa-features" property */
>  static void spapr_populate_pa_features(SpaprMachineState *spapr,
> PowerPCCPU *cpu,
> -   void *fdt, int offset,
> -   bool legacy_guest)
> +   void *fdt, int offset)
>  {
>  uint8_t pa_features_206[] = { 6, 0,
>  0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> @@ -285,7 +284,7 @@ static void spapr_populate_pa_features(SpaprMachineState 
> *spapr,
>  if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
>  pa_features[24] |= 0x80;/* Transactional memory support */
>  }
> -if (legacy_guest && pa_size > 40) {
> +if (spapr->cas_pre_isa3_guest && pa_size > 40) {
>  /* Workaround for broken kernels that attempt (guest) radix
>   * mode when they can't handle it, if they see the radix bit set
>   * in pa-features. So hide it from them. */
> @@ -348,8 +347,7 @@ static int spapr_fixup_cpu_dt(void *fdt, 
> SpaprMachineState *spapr)
>  return ret;
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset,
> -   spapr->cas_legacy_guest_workaround);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  }
>  return ret;
>  }
> @@ -551,7 +549,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void 
> *fdt, int offset,
>page_sizes_prop, page_sizes_prop_size)));
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  
>  _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
> cs->cpu_index / vcpus_per_socket)));
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 23e4bdb829..3d3a67149a 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -1765,8 +1765,7 @@ static target_ulong 
> h_client_architecture_support(PowerPCCPU *cpu,
>  exit(EXIT_FAILURE);
>  }
>  }
> -spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
> -  OV1_PPC_3_00);
> +spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
>  spapr_ovec_cleanup(ov1_guest);
>  if (!spapr->cas_reboot) {
>  /* If spapr_machine_reset() did not set up a HPT but one is necessary
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 03111fd55b..dfec8e8e76 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -175,7 +175,7 @@ struct SpaprMachineState {
>  
>  /* ibm,client-architecture-support option negotiation */
>  bool cas_reboot;
> -bool cas_legacy_guest_workaround;
> +bool cas_pre_isa3_guest;
>  SpaprOptionVector *ov5; /* QEMU-supported option vectors */
>  SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
>  uint32_t max_compat_pvr;
> 

Re: [Qemu-devel] [PATCH] BootLinuxConsoleTest: Test the Quadra 800

[Laurent Vivier]

Le 10/09/2019 à 22:02, Philippe Mathieu-Daudé a écrit :
> On 9/10/19 7:07 PM, Cleber Rosa wrote:
>> On Tue, Sep 10, 2019 at 06:34:30PM +0200, Philippe Mathieu-Daudé wrote:
>>> This test boots a Linux kernel on a Quadra 800 board
>>> and verify the serial is working.
>>>
>>> Example:
>>>
>>>   $ avocado --show=app,console run -t machine:q800 
>>> tests/acceptance/boot_linux_console.py
>>>   console: ABCFGHIJK
>>>   console: Linux version 5.2.0-2-m68k (debian-ker...@lists.debian.org) (gcc 
>>> version 8.3.0 (Debian 8.3.0-21)) #1 Debian 5.2.9-2 (2019-08-21)
>>>   console: Detected Macintosh model: 35
>>>   console: Apple Macintosh Quadra 800
>>>   console: Built 1 zonelists, mobility grouping on.  Total pages: 32448
>>>   console: Kernel command line: printk.time=0 console=ttyS0 vga=off
>>>   [...]
>>>   console: Calibrating delay loop... 1236.99 BogoMIPS (lpj=6184960)
>>>   [...]
>>>   console: NuBus: Scanning NuBus slots.
>>>   console: Slot 9: Board resource not found!
>>>   console: SCSI subsystem initialized
>>>   console: clocksource: Switched to clocksource via1
>>>   [...]
>>>   console: macfb: framebuffer at 0xf9001000, mapped to 0x(ptrval), size 468k
>>>   console: macfb: mode is 800x600x8, linelength=800
>>>   console: Console: switching to colour frame buffer device 100x37
>>>   console: fb0: DAFB frame buffer device
>>>   console: pmac_zilog: 0.6 (Benjamin Herrenschmidt 
>>> )
>>>   console: scc.0: ttyS0 at MMIO 0x50f0c022 (irq = 4, base_baud = 230400) is 
>>> a Z85c30 ESCC - Serial port
>>>   console: scc.1: ttyS1 at MMIO 0x50f0c020 (irq = 4, base_baud = 230400) is 
>>> a Z85c30 ESCC - Serial port
>>>   console: Non-volatile memory driver v1.3
>>>   console: adb: Mac II ADB Driver v1.0 for Unified ADB
>>>   console: mousedev: PS/2 mouse device common for all mice
>>>   console: random: fast init done
>>>   console: Detected ADB keyboard, type .
>>>   console: input: ADB keyboard as /devices/virtual/input/input0
>>>   console: input: ADB mouse as /devices/virtual/input/input1
>>>   console: rtc-generic rtc-generic: registered as rtc0
>>>   console: ledtrig-cpu: registered to indicate activity on CPUs
>>>   [...]
>>>   console: rtc-generic rtc-generic: setting system clock to 
>>> 2019-09-10T16:20:25 UTC (1568132425)
>>>   console: List of all partitions:
>>>   console: No filesystem could mount root, tried:
>>>   JOB TIME   : 2.91 s
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé 
>>> ---
>>> Based-on: <20190910113323.17324-1-laur...@vivier.eu>
>>> "hw/m68k: add Apple Machintosh Quadra 800 machine"
>>> https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg01775.html
>>> ---
>>>  tests/acceptance/boot_linux_console.py | 24 
>>>  1 file changed, 24 insertions(+)
>>>
>>> diff --git a/tests/acceptance/boot_linux_console.py 
>>> b/tests/acceptance/boot_linux_console.py
>>> index 2504ef0150..8e346bb0f4 100644
>>> --- a/tests/acceptance/boot_linux_console.py
>>> +++ b/tests/acceptance/boot_linux_console.py
>>> @@ -373,3 +373,27 @@ class BootLinuxConsole(Test):
>>>  self.vm.launch()
>>>  console_pattern = 'Kernel command line: %s' % kernel_command_line
>>>  self.wait_for_console_pattern(console_pattern)
>>> +
>>> +def test_m68k_q800(self):
>>> +"""
>>> +:avocado: tags=arch:m68k
>>> +:avocado: tags=machine:q800
>>> +"""
>>> +deb_url = 
>>> ('http://ftp.ports.debian.org/debian-ports/pool-m68k/main'
>>> +   
>>> '/l/linux/kernel-image-5.2.0-2-m68k-di_5.2.9-2_m68k.udeb')
>>> +deb_hash = '0797e05129595f22f3c0142db5e199769a723bf9'
>>> +deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
>>> +kernel_path = self.extract_from_deb(deb_path,
>>> +'/boot/vmlinux-5.2.0-2-m68k')
>>> +
>>> +self.vm.set_machine('q800')
>>> +self.vm.set_console()
>>> +kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
>>> +   'console=ttyS0 vga=off')
>>> +self.vm.add_args('-kernel', kernel_path,
>>> + '-append', kernel_command_line)
>>> +self.vm.launch()
>>> +console_pattern = 'Kernel command line: %s' % kernel_command_line
>>> +self.wait_for_console_pattern(console_pattern)
>>> +console_pattern = 'No filesystem could mount root'
>>> +self.wait_for_console_pattern(console_pattern)
>>> -- 
>>> 2.20.1
>>>
>>
>> LGTM.
>>
>> Of course it needs to wait for the series adding the machine type.
>> If there's a new version of the series, shouldn't this be included
>> there?
> 
> At some point I'd like we enforce the rule "each new machine is added
> with an integration test".
> So far we are still trying to figure out what is the best use of Avocado
> for QEMU, and what are good/cheap tests, how easy it is to add/use them,
> and so on. We are improving :)
> So, with this idea, indeed machine tests should go with the the series
> that intro

Re: [Qemu-devel] [PATCH v11 0/9] hw/m68k: add Apple Machintosh Quadra 800 machine

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190910193347.16000-1-laur...@vivier.eu/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v11 0/9] hw/m68k: add Apple Machintosh Quadra 800 
machine
Message-id: 20190910193347.16000-1-laur...@vivier.eu
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag] patchew/20190911064920.1718-1-laur...@vivier.eu -> 
patchew/20190911064920.1718-1-laur...@vivier.eu
Switched to a new branch 'test'
25caa2c hw/m68k: define Macintosh Quadra 800
cd09534 hw/m68k: add a dummy SWIM floppy controller
c2d114a hw/m68k: add Nubus support for macfb video card
322bc5d hw/m68k: add Nubus support
e89cb4f hw/m68k: add macfb video card
07131bc hw/m68k: implement ADB bus support for via
509b447 hw/m68k: add via support
522388d dp8393x: manage big endian bus
d967bd4 esp: add pseudo-DMA as used by Macintosh

=== OUTPUT BEGIN ===
1/9 Checking commit d967bd47bd5b (esp: add pseudo-DMA as used by Macintosh)
2/9 Checking commit 522388d60f5f (dp8393x: manage big endian bus)
3/9 Checking commit 509b447fb695 (hw/m68k: add via support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

ERROR: space prohibited after that '&&' (ctx:WxW)
#426: FILE: hw/misc/mac_via.c:345:
+if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) {
^

total: 1 errors, 1 warnings, 867 lines checked

Patch 3/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/9 Checking commit 07131bcb3f95 (hw/m68k: implement ADB bus support for via)
5/9 Checking commit e89cb4f88dbc (hw/m68k: add macfb video card)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
new file mode 100644

total: 0 errors, 1 warnings, 518 lines checked

Patch 5/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 322bc5db6d96 (hw/m68k: add Nubus support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#62: 
new file mode 100644

total: 0 errors, 1 warnings, 532 lines checked

Patch 6/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/9 Checking commit c2d114a85b93 (hw/m68k: add Nubus support for macfb video 
card)
8/9 Checking commit cd0953416110 (hw/m68k: add a dummy SWIM floppy controller)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 591 lines checked

Patch 8/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/9 Checking commit 25caa2c0716f (hw/m68k: define Macintosh Quadra 800)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#70: 
new file mode 100644

total: 0 errors, 1 warnings, 518 lines checked

Patch 9/9 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190910193347.16000-1-laur...@vivier.eu/testing.checkpatch/?type=message.
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Please send your feedback to patchew-de...@redhat.com

Re: [Qemu-devel] [PATCH 0/3] target/mips: Convert to do_transaction_failed hook

[Aleksandar Markovic]

02.08.2019. 18.29, "Philippe Mathieu-Daudé"  је
написао/ла:
>
> Cc'ing broader MIPS audience.
>
> On 8/2/19 6:04 PM, Peter Maydell wrote:
> > This patchset converts the MIPS target away from the
> > old broken do_unassigned_access hook to the new (added in
> > 2017...) do_transaction_failed hook.
> >

Since Herve now tested this series, unless somebody objects, I am going to
include it in the next Mips queue, scheduled in next few days.

Thanks to all involved!

Aleksandar

> > The motivation here is:
> >  * do_unassigned_access is broken because:
> > + it will be called for any kind of access to physical addresses
> >   where there is no assigned device, whether that access is by the
> >   CPU or by something else (like a DMA controller!), so it can
> >   result in spurious guest CPU exceptions.
> > + It will also get called even when using KVM, when there's nothing
> >   useful it can do.
> > + It isn't passed in the return-address within the TCG generated
> >   code, so it isn't able to correctly restore the CPU state
> >   before generating the exception, and so the exception will
> >   often be generated with the wrong faulting guest PC value
> >  * there are now only a few targets still using the old hook,
> >so if we can convert them we can delete all the old code
> >and complete this API transation. (Patches for SPARC are on
> >the list; the other user is RISCV, which accidentally
> >implemented the old hook rather than the new one recently.)
> >
> > The general approach to the conversion is to check the target for
> > load/store-by-physical-address operations which were previously
> > implicitly causing exceptions, to see if they now need to explicitly
> > check for and handle memory access failures. (The 'git grep' regexes
> > in docs/devel/loads-stores.rst are useful here: the API families to
> > look for are ld*_phys/st*_phys, address_space_ld/st*, and
> > cpu_physical_memory*.)
> >
> > For MIPS, there are none of these (the usual place where targets do
> > this is hardware page table walks where the page table entries are
> > loaded by physical address, and MIPS doesn't seem to have those).
> >
> > Code audit out of the way, the actual hook changeover is pretty
> > simple.
> >
> > The complication here is the MIPS Jazz board, which has some rather
> > dubious code that intercepts the do_unassigned_access hook to suppress
> > generation of exceptions for invalid accesses due to data accesses,
> > while leaving exceptions for invalid instruction fetches in place. I'm
> > a bit dubious about whether the behaviour we have implemented here is
> > really what the hardware does -- it seems pretty odd to me to not
> > generate exceptions for d-side accesses but to generate them for
> > i-side accesses, and looking back through git and mailing list history
> > this code is here mainly as "put back the behaviour we had before a
> > previous commit broke it", and that older behaviour in turn I think is
> > more historical-accident than because anybody deliberately checked the
> > hardware behaviour and made QEMU work that way. However, I don't have
> > any real hardware to do comparative tests on, so this series retains
> > the same behaviour we had before on this board, by making it intercept
> > the new hook in the same way it did the old one. I've beefed up the
> > comment somewhat to indicate what we're doing, why, and why it might
> > not be right.
> >
> > The patch series is structured in three parts:
> >  * make the Jazz board code support CPUs regardless of which
> >of the two hooks they implement
> >  * switch the MIPS CPUs over to implementing the new hook
> >  * remove the no-longer-needed Jazz board code for the old
> >hook
> > (This seemed cleaner to me than squashing the whole thing into
> > a single patch that touched core mips code and the jazz board
> > at the same time.)
> >
> > I have tested this with:
> >  * the ARC Multiboot BIOS linked to from the bug
> >https://bugs.launchpad.net/qemu/+bug/1245924 (and which
> >was the test case for needing the hook intercept)
> >  * a Linux kernel for the 'mips' mips r4k machine
> >  * 'make check'
> > Obviously more extensive testing would be useful, but I
> > don't have any other test images. I also don't have
> > a KVM MIPS host, which would be worth testing to confirm
> > that it also still works.
> >
> > If anybody happens by some chance to still have a working
> > real-hardware Magnum or PICA61 board, we could perhaps test
> > how it handles accesses to invalid memory, but I suspect that
> > nobody does any more :-)
> >
> > thanks
> > -- PMM
> >
> >
> > Peter Maydell (3):
> >   hw/mips/mips_jazz: Override do_transaction_failed hook
> >   target/mips: Switch to do_transaction_failed() hook
> >   hw/mips/mips_jazz: Remove no-longer-necessary override of
> > do_unassigned_access
> >
> >  target/mips/internal.h  |  8 ---
> >  hw/mips/mips_jazz.c | 47 

Re: [Qemu-devel] [PATCH 1/7] spapr: Simplify handling of pre ISA 3.0 guest workaround handling

[Greg Kurz]

On Wed, 11 Sep 2019 14:04:46 +1000
David Gibson  wrote:

> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time.  We workaround this in qemu by explicitly excluding the radix
> (and other ISA 3.0 linked) options if the guest doesn't explicitly note
> support for ISA 3.0.
> 
> This is handled by the 'cas_legacy_guest_workaround' flag, which is pretty
> vague.  Rename it to 'cas_pre_isa3_guest' to be clearer about what it's for.
> 
> In addition, we unnecessarily call spapr_populate_pa_features() with
> different options when initially constructing the device tree and when
> adjusting it at CAS time.  At the initial construct time cas_pre_isa3_guest
> is already false, so we can still use the flag, rather than explicitly
> overriding it to be false at the callsite.
> 
> Signed-off-by: David Gibson 
> ---

Reviewed-by: Greg Kurz 

>  hw/ppc/spapr.c | 10 --
>  hw/ppc/spapr_hcall.c   |  3 +--
>  include/hw/ppc/spapr.h |  2 +-
>  3 files changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 7124053b43..c551001f86 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -218,8 +218,7 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, 
> PowerPCCPU *cpu)
>  /* Populate the "ibm,pa-features" property */
>  static void spapr_populate_pa_features(SpaprMachineState *spapr,
> PowerPCCPU *cpu,
> -   void *fdt, int offset,
> -   bool legacy_guest)
> +   void *fdt, int offset)
>  {
>  uint8_t pa_features_206[] = { 6, 0,
>  0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> @@ -285,7 +284,7 @@ static void spapr_populate_pa_features(SpaprMachineState 
> *spapr,
>  if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
>  pa_features[24] |= 0x80;/* Transactional memory support */
>  }
> -if (legacy_guest && pa_size > 40) {
> +if (spapr->cas_pre_isa3_guest && pa_size > 40) {
>  /* Workaround for broken kernels that attempt (guest) radix
>   * mode when they can't handle it, if they see the radix bit set
>   * in pa-features. So hide it from them. */
> @@ -348,8 +347,7 @@ static int spapr_fixup_cpu_dt(void *fdt, 
> SpaprMachineState *spapr)
>  return ret;
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset,
> -   spapr->cas_legacy_guest_workaround);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  }
>  return ret;
>  }
> @@ -551,7 +549,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void 
> *fdt, int offset,
>page_sizes_prop, page_sizes_prop_size)));
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  
>  _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
> cs->cpu_index / vcpus_per_socket)));
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 23e4bdb829..3d3a67149a 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -1765,8 +1765,7 @@ static target_ulong 
> h_client_architecture_support(PowerPCCPU *cpu,
>  exit(EXIT_FAILURE);
>  }
>  }
> -spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
> -  OV1_PPC_3_00);
> +spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
>  spapr_ovec_cleanup(ov1_guest);
>  if (!spapr->cas_reboot) {
>  /* If spapr_machine_reset() did not set up a HPT but one is necessary
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 03111fd55b..dfec8e8e76 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -175,7 +175,7 @@ struct SpaprMachineState {
>  
>  /* ibm,client-architecture-support option negotiation */
>  bool cas_reboot;
> -bool cas_legacy_guest_workaround;
> +bool cas_pre_isa3_guest;
>  SpaprOptionVector *ov5; /* QEMU-supported option vectors */
>  SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
>  uint32_t max_compat_pvr;

Re: [Qemu-devel] [PATCH 3/7] spapr: Fixes a leak in CAS

[Cédric Le Goater]

On 11/09/2019 06:04, David Gibson wrote:
> From: Alexey Kardashevskiy 
> 
> Add a missing g_free(fdt) if the resulting tree is bigger
> than the space allocated by SLOF.
> 
> Signed-off-by: Alexey Kardashevskiy 
> Signed-off-by: David Gibson 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  hw/ppc/spapr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e03e874d94..d93dacd483 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1024,6 +1024,7 @@ int spapr_h_cas_compose_response(SpaprMachineState 
> *spapr,
>  _FDT((fdt_pack(fdt)));
>  
>  if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
> +g_free(fdt);
>  trace_spapr_cas_failed(size);
>  return -1;
>  }
> 

Re: [Qemu-devel] [PATCH 2/7] spapr: Move handling of special NVLink numa node from reset to init

[Cédric Le Goater]

On 11/09/2019 06:04, David Gibson wrote:
> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
> 
> This simplifies the reset path a bit which will make further improvements
> easier.
> 
> Signed-off-by: David Gibson 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  hw/ppc/spapr.c | 21 +++--
>  1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index c551001f86..e03e874d94 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1737,16 +1737,6 @@ static void spapr_machine_reset(MachineState *machine)
>  spapr_setup_hpt_and_vrma(spapr);
>  }
>  
> -/*
> - * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> - * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> - * called from vPHB reset handler so we initialize the counter here.
> - * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> - * must be equally distant from any other node.
> - * The final value of spapr->gpu_numa_id is going to be written to
> - * max-associativity-domains in spapr_build_fdt().
> - */
> -spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
>  qemu_devices_reset();
>  
>  /*
> @@ -2885,6 +2875,17 @@ static void spapr_machine_init(MachineState *machine)
>  
>  }
>  
> +/*
> + * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> + * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> + * called from vPHB reset handler so we initialize the counter here.
> + * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> + * must be equally distant from any other node.
> + * The final value of spapr->gpu_numa_id is going to be written to
> + * max-associativity-domains in spapr_build_fdt().
> + */
> +spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
> +
>  if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
>  ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
>spapr->max_compat_pvr)) {
> 

Re: [Qemu-devel] [PATCH 2/7] spapr: Move handling of special NVLink numa node from reset to init

[Greg Kurz]

On Wed, 11 Sep 2019 14:04:47 +1000
David Gibson  wrote:

> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
> 
> This simplifies the reset path a bit which will make further improvements
> easier.
> 
> Signed-off-by: David Gibson 
> ---

Reviewed-by: Greg Kurz 

>  hw/ppc/spapr.c | 21 +++--
>  1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index c551001f86..e03e874d94 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1737,16 +1737,6 @@ static void spapr_machine_reset(MachineState *machine)
>  spapr_setup_hpt_and_vrma(spapr);
>  }
>  
> -/*
> - * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> - * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> - * called from vPHB reset handler so we initialize the counter here.
> - * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> - * must be equally distant from any other node.
> - * The final value of spapr->gpu_numa_id is going to be written to
> - * max-associativity-domains in spapr_build_fdt().
> - */
> -spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
>  qemu_devices_reset();
>  
>  /*
> @@ -2885,6 +2875,17 @@ static void spapr_machine_init(MachineState *machine)
>  
>  }
>  
> +/*
> + * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> + * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> + * called from vPHB reset handler so we initialize the counter here.
> + * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> + * must be equally distant from any other node.
> + * The final value of spapr->gpu_numa_id is going to be written to
> + * max-associativity-domains in spapr_build_fdt().
> + */
> +spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
> +
>  if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
>  ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
>spapr->max_compat_pvr)) {

Re: [Qemu-devel] [RFC] docs: vhost-user: add in-band kick/call messages

[Stefan Hajnoczi]

On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> On Tue, 2019-09-10 at 17:03 +0200, Stefan Hajnoczi wrote:
> > 
> > > Now, this means that the CPU (that's part of the simulation) has to
> > > *wait* for the device to add an entry to the simulation calendar in
> > > response to the kick... That means that it really has to look like
> > > 
> > > CPU   device   calendar
> > >  ---[kick]-->
> > >  ---[add entry]-->
> > >  <---[return]-
> > 
> > What are the semantics of returning from the calendar?  Does it mean
> > "it's now your turn to run?", "your entry has been added and you'll be
> > notified later when it's time to run?", or something else?
> 
> The latter - the entry was added, and you'll be notified when it's time
> to run; but we need to have that state on the calendar so the CPU won't
> converse with the calendar before that state is committed.

Is the device only adding a calendar entry and not doing any actual
device emulation at this stage?

If yes, then this suggests the system could be structured more cleanly.
The vhost-user device process should focus on device emulation.  It
should not be aware of the calendar.  The vhost-user protocol also
shouldn't require modifications.

Instead, Linux arch/um code would add the entry to the calendar when the
CPU wants to kick a vhost-user device.  I assume the CPU is suspended
until arch/um code completes adding the entry to the calendar.

When the calendar decides to run the device entry it signals the
vhost-user kick eventfd.  The vhost-user device processes the virtqueue
as if it had been directly signalled by the CPU, totally unaware that
it's running within a simulation system.

The irq path is similar: the device signals the callfd and the calendar
adds an entry to notify UML that the request has completed.

Some pseudo-code:

arch/um/drivers/.../vhost-user.c:

  void um_vu_kick(struct um_vu_vq *vq)
  {
  if (simulation_mode) {
  calendar_add_entry({
  .type = CAL_ENTRY_TYPE_VHOST_USER_KICK,
  .device = vq->dev,
  .vq_idx = vq->idx,
  });
  return;
  }

  /* The normal code path: signal the kickfd */
  uint64_t val = 1;
  write(vq->kickfd, &val, sizeof(val));
  }

I'm suggesting this because it seems like a cleaner approach than
exposing the calendar concept to the vhost-user devices.  I'm not 100%
sure it offers the semantics you need to make everything deterministic
though.

A different topic: vhost-user does not have a 1:1 vq buffer:kick
relationship.  It's possible to add multiple buffers and kick only once.
It is also possible for the device to complete multiple buffers and only
call once.

This could pose a problem for simulation because it allows a degree of
non-determinism.  But as long as the both the CPU and the I/O completion
of the device happen on a strict schedule this isn't a problem.

Stefan


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Re: [Qemu-devel] [PATCH 3/7] spapr: Fixes a leak in CAS

[Greg Kurz]

On Wed, 11 Sep 2019 14:04:48 +1000
David Gibson  wrote:

> From: Alexey Kardashevskiy 
> 
> Add a missing g_free(fdt) if the resulting tree is bigger
> than the space allocated by SLOF.
> 
> Signed-off-by: Alexey Kardashevskiy 
> Signed-off-by: David Gibson 
> ---

Reviewed-by: Greg Kurz 

>  hw/ppc/spapr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e03e874d94..d93dacd483 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1024,6 +1024,7 @@ int spapr_h_cas_compose_response(SpaprMachineState 
> *spapr,
>  _FDT((fdt_pack(fdt)));
>  
>  if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
> +g_free(fdt);
>  trace_spapr_cas_failed(size);
>  return -1;
>  }

Re: [Qemu-devel] [PATCH v6 22/42] block: Fix bdrv_get_allocated_file_size's fallback

[Max Reitz]

On 11.09.19 08:55, Kevin Wolf wrote:
> Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
>> On 10.09.19 16:52, Kevin Wolf wrote:
>>> Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
 If the driver does not implement bdrv_get_allocated_file_size(), we
 should fall back to cumulating the allocated size of all non-COW
 children instead of just bs->file.

 Suggested-by: Vladimir Sementsov-Ogievskiy 
 Signed-off-by: Max Reitz 
>>>
>>> This smells like an overgeneralisation, but if we want to count all vmdk
>>> extents, the qcow2 external data file, etc. it's an improvement anyway.
>>> A driver that has a child that should not be counted must just remember
>>> to implement the callback.
>>>
>>> Let me think of an example... How about quorum, for a change? :-)
>>> Or the second blkverify child.
>>>
>>> Or eventually the block job filter nodes.
>>
>> I actually think it makes sense for all of these nodes to report the sum
>> of all of their children’s allocated sizes.
> 
> Hm... Yes, in a way. But not much more than it would make sense to
> report the sum of the sizes of all images in the whole backing chain
> (this is a useful thing to ask for, just maybe not the right thing to
> return for a low-level interface). But I can accept that it's maybe a
> bit more expected for quorum and blkverify than for COW images.
> 
> If you include the block job filter nodes, I have to disagree, though.
> If mirror_top_bs (or any other job filter) sits in the middle of the
> source chain, then I certainly don't want to see the target size added
> to it.

Hm, I don’t care much either way.  I think it makes complete sense to
add the target size there, but OTOH it’s only temporary while the job
runs, so it may be a bit confusing if it suddenly goes up and then down
again.

But I think this is the special case, so this is what should be handled
in a driver callback.

>> If a quorum node has three children with allocated sizes of 3 MB, 1 MB,
>> and 2 MB, respectively (totally possible if some have explicit zeroes
>> and others don’t; it may also depend on the protocol, the filesystem,
>> etc.), then I think it makes most sense to report indeed 6 MB for the
>> quorum subtree as a whole.  What would you report?  3 MB?
> 
> Do it's the quorum way: Just vote!

Add an option for it?  Average, maximum, median, majority, sum? :-)

> No, you're right, of course. -ENOTSUP is probably the only other thing
> you could do then.
> 
>>> Ehm... Maybe I should just take back what I said first. It almost feels
>>> like it would be better if qcow2 and vmdk explicitly used a handler that
>>> counts all children (could still be a generic one in block.c) rather
>>> than having to remember to disable the functionality everywhere where we
>>> don't want to have it.
>>
>> I don’t, because everywhere we don’t want this functionality, we still
>> need to choose a child.  This has to be done by the driver anyway.
> 
> Well, by default the primary child, which should cover like 90% of the
> drivers?

Hm, yes.

But I still think that the drivers that do not want to count every
single non-COW child are the exception.

Max



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Description: OpenPGP digital signature

Re: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190910163600.19971-1-laur...@vivier.eu/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches
Message-id: 20190910163600.19971-1-laur...@vivier.eu
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
e7ef7ea linux-user: Add support for FDRESET, FDRAWCMD, FDTWADDLE, and FDEJECT 
ioctls
8104348 linux-user: Add support for FDMSGON and FDMSGOFF ioctls
b5ddae8 linux-user: Add support for FDFLUSH ioctl
d6d44ec linux-user: Add support for FIOGETOWN and FIOSETOWN ioctls
1e30bd0 linux-user: Add support for RNDRESEEDCRNG ioctl
1c04aa7 linux-user: drop redundant handling of environment variables
5ed12d4 target/xtensa: linux-user: add call0 ABI support
087a125 linux-user: Support gdb 'qOffsets' query for ELF
684b551 linux-user/arm: Adjust MAX_RESERVED_VA for M-profile
6c1d7ef linux-user: Pass CPUState to MAX_RESERVED_VA
86fc581 linux-user: add memfd_create
3ee2b69 linux-user: fail and report on bad dfilter specs
feda861 linux-user: erroneous fd_trans_unregister call
9708e11 linux-user: Add AT_HWCAP2 for aarch64-linux-user
b6febe2 linux-user: remove useless variable

=== OUTPUT BEGIN ===
1/15 Checking commit b6febe238627 (linux-user: remove useless variable)
2/15 Checking commit 9708e117373c (linux-user: Add AT_HWCAP2 for 
aarch64-linux-user)
3/15 Checking commit feda861cb9a1 (linux-user: erroneous fd_trans_unregister 
call)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Shu-Chun Weng via Qemu-devel 

total: 1 errors, 0 warnings, 7 lines checked

Patch 3/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/15 Checking commit 3ee2b69a6940 (linux-user: fail and report on bad dfilter 
specs)
5/15 Checking commit 86fc5819df23 (linux-user: add memfd_create)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Shu-Chun Weng via Qemu-devel 

total: 1 errors, 0 warnings, 42 lines checked

Patch 5/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/15 Checking commit 6c1d7ef37f6c (linux-user: Pass CPUState to MAX_RESERVED_VA)
7/15 Checking commit 684b55110074 (linux-user/arm: Adjust MAX_RESERVED_VA for 
M-profile)
8/15 Checking commit 087a125d8596 (linux-user: Support gdb 'qOffsets' query for 
ELF)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Josh Kunz via Qemu-devel 

total: 1 errors, 0 warnings, 8 lines checked

Patch 8/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/15 Checking commit 5ed12d480a19 (target/xtensa: linux-user: add call0 ABI 
support)
10/15 Checking commit 1c04aa701dc5 (linux-user: drop redundant handling of 
environment variables)
11/15 Checking commit 1e30bd0b0221 (linux-user: Add support for RNDRESEEDCRNG 
ioctl)
12/15 Checking commit d6d44ec7d76c (linux-user: Add support for FIOGETOWN and 
FIOSETOWN ioctls)
13/15 Checking commit b5ddae8b1ec3 (linux-user: Add support for FDFLUSH ioctl)
14/15 Checking commit 810434810aaf (linux-user: Add support for FDMSGON and 
FDMSGOFF ioctls)
15/15 Checking commit e7ef7ea1bb3c (linux-user: Add support for FDRESET, 
FDRAWCMD, FDTWADDLE, and FDEJECT ioctls)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190910163600.19971-1-laur...@vivier.eu/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [Qemu-devel] [PATCH 1/7] spapr: Simplify handling of pre ISA 3.0 guest workaround handling

[Alexey Kardashevskiy]

On 11/09/2019 14:04, David Gibson wrote:
> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time.  We workaround this in qemu by explicitly excluding the radix
> (and other ISA 3.0 linked) options if the guest doesn't explicitly note
> support for ISA 3.0.
> 
> This is handled by the 'cas_legacy_guest_workaround' flag, which is pretty
> vague.  Rename it to 'cas_pre_isa3_guest' to be clearer about what it's for.
> 
> In addition, we unnecessarily call spapr_populate_pa_features() with
> different options when initially constructing the device tree and when
> adjusting it at CAS time.  At the initial construct time cas_pre_isa3_guest
> is already false, so we can still use the flag, rather than explicitly
> overriding it to be false at the callsite.
> 
> Signed-off-by: David Gibson 



Reviewed-by: Alexey Kardashevskiy 




> ---
>  hw/ppc/spapr.c | 10 --
>  hw/ppc/spapr_hcall.c   |  3 +--
>  include/hw/ppc/spapr.h |  2 +-
>  3 files changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 7124053b43..c551001f86 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -218,8 +218,7 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, 
> PowerPCCPU *cpu)
>  /* Populate the "ibm,pa-features" property */
>  static void spapr_populate_pa_features(SpaprMachineState *spapr,
> PowerPCCPU *cpu,
> -   void *fdt, int offset,
> -   bool legacy_guest)
> +   void *fdt, int offset)
>  {
>  uint8_t pa_features_206[] = { 6, 0,
>  0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> @@ -285,7 +284,7 @@ static void spapr_populate_pa_features(SpaprMachineState 
> *spapr,
>  if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
>  pa_features[24] |= 0x80;/* Transactional memory support */
>  }
> -if (legacy_guest && pa_size > 40) {
> +if (spapr->cas_pre_isa3_guest && pa_size > 40) {
>  /* Workaround for broken kernels that attempt (guest) radix
>   * mode when they can't handle it, if they see the radix bit set
>   * in pa-features. So hide it from them. */
> @@ -348,8 +347,7 @@ static int spapr_fixup_cpu_dt(void *fdt, 
> SpaprMachineState *spapr)
>  return ret;
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset,
> -   spapr->cas_legacy_guest_workaround);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  }
>  return ret;
>  }
> @@ -551,7 +549,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void 
> *fdt, int offset,
>page_sizes_prop, page_sizes_prop_size)));
>  }
>  
> -spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
> +spapr_populate_pa_features(spapr, cpu, fdt, offset);
>  
>  _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
> cs->cpu_index / vcpus_per_socket)));
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 23e4bdb829..3d3a67149a 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -1765,8 +1765,7 @@ static target_ulong 
> h_client_architecture_support(PowerPCCPU *cpu,
>  exit(EXIT_FAILURE);
>  }
>  }
> -spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
> -  OV1_PPC_3_00);
> +spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
>  spapr_ovec_cleanup(ov1_guest);
>  if (!spapr->cas_reboot) {
>  /* If spapr_machine_reset() did not set up a HPT but one is necessary
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 03111fd55b..dfec8e8e76 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -175,7 +175,7 @@ struct SpaprMachineState {
>  
>  /* ibm,client-architecture-support option negotiation */
>  bool cas_reboot;
> -bool cas_legacy_guest_workaround;
> +bool cas_pre_isa3_guest;
>  SpaprOptionVector *ov5; /* QEMU-supported option vectors */
>  SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
>  uint32_t max_compat_pvr;
> 

-- 
Alexey

Re: [Qemu-devel] [PATCH 7/7] spapr: Perform machine reset in a more sensible order

[Alexey Kardashevskiy]

On 11/09/2019 14:04, David Gibson wrote:
> We've made several changes in the past to the machine reset order to fix
> specific problems.  However, we've ended up with an order that doesn't make
> a lot of logical sense.  This is an attempt to rectify this.
> 
> First we reset global CAS options, since that should depend on nothing
> else.  Then we reset the CPUs, which shouldn't depend on external devices.
> Then the irq subsystem, then the bulk of devices (which might rely on
> irqs).  Finally we set up the entry state ready for boot, which could
> potentially rely on a bunch of other things.
> 
> Signed-off-by: David Gibson 


Breaks console on P8 and asserts on rebooting a P9 guest.



> ---
>  hw/ppc/spapr.c | 47 +--
>  1 file changed, 25 insertions(+), 22 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 5a919a6cc1..1560a11738 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1724,6 +1724,28 @@ static void spapr_machine_reset(MachineState *machine)
>  void *fdt;
>  int rc;
>  
> +/*
> + * If this reset wasn't generated by CAS, we should reset our
> + * negotiated options and start from scratch
> + */
> +if (!spapr->cas_reboot) {
> +spapr_ovec_cleanup(spapr->ov5_cas);
> +spapr->ov5_cas = spapr_ovec_new();
> +
> +ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> +}
> +
> +/*
> + * There is no CAS under qtest. Simulate one to please the code that
> + * depends on spapr->ov5_cas. This is especially needed to test device
> + * unplug, so we do that before resetting the DRCs.
> + */
> +if (qtest_enabled()) {
> +spapr_ovec_cleanup(spapr->ov5_cas);
> +spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> +}
> +
> +/* Reset the CPUs */
>  spapr_caps_apply(spapr);
>  
>  first_ppc_cpu = POWERPC_CPU(first_cpu);
> @@ -1741,34 +1763,15 @@ static void spapr_machine_reset(MachineState *machine)
>  spapr_setup_hpt_and_vrma(spapr);
>  }
>  
> -qemu_devices_reset();
> -
> -/*
> - * If this reset wasn't generated by CAS, we should reset our
> - * negotiated options and start from scratch
> - */
> -if (!spapr->cas_reboot) {
> -spapr_ovec_cleanup(spapr->ov5_cas);
> -spapr->ov5_cas = spapr_ovec_new();
> -
> -ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> -}
> -
> +/* Reset IRQ subsystem */
>  /*
>   * This is fixing some of the default configuration of the XIVE
>   * devices. To be called after the reset of the machine devices.
>   */
>  spapr_irq_reset(spapr, &error_fatal);
>  
> -/*
> - * There is no CAS under qtest. Simulate one to please the code that
> - * depends on spapr->ov5_cas. This is especially needed to test device
> - * unplug, so we do that before resetting the DRCs.
> - */
> -if (qtest_enabled()) {
> -spapr_ovec_cleanup(spapr->ov5_cas);
> -spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> -}
> +/* Reset other devices */
> +qemu_devices_reset();
>  
>  /* DRC reset may cause a device to be unplugged. This will cause troubles
>   * if this device is used by another device (eg, a running vhost backend
> 

-- 
Alexey

Re: [Qemu-devel] [PATCH 2/7] spapr: Move handling of special NVLink numa node from reset to init

[Alexey Kardashevskiy]

On 11/09/2019 14:04, David Gibson wrote:
> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
> 
> This simplifies the reset path a bit which will make further improvements
> easier.
> 
> Signed-off-by: David Gibson 


Tested-by: Alexey Kardashevskiy 
Reviewed-by: Alexey Kardashevskiy 


> ---
>  hw/ppc/spapr.c | 21 +++--
>  1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index c551001f86..e03e874d94 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1737,16 +1737,6 @@ static void spapr_machine_reset(MachineState *machine)
>  spapr_setup_hpt_and_vrma(spapr);
>  }
>  
> -/*
> - * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> - * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> - * called from vPHB reset handler so we initialize the counter here.
> - * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> - * must be equally distant from any other node.
> - * The final value of spapr->gpu_numa_id is going to be written to
> - * max-associativity-domains in spapr_build_fdt().
> - */
> -spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
>  qemu_devices_reset();
>  
>  /*
> @@ -2885,6 +2875,17 @@ static void spapr_machine_init(MachineState *machine)
>  
>  }
>  
> +/*
> + * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
> + * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
> + * called from vPHB reset handler so we initialize the counter here.
> + * If no NUMA is configured from the QEMU side, we start from 1 as GPU 
> RAM
> + * must be equally distant from any other node.
> + * The final value of spapr->gpu_numa_id is going to be written to
> + * max-associativity-domains in spapr_build_fdt().
> + */
> +spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
> +
>  if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
>  ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
>spapr->max_compat_pvr)) {
> 

-- 
Alexey

Re: [Qemu-devel] [PATCH v13 6/6] migration: Include migration support for machine check handling

[Aravinda Prasad]

On Tuesday 10 September 2019 02:18 PM, Greg Kurz wrote:
> Hi Aravinda,
> 
> Sorry for not being able to review the whole series in one pass,
> and thus forcing you to poste more versions... but I have some
> more remarks about migration.

That's fine. In fact I have to thank you for your time for reviewing my
patches.

> 
> On Mon, 09 Sep 2019 12:55:02 +0530
> Aravinda Prasad  wrote:
> 
>> This patch includes migration support for machine check
>> handling. Especially this patch blocks VM migration
>> requests until the machine check error handling is
>> complete as (i) these errors are specific to the source
>> hardware and is irrelevant on the target hardware,
>> (ii) these errors cause data corruption and should
>> be handled before migration.
>>
>> Signed-off-by: Aravinda Prasad 
>> ---
>>  hw/ppc/spapr.c |   44 
>>  hw/ppc/spapr_events.c  |   14 ++
>>  hw/ppc/spapr_rtas.c|2 ++
>>  include/hw/ppc/spapr.h |2 ++
>>  4 files changed, 62 insertions(+)
>>
>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>> index 1c0908e..f6262f0 100644
>> --- a/hw/ppc/spapr.c
>> +++ b/hw/ppc/spapr.c
>> @@ -46,6 +46,7 @@
>>  #include "migration/qemu-file-types.h"
>>  #include "migration/global_state.h"
>>  #include "migration/register.h"
>> +#include "migration/blocker.h"
>>  #include "mmu-hash64.h"
>>  #include "mmu-book3s-v3.h"
>>  #include "cpu-models.h"
>> @@ -1829,6 +1830,8 @@ static void spapr_machine_reset(MachineState *machine)
>>  
>>  /* Signal all vCPUs waiting on this condition */
>>  qemu_cond_broadcast(&spapr->mc_delivery_cond);
>> +
>> +migrate_del_blocker(spapr->fwnmi_migration_blocker);
>>  }
>>  
>>  static void spapr_create_nvram(SpaprMachineState *spapr)
>> @@ -2119,6 +2122,42 @@ static const VMStateDescription vmstate_spapr_dtb = {
>>  },
>>  };
>>  
>> +static bool spapr_fwnmi_needed(void *opaque)
>> +{
>> +SpaprMachineState *spapr = (SpaprMachineState *)opaque;
>> +
>> +return spapr->guest_machine_check_addr != -1;
>> +}
>> +
>> +static int spapr_fwnmi_post_load(void *opaque, int version_id)
>> +{
>> +SpaprMachineState *spapr = (SpaprMachineState *)opaque;
>> +
>> +if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) {
>> +
>> +if (kvmppc_has_cap_ppc_fwnmi()) {
>> +return 0;
>> +}
>> +
>> +return kvmppc_set_fwnmi();
>> +}
>> +
>> +return 0;
>> +}
>> +
>> +static const VMStateDescription vmstate_spapr_machine_check = {
>> +.name = "spapr_machine_check",
>> +.version_id = 1,
>> +.minimum_version_id = 1,
>> +.needed = spapr_fwnmi_needed,
>> +.post_load = spapr_fwnmi_post_load,
>> +.fields = (VMStateField[]) {
>> +VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState),
>> +VMSTATE_INT32(mc_status, SpaprMachineState),
>> +VMSTATE_END_OF_LIST()
>> +},
>> +};
>> +
>>  static const VMStateDescription vmstate_spapr = {
>>  .name = "spapr",
>>  .version_id = 3,
>> @@ -2152,6 +2191,7 @@ static const VMStateDescription vmstate_spapr = {
>>  &vmstate_spapr_dtb,
>>  &vmstate_spapr_cap_large_decr,
>>  &vmstate_spapr_cap_ccf_assist,
>> +&vmstate_spapr_machine_check,
>>  NULL
>>  }
>>  };
>> @@ -2948,6 +2988,10 @@ static void spapr_machine_init(MachineState *machine)
>>  exit(1);
>>  }
>>  
>> +/* Create the error string for live migration blocker */
>> +error_setg(&spapr->fwnmi_migration_blocker,
>> +"Live migration not supported during machine check handling");
>> +
>>  /* Register ibm,nmi-register and ibm,nmi-interlock RTAS calls */
>>  spapr_fwnmi_register();
>>  }
>> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
>> index ecc3d68..83f0a22 100644
>> --- a/hw/ppc/spapr_events.c
>> +++ b/hw/ppc/spapr_events.c
>> @@ -43,6 +43,7 @@
>>  #include "qemu/main-loop.h"
>>  #include "hw/ppc/spapr_ovec.h"
>>  #include 
>> +#include "migration/blocker.h"
>>  
>>  #define RTAS_LOG_VERSION_MASK   0xff00
>>  #define   RTAS_LOG_VERSION_60x0600
>> @@ -844,6 +845,8 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered)
>>  {
>>  SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
>>  CPUState *cs = CPU(cpu);
>> +int ret;
>> +Error *local_err = NULL;
>>  
>>  if (spapr->guest_machine_check_addr == -1) {
>>  /*
>> @@ -857,6 +860,17 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool 
>> recovered)
>>  return;
>>  }
>>  
>> +ret = migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err);
> 
> If an MCE is already being handled, this adds yet another blocker. IIUC only
> the vCPU handling the previous MCE is supposed to call "ibm,nmi-interlock"
> and clear the blocker. This might cause a blocker to be leaked. I think
> migrate_add_blocker() should only be called when we know that the 

Re: [Qemu-devel] [PATCH V2 2/2] block/nfs: add support for nfs_umount

[Max Reitz]

On 10.09.19 17:41, Peter Lieven wrote:
> libnfs recently added support for unmounting. Add support
> in Qemu too.
> 
> Signed-off-by: Peter Lieven 
> ---
>  block/nfs.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/block/nfs.c b/block/nfs.c
> index 2c98508275..f39acfdb28 100644
> --- a/block/nfs.c
> +++ b/block/nfs.c
> @@ -398,6 +398,9 @@ static void nfs_client_close(NFSClient *client)
>  nfs_close(client->context, client->fh);
>  client->fh = NULL;
>  }
> +#ifdef LIBNFS_FEATURE_UMOUNT
> +nfs_umount(client->context);
> +#endif
>  nfs_destroy_context(client->context);
>  client->context = NULL;
>  }

I don’t understand what unmounting means in this context.  Is it just
generic clean-up for NFSv3 (it appears that it’s a no-op for NFSv4)?
Why isn’t that done by nfs_destroy_context()?

Max



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Re: [Qemu-devel] [PATCH 7/7] spapr: Perform machine reset in a more sensible order

[David Gibson]

On Wed, Sep 11, 2019 at 05:40:58PM +1000, Alexey Kardashevskiy wrote:
> 
> 
> On 11/09/2019 14:04, David Gibson wrote:
> > We've made several changes in the past to the machine reset order to fix
> > specific problems.  However, we've ended up with an order that doesn't make
> > a lot of logical sense.  This is an attempt to rectify this.
> > 
> > First we reset global CAS options, since that should depend on nothing
> > else.  Then we reset the CPUs, which shouldn't depend on external devices.
> > Then the irq subsystem, then the bulk of devices (which might rely on
> > irqs).  Finally we set up the entry state ready for boot, which could
> > potentially rely on a bunch of other things.
> > 
> > Signed-off-by: David Gibson 
> 
> 
> Breaks console on P8 and asserts on rebooting a P9 guest.

Yeah, I jumped the gun on this one - I need to rethink and test more thoroughly.

> 
> 
> 
> > ---
> >  hw/ppc/spapr.c | 47 +--
> >  1 file changed, 25 insertions(+), 22 deletions(-)
> > 
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 5a919a6cc1..1560a11738 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -1724,6 +1724,28 @@ static void spapr_machine_reset(MachineState 
> > *machine)
> >  void *fdt;
> >  int rc;
> >  
> > +/*
> > + * If this reset wasn't generated by CAS, we should reset our
> > + * negotiated options and start from scratch
> > + */
> > +if (!spapr->cas_reboot) {
> > +spapr_ovec_cleanup(spapr->ov5_cas);
> > +spapr->ov5_cas = spapr_ovec_new();
> > +
> > +ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> > +}
> > +
> > +/*
> > + * There is no CAS under qtest. Simulate one to please the code that
> > + * depends on spapr->ov5_cas. This is especially needed to test device
> > + * unplug, so we do that before resetting the DRCs.
> > + */
> > +if (qtest_enabled()) {
> > +spapr_ovec_cleanup(spapr->ov5_cas);
> > +spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> > +}
> > +
> > +/* Reset the CPUs */
> >  spapr_caps_apply(spapr);
> >  
> >  first_ppc_cpu = POWERPC_CPU(first_cpu);
> > @@ -1741,34 +1763,15 @@ static void spapr_machine_reset(MachineState 
> > *machine)
> >  spapr_setup_hpt_and_vrma(spapr);
> >  }
> >  
> > -qemu_devices_reset();
> > -
> > -/*
> > - * If this reset wasn't generated by CAS, we should reset our
> > - * negotiated options and start from scratch
> > - */
> > -if (!spapr->cas_reboot) {
> > -spapr_ovec_cleanup(spapr->ov5_cas);
> > -spapr->ov5_cas = spapr_ovec_new();
> > -
> > -ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> > -}
> > -
> > +/* Reset IRQ subsystem */
> >  /*
> >   * This is fixing some of the default configuration of the XIVE
> >   * devices. To be called after the reset of the machine devices.
> >   */
> >  spapr_irq_reset(spapr, &error_fatal);
> >  
> > -/*
> > - * There is no CAS under qtest. Simulate one to please the code that
> > - * depends on spapr->ov5_cas. This is especially needed to test device
> > - * unplug, so we do that before resetting the DRCs.
> > - */
> > -if (qtest_enabled()) {
> > -spapr_ovec_cleanup(spapr->ov5_cas);
> > -spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> > -}
> > +/* Reset other devices */
> > +qemu_devices_reset();
> >  
> >  /* DRC reset may cause a device to be unplugged. This will cause 
> > troubles
> >   * if this device is used by another device (eg, a running vhost 
> > backend
> > 
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 7/7] spapr: Perform machine reset in a more sensible order

[Cédric Le Goater]

On 11/09/2019 06:04, David Gibson wrote:
> We've made several changes in the past to the machine reset order to fix
> specific problems.  However, we've ended up with an order that doesn't make
> a lot of logical sense.  This is an attempt to rectify this.

There are some more problems though. See below.

> 
> First we reset global CAS options, since that should depend on nothing
> else.  Then we reset the CPUs, which shouldn't depend on external devices.
> Then the irq subsystem, then the bulk of devices (which might rely on
> irqs).  Finally we set up the entry state ready for boot, which could
> potentially rely on a bunch of other things.
> 
> Signed-off-by: David Gibson 
> ---
>  hw/ppc/spapr.c | 47 +--
>  1 file changed, 25 insertions(+), 22 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 5a919a6cc1..1560a11738 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1724,6 +1724,28 @@ static void spapr_machine_reset(MachineState *machine)
>  void *fdt;
>  int rc;
>  
> +/*
> + * If this reset wasn't generated by CAS, we should reset our
> + * negotiated options and start from scratch
> + */
> +if (!spapr->cas_reboot) {
> +spapr_ovec_cleanup(spapr->ov5_cas);
> +spapr->ov5_cas = spapr_ovec_new();
> +
> +ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> +}
> +
> +/*
> + * There is no CAS under qtest. Simulate one to please the code that
> + * depends on spapr->ov5_cas. This is especially needed to test device
> + * unplug, so we do that before resetting the DRCs.
> + */
> +if (qtest_enabled()) {
> +spapr_ovec_cleanup(spapr->ov5_cas);
> +spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> +}
> +
> +/* Reset the CPUs */
>  spapr_caps_apply(spapr);
>  
>  first_ppc_cpu = POWERPC_CPU(first_cpu);
> @@ -1741,34 +1763,15 @@ static void spapr_machine_reset(MachineState *machine)
>  spapr_setup_hpt_and_vrma(spapr);
>  }
>  
> -qemu_devices_reset();
> -
> -/*
> - * If this reset wasn't generated by CAS, we should reset our
> - * negotiated options and start from scratch
> - */
> -if (!spapr->cas_reboot) {
> -spapr_ovec_cleanup(spapr->ov5_cas);
> -spapr->ov5_cas = spapr_ovec_new();
> -
> -ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
> -}
> -
> +/* Reset IRQ subsystem */
>  /*
>   * This is fixing some of the default configuration of the XIVE
>   * devices. To be called after the reset of the machine devices.
>   */
>  spapr_irq_reset(spapr, &error_fatal);

spapr_irq_reset() is now called before qemu_devices_reset(). So it will
break the XIVE emulated model.

KVM P8 guests are also broken : 

 qemu-system-ppc64: kernel_irqchip requested but unavailable: Unable to restore 
KVM interrupt controller state (0x0) for CPU 0: Invalid argument

Something wrong in kvmppc_xics_set_icp(). I need to look closer.

and TCG P9 guests still do the reset after CAS. 

C.

>  
> -/*
> - * There is no CAS under qtest. Simulate one to please the code that
> - * depends on spapr->ov5_cas. This is especially needed to test device
> - * unplug, so we do that before resetting the DRCs.
> - */
> -if (qtest_enabled()) {
> -spapr_ovec_cleanup(spapr->ov5_cas);
> -spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
> -}
> +/* Reset other devices */
> +qemu_devices_reset();
>  
>  /* DRC reset may cause a device to be unplugged. This will cause troubles
>   * if this device is used by another device (eg, a running vhost backend
> 

Re: [Qemu-devel] [PATCH 4/7] spapr: Skip leading zeroes from memory@ DT node names

[Greg Kurz]

On Wed, 11 Sep 2019 14:04:49 +1000
David Gibson  wrote:

> From: Alexey Kardashevskiy 
> 
> The device tree build by QEMU at the machine reset time is used by SLOF
> to build its internal device tree but the node names are not preserved
> exactly so when QEMU provides a device tree update in response to H_CAS,
> it might become tricky to match a node from the update blob to
> the actual node in SLOF.
> 
> This removed leading zeroes from "memory@" nodes and makes
> the DTC checker happy.
> 
> Signed-off-by: Alexey Kardashevskiy 
> Signed-off-by: David Gibson 
> ---

Reviewed-by: Greg Kurz 

>  hw/ppc/spapr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index d93dacd483..d072c2aa3d 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -386,7 +386,7 @@ static int spapr_populate_memory_node(void *fdt, int 
> nodeid, hwaddr start,
>  mem_reg_property[0] = cpu_to_be64(start);
>  mem_reg_property[1] = cpu_to_be64(size);
>  
> -sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
> +sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
>  off = fdt_add_subnode(fdt, 0, mem_name);
>  _FDT(off);
>  _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));

Re: [Qemu-devel] [Qemu-block] [PATCH 0/7] Move qtests to a separate folder

[Thomas Huth]

On 11/09/2019 08.58, Kevin Wolf wrote:
> Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
>> On 9/10/19 1:58 PM, Thomas Huth wrote:
>>> Our "tests" directory is very overcrowded - we store the qtests,
>>> unit test and other files there. That makes it difficult to
>>> determine which file belongs to each test subsystem, and the
>>> wildcards in the MAINTAINERS file are inaccurate, too.
>>>
>>> Let's clean up this mess. The first patches disentangle some
>>> dependencies, and the last three patches then move the qtests
>>> and libqos (which is a subsystem of the qtests) to a new folder
>>> called "tests/qtest/".
>>
>> I'd also welcome a rename of tests/qemu-iotests to tests/iotests.
> 
> I might prefer if the directory were named "iotests" rather than
> "qemu-iotests" if we were only adding the code now.
> 
> However, I'm not so sure if I'd like a rename now because a rename
> always comes with a cost and the benefits are rather limited in this
> case.

Well, if we all agree that it rather should be renamed, we should maybe
rather do it now than later. Later the cost might even be higher.

 Thomas



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Re: [Qemu-devel] [PATCH v4 02/10] hw/core: create Resettable QOM interface

[David Gibson]

On Wed, Aug 21, 2019 at 06:33:33PM +0200, Damien Hedde wrote:
> This commit defines an interface allowing multi-phase reset. This aims
> to solve a problem of the actual single-phase reset (built in
> DeviceClass and BusClass): reset behavior is dependent on the order
> in which reset handlers are called. In particular doing external
> side-effect (like setting an qemu_irq) is problematic because receiving
> object may not be reset yet.
> 
> The Resettable interface divides the reset in 3 well defined phases.
> To reset an object tree, all 1st phases are executed then all 2nd then
> all 3rd. See the comments in include/hw/resettable.h for a more complete
> description. There is 3 phases to allow a device to be held in reset
> state; the ability to control this state will be added in a following
> commits.
> 
> The qdev/qbus reset in DeviceClass and BusClass will be modified in
> following commits to use this interface.
> No change of behavior is expected because the init phase execution order
> follows the children-then-parent order inside a tree. Since this is the
> actual order of qdev/qbus reset, we will be able to map current reset
> handlers on init phase for example.
> 
> In this patch only cold reset is introduced, which is pretty much the
> actual semantics of the current reset handlers. The interface can be
> extended to support more reset types.
> 
> Documentation will be added in a following commit.
> 
> Signed-off-by: Damien Hedde 
> ---
> 
> I kept the non-recursive count approach (a given object counts reset
> initiated on it as well as reset initiated on its parents in reset
> hierarchy). I implemented the other approach, it is possible but is more
> complex (an object has to know its direct parent(s) and we need to scan
> the reset hierarchy to know if we are in reset) so I prefer not
> to introduce it here.
> Moreover I think it has drawbacks if we want to handle complex reset
> use cases with more reset type.
> Anyway, as long as we don't migrate the reset-related state, there is
> no problem to switch between approaches.
> ---

So, I certainly prefer the more general "reset type" approach taken in
this version.  That said, I find it pretty hard to imagine what types
of reset other than cold will exist that have well enough defined
semantics to be meaningfully used from an external subsystem.

>  Makefile.objs   |   1 +
>  hw/core/Makefile.objs   |   1 +
>  hw/core/resettable.c| 186 
>  hw/core/trace-events|  36 
>  include/hw/resettable.h | 159 ++
>  5 files changed, 383 insertions(+)
>  create mode 100644 hw/core/resettable.c
>  create mode 100644 hw/core/trace-events
>  create mode 100644 include/hw/resettable.h
> 
> diff --git a/Makefile.objs b/Makefile.objs
> index 6a143dcd57..a723a47e14 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -191,6 +191,7 @@ trace-events-subdirs += migration
>  trace-events-subdirs += net
>  trace-events-subdirs += ui
>  endif
> +trace-events-subdirs += hw/core
>  trace-events-subdirs += hw/display
>  trace-events-subdirs += qapi
>  trace-events-subdirs += qom
> diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
> index b49f880a0c..69b408ad1c 100644
> --- a/hw/core/Makefile.objs
> +++ b/hw/core/Makefile.objs
> @@ -1,6 +1,7 @@
>  # core qdev-related obj files, also used by *-user:
>  common-obj-y += qdev.o qdev-properties.o
>  common-obj-y += bus.o reset.o
> +common-obj-y += resettable.o
>  common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o
>  common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o
>  # irq.o needed for qdev GPIO handling:
> diff --git a/hw/core/resettable.c b/hw/core/resettable.c
> new file mode 100644
> index 00..b534c2c7a4
> --- /dev/null
> +++ b/hw/core/resettable.c
> @@ -0,0 +1,186 @@
> +/*
> + * Resettable interface.
> + *
> + * Copyright (c) 2019 GreenSocs SAS
> + *
> + * Authors:
> + *   Damien Hedde
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/module.h"
> +#include "hw/resettable.h"
> +#include "trace.h"
> +
> +#define RESETTABLE_GET_CLASS(obj) \
> +OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE)
> +
> +static void resettable_foreach_child(ResettableClass *rc,
> + Object *obj,
> + void (*func)(Object *, ResetType type),
> + ResetType type)
> +{
> +if (rc->foreach_child) {
> +rc->foreach_child(obj, func, type);
> +}
> +}
> +
> +static void resettable_init_reset(Object *obj, ResetType type)

I wonder if "enter reset" would be better terminology so this doesn't
get confused with the initial, well, initialization of the device.

> +{
> +ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
> +ResetState *s = rc->get_state(obj);
> +

Re: [Qemu-devel] [PATCH v1 4/4] elf: move ELF_ARCH definition to elf-arch.h

[Alex Bennée]

Aleksandar Markovic  writes:

> 10.09.2019. 21.34, "Alex Bennée"  је написао/ла:
>>
>> This is preparatory for plugins which will want to report the
>> architecture to plugins. Move the ELF_ARCH definition out of the
>> loader and into its own header.
>>
>> Signed-off-by: Alex Bennée 
>> ---
>
> ELF_ARCH is and has been used exclusively locally within elfload.c, and
> some architectures use it in a specific way, which is perfectly legal in
> the current code organization, and I have certain reservations about this
> attempt to suddenly attach additional responsibility to these
> constants -

It is used locally for elfload (and was duplicated at that - as there is
a bsd and linux version). All it really does is translate the Elf
standard code for a guest architecture into a common symbol for the
benefit of common code. There is perhaps an argument this would be
better set in config-target.mak/h as it is something we could even know
at configure time.

> "reporting" to some unspecified plugin. In simpler words, it seems to me
> that you are trying to use a thing for something it was not meant to.

The discussion around the plugin is in the thread:

  Subject: [PATCH  v4 00/54] plugins for TCG
  Date: Wed, 31 Jul 2019 17:06:25 +0100
  Message-Id: <20190731160719.11396-1-alex.ben...@linaro.org>

but essentially it would be nice if the plugin could be told what the
guest architecture is so it could either not attempt to initialise or
maybe change how it sets itself up. We could either come up with a QEMU
specific enumeration or perhaps report the TARGET_NAME string but given
the Elf spec defines a bunch of constants why not re-use them?

>
> Also, it would be better if you cc-ed corresponding architecture
> submaintainers.

I was relying on get_maintainer.pl but it doesn't really deal with these
common code cases that well. However they should all be CC'd on the main
movement patch as it touches a lot of subdirs:

  [PATCH  v1 2/4] elf: move elf.h to elf/elf.h and split out types

which should hopefully give them visibility of the thread.

>
> Yours, Aleksandar
>
>>  bsd-user/elfload.c |  13 +
>>  include/elf/elf-arch.h | 109 +
>>  linux-user/elfload.c   |  27 ++
>>  3 files changed, 115 insertions(+), 34 deletions(-)
>>  create mode 100644 include/elf/elf-arch.h
>>
>> diff --git a/bsd-user/elfload.c b/bsd-user/elfload.c
>> index 321ee98b86b..adaae0e0dca 100644
>> --- a/bsd-user/elfload.c
>> +++ b/bsd-user/elfload.c
>> @@ -5,6 +5,7 @@
>>  #include "qemu.h"
>>  #include "disas/disas.h"
>>  #include "qemu/path.h"
>> +#include "elf/elf-arch.h"
>>
>>  #ifdef _ARCH_PPC64
>>  #undef ARCH_DLINFO
>> @@ -12,7 +13,6 @@
>>  #undef ELF_HWCAP
>>  #undef ELF_CLASS
>>  #undef ELF_DATA
>> -#undef ELF_ARCH
>>  #endif
>>
>>  /* from personality.h */
>> @@ -115,7 +115,6 @@ static uint32_t get_elf_hwcap(void)
>>
>>  #define ELF_CLASS  ELFCLASS64
>>  #define ELF_DATA   ELFDATA2LSB
>> -#define ELF_ARCH   EM_X86_64
>>
>>  static inline void init_thread(struct target_pt_regs *regs, struct
> image_info *infop)
>>  {
>> @@ -141,7 +140,6 @@ static inline void init_thread(struct target_pt_regs
> *regs, struct image_info *i
>>   */
>>  #define ELF_CLASS   ELFCLASS32
>>  #define ELF_DATAELFDATA2LSB
>> -#define ELF_ARCHEM_386
>>
>>  static inline void init_thread(struct target_pt_regs *regs, struct
> image_info *infop)
>>  {
>> @@ -176,7 +174,6 @@ static inline void init_thread(struct target_pt_regs
> *regs, struct image_info *i
>>  #else
>>  #define ELF_DATAELFDATA2LSB
>>  #endif
>> -#define ELF_ARCHEM_ARM
>>
>>  static inline void init_thread(struct target_pt_regs *regs, struct
> image_info *infop)
>>  {
>> @@ -231,7 +228,6 @@ enum
>>
>>  #define ELF_CLASS   ELFCLASS64
>>  #define ELF_DATAELFDATA2MSB
>> -#define ELF_ARCHEM_SPARCV9
>>
>>  #define STACK_BIAS  2047
>>
>> @@ -265,7 +261,6 @@ static inline void init_thread(struct target_pt_regs
> *regs, struct image_info *i
>>
>>  #define ELF_CLASS   ELFCLASS32
>>  #define ELF_DATAELFDATA2MSB
>> -#define ELF_ARCHEM_SPARC
>>
>>  static inline void init_thread(struct target_pt_regs *regs, struct
> image_info *infop)
>>  {
>> @@ -302,7 +297,6 @@ static inline void init_thread(struct target_pt_regs
> *regs, struct image_info *i
>>  #else
>>  #define ELF_DATAELFDATA2LSB
>>  #endif
>> -#define ELF_ARCHEM_PPC
>>
>>  /*
>>   * We need to put in some extra aux table entries to tell glibc what
>> @@ -388,7 +382,6 @@ static inline void init_thread(struct target_pt_regs
> *_regs, struct image_info *
>>  #else
>>  #define ELF_DATAELFDATA2LSB
>>  #endif
>> -#define ELF_ARCHEM_MIPS
>>
>>  static inline void init_thread(struct target_pt_regs *regs, struct
> image_info *infop)
>>  {
>> @@ -410,7 +403,6 @@ static inline void init_thread(struct target_pt_regs
> *regs, struct image_info *i
>>
>>  #define ELF_CLASS ELFCLASS32
>>  #define ELF_DATA  ELFDATA2

Re: [Qemu-devel] [PATCH v1 3/4] elf: move elf_ops.h into include/elf/ and rename

[Alex Bennée]

Alex Bennée  writes:

> Lets keep all the Elf manipulation bits together. Also rename the file
> to better reflect how it is used and add a little header to the file.
>
> Signed-off-by: Alex Bennée 
> ---
>  hw/core/loader.c| 4 ++--

It is arguable this could be a private header in hw/core as it is only
included in one place.

>  include/{hw/elf_ops.h => elf/elf_ops.inc.h} | 9 +
>  2 files changed, 11 insertions(+), 2 deletions(-)
>  rename include/{hw/elf_ops.h => elf/elf_ops.inc.h} (98%)
>
> diff --git a/hw/core/loader.c b/hw/core/loader.c
> index e0c6563e643..886179a4947 100644
> --- a/hw/core/loader.c
> +++ b/hw/core/loader.c
> @@ -302,7 +302,7 @@ static void *load_at(int fd, off_t offset, size_t size)
>  #define elf_worduint32_t
>  #define elf_swordint32_t
>  #define bswapSZs bswap32s
> -#include "hw/elf_ops.h"
> +#include "elf/elf_ops.inc.h"
>
>  #undef elfhdr
>  #undef elf_phdr
> @@ -324,7 +324,7 @@ static void *load_at(int fd, off_t offset, size_t size)
>  #define elf_swordint64_t
>  #define bswapSZs bswap64s
>  #define SZ   64
> -#include "hw/elf_ops.h"
> +#include "elf/elf_ops.inc.h"
>
>  const char *load_elf_strerror(int error)
>  {
> diff --git a/include/hw/elf_ops.h b/include/elf/elf_ops.inc.h
> similarity index 98%
> rename from include/hw/elf_ops.h
> rename to include/elf/elf_ops.inc.h
> index 1496d7e7536..a820bd821d5 100644
> --- a/include/hw/elf_ops.h
> +++ b/include/elf/elf_ops.inc.h
> @@ -1,3 +1,12 @@
> +/*
> + * Macro expansions for Elf operations. This is included in a
> + * compilation unit with appropriate definitions for SZ and elf
> + * headers to generate utility functions for reading 32 and 64 bit elf
> + * headers.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
>  static void glue(bswap_ehdr, SZ)(struct elfhdr *ehdr)
>  {
>  bswap16s(&ehdr->e_type); /* Object file type */


--
Alex Bennée

Re: [Qemu-devel] [PATCH v2 1/3] tests/migration: mem leak fix

[Alex Bennée]

Mao Zhongyi  writes:

> ‘data’ has the possibility of memory leaks， so use the
> glic macros g_autofree recommended by CODING_STYLE.rst

nit: glib

> to automatically release the memory that returned from
> g_malloc().
>
> Cc: arm...@redhat.com
> Cc: laur...@vivier.eu
> Cc: tony.ngu...@bt.com
> Cc: alex.ben...@linaro.org
>
> Signed-off-by: Mao Zhongyi 

Reviewed-by: Alex Bennée 

> ---
>  tests/migration/stress.c | 10 ++
>  1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/tests/migration/stress.c b/tests/migration/stress.c
> index d9aa4afe92..6cbb2d49d3 100644
> --- a/tests/migration/stress.c
> +++ b/tests/migration/stress.c
> @@ -170,10 +170,10 @@ static unsigned long long now(void)
>  static int stressone(unsigned long long ramsizeMB)
>  {
>  size_t pagesPerMB = 1024 * 1024 / PAGE_SIZE;
> -char *ram = malloc(ramsizeMB * 1024 * 1024);
> +g_autofree char *ram = malloc(ramsizeMB * 1024 * 1024);
>  char *ramptr;
>  size_t i, j, k;
> -char *data = malloc(PAGE_SIZE);
> +g_autofree char *data = malloc(PAGE_SIZE);
>  char *dataptr;
>  size_t nMB = 0;
>  unsigned long long before, after;
> @@ -186,7 +186,6 @@ static int stressone(unsigned long long ramsizeMB)
>  if (!data) {
>  fprintf(stderr, "%s (%d): ERROR: cannot allocate %d bytes of RAM: 
> %s\n",
>  argv0, gettid(), PAGE_SIZE, strerror(errno));
> -free(ram);
>  return -1;
>  }
>
> @@ -198,8 +197,6 @@ static int stressone(unsigned long long ramsizeMB)
>  memset(ram, 0xfe, ramsizeMB * 1024 * 1024);
>
>  if (random_bytes(data, PAGE_SIZE) < 0) {
> -free(ram);
> -free(data);
>  return -1;
>  }
>
> @@ -227,9 +224,6 @@ static int stressone(unsigned long long ramsizeMB)
>  }
>  }
>  }
> -
> -free(data);
> -free(ram);
>  }


--
Alex Bennée

[Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1

[Palmer Dabbelt]

The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:

  Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07' 
into staging (2019-09-09 09:48:34 +0100)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1

for you to fetch changes up to 1b2d0961bfaaa2db3a237f53273527b6c5e3498a:

  target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point (2019-09-10 06:08:42 
-0700)


RISC-V Patches for the 4.2 Soft Freeze, Part 1

This contains quite a few patches that I'd like to target for 4.2.
They're mostly emulation fixes for the sifive_u board, which now much
more closely matches the hardware and can therefor run the same fireware
as what gets loaded onto the board.  Additional user-visible
improvements include:

* support for loading initrd files from the command line into Linux, via
  /chosen/linux,initrd-{start,end} device tree nodes.
* The conversion of LOG_TRACE to trace events.
* The addition of clock DT nodes for our uart and ethernet.

This also includes some preliminary work for the H extension patches,
but does not include the H extension patches as I haven't had time to
review them yet.

This passes my OE boot test on 32-bit and 64-bit virt machines, as well
as a 64-bit upstream Linux boot on the sifive_u machine.


Alistair Francis (5):
  riscv: plic: Remove unused interrupt functions
  target/riscv: Create function to test if FP is enabled
  target/riscv: Update the Hypervisor CSRs to v0.4
  target/riscv: Fix mstatus dirty mask
  target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

Atish Patra (1):
  target/riscv: Use both register name and ABI name

Bin Meng (36):
  riscv: rv32: Root page table address can be larger than 32-bit
  riscv: Add a helper routine for finding firmware
  riscv: Resolve full path of the given bios image
  riscv: hmp: Add a command to show virtual memory mappings
  riscv: sifive_test: Add reset functionality
  riscv: hw: Remove duplicated "hw/hw.h" inclusion
  riscv: hw: Remove superfluous "linux, phandle" property
  riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
  riscv: hw: Remove not needed PLIC properties in device tree
  riscv: hw: Change create_fdt() to return void
  riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
  riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
  riscv: roms: Remove executable attribute of opensbi images
  riscv: sifive_u: Remove the unnecessary include of prci header
  riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
  riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
  riscv: sifive_e: prci: Update the PRCI register block size
  riscv: sifive_e: Drop sifive_mmio_emulate()
  riscv: Add a sifive_cpu.h to include both E and U cpu type defines
  riscv: hart: Extract hart realize to a separate routine
  riscv: hart: Add a "hartid-base" property to RISC-V hart array
  riscv: sifive_u: Set the minimum number of cpus to 2
  riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
  riscv: sifive_u: Update PLIC hart topology configuration string
  riscv: sifive: Implement PRCI model for FU540
  riscv: sifive_u: Generate hfclk and rtcclk nodes
  riscv: sifive_u: Add PRCI block to the SoC
  riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
  riscv: sifive_u: Update UART base addresses and IRQs
  riscv: sifive_u: Change UART node name in device tree
  riscv: roms: Update default bios for sifive_u machine
  riscv: sifive: Implement a model for SiFive FU540 OTP
  riscv: sifive_u: Instantiate OTP memory with a serial number
  riscv: sifive_u: Fix broken GEM support
  riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
  riscv: sifive_u: Update model and compatible strings in device tree

Guenter Roeck (3):
  riscv: sifive_u: Add support for loading initrd
  riscv: sivive_u: Add dummy serial clock and aliases entry for uart
  riscv: sifive_u: Fix clock-names property for ethernet node

Philippe Mathieu-Daudé (2):
  target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
  target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events

 hmp-commands-info.hx |   2 +-
 hw/riscv/Kconfig |   2 +
 hw/riscv/Makefile.objs   |   4 +-
 hw/riscv/boot.c  |  26 ++-
 hw/riscv/riscv_hart.c|  34 ++--
 hw/riscv/sifive_e.c  |  27 ++-
 hw/riscv/sifive_e_prci.c | 124 +
 hw/riscv/sifive_plic.c   |  12 --
 hw/riscv/s

[Qemu-devel] [PULL 03/47] riscv: sifive_u: Fix clock-names property for ethernet node

[Palmer Dabbelt]

From: Guenter Roeck 

The correct property name is clock-names, not clocks-names.

Without this patch, the Ethernet driver fails to instantiate with
the following error.

macb 100900fc.ethernet: failed to get macb_clk (-2)
macb: probe of 100900fc.ethernet failed with error -2

Signed-off-by: Guenter Roeck 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8313f2605e..ae5a16e636 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -215,7 +215,7 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 ethclk_phandle, ethclk_phandle, ethclk_phandle);
-qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
+qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 sizeof(ethclk_names));
 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
-- 
2.21.0

Re: [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers

[Palmer Dabbelt]

On Fri, 23 Aug 2019 16:38:15 PDT (-0700), Alistair Francis wrote:

To handle the new Hypervisor CSR register swapping let's use pointers.

We only need to convert the MIE and MSTATUS CSRs. With the exception of
MIP all of the other CSRs that swap with virtulsation changes are S-Mode
only, so we can just do a lazy switch. This because more challenging for
the M-Mode registers so it ends up being easier to use pointers.

As the MIP CSR is always accessed atomicly the pointer swap doesn't work
so we leave that as is.

Signed-off-by: Alistair Francis 
---
 target/riscv/cpu.c| 16 
 target/riscv/cpu.h| 12 ++--
 target/riscv/cpu_helper.c | 32 
 target/riscv/csr.c| 28 ++--
 target/riscv/op_helper.c  | 14 +++---
 5 files changed, 59 insertions(+), 43 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index be8f643fc2..371d5845af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -228,7 +228,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int 
flags)
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc  ", env->pc);
 #ifndef CONFIG_USER_ONLY
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", *env->mstatus);
 if (riscv_has_ext(env, RVH)) {
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstatus);
@@ -239,7 +239,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int 
flags)
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsip",
  (target_ulong)atomic_read(&env->vsip));
 }
-qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", *env->mie);
 if (riscv_has_ext(env, RVH)) {
 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsie", env->vsie);
 }
@@ -309,7 +309,7 @@ static bool riscv_cpu_has_work(CPUState *cs)
  * Definition of the WFI instruction requires it to ignore the privilege
  * mode and delegation registers, but respect individual enables
  */
-return (atomic_read(&env->mip) & env->mie) != 0;
+return (atomic_read(&env->mip) & *env->mie) != 0;
 #else
 return true;
 #endif
@@ -330,7 +330,7 @@ static void riscv_cpu_reset(CPUState *cs)
 mcc->parent_reset(cs);
 #ifndef CONFIG_USER_ONLY
 env->priv = PRV_M;
-env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+*env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 env->mcause = 0;
 env->pc = env->resetvec;
 #endif
@@ -459,8 +459,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 static void riscv_cpu_init(Object *obj)
 {
 RISCVCPU *cpu = RISCV_CPU(obj);
+#ifndef CONFIG_USER_ONLY
+CPURISCVState *env = &cpu->env;
+#endif

 cpu_set_cpustate_pointers(cpu);
+
+#ifndef CONFIG_USER_ONLY
+env->mie = &env->mie_novirt;
+env->mstatus = &env->mstatus_novirt;
+#endif
 }

 static const VMStateDescription vmstate_riscv_cpu = {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4c342e7a79..680592cb60 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -122,7 +122,7 @@ struct CPURISCVState {
 target_ulong resetvec;

 target_ulong mhartid;
-target_ulong mstatus;
+target_ulong *mstatus;

 /*
  * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
@@ -136,7 +136,7 @@ struct CPURISCVState {
 uint32_t mip;
 uint32_t miclaim;

-target_ulong mie;
+target_ulong *mie;
 target_ulong mideleg;

 target_ulong sptbr;  /* until: priv-1.9.1 */
@@ -154,6 +154,14 @@ struct CPURISCVState {
 target_ulong mcause;
 target_ulong mtval;  /* since: priv-1.10.0 */

+/* The following registers are the "real" versions that the pointer
+ * versions point to. These should never be used unless you know what you
+ * are doing. To access these use the pointer versions instead. This is
+ * required to handle the Hypervisor register swapping.
+ */
+target_ulong mie_novirt;
+target_ulong mstatus_novirt;
+
 /* Hypervisor CSRs */
 target_ulong hstatus;
 target_ulong hedeleg;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5bcfc2e090..c597523d74 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -36,9 +36,9 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {
-target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
-target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
-target_ulong pending = atomic_read(&env->mip) & env->mie;
+target_ulong mstatus_mie = get_field(*env->mstatus, MSTATUS_MIE);
+target_ul

[Qemu-devel] [PULL 02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart

[Palmer Dabbelt]

From: Guenter Roeck 

The riscv uart needs valid clocks. This requires a refereence
to the clock node. Since the SOC clock is not emulated by qemu,
add a reference to a fixed clock instead. The clock-frequency
entry in the uart node does not seem to be necessary, so drop it.

In addition to a reference to the clock, the driver also needs
an aliases entry for the serial node. Add it as well.

Without this patch, the serial driver fails to instantiate with
the following error message.

sifive-serial 10013000.uart: unable to find controller clock
sifive-serial: probe of 10013000.uart failed with error -2

when trying to boot Linux.

Signed-off-by: Guenter Roeck 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 32167d05a1..8313f2605e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -76,6 +76,7 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 char *nodename;
 char ethclk_names[] = "pclk\0hclk\0tx_clk";
 uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+uint32_t uartclk_phandle;
 
 fdt = s->fdt = create_device_tree(&s->fdt_size);
 if (!fdt) {
@@ -226,6 +227,17 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
+uartclk_phandle = phandle++;
+nodename = g_strdup_printf("/soc/uartclk");
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", uartclk_phandle);
+uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
+g_free(nodename);
+
 nodename = g_strdup_printf("/soc/uart@%lx",
 (long)memmap[SIFIVE_U_UART0].base);
 qemu_fdt_add_subnode(fdt, nodename);
@@ -233,8 +245,7 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_UART0].base,
 0x0, memmap[SIFIVE_U_UART0].size);
-qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-  SIFIVE_U_CLOCK_FREQ / 2);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks", uartclk_phandle);
 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 
@@ -243,6 +254,10 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 if (cmdline) {
 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 }
+
+qemu_fdt_add_subnode(fdt, "/aliases");
+qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
+
 g_free(nodename);
 
 return fdt;
-- 
2.21.0

[Qemu-devel] [PULL 07/47] target/riscv: Create function to test if FP is enabled

[Palmer Dabbelt]

From: Alistair Francis 

Let's create a function that tests if floating point support is
enabled. We can then protect all floating point operations based on if
they are enabled.

This patch so far doesn't change anything, it's just preparing for the
Hypervisor support for floating point operations.

Signed-off-by: Alistair Francis 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Christophe de Dinechin 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu.h|  6 +-
 target/riscv/cpu_helper.c | 10 ++
 target/riscv/csr.c| 20 +++-
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 18d91d0920..16efe8c860 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu);
 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
+bool riscv_cpu_fp_enabled(CPURISCVState *env);
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
@@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState 
*env, target_ulong *pc,
 #ifdef CONFIG_USER_ONLY
 *flags = TB_FLAGS_MSTATUS_FS;
 #else
-*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
+*flags = cpu_mmu_index(env, 0);
+if (riscv_cpu_fp_enabled(env)) {
+*flags |= env->mstatus & MSTATUS_FS;
+}
 #endif
 }
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b6126af..96373b67d8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
 
 #if !defined(CONFIG_USER_ONLY)
 
+/* Return true is floating point support is currently enabled */
+bool riscv_cpu_fp_enabled(CPURISCVState *env)
+{
+if (env->mstatus & MSTATUS_FS) {
+return true;
+}
+
+return false;
+}
+
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 {
 CPURISCVState *env = &cpu->env;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0d4586760..2789215b5e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
 static int fs(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 #endif
@@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno)
 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 #endif
@@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, 
target_ulong *val)
 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 env->mstatus |= MSTATUS_FS;
@@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, 
target_ulong val)
 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 #endif
@@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, 
target_ulong *val)
 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 env->mstatus |= MSTATUS_FS;
@@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, 
target_ulong val)
 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 #endif
@@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, 
target_ulong *val)
 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
-if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
+if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 return -1;
 }
 env->mstatus |= MSTATUS_FS;
@@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, 
target_ulong val)
 {
 target_ulong mstatus = env-

[Qemu-devel] [PULL 05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events

[Palmer Dabbelt]

From: Philippe Mathieu-Daudé 

Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.

Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/pmp.c| 31 ++-
 target/riscv/trace-events |  6 ++
 2 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d836288cb4..d4f1007109 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -27,14 +27,7 @@
 #include "qemu/log.h"
 #include "qapi/error.h"
 #include "cpu.h"
-
-#define RISCV_DEBUG_PMP 0
-#define PMP_DEBUG(fmt, ...)
\
-do {   
\
-if (RISCV_DEBUG_PMP) { 
\
-qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, 
##__VA_ARGS__);\
-}  
\
-} while (0)
+#include "trace.h"
 
 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
 uint8_t val);
@@ -302,8 +295,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t 
reg_index,
 int i;
 uint8_t cfg_val;
 
-PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
-env->mhartid, reg_index, val);
+trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
 
 if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
 qemu_log_mask(LOG_GUEST_ERROR,
@@ -332,9 +324,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t 
reg_index)
 val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
 cfg_val |= (val << (i * 8));
 }
-
-PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
-env->mhartid, reg_index, cfg_val);
+trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
 
 return cfg_val;
 }
@@ -346,9 +336,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t 
reg_index)
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
 target_ulong val)
 {
-PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
-env->mhartid, addr_index, val);
-
+trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
 if (addr_index < MAX_RISCV_PMPS) {
 if (!pmp_is_locked(env, addr_index)) {
 env->pmp_state.pmp[addr_index].addr_reg = val;
@@ -369,14 +357,15 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
  */
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
 {
-PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
-env->mhartid, addr_index,
-env->pmp_state.pmp[addr_index].addr_reg);
+target_ulong val = 0;
+
 if (addr_index < MAX_RISCV_PMPS) {
-return env->pmp_state.pmp[addr_index].addr_reg;
+val = env->pmp_state.pmp[addr_index].addr_reg;
+trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
 } else {
 qemu_log_mask(LOG_GUEST_ERROR,
   "ignoring pmpaddr read - out of bounds\n");
-return 0;
 }
+
+return val;
 }
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index 48af0373df..4b6c652ae9 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -1,2 +1,8 @@
 # target/riscv/cpu_helper.c
 riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t 
tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", 
epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
+
+# pmp.c
+pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" 
PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64
+pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" 
PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
+pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" 
PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
+pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart 
%" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
-- 
2.21.0

[Qemu-devel] [PULL 01/47] riscv: sifive_u: Add support for loading initrd

[Palmer Dabbelt]

From: Guenter Roeck 

Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.

Signed-off-by: Guenter Roeck 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9910fa6708..32167d05a1 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -67,7 +67,7 @@ static const struct MemmapEntry {
 
 #define GEM_REVISION0x10070109
 
-static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
+static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 uint64_t mem_size, const char *cmdline)
 {
 void *fdt;
@@ -244,11 +244,14 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 }
 g_free(nodename);
+
+return fdt;
 }
 
 static void riscv_sifive_u_init(MachineState *machine)
 {
 const struct MemmapEntry *memmap = sifive_u_memmap;
+void *fdt;
 
 SiFiveUState *s = g_new0(SiFiveUState, 1);
 MemoryRegion *system_memory = get_system_memory();
@@ -269,13 +272,24 @@ static void riscv_sifive_u_init(MachineState *machine)
 main_mem);
 
 /* create device tree */
-create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
  memmap[SIFIVE_U_DRAM].base);
 
 if (machine->kernel_filename) {
-riscv_load_kernel(machine->kernel_filename);
+uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+
+if (machine->initrd_filename) {
+hwaddr start;
+hwaddr end = riscv_load_initrd(machine->initrd_filename,
+   machine->ram_size, kernel_entry,
+   &start);
+qemu_fdt_setprop_cell(fdt, "/chosen",
+  "linux,initrd-start", start);
+qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+  end);
+}
 }
 
 /* reset vector */
-- 
2.21.0

[Qemu-devel] [PULL 04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation

[Palmer Dabbelt]

From: Philippe Mathieu-Daudé 

The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/Makefile.objs | 3 ++-
 target/riscv/pmp.c | 4 
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index b1c79bc1d1..b754e4bf32 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,4 +1,5 @@
-obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
gdbstub.o pmp.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
gdbstub.o
+obj-$(CONFIG_SOFTMMU) += pmp.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 958c7502a0..d836288cb4 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -28,8 +28,6 @@
 #include "qapi/error.h"
 #include "cpu.h"
 
-#ifndef CONFIG_USER_ONLY
-
 #define RISCV_DEBUG_PMP 0
 #define PMP_DEBUG(fmt, ...)
\
 do {   
\
@@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t 
addr_index)
 return 0;
 }
 }
-
-#endif
-- 
2.21.0

[Qemu-devel] [PULL 10/47] riscv: Add a helper routine for finding firmware

[Palmer Dabbelt]

From: Bin Meng 

This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/boot.c | 22 +++---
 include/hw/riscv/boot.h |  1 +
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 4c63b5cf8a..10f7991490 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -69,13 +69,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
  * so then in the future we can make "-bios default" the default option
  * if no -bios option is set without breaking anything.
  */
-firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
-   default_machine_firmware);
-if (firmware_filename == NULL) {
-error_report("Unable to load the default RISC-V firmware \"%s\"",
- default_machine_firmware);
-exit(1);
-}
+firmware_filename = riscv_find_firmware(default_machine_firmware);
 } else {
 firmware_filename = machine->firmware;
 }
@@ -90,6 +84,20 @@ void riscv_find_and_load_firmware(MachineState *machine,
 }
 }
 
+char *riscv_find_firmware(const char *firmware_filename)
+{
+char *filename;
+
+filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
+if (filename == NULL) {
+error_report("Unable to load the RISC-V firmware \"%s\"",
+ firmware_filename);
+exit(1);
+}
+
+return filename;
+}
+
 target_ulong riscv_load_firmware(const char *firmware_filename,
  hwaddr firmware_load_addr)
 {
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 1f21c2bef1..66075d0e57 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -25,6 +25,7 @@
 void riscv_find_and_load_firmware(MachineState *machine,
   const char *default_machine_firmware,
   hwaddr firmware_load_addr);
+char *riscv_find_firmware(const char *firmware_filename);
 target_ulong riscv_load_firmware(const char *firmware_filename,
  hwaddr firmware_load_addr);
 target_ulong riscv_load_kernel(const char *kernel_filename);
-- 
2.21.0

[Qemu-devel] [PULL 09/47] riscv: rv32: Root page table address can be larger than 32-bit

[Palmer Dabbelt]

From: Bin Meng 

For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu_helper.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 96373b67d8..87dd6a6ece 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -186,12 +186,12 @@ static int get_physical_address(CPURISCVState *env, 
hwaddr *physical,
 
 *prot = 0;
 
-target_ulong base;
+hwaddr base;
 int levels, ptidxbits, ptesize, vm, sum;
 int mxr = get_field(env->mstatus, MSTATUS_MXR);
 
 if (env->priv_ver >= PRIV_VERSION_1_10_0) {
-base = get_field(env->satp, SATP_PPN) << PGSHIFT;
+base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 sum = get_field(env->mstatus, MSTATUS_SUM);
 vm = get_field(env->satp, SATP_MODE);
 switch (vm) {
@@ -211,7 +211,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr 
*physical,
   g_assert_not_reached();
 }
 } else {
-base = env->sptbr << PGSHIFT;
+base = (hwaddr)(env->sptbr) << PGSHIFT;
 sum = !get_field(env->mstatus, MSTATUS_PUM);
 vm = get_field(env->mstatus, MSTATUS_VM);
 switch (vm) {
@@ -249,7 +249,7 @@ restart:
((1 << ptidxbits) - 1);
 
 /* check that physical address of PTE is legal */
-target_ulong pte_addr = base + idx * ptesize;
+hwaddr pte_addr = base + idx * ptesize;
 
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
@@ -261,7 +261,7 @@ restart:
 #elif defined(TARGET_RISCV64)
 target_ulong pte = ldq_phys(cs->as, pte_addr);
 #endif
-target_ulong ppn = pte >> PTE_PPN_SHIFT;
+hwaddr ppn = pte >> PTE_PPN_SHIFT;
 
 if (!(pte & PTE_V)) {
 /* Invalid PTE */
-- 
2.21.0

[Qemu-devel] [PULL 08/47] target/riscv: Update the Hypervisor CSRs to v0.4

[Palmer Dabbelt]

From: Alistair Francis 

Update the Hypervisor CSR addresses to match the v0.4 spec.

Signed-off-by: Alistair Francis 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu_bits.h | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971ad5d..e99834856c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -173,6 +173,24 @@
 #define CSR_SPTBR   0x180
 #define CSR_SATP0x180
 
+/* Hpervisor CSRs */
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HCOUNTERNEN 0x606
+#define CSR_HGATP   0x680
+
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE   SATP32_MODE
+#define HGATP_VMID   SATP32_ASID
+#define HGATP_PPNSATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE   SATP64_MODE
+#define HGATP_VMID   SATP64_ASID
+#define HGATP_PPNSATP64_PPN
+#endif
+
 /* Physical Memory Protection */
 #define CSR_PMPCFG0 0x3a0
 #define CSR_PMPCFG1 0x3a1
@@ -206,23 +224,6 @@
 #define CSR_DPC 0x7b1
 #define CSR_DSCRATCH0x7b2
 
-/* Hpervisor CSRs */
-#define CSR_HSTATUS 0xa00
-#define CSR_HEDELEG 0xa02
-#define CSR_HIDELEG 0xa03
-#define CSR_HGATP   0xa80
-
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE   SATP32_MODE
-#define HGATP_ASID   SATP32_ASID
-#define HGATP_PPNSATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE   SATP64_MODE
-#define HGATP_ASID   SATP64_ASID
-#define HGATP_PPNSATP64_PPN
-#endif
-
 /* Performance Counters */
 #define CSR_MHPMCOUNTER30xb03
 #define CSR_MHPMCOUNTER40xb04
-- 
2.21.0

[Qemu-devel] [PULL 06/47] riscv: plic: Remove unused interrupt functions

[Palmer Dabbelt]

From: Alistair Francis 

Signed-off-by: Alistair Francis 
Reviewed-by: Jonathan Behrens 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Chih-Min Chao 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_plic.c | 12 
 include/hw/riscv/sifive_plic.h |  3 ---
 2 files changed, 15 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 64a1a10380..98e4304b66 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -162,18 +162,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
 }
 }
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
-sifive_plic_set_pending(plic, irq, true);
-sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
-sifive_plic_set_pending(plic, irq, false);
-sifive_plic_update(plic);
-}
-
 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 {
 int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index b0edba2884..4421e81249 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
 uint32_t aperture_size;
 } SiFivePLICState;
 
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 uint32_t num_sources, uint32_t num_priorities,
 uint32_t priority_base, uint32_t pending_base,
-- 
2.21.0

[Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree

[Palmer Dabbelt]

From: Bin Meng 

This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.

Signed-off-by: Bin Meng 
Reviewed-by: Jonathan Behrens 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 2 --
 hw/riscv/virt.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 762223c6fe..e8acdd9b12 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -180,8 +180,6 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_PLIC].base,
 0x0, memmap[SIFIVE_U_PLIC].size);
-qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
-qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6852178bc2..090512be13 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[VIRT_PLIC].base,
 0x0, memmap[VIRT_PLIC].size);
-qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
-qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
-- 
2.21.0

[Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality

[Palmer Dabbelt]

From: Bin Meng 

This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_test.c | 4 
 include/hw/riscv/sifive_test.h | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index afbb3aaf34..3557e16701 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -22,6 +22,7 @@
 #include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "qemu/module.h"
+#include "sysemu/runstate.h"
 #include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/riscv/sifive_test.h"
@@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
 exit(code);
 case FINISHER_PASS:
 exit(0);
+case FINISHER_RESET:
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+return;
 default:
 break;
 }
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
index 3a603a6ead..1ec416ac1b 100644
--- a/include/hw/riscv/sifive_test.h
+++ b/include/hw/riscv/sifive_test.h
@@ -36,7 +36,8 @@ typedef struct SiFiveTestState {
 
 enum {
 FINISHER_FAIL = 0x,
-FINISHER_PASS = 0x
+FINISHER_PASS = 0x,
+FINISHER_RESET = 0x
 };
 
 DeviceState *sifive_test_create(hwaddr addr);
-- 
2.21.0

[Qemu-devel] [PULL 12/47] riscv: hmp: Add a command to show virtual memory mappings

[Palmer Dabbelt]

From: Bin Meng 

This adds 'info mem' command for RISC-V, to show virtual memory
mappings that aids debugging.

Rather than showing every valid PTE, the command compacts the
output by merging all contiguous physical address mappings into
one block and only shows the merged block mapping details.

Signed-off-by: Bin Meng 
Acked-by: Dr. David Alan Gilbert 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt 
---
 hmp-commands-info.hx   |   2 +-
 target/riscv/Makefile.objs |   4 +
 target/riscv/monitor.c | 229 +
 3 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/monitor.c

diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
index c59444c461..257ee7d7a3 100644
--- a/hmp-commands-info.hx
+++ b/hmp-commands-info.hx
@@ -249,7 +249,7 @@ STEXI
 Show virtual to physical memory mappings.
 ETEXI
 
-#if defined(TARGET_I386)
+#if defined(TARGET_I386) || defined(TARGET_RISCV)
 {
 .name   = "mem",
 .args_type  = "",
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index b754e4bf32..ff651f69f6 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,6 +1,10 @@
 obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o 
gdbstub.o
 obj-$(CONFIG_SOFTMMU) += pmp.o
 
+ifeq ($(CONFIG_SOFTMMU),y)
+obj-y += monitor.o
+endif
+
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
 decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
new file mode 100644
index 00..d725a7a36e
--- /dev/null
+++ b/target/riscv/monitor.c
@@ -0,0 +1,229 @@
+/*
+ * QEMU monitor for RISC-V
+ *
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * RISC-V specific monitor commands implementation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_bits.h"
+#include "monitor/monitor.h"
+#include "monitor/hmp-target.h"
+
+#ifdef TARGET_RISCV64
+#define PTE_HEADER_FIELDS   "vaddrpaddr"\
+"size attr\n"
+#define PTE_HEADER_DELIMITER"  "\
+" ---\n"
+#else
+#define PTE_HEADER_FIELDS   "vaddrpaddrsize attr\n"
+#define PTE_HEADER_DELIMITER"   ---\n"
+#endif
+
+/* Perform linear address sign extension */
+static target_ulong addr_canonical(int va_bits, target_ulong addr)
+{
+#ifdef TARGET_RISCV64
+if (addr & (1UL << (va_bits - 1))) {
+addr |= (hwaddr)-(1L << va_bits);
+}
+#endif
+
+return addr;
+}
+
+static void print_pte_header(Monitor *mon)
+{
+monitor_printf(mon, PTE_HEADER_FIELDS);
+monitor_printf(mon, PTE_HEADER_DELIMITER);
+}
+
+static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
+  hwaddr paddr, target_ulong size, int attr)
+{
+/* santity check on vaddr */
+if (vaddr >= (1UL << va_bits)) {
+return;
+}
+
+if (!size) {
+return;
+}
+
+monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
+   " %c%c%c%c%c%c%c\n",
+   addr_canonical(va_bits, vaddr),
+   paddr, size,
+   attr & PTE_R ? 'r' : '-',
+   attr & PTE_W ? 'w' : '-',
+   attr & PTE_X ? 'x' : '-',
+   attr & PTE_U ? 'u' : '-',
+   attr & PTE_G ? 'g' : '-',
+   attr & PTE_A ? 'a' : '-',
+   attr & PTE_D ? 'd' : '-');
+}
+
+static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+ int level, int ptidxbits, int ptesize, int va_bits,
+ target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
+ target_ulong *last_size, int *last_attr)
+{
+hwaddr pte_addr;
+hwaddr paddr;
+target_ulong pgsize;
+target_ulong pte;
+int ptshift;
+int attr;
+int idx;
+
+if (level < 0) {
+return;
+}
+
+ptshift = level * ptidxbits;
+pgsize = 1UL << (PGSHIFT + ptshift);
+
+for (idx = 0; idx < (1UL << ptidxbits); idx++) {
+pte_addr = base + idx * ptesize;
+cpu_physical_memory_read(pte_addr, &pte, ptesize);
+
+paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
+

[Qemu-devel] [PULL 11/47] riscv: Resolve full path of the given bios image

[Palmer Dabbelt]

From: Bin Meng 

At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/boot.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 10f7991490..2e92fb0680 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -72,14 +72,14 @@ void riscv_find_and_load_firmware(MachineState *machine,
 firmware_filename = riscv_find_firmware(default_machine_firmware);
 } else {
 firmware_filename = machine->firmware;
+if (strcmp(firmware_filename, "none")) {
+firmware_filename = riscv_find_firmware(firmware_filename);
+}
 }
 
 if (strcmp(firmware_filename, "none")) {
 /* If not "none" load the firmware */
 riscv_load_firmware(firmware_filename, firmware_load_addr);
-}
-
-if (!strcmp(machine->firmware, "default")) {
 g_free(firmware_filename);
 }
 }
-- 
2.21.0

[Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

[Palmer Dabbelt]

From: Bin Meng 

The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_prci.c | 1 -
 hw/riscv/sifive_test.c | 1 -
 hw/riscv/sifive_uart.c | 1 -
 3 files changed, 3 deletions(-)

diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 982fbb26fd..c413f0cb76 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -22,7 +22,6 @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/riscv/sifive_prci.h"
 
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index aa544e7428..339195c6ff 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -23,7 +23,6 @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
-#include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/riscv/sifive_test.h"
 
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 215990b443..a403ae90f5 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -22,7 +22,6 @@
 #include "hw/sysbus.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
 #include "hw/riscv/sifive_uart.h"
-- 
2.21.0

[Qemu-devel] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property

[Palmer Dabbelt]

From: Bin Meng 

"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 4 
 hw/riscv/spike.c| 1 -
 hw/riscv/virt.c | 3 ---
 3 files changed, 8 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ae5a16e636..0d9ff76a4f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -126,7 +126,6 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 qemu_fdt_add_subnode(fdt, intc);
 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
-qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -185,7 +184,6 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -198,7 +196,6 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 SIFIVE_U_GEM_CLOCK_FREQ);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
-qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(nodename);
 
@@ -234,7 +231,6 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
-qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", uartclk_phandle);
 uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(nodename);
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 7c04bd554f..d60415d190 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -112,7 +112,6 @@ static void create_fdt(SpikeState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 qemu_fdt_add_subnode(fdt, intc);
 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
-qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9bced28486..78091707dc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
-qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
 intc_phandle = phandle++;
 qemu_fdt_add_subnode(fdt, intc);
 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
-qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
-- 
2.21.0

[Qemu-devel] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead

[Palmer Dabbelt]

From: Bin Meng 

Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_prci.c | 8 +---
 hw/riscv/sifive_test.c | 5 +++--
 hw/riscv/sifive_uart.c | 9 +
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 562bc3dc4c..982fbb26fd 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -20,6 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/sysbus.h"
+#include "qemu/log.h"
 #include "qemu/module.h"
 #include "target/riscv/cpu.h"
 #include "hw/hw.h"
@@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, 
unsigned int size)
 case SIFIVE_PRCI_PLLOUTDIV:
 return s->plloutdiv;
 }
-hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
+  __func__, (int)addr);
 return 0;
 }
 
@@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
 s->plloutdiv = (uint32_t) val64;
 break;
 default:
-hw_error("%s: bad write: addr=0x%x v=0x%x\n",
- __func__, (int)addr, (int)val64);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+  __func__, (int)addr, (int)val64);
 }
 }
 
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 711740939e..aa544e7428 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -20,6 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/sysbus.h"
+#include "qemu/log.h"
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "target/riscv/cpu.h"
@@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr,
 break;
 }
 }
-hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
-__func__, (int)addr, val64);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 
"\n",
+  __func__, (int)addr, val64);
 }
 
 static const MemoryRegionOps sifive_test_ops = {
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 9de42b1680..215990b443 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -18,6 +18,7 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "qemu/log.h"
 #include "hw/sysbus.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
@@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
 return s->div;
 }
 
-hw_error("%s: bad read: addr=0x%x\n",
-__func__, (int)addr);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
+  __func__, (int)addr);
 return 0;
 }
 
@@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr,
 s->div = val64;
 return;
 }
-hw_error("%s: bad write: addr=0x%x v=0x%x\n",
-__func__, (int)addr, (int)value);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+  __func__, (int)addr, (int)value);
 }
 
 static const MemoryRegionOps uart_ops = {
-- 
2.21.0

[Qemu-devel] [PULL 14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion

[Palmer Dabbelt]

From: Bin Meng 

Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
added "hw/hw.h" to sifive_prci.c and sifive_test.c.

Another inclusion of "hw/hw.h" was later added via
commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that
resulted in duplicated inclusion of "hw/hw.h".

Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_prci.c | 1 -
 hw/riscv/sifive_test.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 9837b6166f..562bc3dc4c 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -19,7 +19,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "qemu/module.h"
 #include "target/riscv/cpu.h"
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 3557e16701..711740939e 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -19,7 +19,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
-- 
2.21.0

[Qemu-devel] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

[Palmer Dabbelt]

From: Bin Meng 

Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 18 +-
 hw/riscv/virt.c | 24 
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0d9ff76a4f..762223c6fe 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -183,7 +183,7 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
-qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -208,20 +208,20 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 0x0, memmap[SIFIVE_U_GEM].size);
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 ethclk_phandle, ethclk_phandle, ethclk_phandle);
 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 sizeof(ethclk_names));
-qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
-qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
+qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 g_free(nodename);
 
 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
 uartclk_phandle = phandle++;
@@ -241,9 +241,9 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_UART0].base,
 0x0, memmap[SIFIVE_U_UART0].size);
-qemu_fdt_setprop_cells(fdt, nodename, "clocks", uartclk_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
+qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 
 qemu_fdt_add_subnode(fdt, "/chosen");
 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 78091707dc..6852178bc2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 (long)memmap[VIRT_PLIC].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
-   FDT_PLIC_ADDR_CELLS);
+qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
+  FDT_PLIC_ADDR_CELLS);
 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
   FDT_PLIC_INT_CELLS);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
-qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 0x0, memmap[VIRT_VIRTIO].size);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", 
plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
+

[Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images

[Palmer Dabbelt]

From: Bin Meng 

Like other binary files, the executable attribute of opensbi images
should not be set.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
 pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin
 3 files changed, 0 insertions(+), 0 deletions(-)
 mode change 100755 => 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
 mode change 100755 => 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
 mode change 100755 => 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin

diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin 
b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin 
b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin 
b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
old mode 100755
new mode 100644
-- 
2.21.0

[Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array

[Palmer Dabbelt]

From: Bin Meng 

At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.

Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/riscv_hart.c | 3 ++-
 include/hw/riscv/riscv_hart.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 6620e41cb7..5b98227db6 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -29,6 +29,7 @@
 
 static Property riscv_harts_props[] = {
 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
 DEFINE_PROP_END_OF_LIST(),
 };
@@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int 
idx,
 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
 sizeof(RISCVCPU), cpu_type,
 &error_abort, NULL);
-s->harts[idx].env.mhartid = idx;
+s->harts[idx].env.mhartid = s->hartid_base + idx;
 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
 object_property_set_bool(OBJECT(&s->harts[idx]), true,
  "realized", &err);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 3b52b50571..c75856fa73 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
 
 /*< public >*/
 uint32_t num_harts;
+uint32_t hartid_base;
 char *cpu_type;
 RISCVCPU *harts;
 } RISCVHartArrayState;
-- 
2.21.0

[Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate()

[Palmer Dabbelt]

From: Bin Meng 

Use create_unimplemented_device() instead.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/Kconfig|  1 +
 hw/riscv/sifive_e.c | 23 ---
 2 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8674211085..33e54b031d 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -12,6 +12,7 @@ config SIFIVE_E
 bool
 select HART
 select SIFIVE
+select UNIMP
 
 config SIFIVE_U
 bool
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1428a99fce..0f9d641a0e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -36,6 +36,7 @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
@@ -74,14 +75,6 @@ static const struct MemmapEntry {
 [SIFIVE_E_DTIM] = { 0x8000, 0x4000 }
 };
 
-static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
- uintptr_t offset, uintptr_t length)
-{
-MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
-memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
-memory_region_add_subregion(parent, offset, mock_mmio);
-}
-
 static void riscv_sifive_e_init(MachineState *machine)
 {
 const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -172,7 +165,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, 
Error **errp)
 sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
+create_unimplemented_device("riscv.sifive.e.aon",
 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
 sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
 
@@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, 
Error **errp)
 
 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
+create_unimplemented_device("riscv.sifive.e.qspi0",
 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
+create_unimplemented_device("riscv.sifive.e.pwm0",
 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
+create_unimplemented_device("riscv.sifive.e.qspi1",
 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
+create_unimplemented_device("riscv.sifive.e.pwm1",
 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
+create_unimplemented_device("riscv.sifive.e.qspi2",
 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
-sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
+create_unimplemented_device("riscv.sifive.e.pwm2",
 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
 
 /* Flash memory */
-- 
2.21.0

[Qemu-devel] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header

[Palmer Dabbelt]

From: Bin Meng 

sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 32d8cee335..2947e06f71 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -38,7 +38,6 @@
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
-- 
2.21.0

[Qemu-devel] [PULL 18/47] riscv: hw: Change create_fdt() to return void

[Palmer Dabbelt]

From: Bin Meng 

There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 11 ---
 hw/riscv/virt.c | 11 ---
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e8acdd9b12..32d8cee335 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -67,7 +67,7 @@ static const struct MemmapEntry {
 
 #define GEM_REVISION0x10070109
 
-static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
+static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 uint64_t mem_size, const char *cmdline)
 {
 void *fdt;
@@ -253,14 +253,11 @@ static void *create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 
 g_free(nodename);
-
-return fdt;
 }
 
 static void riscv_sifive_u_init(MachineState *machine)
 {
 const struct MemmapEntry *memmap = sifive_u_memmap;
-void *fdt;
 
 SiFiveUState *s = g_new0(SiFiveUState, 1);
 MemoryRegion *system_memory = get_system_memory();
@@ -281,7 +278,7 @@ static void riscv_sifive_u_init(MachineState *machine)
 main_mem);
 
 /* create device tree */
-fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
  memmap[SIFIVE_U_DRAM].base);
@@ -294,9 +291,9 @@ static void riscv_sifive_u_init(MachineState *machine)
 hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
-qemu_fdt_setprop_cell(fdt, "/chosen",
+qemu_fdt_setprop_cell(s->fdt, "/chosen",
   "linux,initrd-start", start);
-qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
   end);
 }
 }
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 090512be13..d36f5625ec 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
0x1800, 0, 0, 0x7);
 }
 
-static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
+static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 uint64_t mem_size, const char *cmdline)
 {
 void *fdt;
@@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 }
 g_free(nodename);
-
-return fdt;
 }
 
 
@@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine)
 size_t plic_hart_config_len;
 int i;
 unsigned int smp_cpus = machine->smp.cpus;
-void *fdt;
 
 /* Initialize SOC */
 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine)
 main_mem);
 
 /* create device tree */
-fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
 /* boot rom */
 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
@@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine)
 hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
-qemu_fdt_setprop_cell(fdt, "/chosen",
+qemu_fdt_setprop_cell(s->fdt, "/chosen",
   "linux,initrd-start", start);
-qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
   end);
 }
 }
-- 
2.21.0

[Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2

[Palmer Dabbelt]

From: Bin Meng 

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 4 +++-
 include/hw/riscv/sifive_u.h | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2947e06f71..2023b71d53 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,7 +10,8 @@
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  *
- * This board currently uses a hardcoded devicetree that indicates one hart.
+ * This board currently generates devicetree dynamically that indicates at 
least
+ * two harts.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -433,6 +434,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
  * management CPU.
  */
 mc->max_cpus = 4;
+mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index f25bad8f13..6d227410f8 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@ enum {
 SIFIVE_U_GEM_CLOCK_FREQ = 12500
 };
 
+#define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
+
 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
 #define SIFIVE_U_PLIC_NUM_SOURCES 54
 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
-- 
2.21.0

[Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

[Palmer Dabbelt]

From: Bin Meng 

Group SiFive E and U cpu type defines into one header file.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Palmer Dabbelt 
---
 include/hw/riscv/sifive_cpu.h | 31 +++
 include/hw/riscv/sifive_e.h   |  7 +--
 include/hw/riscv/sifive_u.h   |  7 +--
 3 files changed, 33 insertions(+), 12 deletions(-)
 create mode 100644 include/hw/riscv/sifive_cpu.h

diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
new file mode 100644
index 00..136799633a
--- /dev/null
+++ b/include/hw/riscv/sifive_cpu.h
@@ -0,0 +1,31 @@
+/*
+ * SiFive CPU types
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef HW_SIFIVE_CPU_H
+#define HW_SIFIVE_CPU_H
+
+#if defined(TARGET_RISCV32)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
+#elif defined(TARGET_RISCV64)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#endif
+
+#endif /* HW_SIFIVE_CPU_H */
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 9c868dd7f9..25ce7aa9d5 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -20,6 +20,7 @@
 #define HW_SIFIVE_E_H
 
 #include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
@@ -84,10 +85,4 @@ enum {
 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x20
 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
 
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#endif
-
 #endif
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index be021ce256..f25bad8f13 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -21,6 +21,7 @@
 
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_cpu.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -78,10 +79,4 @@ enum {
 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x20
 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
 
-#if defined(TARGET_RISCV32)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
 #endif
-- 
2.21.0

[Qemu-devel] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

[Palmer Dabbelt]

From: Bin Meng 

Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/Makefile.objs  |  2 +-
 hw/riscv/sifive_e.c |  4 +-
 hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++---
 include/hw/riscv/sifive_e_prci.h| 69 ++
 include/hw/riscv/sifive_prci.h  | 71 --
 5 files changed, 111 insertions(+), 114 deletions(-)
 rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (51%)
 create mode 100644 include/hw/riscv/sifive_e_prci.h
 delete mode 100644 include/hw/riscv/sifive_prci.h

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index eb9d4f9ffc..c8596977a8 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -2,9 +2,9 @@ obj-y += boot.o
 obj-$(CONFIG_SPIKE) += riscv_htif.o
 obj-$(CONFIG_HART) += riscv_hart.o
 obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_clint.o
 obj-$(CONFIG_SIFIVE) += sifive_gpio.o
-obj-$(CONFIG_SIFIVE) += sifive_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 792d75a1a3..1428a99fce 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,9 +40,9 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_clint.h"
-#include "hw/riscv/sifive_prci.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
+#include "hw/riscv/sifive_e_prci.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
@@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, 
Error **errp)
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
-sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
+sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
 
 /* GPIO */
 
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c
similarity index 51%
rename from hw/riscv/sifive_prci.c
rename to hw/riscv/sifive_e_prci.c
index c413f0cb76..b6d32db935 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -1,5 +1,5 @@
 /*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
  *
  * Copyright (c) 2017 SiFive, Inc.
  *
@@ -23,19 +23,19 @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_prci.h"
+#include "hw/riscv/sifive_e_prci.h"
 
-static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int 
size)
 {
-SiFivePRCIState *s = opaque;
+SiFiveEPRCIState *s = opaque;
 switch (addr) {
-case SIFIVE_PRCI_HFROSCCFG:
+case SIFIVE_E_PRCI_HFROSCCFG:
 return s->hfrosccfg;
-case SIFIVE_PRCI_HFXOSCCFG:
+case SIFIVE_E_PRCI_HFXOSCCFG:
 return s->hfxosccfg;
-case SIFIVE_PRCI_PLLCFG:
+case SIFIVE_E_PRCI_PLLCFG:
 return s->pllcfg;
-case SIFIVE_PRCI_PLLOUTDIV:
+case SIFIVE_E_PRCI_PLLOUTDIV:
 return s->plloutdiv;
 }
 qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
@@ -43,27 +43,27 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, 
unsigned int size)
 return 0;
 }
 
-static void sifive_prci_write(void *opaque, hwaddr addr,
-   uint64_t val64, unsigned int size)
+static void sifive_e_prci_write(void *opaque, hwaddr addr,
+uint64_t val64, unsigned int size)
 {
-SiFivePRCIState *s = opaque;
+SiFiveEPRCIState *s = opaque;
 switch (addr) {
-case SIFIVE_PRCI_HFROSCCFG:
+case SIFIVE_E_PRCI_HFROSCCFG:
 s->hfrosccfg = (uint32_t) val64;
 /* OSC stays ready */
-s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
+s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
 break;
-case SIFIVE_PRCI_HFXOSCCFG:
+case SIFIVE_E_PRCI_HFXOSCCFG:
 s->hfxosccfg = (uint32_t) val64;
 /* OSC stays ready */
-s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
+s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
 break;
-case SIFIVE_PRCI_PLLCFG:
+case SIFIVE_E_PRCI_PLLCFG:
 s->pllcfg = (uint32_t) val64;
 /* PLL stays locked */
-s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
+s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
 break;
-case SIFIVE_PRCI_PLLOUTDIV:
+case SIFIVE_E_PRCI_PLLOUTDIV:
 s->

[Qemu-devel] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

[Palmer Dabbelt]

From: Bin Meng 

For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.

Signed-off-by: Bin Meng 
Acked-by: Alistair Francis 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_e_prci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index b6d32db935..bfe9b13a67 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -91,7 +91,7 @@ static void sifive_e_prci_init(Object *obj)
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 
 s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
-s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN);
 s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
  SIFIVE_E_PRCI_PLLCFG_LOCK);
 s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
-- 
2.21.0

[Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes

[Palmer Dabbelt]

From: Bin Meng 

Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c  |  7 ---
 include/hw/riscv/sifive_u_prci.h | 10 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ff2e28e26c..ea21095513 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -78,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 int cpu;
 uint32_t *cells;
 char *nodename;
-char ethclk_names[] = "pclk\0hclk\0tx_clk";
+char ethclk_names[] = "pclk\0hclk";
 uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
 uint32_t uartclk_phandle;
 uint32_t hfclk_phandle, rtcclk_phandle;
@@ -263,7 +263,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
-ethclk_phandle, ethclk_phandle, ethclk_phandle);
+prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 sizeof(ethclk_names));
 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
@@ -293,7 +293,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_UART0].base,
 0x0, memmap[SIFIVE_U_UART0].size);
-qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+prci_phandle, PRCI_CLK_TLCLK);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
index 60a2eab0e9..0a531fdadc 100644
--- a/include/hw/riscv/sifive_u_prci.h
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState {
 uint32_t clkmuxstatus;
 } SiFiveUPRCIState;
 
+/*
+ * Clock indexes for use by Device Tree data and the PRCI driver.
+ *
+ * These values are from sifive-fu540-prci.h in the Linux kernel.
+ */
+#define PRCI_CLK_COREPLL0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL  2
+#define PRCI_CLK_TLCLK  3
+
 #endif /* HW_SIFIVE_U_PRCI_H */
-- 
2.21.0

[Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string

[Palmer Dabbelt]

From: Bin Meng 

With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.

Suggested-by: Fabien Chouteau 
Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6c4634dcac..713c451e85 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -424,10 +424,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 plic_hart_config = g_malloc0(plic_hart_config_len);
 for (i = 0; i < ms->smp.cpus; i++) {
 if (i != 0) {
-strncat(plic_hart_config, ",", plic_hart_config_len);
+strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
+plic_hart_config_len);
+} else {
+strncat(plic_hart_config, "M", plic_hart_config_len);
 }
-strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
-plic_hart_config_len);
 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 }
 
-- 
2.21.0

[Qemu-devel] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size

[Palmer Dabbelt]

From: Bin Meng 

Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_e_prci.c | 2 +-
 include/hw/riscv/sifive_e_prci.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index bfe9b13a67..a1c0d44f18 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -87,7 +87,7 @@ static void sifive_e_prci_init(Object *obj)
 SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
 
 memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
-  TYPE_SIFIVE_E_PRCI, 0x8000);
+  TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 
 s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
index c4b76aa17a..698b0b451c 100644
--- a/include/hw/riscv/sifive_e_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -47,6 +47,8 @@ enum {
 SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
 };
 
+#define SIFIVE_E_PRCI_REG_SIZE  0x1000
+
 #define TYPE_SIFIVE_E_PRCI  "riscv.sifive.e.prci"
 
 #define SIFIVE_E_PRCI(obj) \
-- 
2.21.0

[Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine

[Palmer Dabbelt]

From: Bin Meng 

Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.

Note the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/riscv_hart.c | 33 -
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index d0f3199968..6620e41cb7 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2017 SiFive, Inc.
  *
- * Holds the state of a heterogenous array of RISC-V harts
+ * Holds the state of a homogeneous array of RISC-V harts
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -39,26 +39,33 @@ static void riscv_harts_cpu_reset(void *opaque)
 cpu_reset(CPU(cpu));
 }
 
+static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
+   char *cpu_type, Error **errp)
+{
+Error *err = NULL;
+
+object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
+sizeof(RISCVCPU), cpu_type,
+&error_abort, NULL);
+s->harts[idx].env.mhartid = idx;
+qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
+object_property_set_bool(OBJECT(&s->harts[idx]), true,
+ "realized", &err);
+if (err) {
+error_propagate(errp, err);
+return;
+}
+}
+
 static void riscv_harts_realize(DeviceState *dev, Error **errp)
 {
 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
-Error *err = NULL;
 int n;
 
 s->harts = g_new0(RISCVCPU, s->num_harts);
 
 for (n = 0; n < s->num_harts; n++) {
-object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
-sizeof(RISCVCPU), s->cpu_type,
-&error_abort, NULL);
-s->harts[n].env.mhartid = n;
-qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
-object_property_set_bool(OBJECT(&s->harts[n]), true,
- "realized", &err);
-if (err) {
-error_propagate(errp, err);
-return;
-}
+riscv_hart_realize(s, n, s->cpu_type, errp);
 }
 }
 
-- 
2.21.0

[Qemu-devel] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet

[Palmer Dabbelt]

From: Bin Meng 

In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 24 +---
 include/hw/riscv/sifive_u.h |  3 +--
 2 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3b61fab42c..507a6e2fa9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -87,8 +87,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 uint32_t *cells;
 char *nodename;
 char ethclk_names[] = "pclk\0hclk";
-uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
-uint32_t uartclk_phandle;
+uint32_t plic_phandle, prci_phandle, phandle = 1;
 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 
 fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -248,17 +247,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(cells);
 g_free(nodename);
 
-ethclk_phandle = phandle++;
-nodename = g_strdup_printf("/soc/ethclk");
-qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
-qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
-qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-SIFIVE_U_GEM_CLOCK_FREQ);
-qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
-ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
-g_free(nodename);
-
 phy_phandle = phandle++;
 nodename = g_strdup_printf("/soc/ethernet@%lx",
 (long)memmap[SIFIVE_U_GEM].base);
@@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
-uartclk_phandle = phandle++;
-nodename = g_strdup_printf("/soc/uartclk");
-qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
-qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
-qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
-qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
-uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
-g_free(nodename);
-
 nodename = g_strdup_printf("/soc/serial@%lx",
 (long)memmap[SIFIVE_U_UART0].base);
 qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5270851aa2..e4df298c23 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -77,8 +77,7 @@ enum {
 enum {
 SIFIVE_U_CLOCK_FREQ = 10,
 SIFIVE_U_HFCLK_FREQ = ,
-SIFIVE_U_RTCCLK_FREQ = 100,
-SIFIVE_U_GEM_CLOCK_FREQ = 12500
+SIFIVE_U_RTCCLK_FREQ = 100
 };
 
 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
-- 
2.21.0

[Qemu-devel] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP

[Palmer Dabbelt]

From: Bin Meng 

This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/Makefile.objs  |   1 +
 hw/riscv/sifive_u_otp.c | 191 
 include/hw/riscv/sifive_u_otp.h |  80 +
 3 files changed, 272 insertions(+)
 create mode 100644 hw/riscv/sifive_u_otp.c
 create mode 100644 include/hw/riscv/sifive_u_otp.h

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index b95bbd51e2..fc3c6dd7c8 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_uart.o
 obj-$(CONFIG_SPIKE) += spike.o
diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c
new file mode 100644
index 00..ea0eee5678
--- /dev/null
+++ b/hw/riscv/sifive_u_otp.c
@@ -0,0 +1,191 @@
+/*
+ * QEMU SiFive U OTP (One-Time Programmable) Memory interface
+ *
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * Simple model of the OTP to emulate register reads made by the SDK BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/riscv/sifive_u_otp.h"
+
+static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
+{
+SiFiveUOTPState *s = opaque;
+
+switch (addr) {
+case SIFIVE_U_OTP_PA:
+return s->pa;
+case SIFIVE_U_OTP_PAIO:
+return s->paio;
+case SIFIVE_U_OTP_PAS:
+return s->pas;
+case SIFIVE_U_OTP_PCE:
+return s->pce;
+case SIFIVE_U_OTP_PCLK:
+return s->pclk;
+case SIFIVE_U_OTP_PDIN:
+return s->pdin;
+case SIFIVE_U_OTP_PDOUT:
+if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
+(s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
+(s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
+return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
+} else {
+return 0xff;
+}
+case SIFIVE_U_OTP_PDSTB:
+return s->pdstb;
+case SIFIVE_U_OTP_PPROG:
+return s->pprog;
+case SIFIVE_U_OTP_PTC:
+return s->ptc;
+case SIFIVE_U_OTP_PTM:
+return s->ptm;
+case SIFIVE_U_OTP_PTM_REP:
+return s->ptm_rep;
+case SIFIVE_U_OTP_PTR:
+return s->ptr;
+case SIFIVE_U_OTP_PTRIM:
+return s->ptrim;
+case SIFIVE_U_OTP_PWE:
+return s->pwe;
+}
+
+qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+  __func__, addr);
+return 0;
+}
+
+static void sifive_u_otp_write(void *opaque, hwaddr addr,
+   uint64_t val64, unsigned int size)
+{
+SiFiveUOTPState *s = opaque;
+uint32_t val32 = (uint32_t)val64;
+
+switch (addr) {
+case SIFIVE_U_OTP_PA:
+s->pa = val32 & SIFIVE_U_OTP_PA_MASK;
+break;
+case SIFIVE_U_OTP_PAIO:
+s->paio = val32;
+break;
+case SIFIVE_U_OTP_PAS:
+s->pas = val32;
+break;
+case SIFIVE_U_OTP_PCE:
+s->pce = val32;
+break;
+case SIFIVE_U_OTP_PCLK:
+s->pclk = val32;
+break;
+case SIFIVE_U_OTP_PDIN:
+s->pdin = val32;
+break;
+case SIFIVE_U_OTP_PDOUT:
+/* read-only */
+break;
+case SIFIVE_U_OTP_PDSTB:
+s->pdstb = val32;
+break;
+case SIFIVE_U_OTP_PPROG:
+s->pprog = val32;
+break;
+case SIFIVE_U_OTP_PTC:
+s->ptc = val32;
+break;
+case SIFIVE_U_OTP_PTM:
+s->ptm = val32;
+break;
+case SIFIVE_U_OTP_PTM_REP:
+s->ptm_rep = val32;
+break;
+case SIFIVE_U_OTP_PTR:
+s->ptr = val32;
+break;
+case SIFIVE_U_OTP_PTRIM:
+s->ptrim = val32;
+break;
+case SIFIVE_U_OTP_PWE:
+s->pwe = val32;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+

[Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

[Palmer Dabbelt]

From: Bin Meng 

The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.

The cpu nodes in the generated DTS have been updated as well.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 92 +++--
 include/hw/riscv/sifive_u.h |  6 ++-
 2 files changed, 72 insertions(+), 26 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2023b71d53..6c4634dcac 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -11,7 +11,7 @@
  * 2) PLIC (Platform Level Interrupt Controller)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
- * two harts.
+ * two harts and up to five harts.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -34,6 +34,7 @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
+#include "hw/cpu/cluster.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
@@ -70,6 +71,7 @@ static const struct MemmapEntry {
 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 uint64_t mem_size, const char *cmdline)
 {
+MachineState *ms = MACHINE(qdev_get_machine());
 void *fdt;
 int cpu;
 uint32_t *cells;
@@ -110,15 +112,21 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 
-for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
+for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 int cpu_phandle = phandle++;
 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
+char *isa;
 qemu_fdt_add_subnode(fdt, nodename);
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
   SIFIVE_U_CLOCK_FREQ);
-qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+/* cpu 0 is the management hart that does not have mmu */
+if (cpu != 0) {
+qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
+} else {
+isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
+}
 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
@@ -134,8 +142,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(nodename);
 }
 
-cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
-for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
+cells =  g_new0(uint32_t, ms->smp.cpus * 4);
+for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 nodename =
 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -153,20 +161,26 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 0x0, memmap[SIFIVE_U_CLINT].base,
 0x0, memmap[SIFIVE_U_CLINT].size);
 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
+cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 g_free(cells);
 g_free(nodename);
 
 plic_phandle = phandle++;
-cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
-for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
+cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
+for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 nodename =
 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
-cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
-cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
-cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
-cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+/* cpu 0 is the management hart that does not have S-mode */
+if (cpu == 0) {
+cells[0] = cpu_to_be32(intc_phandle);
+cells[1] = cpu_to_be32(IRQ_M_EXT);
+} else {
+cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
+cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
+cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+cells[cpu * 4 + 1] = cpu_to_be32(

[Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC

[Palmer Dabbelt]

From: Bin Meng 

Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 24 +++-
 include/hw/riscv/sifive_u.h |  3 +++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3ee6fcbd12..ff2e28e26c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -9,6 +9,7 @@
  * 0) UART
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
+ * 3) PRCI (Power, Reset, Clock, Interrupt)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -60,6 +61,7 @@ static const struct MemmapEntry {
 [SIFIVE_U_MROM] = { 0x1000,0x11000 },
 [SIFIVE_U_CLINT] ={  0x200,0x1 },
 [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
+[SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
 [SIFIVE_U_UART0] ={ 0x10013000, 0x1000 },
 [SIFIVE_U_UART1] ={ 0x10023000, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
@@ -77,7 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 uint32_t *cells;
 char *nodename;
 char ethclk_names[] = "pclk\0hclk\0tx_clk";
-uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
 uint32_t uartclk_phandle;
 uint32_t hfclk_phandle, rtcclk_phandle;
 
@@ -188,6 +190,21 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(cells);
 g_free(nodename);
 
+prci_phandle = phandle++;
+nodename = g_strdup_printf("/soc/clock-controller@%lx",
+(long)memmap[SIFIVE_U_PRCI].base);
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+hfclk_phandle, rtcclk_phandle);
+qemu_fdt_setprop_cells(fdt, nodename, "reg",
+0x0, memmap[SIFIVE_U_PRCI].base,
+0x0, memmap[SIFIVE_U_PRCI].size);
+qemu_fdt_setprop_string(fdt, nodename, "compatible",
+"sifive,fu540-c000-prci");
+g_free(nodename);
+
 plic_phandle = phandle++;
 cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
@@ -402,6 +419,8 @@ static void riscv_sifive_u_soc_init(Object *obj)
 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 
+sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
+  TYPE_SIFIVE_U_PRCI);
 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
   TYPE_CADENCE_GEM);
 }
@@ -475,6 +494,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 
+object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+
 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 }
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 24418145aa..bb46745356 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -22,6 +22,7 @@
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
+#include "hw/riscv/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -37,6 +38,7 @@ typedef struct SiFiveUSoCState {
 RISCVHartArrayState e_cpus;
 RISCVHartArrayState u_cpus;
 DeviceState *plic;
+SiFiveUPRCIState prci;
 CadenceGEMState gem;
 } SiFiveUSoCState;
 
@@ -55,6 +57,7 @@ enum {
 SIFIVE_U_MROM,
 SIFIVE_U_CLINT,
 SIFIVE_U_PLIC,
+SIFIVE_U_PRCI,
 SIFIVE_U_UART0,
 SIFIVE_U_UART1,
 SIFIVE_U_DRAM,
-- 
2.21.0

[Qemu-devel] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree

[Palmer Dabbelt]

From: Bin Meng 

This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 507a6e2fa9..ca9f7fea41 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -96,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 exit(1);
 }
 
-qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
-qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
+qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
+qemu_fdt_setprop_string(fdt, "/", "compatible",
+"sifive,hifive-unleashed-a00");
 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 
-- 
2.21.0

[Qemu-devel] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine

[Palmer Dabbelt]

From: Bin Meng 

With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 40968 -> 45064 bytes
 roms/Makefile|   4 ++--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin 
b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
index 
5d7a1ef6818994bac4a36818ad36043b592ce309..eb22aefdfb468cfe2804cb4b0bc422d8ebcae93b
 100644
GIT binary patch
delta 10830
zcmcI~eOOf0_WwTTaAp|5zy=s$G)G2;B$Y8xQwsqZMktj?Fen8a(7-p07sHnZ7-n!l
zMBCydW6I@gkn_7&ttq)_3KlO(VPJ-_F<-9NtbxZHEj
z{_M5aUTf{O*51R;dU|IYeF9VCYY-ChyTdf=_$;$t$%-!FBh)PF2YiLnP&GJ#RtlO4
zf`7%(Y&Ovh1uu^=BI*)uVqWvTi1HA8ri}M#lXXVj799nsK;XrsM6yhpfDIJrX~XyC
z2!|6CowN*ZcY7WO@m?9<2q^Y_gGC}=pjE1PeV*?)24lA+F1Veyny!q&5qy)IT&z**
z9rPutBL0(>5I47X9AAARDRjwiGOa}(Juz}vMdK*G692<-3vK0Nnc&)lwu}o}=nauO
zcZ?TY@G#q+qP_71r*$d=x5^cU{Rm;*npek1)(iPIr(~VJW~mN-36_!SG&$4uS~~N
zonLU~df7CKT(SnQcb*l>JuB8)tVcB(J|0hh;{4>3FrF7NUbBFQV#_`kT`g;OzrM@A#ALL{
zFTU_?J&qa|jALA1rVijEu5Z$42A<$HLllzdOpW)s4KC2e>p^Za^`^qUJBC{Py4!EA
zutuzHbf2QIpb(0@8y_(H6QcRl+ZIXQ6a)AlE~>f3d6UUogxm|
z*kzH_OU(7-Ptx?B#rQ4vb~<{#`E`#i4&aR6drkM2ziH&Nh*hXk`_T9gC`6$aZcQh)
zV{dOMfP%ff7aUy+I6J_`D7soZ)`!j_sahQuzb>@g*xD?yR~LRZ00n1kc|r)?_U(B6Tyr^792v7v?!|R
zf-X*H>-Ak>>vO=8IlS+h~Y>Fke_l-#wN!wf;{Zxr>5mD#b1Oqq6nuJjfiZDAe
z9+1=DnQRAk$Jl_kV#a`T?ZBk~oPtk`As5?`i^q`D?Z`!d^u$S$QJ%qeWbhbriXHhJ
zAf2(>lu=}m9T_x+^t2;q021N)F{Hm8=|6^awj+HkZq{s^;WNrpVn<5GkjRb{0Wuv+
zq@zerJJNFu*=I+(05TC@97DR;kuGD%yLKc6$mKY1>L^dzj-IBGR@o5jR~9$w0|D(-07zoZw)HjrO(kIKH(9^=JO?UhKu_4FYHvMB-U9Ol5;Tb}yi`Px~pI?{-$hQJQaxrTZ@pusP*TeGUMh6zDgaSIhCttB64&r3AWZUC0
zLcHG{g7y88>$M&cn2ly&X0?kY`UHRT@UV5Dc67>GK61lF&Gf-Vu1MmjFVS|?rnXMP
zS~hy~8X=D-nafgcAga@-Ahnk(7C>)hYpvH!N>PxPz1im`ud8~frT;?jCF_-*Yqx*y
zY;RjLl-|Fw7YY9Dhk}?!5ydp~DNUo=k7AnUQko_u<-=+kR#5S!pR-K!TIzi1Y97f
zbiRV)XkFOKPU~<>8)TZo5!1XJX_~T-ra1+PJ#~~=#HZqSt7CT?4Mk|>ZZVJNR!#Ci
zv_z~@uslOHNT_8Khyd34{(2ES3t4SEOns6}*`hUY{yKdr&ke3CJ1*CHy{B-^+yxVgj4h;RA
zzZQn^o5RdQp^GV6jd8@HIQn=cKD1~TeWMId4}ZyFVcu__;F;mU_*A$Hy=)MF8Gesm
z)`S14*h)`s#nrKMaC(F%?Rpv)L`(ex{FqhxaI3XiF1*eQ_LJ_67cU@tgFr
z&+yZc-2rK^X8qAGM9>NaM|XljU<~BJfrF~O%|0o?<&McD0{Em*3VS4gI6(N~BEJVXXIY&uXEeoK
zOWUTyB6tr4?;UrQR%tdE(B(3lr=;G-3DJ|L+01*((zeWKLw0wLB60JBkv=<`?ZlPQ
zVljvAx@l>1HQ45>X|r*AzYSlBe(+*0$e@q>#*hVVVfZ)Tac#@Anpy#pY0ce!6q!Lf
z|H0Rmwr{kVDBA7c{vkmG?=N`1+2{9kKa{L7KBG`>WXXiTek1?JU9ngub
zuN)A{qbI8-v2J)E7l~GoH7X_e;PTf%XEX7`<-K%31GdIy^PvlzmBs7h-k`tv#C#>L
zfTqhzaYFngkGTj18@lPWlD*J3eaQ
zjKSXH*Nxp@*96+1);^NTk37_W5+B=l2BIV}2e>FMDv}*sqbZh3v0
zhwZx$^bQR;7*dG33MJTarAo#1bbJ4KT=Rs3D%vAAKe#+!Iq{s&A5ws&E%A(vd$;Gi
zs!3mofQOJ@<2hjwDI_U{>QOf*f$hDYJHD`TN<3hsAJ#lc#z{Y|apT&5)Vlq_rEIc{
z+o^I){_~9LkI4vJ#2xTIu0aB_s7PV^*1P^9tvre%YcXr3
z!JX?}AK;LT8H{Alvp6HegOMX=yfb4KQ|~&AKg$SU>c1Jr_cHvL`m&$!gw4|c_ZAM{
zEQK}~r*D3bsSmh~o!-2|)E_@X%g-;b0}?Hw=p)
zga~=n?c5o`s%{_O$oMr3?^UYk2M!``MCwhzzxPMHtPM}h-oZ#N&cg?@0~txi9DFHz
z79a3ftGI-na$*@t(kpm%&O8ve3LnY|1#u7I_MF9Z;vk;BWjd|y#|c|rU?gn|amAKb
zKzMg--4a8qhjI8@DtJ8;o8DT$NZeR_`>h-BJQ26#PMIR9%rX_KUSrXnx@s*IK@M_x
znWn;y2zF?x)^Z}T6}xQpp>K3y`PM0nB*Yyr-wM*TrQ_nQbAm?B83k~fEcQaGi$M(g
z0gOJ8cq35Y8#)|xx^QZ!SF2FqfmB}yQBa-fAPb*3d=>X@okJ&{#?!YwOW!z!leWb?
zb>kzuE(T?gmVt?NS>KHFrb0;9CnkT0FK+XZ9R84`Q0dIhhvuSAq}nt@w9Rsm^tR2NC}O@*eSju7_Ij)Ym2P$bU7RXY@n+lh7f?v9nh
zd0-yBAWFy!AH2pL36q34;q5on{zV$42gN8@idhV`QiLBR_RvyB1D`ryX71)w#{D{o
z`}uxCHiK5}=%Y0eMTl8!K$^w1h*8ua=%>UJ94YfH9vO+uw>+uyyYppd-h)%nYXbWPLYZ0I+ak(QAlH;+>EZQc13jNSmr(f0^WnJ16b33jx5A2~)!ZuUDcKb32&L~r1!`PH=
z+iFA$SIds+ak-jL=kKj97i#si*hxp9EVi6*{RxgvPfI@-026{an~6EWjLk>Dn_!p1
zHo97Rxzx6O3Ow@n#_6id1GSNq<;12RjYUpKc%=v|Rg7Zv;>+NDuNG5cVr|c2idc!*
z=A1^D;Kc1?*p)05Stj=6QNpbcUGakluC2RYE)#nflO2Zw??zBp%cMslDQVRJt!ZpP
z4DqTa2QZPl%{1Ututr+bJeB6w2;v#{^Wfk`PA9RPy+?QZ)zZK5AA`0IpD}T9+;0XWNGC-@r4${g2x;-N-t164m
zZBGkJuS%Z+R*m0WWv%YH(0QpXZfLbt*V}SCp?_8Hnx6FA8$0tRm>H|za(4M^zL7tzz1*mqhpNke
ztB{^Jg+7!~Bxw
zVhOhmx?U|4i%U@8FKa2`4|-US9@MI*q(|0pczjjx7#tgPuMk3r}-MxLR<@6P16Lf2ChYH%QW^v
zpyPqfJCX6=F3Q~VHRL0(H)ze=viW;V`!4O%Mu38~z9j>~AN3H3^ho%f
zp24r`8KD8_ih#l*c#acrsY6X-63Mq=6G(>r+=Ij?vQtT}_3;#cr>BHJ3h36dDo^99
zdJ4x1=$FebmkF=vX&k4gX(7o!1rtWOtajwaUllNfTRTfQ!ERy*w=f=Y%GR>adBWTQ
z*O$wx1eeQv)B2zCk_vt5*oi`-wCDA>hEf4wYkLfkx
zETxHp2p{E3F)z-hAOqj@I{(KwLa!r{1kBTRyhnBQC~WdV%2)xRw<{JXl@fcai;=lY
zK^1tsBgo%-0S+K+L`ylb=Sbelx*f4g>Q-*9YLg8`^)Ky>vFbYGdh#6o^)rj1e6-%U
zW-9bLU!BB*+nTW4_N=O0dTV=nGE8_$E95l{l4%2a{EH`@hoZT%?j|E^7&P(}=(mdT
zvdtBy;(Qq;yQJny+mRwup<-C9^F|kl^(qhlYeTJOYQtb`?WE0Bx2rps4#o7x^(I(X
z_2_z9+Vb2?`eVh!jB#Lp
zs35?G5ZAdt1h#`fSd*DuI1~j(0!w9L+n@U$H&$Fv!fjnAF&EL*oZ?f&WOb%Os`YV`;cK~0YEaT3
zk&;;KhEDqYk%zMzK}mx|D^c17f;kjXl}%GbOBU<#9#f&1FF=Zc-$Rq03e^Y)?z=+3
z_JYj?S|hh9woJ&(EgS^B3@+8Z{sri4@RIgJesH;^^2T>(YK3Zk;ot>MO~mmQ?ll!o
z8-`T^_>y)O3*PYUQKBllrg%f7zTr+V*25oBk9j=N4(2rsErok;a$ytj&;xAUFl5r^
zM~nlPlWAvx=&m<^-y@tpebo&^e|$Bn#u#f{kFIlRZ^G?7M{dgEIpA=K|Ig<2?O9>D
zHlGh$mrT4Kemk;H+@gwOoxskM`i96(;NH6B

[Qemu-devel] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs

[Palmer Dabbelt]

From: Bin Meng 

This updates the UART base address and IRQs to match the hardware.

Signed-off-by: Bin Meng 
Reviewed-by: Jonathan Behrens 
Acked-by: Alistair Francis 
Reviewed-by: Chih-Min Chao 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 4 ++--
 include/hw/riscv/sifive_u.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ea21095513..a3ee1ec0a9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -62,8 +62,8 @@ static const struct MemmapEntry {
 [SIFIVE_U_CLINT] ={  0x200,0x1 },
 [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
 [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
-[SIFIVE_U_UART0] ={ 0x10013000, 0x1000 },
-[SIFIVE_U_UART1] ={ 0x10023000, 0x1000 },
+[SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
+[SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
 [SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
 };
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index bb46745356..7dfd1cb22e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -65,8 +65,8 @@ enum {
 };
 
 enum {
-SIFIVE_U_UART0_IRQ = 3,
-SIFIVE_U_UART1_IRQ = 4,
+SIFIVE_U_UART0_IRQ = 4,
+SIFIVE_U_UART1_IRQ = 5,
 SIFIVE_U_GEM_IRQ = 0x35
 };
 
-- 
2.21.0

[Qemu-devel] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes

[Palmer Dabbelt]

From: Bin Meng 

To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 23 +++
 include/hw/riscv/sifive_u.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 713c451e85..3ee6fcbd12 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 char ethclk_names[] = "pclk\0hclk\0tx_clk";
 uint32_t plic_phandle, ethclk_phandle, phandle = 1;
 uint32_t uartclk_phandle;
+uint32_t hfclk_phandle, rtcclk_phandle;
 
 fdt = s->fdt = create_device_tree(&s->fdt_size);
 if (!fdt) {
@@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
+hfclk_phandle = phandle++;
+nodename = g_strdup_printf("/hfclk");
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+SIFIVE_U_HFCLK_FREQ);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+g_free(nodename);
+
+rtcclk_phandle = phandle++;
+nodename = g_strdup_printf("/rtcclk");
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+SIFIVE_U_RTCCLK_FREQ);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+g_free(nodename);
+
 nodename = g_strdup_printf("/memory@%lx",
 (long)memmap[SIFIVE_U_DRAM].base);
 qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 6b2b5b68e2..24418145aa 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@ enum {
 
 enum {
 SIFIVE_U_CLOCK_FREQ = 10,
+SIFIVE_U_HFCLK_FREQ = ,
+SIFIVE_U_RTCCLK_FREQ = 100,
 SIFIVE_U_GEM_CLOCK_FREQ = 12500
 };
 
-- 
2.21.0

[Qemu-devel] [PULL 46/47] target/riscv: Fix mstatus dirty mask

[Palmer Dabbelt]

From: Alistair Francis 

This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.

Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis 
Reviewed-by: Bin Meng 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2789215b5e..f767ad24be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, 
target_ulong val)
  * RV32: MPV and MTL are not in mstatus. The current plan is to
  * add them to mstatush. For now, we just don't support it.
  */
-mask |= MSTATUS_MPP | MSTATUS_MPV;
+mask |= MSTATUS_MTL | MSTATUS_MPV;
 #endif
 }
 
-- 
2.21.0

[Qemu-devel] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540

[Palmer Dabbelt]

From: Bin Meng 

This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/Makefile.objs   |   1 +
 hw/riscv/sifive_u_prci.c | 169 +++
 include/hw/riscv/sifive_u_prci.h |  81 +++
 3 files changed, 251 insertions(+)
 create mode 100644 hw/riscv/sifive_u_prci.c
 create mode 100644 include/hw/riscv/sifive_u_prci.h

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index c8596977a8..b95bbd51e2 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_uart.o
 obj-$(CONFIG_SPIKE) += spike.o
 obj-$(CONFIG_RISCV_VIRT) += virt.o
diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c
new file mode 100644
index 00..4fa590c064
--- /dev/null
+++ b/hw/riscv/sifive_u_prci.c
@@ -0,0 +1,169 @@
+/*
+ * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
+ *
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * Simple model of the PRCI to emulate register reads made by the SDK BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/riscv/sifive_u_prci.h"
+
+static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int 
size)
+{
+SiFiveUPRCIState *s = opaque;
+
+switch (addr) {
+case SIFIVE_U_PRCI_HFXOSCCFG:
+return s->hfxosccfg;
+case SIFIVE_U_PRCI_COREPLLCFG0:
+return s->corepllcfg0;
+case SIFIVE_U_PRCI_DDRPLLCFG0:
+return s->ddrpllcfg0;
+case SIFIVE_U_PRCI_DDRPLLCFG1:
+return s->ddrpllcfg1;
+case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
+return s->gemgxlpllcfg0;
+case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
+return s->gemgxlpllcfg1;
+case SIFIVE_U_PRCI_CORECLKSEL:
+return s->coreclksel;
+case SIFIVE_U_PRCI_DEVICESRESET:
+return s->devicesreset;
+case SIFIVE_U_PRCI_CLKMUXSTATUS:
+return s->clkmuxstatus;
+}
+
+qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+  __func__, addr);
+
+return 0;
+}
+
+static void sifive_u_prci_write(void *opaque, hwaddr addr,
+uint64_t val64, unsigned int size)
+{
+SiFiveUPRCIState *s = opaque;
+uint32_t val32 = (uint32_t)val64;
+
+switch (addr) {
+case SIFIVE_U_PRCI_HFXOSCCFG:
+s->hfxosccfg = val32;
+/* OSC stays ready */
+s->hfxosccfg |= SIFIVE_U_PRCI_HFXOSCCFG_RDY;
+break;
+case SIFIVE_U_PRCI_COREPLLCFG0:
+s->corepllcfg0 = val32;
+/* internal feedback */
+s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+/* PLL stays locked */
+s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_U_PRCI_DDRPLLCFG0:
+s->ddrpllcfg0 = val32;
+/* internal feedback */
+s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+/* PLL stays locked */
+s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_U_PRCI_DDRPLLCFG1:
+s->ddrpllcfg1 = val32;
+break;
+case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
+s->gemgxlpllcfg0 = val32;
+/* internal feedback */
+s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+/* PLL stays locked */
+s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
+s->gemgxlpllcfg1 = val32;
+break;
+case SIFIVE_U_PRCI_CORECLKSEL:
+s->coreclksel = val32;
+break;
+case SIFIVE_U_PRCI_DEVICESRESET:
+s->devicesreset = val32;
+break;
+case SIFIVE_U_PRCI_CLKMUXSTATUS:
+s->clkmuxstatus = val32;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+  " v=0x%x\n", __func__, addr, val32);
+}
+}
+
+static const MemoryRegionOps sifive_u_prci_ops = {
+.read = sifive_u_prci_read,
+.write = sifive_u_prci_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid 

Re: [Qemu-devel] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types

[BALATON Zoltan]

On Tue, 10 Sep 2019, Alex Bennée wrote:

diff --git a/include/elf/elf-types.inc.h b/include/elf/elf-types.inc.h
new file mode 100644
index 000..35163adb2b5
--- /dev/null
+++ b/include/elf/elf-types.inc.h
@@ -0,0 +1,63 @@
+/*
+ * Elf Type Specialisation
+ *
+ * Copyright (c) 2019
+ * Written by Alex Bennée 
+ *
+ * This code is licensed under the GNU .


You're missing end of licence sentence here. Also original file did not 
have copyright and licence header so you may want to fix that too or leave 
it out here as well for consistency,



+ */
+
+#ifndef _ELF_TYPES_INC_H_
+#define _ELF_TYPES_INC_H_
+
+#ifndef ELF_CLASS
+#error you must define ELF_CLASS before including elf-types.inc.h
+#else
+
+#if ELF_CLASS == ELFCLASS32
+
+#define elfhdr  elf32_hdr
+#define elf_phdrelf32_phdr
+#define elf_noteelf32_note
+#define elf_shdrelf32_shdr
+#define elf_sym elf32_sym
+#define elf_addr_t  Elf32_Off
+#define elf_relaelf32_rela
+
+#ifdef ELF_USES_RELOCA
+# define ELF_RELOC  Elf32_Rela
+#else
+# define ELF_RELOC  Elf32_Rel
+#endif
+
+#ifndef ElfW
+#  define ElfW(x)   Elf32_ ## x
+#  define ELFW(x)   ELF32_ ## x
+#endif
+
+#else /* ELF_CLASS == ELFCLASS64 */
+
+#define elfhdr  elf64_hdr
+#define elf_phdrelf64_phdr
+#define elf_noteelf64_note
+#define elf_shdrelf64_shdr
+#define elf_sym elf64_sym
+#define elf_addr_t  Elf64_Off
+#define elf_relaelf64_rela
+
+#ifdef ELF_USES_RELOCA
+# define ELF_RELOC  Elf64_Rela
+#else
+# define ELF_RELOC  Elf64_Rel
+#endif
+
+#ifndef ElfW
+#  define ElfW(x)   Elf64_ ## x
+#  define ELFW(x)   ELF64_ ## x
+#endif
+
+#endif /* ELF_CLASS == ELFCLASS64 */
+#endif /* ELF_CLASS */
+#else
+#error elf-types.inc.h should not be included twice in one compilation unit
+#endif /* _ELF_TYPES_INC_H_ */
diff --git a/include/elf.h b/include/elf/elf.h
similarity index 98%
rename from include/elf.h
rename to include/elf/elf.h
index 3501e0c8d03..2e264c1a7a0 100644
--- a/include/elf.h
+++ b/include/elf/elf.h
@@ -1696,49 +1696,7 @@ struct elf32_fdpic_loadmap {
};

#ifdef ELF_CLASS
-#if ELF_CLASS == ELFCLASS32
-
-#define elfhdr elf32_hdr
-#define elf_phdr   elf32_phdr
-#define elf_note   elf32_note
-#define elf_shdr   elf32_shdr
-#define elf_symelf32_sym
-#define elf_addr_t Elf32_Off
-#define elf_rela  elf32_rela
-
-#ifdef ELF_USES_RELOCA
-# define ELF_RELOC  Elf32_Rela
-#else
-# define ELF_RELOC  Elf32_Rel
-#endif
-
-#else
-
-#define elfhdr elf64_hdr
-#define elf_phdr   elf64_phdr
-#define elf_note   elf64_note
-#define elf_shdr   elf64_shdr
-#define elf_symelf64_sym
-#define elf_addr_t Elf64_Off
-#define elf_rela  elf64_rela
-
-#ifdef ELF_USES_RELOCA
-# define ELF_RELOC  Elf64_Rela
-#else
-# define ELF_RELOC  Elf64_Rel
-#endif
-
-#endif /* ELF_CLASS */

-#ifndef ElfW
-# if ELF_CLASS == ELFCLASS32
-#  define ElfW(x)  Elf32_ ## x
-#  define ELFW(x)  ELF32_ ## x
-# else
-#  define ElfW(x)  Elf64_ ## x
-#  define ELFW(x)  ELF64_ ## x
-# endif
-#endif

#endif /* ELF_CLASS */


Is there anything remaining in this #ifdef ELF_CLASS after this patch? If 
not why do you keep it?


Regards,
BALATON Zoltan

[Qemu-devel] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree

[Palmer Dabbelt]

From: Bin Meng 

OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a3ee1ec0a9..5ca3793d35 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -286,7 +286,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(nodename);
 
-nodename = g_strdup_printf("/soc/uart@%lx",
+nodename = g_strdup_printf("/soc/serial@%lx",
 (long)memmap[SIFIVE_U_UART0].base);
 qemu_fdt_add_subnode(fdt, nodename);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
-- 
2.21.0

[Qemu-devel] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

[Palmer Dabbelt]

From: Alistair Francis 

Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.

Signed-off-by: Alistair Francis 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 16efe8c860..124ed33ee4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -301,7 +301,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, 
target_ulong *pc,
 #else
 *flags = cpu_mmu_index(env, 0);
 if (riscv_cpu_fp_enabled(env)) {
-*flags |= env->mstatus & MSTATUS_FS;
+*flags |= TB_FLAGS_MSTATUS_FS;
 }
 #endif
 }
-- 
2.21.0

[Qemu-devel] [PULL 42/47] riscv: sifive_u: Fix broken GEM support

[Palmer Dabbelt]

From: Bin Meng 

At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the  property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/Kconfig|  1 +
 hw/riscv/sifive_u.c | 24 
 include/hw/riscv/sifive_u.h |  3 ++-
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 33e54b031d..fb19b2df3a 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_U
 select CADENCE
 select HART
 select SIFIVE
+select UNIMP
 
 config SPIKE
 bool
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4803e47ae4..3b61fab42c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -3,6 +3,7 @@
  *
  * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
  * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng 
  *
  * Provides a board compatible with the SiFive Freedom U SDK:
  *
@@ -11,6 +12,7 @@
  * 2) PLIC (Platform Level Interrupt Controller)
  * 3) PRCI (Power, Reset, Clock, Interrupt)
  * 4) OTP (One-Time Programmable) memory with stored serial number
+ * 5) GEM (Gigabit Ethernet Controller) and management block
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -37,6 +39,7 @@
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
 #include "hw/cpu/cluster.h"
+#include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
@@ -45,6 +48,7 @@
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
+#include "net/eth.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
@@ -67,7 +71,8 @@ static const struct MemmapEntry {
 [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
 [SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
-[SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
+[SIFIVE_U_GEM] =  { 0x1009, 0x2000 },
+[SIFIVE_U_GEM_MGMT] = { 0x100a, 0x1000 },
 };
 
 #define OTP_SERIAL  1
@@ -84,7 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 char ethclk_names[] = "pclk\0hclk";
 uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
 uint32_t uartclk_phandle;
-uint32_t hfclk_phandle, rtcclk_phandle;
+uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 
 fdt = s->fdt = create_device_tree(&s->fdt_size);
 if (!fdt) {
@@ -254,21 +259,28 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(nodename);
 
+phy_phandle = phandle++;
 nodename = g_strdup_printf("/soc/ethernet@%lx",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
+qemu_fdt_setprop_string(fdt, nodename, "compatible",
+"sifive,fu540-c000-gem");
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_GEM].base,
-0x0, memmap[SIFIVE_U_GEM].size);
+0x0, memmap[SIFIVE_U_GEM].size,
+0x0, memmap[SIFIVE_U_GEM_MGMT].base,
+0x0, memmap[SIFIVE_U_GEM_MGMT].size);
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
+qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 sizeof(ethclk_names));
+qemu_fdt_setprop(fdt, nodename, "local-mac-address",
+s->soc.gem.conf.macaddr.a, ETH_ALEN);
 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 g_free(nodename);
@@ -276,6 +288,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 nodename = g_strdup_

[Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number

[Palmer Dabbelt]

From: Bin Meng 

This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_u.c | 9 +
 include/hw/riscv/sifive_u.h | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ca3793d35..4803e47ae4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,6 +10,7 @@
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  * 3) PRCI (Power, Reset, Clock, Interrupt)
+ * 4) OTP (One-Time Programmable) memory with stored serial number
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -64,10 +65,12 @@ static const struct MemmapEntry {
 [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
 [SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
 [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
+[SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
 [SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
 };
 
+#define OTP_SERIAL  1
 #define GEM_REVISION0x10070109
 
 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
@@ -422,6 +425,9 @@ static void riscv_sifive_u_soc_init(Object *obj)
 
 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
   TYPE_SIFIVE_U_PRCI);
+sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
+  TYPE_SIFIVE_U_OTP);
+qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
   TYPE_CADENCE_GEM);
 }
@@ -498,6 +504,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
 
+object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+
 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 }
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 7dfd1cb22e..4d4733cb6a 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -23,6 +23,7 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_u_prci.h"
+#include "hw/riscv/sifive_u_otp.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -39,6 +40,7 @@ typedef struct SiFiveUSoCState {
 RISCVHartArrayState u_cpus;
 DeviceState *plic;
 SiFiveUPRCIState prci;
+SiFiveUOTPState otp;
 CadenceGEMState gem;
 } SiFiveUSoCState;
 
@@ -60,6 +62,7 @@ enum {
 SIFIVE_U_PRCI,
 SIFIVE_U_UART0,
 SIFIVE_U_UART1,
+SIFIVE_U_OTP,
 SIFIVE_U_DRAM,
 SIFIVE_U_GEM
 };
-- 
2.21.0

Re: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190910163600.19971-1-laur...@vivier.eu/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches
Message-id: 20190910163600.19971-1-laur...@vivier.eu
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  patchew/cover.1566603412.git.alistair.fran...@wdc.com -> 
patchew/cover.1566603412.git.alistair.fran...@wdc.com
 - [tag update]  
patchew/cover.1568170994.git.maozhon...@cmss.chinamobile.com -> 
patchew/cover.1568170994.git.maozhon...@cmss.chinamobile.com
Switched to a new branch 'test'
be22b95 linux-user: Add support for FDRESET, FDRAWCMD, FDTWADDLE, and FDEJECT 
ioctls
1812166 linux-user: Add support for FDMSGON and FDMSGOFF ioctls
40884ed linux-user: Add support for FDFLUSH ioctl
d574b3a linux-user: Add support for FIOGETOWN and FIOSETOWN ioctls
e16b8dd linux-user: Add support for RNDRESEEDCRNG ioctl
922669d linux-user: drop redundant handling of environment variables
deb18db target/xtensa: linux-user: add call0 ABI support
a70df8a linux-user: Support gdb 'qOffsets' query for ELF
2ad3c68 linux-user/arm: Adjust MAX_RESERVED_VA for M-profile
b4ab4ac linux-user: Pass CPUState to MAX_RESERVED_VA
a59d788 linux-user: add memfd_create
a689210 linux-user: fail and report on bad dfilter specs
a5018de linux-user: erroneous fd_trans_unregister call
d3dcf99 linux-user: Add AT_HWCAP2 for aarch64-linux-user
3378a43 linux-user: remove useless variable

=== OUTPUT BEGIN ===
1/15 Checking commit 3378a432a4fc (linux-user: remove useless variable)
2/15 Checking commit d3dcf9993f90 (linux-user: Add AT_HWCAP2 for 
aarch64-linux-user)
3/15 Checking commit a5018de8c612 (linux-user: erroneous fd_trans_unregister 
call)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Shu-Chun Weng via Qemu-devel 

total: 1 errors, 0 warnings, 7 lines checked

Patch 3/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/15 Checking commit a689210767d2 (linux-user: fail and report on bad dfilter 
specs)
5/15 Checking commit a59d78863227 (linux-user: add memfd_create)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Shu-Chun Weng via Qemu-devel 

total: 1 errors, 0 warnings, 42 lines checked

Patch 5/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/15 Checking commit b4ab4acec65b (linux-user: Pass CPUState to MAX_RESERVED_VA)
7/15 Checking commit 2ad3c68003d3 (linux-user/arm: Adjust MAX_RESERVED_VA for 
M-profile)
8/15 Checking commit a70df8af8d3c (linux-user: Support gdb 'qOffsets' query for 
ELF)
ERROR: Author email address is mangled by the mailing list
#2: 
Author: Josh Kunz via Qemu-devel 

total: 1 errors, 0 warnings, 8 lines checked

Patch 8/15 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/15 Checking commit deb18db43c2a (target/xtensa: linux-user: add call0 ABI 
support)
10/15 Checking commit 922669d1ad47 (linux-user: drop redundant handling of 
environment variables)
11/15 Checking commit e16b8ddf82eb (linux-user: Add support for RNDRESEEDCRNG 
ioctl)
12/15 Checking commit d574b3a3ed75 (linux-user: Add support for FIOGETOWN and 
FIOSETOWN ioctls)
13/15 Checking commit 40884edbc45d (linux-user: Add support for FDFLUSH ioctl)
14/15 Checking commit 18121669c965 (linux-user: Add support for FDMSGON and 
FDMSGOFF ioctls)
15/15 Checking commit be22b959d66f (linux-user: Add support for FDRESET, 
FDRAWCMD, FDTWADDLE, and FDEJECT ioctls)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190910163600.19971-1-laur...@vivier.eu/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [Qemu-devel] [PATCH v6 22/42] block: Fix bdrv_get_allocated_file_size's fallback

[Kevin Wolf]

Am 11.09.2019 um 09:37 hat Max Reitz geschrieben:
> On 11.09.19 08:55, Kevin Wolf wrote:
> > Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
> >> On 10.09.19 16:52, Kevin Wolf wrote:
> >>> Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
>  If the driver does not implement bdrv_get_allocated_file_size(), we
>  should fall back to cumulating the allocated size of all non-COW
>  children instead of just bs->file.
> 
>  Suggested-by: Vladimir Sementsov-Ogievskiy 
>  Signed-off-by: Max Reitz 
> >>>
> >>> This smells like an overgeneralisation, but if we want to count all vmdk
> >>> extents, the qcow2 external data file, etc. it's an improvement anyway.
> >>> A driver that has a child that should not be counted must just remember
> >>> to implement the callback.
> >>>
> >>> Let me think of an example... How about quorum, for a change? :-)
> >>> Or the second blkverify child.
> >>>
> >>> Or eventually the block job filter nodes.
> >>
> >> I actually think it makes sense for all of these nodes to report the sum
> >> of all of their children’s allocated sizes.
> > 
> > Hm... Yes, in a way. But not much more than it would make sense to
> > report the sum of the sizes of all images in the whole backing chain
> > (this is a useful thing to ask for, just maybe not the right thing to
> > return for a low-level interface). But I can accept that it's maybe a
> > bit more expected for quorum and blkverify than for COW images.
> > 
> > If you include the block job filter nodes, I have to disagree, though.
> > If mirror_top_bs (or any other job filter) sits in the middle of the
> > source chain, then I certainly don't want to see the target size added
> > to it.
> 
> Hm, I don’t care much either way.  I think it makes complete sense to
> add the target size there, but OTOH it’s only temporary while the job
> runs, so it may be a bit confusing if it suddenly goes up and then down
> again.

I think the number that most users are interested in is knowing how much
space the image for their /dev/vda takes up on the host.

I can see how they might be interested in not only that one image file,
but all other image files connected to it, i.e. their /dev/vda with all
of its snapshots. This would mean counting backing files. I think adding
up the numbers for this should be done in the management layer.

I can possibly also imagine users wanting to count everything that's
even loosely connected to their /dev/vda, like copies of it. I doubt,
however, they want to count only copies that are currently being made,
but not snapshots and copies that have been completed earlier. So this
is clearly a management layer thing, too.

> But I think this is the special case, so this is what should be handled
> in a driver callback.

It's a special case, yes. But see below.

> >> If a quorum node has three children with allocated sizes of 3 MB, 1 MB,
> >> and 2 MB, respectively (totally possible if some have explicit zeroes
> >> and others don’t; it may also depend on the protocol, the filesystem,
> >> etc.), then I think it makes most sense to report indeed 6 MB for the
> >> quorum subtree as a whole.  What would you report?  3 MB?
> > 
> > Do it's the quorum way: Just vote!
> 
> Add an option for it?  Average, maximum, median, majority, sum? :-)

We could also introduce a mode with an Electoral College so that
sometimes an image that missed the majority has a chance to win anyway.

> > No, you're right, of course. -ENOTSUP is probably the only other thing
> > you could do then.
> > 
> >>> Ehm... Maybe I should just take back what I said first. It almost feels
> >>> like it would be better if qcow2 and vmdk explicitly used a handler that
> >>> counts all children (could still be a generic one in block.c) rather
> >>> than having to remember to disable the functionality everywhere where we
> >>> don't want to have it.
> >>
> >> I don’t, because everywhere we don’t want this functionality, we still
> >> need to choose a child.  This has to be done by the driver anyway.
> > 
> > Well, by default the primary child, which should cover like 90% of the
> > drivers?
> 
> Hm, yes.
> 
> But I still think that the drivers that do not want to count every
> single non-COW child are the exception.

They are, but drivers that want to count more than their primary node
are exceptions, too. And I think you're more likely to remember adding
the callback when you want to have a certain feature, not when you don't
want to have it.

I really think we're likely to forget adding the callback where we need
to disable the feature.

I can see two options that should address both of our views:

1. Just don't have a fallback at all, make the callback mandatory and
   provide implementations in block.c that can be referred to in
   BlockDriver. Not specifying the callback causes an assertion failure,
   so we'd hopefully notice it quite early (assuming that we run either
   'qemu-img info' or 'query-block' on a configuration with the block
   driver,

[Qemu-devel] [PULL 45/47] target/riscv: Use both register name and ABI name

[Palmer Dabbelt]

From: Atish Patra 

Use both the generic register name and ABI name for the general purpose
registers and floating point registers.

Signed-off-by: Atish Patra 
Signed-off-by: Alistair Francis 
Reviewed-by: Bin Meng 
Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6d52f97d7c..f13e298a36 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,17 +34,20 @@
 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
 
 const char * const riscv_int_regnames[] = {
-  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
-  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
-  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
-  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
+  "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
+  "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
+  "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
+  "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
+  "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
 };
 
 const char * const riscv_fpr_regnames[] = {
-  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
-  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
-  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
-  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+  "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
+  "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
+  "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
+  "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
+  "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
+  "f30/ft10", "f31/ft11"
 };
 
 const char * const riscv_excp_names[] = {
-- 
2.21.0

Re: [Qemu-devel] QEMU as ISS (Instruction Set Simulator)

[Libo Zhou]

Reverting the commit solved my problem, although I don't know why it needed to 
be fixed to 64-bit back then. Finally I can now  single step a cross-compiled 
MIPS program on a QEMU Linux user binary and observe the register and memory 
contents.



-- Original --
From:  "Aleksandar Markovic";;
Send time: Wednesday, Sep 11, 2019 1:50 AM
To: "Libo Zhou"; 
Cc: "Alex Bennée"; "qemu-devel"; 
Subject:  Re: [Qemu-devel] QEMU as ISS (Instruction Set Simulator)



10.09.2019. 19.26, aleksandar.m.m...@gmail.com ?е написао/ла:
>
>
> 10.09.2019. 11.57, "Libo Zhou"  ?е написао/ла:
> >
> > Hi Alex,
> >
> > gdb says remote 'g' packet reply is too long, and then prints out a
long string of zeros and some other digits sparsely.
> >
> > I have tried a lot of combinations of flags but I just can't get it
running properly. Do you know what is causing this error?
> >
>
> This is a known bug, actually in gdb, but there is a workaround is to
rollback a commit made  around a year ago in QEMU, about 64-bit FPU Mips
registers.

More previsely, reverting
https://github.com/qemu/qemu/commit/8e0b373f8aa4b9feec7b44029455587e2e3d2b0f
would most likely rrmove your problem.

Aleksandar

> Or you can fix the buffer size in gdb.
>
> Aleksandar
>
> > Cheers,
> > Libo
> >
> >
> > -- Original --
> > From:  "Alex Bennée";;
> > Send time: Friday, Sep 6, 2019 5:19 PM
> > To: "Libo Zhou";
> > Cc: "qemu-devel"; "Aleksandar Markovic"<
aleksandar.m.m...@gmail.com>;
> > Subject:  Re: [Qemu-devel] QEMU as ISS (Instruction Set Simulator)
> >
> >
> > Libo Zhou  writes:
> >
> > > Hi Alex,
> > >
> > >
> > > I just need to log the registers and memory after the program finishes
> > > its execution. Is it possible to add this functionality myself?
> >
> > You'll need to set some sort of breakpoint on the last instruction so
> > gdb can inspect things before the program is unloaded. I think it's
> > possible to wire poweroff events to the gdbstub but I haven't looked
> > into that myself.
> >
> > > As for the GDB option, can you tell me the specific steps to do that?
I've tried it myself but I had no luck getting it running due to me being
new to all this.
> > >
> >
> > For linux-user:
> >
> >   $QEMU -g 1234 $PRG
> >
> > for system emulation
> >
> >   $QEMU -s -S
> >
> > and then on the gdb end:
> >
> >   gdb $BIN -ex "target remote localhost:1234"
> >
> > and then you can operate as you normally do with a gdb session. GDB has
> > two scripting interfaces. The command mode is basically a list of gdb
> > commands but might work for what you want. If you want to be a bit more
> > programatic you can use python. See the example in
> > tests/guest-debug/test-gdbstub.py
> >
> > >
> > > Thanks,
> > > Libo
> > >
> > >
> > >
> > > -- Original --
> > > From:  "Alex Bennée";;
> > > Send time: Thursday, Sep 5, 2019 8:58 PM
> > > To: "qemu-devel";
> > > Cc: "Aleksandar Markovic";
> > > Subject:  Re: [Qemu-devel] QEMU as ISS (Instruction Set Simulator)
> > >
> > >
> > >
> > >
> > > Libo Zhou  writes:
> > >
> > >> Do you know where in the source file I should look into to add my
custom logging functionality?
> > >>
> > >>
> > >> Or, would you suggest using gdb to look at my target register and
memory contents? The answer in this link below looks really promising. I'm
gonna give it a try first.
> > >>
> > >>
https://stackoverflow.com/questions/39503997/how-to-run-a-single-line-of-assembly-then-see-r1-and-condition-flags
> > >
> > > The gdbstub should allow you do full introspection and adding
> > > additional registers is fairly easy, see FOO_gdb_[set|get]_reg helpers
> > > in the appropriate target/FOO directories.
> > >
> > >> However, if I am able to customize log, it will be super convenient.
> > >
> > > So you want something above what -d cpu will show you?
> > >
> > >>
> > >>
> > >>
> > >> Cheers,
> > >>
> > >> Libo
> > >>
> > >>
> > >>
> > >> -- Original --
> > >> From:  "Aleksandar Markovic";;
> > >> Send time: Thursday, Sep 5, 2019 6:54 PM
> > >> To: "Libo Zhou";
> > >> Cc: "qemu-devel";
> > >> Subject:  Re: [Qemu-devel] QEMU as ISS (Instruction Set Simulator)
> > >>
> > >>
> > >>
> > >> 04.09.2019. 05.23, "Libo Zhou"  ?е написао/ла:
> > >>>
> > >>> Hi Aleksandar,
> > >>>
> > >>> I have spent some time looking at your MXU ASE patch. It's super
helpful.
> > >> I need to do exactly the same thing as you did.
> > >>>
> > >>> Now I just need a way to observe the memory and register file
contents to
> > >> debug my instruction set simulator. I played with the "-d" switch to
log a
> > >> bunch of information, but it seems that none of the items is of my
> > >> interest. The "-d cpu_reset" option displays all zeros in the GPR
log.
> > >>>
> > >>
> > >> It looks you need a custom logging tailored to your needs, based on
> > >> intercepting the instructions you added.
> > >>
> > >> Aleksandar
> > >>
> > >>> Please take your time, as I fully under

Re: [Qemu-devel] [Qemu-block] [PATCH 0/7] Move qtests to a separate folder

[Kevin Wolf]

Am 11.09.2019 um 10:01 hat Thomas Huth geschrieben:
> On 11/09/2019 08.58, Kevin Wolf wrote:
> > Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
> >> On 9/10/19 1:58 PM, Thomas Huth wrote:
> >>> Our "tests" directory is very overcrowded - we store the qtests,
> >>> unit test and other files there. That makes it difficult to
> >>> determine which file belongs to each test subsystem, and the
> >>> wildcards in the MAINTAINERS file are inaccurate, too.
> >>>
> >>> Let's clean up this mess. The first patches disentangle some
> >>> dependencies, and the last three patches then move the qtests
> >>> and libqos (which is a subsystem of the qtests) to a new folder
> >>> called "tests/qtest/".
> >>
> >> I'd also welcome a rename of tests/qemu-iotests to tests/iotests.
> > 
> > I might prefer if the directory were named "iotests" rather than
> > "qemu-iotests" if we were only adding the code now.
> > 
> > However, I'm not so sure if I'd like a rename now because a rename
> > always comes with a cost and the benefits are rather limited in this
> > case.
> 
> Well, if we all agree that it rather should be renamed, we should maybe
> rather do it now than later. Later the cost might even be higher.

What I'm saying is that I'm not sure that it should be renamed. What
will we gain from the rename apart from saving five redundant characters
in the path?

Kevin


signature.asc
Description: PGP signature

Re: [Qemu-devel] [PATCH 1/3] cputlb: Disable __always_inline__ without optimization

[Peter Maydell]

On Wed, 11 Sep 2019 at 02:43, Richard Henderson
 wrote:
>
> This forced inlining can result in missing symbols,
> which makes a debugging build harder to follow.
>
> Reported-by: Peter Maydell 
> Signed-off-by: Richard Henderson 
> ---
>  accel/tcg/cputlb.c | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index abae79650c..909f01ebcc 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -1269,6 +1269,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, 
> target_ulong addr,
>  cpu_loop_exit_atomic(env_cpu(env), retaddr);
>  }
>
> +/*
> + * In order for the expected constant folding to happen,
> + * we require that some functions be inlined.
> + * However, this inlining can make debugging harder for a
> + * non-optimizing build.
> + */
> +#ifdef __OPTIMIZE__
> +#define ALWAYS_INLINE  __attribute__((always_inline))
> +#else
> +#define ALWAYS_INLINE
> +#endif
> +

Maybe this should go in compiler.h ?

>  /*
>   * Load Helpers
>   *
> @@ -1281,7 +1293,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, 
> target_ulong addr,
>  typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
>  TCGMemOpIdx oi, uintptr_t retaddr);
>
> -static inline uint64_t __attribute__((always_inline))
> +static inline uint64_t ALWAYS_INLINE
>  load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
>  uintptr_t retaddr, MemOp op, bool code_read,
>  FullLoadHelper *full_load)
> @@ -1530,7 +1542,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, 
> target_ulong addr,
>   * Store Helpers
>   */
>
> -static inline void __attribute__((always_inline))
> +static inline void ALWAYS_INLINE
>  store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
>   TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
>  {
> --
> 2.17.1

Either way

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [Qemu-devel] [RFC] docs: vhost-user: add in-band kick/call messages

[Johannes Berg]

On Wed, 2019-09-11 at 09:35 +0200, Stefan Hajnoczi wrote:
> On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> > On Tue, 2019-09-10 at 17:03 +0200, Stefan Hajnoczi wrote:
> > > > Now, this means that the CPU (that's part of the simulation) has to
> > > > *wait* for the device to add an entry to the simulation calendar in
> > > > response to the kick... That means that it really has to look like
> > > > 
> > > > CPU   device   calendar
> > > >  ---[kick]-->
> > > >  ---[add entry]-->
> > > >  <---[return]-
> > > 
> > > What are the semantics of returning from the calendar?  Does it mean
> > > "it's now your turn to run?", "your entry has been added and you'll be
> > > notified later when it's time to run?", or something else?
> > 
> > The latter - the entry was added, and you'll be notified when it's time
> > to run; but we need to have that state on the calendar so the CPU won't
> > converse with the calendar before that state is committed.
> 
> Is the device only adding a calendar entry and not doing any actual
> device emulation at this stage?

Correct, yes.

With one exception: in the case of the simtime (calendar) device, the
actual processing *does* happen at this stage, of course - the calendar
entry has to have been added before we return.

> If yes, then this suggests the system could be structured more cleanly.
> The vhost-user device process should focus on device emulation.  It
> should not be aware of the calendar.

Decoupling the device entirely from the simulation doesn't work, at
least it depends on what you want to emulate. If you don't care that
everything in the device happens immediately (in simulation time), then
this might be OK - but in most cases you do want to model some latency,
processing time or similar in the device, and that means the device has
to request more calendar entries for its further processing.

Take a network device for example that wants to model a 50ms latency. It
has to first have a calendar event to take the packet from the deriver
onto the wire, and then have another calendar event to push the packet
from the wire out some other driver. The first of those events could be
modelled by what you suggest below, the second cannot.

> The vhost-user protocol also shouldn't require modifications.
> 
> Instead, Linux arch/um code would add the entry to the calendar when the
> CPU wants to kick a vhost-user device.  I assume the CPU is suspended
> until arch/um code completes adding the entry to the calendar.

Right, OK, so far I'm following, and it seems perfectly reasonable.

Though as I said above (the simtime exception) - suspending the CPU
while adding an entry to the calendar actually also relies on the
KICK/ACK message semantics right now. This could easily be implemented
differently in this particular device though, e.g. by waiting for an ACK
message on a response virtqueue after sending the "add-entry" request on
the command virtqueue.

> When the calendar decides to run the device entry it signals the
> vhost-user kick eventfd.

Now you have to send those FDs also to the calendar, but I guess the
calendar is a vhost-user device too anyway, so we can send it the FD
along with the request to add the calendar entry, i.e. instead of adding
a calendar entry "please tell me" you can add a calendar entry with
"please kick this FD". Seems reasonable, though it requires much deeper
integration of the virtio implementation with the calendar than I was
planning, though possibly a bit less such integration on the device
side.

> The vhost-user device processes the virtqueue
> as if it had been directly signalled by the CPU, totally unaware that
> it's running within a simulation system.

As I said above, it cannot be entirely unaware unless it's a very
trivial device emulation. That *might* be something you actually
want/don't care, for example for a "control network" within the
simulation where you don't need to model any latencies, however it also
very easily introduces issues, say if the vhost-user device emulation,
focusing completely on emulation, starts doing 'sleep()' or similar OS
calls; they really should be going to the simulation instead.


However, really the place where this breaks down is that you don't know
when the device has finished processing.

As a totally made-up example, say you're emulating a strange /dev/null
device, but as a special quirk it can only ever consume an even number
of buffers. You give it a buffer on a virtqueue and kick it, nothing
happens; you give it another one and kick it, it'll consume both and
free (call) up the two entries, doing nothing else.

In the simulation of this device, it has to essentially behave like
this:
On kick, it schedules a calendar entry to process the interrupt. Once
that entry is signalled, the interrupt processing code runs and checks
the state of the virtqueue; if there's an even number of buffers it
releases 

Re: [Qemu-devel] [PATCH 5/7] spapr: Do not put empty properties for -kernel/-initrd/-append

[Greg Kurz]

On Wed, 11 Sep 2019 14:04:50 +1000
David Gibson  wrote:

> From: Alexey Kardashevskiy 
> 
> We are going to use spapr_build_fdt() for the boot time FDT and as an
> update for SLOF during handling of H_CAS. SLOF will apply all properties
> from the QEMU's FDT which is usually ok unless there are properties
> changed by grub or guest kernel. The properties are:
> bootargs, linux,initrd-start, linux,initrd-end, linux,stdout-path,
> linux,rtas-base, linux,rtas-entry. Resetting those during CAS will most
> likely cause grub failure.
> 

s/Resetting/Clearing ? They still get reset to the initial setup if "-kernel"
and "-initrd" were passed, but it is okay since neither grub, nor the guest
kernel is supposed to change them in this case, correct ?

> This only creates such properties if we are booting with "-kernel" and
> "-initrd" so they won't get included into the DT update blob and

so they won't get included {if we're not booting with "-kernel" ...}

> therefore the guest is more likely to boot successfully.
> 

Maybe rephrase like:

Don't create such properties if we're booting without "-kernel" and
"-initrd" ...

> Signed-off-by: Alexey Kardashevskiy 
> Signed-off-by: David Gibson 
> ---
>  hw/ppc/spapr.c | 15 ++-
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index d072c2aa3d..d18744268f 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1177,11 +1177,16 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, 
> void *fdt)
>  
>  _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
>  
> -_FDT(fdt_setprop_string(fdt, chosen, "bootargs", 
> machine->kernel_cmdline));
> -_FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
> -  spapr->initrd_base));
> -_FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
> -  spapr->initrd_base + spapr->initrd_size));
> +if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {

machine->kernel_cmdline cannot be NULL.

From vl.c:

if (!kernel_cmdline) {
kernel_cmdline = "";
current_machine->kernel_cmdline = (char *)kernel_cmdline;
}

Also this doesn't check if we're booting with -kernel but rather
that we're booting with -append ${some_not_empty_string}... what
about checking spapr->kernel_size, pretty much like you do for
the initrd ?

> +_FDT(fdt_setprop_string(fdt, chosen, "bootargs",
> +machine->kernel_cmdline));
> +}
> +if (spapr->initrd_size) {
> +_FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
> +  spapr->initrd_base));
> +_FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
> +  spapr->initrd_base + spapr->initrd_size));
> +}
>  
>  if (spapr->kernel_size) {
>  uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),

Re: [Qemu-devel] [PATCH v2 1/3] migration: Add validate-uuid capability

[Dr. David Alan Gilbert]

* Yury Kotov (yury-ko...@yandex-team.ru) wrote:
> This capability realizes simple source validation by UUID.
> It's useful for live migration between hosts.
> 
> Signed-off-by: Yury Kotov 

Reviewed-by: Dr. David Alan Gilbert 

> ---
>  migration/migration.c |  9 +
>  migration/migration.h |  1 +
>  migration/savevm.c| 45 +++
>  qapi/migration.json   |  5 -
>  4 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/migration/migration.c b/migration/migration.c
> index 8b9f2fe30a..2391a8d418 100644
> --- a/migration/migration.c
> +++ b/migration/migration.c
> @@ -2140,6 +2140,15 @@ bool migrate_ignore_shared(void)
>  return s->enabled_capabilities[MIGRATION_CAPABILITY_X_IGNORE_SHARED];
>  }
>  
> +bool migrate_validate_uuid(void)
> +{
> +MigrationState *s;
> +
> +s = migrate_get_current();
> +
> +return s->enabled_capabilities[MIGRATION_CAPABILITY_VALIDATE_UUID];
> +}
> +
>  bool migrate_use_events(void)
>  {
>  MigrationState *s;
> diff --git a/migration/migration.h b/migration/migration.h
> index 3e1ea2b5dc..4f2fe193dc 100644
> --- a/migration/migration.h
> +++ b/migration/migration.h
> @@ -290,6 +290,7 @@ bool migrate_postcopy_ram(void);
>  bool migrate_zero_blocks(void);
>  bool migrate_dirty_bitmaps(void);
>  bool migrate_ignore_shared(void);
> +bool migrate_validate_uuid(void);
>  
>  bool migrate_auto_converge(void);
>  bool migrate_use_multifd(void);
> diff --git a/migration/savevm.c b/migration/savevm.c
> index 4a86128ac4..493dc24fd2 100644
> --- a/migration/savevm.c
> +++ b/migration/savevm.c
> @@ -256,6 +256,7 @@ typedef struct SaveState {
>  uint32_t target_page_bits;
>  uint32_t caps_count;
>  MigrationCapability *capabilities;
> +QemuUUID uuid;
>  } SaveState;
>  
>  static SaveState savevm_state = {
> @@ -307,6 +308,7 @@ static int configuration_pre_save(void *opaque)
>  state->capabilities[j++] = i;
>  }
>  }
> +state->uuid = qemu_uuid;
>  
>  return 0;
>  }
> @@ -464,6 +466,48 @@ static const VMStateDescription vmstate_capabilites = {
>  }
>  };
>  
> +static bool vmstate_uuid_needed(void *opaque)
> +{
> +return qemu_uuid_set && migrate_validate_uuid();
> +}
> +
> +static int vmstate_uuid_post_load(void *opaque, int version_id)
> +{
> +SaveState *state = opaque;
> +char uuid_src[UUID_FMT_LEN + 1];
> +char uuid_dst[UUID_FMT_LEN + 1];
> +
> +if (!qemu_uuid_set) {
> +/*
> + * It's warning because user might not know UUID in some cases,
> + * e.g. load an old snapshot
> + */
> +qemu_uuid_unparse(&state->uuid, uuid_src);
> +warn_report("UUID is received %s, but local uuid isn't set",
> + uuid_src);
> +return 0;
> +}
> +if (!qemu_uuid_is_equal(&state->uuid, &qemu_uuid)) {
> +qemu_uuid_unparse(&state->uuid, uuid_src);
> +qemu_uuid_unparse(&qemu_uuid, uuid_dst);
> +error_report("UUID received is %s and local is %s", uuid_src, 
> uuid_dst);
> +return -EINVAL;
> +}
> +return 0;
> +}
> +
> +static const VMStateDescription vmstate_uuid = {
> +.name = "configuration/uuid",
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.needed = vmstate_uuid_needed,
> +.post_load = vmstate_uuid_post_load,
> +.fields = (VMStateField[]) {
> +VMSTATE_UINT8_ARRAY_V(uuid.data, SaveState, sizeof(QemuUUID), 1),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
>  static const VMStateDescription vmstate_configuration = {
>  .name = "configuration",
>  .version_id = 1,
> @@ -478,6 +522,7 @@ static const VMStateDescription vmstate_configuration = {
>  .subsections = (const VMStateDescription*[]) {
>  &vmstate_target_page_bits,
>  &vmstate_capabilites,
> +&vmstate_uuid,
>  NULL
>  }
>  };
> diff --git a/qapi/migration.json b/qapi/migration.json
> index 9cfbaf8c6c..82feb5bd39 100644
> --- a/qapi/migration.json
> +++ b/qapi/migration.json
> @@ -415,6 +415,9 @@
>  #
>  # @x-ignore-shared: If enabled, QEMU will not migrate shared memory (since 
> 4.0)
>  #
> +# @validate-uuid: Send the UUID of the source to allow the destination
> +# to ensure it is the same. (since 4.2)
> +#
>  # Since: 1.2
>  ##
>  { 'enum': 'MigrationCapability',
> @@ -422,7 +425,7 @@
> 'compress', 'events', 'postcopy-ram', 'x-colo', 'release-ram',
> 'block', 'return-path', 'pause-before-switchover', 'multifd',
> 'dirty-bitmaps', 'postcopy-blocktime', 'late-block-activate',
> -   'x-ignore-shared' ] }
> +   'x-ignore-shared', 'validate-uuid' ] }
>  
>  ##
>  # @MigrationCapabilityStatus:
> -- 
> 2.17.1
> 
--
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK

Re: [Qemu-devel] [RFC] libvhost-user: implement VHOST_USER_PROTOCOL_F_KICK_CALL_MSGS

[Michael S. Tsirkin]

On Tue, Sep 10, 2019 at 05:52:36PM +0200, Johannes Berg wrote:
> On Mon, 2019-09-09 at 15:50 +0200, Johannes Berg wrote:
> 
> > > We can document how to behave in case of inconsistent protocol features,
> > > yes.
> > 
> > OK.
> 
> Coming back to this, I was just looking at it.
> 
> How/where would you like to see this done?
> 
> There isn't really any section that lists and explains the various
> protocol features, there's only a list. I could add a new section for
> "Simulation" or something like that that explains it, but then most
> people would probably skip that and not ever read the text about how you
> shouldn't implement F_KICK_CALL_MSGS :-)
> 
> Any thoughts?
> 
> johannes

Each feature is documented near the description of the functionality it
enables, that can work for this. I don't much like F_KICK_CALL_MSGS as
not generic enough but it's not simulation as such:
IN_BAND_NOTIFICATIONS?


As for how to handle errors, that probably belongs near
"Communication".

Or maybe add a new "Error handling" section.

Re: [Qemu-devel] [PATCH v2] docs/nvdimm: add example on persistent backend setup

[Wei Yang]

On Thu, Aug 01, 2019 at 08:40:53AM +0800, Wei Yang wrote:
>Persistent backend setup requires some knowledge about nvdimm and ndctl
>tool. Some users report they may struggle to gather these knowledge and
>have difficulty to setup it properly.
>
>Here we provide two examples for persistent backend and gives the link
>to ndctl. By doing so, user could try it directly and do more
>investigation on persistent backend setup with ndctl.
>
>Signed-off-by: Wei Yang 
>Reviewed-by: Pankaj Gupta 
>

Would someone pick up this one?

Thanks ~


-- 
Wei Yang
Help you, Help me