Re: [RFC PATCH 0/5] hw/mips: Fix Fuloong2E to boot Linux guest again
On Sat, 2 Jan 2021, Philippe Mathieu-Daudé wrote: We closed 2020 with few discussions about the Fuloong 2E board (see [1] and [2]). This series collect the minimum set of patch to have the machine booting Linux guest again, including integration tests. This is sent as RFC because Mark raised some issues in (see [3] and previous in this thread) and I don't understand PCI enough to intervene. Thanks for collecting these. Let me summarise the discussion because the meaning may have been lost in the seamingly heated debate but I think Mark's main concern was that he does not like having a feature flag and property setting the emulation to partially emulate the device: either only emulating legacy mode or native mode that this patch does but he would prefer to faithfully emulate the device preferably allowing switching between modes. But that's not easily possible without rewritig either the ISA emulation or PCI emulation in QEMU because current code does not allow these to be switched once created. That's way more work and risk of breaking other things using these fundamental parts that I would want to take on. My goal was only to allow using this (otherwise quite unused and deglected) device model in pegasos2 emulation which needs native mode. But turns out fuloong2e Linux wants legacy mode so we need a way to resolve this conflict and the solution was this flag and keeping partial emulation depending on machine. But Mark still considered that a horrible hack but after looking more closely he also found the difficulty of implementing a more faithful emulation so he would accept the flag at the end but still wanted registers to be set more consistently matching what the data sheet and whatever ideals would dictate. However I've spent a lot of time before finding these values that work with all clients and found some of these clients have assumptions instead of working in an ideal world following what data sheets say and I don't want to make any changes to this now before we also have pegasos2 upstreamed so any change can be more throughly tested and I don't have to retest everything for every small change just to find something broke, This was the main reason for disagreement and I think Mark's standards for this device was way higher than necessary in this situation and I may have got upset to have this pushed back again when we've already went through this last March where we also had a long discussion after which Mark managed to get rid of the flag but that now came back in a different form. (Previously it was switching between fully native and non-100% native mode, now it selects legacy or non-100% native mode where legacy is needed for fuloong2e linux and non-100% native mode is needed for pegasos2 guests.) This may not be how the real device work (Mark also has concerns about what exactly is non-100% native mode) and it may be a horrible hack but it's probably the best that can be done with current QEMU facilities and in the time I had and since this is only used on fuloong2e and pegasos2 for a few obscure guests I think it does not need any more complex solution at the moment. It seems this disagreement on what's good enough for a device model to get in QEMU is the source of disagreement between us with Mark but we'll sort that out off list once I finish preparing my pegasos2 patches that will finally show where these changes go and oters can also test any proposed changes. Regards, BALATON Zoltan Peter commented a similar PCI issue with the Sam460ex [4] so might be able to help us here. Anyhow, sharing this PoC on the list with the test, the avoid boring manual testing. Regards, Phil. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769105.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769557.html [3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769593.html [4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769697.html BALATON Zoltan (1): ide: Make room for flags in PCIIDEState and add one for legacy mode Guenter Roeck (1): via-ide: Fix fuloong2e support Jiaxun Yang (1): tests/acceptance: Test boot_linux_console for fuloong2e Philippe Mathieu-Daudé (2): hw/pci-host/bonito: Remap PCI "lo" regions when PCIMAP reg is modified tests/integration: Test Fuloong2E IDE drive, run userspace commands include/hw/ide/pci.h | 7 +++- hw/ide/cmd646.c| 6 ++-- hw/ide/via.c | 19 -- hw/mips/fuloong2e.c| 4 ++- hw/pci-host/bonito.c | 49 +++--- hw/sparc64/sun4u.c | 2 +- tests/acceptance/boot_linux_console.py | 47 7 files changed, 113 insertions(+), 21 deletions(-) -- 2.26.2
Re: [RFC PATCH 3/5] hw/pci-host/bonito: Remap PCI "lo" regions when PCIMAP reg is modified
On Fri, 1 Jan 2021 at 23:12, Philippe Mathieu-Daudé wrote:
>
> Per the datasheet (Chapter 5.7.1. "PCI address regions"),
> the PCIMAP register:
>
> Map the 64Mbyte regions marked "PCI_Lo" in the CPU's memory map,
> each of which can be assigned to any 64 Mbyte-aligned region of
> PCI memory. The address appearing on the PCI bus consists of the
> low 26 bits of the CPU physical address, with the high 6 bits
> coming from the appropriate base6 field. Each of the three regions
> is an independent window onto PCI memory, and can be positioned on
> any 64Mbyte boundary in PCI space.
>
> Remap the 3 regions on reset and when PCIMAP is updated.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 49
> 1 file changed, 36 insertions(+), 13 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
> index a99eced0657..c58eeaf504c 100644
> --- a/hw/pci-host/bonito.c
> +++ b/hw/pci-host/bonito.c
> @@ -137,6 +137,10 @@ FIELD(BONGENCFG, PCIQUEUE, 12, 1)
>
> /* 4. PCI address map control */
> #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
> +FIELD(PCIMAP, LO0, 0, 6)
> +FIELD(PCIMAP, LO1, 6, 6)
> +FIELD(PCIMAP, LO2, 12, 6)
> +FIELD(PCIMAP, 2G, 18, 1)
> #define BONITO_PCIMEMBASECFG(0x14 >> 2) /* 0x114 */
> #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
>
> @@ -237,6 +241,7 @@ struct BonitoState {
> qemu_irq *pic;
> PCIBonitoState *pci_dev;
> MemoryRegion pci_mem;
> +MemoryRegion pcimem_lo_alias[3];
> };
>
> #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
> @@ -245,6 +250,31 @@ OBJECT_DECLARE_SIMPLE_TYPE(BonitoState,
> BONITO_PCI_HOST_BRIDGE)
> #define TYPE_PCI_BONITO "Bonito"
> OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
>
> +static void bonito_remap(PCIBonitoState *s)
> +{
> +static const char *const region_name[3] = {
> +"pci.lomem0", "pci.lomem1", "pci.lomem2"
> +};
> +BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
> +
> +for (size_t i = 0; i < 3; i++) {
> +uint32_t offset = extract32(s->regs[BONITO_PCIMAP], 6 * i, 6) << 26;
> +
> +if (memory_region_is_mapped(>pcimem_lo_alias[i])) {
> +memory_region_del_subregion(get_system_memory(),
> +>pcimem_lo_alias[i]);
> +object_unparent(OBJECT(>pcimem_lo_alias[i]));
> +}
> +
> +memory_region_init_alias(>pcimem_lo_alias[i], OBJECT(s),
> + region_name[i], >pci_mem,
> + offset, 64 * MiB);
> +memory_region_add_subregion(get_system_memory(),
> +BONITO_PCILO_BASE + i * 64 * MiB,
> +>pcimem_lo_alias[i]);
> +}
Rather than delete-and-reinit-and-add, it's probably better to
just create the subregions once at device startup, and then use
memory_region_set_enabled() and memory_region_set_address()
to manipulate whether the subregion is visible and what address
in the system memory it is mapped at.
thanks
-- PMM
Re: [PATCH v2 3/8] hw/mips: Use address translation helper to handle ENVP_ADDR
On 1/1/21 9:38 PM, Philippe Mathieu-Daudé wrote: > On 12/15/20 7:41 AM, Jiaxun Yang wrote: >> It will signed extend vaddr properly. >> >> Signed-off-by: Jiaxun Yang >> --- >> hw/mips/fuloong2e.c | 24 +- >> hw/mips/malta.c | 62 ++--- >> 2 files changed, 43 insertions(+), 43 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH v2 6/8] target/mips/addr: Add translation helpers for KSEG1
On 1/1/21 9:42 PM, Philippe Mathieu-Daudé wrote: > On 12/15/20 7:45 AM, Jiaxun Yang wrote: >> It's useful for bootloader to do IO opreations. >> >> Signed-off-by: Jiaxun Yang >> --- >> target/mips/addr.c | 10 ++ >> target/mips/cpu.h | 2 ++ >> 2 files changed, 12 insertions(+) > > Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH v2 1/8] hw/mips: Make bootloader addresses unsgined
On 12/15/20 7:41 AM, Jiaxun Yang wrote: > Address should be unsigned anyway, otherwise it may carry > calculations wrongly. > > Signed-off-by: Jiaxun Yang > --- > hw/mips/fuloong2e.c | 12 ++-- > hw/mips/malta.c | 22 +++--- > 2 files changed, 17 insertions(+), 17 deletions(-) Tested-by: Philippe Mathieu-Daudé
[RFC PATCH 5/5] tests/integration: Test Fuloong2E IDE drive, run userspace commands
Boot rootfs build by Guenter Roeck [*]. Full test output: $ avocado --show=app,console run -t machine:fuloong2e tests/acceptance/ Fetching asset from tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_mips64el_fuloong2e Fetching asset from tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_mips64el_fuloong2e JOB ID : 4a89d17bd6fa596220113ea9b974412c37c6cf9a JOB LOG: /home/phil/avocado/job-results/job-2021-01-01T23.54-4a89d17/job.log (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_mips64el_fuloong2e: console: [0.00] Initializing cgroup subsys cpuset console: [0.00] Initializing cgroup subsys cpu console: [0.00] Initializing cgroup subsys cpuacct console: [0.00] Linux version 3.16.0-6-loongson-2e (debian-ker...@lists.debian.org) (gcc version 4.8.4 (Debian 4.8.4-1) ) #1 Debian 3.16.56-1+deb8u1 (2018-05-08) console: [0.00] memsize=256, highmemsize=0 console: [0.00] CpuClock = 1 console: [0.00] bootconsole [early0] enabled console: [0.00] CPU0 revision is: 6302 (ICT Loongson-2) console: [0.00] FPU revision is: 0501 console: [0.00] Checking for the multiply/shift bug... no. console: [0.00] Checking for the daddiu bug... no. console: [0.00] Determined physical RAM map: console: [0.00] memory: 1000 @ (usable) console: [0.00] memory: 0400 @ 1000 (reserved) console: [0.00] memory: 03ff @ 1c01 (reserved) console: [0.00] Initrd not found or empty - disabling initrd console: [0.00] Zone ranges: console: [0.00] DMA [mem 0x-0x00ff] console: [0.00] Normal [mem 0x0100-0x0fff] console: [0.00] Movable zone start for each node console: [0.00] Early memory node ranges console: [0.00] node 0: [mem 0x-0x0fff] console: [0.00] Reserving 0MB of memory at 0MB for crashkernel console: [0.00] Primary instruction cache 64kB, VIPT, direct mapped, linesize 32 bytes. console: [0.00] Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 32 bytes console: [0.00] Unified secondary cache 512kB 4-way, linesize 32 bytes. console: [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16327 console: [0.00] Kernel command line: printk.time=0 console=ttyS0 root=/dev/sda ro panic=-1 noreboot console: PID hash table entries: 1024 (order: -1, 8192 bytes) console: Dentry cache hash table entries: 32768 (order: 4, 262144 bytes) console: Inode-cache hash table entries: 16384 (order: 3, 131072 bytes) console: Memory: 250752K/262144K available (5597K kernel code, 716K rwdata, 1548K rodata, 480K init, 581K bss, 11392K reserved) console: NR_IRQS:128 console: Console: colour dummy device 80x25 console: Calibrating delay loop... 118.60 BogoMIPS (lpj=237216) console: pid_max: default: 32768 minimum: 301 console: Security Framework initialized console: AppArmor: AppArmor disabled by boot time parameter console: Yama: disabled by default; enable with sysctl kernel.yama.* console: Mount-cache hash table entries: 2048 (order: 0, 16384 bytes) console: Mountpoint-cache hash table entries: 2048 (order: 0, 16384 bytes) console: Initializing cgroup subsys memory console: Initializing cgroup subsys devices console: Initializing cgroup subsys freezer console: Initializing cgroup subsys net_cls console: Initializing cgroup subsys blkio console: Initializing cgroup subsys perf_event console: Initializing cgroup subsys net_prio console: Checking for the daddi bug... no. console: ftrace: allocating 17617 entries in 18 pages console: devtmpfs: initialized console: futex hash table entries: 256 (order: -2, 6144 bytes) console: NET: Registered protocol family 16 console: vgaarb: loaded console: SCSI subsystem initialized console: PCI host bridge to bus :00 console: pci_bus :00: root bus resource [mem 0x1400-0x1c00] console: pci_bus :00: root bus resource [io 0x4000-0x] console: pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] console: via686b fix: ISA bridge console: via686b fix: ISA bridge done console: pci :00:05.1: legacy IDE quirk: reg 0x10: [io 0x01f0-0x01f7] console: pci :00:05.1: legacy IDE quirk: reg 0x14: [io 0x03f6] console: pci :00:05.1: legacy IDE quirk: reg 0x18: [io 0x0170-0x0177] console: pci :00:05.1: legacy IDE quirk: reg 0x1c: [io 0x0376] console: via686b fix: IDE console: via686b fix: IDE done console: pci :00:05.4: quirk: [io 0xeee0-0xeeef] claimed by vt82c686 SMB console: pci :00:07.0: BAR 6: assigned [mem 0x1400-0x1403 pref] console: pci :00:07.0: BAR 0: assigned [io
[RFC PATCH 4/5] tests/acceptance: Test boot_linux_console for fuloong2e
From: Jiaxun Yang
The kernel comes from debian archive so it's trusted.
Signed-off-by: Jiaxun Yang
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Willian Rampazzo
Reviewed-by: Huacai Chen
Message-Id: <20201224031750.52146-9-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/boot_linux_console.py | 21 +
1 file changed, 21 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index cc6ec0f8c15..fb41bb7144b 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -170,6 +170,27 @@ def test_mips64el_malta(self):
console_pattern = 'Kernel command line: %s' % kernel_command_line
self.wait_for_console_pattern(console_pattern)
+def test_mips64el_fuloong2e(self):
+"""
+:avocado: tags=arch:mips64el
+:avocado: tags=machine:fuloong2e
+:avocado: tags=endian:little
+"""
+deb_url = ('http://archive.debian.org/debian/pool/main/l/linux/'
+
'linux-image-3.16.0-6-loongson-2e_3.16.56-1+deb8u1_mipsel.deb')
+deb_hash = 'd04d446045deecf7b755ef576551de0c4184dd44'
+deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+kernel_path = self.extract_from_deb(deb_path,
+
'/boot/vmlinux-3.16.0-6-loongson-2e')
+
+self.vm.set_console()
+kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0'
+self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line)
+self.vm.launch()
+console_pattern = 'Kernel command line: %s' % kernel_command_line
+self.wait_for_console_pattern(console_pattern)
+
def test_mips_malta_cpio(self):
"""
:avocado: tags=arch:mips
--
2.26.2
[RFC PATCH 1/5] ide: Make room for flags in PCIIDEState and add one for legacy mode
From: BALATON Zoltan
We'll need a flag for implementing some device specific behaviour in
via-ide but we already have a currently CMD646 specific field that can
be repurposed for this and leave room for further flags if needed in
the future. This patch changes the "secondary" field to "flags" and
change CMD646 and its users accordingly and define a new flag for
forcing legacy mode that will be used by via-ide for now.
Signed-off-by: BALATON Zoltan
Tested-by: Guenter Roeck
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
Message-Id:
<28150c05831caea5926d4c6a881f448c2827703d.1609191252.git.bala...@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ide/pci.h | 7 ++-
hw/ide/cmd646.c | 6 +++---
hw/sparc64/sun4u.c | 2 +-
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h
index d8384e1c422..75d1a32f6d2 100644
--- a/include/hw/ide/pci.h
+++ b/include/hw/ide/pci.h
@@ -42,6 +42,11 @@ typedef struct BMDMAState {
#define TYPE_PCI_IDE "pci-ide"
OBJECT_DECLARE_SIMPLE_TYPE(PCIIDEState, PCI_IDE)
+enum {
+PCI_IDE_SECONDARY, /* used only for cmd646 */
+PCI_IDE_LEGACY_MODE
+};
+
struct PCIIDEState {
/*< private >*/
PCIDevice parent_obj;
@@ -49,7 +54,7 @@ struct PCIIDEState {
IDEBus bus[2];
BMDMAState bmdma[2];
-uint32_t secondary; /* used only for cmd646 */
+uint32_t flags;
MemoryRegion bmdma_bar;
MemoryRegion cmd_bar[2];
MemoryRegion data_bar[2];
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index c2546314855..cfea7fca06f 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -255,8 +255,8 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error
**errp)
pci_conf[PCI_CLASS_PROG] = 0x8f;
-pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
-if (d->secondary) {
+pci_conf[CNTRL] = CNTRL_EN_CH0; /* enable IDE0 */
+if (d->flags & BIT(PCI_IDE_SECONDARY)) {
/* XXX: if not enabled, really disable the seconday IDE controller */
pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
}
@@ -314,7 +314,7 @@ static void pci_cmd646_ide_exitfn(PCIDevice *dev)
}
static Property cmd646_ide_properties[] = {
-DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
+DEFINE_PROP_BIT("secondary", PCIIDEState, flags, PCI_IDE_SECONDARY, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 0fa13a73302..c46baa9f489 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -674,7 +674,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
}
pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
-qdev_prop_set_uint32(_dev->qdev, "secondary", 1);
+qdev_prop_set_bit(_dev->qdev, "secondary", true);
pci_realize_and_unref(pci_dev, pci_busA, _fatal);
pci_ide_create_devs(pci_dev);
--
2.26.2
[RFC PATCH 2/5] via-ide: Fix fuloong2e support
From: Guenter Roeck
The IDE legacy mode emulation has been removed in commit 4ea98d317eb
("ide/via: Implement and use native PCI IDE mode") but some Linux
kernels (probably including def_config) require legacy mode on the
Fuloong2e so only emulating native mode did not turn out feasible.
Add property to via-ide model to make the mode configurable, and set
legacy mode for Fuloong2e.
[balaton: Use bit in flags for property, add comment for missing BAR4]
Signed-off-by: Guenter Roeck
Signed-off-by: BALATON Zoltan
Tested-by: Guenter Roeck
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Message-Id:
<17a50e58e6baa26440c7dac83f07fdbba1595439.1609191252.git.bala...@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/via.c| 19 +--
hw/mips/fuloong2e.c | 4 +++-
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index be09912b334..2d935b910f8 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
+#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
@@ -185,12 +186,19 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
>bus[1], "via-ide1-cmd", 4);
pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, >cmd_bar[1]);
-bmdma_setup_bar(d);
-pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, >bmdma_bar);
+if (!(d->flags & BIT(PCI_IDE_LEGACY_MODE))) {
+/* Missing BAR4 will make Linux driver fall back to legacy PIO mode */
+bmdma_setup_bar(d);
+pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, >bmdma_bar);
+}
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_new(>bus[i], sizeof(d->bus[i]), ds, i, 2);
+if (d->flags & BIT(PCI_IDE_LEGACY_MODE)) {
+ide_init_ioport(>bus[i], NULL, i ? 0x170 : 0x1f0,
+i ? 0x376 : 0x3f6);
+}
ide_init2(>bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(>bus[i], >bmdma[i], d);
@@ -210,6 +218,12 @@ static void via_ide_exitfn(PCIDevice *dev)
}
}
+static Property via_ide_properties[] = {
+DEFINE_PROP_BIT("legacy-mode", PCIIDEState, flags, PCI_IDE_LEGACY_MODE,
+false),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void via_ide_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -223,6 +237,7 @@ static void via_ide_class_init(ObjectClass *klass, void
*data)
k->device_id = PCI_DEVICE_ID_VIA_IDE;
k->revision = 0x06;
k->class_id = PCI_CLASS_STORAGE_IDE;
+device_class_set_props(dc, via_ide_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 45c596f4fe5..d334fde389f 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -253,7 +253,9 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int
slot, qemu_irq intc,
/* Super I/O */
isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
-dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide");
+dev = pci_new(PCI_DEVFN(slot, 1), "via-ide");
+qdev_prop_set_bit(>qdev, "legacy-mode", true);
+pci_realize_and_unref(dev, pci_bus, _fatal);
pci_ide_create_devs(dev);
pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci");
--
2.26.2
[RFC PATCH 3/5] hw/pci-host/bonito: Remap PCI "lo" regions when PCIMAP reg is modified
Per the datasheet (Chapter 5.7.1. "PCI address regions"),
the PCIMAP register:
Map the 64Mbyte regions marked "PCI_Lo" in the CPU's memory map,
each of which can be assigned to any 64 Mbyte-aligned region of
PCI memory. The address appearing on the PCI bus consists of the
low 26 bits of the CPU physical address, with the high 6 bits
coming from the appropriate base6 field. Each of the three regions
is an independent window onto PCI memory, and can be positioned on
any 64Mbyte boundary in PCI space.
Remap the 3 regions on reset and when PCIMAP is updated.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/bonito.c | 49
1 file changed, 36 insertions(+), 13 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index a99eced0657..c58eeaf504c 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -137,6 +137,10 @@ FIELD(BONGENCFG, PCIQUEUE, 12, 1)
/* 4. PCI address map control */
#define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
+FIELD(PCIMAP, LO0, 0, 6)
+FIELD(PCIMAP, LO1, 6, 6)
+FIELD(PCIMAP, LO2, 12, 6)
+FIELD(PCIMAP, 2G, 18, 1)
#define BONITO_PCIMEMBASECFG(0x14 >> 2) /* 0x114 */
#define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
@@ -237,6 +241,7 @@ struct BonitoState {
qemu_irq *pic;
PCIBonitoState *pci_dev;
MemoryRegion pci_mem;
+MemoryRegion pcimem_lo_alias[3];
};
#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
@@ -245,6 +250,31 @@ OBJECT_DECLARE_SIMPLE_TYPE(BonitoState,
BONITO_PCI_HOST_BRIDGE)
#define TYPE_PCI_BONITO "Bonito"
OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
+static void bonito_remap(PCIBonitoState *s)
+{
+static const char *const region_name[3] = {
+"pci.lomem0", "pci.lomem1", "pci.lomem2"
+};
+BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
+
+for (size_t i = 0; i < 3; i++) {
+uint32_t offset = extract32(s->regs[BONITO_PCIMAP], 6 * i, 6) << 26;
+
+if (memory_region_is_mapped(>pcimem_lo_alias[i])) {
+memory_region_del_subregion(get_system_memory(),
+>pcimem_lo_alias[i]);
+object_unparent(OBJECT(>pcimem_lo_alias[i]));
+}
+
+memory_region_init_alias(>pcimem_lo_alias[i], OBJECT(s),
+ region_name[i], >pci_mem,
+ offset, 64 * MiB);
+memory_region_add_subregion(get_system_memory(),
+BONITO_PCILO_BASE + i * 64 * MiB,
+>pcimem_lo_alias[i]);
+}
+}
+
static void bonito_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -260,7 +290,6 @@ static void bonito_writel(void *opaque, hwaddr addr,
case BONITO_BONPONCFG:
case BONITO_IODEVCFG:
case BONITO_SDCFG:
-case BONITO_PCIMAP:
case BONITO_PCIMEMBASECFG:
case BONITO_PCIMAP_CFG:
case BONITO_GPIODATA:
@@ -282,6 +311,10 @@ static void bonito_writel(void *opaque, hwaddr addr,
case BONITO_MEMSIZE:
s->regs[saddr] = val;
break;
+case BONITO_PCIMAP:
+s->regs[saddr] = val;
+bonito_remap(s);
+break;
case BONITO_BONGENCFG:
if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
reset = 1; /* bit 2 jump from 0 to 1 cause reset */
@@ -610,6 +643,8 @@ static void bonito_reset(void *opaque)
s->regs[BONITO_DQCFG] = 0x8;
s->regs[BONITO_MEMSIZE] = 0x1000;
s->regs[BONITO_PCIMAP] = 0x6140;
+
+bonito_remap(s);
}
static const VMStateDescription vmstate_bonito = {
@@ -626,7 +661,6 @@ static void bonito_pcihost_realize(DeviceState *dev, Error
**errp)
{
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
-MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
memory_region_init(>pci_mem, OBJECT(dev), "pci.mem",
BONITO_PCIHI_SIZE);
phb->bus = pci_register_root_bus(dev, "pci",
@@ -634,17 +668,6 @@ static void bonito_pcihost_realize(DeviceState *dev, Error
**errp)
dev, >pci_mem, get_system_io(),
0x28, 32, TYPE_PCI_BUS);
-for (size_t i = 0; i < 3; i++) {
-char *name = g_strdup_printf("pci.lomem%zu", i);
-
-memory_region_init_alias(_lo_alias[i], NULL, name,
- >pci_mem, i * 64 * MiB, 64 * MiB);
-memory_region_add_subregion(get_system_memory(),
-BONITO_PCILO_BASE + i * 64 * MiB,
-_lo_alias[i]);
-g_free(name);
-}
-
create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
}
--
2.26.2
[RFC PATCH 0/5] hw/mips: Fix Fuloong2E to boot Linux guest again
We closed 2020 with few discussions about the Fuloong 2E board (see [1] and [2]). This series collect the minimum set of patch to have the machine booting Linux guest again, including integration tests. This is sent as RFC because Mark raised some issues in (see [3] and previous in this thread) and I don't understand PCI enough to intervene. Peter commented a similar PCI issue with the Sam460ex [4] so might be able to help us here. Anyhow, sharing this PoC on the list with the test, the avoid boring manual testing. Regards, Phil. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769105.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769557.html [3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769593.html [4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg769697.html BALATON Zoltan (1): ide: Make room for flags in PCIIDEState and add one for legacy mode Guenter Roeck (1): via-ide: Fix fuloong2e support Jiaxun Yang (1): tests/acceptance: Test boot_linux_console for fuloong2e Philippe Mathieu-Daudé (2): hw/pci-host/bonito: Remap PCI "lo" regions when PCIMAP reg is modified tests/integration: Test Fuloong2E IDE drive, run userspace commands include/hw/ide/pci.h | 7 +++- hw/ide/cmd646.c| 6 ++-- hw/ide/via.c | 19 -- hw/mips/fuloong2e.c| 4 ++- hw/pci-host/bonito.c | 49 +++--- hw/sparc64/sun4u.c | 2 +- tests/acceptance/boot_linux_console.py | 47 7 files changed, 113 insertions(+), 21 deletions(-) -- 2.26.2
Re: [PATCH v2 09/10] vt82c686: Convert debug printf to trace points
On Fri, 1 Jan 2021, Philippe Mathieu-Daudé wrote:
On 12/28/20 3:08 AM, BALATON Zoltan via wrote:
Drop DPRINTF and use trace functions instead. Two debug messages about
unimplemented registers could be converted to qemu_log_mask() but in
reality all registers are currently unimplemented (we just store and
return values of writable regs but do nothing with them). As we
already trace register access there's no need for additional debug
messages so these are just removed and a comment is added as a reminder.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
v2: Extended commit message
hw/isa/trace-events | 6 ++
hw/isa/vt82c686.c | 51 +
2 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/hw/isa/trace-events b/hw/isa/trace-events
index 3544c6213c..d267d3e652 100644
--- a/hw/isa/trace-events
+++ b/hw/isa/trace-events
@@ -13,3 +13,9 @@ pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x
val=0x%x"
# apm.c
apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
+
+# vt82c686.c
+via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
+via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index cd87ec0103..d7ce15bf9f 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -27,14 +27,7 @@
#include "qemu/timer.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
-
-/* #define DEBUG_VT82C686B */
-
-#ifdef DEBUG_VT82C686B
-#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
-#else
-#define DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
typedef struct SuperIOConfig {
uint8_t config[0x100];
@@ -55,12 +48,12 @@ static void superio_ioport_writeb(void *opaque, hwaddr
addr, uint64_t data,
{
SuperIOConfig *superio_conf = opaque;
-DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
-if (addr == 0x3f0) {
+if (addr == 0x3f0) { /* config index register */
superio_conf->index = data & 0xff;
} else {
bool can_write = true;
-/* 0x3f1 */
+/* 0x3f1, config data register */
+trace_via_superio_write(superio_conf->index, data & 0xff);
switch (superio_conf->index) {
case 0x00 ... 0xdf:
case 0xe4:
@@ -73,18 +66,7 @@ static void superio_ioport_writeb(void *opaque, hwaddr addr,
uint64_t data,
case 0xfd ... 0xff:
can_write = false;
break;
-case 0xe7:
-if ((data & 0xff) != 0xfe) {
-DPRINTF("change uart 1 base. unsupported yet\n");
-can_write = false;
-}
-break;
-case 0xe8:
-if ((data & 0xff) != 0xbe) {
-DPRINTF("change uart 2 base. unsupported yet\n");
-can_write = false;
-}
-break;
+/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
If you don't mind I'll prepend this patch:
-- >8 --
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index cd87ec01039..23b4deaac93 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -25,6 +25,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
+#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
@@ -73,17 +74,9 @@ static void superio_ioport_writeb(void *opaque,
hwaddr addr, uint64_t data,
case 0xfd ... 0xff:
can_write = false;
break;
-case 0xe7:
-if ((data & 0xff) != 0xfe) {
-DPRINTF("change uart 1 base. unsupported yet\n");
-can_write = false;
-}
-break;
-case 0xe8:
-if ((data & 0xff) != 0xbe) {
-DPRINTF("change uart 2 base. unsupported yet\n");
-can_write = false;
-}
+case 0xe6 ... 0xe8: /* set base port of parallel and serial */
+qemu_log_mask(LOG_UNIMP, "change base port not implemented\n");
+can_write = false;
Actually I won't add this log becuse in later patches I've added logging
for all unimplemented regs here and implemented changing base for serial
(needed for pegasos2 which puts the single serial port at 0x2f8). Still
want this patch spit into too?
Regards,
BALATON Zoltan
Re: [PATCH v2 09/10] vt82c686: Convert debug printf to trace points
On Fri, 1 Jan 2021, Philippe Mathieu-Daudé wrote:
On 12/28/20 3:08 AM, BALATON Zoltan via wrote:
Drop DPRINTF and use trace functions instead. Two debug messages about
unimplemented registers could be converted to qemu_log_mask() but in
reality all registers are currently unimplemented (we just store and
return values of writable regs but do nothing with them). As we
already trace register access there's no need for additional debug
messages so these are just removed and a comment is added as a reminder.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
v2: Extended commit message
hw/isa/trace-events | 6 ++
hw/isa/vt82c686.c | 51 +
2 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/hw/isa/trace-events b/hw/isa/trace-events
index 3544c6213c..d267d3e652 100644
--- a/hw/isa/trace-events
+++ b/hw/isa/trace-events
@@ -13,3 +13,9 @@ pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x
val=0x%x"
# apm.c
apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
+
+# vt82c686.c
+via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
+via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index cd87ec0103..d7ce15bf9f 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -27,14 +27,7 @@
#include "qemu/timer.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
-
-/* #define DEBUG_VT82C686B */
-
-#ifdef DEBUG_VT82C686B
-#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
-#else
-#define DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
typedef struct SuperIOConfig {
uint8_t config[0x100];
@@ -55,12 +48,12 @@ static void superio_ioport_writeb(void *opaque, hwaddr
addr, uint64_t data,
{
SuperIOConfig *superio_conf = opaque;
-DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
-if (addr == 0x3f0) {
+if (addr == 0x3f0) { /* config index register */
superio_conf->index = data & 0xff;
} else {
bool can_write = true;
-/* 0x3f1 */
+/* 0x3f1, config data register */
+trace_via_superio_write(superio_conf->index, data & 0xff);
switch (superio_conf->index) {
case 0x00 ... 0xdf:
case 0xe4:
@@ -73,18 +66,7 @@ static void superio_ioport_writeb(void *opaque, hwaddr addr,
uint64_t data,
case 0xfd ... 0xff:
can_write = false;
break;
-case 0xe7:
-if ((data & 0xff) != 0xfe) {
-DPRINTF("change uart 1 base. unsupported yet\n");
-can_write = false;
-}
-break;
-case 0xe8:
-if ((data & 0xff) != 0xbe) {
-DPRINTF("change uart 2 base. unsupported yet\n");
-can_write = false;
-}
-break;
+/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
If you don't mind I'll prepend this patch:
I'll split it. I've finished rewriting vt82c686b to add vt8231 emulation
and ended up with a 24 patch series. This'll make it 25. This includes all
of part I and part II I've already posted and some more. Fuloong2e still
seems to work (with the Bonito fix) at least with PMON and pegasos2
firmware also runs and starts to boot but MorphOS does not fully boot for
some reason but I'm not sure if it's because of some other change or a bug
somewhere in this series. I need to do more testing but I think I'll
submit this series now anyway so it can be reviewed in the meantime and I
can make changes in next iteration and don't need too many versions
because I'll have less time for it now.
Regards and happy new year,
BALATON Zoltan
-- >8 --
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index cd87ec01039..23b4deaac93 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -25,6 +25,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
+#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
@@ -73,17 +74,9 @@ static void superio_ioport_writeb(void *opaque,
hwaddr addr, uint64_t data,
case 0xfd ... 0xff:
can_write = false;
break;
-case 0xe7:
-if ((data & 0xff) != 0xfe) {
-DPRINTF("change uart 1 base. unsupported yet\n");
-can_write = false;
-}
-break;
-case 0xe8:
-if ((data & 0xff) != 0xbe) {
-DPRINTF("change uart 2 base. unsupported yet\n");
-can_write = false;
-}
+case 0xe6 ... 0xe8: /* set base port of parallel and serial */
+
Re: [PATCH v2 09/10] vt82c686: Convert debug printf to trace points
On 12/28/20 3:08 AM, BALATON Zoltan via wrote:
> Drop DPRINTF and use trace functions instead. Two debug messages about
> unimplemented registers could be converted to qemu_log_mask() but in
> reality all registers are currently unimplemented (we just store and
> return values of writable regs but do nothing with them). As we
> already trace register access there's no need for additional debug
> messages so these are just removed and a comment is added as a reminder.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
> ---
> v2: Extended commit message
>
> hw/isa/trace-events | 6 ++
> hw/isa/vt82c686.c | 51 +
> 2 files changed, 21 insertions(+), 36 deletions(-)
>
> diff --git a/hw/isa/trace-events b/hw/isa/trace-events
> index 3544c6213c..d267d3e652 100644
> --- a/hw/isa/trace-events
> +++ b/hw/isa/trace-events
> @@ -13,3 +13,9 @@ pc87312_io_write(uint32_t addr, uint32_t val) "write
> addr=0x%x val=0x%x"
> # apm.c
> apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
> apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
> +
> +# vt82c686.c
> +via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
> 0x%x"
> +via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
> 0x%x"
> +via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
> +via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"
> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> index cd87ec0103..d7ce15bf9f 100644
> --- a/hw/isa/vt82c686.c
> +++ b/hw/isa/vt82c686.c
> @@ -27,14 +27,7 @@
> #include "qemu/timer.h"
> #include "exec/address-spaces.h"
> #include "qom/object.h"
> -
> -/* #define DEBUG_VT82C686B */
> -
> -#ifdef DEBUG_VT82C686B
> -#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__,
> ##__VA_ARGS__)
> -#else
> -#define DPRINTF(fmt, ...)
> -#endif
> +#include "trace.h"
>
> typedef struct SuperIOConfig {
> uint8_t config[0x100];
> @@ -55,12 +48,12 @@ static void superio_ioport_writeb(void *opaque, hwaddr
> addr, uint64_t data,
> {
> SuperIOConfig *superio_conf = opaque;
>
> -DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
> -if (addr == 0x3f0) {
> +if (addr == 0x3f0) { /* config index register */
> superio_conf->index = data & 0xff;
> } else {
> bool can_write = true;
> -/* 0x3f1 */
> +/* 0x3f1, config data register */
> +trace_via_superio_write(superio_conf->index, data & 0xff);
> switch (superio_conf->index) {
> case 0x00 ... 0xdf:
> case 0xe4:
> @@ -73,18 +66,7 @@ static void superio_ioport_writeb(void *opaque, hwaddr
> addr, uint64_t data,
> case 0xfd ... 0xff:
> can_write = false;
> break;
> -case 0xe7:
> -if ((data & 0xff) != 0xfe) {
> -DPRINTF("change uart 1 base. unsupported yet\n");
> -can_write = false;
> -}
> -break;
> -case 0xe8:
> -if ((data & 0xff) != 0xbe) {
> -DPRINTF("change uart 2 base. unsupported yet\n");
> -can_write = false;
> -}
> -break;
> +/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
If you don't mind I'll prepend this patch:
-- >8 --
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index cd87ec01039..23b4deaac93 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -25,6 +25,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
+#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
@@ -73,17 +74,9 @@ static void superio_ioport_writeb(void *opaque,
hwaddr addr, uint64_t data,
case 0xfd ... 0xff:
can_write = false;
break;
-case 0xe7:
-if ((data & 0xff) != 0xfe) {
-DPRINTF("change uart 1 base. unsupported yet\n");
-can_write = false;
-}
-break;
-case 0xe8:
-if ((data & 0xff) != 0xbe) {
-DPRINTF("change uart 2 base. unsupported yet\n");
-can_write = false;
-}
+case 0xe6 ... 0xe8: /* set base port of parallel and serial */
+qemu_log_mask(LOG_UNIMP, "change base port not implemented\n");
+can_write = false;
break;
default:
break;
---
Re: [PATCH v2 06/10] audio/via-ac97: Simplify code and set user_creatable to false
On 12/28/20 3:08 AM, BALATON Zoltan via wrote: > Remove some unneded, empty code and set user_creatable to false > (besides being not implemented yet, so does nothing anyway) it's also > normally part of VIA south bridge chips so no need to confuse users > showing them these devices. > > Signed-off-by: BALATON Zoltan > --- > hw/audio/via-ac97.c | 51 + > 1 file changed, 19 insertions(+), 32 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2 04/10] vt82c686: Remove vt82c686b_[am]c97_init() functions
On 12/28/20 3:08 AM, BALATON Zoltan via wrote: > These are legacy init functions that are just equivalent to directly > calling pci_create_simple so do that instead. Also rename objects to > lower case via-ac97 and via-mc97 matching naming of other devices. > > Signed-off-by: BALATON Zoltan > --- > hw/isa/vt82c686.c | 27 --- > hw/mips/fuloong2e.c | 4 ++-- > include/hw/isa/vt82c686.h | 4 ++-- > 3 files changed, 8 insertions(+), 27 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 04/12] vt82c686: Remove vt82c686b_[am]c97_init() functions
On 12/27/20 2:10 AM, BALATON Zoltan via wrote: > These are legacy init functions that are just equivalent to directly > calling pci_create_simple so do that instead. Also rename objects to > lower case via-ac97 and via-mc97 matching naming of other devices. > > Signed-off-by: BALATON Zoltan > --- > hw/isa/vt82c686.c | 27 --- > hw/mips/fuloong2e.c | 4 ++-- > include/hw/isa/vt82c686.h | 4 ++-- > 3 files changed, 8 insertions(+), 27 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v3 5/8] hw/mips/fuloong2e: Remove unused env entry
On 1/1/21 7:05 PM, Philippe Mathieu-Daudé wrote: > On 12/24/20 4:17 AM, Jiaxun Yang wrote: >> modetty is not handled by kernel and the parameter >> here seems unreasonable. >> >> Signed-off-by: Jiaxun Yang >> --- >> v3: Bring busclock back >> --- >> hw/mips/fuloong2e.c | 2 -- >> 1 file changed, 2 deletions(-) >> >> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c >> index d846ef7b00..c4843dd15e 100644 >> --- a/hw/mips/fuloong2e.c >> +++ b/hw/mips/fuloong2e.c >> @@ -159,10 +159,8 @@ static uint64_t load_kernel(CPUMIPSState *env) >> } >> >> /* Setup minimum environment variables */ >> -prom_set(prom_buf, index++, "busclock=3300"); Ah but you still removed busclock... This might explain why. >> prom_set(prom_buf, index++, "cpuclock=1"); >> prom_set(prom_buf, index++, "memsize=%"PRIi64, loaderparams.ram_size / >> MiB); >> -prom_set(prom_buf, index++, "modetty0=38400n8r"); >> prom_set(prom_buf, index++, NULL); > > This makes my Linux kernel 2.6 test behave oddly: > > (4/4) > tests/acceptance/machine_mips_fuloong2e.py:MipsFuloong2e.test_linux_kernel_isa_serial: > console: Linux version 2.6.27.7lemote (root@debian) (gcc version 4.1.3 > 20080623 (prerelease) (Debian 4.1.2-23)) #6 Fri Dec 12 00:11:25 CST 2008 > console: busclock=0, cpuclock=-2145008360,memsize=256,highmemsize=0 > console: console [early0] enabled > console: CPU revision is: 6302 (ICT Loongson-2) >
Re: [PATCH V19 4/5] hw/mips: Add Loongson-3 machine support
On 12/21/20 12:05 PM, Huacai Chen wrote: > Add Loongson-3 based machine support, it use liointc as the interrupt > controler and use GPEX as the pci controller. Currently it can work with > both TCG and KVM. > > As the machine model is not based on any exiting physical hardware, the > name of the machine is "loongson3-virt". It may be superseded in future > by a real machine model. If this happens, then a regular deprecation > procedure shall occur for "loongson3-virt" machine. > > We now already have a full functional Linux kernel (based on Linux-5.4.x > LTS) here: > > https://github.com/chenhuacai/linux > > Of course the upstream kernel is also usable (the kvm host side and > guest side have both been upstream in Linux-5.9): > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > > How to use QEMU/Loongson-3? > 1, Download kernel source from the above URL; > 2, Build a kernel with arch/mips/configs/loongson3_defconfig; > 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode); > 4, Build QEMU-master with this patchset; > 5, modprobe kvm (only necessary for KVM mode); > 6, Use QEMU with TCG: >qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 > -kernel -append ... >Use QEMU with KVM: >qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 > -kernel -append ... > >The "-cpu" parameter is optional here and QEMU will use the correct type > for TCG/KVM automatically. > > Signed-off-by: Huacai Chen > Co-developed-by: Jiaxun Yang > Signed-off-by: Jiaxun Yang > --- > MAINTAINERS | 1 + > default-configs/devices/mips64el-softmmu.mak | 1 + > hw/mips/Kconfig | 11 + > hw/mips/loongson3_virt.c | 621 +++ > hw/mips/meson.build | 2 +- > 5 files changed, 635 insertions(+), 1 deletion(-) > create mode 100644 hw/mips/loongson3_virt.c Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH V19 3/5] hw/mips: Add Loongson-3 boot parameter helpers
On 12/21/20 12:05 PM, Huacai Chen wrote:
> Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Huacai Chen
> Co-developed-by: Jiaxun Yang
> Signed-off-by: Jiaxun Yang
> ---
> MAINTAINERS | 2 +
> hw/mips/loongson3_bootp.c | 151
> hw/mips/loongson3_bootp.h | 241 ++
> hw/mips/meson.build | 1 +
> 4 files changed, 395 insertions(+)
> create mode 100644 hw/mips/loongson3_bootp.c
> create mode 100644 hw/mips/loongson3_bootp.h
...
> +struct MemmapEntry {
> +hwaddr base;
> +hwaddr size;
> +};
> +
> +extern const struct MemmapEntry virt_memmap[];
I'd rather avoid this extern (pass MemmapEntry as argument?).
Anyhow, not a big deal ;)
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2 6/8] target/mips/addr: Add translation helpers for KSEG1
On 12/15/20 7:45 AM, Jiaxun Yang wrote: > It's useful for bootloader to do IO opreations. > > Signed-off-by: Jiaxun Yang > --- > target/mips/addr.c | 10 ++ > target/mips/cpu.h | 2 ++ > 2 files changed, 12 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2 2/8] hw/mips/malta: Use address translation helper to calculate bootloader_run_addr
On 12/15/20 7:41 AM, Jiaxun Yang wrote: > So it will sign extend adresses properly. > > Signed-off-by: Jiaxun Yang > --- > hw/mips/malta.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2 3/8] hw/mips: Use address translation helper to handle ENVP_ADDR
On 12/15/20 7:41 AM, Jiaxun Yang wrote: > It will signed extend vaddr properly. > > Signed-off-by: Jiaxun Yang > --- > hw/mips/fuloong2e.c | 24 +- > hw/mips/malta.c | 62 ++--- > 2 files changed, 43 insertions(+), 43 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2 0/4] clock: Get rid of clock_get_ns()
On 12/15/20 4:09 PM, Peter Maydell wrote: > This patchseries makes some changes to the clock API: > * Remove clock_get_ns() > * Add clock_ticks_to_ns() to return number of nanoseconds >it will take the clock to tick N times > * clock_display_freq() to return prettily-formatted string >for showing humans the approximate clock frequency > > This is based on discussions we had about these APIs a little while > back. The core driver here is that the clock objects internally > store the period in units of 2^-32 ns, so both clock_get_ns() and > clock_get_hz() are inherently returning a rounded-off result, which > can be badly inaccurate for fast clocks or if you want to multiply it > by a large tick count. ... > Peter Maydell (4): > clock: Introduce clock_ticks_to_ns() > target/mips: Don't use clock_get_ns() in clock period calculation > clock: Remove clock_get_ns() > clock: Define and use new clock_display_freq() > > docs/devel/clocks.rst | 51 > include/hw/clock.h | 53 +++--- > hw/core/clock.c| 6 + > softmmu/qdev-monitor.c | 6 ++--- > target/mips/cpu.c | 4 ++-- > 5 files changed, 108 insertions(+), 12 deletions(-) Until someone else prefers otherwise, I plan to queue this series via the MIPS tree, as I can add the patch which increases the Loongson3v frequency to 2GHz on top (the unique machine using a frequency over 1GHz). Thanks, Phil.
Re: [PULL 00/55] Misc patches for 2020-12-21
Il ven 1 gen 2021, 18:05 Peter Maydell ha scritto: > (why does it print the same failure three times rather than > stopping after the first one?) > It probably has something to do with how make processes rules to rebuild makefiles. I will remove the patch that moves xgettext from boolean to feature and then try to reproduce the failure. Paolo > thanks > -- PMM > >
Re: [PULL 00/14] s390x update
On Tue, 22 Dec 2020 at 10:45, Cornelia Huck wrote: > > The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8: > > Merge remote-tracking branch > 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging > (2020-12-18 11:12:35 +) > > are available in the Git repository at: > > https://gitlab.com/cohuck/qemu.git tags/s390x-20201222 > > for you to fetch changes up to 24bfaae13958b823a4f33b70fca52f086851641f: > > tests/acceptance: Add a test with the Fedora 31 kernel and initrd > (2020-12-22 09:23:09 +0100) > > > Further s390x updates: > - enhance the s390 devices acceptance test > - tcg: improve carry computation > - qga: send the ccw address with the fsinfo data > - fixes for protected virtualisation and zpci > > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
Re: [PULL 0/5] fuzzer and gitlab-CI patches
On Mon, 21 Dec 2020 at 13:45, Thomas Huth wrote: > > Hi! > > The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2: > > Merge remote-tracking branch > 'remotes/ehabkost-gl/tags/x86-next-pull-request' > into staging (2020-12-17 18:53:36 +) > > are available in the Git repository at: > > https://gitlab.com/huth/qemu.git tags/pull-request-2020-12-21 > > for you to fetch changes up to df063546c2de1a5045e356253abd9a2e6e2bec6d: > > gitlab-ci: Archive logs of acceptance tests (2020-12-18 12:25:42 +0100) > > > * Two fuzzer patches from Alexander > * Show logs of failed acceptance jobs in the gitlab-CI > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
Re: [PATCH v3 5/8] hw/mips/fuloong2e: Remove unused env entry
On 12/24/20 4:17 AM, Jiaxun Yang wrote: > modetty is not handled by kernel and the parameter > here seems unreasonable. > > Signed-off-by: Jiaxun Yang > --- > v3: Bring busclock back > --- > hw/mips/fuloong2e.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c > index d846ef7b00..c4843dd15e 100644 > --- a/hw/mips/fuloong2e.c > +++ b/hw/mips/fuloong2e.c > @@ -159,10 +159,8 @@ static uint64_t load_kernel(CPUMIPSState *env) > } > > /* Setup minimum environment variables */ > -prom_set(prom_buf, index++, "busclock=3300"); > prom_set(prom_buf, index++, "cpuclock=1"); > prom_set(prom_buf, index++, "memsize=%"PRIi64, loaderparams.ram_size / > MiB); > -prom_set(prom_buf, index++, "modetty0=38400n8r"); > prom_set(prom_buf, index++, NULL); This makes my Linux kernel 2.6 test behave oddly: (4/4) tests/acceptance/machine_mips_fuloong2e.py:MipsFuloong2e.test_linux_kernel_isa_serial: console: Linux version 2.6.27.7lemote (root@debian) (gcc version 4.1.3 20080623 (prerelease) (Debian 4.1.2-23)) #6 Fri Dec 12 00:11:25 CST 2008 console: busclock=0, cpuclock=-2145008360,memsize=256,highmemsize=0 console: console [early0] enabled console: CPU revision is: 6302 (ICT Loongson-2)
[Bug 1909823] [NEW] RDPMC check on PCE is backwards
Public bug reported: At [this line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225) the check on CR4_PCE_MASK is backwards: it's raising an exception if the flag is set (and CPL != 0) rather than if the flag is clear. It's low priority at the moment because the instruction isn't implemented, so you get an illegal opcode exception when expecting a GPF, or vice versa, but it's a time bomb for if it is ever implemented. The Intel docs also indicate that CR0.PE influences the protection; I don't know if that's already reflected in env->hflags & HF_CPL_MASK. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1909823 Title: RDPMC check on PCE is backwards Status in QEMU: New Bug description: At [this line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225) the check on CR4_PCE_MASK is backwards: it's raising an exception if the flag is set (and CPL != 0) rather than if the flag is clear. It's low priority at the moment because the instruction isn't implemented, so you get an illegal opcode exception when expecting a GPF, or vice versa, but it's a time bomb for if it is ever implemented. The Intel docs also indicate that CR0.PE influences the protection; I don't know if that's already reflected in env->hflags & HF_CPL_MASK. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1909823/+subscriptions
Re: [PULL 00/55] Misc patches for 2020-12-21
On Mon, 21 Dec 2020 at 14:51, Paolo Bonzini wrote: > > The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8: > > Merge remote-tracking branch > 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging > (2020-12-18 11:12:35 +) > > are available in the Git repository at: > > https://gitlab.com/bonzini/qemu.git tags/for-upstream > > for you to fetch changes up to 16efbeeb765944fdda71862b40d60f0abeb1e200: > > win32: drop fd registration to the main-loop on setting non-block > (2020-12-21 13:53:24 +0100) > > > From Alex's pull request: > * improve cross-build KVM coverage > * new --without-default-features configure flag > * add __repr__ for ConsoleSocket for debugging > * build tcg tests with -Werror > * test 32 bit builds with fedora > * remove last traces of debian9 > * hotfix for centos8 powertools repo > > * Move lots of feature detection code to meson (Alex, myself) > * CFI and LTO support (Daniele) > * test-char dangling pointer (Eduardo) > * Build system and win32 fixes (Marc-André) > * Initialization fixes (myself) > * TCG include cleanup (Richard, myself) > * x86 'int N' fix (Peter) Fails to build, all hosts: make: Entering directory '/home/ubuntu/qemu/build/all' (cd /home/ubuntu/qemu && GIT="git" ./scripts/git-submodule.sh update ui/keycodemapdb tests/fp/berkeley-testfloat-3 te sts/fp/berkeley-softfloat-3 meson dtc capstone slirp roms/SLOF) config-host.mak is out-of-date, running configure cross containers no NOTE: guest cross-compilers enabled: cc cc /usr/bin/ninja -v build.ninja && touch build.ninja.stamp [0/1] /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate /home/ubuntu/qemu /home/ubuntu/qemu/bui ld/all --backend ninja WARNING: Regenerating configuration from scratch. Reason: Coredata file '/home/ubuntu/qemu/build/all/meson-private/coredata.dat' references functions or classes that d on't exist. This probably means that it was generated with an old version of meson. The Meson build system Version: 0.56.0 Source dir: /home/ubuntu/qemu Build dir: /home/ubuntu/qemu/build/all Build type: native build ../../meson.build:1:0: ERROR: Value "true" (of type "string") for combo option "Localization of the GTK+ user interface" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto". A full log can be found at /home/ubuntu/qemu/build/all/meson-logs/meson-log.txt FAILED: build.ninja /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate /home/ubuntu/qemu /home/ubuntu/qemu/build/all --backend ninja ninja: error: rebuilding 'build.ninja': subcommand failed /usr/bin/ninja -v build.ninja && touch build.ninja.stamp [0/1] /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate /home/ubuntu/qemu /home/ubuntu/qemu/build/all --backend ninja WARNING: Regenerating configuration from scratch. Reason: Coredata file '/home/ubuntu/qemu/build/all/meson-private/coredata.dat' references functions or classes that don't exist. This probably means that it was generated with an old version of meson. The Meson build system Version: 0.56.0 Source dir: /home/ubuntu/qemu Build dir: /home/ubuntu/qemu/build/all Build type: native build ../../meson.build:1:0: ERROR: Value "true" (of type "string") for combo option "Localization of the GTK+ user interface" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto". A full log can be found at /home/ubuntu/qemu/build/all/meson-logs/meson-log.txt FAILED: build.ninja /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate /home/ubuntu/qemu /home/ubuntu/qemu/build/all --backend ninja ninja: error: rebuilding 'build.ninja': subcommand failed /usr/bin/ninja -v all | cat make -C pc-bios/s390-ccw/ V="1" TARGET_DIR="pc-bios/s390-ccw/" all make[1]: Entering directory '/home/ubuntu/qemu/build/all/pc-bios/s390-ccw' make[1]: Leaving directory '/home/ubuntu/qemu/build/all/pc-bios/s390-ccw' [0/1] /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate /home/ubuntu/qemu /home/ubuntu/qemu/build/all --backend ninja WARNING: Regenerating configuration from scratch. Reason: Coredata file '/home/ubuntu/qemu/build/all/meson-private/coredata.dat' references functions or classes that don't exist. This probably means that it was generated with an old version of meson. The Meson build system Version: 0.56.0 Source dir: /home/ubuntu/qemu Build dir: /home/ubuntu/qemu/build/all Build type: native build ../../meson.build:1:0: ERROR: Value "true" (of type "string") for combo option "Localization of the GTK+ user interface" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto". A full log can be found at /home/ubuntu/qemu/build/all/meson-logs/meson-log.txt ninja: error: rebuilding 'build.ninja': subcommand failed FAILED: build.ninja /usr/bin/python3 /home/ubuntu/qemu/meson/meson.py --internal regenerate
Re: [PATCH 21/25] esp: rename get_cmd_cb() to esp_select()
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > This better describes the purpose of the function. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PULL 00/33] QAPI patches patches for 2020-12-19
On Sat, 19 Dec 2020 at 10:55, Markus Armbruster wrote: > > The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8: > > Merge remote-tracking branch > 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging > (2020-12-18 11:12:35 +) > > are available in the Git repository at: > > git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2020-12-19 > > for you to fetch changes up to 4ac76ba414ecb94f086d73621775d8b38b6f0a43: > > qobject: Make QString immutable (2020-12-19 10:39:41 +0100) > > > QAPI patches patches for 2020-12-19 > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
Re: [PATCH 06/25] esp: introduce esp_get_tc() and esp_set_tc()
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > This simplifies reading and writing the TC register value without having to > manually shift each individual 8-bit value. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 34 ++ > 1 file changed, 22 insertions(+), 12 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 04/25] esp: add PDMA trace events
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > This will become more useful later when trying to debug mixed FIFO and PDMA > requests. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c| 6 ++ > hw/scsi/trace-events | 4 > 2 files changed, 10 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 03/25] esp: fix esp_reg_read() trace event
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > Move the trace event to the end of the function so that it correctly reports > the returned value if it doesn't come directly from the rregs array. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 18 -- > 1 file changed, 12 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 02/25] esp: add trace event when receiving a TI command
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > This enables us to determine whether the command being issued is for a DMA or > a > non-DMA transfer. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c| 1 + > hw/scsi/trace-events | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 01/25] esp: checkpatch fixes
On 12/30/20 4:37 PM, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 52 ++- > 1 file changed, 31 insertions(+), 21 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [Qemu-devel] [PULL 0/1] RDMA queue
On Fri, 18 Dec 2020 at 19:00, Marcel Apfelbaum wrote: > > The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8: > > Merge remote-tracking branch > 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging > (2020-12-18 11:12:35 +) > > are available in the Git repository at: > > https://github.com/marcel-apf/qemu tags/rdma-pull-request > > for you to fetch changes up to eed31bc5e2e9cc68626d51e7a10914dc52c370f8: > > contrib/rdmacm-mux: Fix error condition in hash_tbl_search_fd_by_ifid() > (2020-12-18 20:15:42 +0200) > > > RDMA queue > > * bug fix in contrib/rdmacm-mux > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
Re: [PATCH v3 4/8] hw/pci-host/bonito: Fixup pci.lomem mapping
在 2021/1/1 下午7:07, Philippe Mathieu-Daudé 写道:
On 12/24/20 4:17 AM, Jiaxun Yang wrote:
The original mapping had wrong base address.
TBO this rational is a bit scarce ;)
Yes. I was just trying to get Linux work as I was programing facing the
kernel,
not the hardware ;-(
I asked Loongson guys for a copy of Bonito 2E manual and they promised me
they'll give it to me after the holiday.
Thanks.
- Jiaxun
I sent a patch implementing the REMAP register:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg769751.html
If this isn't enough with a Linux kernel because it expects
the the Bonito being configured by the bootloader, then we
need to do the mapping in write_bootloader().
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 3fad470fc6..737ee131e1 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -85,9 +85,8 @@
#define BONITO_PCILO_BASE_VA0xb000
#define BONITO_PCILO_SIZE 0x0c00
#define BONITO_PCILO_TOP(BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
-#define BONITO_PCILO0_BASE 0x1000
-#define BONITO_PCILO1_BASE 0x1400
-#define BONITO_PCILO2_BASE 0x1800
+#define BONITO_PCILOx_BASE(x) (BONITO_PCILO_BASE + BONITO_PCILOx_SIZE * x)
+#define BONITO_PCILOx_SIZE 0x0400
#define BONITO_PCIHI_BASE 0x2000
#define BONITO_PCIHI_SIZE 0x6000
#define BONITO_PCIHI_TOP(BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
@@ -610,7 +609,7 @@ static void bonito_pcihost_realize(DeviceState *dev, Error
**errp)
{
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
-MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
+MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 1);
memory_region_init(>pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
phb->bus = pci_register_root_bus(dev, "pci",
@@ -622,9 +621,10 @@ static void bonito_pcihost_realize(DeviceState *dev, Error
**errp)
char *name = g_strdup_printf("pci.lomem%zu", i);
memory_region_init_alias(_lo_alias[i], NULL, name,
- >pci_mem, i * 64 * MiB, 64 * MiB);
+ >pci_mem, BONITO_PCILOx_BASE(i),
+ BONITO_PCILOx_SIZE);
memory_region_add_subregion(get_system_memory(),
-BONITO_PCILO_BASE + i * 64 * MiB,
+BONITO_PCILOx_BASE(i),
_lo_alias[i]);
g_free(name);
}
Re: [PULL 00/30] Block patches
On Fri, 18 Dec 2020 at 15:12, Max Reitz wrote: > > The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2: > > Merge remote-tracking branch > 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17 > 18:53:36 +) > > are available in the Git repository at: > > https://github.com/XanClic/qemu.git tags/pull-block-2020-12-18 > > for you to fetch changes up to 0e72078128229bf9efb542e396ab44bf91b91340: > > iotests: Fix _send_qemu_cmd with bash 5.1 (2020-12-18 12:47:38 +0100) > > > Block patches: > - New block filter: preallocate (which, on writes beyond an image file's > end, allocates big chunks of data so that such post-EOF writes will > occur less frequently) > - write-zeroes and block-status support for Quorum > - Implementation of truncate for the nvme block driver similarly to the > existing implementations for host block devices and iscsi devices > - Block layer refactoring: Drop the tighten_restrictions concept in the > block permission functions > - iotest fixes Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
Re: [PATCH v2 3/3] sam460ex: Clean up irq mapping
On Thu, 31 Dec 2020 at 20:55, BALATON Zoltan wrote: > The SoC is called 460EX (despite having a PPC 440 core not 460 one) but I > think you've looked at the right data sheet and it's just a typo. I also > don't know how the board is wired so I think in this case I prefer > dropping this patch and keeping the current code just for simplicity but > to avoid going through this again maybe we should add a comment saying why > it's working. Can you please suggest a text for such comment pointing to > the relevant part of pci_change_irq_level() you refer to above? I don't > think I understand it enough to document it. How about: /* * All four IRQ[ABCD] pins from all slots are tied to a single board * IRQ, so our mapping function here maps everything to IRQ 0. * The code in pci_change_irq_level() tracks the number of times * the mapped IRQ is asserted and deasserted, so if multiple devices * assert an IRQ at the same time the behaviour is correct. */ ? thanks -- PMM
Re: [PATCH v3 4/8] hw/pci-host/bonito: Fixup pci.lomem mapping
On 12/24/20 4:17 AM, Jiaxun Yang wrote:
> The original mapping had wrong base address.
TBO this rational is a bit scarce ;)
I sent a patch implementing the REMAP register:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg769751.html
If this isn't enough with a Linux kernel because it expects
the the Bonito being configured by the bootloader, then we
need to do the mapping in write_bootloader().
>
> Signed-off-by: Jiaxun Yang
> ---
> hw/pci-host/bonito.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
> index 3fad470fc6..737ee131e1 100644
> --- a/hw/pci-host/bonito.c
> +++ b/hw/pci-host/bonito.c
> @@ -85,9 +85,8 @@
> #define BONITO_PCILO_BASE_VA0xb000
> #define BONITO_PCILO_SIZE 0x0c00
> #define BONITO_PCILO_TOP(BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
> -#define BONITO_PCILO0_BASE 0x1000
> -#define BONITO_PCILO1_BASE 0x1400
> -#define BONITO_PCILO2_BASE 0x1800
> +#define BONITO_PCILOx_BASE(x) (BONITO_PCILO_BASE + BONITO_PCILOx_SIZE * x)
> +#define BONITO_PCILOx_SIZE 0x0400
> #define BONITO_PCIHI_BASE 0x2000
> #define BONITO_PCIHI_SIZE 0x6000
> #define BONITO_PCIHI_TOP(BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
> @@ -610,7 +609,7 @@ static void bonito_pcihost_realize(DeviceState *dev,
> Error **errp)
> {
> PCIHostState *phb = PCI_HOST_BRIDGE(dev);
> BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
> -MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
> +MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 1);
>
> memory_region_init(>pci_mem, OBJECT(dev), "pci.mem",
> BONITO_PCIHI_SIZE);
> phb->bus = pci_register_root_bus(dev, "pci",
> @@ -622,9 +621,10 @@ static void bonito_pcihost_realize(DeviceState *dev,
> Error **errp)
> char *name = g_strdup_printf("pci.lomem%zu", i);
>
> memory_region_init_alias(_lo_alias[i], NULL, name,
> - >pci_mem, i * 64 * MiB, 64 * MiB);
> + >pci_mem, BONITO_PCILOx_BASE(i),
> + BONITO_PCILOx_SIZE);
> memory_region_add_subregion(get_system_memory(),
> -BONITO_PCILO_BASE + i * 64 * MiB,
> +BONITO_PCILOx_BASE(i),
> _lo_alias[i]);
> g_free(name);
> }
>
Re: [PATCH v2] meson: fix ncurses detection on macOS
On 12/30/20 11:17 PM, Chris Hofstaedtler wrote:
> Without this, meson fails with "curses package not usable" when using ncurses
> 6.2. Apparently the wide functions (addwstr, etc) are hidden behind the extra
> define, and meson does not define it at that detection stage.
>
> Regression from b01a4fd3bd7d6f2 ("configure: Define NCURSES_WIDECHAR if we're
> using curses"). The meson conversion has seen many iterations of the curses
> check, so pinpointing the exact commit breaking this is not so easy.
>
> Signed-off-by: Chris Hofstaedtler
> Cc: Peter Maydell
> Cc: Philippe Mathieu-Daudé
> Cc: Samuel Thibault
> Cc: Yonggang Luo
> ---
> meson.build | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Suggested-by: Yonggang Luo
Reviewed-by: Philippe Mathieu-Daudé
