RE: [PATCH v4 6/6] vfio: defer to commit kvm irq routing when enable msi/msix

[Longpeng (Mike, Cloud Infrastructure Service Product Dept.)]

> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Friday, October 22, 2021 4:51 AM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
> 
> Cc: pbonz...@redhat.com; qemu-devel@nongnu.org; k...@vger.kernel.org; Gonglei
> (Arei) 
> Subject: Re: [PATCH v4 6/6] vfio: defer to commit kvm irq routing when enable
> msi/msix
> 
> On Thu, 14 Oct 2021 08:48:52 +0800
> "Longpeng(Mike)"  wrote:
> 
> > In migration resume phase, all unmasked msix vectors need to be
> > setup when loading the VF state. However, the setup operation would
> > take longer if the VM has more VFs and each VF has more unmasked
> > vectors.
> >
> > The hot spot is kvm_irqchip_commit_routes, it'll scan and update
> > all irqfds that are already assigned each invocation, so more
> > vectors means need more time to process them.
> >
> > vfio_pci_load_config
> >   vfio_msix_enable
> > msix_set_vector_notifiers
> >   for (vector = 0; vector < dev->msix_entries_nr; vector++) {
> > vfio_msix_vector_do_use
> >   vfio_add_kvm_msi_virq
> > kvm_irqchip_commit_routes <-- expensive
> >   }
> >
> > We can reduce the cost by only committing once outside the loop.
> > The routes are cached in kvm_state, we commit them first and then
> > bind irqfd for each vector.
> >
> > The test VM has 128 vcpus and 8 VF (each one has 65 vectors),
> > we measure the cost of the vfio_msix_enable for each VF, and
> > we can see 90+% costs can be reduce.
> >
> > VF  Count of irqfds[*]  OriginalWith this patch
> >
> > 1st   658   2
> > 2nd   130   15  2
> > 3rd   195   22  2
> > 4th   260   24  3
> > 5th   325   36  2
> > 6th   390   44  3
> > 7th   455   51  3
> > 8th   520   58  4
> > Total   258ms   21ms
> >
> > [*] Count of irqfds
> > How many irqfds that already assigned and need to process in this
> > round.
> >
> > The optimization can be applied to msi type too.
> >
> > Signed-off-by: Longpeng(Mike) 
> > ---
> >  hw/vfio/pci.c | 129
> ++
> >  hw/vfio/pci.h |   1 +
> >  2 files changed, 105 insertions(+), 25 deletions(-)
> >
> > diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> > index 0bd832b..dca2d0c 100644
> > --- a/hw/vfio/pci.c
> > +++ b/hw/vfio/pci.c
> > @@ -413,8 +413,6 @@ static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool
> msix)
> >  static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector
> *vector,
> >int vector_n, bool msix)
> >  {
> > -int virq;
> > -
> >  if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) {
> >  return;
> >  }
> > @@ -423,20 +421,31 @@ static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev,
> VFIOMSIVector *vector,
> >  return;
> >  }
> >
> > -virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev);
> > -if (virq < 0) {
> > +vector->virq = kvm_irqchip_add_deferred_msi_route(kvm_state, vector_n,
> > +  &vdev->pdev);
> > +if (vector->virq < 0) {
> >  event_notifier_cleanup(&vector->kvm_interrupt);
> > +vector->virq = -1;
> 
> Nit, it seems like all negative values are equivalent here, I don't
> think we need to explicitly set virq to -1 given that it's already < 0.
> 

OK.

> > +return;
> > +}
> > +
> > +if (vdev->defer_kvm_irq_routing) {
> > +/*
> > + * The vector->virq will be reset to -1 if we fail to add the
> > + * corresponding irqfd in vfio_commit_kvm_msi_virq_batch().
> > + */
> >  return;
> >  }
> >
> > +kvm_irqchip_commit_routes(kvm_state);
> > +
> >  if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state,
> &vector->kvm_interrupt,
> > -   NULL, virq) < 0) {
> > -kvm_irqchip_release_virq(kvm_state, virq);
> > +   NULL, vector->virq) < 0) {
> > +kvm_irqchip_release_virq(kvm_state, vector->virq);
> >  event_notifier_cleanup(&vector->kvm_interrupt);
> > +vector->virq = -1;
> >  return;
> >  }
> > -
> > -vector->virq = virq;
> >  }
> >
> >  static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector)
> > @@ -501,11 +510,13 @@ static int vfio_msix_vector_do_use(PCIDevice *pdev,
> unsigned int nr,
> >   * increase them as needed.
> >   */
> >  if (vdev->nr_vectors < nr + 1) {
> > -vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
> >  vdev->nr_vectors = nr + 1;
> > -ret = vfio_enable_vectors(vdev, true);
> > -if (ret) {
> > -error_report("vfio: failed to enable vectors, %d", ret);
> 

Re: [PATCH v5 3/4] docs: (further further) remove non-reference uses of single backticks

[Thomas Huth]

On 02/11/2021 19.43, John Snow wrote:

Signed-off-by: John Snow 
---
  docs/devel/build-system.rst | 21 +++--
  1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst
index 7f106d2f1c..48e56d7ea9 100644
--- a/docs/devel/build-system.rst
+++ b/docs/devel/build-system.rst
@@ -47,16 +47,17 @@ command line options for which a same-named Meson option 
exists;
  dashes in the command line are replaced with underscores.
  
  Many checks on the compilation environment are still found in configure

-rather than `meson.build`, but new checks should be added directly to
-`meson.build`.
+rather than ``meson.build``, but new checks should be added directly to
+``meson.build``.
  
  Patches are also welcome to move existing checks from the configure

-phase to `meson.build`.  When doing so, ensure that `meson.build` does
-not use anymore the keys that you have removed from `config-host.mak`.
-Typically these will be replaced in `meson.build` by boolean variables,
-``get_option('optname')`` invocations, or `dep.found()` expressions.
-In general, the remaining checks have little or no interdependencies,
-so they can be moved one by one.
+phase to ``meson.build``.  When doing so, ensure that ``meson.build``
+does not use anymore the keys that you have removed from
+``config-host.mak``.  Typically these will be replaced in
+``meson.build`` by boolean variables, ``get_option('optname')``
+invocations, or ``dep.found()`` expressions.  In general, the remaining
+checks have little or no interdependencies, so they can be moved one by
+one.
  
  Helper functions

  
@@ -298,7 +299,7 @@ comprises the following tasks:
  
   - Add code to perform the actual feature check.
  
- - Add code to include the feature status in `config-host.h`

+ - Add code to include the feature status in ``config-host.h``
  
   - Add code to print out the feature status in the configure summary

 upon completion.
@@ -334,7 +335,7 @@ The other supporting code is generally simple::
  
  For the configure script to parse the new option, the

  ``scripts/meson-buildoptions.sh`` file must be up-to-date; ``make
-update-buildoptions`` (or just `make`) will take care of updating it.
+update-buildoptions`` (or just ``make``) will take care of updating it.
  
  
  Support scripts




Reviewed-by: Thomas Huth 

Re: [PATCH v5 2/4] docs: (further) remove non-reference uses of single backticks

[Thomas Huth]

On 02/11/2021 19.43, John Snow wrote:

The series rotted already. Here's the new changes.


Please change the patch description for the final commit (looks ugly in the 
git log otherwise)



Signed-off-by: John Snow 
---
  docs/system/i386/sgx.rst | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Reviewed-by: Thomas Huth 

Question on plugin or modules support on windows

[LIU Zhiwei]

Hi folks,

I want to use plugins or modules on Windows. However, these features are 
still not supported  on cross build for Windows.

Does someone know why it is not supported?

I also want to look for some suggestions on how to implement it.

Any advice is appreciated.

Thanks,
Zhiwei

Re: [PULL 00/12] Block layer patches

[Richard Henderson]

On 11/2/21 12:05 PM, Kevin Wolf wrote:

The following changes since commit 8cb41fda78c7ebde0dd248c6afe1d336efb0de50:

   Merge remote-tracking branch 'remotes/philmd/tags/machine-20211101' into 
staging (2021-11-02 05:53:45 -0400)

are available in the Git repository at:

   git://repo.or.cz/qemu/kevin.git tags/for-upstream

for you to fetch changes up to a8951438946d72d74c9bdbdb38fce95aa2973a88:

   block/nvme: Extract nvme_free_queue() from nvme_free_queue_pair() 
(2021-11-02 15:49:13 +0100)


Block layer patches

- Fail gracefully when blockdev-snapshot creates loops
- ide: Fix IDENTIFY DEVICE for disks > 128 GiB
- file-posix: Fix return value translation for AIO discards
- file-posix: add 'aio-max-batch' option
- rbd: implement bdrv_co_block_status
- Code cleanups and build fixes


Ari Sundholm (1):
   block/file-posix: Fix return value translation for AIO discards

Fabrice Fontaine (1):
   block/export/fuse.c: fix musl build

Hanna Reitz (1):
   block-backend: Silence clang -m32 compiler warning

Kevin Wolf (1):
   block: Fail gracefully when blockdev-snapshot creates loops

Peter Lieven (1):
   block/rbd: implement bdrv_co_block_status

Philippe Mathieu-Daudé (3):
   block/nvme: Automatically free qemu_memalign() with QEMU_AUTO_VFREE
   block/nvme: Display CQ/SQ pointer in nvme_free_queue_pair()
   block/nvme: Extract nvme_free_queue() from nvme_free_queue_pair()

Samuel Thibault (1):
   ide: Cap LBA28 capacity announcement to 2^28-1

Stefano Garzarella (3):
   file-posix: add `aio-max-batch` option
   linux-aio: add `dev_max_batch` parameter to laio_co_submit()
   linux-aio: add `dev_max_batch` parameter to laio_io_unplug()

  qapi/block-core.json   |   7 +++
  include/block/raw-aio.h|   6 ++-
  block.c|  10 
  block/block-backend.c  |   2 +-
  block/export/fuse.c|   4 ++
  block/file-posix.c |  18 ++--
  block/linux-aio.c  |  38 ++-
  block/nvme.c   |  22 +
  block/rbd.c| 112 +
  hw/ide/core.c  |   8 +++-
  block/trace-events |   2 +-
  tests/qemu-iotests/085 |  31 -
  tests/qemu-iotests/085.out |  33 +++--
  13 files changed, 258 insertions(+), 35 deletions(-)


Applied, thanks.

r~

Re: [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

[Alistair Francis]

On Sun, Oct 31, 2021 at 12:02 AM Bin Meng  wrote:
>
> This is now used by RISC-V as well. Update the comments.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Richard Henderson 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> (no changes since v1)
>
>  include/hw/core/tcg-cpu-ops.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 6cbe17f2e6..532c148a80 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -92,6 +92,7 @@ struct TCGCPUOps {
>  /**
>   * @debug_check_watchpoint: return true if the architectural
>   * watchpoint whose address has matched should really fire, used by ARM
> + * and RISC-V
>   */
>  bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
>
> --
> 2.25.1
>
>

Re: [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug

[Alistair Francis]

On Sat, Oct 30, 2021 at 11:57 PM Bin Meng  wrote:
>
> Add a config option to enable support for native M-mode debug.
> This is disabled by default and can be enabled with 'debug=true'.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> Changes in v2:
> - change the config option to 'disabled' by default
>
>  target/riscv/cpu.h | 2 ++
>  target/riscv/cpu.c | 5 +
>  2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1fb13e8b94..b2301425c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -75,6 +75,7 @@ enum {
>  RISCV_FEATURE_MMU,
>  RISCV_FEATURE_PMP,
>  RISCV_FEATURE_EPMP,
> +RISCV_FEATURE_DEBUG,
>  RISCV_FEATURE_MISA
>  };
>
> @@ -327,6 +328,7 @@ struct RISCVCPU {
>  bool mmu;
>  bool pmp;
>  bool epmp;
> +bool debug;
>  uint64_t resetvec;
>  } cfg;
>  };
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7061ae05fb..84116768ce 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  }
>  }
>
> +if (cpu->cfg.debug) {
> +set_feature(env, RISCV_FEATURE_DEBUG);
> +}
> +
>  set_resetvec(env, cpu->cfg.resetvec);
>
>  /* Validate that MISA_MXL is set properly. */
> @@ -631,6 +635,7 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>  DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>  DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
>
>  DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>
> --
> 2.25.1
>
>

Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs

[Alistair Francis]

On Mon, Nov 1, 2021 at 5:57 PM Anup Patel  wrote:
>
> On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis  wrote:
> >
> > On Tue, Oct 26, 2021 at 5:01 PM Anup Patel  wrote:
> > >
> > > The RISC-V AIA specification extends RISC-V local interrupts and
> > > introduces new CSRs. This patch adds defines for the new AIA CSRs.
> > >
> > > Signed-off-by: Anup Patel 
> >
> > What's the status of these CSR addresses being finalised?
>
> These CSR addresses have not changed since the past 2 months.
>
> Overall, the AIA spec has been in stable state for quite some time
> without much changes or objections.

Let's at least get a CSR address request submitted so we can start to
finalise on the addresses.

Alistair

>
> Regards,
> Anup
>
> >
> > Alistair

Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

[Alistair Francis]

On Tue, Oct 26, 2021 at 6:41 AM Atish Patra  wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra 
> ---
>  target/riscv/cpu.c |  2 +-
>  target/riscv/cpu.h |  2 +-
>  target/riscv/csr.c | 96 ++
>  3 files changed, 65 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3b55f5ed0036..aec94101a4c0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
>  DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>  DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> -DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> +DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>  DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>  DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>  DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ebc1a8754032..d0a722e7cbe1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,10 +294,10 @@ struct RISCVCPU {
>  bool ext_zbb;
>  bool ext_zbc;
>  bool ext_zbs;
> -bool ext_pmu;
>  bool ext_ifencei;
>  bool ext_icsr;
>
> +uint8_t pmu_num;
>  char *priv_spec;
>  char *user_spec;
>  char *bext_spec;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c486eeaffeb8..a7249eaf917f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno)
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> +static RISCVException mctr(CPURISCVState *env, int csrno)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +int ctr_index;
> +int base_csrno = CSR_MHPMCOUNTER3;
> +
> +if (riscv_cpu_is_32bit(env) && csrno >= CSR_MCYCLEH) {
> +/* Offset for RV32 mhpmcounternh counters */
> +base_csrno += 0x80;
> +}
> +ctr_index = csrno - base_csrno;
> +if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
> +/* The PMU is not enabled or counter is out of range*/
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +return RISCV_EXCP_NONE;
> +#endif

This needs a return type for #if defined(CONFIG_USER_ONLY)

Alistair

> +}
> +
>  static RISCVException ctr(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
>  CPUState *cs = env_cpu(env);
>  RISCVCPU *cpu = RISCV_CPU(cs);
>  int ctr_index;
> +int base_csrno = CSR_CYCLE;
> +bool brv32 = riscv_cpu_is_32bit(env);
> +
> +if (brv32 && csrno >= CSR_CYCLEH) {
> +/* Offset for RV32 hpmcounternh counters */
> +base_csrno += 0x80;
> +}
> +ctr_index = csrno - base_csrno;
>
> -if (!cpu->cfg.ext_pmu) {
> -/* The Counters extensions is not enabled */
> +if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num + 3)) {
> +/* The PMU is not enabled or counter is out of range */
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  }
>  break;
>  }
> -if (riscv_cpu_is_32bit(env)) {
> +if (brv32) {
>  switch (csrno) {
>  case CSR_CYCLEH:
>  if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  }
>  break;
>  }
> -if (riscv_cpu_is_32bit(env)) {
> +if (brv32) {
>  switch (csrno) {
>  case CSR_CYCLEH:
>  if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> @@ -1720,35 +1750,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>  [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,read_zero },
>  [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,read_zero },
>
> -[CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,read_zero },
> -[CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,read_zero },
> -[CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,read_zero },
> -[CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,read_zero },
> -[CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,read_zero },
> -[CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,read_zero },
> -[CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,read_zero },
> -[CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,read_zero },
> -   

Re: [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR

[Alistair Francis]

On Tue, Oct 26, 2021 at 6:05 AM Atish Patra  wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.h  |  2 ++
>  target/riscv/cpu_bits.h |  4 
>  target/riscv/csr.c  | 25 +
>  target/riscv/machine.c  |  5 +++--
>  4 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0a722e7cbe1..b421eefa623f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -217,6 +217,8 @@ struct CPURISCVState {
>  target_ulong scounteren;
>  target_ulong mcounteren;
>
> +target_ulong mcountinhibit;
> +
>  target_ulong sscratch;
>  target_ulong mscratch;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee2d..72b1485e621f 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -275,6 +275,10 @@
>  #define CSR_MHPMCOUNTER29   0xb1d
>  #define CSR_MHPMCOUNTER30   0xb1e
>  #define CSR_MHPMCOUNTER31   0xb1f
> +
> +/* Machine counter-inhibit register */
> +#define CSR_MCOUNTINHIBIT   0x320
> +
>  #define CSR_MHPMEVENT3  0x323
>  #define CSR_MHPMEVENT4  0x324
>  #define CSR_MHPMEVENT5  0x325
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a7249eaf917f..faf02e12ec34 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -766,6 +766,28 @@ static RISCVException write_mtvec(CPURISCVState *env, 
> int csrno,
>  return RISCV_EXCP_NONE;
>  }
>
> +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +if (env->priv_ver < PRIV_VERSION_1_11_0) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +*val = env->mcountinhibit;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
> +  target_ulong val)
> +{
> +if (env->priv_ver < PRIV_VERSION_1_11_0) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +env->mcountinhibit = val;
> +return RISCV_EXCP_NONE;
> +}
> +
>  static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
>target_ulong *val)
>  {
> @@ -1780,6 +1802,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>  [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  mctr,   read_zero },
>  [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  mctr,   read_zero },
>
> +[CSR_MCOUNTINHIBIT]  = { "mcountinhibit",   any,read_mcountinhibit,
> +   write_mcountinhibit },
> +
>  [CSR_MHPMEVENT3] = { "mhpmevent3", any,read_zero },
>  [CSR_MHPMEVENT4] = { "mhpmevent4", any,read_zero },
>  [CSR_MHPMEVENT5] = { "mhpmevent5", any,read_zero },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 16a08302daff..20dea0843604 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
>
>  const VMStateDescription vmstate_riscv_cpu = {
>  .name = "cpu",
> -.version_id = 2,
> -.minimum_version_id = 2,
> +.version_id = 3,
> +.minimum_version_id = 3,
>  .fields = (VMStateField[]) {
>  VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
>  VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>  VMSTATE_UINTTL(env.mtval, RISCVCPU),
>  VMSTATE_UINTTL(env.scounteren, RISCVCPU),
>  VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> +VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
>  VMSTATE_UINTTL(env.sscratch, RISCVCPU),
>  VMSTATE_UINTTL(env.mscratch, RISCVCPU),
>  VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> --
> 2.31.1
>
>

Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu

[Alistair Francis]

On Tue, Oct 26, 2021 at 6:03 AM Atish Patra  wrote:
>
> The PMU counters are supported via cpu config "Counters" which doesn't
> indicate the correct purpose of those counters.
>
> Rename the config property to pmu to indicate that these counters
> are performance monitoring counters. This aligns with cpu options for
> ARM architecture as well.
>
> Signed-off-by: Atish Patra 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 2 +-
>  target/riscv/cpu.h | 2 +-
>  target/riscv/csr.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e63..3b55f5ed0036 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
>  DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>  DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> -DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> +DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
>  DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>  DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>  DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9e55b2f5b170..ebc1a8754032 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -294,7 +294,7 @@ struct RISCVCPU {
>  bool ext_zbb;
>  bool ext_zbc;
>  bool ext_zbs;
> -bool ext_counters;
> +bool ext_pmu;
>  bool ext_ifencei;
>  bool ext_icsr;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index de484c74d3b4..c486eeaffeb8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  RISCVCPU *cpu = RISCV_CPU(cs);
>  int ctr_index;
>
> -if (!cpu->cfg.ext_counters) {
> +if (!cpu->cfg.ext_pmu) {
>  /* The Counters extensions is not enabled */
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
> --
> 2.31.1
>
>

Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for

[Alistair Francis]

On Tue, Oct 26, 2021 at 5:56 AM Atish Patra  wrote:
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode access in the predicate function as well.
>
> Signed-off-by: Atish Patra 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/csr.c | 52 ++
>  1 file changed, 52 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ec776013435..de484c74d3b4 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  #if !defined(CONFIG_USER_ONLY)
>  CPUState *cs = env_cpu(env);
>  RISCVCPU *cpu = RISCV_CPU(cs);
> +int ctr_index;
>
>  if (!cpu->cfg.ext_counters) {
>  /* The Counters extensions is not enabled */
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> +if (env->priv == PRV_S) {
> +switch (csrno) {
> +case CSR_CYCLE:
> +if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_TIME:
> +if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_INSTRET:
> +if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> +ctr_index = csrno - CSR_CYCLE;
> +if (!get_field(env->mcounteren, 1 << ctr_index)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +}
> +if (riscv_cpu_is_32bit(env)) {
> +switch (csrno) {
> +case CSR_CYCLEH:
> +if (!get_field(env->mcounteren, COUNTEREN_CY)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_TIMEH:
> +if (!get_field(env->mcounteren, COUNTEREN_TM)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_INSTRETH:
> +if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> +ctr_index = csrno - CSR_CYCLEH;
> +if (!get_field(env->mcounteren, 1 << ctr_index)) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +break;
> +}
> +}
> +}
> +
>  if (riscv_cpu_virt_enabled(env)) {
>  switch (csrno) {
>  case CSR_CYCLE:
> --
> 2.31.1
>
>

Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function

[Alistair Francis]

On Tue, Oct 26, 2021 at 6:39 AM Atish Patra  wrote:
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Signed-off-by: Atish Patra 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/csr.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd32162a..1ec776013435 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -89,8 +89,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  }
>  break;
>  case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> -if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) 
> &&
> -get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> +ctr_index = csrno - CSR_CYCLE;
> +if (!get_field(env->hcounteren, 1 << ctr_index) &&
> + get_field(env->mcounteren, 1 << ctr_index)) {
>  return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>  }
>  break;
> @@ -116,8 +117,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>  }
>  break;
>  case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> -if (!get_field(env->hcounteren, 1 << (csrno - 
> CSR_HPMCOUNTER3H)) &&
> -get_field(env->mcounteren, 1 << (csrno - 
> CSR_HPMCOUNTER3H))) {
> +ctr_index = csrno - CSR_CYCLEH;
> +if (!get_field(env->hcounteren, 1 << ctr_index) &&
> + get_field(env->mcounteren, 1 << ctr_index)) {
>  return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>  }
>  break;
> --
> 2.31.1
>
>

Re: [PATCH v2 1/2] virtio-gpu: splitting one extended mode guest fb into n-scanouts

[Gerd Hoffmann]

On Tue, Nov 02, 2021 at 05:41:10PM -0700, Dongwon Kim wrote:
> I double-checked the patch and also tried to build with --disable-opengl
> but couldn't find any issue. Can you please give me some hint? Like
> build errors you saw. What are changed by the patch are pretty much
> limited to virtio-gpu blob case and just one change in common area is
> egl_fb_blit function but the function interface stays same and there are
> no variables enabled only with certain define.
> 
> Is there any chance that the build system was building it with the
> previous patch, "ui/gtk-egl: un-tab and re-tab should destroy egl
> surface and context" still applied?

Hmm, I had applied both, then dropped the failing series, but possibly I
missed some broken patch.

Trying to apply the series on top of the v2 just sent failed.

Any chance you can send a single patch series with all pending patches
(including the "virtio-gpu: Add a default synchronization mechanism for
blobs" series by Vivek which also doesn't apply cleanly any more)?

Ideally tested in gitlab ci?

thanks,
  Gerd

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

[Anup Patel]

On Tue, Nov 2, 2021 at 4:22 PM Bin Meng  wrote:
>
> On Tue, Nov 2, 2021 at 6:24 PM Anup Patel  wrote:
> >
> > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng  wrote:
> > >
> > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel  wrote:
> > > >
> > > > A hypervsior can optionally take guest external interrupts using
> > >
> > > typo: hypervisor
> >
> > Okay, I will update.
> >
> > >
> > > > SGEIP bit of hip and hie CSRs.
> > > >
> > > > Signed-off-by: Anup Patel 
> > > > Reviewed-by: Alistair Francis 
> > > > ---
> > > >  target/riscv/cpu.c  |  3 ++-
> > > >  target/riscv/cpu_bits.h |  3 +++
> > > >  target/riscv/csr.c  | 18 +++---
> > > >  3 files changed, 16 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index 788fa0b11c..0460a3972b 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> > > >  env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, 
> > > > env->misa_mxl);
> > > >  }
> > > >  env->mcause = 0;
> > > > +env->miclaim = MIP_SGEIP;
> > > >  env->pc = env->resetvec;
> > > >  env->two_stage_lookup = false;
> > > >  #endif
> > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> > > >  cpu_set_cpustate_pointers(cpu);
> > > >
> > > >  #ifndef CONFIG_USER_ONLY
> > > > -qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> > > > +qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> > > >  #endif /* CONFIG_USER_ONLY */
> > > >  }
> > > >
> > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > index cffcd3a5df..8a5a4cde95 100644
> > > > --- a/target/riscv/cpu_bits.h
> > > > +++ b/target/riscv/cpu_bits.h
> > > > @@ -498,6 +498,8 @@ typedef enum RISCVException {
> > > >  #define IRQ_S_EXT  9
> > > >  #define IRQ_VS_EXT 10
> > > >  #define IRQ_M_EXT  11
> > > > +#define IRQ_S_GEXT 12
> > > > +#define IRQ_LOCAL_MAX  13
> > >
> > > The IRQ_LOCAL_MAX should be XLEN long, not 13.
> >
> > The IRQ_LOCAL_MAX here represents local interrupts
> > standardized by the RISC-V privilege spec. This value
>
> The standardardized IRQ number is 16.

Max local IRQ as 13 is more conservative and better (IMO)
because we are not including any undefined local IRQ.

I also totally fine changing max local IRQ to 16 as well.

>
> > will change only when more local interrupts are
> > standardized by the RISC-V privilege spec.
>
> We should leave room for platform / custom IRQ as it is already
> defined by the priv spec.

custom local IRQs are not going to be accepted in the first 16 local
IRQs.

The AIA spec defines a sparse numbering scheme for both
standard/custom local IRQs beyond 16. The AIA spec will also
maintain a table of defined local IRQs.

IMO, we should deal with custom local IRQs as when they show
up and standard local IRQs should always get first class treatment.

Regards,
Anup

>
> Regards,
> Bin

Re: [PATCH v5 06/26] arm: qemu: Add a devicetree file for qemu_arm64

[François Ozog]

Hi Simon

Le mer. 3 nov. 2021 à 02:30, Simon Glass  a écrit :

> Hi Tom,
>
> On Tue, 2 Nov 2021 at 11:28, Tom Rini  wrote:
> >
> > On Tue, Nov 02, 2021 at 09:00:53AM -0600, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Mon, 1 Nov 2021 at 12:07, Tom Rini  wrote:
> > > >
> > > > On Mon, Nov 01, 2021 at 06:33:35PM +0100, François Ozog wrote:
> > > > > Hi Simon
> > > > >
> > > > > Le lun. 1 nov. 2021 à 17:58, Simon Glass  a
> écrit :
> > > > >
> > > > > > Hi Peter,
> > > > > >
> > > > > > On Mon, 1 Nov 2021 at 04:48, Peter Maydell <
> peter.mayd...@linaro.org>
> > > > > > wrote:
> > > > > > >
> > > > > > > On Tue, 26 Oct 2021 at 01:33, Simon Glass 
> wrote:
> > > > > > > >
> > > > > > > > Add this file, generated from qemu, so there is a reference
> devicetree
> > > > > > > > in the U-Boot tree.
> > > > > > > >
> > > > > > > > Signed-off-by: Simon Glass 
> > > > > > >
> > > > > > > Note that the dtb you get from QEMU is only guaranteed to work
> if:
> > > > > > >  1) you run it on the exact same QEMU version you generated it
> with
> > > > > > >  2) you pass QEMU the exact same command line arguments you
> used
> > > > > > > when you generated it
> > > > > >
> > > > > > Yes, I certainly understand that. In general this is not safe,
> but in
> > > > > > practice it works well enough for development and CI.
> > > > >
> > > > > You recognize that you hijack a product directory with development
> hack
> > > > > facility. There is a test directory to keep things clear. There
> can be a
> > > > > dev-dts or something similar for Dev time tools.
> > > > > I have only seen push back on those fake dts files in the dts
> directory: I
> > > > > guess that unless someone strongly favors a continuation of the
> discussion,
> > > > > you may consider re-shaping the proposal to address concerns.
> > > >
> > > > Yes.  We need to document how to make development easier.  But I'm
> still
> > > > not on board with the notion of including DTS files for platforms
> where
> > > > the source of truth for the DTB is elsewhere.  That's going to bring
> us
> > > > a lot more pain.
> > >
> > > Are you talking about QEMU specifically, or Raspberry Pi?
> >
> > I was using two of the more common and readily available platforms where
> > the source of truth for the DTS/DTB is not (and will not be) U-Boot.
> >
> > > How can we get this resolved? I very much want to get to just having
> > > OF_SEPARATE and OF_EMBED as the only available build-time options,
> > > with OF_BOARD (and perhaps OF_PASSAGE) as something we can enable for
> > > runtime support. I feel that separating the build-time and run-time
> > > behaviour is very important. Over time perhaps we will have some
> > > success in upstreaming bindings, but for now we have what we have.
> > > There is still a lot of pushback on U-Boot having things in the
> > > devicetree, although I do see that softening somewhat.
> >
> >
> > To reiterate, the uniform bit of feedback on this series has been that
> > everyone else disagrees with your notion that we _must_ have a dts
> > in-tree.
>
> [I would like everyone to take a deep breath and think about what this
> actually impacts. I argue the impact outside U-Boot is approximately
> zero. What are we actually discussing here?]
>
> A few have responded that they can just add the files. I think that is
> the case for everything except QEMU, right? I think even François
> agrees with the documentation argument.

I do providing that the sample goes into documentation, not actionable as a
build artifact in the dts directory.

> There is no real burden in
> adding the files so we can see what is going on, add a binman node,
> SPL nodes, etc.
>
> So I am going to stand my ground on that one. It affects:
>
> - highbank
> - qemu-ppce500
> - rpi_4
> - xilinx_versal_virt
> - octeontx
> - xenguest_arm64
> - juno
>
> So that is just 7 boards that I want to add devicetree files for. I
> think that is reasonable and not a burden on these maintainers.
>
> Let me deal with QEMU.
>
> Let's imagine that we were in the state that I am proposing here,
> which we would be if I were a better devicetree maintainer for U-Boot
> and had not taken my eye off the ball, basically with my review of
> [1], where I should have pushed to get a response on the questions
> before it was applied. That might have triggered me to think about the
> implications of this at the time.
>
> Anyway, in the state that I am proposing, what problems would we have?
>
> 1. QEMU has a DT which only matches the 'standard' invocation as
> documented at [2]


>
> 2. QEMU may get out of date if there is a new release.
>
> I don't think (1) is really a problem. People will have to remove
> CONFIG_OF_BOARD from configs/qemu_arm_spl_defconfig (or the like) to
> get into this state, and we have a message now that prints out where
> the devicetree comes from ("separate" in this case):
>
> Core:  42 devices, 11 uclasses, devicetree: separate
>
> For (2), I tested QEMU 6.1.50 and the only differenc

Re: [PATCH v5 00/26] fdt: Make OF_BOARD a boolean option

[François Ozog]

Hi Simon

Le mer. 3 nov. 2021 à 02:21, Simon Glass  a écrit :

> Hi François,
>
> On Wed, 27 Oct 2021 at 14:07, François Ozog 
> wrote:
> >
> > Hi Simon
> >
> > Le mer. 27 oct. 2021 à 20:23, Simon Glass  a écrit :
> >>
> >> Hi François,
> >>
> >> On Wed, 27 Oct 2021 at 09:14, François Ozog 
> wrote:
> >> >
> >> >
> >> >
> >> > On Wed, 27 Oct 2021 at 16:08, Simon Glass  wrote:
> >> >>
> >> >> Hi François,
> >> >>
> >> >> On Tue, 26 Oct 2021 at 00:07, François Ozog <
> francois.o...@linaro.org> wrote:
> >> >> >
> >> >> > Hi Simon
> >> >> >
> >> >> > Position unchanged on this series: adding fake dts for boards that
> generate their device tree in the dts directory is not good. If you have
> them in documentation the it is acceptable.
> >> >>
> >> >> I think we are going to have to disagree on this one. I actually used
> >> >> the qemu one in testing/development recently. We have to have a way
> to
> >> >> develop in-tree with U-Boot. It does not impinge on any of your use
> >> >> cases, so far as I know.
> >> >
> >> > I am not the only one in disagreement... You just saw Alex Bénée from
> Qemu saying the same thing.
> >> > I understand the advanced debug/development scenario you mention.
> >> > But locating the DT files in the dts directory is mis-leading the
> contributors to think that they need to compile the DT for the targeted
> platforms.
> >> > For your advanced scenario, you can still have the dts in the
> documentation area, or whatever directory (except dts). compile it and
> supply to U-Boot.
> >>
> >> We have this situation with rpi 1, 2 and 3 and I don't believe anyone
> >> has noticed. U-Boot handles the build automatically. If you turn off
> >> OF_BOARD, it will use the U-Boot devicetree always so you know what is
> >> going on.
> >>
> >> We can add a message to U-Boot indicating where the devicetree came
> >> from, perhaps? That might be useful given everything that is going on.
> >>
> >> As in this case, quite often in these discussions I struggle to
> >> understand what is behind the objection. Is it that your customers are
> >> demanding that devicetrees become private, secret data, not included
> >> in open-source projects? Or is it just the strange case of QEMU that
> >> is informing your thinking? I know of at least one project where the
> >> first-stage bootloader produces a devicetree and no one has the source
> >> for it. I believe TF-A was created for licensing reasons...so can you
> >> be a bit clearer about what the problem actually is?
> >
> > there are situations where U-Boot must have a dtb. Then those dTB
> sources are logically found in the dts directory.
> > There are situations where U-Boot should not have a dtb. In that case
> there should be no element in the dts directory. Otherwise it creates
> confusion.
> > Now as you point out, we need “playgrounds” to deal with some situation.
> So having examples in an ad-hoc directory, different from dts is fine. I
> proposed documentation but you may find a better place.
> > In other words, dts shall host only dt source when U-Boot cannot do but
> make a dTB for a platform.
> > As you have seen in different mail thread (firmware sustainability and
> OCP checklist) freedom is important to Linaro and there are no hidden
> Trojan horse for licensing.
>
> I don't understand what you are getting at with the Trojan horse.

I was referring to your statement that “TFA was created for licensing “
reasons. That’s not the case. It was created to address fragmentation in
the secure firmware for which there was no open source at all. SPL is
definitely not architected to be the basis of Arm secure firmware {
TFA/BL31 (secure monitor), TFA/BL32 (OP-TEE), TFA/SEL2(Hafnium), TFA/SCMI
server, SCP…}. That said  SPL and TFA/BL2 have similar roles from a
10,000ft perspective.
I felt your comment was alluding to TFA was created to promote binary
components integration, which is also not the case. Hence my reference to
Trojan Horse.

> But
> you have no objection to requiring boards to supply a DT (whether in
> documentation or arch/arm/dts) to be in U-Boot?

I agree that boards need to properly document their DT. For (a) boards that
have defined their standard boot flow to assume U-Boot will only do fix ups
and overlays, the DT shall be in the U-Boot documentation part (either in
full or pointing to their project documentation), in all other cases (b) it
shall be in dts. Boards in the (a) case (may not be exhaustive): Qemu,
SystemReady, RPI (it actually assumes it boot a Linux kernel but U-Boot
smartly interposes). There may be RISCV boards that comply to EBBR too but
I let Heinrich/Atish comment.

>
>
> >
> >
> >> If a board is
> >> in-tree in U-Boot I would like it to have a devicetree there, at least
> >> until we have a better option. At the very least, it MUST be
> >> discoverable and it must be possible to undertake U-Boot development
> >> easily without a lot of messing around.
> >
> > You can if you keep two dts directories separate:
> > dts f

Re: [PULL 0/4] Block patches

[Richard Henderson]

On 11/2/21 10:22 AM, Hanna Reitz wrote:

The following changes since commit 8cb41fda78c7ebde0dd248c6afe1d336efb0de50:

   Merge remote-tracking branch 'remotes/philmd/tags/machine-20211101' into 
staging (2021-11-02 05:53:45 -0400)

are available in the Git repository at:

   https://github.com/XanClic/qemu.git tags/pull-block-2021-11-02

for you to fetch changes up to 7da9623cc078229caf07c290e16401ccdb9408d2:

   block/vpc: Add a sanity check that fixed-size images have the right type 
(2021-11-02 12:47:51 +0100)


Emanuele Giuseppe Esposito (1):
   pylint: fix errors and warnings generated by tests/qemu-iotests/297

Eric Blake (1):
   qemu-img: Consistent docs for convert -F

Thomas Huth (1):
   block/vpc: Add a sanity check that fixed-size images have the right
 type

Thomas Weißschuh (1):
   vmdk: allow specification of tools version

  docs/tools/qemu-img.rst |  2 +-
  qapi/block-core.json|  3 +++
  block/vmdk.c| 24 
  block/vpc.c |  3 ++-
  qemu-img-cmds.hx|  2 +-
  tests/qemu-iotests/129  | 18 +-
  tests/qemu-iotests/310  | 16 
  tests/qemu-iotests/check| 11 ++-
  tests/qemu-iotests/iotests.py   |  7 ---
  tests/qemu-iotests/tests/image-fleecing |  4 ++--
  10 files changed, 56 insertions(+), 34 deletions(-)


Applied, thanks.

r~

[PATCH v4 06/10] target/arm: Split compute_fsr_fsc out of arm_deliver_fault

[Richard Henderson]

We will reuse this section of arm_deliver_fault for
raising pc alignment faults.

Signed-off-by: Richard Henderson 
---
 target/arm/tlb_helper.c | 45 +
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 12a934e924..4cacb9658f 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t 
template_syn,
 return syn;
 }
 
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
-MMUAccessType access_type,
-int mmu_idx, ARMMMUFaultInfo *fi)
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
+int target_el, int mmu_idx, uint32_t *ret_fsc)
 {
-CPUARMState *env = &cpu->env;
-int target_el;
-bool same_el;
-uint32_t syn, exc, fsr, fsc;
 ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
-
-target_el = exception_target_el(env);
-if (fi->stage2) {
-target_el = 2;
-env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
-if (arm_is_secure_below_el3(env) && fi->s1ns) {
-env->cp15.hpfar_el2 |= HPFAR_NS;
-}
-}
-same_el = (arm_current_el(env) == target_el);
+uint32_t fsr, fsc;
 
 if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
 arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
@@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, 
vaddr addr,
 fsc = 0x3f;
 }
 
+*ret_fsc = fsc;
+return fsr;
+}
+
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+MMUAccessType access_type,
+int mmu_idx, ARMMMUFaultInfo *fi)
+{
+CPUARMState *env = &cpu->env;
+int target_el;
+bool same_el;
+uint32_t syn, exc, fsr, fsc;
+
+target_el = exception_target_el(env);
+if (fi->stage2) {
+target_el = 2;
+env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
+if (arm_is_secure_below_el3(env) && fi->s1ns) {
+env->cp15.hpfar_el2 |= HPFAR_NS;
+}
+}
+same_el = (arm_current_el(env) == target_el);
+
+fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
+
 if (access_type == MMU_INST_FETCH) {
 syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
 exc = EXCP_PREFETCH_ABORT;
-- 
2.25.1

[PATCH v4 09/10] target/arm: Suppress bp for exceptions with more priority

[Richard Henderson]

Both single-step and pc alignment faults have priority over
breakpoint exceptions.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 target/arm/debug_helper.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2983e36dd3..32f3caec23 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs)
 {
 ARMCPU *cpu = ARM_CPU(cs);
 CPUARMState *env = &cpu->env;
+target_ulong pc;
 int n;
 
 /*
@@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs)
 return false;
 }
 
+/*
+ * Single-step exceptions have priority over breakpoint exceptions.
+ * If single-step state is active-pending, suppress the bp.
+ */
+if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
+return false;
+}
+
+/*
+ * PC alignment faults have priority over breakpoint exceptions.
+ */
+pc = is_a64(env) ? env->pc : env->regs[15];
+if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
+return false;
+}
+
+/*
+ * Instruction aborts have priority over breakpoint exceptions.
+ * TODO: We would need to look up the page for PC and verify that
+ * it is present and executable.
+ */
+
 for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
 if (bp_wp_matches(cpu, n, false)) {
 return true;
-- 
2.25.1

[PATCH v4 07/10] target/arm: Take an exception if PC is misaligned

[Richard Henderson]

For A64, any input to an indirect branch can cause this.

For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not.  This includes the BX instruction but also
other interworking changes to PC.  Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
exception or force align the PC.

We choose to raise an exception because we have the infrastructure,
it makes the generated code for gen_bx simpler, and it has the
possibility of catching more guest bugs.

Signed-off-by: Richard Henderson 
---
 target/arm/helper.h   |  1 +
 target/arm/syndrome.h |  5 
 linux-user/aarch64/cpu_loop.c | 46 ---
 target/arm/tlb_helper.c   | 18 ++
 target/arm/translate-a64.c| 15 
 target/arm/translate.c| 22 -
 6 files changed, 87 insertions(+), 20 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index 448a86edfd..b463d9343b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
 DEF_HELPER_2(exception_internal, void, env, i32)
 DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
 DEF_HELPER_1(setend, void, env)
 DEF_HELPER_2(wfi, void, env, i32)
 DEF_HELPER_1(wfe, void, env)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index f30f4130a2..8cde8e7243 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void)
 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_pcalignment(void)
+{
+return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 97e0728b67..f9f3473288 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env)
 break;
 case EXCP_PREFETCH_ABORT:
 case EXCP_DATA_ABORT:
-/* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
 ec = syn_get_ec(env->exception.syndrome);
-assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
-
-/* Both EC have the same format for FSC, or close enough. */
-fsc = extract32(env->exception.syndrome, 0, 6);
-switch (fsc) {
-case 0x04 ... 0x07: /* Translation fault, level {0-3} */
-si_signo = TARGET_SIGSEGV;
-si_code = TARGET_SEGV_MAPERR;
+switch (ec) {
+case EC_DATAABORT:
+case EC_INSNABORT:
+/* Both EC have the same format for FSC, or close enough. */
+fsc = extract32(env->exception.syndrome, 0, 6);
+switch (fsc) {
+case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+si_signo = TARGET_SIGSEGV;
+si_code = TARGET_SEGV_MAPERR;
+break;
+case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+si_signo = TARGET_SIGSEGV;
+si_code = TARGET_SEGV_ACCERR;
+break;
+case 0x11: /* Synchronous Tag Check Fault */
+si_signo = TARGET_SIGSEGV;
+si_code = TARGET_SEGV_MTESERR;
+break;
+case 0x21: /* Alignment fault */
+si_signo = TARGET_SIGBUS;
+si_code = TARGET_BUS_ADRALN;
+break;
+default:
+g_assert_not_reached();
+}
 break;
-case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
-case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
-si_signo = TARGET_SIGSEGV;
-si_code = TARGET_SEGV_ACCERR;
-break;
-case 0x11: /* Synchronous Tag Check Fault */
-si_signo = TARGET_SIGSEGV;
-si_code = TARGET_SEGV_MTESERR;
-break;
-case 0x21: /* Alignment fault */
+case EC_PCALIGNMENT:
 si_signo = TARGET_SIGBUS;
 si_code = TARGET_BUS_ADRALN;
 break;
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 4cacb9658f..b79004e0cc 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -9,6 +9,7 @@
 #include "cpu.h"
 #include "internals.h"
 #include "exec/exec-all.h"
+#include "exec/helper-proto.h"
 
 static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
 unsigned int tar

[PATCH v4 01/10] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cec672f229..9c4258ccac 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 {
 DisasContext *s = container_of(dcbase, DisasContext, base);
 CPUARMState *env = cpu->env_ptr;
+uint64_t pc = s->base.pc_next;
 uint32_t insn;
 
 if (s->ss_active && !s->pstate_ss) {
@@ -14769,10 +14770,10 @@ static void 
aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 return;
 }
 
-s->pc_curr = s->base.pc_next;
-insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
+s->pc_curr = pc;
+insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
 s->insn = insn;
-s->base.pc_next += 4;
+s->base.pc_next = pc + 4;
 
 s->fp_access_checked = false;
 s->sve_access_checked = false;
-- 
2.25.1

[PATCH v4 10/10] tests/tcg: Add arm and aarch64 pc alignment tests

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tests/tcg/aarch64/pcalign-a64.c   | 37 +
 tests/tcg/arm/pcalign-a32.c   | 46 +++
 tests/tcg/aarch64/Makefile.target |  4 +--
 tests/tcg/arm/Makefile.target |  4 +++
 4 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/aarch64/pcalign-a64.c
 create mode 100644 tests/tcg/arm/pcalign-a32.c

diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
new file mode 100644
index 00..6b9277f919
--- /dev/null
+++ b/tests/tcg/aarch64/pcalign-a64.c
@@ -0,0 +1,37 @@
+/* Test PC misalignment exception */
+
+#include 
+#include 
+#include 
+#include 
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+assert(info->si_code == BUS_ADRALN);
+assert(info->si_addr == expected);
+exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+void *tmp;
+
+struct sigaction sa = {
+.sa_sigaction = sigbus,
+.sa_flags = SA_SIGINFO
+};
+
+if (sigaction(SIGBUS, &sa, NULL) < 0) {
+perror("sigaction");
+return EXIT_FAILURE;
+}
+
+asm volatile("adr %0, 1f + 1\n\t"
+ "str %0, %1\n\t"
+ "br  %0\n"
+ "1:"
+ : "=&r"(tmp), "=m"(expected));
+abort();
+}
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
new file mode 100644
index 00..3c9c8cc97b
--- /dev/null
+++ b/tests/tcg/arm/pcalign-a32.c
@@ -0,0 +1,46 @@
+/* Test PC misalignment exception */
+
+#ifdef __thumb__
+#error "This test must be compiled for ARM"
+#endif
+
+#include 
+#include 
+#include 
+#include 
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+assert(info->si_code == BUS_ADRALN);
+assert(info->si_addr == expected);
+exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+void *tmp;
+
+struct sigaction sa = {
+.sa_sigaction = sigbus,
+.sa_flags = SA_SIGINFO
+};
+
+if (sigaction(SIGBUS, &sa, NULL) < 0) {
+perror("sigaction");
+return EXIT_FAILURE;
+}
+
+asm volatile("adr %0, 1f + 2\n\t"
+ "str %0, %1\n\t"
+ "bx  %0\n"
+ "1:"
+ : "=&r"(tmp), "=m"(expected));
+
+/*
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
+ * the address or not.  If so, we can legitimately fall through.
+ */
+return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/aarch64/Makefile.target 
b/tests/tcg/aarch64/Makefile.target
index 2c05c90d17..1d967901bd 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -8,8 +8,8 @@ VPATH   += $(ARM_SRC)
 AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
 VPATH  += $(AARCH64_SRC)
 
-# Float-convert Tests
-AARCH64_TESTS=fcvt
+# Base architecture tests
+AARCH64_TESTS=fcvt pcalign-a64
 
 fcvt: LDFLAGS+=-lm
 
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 5ab59ed6ce..f509d823d4 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -29,6 +29,10 @@ run-fcvt: fcvt
$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
 
+# PC alignment test
+ARM_TESTS += pcalign-a32
+pcalign-a32: CFLAGS+=-marm
+
 ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
 
 # Semihosting smoke test for linux-user
-- 
2.25.1

[PATCH v4 05/10] target/arm: Advance pc for arch single-step exception

[Richard Henderson]

The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9c4258ccac..2986fe1393 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 assert(s->base.num_insns == 1);
 gen_swstep_exception(s, 0, 0);
 s->base.is_jmp = DISAS_NORETURN;
+s->base.pc_next = pc + 4;
 return;
 }
 
-- 
2.25.1

[PATCH v4 03/10] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/translate.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ead77e9006..a39456ea98 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9629,25 +9629,25 @@ static void thumb_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 {
 DisasContext *dc = container_of(dcbase, DisasContext, base);
 CPUARMState *env = cpu->env_ptr;
+uint32_t pc = dc->base.pc_next;
 uint32_t insn;
 bool is_16bit;
 
 if (arm_pre_translate_insn(dc)) {
-dc->base.pc_next += 2;
+dc->base.pc_next = pc + 2;
 return;
 }
 
-dc->pc_curr = dc->base.pc_next;
-insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+dc->pc_curr = pc;
+insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
 is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
-dc->base.pc_next += 2;
+pc += 2;
 if (!is_16bit) {
-uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
-   dc->sctlr_b);
-
+uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
 insn = insn << 16 | insn2;
-dc->base.pc_next += 2;
+pc += 2;
 }
+dc->base.pc_next = pc;
 dc->insn = insn;
 
 if (dc->pstate_il) {
-- 
2.25.1

[PATCH v4 08/10] target/arm: Assert thumb pc is aligned

[Richard Henderson]

Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.

Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 target/arm/gdbstub.c   |  9 +++--
 target/arm/machine.c   | 10 ++
 target/arm/translate.c |  3 +++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index e0dcb33e32..90bf803be2 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 
 tmp = ldl_p(mem_buf);
 
-/* Mask out low bit of PC to workaround gdb bugs.  This will probably
-   cause problems if we ever implement the Jazelle DBX extensions.  */
+/*
+ * Mask out low bits of PC to workaround gdb bugs.
+ * This avoids an assert in thumb_tr_translate_insn, because it is
+ * architecturally impossible to misalign the pc.
+ * This will probably cause problems if we ever implement the
+ * Jazelle DBX extensions.
+ */
 if (n == 15) {
 tmp &= ~1;
 }
diff --git a/target/arm/machine.c b/target/arm/machine.c
index c74d8c3f4b..135d2420b5 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id)
 return -1;
 }
 }
+
+/*
+ * Misaligned thumb pc is architecturally impossible.
+ * We have an assert in thumb_tr_translate_insn to verify this.
+ * Fail an incoming migrate to avoid this assert.
+ */
+if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+return -1;
+}
+
 if (!kvm_enabled()) {
 pmu_op_finish(&cpu->env);
 }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 828fb328ee..9ac4292cfb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9657,6 +9657,9 @@ static void thumb_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 uint32_t insn;
 bool is_16bit;
 
+/* Misaligned thumb PC is architecturally impossible. */
+assert((dc->base.pc_next & 1) == 0);
+
 if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
 dc->base.pc_next = pc + 2;
 return;
-- 
2.25.1

[PATCH v4 04/10] target/arm: Split arm_pre_translate_insn

[Richard Henderson]

Create arm_check_ss_active and arm_check_kernelpage.

Reverse the order of the tests.  While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.

Signed-off-by: Richard Henderson 
---
 target/arm/translate.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index a39456ea98..82d4e24c27 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9513,7 +9513,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, 
CPUState *cpu)
 dc->insn_start = tcg_last_op();
 }
 
-static bool arm_pre_translate_insn(DisasContext *dc)
+static bool arm_check_kernelpage(DisasContext *dc)
 {
 #ifdef CONFIG_USER_ONLY
 /* Intercept jump to the magic kernel page.  */
@@ -9525,7 +9525,11 @@ static bool arm_pre_translate_insn(DisasContext *dc)
 return true;
 }
 #endif
+return false;
+}
 
+static bool arm_check_ss_active(DisasContext *dc)
+{
 if (dc->ss_active && !dc->pstate_ss) {
 /* Singlestep state is Active-pending.
  * If we're in this state at the start of a TB then either
@@ -9562,7 +9566,7 @@ static void arm_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 uint32_t pc = dc->base.pc_next;
 unsigned int insn;
 
-if (arm_pre_translate_insn(dc)) {
+if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
 dc->base.pc_next = pc + 4;
 return;
 }
@@ -9633,7 +9637,7 @@ static void thumb_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 uint32_t insn;
 bool is_16bit;
 
-if (arm_pre_translate_insn(dc)) {
+if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
 dc->base.pc_next = pc + 2;
 return;
 }
-- 
2.25.1

[PATCH v4 02/10] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/translate.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index d6af5b1b03..ead77e9006 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9559,17 +9559,18 @@ static void arm_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 {
 DisasContext *dc = container_of(dcbase, DisasContext, base);
 CPUARMState *env = cpu->env_ptr;
+uint32_t pc = dc->base.pc_next;
 unsigned int insn;
 
 if (arm_pre_translate_insn(dc)) {
-dc->base.pc_next += 4;
+dc->base.pc_next = pc + 4;
 return;
 }
 
-dc->pc_curr = dc->base.pc_next;
-insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+dc->pc_curr = pc;
+insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
 dc->insn = insn;
-dc->base.pc_next += 4;
+dc->base.pc_next = pc + 4;
 disas_arm_insn(dc, insn);
 
 arm_post_translate_insn(dc);
-- 
2.25.1

[PATCH v4 00/10] target/arm: Fix insn exception priorities

[Richard Henderson]

Raise pc alignment faults.
Fix single-step and pc-align priority over breakpoints.
Not yet fixing insn abort priority over breakpoints.


r~


Changes for v4:
  * Rebase on master.
  * Split some cleanups into new patches.
  * No special cases in helper_exception_pc_alignment.

Changes for v3:
  * Rebase on siginfo_t patch set -- while probably only
force_sig_fault is required, I suspect minor conflicts
with the other cleanups.
  * Typo fix.

Changes for v2:
  * Handle the exceptions in cpu_loop.
  * Fix how the instruction is raised for aa32 el1.
  * Add pc alignment test cases.

Richard Henderson (10):
  target/arm: Hoist pc_next to a local variable in
aarch64_tr_translate_insn
  target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
  target/arm: Hoist pc_next to a local variable in
thumb_tr_translate_insn
  target/arm: Split arm_pre_translate_insn
  target/arm: Advance pc for arch single-step exception
  target/arm: Split compute_fsr_fsc out of arm_deliver_fault
  target/arm: Take an exception if PC is misaligned
  target/arm: Assert thumb pc is aligned
  target/arm: Suppress bp for exceptions with more priority
  tests/tcg: Add arm and aarch64 pc alignment tests

 target/arm/helper.h   |  1 +
 target/arm/syndrome.h |  5 +++
 linux-user/aarch64/cpu_loop.c | 46 --
 target/arm/debug_helper.c | 23 +++
 target/arm/gdbstub.c  |  9 -
 target/arm/machine.c  | 10 +
 target/arm/tlb_helper.c   | 63 ++-
 target/arm/translate-a64.c| 23 +--
 target/arm/translate.c| 58 
 tests/tcg/aarch64/pcalign-a64.c   | 37 ++
 tests/tcg/arm/pcalign-a32.c   | 46 ++
 tests/tcg/aarch64/Makefile.target |  4 +-
 tests/tcg/arm/Makefile.target |  4 ++
 13 files changed, 271 insertions(+), 58 deletions(-)
 create mode 100644 tests/tcg/aarch64/pcalign-a64.c
 create mode 100644 tests/tcg/arm/pcalign-a32.c

-- 
2.25.1

Re: [PATCH v2 30/30] bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Signed-off-by: Warner Losh
---
  bsd-user/x86_64/target_arch_signal.h | 9 +
  1 file changed, 1 insertion(+), 8 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 29/30] bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.h

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Signed-off-by: Warner Losh
---
  bsd-user/i386/target_arch_signal.h | 9 +
  1 file changed, 1 insertion(+), 8 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 27/30] bsd-user/i386/target_arch_signal.h: Remove target_sigcontext

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.

Signed-off-by: Warner Losh
---
  bsd-user/i386/target_arch_signal.h | 4 
  1 file changed, 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 28/30] bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontext

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.

Signed-off-by: Warner Losh
---
  bsd-user/x86_64/target_arch_signal.h | 4 
  1 file changed, 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 26/30] bsd-user: add arm target build

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

CC: Paolo Bonzini 
Signed-off-by: Warner Losh 
Acked-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
  configs/targets/arm-bsd-user.mak | 2 ++
  1 file changed, 2 insertions(+)
  create mode 100644 configs/targets/arm-bsd-user.mak

diff --git a/configs/targets/arm-bsd-user.mak b/configs/targets/arm-bsd-user.mak
new file mode 100644
index 00..90b6533195
--- /dev/null
+++ b/configs/targets/arm-bsd-user.mak
@@ -0,0 +1,2 @@
+TARGET_ARCH=arm
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml 
gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml 
gdb-xml/arm-m-profile.xml



Note that we just added one more xml file for m-profile mve.


r~

Re: [PATCH v2 25/30] bsd-user/arm/target_arch_signal.h: arm get_ucontext_sigreturn

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Update ucontext to implement sigreturn.

Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
  bsd-user/arm/target_arch_signal.h | 9 +
  1 file changed, 9 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 24/30] bsd-user/arm/target_arch_signal.h: arm set_mcontext

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

+env->regs[15] = tswap32(gr[TARGET_REG_PC]);


This will be able to crash qemu with an odd pc in thumb mode.
You'd have to artificially create this mcontext of course.

Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v2 22/30] bsd-user/arm/target_arch_signal.h: arm set_sigtramp_args

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

+/*
+ * Low bit indicates whether or not we're entering thumb mode.
+ */
+cpsr = cpsr_read(env);
+if (ka->_sa_handler & 1) {
+cpsr |= CPSR_T;
+} else {
+cpsr &= ~CPSR_T;
+}
+cpsr_write(env, cpsr, CPSR_T, CPSRWriteByInstr);


Like I said before, you don't need the cpsr_read, because the mask ensures that only 
CPSR_T will change:


  cpsr_write(env, (ka->_sa_handler & 1) * CPSR_T, CPSR_T, CPSRWriteByInstr);


Otherwise,
Reviewed-by: Richard Henderson 


r~

Re: [PATCH v2 21/30] bsd-user/arm/target_arch_signal.h: arm user context and trapframe for signals

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Arm specific user context structures for signal handling and the closely
related trap frame.

Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
  bsd-user/arm/target_arch_signal.h | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 20/30] bsd-user/arm/target_arch_signal.h: arm machine context for signals

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
  bsd-user/arm/target_arch_signal.h | 20 
  1 file changed, 20 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 18/30] bsd-user/freebsd: Create common target_os_ucontext.h file

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from sys/_ucontext.h with the comments about layout removed
because we don't support ancient FreeBSD binaries.

Signed-off-by: Warner Losh
---
  bsd-user/freebsd/target_os_signal.h   |  3 ---
  bsd-user/freebsd/target_os_ucontext.h | 26 ++
  2 files changed, 26 insertions(+), 3 deletions(-)
  create mode 100644 bsd-user/freebsd/target_os_ucontext.h


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 14/30] bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

+/*
+ * Thumb mode is encoded by the low bit in the entry point (since ARM can't
+ * execute at odd addresses). When it's set, set the Thumb bit (T) in the
+ * CPSR.
+ */
+if (entry & 0x1) {
+cpsr_write(env, cpsr_read(env) | CPSR_T, CPSR_T, CPSRWriteByInstr);
+}


This should be

  cpsr_write(env, (entry & 1) * CPSR_T, CPSR_T, CPSRWriteByInstr);

because you need to clear T for arm mode as well.


+/* FIXME - what to for failure of get_user()? */
+get_user_ual(regs->ARM_r2, stack + 8); /* envp */
+get_user_ual(regs->ARM_r1, stack + 4); /* envp */


Surely these values are present in image_info anyway?


r~

Re: [RFC PATCH v5 21/26] vhost: Add vhost_svq_valid_guest_features to shadow vq

[Jason Wang]

On Tue, Nov 2, 2021 at 4:10 PM Eugenio Perez Martin  wrote:
>
> On Tue, Nov 2, 2021 at 6:26 AM Jason Wang  wrote:
> >
> > On Sat, Oct 30, 2021 at 2:44 AM Eugenio Pérez  wrote:
> > >
> > > This allows it to test if the guest has aknowledge an invalid transport
> > > feature for SVQ. This will include packed vq layout or event_idx,
> > > where VirtIO device needs help from SVQ.
> > >
> > > There is not needed at this moment, but since SVQ will not re-negotiate
> > > features again with the guest, a failure in acknowledge them is fatal
> > > for SVQ.
> > >
> >
> > It's not clear to me why we need this. Maybe you can give me an
> > example. E.g isn't it sufficient to filter out the device with
> > event_idx?
> >
>
> If the guest did negotiate _F_EVENT_IDX, it expects to be notified
> only when device marks as used a specific number of descriptors.
>
> If we use VirtQueue notification, the VirtQueue code handles it
> transparently. But if we want to be able to change the guest VQ's
> call_fd, we cannot use VirtQueue's, so this needs to be handled by SVQ
> code. And that is still not implemented.
>
> Of course in the event_idx case we could just ignore it and notify in
> all used descriptors, but it seems not polite to me :). I will develop
> event_idx on top of this, either exposing the needed pieces in
> VirtQueue (I prefer this) or rolling our own in SVQ.

Yes, but what I meant is, we can fail the SVQ enabling if the device
supports event_idx. Then we're sure guests won't negotiate event_idx.

Thanks

>
> Same reasoning can be applied to unknown transport features.
>
> Thanks!
>
> > Thanks
> >
> > > Signed-off-by: Eugenio Pérez 
> > > ---
> > >  hw/virtio/vhost-shadow-virtqueue.h | 1 +
> > >  hw/virtio/vhost-shadow-virtqueue.c | 6 ++
> > >  2 files changed, 7 insertions(+)
> > >
> > > diff --git a/hw/virtio/vhost-shadow-virtqueue.h 
> > > b/hw/virtio/vhost-shadow-virtqueue.h
> > > index 946b2c6295..ac55588009 100644
> > > --- a/hw/virtio/vhost-shadow-virtqueue.h
> > > +++ b/hw/virtio/vhost-shadow-virtqueue.h
> > > @@ -16,6 +16,7 @@
> > >  typedef struct VhostShadowVirtqueue VhostShadowVirtqueue;
> > >
> > >  bool vhost_svq_valid_device_features(uint64_t *features);
> > > +bool vhost_svq_valid_guest_features(uint64_t *features);
> > >
> > >  void vhost_svq_set_svq_kick_fd(VhostShadowVirtqueue *svq, int 
> > > svq_kick_fd);
> > >  void vhost_svq_set_guest_call_notifier(VhostShadowVirtqueue *svq, int 
> > > call_fd);
> > > diff --git a/hw/virtio/vhost-shadow-virtqueue.c 
> > > b/hw/virtio/vhost-shadow-virtqueue.c
> > > index 6e0508a231..cb9ffcb015 100644
> > > --- a/hw/virtio/vhost-shadow-virtqueue.c
> > > +++ b/hw/virtio/vhost-shadow-virtqueue.c
> > > @@ -62,6 +62,12 @@ bool vhost_svq_valid_device_features(uint64_t 
> > > *dev_features)
> > >  return true;
> > >  }
> > >
> > > +/* If the guest is using some of these, SVQ cannot communicate */
> > > +bool vhost_svq_valid_guest_features(uint64_t *guest_features)
> > > +{
> > > +return true;
> > > +}
> > > +
> > >  /* Forward guest notifications */
> > >  static void vhost_handle_guest_kick(EventNotifier *n)
> > >  {
> > > --
> > > 2.27.0
> > >
> >
>

Re: [PATCH v2 08/30] bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

+case EXCP_UDEF:
+{
+/* See arm/arm/undefined.c undefinedinstruction(); */
+info.si_addr = env->regs[15];
+
+/*
+ * Make sure the PC is correctly aligned. (It should
+ * be.)
+ */
+if ((info.si_addr & 3) != 0) {
+info.si_signo = TARGET_SIGILL;
+info.si_errno = 0;
+info.si_code = TARGET_ILL_ILLADR;
+queue_signal(env, info.si_signo, &info);


You won't need this; unaligned pc will raise a different exception.


+} else {
+int rc = 0;
+#ifdef NOT_YET
+uint32_t opcode;
+
+/*
+ * Get the opcode.
+ *
+ * FIXME - what to do if get_user() fails?
+ */
+get_user_u32(opcode, env->regs[15]);
+
+/* Check the opcode with CP handlers we may have. */
+rc = EmulateAll(opcode, &ts->fpa, env);
+#endif /* NOT_YET */


Drop this til you need it.  Even then, we prefer to emulate all insns in the front-end. 
We can talk about what changes need to happen such that the actual CP registers are simply 
available at EL0.  I suspect they've already been done for linux-user anyway...



r~

Re: [RFC PATCH v5 23/26] util: Add iova_tree_alloc

[Jason Wang]

On Tue, Nov 2, 2021 at 4:29 PM Eugenio Perez Martin  wrote:
>
> On Tue, Nov 2, 2021 at 7:35 AM Jason Wang  wrote:
> >
> >
> > 在 2021/10/30 上午2:35, Eugenio Pérez 写道:
> > > This iova tree function allows it to look for a hole in allocated
> > > regions and return a totally new translation for a given translated
> > > address.
> > >
> > > It's usage is mainly to allow devices to access qemu address space,
> > > remapping guest's one into a new iova space where qemu can add chunks of
> > > addresses.
> > >
> > > Signed-off-by: Eugenio Pérez 
> > > ---
> > >   include/qemu/iova-tree.h |  17 +
> > >   util/iova-tree.c | 139 +++
> > >   2 files changed, 156 insertions(+)
> > >
> > > diff --git a/include/qemu/iova-tree.h b/include/qemu/iova-tree.h
> > > index 8249edd764..33f9b2e13f 100644
> > > --- a/include/qemu/iova-tree.h
> > > +++ b/include/qemu/iova-tree.h
> > > @@ -29,6 +29,7 @@
> > >   #define  IOVA_OK   (0)
> > >   #define  IOVA_ERR_INVALID  (-1) /* Invalid parameters */
> > >   #define  IOVA_ERR_OVERLAP  (-2) /* IOVA range overlapped */
> > > +#define  IOVA_ERR_NOMEM(-3) /* Cannot allocate */
> >
> >
> > I think we need a better name other than "NOMEM", since it's actually
> > means there's no sufficient hole for the range?
> >
>
> Actually, yes. I'm totally fine with changing it, but "the
> inspiration" is that ENOMEM is also the error that malloc sets in
> errno if not enough contiguous VM can be allocated.

Ok, then I think it's fine.

>
> What would be a more descriptive name?
>
> >
> > >
> > >   typedef struct IOVATree IOVATree;
> > >   typedef struct DMAMap {
> > > @@ -119,6 +120,22 @@ const DMAMap *iova_tree_find_address(const IOVATree 
> > > *tree, hwaddr iova);
> > >*/
> > >   void iova_tree_foreach(IOVATree *tree, iova_tree_iterator iterator);
> > >
> > > +/**
> > > + * iova_tree_alloc:
> > > + *
> > > + * @tree: the iova tree to allocate from
> > > + * @map: the new map (as translated addr & size) to allocate in iova 
> > > region
> > > + * @iova_begin: the minimum address of the allocation
> > > + * @iova_end: the maximum addressable direction of the allocation
> > > + *
> > > + * Allocates a new region of a given size, between iova_min and iova_max.
> > > + *
> > > + * Return: Same as iova_tree_insert, but cannot overlap and can be out of
> > > + * free contiguous range. Caller can get the assigned iova in map->iova.
> > > + */
> > > +int iova_tree_alloc(IOVATree *tree, DMAMap *map, hwaddr iova_begin,
> > > +hwaddr iova_end);
> > > +
> >
> >
> > "iova_tree_alloc_map" seems better.
> >
>
> Right, I changed in vhost but I forgot to change here.
>
> >
> > >   /**
> > >* iova_tree_destroy:
> > >*
> > > diff --git a/util/iova-tree.c b/util/iova-tree.c
> > > index 23ea35b7a4..27c921c4e2 100644
> > > --- a/util/iova-tree.c
> > > +++ b/util/iova-tree.c
> > > @@ -16,6 +16,36 @@ struct IOVATree {
> > >   GTree *tree;
> > >   };
> > >
> > > +/* Args to pass to iova_tree_alloc foreach function. */
> > > +struct IOVATreeAllocArgs {
> > > +/* Size of the desired allocation */
> > > +size_t new_size;
> > > +
> > > +/* The minimum address allowed in the allocation */
> > > +hwaddr iova_begin;
> > > +
> > > +/* The last addressable allowed in the allocation */
> > > +hwaddr iova_last;
> > > +
> > > +/* Previously-to-last iterated map, can be NULL in the first node */
> > > +const DMAMap *hole_left;
> > > +
> > > +/* Last iterated map */
> > > +const DMAMap *hole_right;
> >
> >
> > Any reason we can move those to IOVATree structure, it can simplify a
> > lot of things.
> >
>
> I can move for the next version for sure, but then it needs to be
> clear enough that these fields are alloc arguments.

Sure.

>
> >
> > > +};
> > > +
> > > +/**
> > > + * Iterate args to tne next hole
>
> s/tne/the/
>
> > > + *
> > > + * @args  The alloc arguments
> > > + * @next  The next mapping in the tree. Can be NULL to signal the last 
> > > one
> > > + */
> > > +static void iova_tree_alloc_args_iterate(struct IOVATreeAllocArgs *args,
> > > + const DMAMap *next) {
> > > +args->hole_left = args->hole_right;
> > > +args->hole_right = next;
> > > +}
> > > +
> > >   static int iova_tree_compare(gconstpointer a, gconstpointer b, gpointer 
> > > data)
> > >   {
> > >   const DMAMap *m1 = a, *m2 = b;
> > > @@ -107,6 +137,115 @@ int iova_tree_remove(IOVATree *tree, const DMAMap 
> > > *map)
> > >   return IOVA_OK;
> > >   }
> > >
> > > +/**
> > > + * Try to accomodate a map of size ret->size in a hole between
> > > + * max(end(hole_left), iova_start).
> > > + *
> > > + * @args Arguments to allocation
> > > + */
> > > +static bool iova_tree_alloc_map_in_hole(const struct IOVATreeAllocArgs 
> > > *args)
> > > +{
> > > +const DMAMap *left = args->hole_left, *right = args->hole_right;
> > > +uint64_t hole_start, hole_last;
> > > +
> > > +if 

Re: [PATCH v2 05/30] bsd-user/arm/target_arch_cpu.h: CPU Loop definitions

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

target_arch_cpu.h is for CPU loop definitions. Create the file and
define target_cpu_init and target_cpu_reset for arm.

Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
---
  bsd-user/arm/target_arch_cpu.h | 43 ++
  1 file changed, 43 insertions(+)
  create mode 100644 bsd-user/arm/target_arch_cpu.h


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 1/1] vhost: Fix last queue index of devices with no cvq

[Jason Wang]

On Tue, Nov 2, 2021 at 7:41 PM Eugenio Pérez  wrote:
>
> The -1 assumes that all devices with no cvq have an spare vq allocated
> for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This is an invalid
> device by the standard, so just stick to the right number of device
> models.
>
> This is not a problem to vhost-net, but it is to vhost-vdpa, which
> device model trust to reach the last index to finish starting the
> device.
>
> Tested with vp_vdpa with host's vhost=on and vhost=off.
>
> Fixes: 049eb15b5fc9 ("vhost: record the last virtqueue index for the virtio 
> device")
> Reviewed-by: Juan Quintela 
> Signed-off-by: Eugenio Pérez 
> ---
>  hw/net/vhost_net.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
> index 0d888f29a6..a859cc943d 100644
> --- a/hw/net/vhost_net.c
> +++ b/hw/net/vhost_net.c
> @@ -329,10 +329,6 @@ int vhost_net_start(VirtIODevice *dev, NetClientState 
> *ncs,
>  int r, e, i, last_index = data_queue_pairs * 2;
>  NetClientState *peer;
>
> -if (!cvq) {
> -last_index -= 1;
> -}
> -

So I think the math is wrong at least from the perspective of virtio:
If we had a device with 1 queue pair without cvq, last_index is 2 but
should be 1.

Another thing is that it may break the device with cvq. If we have a
device with 1 queue pair + cvq, last_index is 2.

We will start the device before cvq vhost_net is initialized. Since
for the first vhost_net device (first queue pair) we meet the:

dev->vq_index + dev->nvqs == dev->last_index (0 + 2 == 2).

Then we set DRIVER_OK before initializing cvq.

Thanks

>  if (!k->set_guest_notifiers) {
>  error_report("binding does not support guest notifiers");
>  return -ENOSYS;
> --
> 2.27.0
>

[PATCH v3] Optimized the function of fill_connection_key.

[Rao, Lei]

From: "Rao, Lei" 

Remove some unnecessary code to improve the performance of
the filter-rewriter module.

Signed-off-by: Lei Rao 
Reviewed-by: Zhang Chen 
Reviewed-by: Juan Quintela 
---
 net/colo-compare.c|  2 +-
 net/colo.c| 31 ---
 net/colo.h|  6 +++---
 net/filter-rewriter.c | 10 +-
 4 files changed, 17 insertions(+), 32 deletions(-)

diff --git a/net/colo-compare.c b/net/colo-compare.c
index 4a64a5d..b8876d7 100644
--- a/net/colo-compare.c
+++ b/net/colo-compare.c
@@ -264,7 +264,7 @@ static int packet_enqueue(CompareState *s, int mode, 
Connection **con)
 pkt = NULL;
 return -1;
 }
-fill_connection_key(pkt, &key);
+fill_connection_key(pkt, &key, false);
 
 conn = connection_get(s->connection_track_table,
   &key,
diff --git a/net/colo.c b/net/colo.c
index 3a3e6e8..1f8162f 100644
--- a/net/colo.c
+++ b/net/colo.c
@@ -83,19 +83,26 @@ int parse_packet_early(Packet *pkt)
 return 0;
 }
 
-void extract_ip_and_port(uint32_t tmp_ports, ConnectionKey *key, Packet *pkt)
+void extract_ip_and_port(uint32_t tmp_ports, ConnectionKey *key,
+ Packet *pkt, bool reverse)
 {
+if (reverse) {
+key->src = pkt->ip->ip_dst;
+key->dst = pkt->ip->ip_src;
+key->src_port = ntohs(tmp_ports & 0x);
+key->dst_port = ntohs(tmp_ports >> 16);
+} else {
 key->src = pkt->ip->ip_src;
 key->dst = pkt->ip->ip_dst;
 key->src_port = ntohs(tmp_ports >> 16);
 key->dst_port = ntohs(tmp_ports & 0x);
+}
 }
 
-void fill_connection_key(Packet *pkt, ConnectionKey *key)
+void fill_connection_key(Packet *pkt, ConnectionKey *key, bool reverse)
 {
-uint32_t tmp_ports;
+uint32_t tmp_ports = 0;
 
-memset(key, 0, sizeof(*key));
 key->ip_proto = pkt->ip->ip_p;
 
 switch (key->ip_proto) {
@@ -106,29 +113,15 @@ void fill_connection_key(Packet *pkt, ConnectionKey *key)
 case IPPROTO_SCTP:
 case IPPROTO_UDPLITE:
 tmp_ports = *(uint32_t *)(pkt->transport_header);
-extract_ip_and_port(tmp_ports, key, pkt);
 break;
 case IPPROTO_AH:
 tmp_ports = *(uint32_t *)(pkt->transport_header + 4);
-extract_ip_and_port(tmp_ports, key, pkt);
 break;
 default:
 break;
 }
-}
-
-void reverse_connection_key(ConnectionKey *key)
-{
-struct in_addr tmp_ip;
-uint16_t tmp_port;
-
-tmp_ip = key->src;
-key->src = key->dst;
-key->dst = tmp_ip;
 
-tmp_port = key->src_port;
-key->src_port = key->dst_port;
-key->dst_port = tmp_port;
+extract_ip_and_port(tmp_ports, key, pkt, reverse);
 }
 
 Connection *connection_new(ConnectionKey *key)
diff --git a/net/colo.h b/net/colo.h
index d91cd24..8b3e8d5 100644
--- a/net/colo.h
+++ b/net/colo.h
@@ -89,9 +89,9 @@ typedef struct Connection {
 uint32_t connection_key_hash(const void *opaque);
 int connection_key_equal(const void *opaque1, const void *opaque2);
 int parse_packet_early(Packet *pkt);
-void extract_ip_and_port(uint32_t tmp_ports, ConnectionKey *key, Packet *pkt);
-void fill_connection_key(Packet *pkt, ConnectionKey *key);
-void reverse_connection_key(ConnectionKey *key);
+void extract_ip_and_port(uint32_t tmp_ports, ConnectionKey *key,
+ Packet *pkt, bool reverse);
+void fill_connection_key(Packet *pkt, ConnectionKey *key, bool reverse);
 Connection *connection_new(ConnectionKey *key);
 void connection_destroy(void *opaque);
 Connection *connection_get(GHashTable *connection_track_table,
diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c
index cb3a96c..bf05023 100644
--- a/net/filter-rewriter.c
+++ b/net/filter-rewriter.c
@@ -279,15 +279,7 @@ static ssize_t colo_rewriter_receive_iov(NetFilterState 
*nf,
  */
 if (pkt && is_tcp_packet(pkt)) {
 
-fill_connection_key(pkt, &key);
-
-if (sender == nf->netdev) {
-/*
- * We need make tcp TX and RX packet
- * into one connection.
- */
-reverse_connection_key(&key);
-}
+fill_connection_key(pkt, &key, sender == nf->netdev);
 
 /* After failover we needn't change new TCP packet */
 if (s->failover_mode &&
-- 
1.8.3.1

Re: [PATCH] net/vhost-vdpa: fix memory leak in vhost_vdpa_get_max_queue_pairs()

[Jason Wang]

On Tue, Nov 2, 2021 at 11:52 PM Stefano Garzarella  wrote:
>
> Use g_autofree to ensure that `config` is freed when
> vhost_vdpa_get_max_queue_pairs() returns.
>
> Reported-by: Coverity (CID 1465228: RESOURCE_LEAK)
> Fixes: 402378407d ("vhost-vdpa: multiqueue support")
> Signed-off-by: Stefano Garzarella 

Acked-by: Jason Wang 

> ---
>  net/vhost-vdpa.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
> index 49ab322511..373b706b90 100644
> --- a/net/vhost-vdpa.c
> +++ b/net/vhost-vdpa.c
> @@ -214,7 +214,7 @@ static NetClientState *net_vhost_vdpa_init(NetClientState 
> *peer,
>  static int vhost_vdpa_get_max_queue_pairs(int fd, int *has_cvq, Error **errp)
>  {
>  unsigned long config_size = offsetof(struct vhost_vdpa_config, buf);
> -struct vhost_vdpa_config *config;
> +g_autofree struct vhost_vdpa_config *config = NULL;
>  __virtio16 *max_queue_pairs;
>  uint64_t features;
>  int ret;
> --
> 2.31.1
>

[Bug 1903712] Re: when ../configure, cannot find Ninjia

[Shi]

1、install re2c。[url：http://re2c.org/index.html]
tar -xvzf re2c-1.0.3.tar.gz
cd re2c-1.0.3/
autoreconf -i -W all
./configure
make&&make install
2、git clone git://github.com/ninja-build/ninja.git && cd ninja
./configure.py --bootstrap
cp ninja /usr/bin/

[root@aix7 ~]# ninja --version
1.10.2.git

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1903712

Title:
  when ../configure, cannot find Ninjia

Status in QEMU:
  Expired

Bug description:
  On unbuntu18.04, after finishing

  wget https://download.qemu.org/qemu-5.2.0-rc0.tar.xz
  tar xvJf qemu-5.2.0-rc0.tar.xz
  cd qemu-5.2.0-rc0

  when I input

  mkdir build
  cd build
  ../configure

  Return Error:
  cannot find Ninjia

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1903712/+subscriptions

RE: [PATCH v2 7/7] Optimized the function of fill_connection_key.

[Rao, Lei]

Will be changed and sent separately.

Thanks,
Lei

-Original Message-
From: Juan Quintela  
Sent: Wednesday, November 3, 2021 12:23 AM
To: Rao, Lei 
Cc: Zhang, Chen ; lizhij...@cn.fujitsu.com; 
jasow...@redhat.com; zhang.zhanghaili...@huawei.com; lukasstra...@web.de; 
dgilb...@redhat.com; qemu-devel@nongnu.org
Subject: Re: [PATCH v2 7/7] Optimized the function of fill_connection_key.

"Rao, Lei"  wrote:
> From: "Rao, Lei" 
>
> Remove some unnecessary code to improve the performance of the 
> filter-rewriter module.
>
> Signed-off-by: Lei Rao 
> Reviewed-by: Zhang Chen 

As Chen has already reviewed it:

Reviewed-by: Juan Quintela 

But I think that you should change in a following patch:

s/int reverse/bool reverse/

Later, Juan.

Re: [PATCH v5 06/26] arm: qemu: Add a devicetree file for qemu_arm64

[Simon Glass]

Hi Tom,

On Tue, 2 Nov 2021 at 10:57, Tom Rini  wrote:
>
> On Tue, Nov 02, 2021 at 08:59:45AM -0600, Simon Glass wrote:
> > Hi François,
> >
> > On Mon, 1 Nov 2021 at 11:33, François Ozog  wrote:
> > >
> > > Hi Simon
> > >
> > > Le lun. 1 nov. 2021 à 17:58, Simon Glass  a écrit :
> > >>
> > >> Hi Peter,
> > >>
> > >> On Mon, 1 Nov 2021 at 04:48, Peter Maydell  
> > >> wrote:
> > >> >
> > >> > On Tue, 26 Oct 2021 at 01:33, Simon Glass  wrote:
> > >> > >
> > >> > > Add this file, generated from qemu, so there is a reference 
> > >> > > devicetree
> > >> > > in the U-Boot tree.
> > >> > >
> > >> > > Signed-off-by: Simon Glass 
> > >> >
> > >> > Note that the dtb you get from QEMU is only guaranteed to work if:
> > >> >  1) you run it on the exact same QEMU version you generated it with
> > >> >  2) you pass QEMU the exact same command line arguments you used
> > >> > when you generated it
> > >>
> > >> Yes, I certainly understand that. In general this is not safe, but in
> > >> practice it works well enough for development and CI.
> > >
> > > You recognize that you hijack a product directory with development hack 
> > > facility. There is a test directory to keep things clear. There can be a 
> > > dev-dts or something similar for Dev time tools.
> > > I have only seen push back on those fake dts files in the dts directory: 
> > > I guess that unless someone strongly favors a continuation of the 
> > > discussion, you may consider re-shaping the proposal to address concerns.
> >
> > As stated previously, I would like to have at least a sample DT
> > in-tree for all boards. I cannot see another way to get the Kconfig
>
> What's the point of having a sample when it's not going to always be
> correct or may be actively wrong and we can tell interested developers /
> users how to get the correct DTB/DTS to examine?
>
> > options in line. If we are able to put these files somewhere else in
> > the future and get them out of U-Boot, with perhaps just an overlay
> > for development purposes, I'd be keen to see it. But for now, this is
> > where we are, I believe.
> >
> > In this particular case, this is not just a dev hack. It is also for
> > CI tests which need to use a devicetree. See for example here:
> >
> > https://patchwork.ozlabs.org/project/uboot/patch/20211101011734.1614781-15-...@chromium.org/
> > https://patchwork.ozlabs.org/project/uboot/patch/20211101011734.1614781-24-...@chromium.org/
>
> This example would probably be better done on vexpress_ca9x4 where we do
> test in CI via QEMU but do not need to modify a device tree that is
> passed on to us, we already control the source of truth DTB in this
> case.

But that board:

- uses OF_EMBED, which it should not
- does not use SPL, which I need

>
> And also yes, I'm behind on reviewing things I need to review.

Aren't we all...I can't even keep up with these threads.

Regards,
Simon

Re: [PATCH v5 06/26] arm: qemu: Add a devicetree file for qemu_arm64

[Simon Glass]

Hi Tom,

On Tue, 2 Nov 2021 at 11:28, Tom Rini  wrote:
>
> On Tue, Nov 02, 2021 at 09:00:53AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Mon, 1 Nov 2021 at 12:07, Tom Rini  wrote:
> > >
> > > On Mon, Nov 01, 2021 at 06:33:35PM +0100, François Ozog wrote:
> > > > Hi Simon
> > > >
> > > > Le lun. 1 nov. 2021 à 17:58, Simon Glass  a écrit :
> > > >
> > > > > Hi Peter,
> > > > >
> > > > > On Mon, 1 Nov 2021 at 04:48, Peter Maydell 
> > > > > wrote:
> > > > > >
> > > > > > On Tue, 26 Oct 2021 at 01:33, Simon Glass  wrote:
> > > > > > >
> > > > > > > Add this file, generated from qemu, so there is a reference 
> > > > > > > devicetree
> > > > > > > in the U-Boot tree.
> > > > > > >
> > > > > > > Signed-off-by: Simon Glass 
> > > > > >
> > > > > > Note that the dtb you get from QEMU is only guaranteed to work if:
> > > > > >  1) you run it on the exact same QEMU version you generated it with
> > > > > >  2) you pass QEMU the exact same command line arguments you used
> > > > > > when you generated it
> > > > >
> > > > > Yes, I certainly understand that. In general this is not safe, but in
> > > > > practice it works well enough for development and CI.
> > > >
> > > > You recognize that you hijack a product directory with development hack
> > > > facility. There is a test directory to keep things clear. There can be a
> > > > dev-dts or something similar for Dev time tools.
> > > > I have only seen push back on those fake dts files in the dts 
> > > > directory: I
> > > > guess that unless someone strongly favors a continuation of the 
> > > > discussion,
> > > > you may consider re-shaping the proposal to address concerns.
> > >
> > > Yes.  We need to document how to make development easier.  But I'm still
> > > not on board with the notion of including DTS files for platforms where
> > > the source of truth for the DTB is elsewhere.  That's going to bring us
> > > a lot more pain.
> >
> > Are you talking about QEMU specifically, or Raspberry Pi?
>
> I was using two of the more common and readily available platforms where
> the source of truth for the DTS/DTB is not (and will not be) U-Boot.
>
> > How can we get this resolved? I very much want to get to just having
> > OF_SEPARATE and OF_EMBED as the only available build-time options,
> > with OF_BOARD (and perhaps OF_PASSAGE) as something we can enable for
> > runtime support. I feel that separating the build-time and run-time
> > behaviour is very important. Over time perhaps we will have some
> > success in upstreaming bindings, but for now we have what we have.
> > There is still a lot of pushback on U-Boot having things in the
> > devicetree, although I do see that softening somewhat.
>
>
> To reiterate, the uniform bit of feedback on this series has been that
> everyone else disagrees with your notion that we _must_ have a dts
> in-tree.

[I would like everyone to take a deep breath and think about what this
actually impacts. I argue the impact outside U-Boot is approximately
zero. What are we actually discussing here?]

A few have responded that they can just add the files. I think that is
the case for everything except QEMU, right? I think even François
agrees with the documentation argument. There is no real burden in
adding the files so we can see what is going on, add a binman node,
SPL nodes, etc.

So I am going to stand my ground on that one. It affects:

- highbank
- qemu-ppce500
- rpi_4
- xilinx_versal_virt
- octeontx
- xenguest_arm64
- juno

So that is just 7 boards that I want to add devicetree files for. I
think that is reasonable and not a burden on these maintainers.

Let me deal with QEMU.

Let's imagine that we were in the state that I am proposing here,
which we would be if I were a better devicetree maintainer for U-Boot
and had not taken my eye off the ball, basically with my review of
[1], where I should have pushed to get a response on the questions
before it was applied. That might have triggered me to think about the
implications of this at the time.

Anyway, in the state that I am proposing, what problems would we have?

1. QEMU has a DT which only matches the 'standard' invocation as
documented at [2]

2. QEMU may get out of date if there is a new release.

I don't think (1) is really a problem. People will have to remove
CONFIG_OF_BOARD from configs/qemu_arm_spl_defconfig (or the like) to
get into this state, and we have a message now that prints out where
the devicetree comes from ("separate" in this case):

Core:  42 devices, 11 uclasses, devicetree: separate

For (2), I tested QEMU 6.1.50 and the only difference from 4.2.1 (a
year old) is:

kaslr-seed = <0x2037f53d 0x42c279e8>;

It doesn't affect anything here. It boots the lastest image fine.

Just for interest I went back to 2.5.0 which is nearly 6 years old!
There are a few differences like dma-coherent and gpio-keys being
added, but again it boots fine.

So in practice that doesn't seem to be a problem from what I can tell.

3. Anything else?

For qemu_arm_spl, it 

Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr

[Richard Henderson]

On 11/2/21 9:06 PM, liweiwei wrote:


在 2021/11/3 上午1:56, Richard Henderson 写道:

On 11/1/21 11:11 PM, liweiwei wrote:

+    if (cpu->cfg.ext_zk) {
+    cpu->cfg.ext_zbkb = true;
+    cpu->cfg.ext_zbkc = true;
+    cpu->cfg.ext_zbkx = true;
+    cpu->cfg.ext_zknd = true;
+    cpu->cfg.ext_zkne = true;
+    cpu->cfg.ext_zknh = true;
+    cpu->cfg.ext_zkr = true;
+    }


Section 2.12 lists instead the larger Zkn, Zks, Zkt extensions.
I think it's better to follow that.

OK. I'll replace this with setting ext_zkn, ext_zks, ext_zkt true. By the way, Zkt only 
includes partial RVI/M/C instructions. Is it neccessary to distinguish them?


I don't know if Zkt needs to be called out; it probably depends on whether it is exposed 
to the guest via some MISA csr extension.



r~

Re: [PATCH v5 00/26] fdt: Make OF_BOARD a boolean option

[Simon Glass]

Hi François,

On Wed, 27 Oct 2021 at 14:07, François Ozog  wrote:
>
> Hi Simon
>
> Le mer. 27 oct. 2021 à 20:23, Simon Glass  a écrit :
>>
>> Hi François,
>>
>> On Wed, 27 Oct 2021 at 09:14, François Ozog  wrote:
>> >
>> >
>> >
>> > On Wed, 27 Oct 2021 at 16:08, Simon Glass  wrote:
>> >>
>> >> Hi François,
>> >>
>> >> On Tue, 26 Oct 2021 at 00:07, François Ozog  
>> >> wrote:
>> >> >
>> >> > Hi Simon
>> >> >
>> >> > Position unchanged on this series: adding fake dts for boards that 
>> >> > generate their device tree in the dts directory is not good. If you 
>> >> > have them in documentation the it is acceptable.
>> >>
>> >> I think we are going to have to disagree on this one. I actually used
>> >> the qemu one in testing/development recently. We have to have a way to
>> >> develop in-tree with U-Boot. It does not impinge on any of your use
>> >> cases, so far as I know.
>> >
>> > I am not the only one in disagreement... You just saw Alex Bénée from Qemu 
>> > saying the same thing.
>> > I understand the advanced debug/development scenario you mention.
>> > But locating the DT files in the dts directory is mis-leading the 
>> > contributors to think that they need to compile the DT for the targeted 
>> > platforms.
>> > For your advanced scenario, you can still have the dts in the 
>> > documentation area, or whatever directory (except dts). compile it and 
>> > supply to U-Boot.
>>
>> We have this situation with rpi 1, 2 and 3 and I don't believe anyone
>> has noticed. U-Boot handles the build automatically. If you turn off
>> OF_BOARD, it will use the U-Boot devicetree always so you know what is
>> going on.
>>
>> We can add a message to U-Boot indicating where the devicetree came
>> from, perhaps? That might be useful given everything that is going on.
>>
>> As in this case, quite often in these discussions I struggle to
>> understand what is behind the objection. Is it that your customers are
>> demanding that devicetrees become private, secret data, not included
>> in open-source projects? Or is it just the strange case of QEMU that
>> is informing your thinking? I know of at least one project where the
>> first-stage bootloader produces a devicetree and no one has the source
>> for it. I believe TF-A was created for licensing reasons...so can you
>> be a bit clearer about what the problem actually is?
>
> there are situations where U-Boot must have a dtb. Then those dTB sources are 
> logically found in the dts directory.
> There are situations where U-Boot should not have a dtb. In that case there 
> should be no element in the dts directory. Otherwise it creates confusion.
> Now as you point out, we need “playgrounds” to deal with some situation. So 
> having examples in an ad-hoc directory, different from dts is fine. I 
> proposed documentation but you may find a better place.
> In other words, dts shall host only dt source when U-Boot cannot do but make 
> a dTB for a platform.
> As you have seen in different mail thread (firmware sustainability and OCP 
> checklist) freedom is important to Linaro and there are no hidden Trojan 
> horse for licensing.

I don't understand what you are getting at with the Trojan horse. But
you have no objection to requiring boards to supply a DT (whether in
documentation or arch/arm/dts) to be in U-Boot?

>
>
>> If a board is
>> in-tree in U-Boot I would like it to have a devicetree there, at least
>> until we have a better option. At the very least, it MUST be
>> discoverable and it must be possible to undertake U-Boot development
>> easily without a lot of messing around.
>
> You can if you keep two dts directories separate:
> dts for boards for which U-Boot must have one
> debug-dts for boards for which U-Boot get the DT at runtime but for which you 
> want a playground for debug/easier development.
>>
>>
>> >>
>> >>
>> >> But trying to do any driver / core work for a board where you don't
>> >> have the devicetree is currently not possible. The devicetree is a
>> >> core component and being unable to modify it is simply not practical.
>> >> We are talking here about an option that can be enabled or disabled.
>> >> In my case I am able to disable it locally and do my development work.
>> >>
>> >>
>> >> BTW I've got the bloblist handoff working with a devicetree inside it,
>> >> for qemu_arm. I need to try it on a real board to figure out what the
>> >> difference is.
>> >>
>> > That's great news and much needed for stabilizing the inbound ABI from 
>> > prior loader to U-Boot. Let's create another thread to discuss this 
>> > important topic.
>> >>
>>
>> My scenario is not all that advanced and I am using qemu_arm to test
>> the bloblist handoff stuff and include it in CI, with a suitable
>> devicetree and a binman node.
>>
>> Regards,
>> Simon
>>
>> >> >
>> >> > Cheers
>> >> >
>> >> > FF
>> >> >
>> >> > Le mar. 26 oct. 2021 à 02:24, Simon Glass  a écrit :
>> >> >>
>> >> >> With Ilias' efforts we have dropped OF_PRIOR_STAGE and OF_HOSTFILE so
>> >> >> there a

Re: [PATCH v5 00/26] fdt: Make OF_BOARD a boolean option

[Simon Glass]

Hi Mark,

On Wed, 27 Oct 2021 at 16:30, Mark Kettenis  wrote:
>
> > From: Simon Glass 
> > Date: Wed, 27 Oct 2021 12:23:21 -0600
> >
> > Hi François,
> >
> > On Wed, 27 Oct 2021 at 09:14, François Ozog  
> > wrote:
> > >
> > >
> > >
> > > On Wed, 27 Oct 2021 at 16:08, Simon Glass  wrote:
> > >>
> > >> Hi François,
> > >>
> > >> On Tue, 26 Oct 2021 at 00:07, François Ozog  
> > >> wrote:
> > >> >
> > >> > Hi Simon
> > >> >
> > >> > Position unchanged on this series: adding fake dts for boards that 
> > >> > generate their device tree in the dts directory is not good. If you 
> > >> > have them in documentation the it is acceptable.
> > >>
> > >> I think we are going to have to disagree on this one. I actually used
> > >> the qemu one in testing/development recently. We have to have a way to
> > >> develop in-tree with U-Boot. It does not impinge on any of your use
> > >> cases, so far as I know.
> > >
> > > I am not the only one in disagreement... You just saw Alex Bénée from 
> > > Qemu saying the same thing.
> > > I understand the advanced debug/development scenario you mention.
> > > But locating the DT files in the dts directory is mis-leading the 
> > > contributors to think that they need to compile the DT for the targeted 
> > > platforms.
> > > For your advanced scenario, you can still have the dts in the 
> > > documentation area, or whatever directory (except dts). compile it and 
> > > supply to U-Boot.
> >
> > We have this situation with rpi 1, 2 and 3 and I don't believe anyone
> > has noticed. U-Boot handles the build automatically. If you turn off
> > OF_BOARD, it will use the U-Boot devicetree always so you know what is
> > going on.
>
> Until.  The Raspberry Pi foundation releases a new firmware that
> configures the hardware differently such that the addresses in the
> U-Boot devicetree are wrong and nothing works anymore.  Can't speak
> for the rpi 1, but this has happened in the past for the rpi 2 and 3
> as well as more recently on the rpi 4.

So I update my SD card with a new private-binary bootloader and things
stop working? I think I can narrow that one down :-)

>
> > We can add a message to U-Boot indicating where the devicetree came
> > from, perhaps? That might be useful given everything that is going on.
> >
> > As in this case, quite often in these discussions I struggle to
> > understand what is behind the objection. Is it that your customers are
> > demanding that devicetrees become private, secret data, not included
> > in open-source projects? Or is it just the strange case of QEMU that
> > is informing your thinking? I know of at least one project where the
> > first-stage bootloader produces a devicetree and no one has the source
> > for it. I believe TF-A was created for licensing reasons...so can you
> > be a bit clearer about what the problem actually is? If a board is
> > in-tree in U-Boot I would like it to have a devicetree there, at least
> > until we have a better option. At the very least, it MUST be
> > discoverable and it must be possible to undertake U-Boot development
> > easily without a lot of messing around.
>
> How many people are there out there that work on U-Boot that don't
> have a Linux source tree checked out?  Even I have several of those
> lying around on my development systems and I am an OpenBSD developer ;).

So it is OK to have the DT in Linux but not in U-Boot? I don't even
know what to say that. How does that square with your point above?

I am not talking about disabling OF_BOARD, just making it *possible* to do so.

Regards,
Simon

Re: [PULL 0/4] Trivial branch for 6.2 patches

[BALATON Zoltan]

On Wed, 3 Nov 2021, Laurent Vivier wrote:

The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:

 Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into 
staging (2021-10-30 11:31:41 -0700)

are available in the Git repository at:

 git://github.com/vivier/qemu.git tags/trivial-branch-for-6.2-pull-request

for you to fetch changes up to 5d2bd73588d14b5868129ace9c7912a777f06753:

 hw/input/lasips2: Fix typos in function names (2021-10-31 21:05:40 +0100)


Trivial patches branch pull request 20211101 v2


Did you see this one?
https://patchew.org/QEMU/20211030095225.513d4748...@zero.eik.bme.hu/

Could somebody take it please?

Regards,
BALATON Zoltan




Markus Armbruster (1):
 monitor: Trim some trailing space from human-readable output

Philippe Mathieu-Daudé (2):
 MAINTAINERS: Split HPPA TCG vs HPPA machines/hardware
 hw/input/lasips2: Fix typos in function names

Yanan Wang (1):
 hw/core/machine: Add the missing delimiter in cpu_slot_to_string()

MAINTAINERS| 5 ++---
hw/core/machine.c  | 3 +++
hw/input/lasips2.c | 8 
monitor/hmp-cmds.c | 2 +-
target/i386/cpu-dump.c | 4 ++--
target/i386/cpu.c  | 2 +-
target/ppc/cpu_init.c  | 2 +-
target/s390x/cpu_models.c  | 4 ++--
target/xtensa/mmu_helper.c | 2 +-
9 files changed, 17 insertions(+), 15 deletions(-)

--
2.31.1

Re: [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk*

[liweiwei]

在 2021/11/3 上午2:56, Richard Henderson 写道:

On 11/1/21 11:11 PM, liweiwei wrote:

+uint8_t AES_ENC_SBOX[] = {
+  0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
+  0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
+  0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
+  0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,


Use "crypto/aes.h".


OK. I'll reuse this.



+/* SM4 forward SBox. SM4 has no inverse sbox. */
+static const uint8_t sm4_sbox[256] = {
+    0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 
0x14, 0xC2,
+    0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 
0x04, 0xC3,
+    0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 
0x50, 0xF4,


Hmm.  We have an existing copy of this in target/arm/crypto_helper.c.  
I think we should move that code out to a shared location like aes.

OK. I'll try to move it.



+#define sext_xlen(x) (((int64_t)(x) << (XLEN - 32)) >> (XLEN  - 32))


This is (target_ulong)(int32_t)(x).


OK. I'll improve this.


r~

Re: [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr

[liweiwei]

在 2021/11/3 上午1:56, Richard Henderson 写道:

On 11/1/21 11:11 PM, liweiwei wrote:

+    if (cpu->cfg.ext_zk) {
+    cpu->cfg.ext_zbkb = true;
+    cpu->cfg.ext_zbkc = true;
+    cpu->cfg.ext_zbkx = true;
+    cpu->cfg.ext_zknd = true;
+    cpu->cfg.ext_zkne = true;
+    cpu->cfg.ext_zknh = true;
+    cpu->cfg.ext_zkr = true;
+    }


Section 2.12 lists instead the larger Zkn, Zks, Zkt extensions.
I think it's better to follow that.

OK. I'll replace this with setting ext_zkn, ext_zks, ext_zkt true. By 
the way, Zkt only includes partial RVI/M/C instructions. Is it 
neccessary to distinguish them?


r~

Re: [PULL 0/9] pc,pci,virtio: features, fixes

[Richard Henderson]

On 11/1/21 7:44 PM, Michael S. Tsirkin wrote:

The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:

   Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into 
staging (2021-10-30 11:31:41 -0700)

are available in the Git repository at:

   git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream

for you to fetch changes up to d99e8b5fcb138b19f751c027ed5599224f9b5036:

   hw/i386: fix vmmouse registration (2021-11-01 19:36:11 -0400)


pc,pci,virtio: features, fixes

virtio-iommu support for x86/ACPI.
Fixes, cleanups all over the place.

Signed-off-by: Michael S. Tsirkin 


David Hildenbrand (1):
   vhost-vdpa: Set discarding of RAM broken when initializing the backend

Igor Mammedov (1):
   qtest: fix 'expression is always false' build failure in 
qtest_has_accel()

Jean-Philippe Brucker (4):
   hw/acpi: Add VIOT table
   hw/i386/pc: Remove x86_iommu_get_type()
   hw/i386/pc: Move IOMMU singleton into PCMachineState
   hw/i386/pc: Allow instantiating a virtio-iommu device

Pavel Dovgalyuk (1):
   hw/i386: fix vmmouse registration

Peter Xu (2):
   pci: Define pci_bus_dev_fn/pci_bus_fn/pci_bus_ret_fn
   pci: Export pci_for_each_device_under_bus*()

  hw/acpi/viot.h  |  13 +
  include/hw/i386/pc.h|   1 +
  include/hw/i386/x86-iommu.h |  12 -
  include/hw/pci/pci.h|  24 ++
  hw/acpi/viot.c  | 114 
  hw/i386/acpi-build.c|  33 +++--
  hw/i386/amd_iommu.c |   2 -
  hw/i386/intel_iommu.c   |   3 --
  hw/i386/pc.c|  26 +-
  hw/i386/vmmouse.c   |   1 +
  hw/i386/x86-iommu-stub.c|   5 --
  hw/i386/x86-iommu.c |  31 
  hw/pci/pci.c|  26 --
  hw/pci/pcie.c   |   4 +-
  hw/ppc/spapr_pci.c  |  12 ++---
  hw/ppc/spapr_pci_nvlink2.c  |   7 ++-
  hw/ppc/spapr_pci_vfio.c |   4 +-
  hw/s390x/s390-pci-bus.c |   5 +-
  hw/virtio/vhost-vdpa.c  |  13 +
  hw/xen/xen_pt.c |   4 +-
  hw/acpi/Kconfig |   4 ++
  hw/acpi/meson.build |   1 +
  hw/i386/Kconfig |   1 +
  meson.build |   2 +-
  24 files changed, 239 insertions(+), 109 deletions(-)
  create mode 100644 hw/acpi/viot.h
  create mode 100644 hw/acpi/viot.c


Applied, thanks.

r~

Re: [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc.

[liweiwei]

Thanks for your suggestions.

在 2021/11/2 下午11:44, Richard Henderson 写道:

On 11/1/21 11:11 PM, liweiwei wrote:

Signed-off-by: liweiwei 
Signed-off-by: wangjunqiang 


You managed to get the whole patch description into the subject line.
Please break it up.


OK.

+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+    return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}


Are we expecting to see the full grev instruction at any point? If 
not, we can certainly implement Zbk with a simpler implementation.
The main idea that I add this helper is that  grev may be added to 
B-extension later and it can be reused. However, it have no effect 
currently.  I'll replace this with a simpler implementation.


+target_ulong HELPER(xperm)(target_ulong rs1, target_ulong rs2, 
uint32_t sz_log2)

+{
+    target_ulong r = 0;
+    target_ulong sz = 1LL << sz_log2;
+    target_ulong mask = (1LL << sz) - 1;
+    for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+    target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
+    if (pos < sizeof(target_ulong) * 8) {
+    r |= ((rs1 >> pos) & mask) << i;
+    }
+    }
+    return r;
+}


This could become a static inline do_xperm, and provide two specific 
xperm4 and xperm8 helpers; the compiler would fold all of the sz_log2 
stuff into a more efficient implementation.

OK.



+target_ulong HELPER(unshfl)(target_ulong rs1,
+    target_ulong rs2)
+{
+    target_ulong x = rs1;
+    int i, shift;
+    int bits = TARGET_LONG_BITS >> 1;
+    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+    if (rs2 & shift) {
+    x = do_shuf_stage(x, shuf_masks[i], shuf_masks[i] >> 
shift, shift);

+    }
+    }
+    return x;
+}
+
+target_ulong HELPER(shfl)(target_ulong rs1,
+  target_ulong rs2)
+{
+    target_ulong x = rs1;
+    int i, shift;
+    shift = TARGET_LONG_BITS >> 2;
+    i = (shift == 8) ? 3 : 4;
+    for (; i >= 0; i--, shift >>= 1) {
+    if (rs2 & shift) {
+    x = do_shuf_stage(x, shuf_masks[i], shuf_masks[i] >> 
shift, shift);

+    }
+    }
+    return x;
+}


Similar comment as for grev.


+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+  zext_h_32  100 0 . 100 . 0110011 @r2
+  pack   100 . . 100 . 0110011 @r
+}


Note to self: improve tcg_gen_deposit to notice zeros, so that the 
more general pack compiles to zero-extension.


@@ -556,6 +563,81 @@ static bool gen_unary_per_ol(DisasContext *ctx, 
arg_r2 *a, DisasExtend ext,

  return gen_unary(ctx, a, ext, f_tl);
  }
  +static bool gen_xperm(DisasContext *ctx, arg_r *a, int32_t size)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    TCGv_i32 sz = tcg_const_i32(size);
+    gen_helper_xperm(dest, src1, src2, sz);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free_i32(sz);
+    return true;
+}
+
+static bool gen_grevi(DisasContext *ctx, arg_r2 *a, int shamt)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    if (shamt == (TARGET_LONG_BITS - 8)) {
+    /* rev8, byte swaps */
+    tcg_gen_bswap_tl(dest, src1);
+    } else {
+    TCGv src2 = tcg_temp_new();
+    tcg_gen_movi_tl(src2, shamt);
+    gen_helper_grev(dest, src1, src2);
+    tcg_temp_free(src2);
+    }
+
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+    tcg_gen_deposit_tl(ret, src1, src2,
+   TARGET_LONG_BITS / 2,
+   TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext8u_tl(t, src2);
+    tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+    tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext16s_tl(t, src2);
+    tcg_gen_deposit_tl(ret, src1, t, 16, 48);
+    tcg_temp_free(t);
+}
+
+static bool gen_shufi(DisasContext *ctx, arg_r2 *a, int shamt,
+   void(*func)(TCGv, TCGv, TCGv))
+{
+    if (shamt >= TARGET_LONG_BITS / 2) {
+    return false;
+    }
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = tcg_temp_new();
+
+    tcg_gen_movi_tl(src2, shamt);
+    (*func)(dest, src1, src2);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free(src2);
+    return true;
+}


All of the gen functions belong in insn_trans/trans_rvb.c.inc.

OK. I'll move them to insn_trans/trans_rvb.c.inc.



r~

Re: [PATCH v2 1/2] virtio-gpu: splitting one extended mode guest fb into n-scanouts

[Dongwon Kim]

I double-checked the patch and also tried to build with --disable-opengl
but couldn't find any issue. Can you please give me some hint? Like
build errors you saw. What are changed by the patch are pretty much
limited to virtio-gpu blob case and just one change in common area is
egl_fb_blit function but the function interface stays same and there are
no variables enabled only with certain define.

Is there any chance that the build system was building it with the
previous patch, "ui/gtk-egl: un-tab and re-tab should destroy egl
surface and context" still applied?

Thanks!
DW

On Tue, Nov 02, 2021 at 02:51:54PM +0100, Gerd Hoffmann wrote:
> On Mon, Jul 26, 2021 at 02:59:49PM -0700, Dongwon Kim wrote:
> > When guest is running Linux/X11 with extended multiple displays mode 
> > enabled,
> > the guest shares one scanout resource each time containing whole surface
> > rather than sharing individual display output separately. This extended 
> > frame
> > is properly splited and rendered on the corresponding scanout surfaces but
> > not in case of blob-resource (zero copy).
> > 
> > This code change lets the qemu split this one large surface data into 
> > multiple
> > in case of blob-resource as well so that each sub frame then can be blitted
> > properly to each scanout.
> 
> Fails windows test build too.
> 
> take care,
>   Gerd
> 

Re: [PATCH] ppc/pegasos2: Suppress warning when qtest enabled

[David Gibson]

On Mon, Nov 01, 2021 at 04:08:31PM +0100, BALATON Zoltan wrote:
> Suggested-by: Peter Maydell 
> Signed-off-by: BALATON Zoltan 

Applied to ppc-for-6.2, thanks.

> ---
>  hw/ppc/pegasos2.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
> index e427ac2fe0..298e6b93e2 100644
> --- a/hw/ppc/pegasos2.c
> +++ b/hw/ppc/pegasos2.c
> @@ -23,6 +23,7 @@
>  #include "hw/qdev-properties.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> +#include "sysemu/qtest.h"
>  #include "hw/boards.h"
>  #include "hw/loader.h"
>  #include "hw/fw-path-provider.h"
> @@ -199,7 +200,7 @@ static void pegasos2_init(MachineState *machine)
>  if (!pm->vof) {
>  warn_report("Option -kernel may be ineffective with -bios.");
>  }
> -} else if (pm->vof) {
> +} else if (pm->vof && !qtest_enabled()) {
>  warn_report("Using Virtual OpenFirmware but no -kernel option.");
>  }
>  

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Description: PGP signature

Re: [PATCH] ppc/pnv: Fix check on block device before updating drive contents

[David Gibson]

On Tue, Nov 02, 2021 at 05:29:05PM +0100, Cédric Le Goater wrote:
> Test is wrong and the backend can never updated. It could have led to
> a QEMU crash but since the firmware deactivates flash access if a valid
> layout is not detected, it went unnoticed.
> 
> Reported-by: Coverity CID 1465223
> Fixes: 35dde5766211 ("ppc/pnv: Add a PNOR model")
> Signed-off-by: Cédric Le Goater 

Applied to ppc-for-6.2, thanks.

> ---
>  hw/ppc/pnv_pnor.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c
> index 5ef1cf2afbe1..83ea28df 100644
> --- a/hw/ppc/pnv_pnor.c
> +++ b/hw/ppc/pnv_pnor.c
> @@ -36,7 +36,7 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int 
> size)
>  int offset_end;
>  int ret;
>  
> -if (s->blk) {
> +if (!s->blk || !blk_is_writable(s->blk)) {
>  return;
>  }
>  

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Description: PGP signature

Re: [PULL 00/60] accel/tcg patch queue

[Warner Losh]

On Tue, Nov 2, 2021 at 5:35 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 11/2/21 7:27 PM, Warner Losh wrote:
> > This breaks bsd-user building. That’s OK, imho, for two reasons: First
> it only runs ‘hello world’. Second, I’ve updated my patch train which will
> fix this (message-id 20211019164447.16359-1-...@bsdimp.com).
> >
> > If there’s urgency to this, I can pull patch 1 out and submit it.
>
> Dangit.  I shouldn't have broken the build, even with signals still
> disabled in bsd-user.
>   I let my guard down because the cirrus bsd build has gone wonky, and the
> shared machine
> I'm doing other cross-testing on has got some temporary resource conflict.
>
> Let's fix the build asap.
>

The fix is simple. If you review the first patch 01/30 of my series, I can
create a pull request with that one change (or you can, I'm not
territorial, so long as we know who is doing it).

Warner

Re: [PATCH v2 01/30] bsd-user: Add stubs for new signal routines

[Warner Losh]

On Tue, Nov 2, 2021 at 5:37 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 11/2/21 6:52 PM, Warner Losh wrote:
> > Until the signal support is merged from the bsd-user fork, we need stubs
> > for cpu_loop_exit_sigsegv and cpu_loop_exit_sigbus to link. These call
> > abort after logging a message. Since singals aren't supported here
> > yet, this is sufficient.
> >
> > Signed-off-by: Warner Losh 
> > ---
> >   bsd-user/signal.c | 21 +
> >   1 file changed, 21 insertions(+)
> >
> > diff --git a/bsd-user/signal.c b/bsd-user/signal.c
> > index 0c1093deb1..05b277c642 100644
> > --- a/bsd-user/signal.c
> > +++ b/bsd-user/signal.c
> > @@ -20,6 +20,11 @@
> >   #include "qemu/osdep.h"
> >   #include "qemu.h"
> >
> > +/*
> > + * Stubbed out routines until we merge signal support from bsd-user
> > + * fork.
> > + */
> > +
> >   /*
> >* Queue a signal so that it will be send to the virtual CPU as soon as
> >* possible.
> > @@ -36,3 +41,19 @@ void signal_init(void)
> >   void process_pending_signals(CPUArchState *cpu_env)
> >   {
> >   }
> > +
> > +void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
> > +   MMUAccessType access_type, bool maperr,
> uintptr_t ra)
> > +{
> > +qemu_log_mask(LOG_UNIMP, "No signal support for SIGSEGV\n");
> > +/* unreachable */
> > +abort();
> > +}
> > +
> > +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
> > +  MMUAccessType access_type, uintptr_t ra)
> > +{
> > +qemu_log_mask(LOG_UNIMP, "No signal support for SIGBUS\n");
> > +/* unreachable */
> > +abort();
> > +}
> >
>
> I'm going to apply this directly to master as a build fix.
> Sorry about that.
>

Works for me. I just cherry-picked and the build works with it.

Warner

Re: [PATCH v2 01/30] bsd-user: Add stubs for new signal routines

[Richard Henderson]

On 11/2/21 6:52 PM, Warner Losh wrote:

Until the signal support is merged from the bsd-user fork, we need stubs
for cpu_loop_exit_sigsegv and cpu_loop_exit_sigbus to link. These call
abort after logging a message. Since singals aren't supported here
yet, this is sufficient.

Signed-off-by: Warner Losh 
---
  bsd-user/signal.c | 21 +
  1 file changed, 21 insertions(+)

diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index 0c1093deb1..05b277c642 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -20,6 +20,11 @@
  #include "qemu/osdep.h"
  #include "qemu.h"
  
+/*

+ * Stubbed out routines until we merge signal support from bsd-user
+ * fork.
+ */
+
  /*
   * Queue a signal so that it will be send to the virtual CPU as soon as
   * possible.
@@ -36,3 +41,19 @@ void signal_init(void)
  void process_pending_signals(CPUArchState *cpu_env)
  {
  }
+
+void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+   MMUAccessType access_type, bool maperr, uintptr_t 
ra)
+{
+qemu_log_mask(LOG_UNIMP, "No signal support for SIGSEGV\n");
+/* unreachable */
+abort();
+}
+
+void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
+  MMUAccessType access_type, uintptr_t ra)
+{
+qemu_log_mask(LOG_UNIMP, "No signal support for SIGBUS\n");
+/* unreachable */
+abort();
+}



I'm going to apply this directly to master as a build fix.
Sorry about that.


r~

Re: [PULL 00/60] accel/tcg patch queue

[Richard Henderson]

On 11/2/21 7:27 PM, Warner Losh wrote:

This breaks bsd-user building. That’s OK, imho, for two reasons: First it only 
runs ‘hello world’. Second, I’ve updated my patch train which will fix this 
(message-id 20211019164447.16359-1-...@bsdimp.com).

If there’s urgency to this, I can pull patch 1 out and submit it.


Dangit.  I shouldn't have broken the build, even with signals still disabled in bsd-user. 
 I let my guard down because the cirrus bsd build has gone wonky, and the shared machine 
I'm doing other cross-testing on has got some temporary resource conflict.


Let's fix the build asap.


r~

[PATCH 3/4] ui/gtk-egl: guest fb texture needs to be regenerated when reinitializing egl

[Dongwon Kim]

If guest fb is backed by dmabuf (blob-resource), the texture bound to the
old context needs to be recreated in case the egl is re-initialized (e.g.
new window for vc is created in case of detaching/reattaching of the tab)

v2: call egl_dmabuf_release_texutre instead of putting 0 to dmabuf->texture
(Vivek Kasireddy)

Cc: Gerd Hoffmann 
Signed-off-by: Dongwon Kim 
---
 ui/gtk-egl.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index 7c9629d6cc..8c55ed18fb 100644
--- a/ui/gtk-egl.c
+++ b/ui/gtk-egl.c
@@ -142,6 +142,10 @@ void gd_egl_refresh(DisplayChangeListener *dcl)
 surface_gl_destroy_texture(vc->gfx.gls, vc->gfx.ds);
 surface_gl_create_texture(vc->gfx.gls, vc->gfx.ds);
 }
+if (vc->gfx.guest_fb.dmabuf) {
+egl_dmabuf_release_texture(vc->gfx.guest_fb.dmabuf);
+gd_egl_scanout_dmabuf(dcl, vc->gfx.guest_fb.dmabuf);
+}
 }
 
 graphic_hw_update(dcl->con);
-- 
2.30.2

Re: [PULL 00/60] accel/tcg patch queue

[Warner Losh]

This breaks bsd-user building. That’s OK, imho, for two reasons: First it only 
runs ‘hello world’. Second, I’ve updated my patch train which will fix this 
(message-id 20211019164447.16359-1-...@bsdimp.com).

If there’s urgency to this, I can pull patch 1 out and submit it.

Warner

> On Nov 2, 2021, at 1:11 PM, Richard Henderson  
> wrote:
> 
> On 11/2/21 7:06 AM, Richard Henderson wrote:
>> The following changes since commit dd61b91c080cdfba1360a5ea1e4693fffb3445b0:
>>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29' 
>> into staging (2021-10-29 19:42:36 -0700)
>> are available in the Git repository at:
>>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211102
>> for you to fetch changes up to 742f07628c0a0bd847b47ee0a0b20c44531e0ba5:
>>   linux-user: Handle BUS_ADRALN in host_signal_handler (2021-11-02 07:00:52 
>> -0400)
>> 
>> - Split out host signal handing from accel/tcg/user-exec.c
>>   to linux-user/host/arch/host-signal.h
>> - Replace TCGCPUOps.tlb_fill with TCGCPUOps.record_sigsegv for user-only
>> - Add TCGCPUOps.record_sigbus for user-only
>> - Remove a lot of target-specific cpu_loop handling for signals,
>>   now accomplished with generic code.
>> 
>> Richard Henderson (60):
>>   accel/tcg: Split out adjust_signal_pc
>>   accel/tcg: Move clear_helper_retaddr to cpu loop
>>   accel/tcg: Split out handle_sigsegv_accerr_write
>>   accel/tcg: Fold cpu_exit_tb_from_sighandler into caller
>>   configure: Merge riscv32 and riscv64 host architectures
>>   linux-user: Reorg handling for SIGSEGV
>>   linux-user/host/x86: Populate host_signal.h
>>   linux-user/host/ppc: Populate host_signal.h
>>   linux-user/host/alpha: Populate host_signal.h
>>   linux-user/host/sparc: Populate host_signal.h
>>   linux-user/host/arm: Populate host_signal.h
>>   linux-user/host/aarch64: Populate host_signal.h
>>   linux-user/host/s390: Populate host_signal.h
>>   linux-user/host/mips: Populate host_signal.h
>>   linux-user/host/riscv: Populate host_signal.h
>>   target/arm: Fixup comment re handle_cpu_signal
>>   linux-user/host/riscv: Improve host_signal_write
>>   linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER
>>   hw/core: Add TCGCPUOps.record_sigsegv
>>   linux-user: Add cpu_loop_exit_sigsegv
>>   target/alpha: Implement alpha_cpu_record_sigsegv
>>   target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup
>>   target/arm: Implement arm_cpu_record_sigsegv
>>   target/cris: Make cris_cpu_tlb_fill sysemu only
>>   target/hexagon: Remove hexagon_cpu_tlb_fill
>>   target/hppa: Make hppa_cpu_tlb_fill sysemu only
>>   target/i386: Implement x86_cpu_record_sigsegv
>>   target/m68k: Make m68k_cpu_tlb_fill sysemu only
>>   target/microblaze: Make mb_cpu_tlb_fill sysemu only
>>   target/mips: Make mips_cpu_tlb_fill sysemu only
>>   target/nios2: Implement nios2_cpu_record_sigsegv
>>   linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE
>>   target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
>>   target/ppc: Implement ppc_cpu_record_sigsegv
>>   target/riscv: Make riscv_cpu_tlb_fill sysemu only
>>   target/s390x: Use probe_access_flags in s390_probe_access
>>   target/s390x: Implement s390_cpu_record_sigsegv
>>   target/sh4: Make sh4_cpu_tlb_fill sysemu only
>>   target/sparc: Make sparc_cpu_tlb_fill sysemu only
>>   target/xtensa: Make xtensa_cpu_tlb_fill sysemu only
>>   accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
>>   hw/core: Add TCGCPUOps.record_sigbus
>>   linux-user: Add cpu_loop_exit_sigbus
>>   target/alpha: Implement alpha_cpu_record_sigbus
>>   target/arm: Implement arm_cpu_record_sigbus
>>   linux-user/hppa: Remove EXCP_UNALIGN handling
>>   target/microblaze: Do not set MO_ALIGN for user-only
>>   target/ppc: Move SPR_DSISR setting to powerpc_excp
>>   target/ppc: Set fault address in ppc_cpu_do_unaligned_access
>>   target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
>>   linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling
>>   target/s390x: Implement s390x_cpu_record_sigbus
>>   target/sh4: Set fault address in superh_cpu_do_unaligned_access
>>   target/sparc: Remove DEBUG_UNALIGNED
>>   target/sparc: Split out build_sfsr
>>   target/

[PATCH v2 27/30] bsd-user/i386/target_arch_signal.h: Remove target_sigcontext

[Warner Losh]

In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.

Signed-off-by: Warner Losh 
---
 bsd-user/i386/target_arch_signal.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/bsd-user/i386/target_arch_signal.h 
b/bsd-user/i386/target_arch_signal.h
index a90750d602..e262667bda 100644
--- a/bsd-user/i386/target_arch_signal.h
+++ b/bsd-user/i386/target_arch_signal.h
@@ -27,10 +27,6 @@
 #define TARGET_MINSIGSTKSZ  (512 * 4)   /* min sig stack size */
 #define TARGET_SIGSTKSZ (MINSIGSTKSZ + 32768)   /* recommended size */
 
-struct target_sigcontext {
-/* to be added */
-};
-
 typedef struct target_mcontext {
 } target_mcontext_t;
 
-- 
2.33.0

Re: [PULL 00/41] MIPS patches for 2021-11-02

[Richard Henderson]

On 11/2/21 9:41 AM, Philippe Mathieu-Daudé wrote:

The following changes since commit 844d6dfc3e48a8d404b03ea815868fd01c6f7317:

   Merge remote-tracking branch 
'remotes/alex.williamson/tags/vfio-update-20211101.0' into staging (2021-11-02 
07:25:59 -0400)

are available in the Git repository at:

   https://github.com/philmd/qemu.git tags/mips-20211102

for you to fetch changes up to 6f08c9c5316a80a049d4861eaac5844466ba3eba:

   Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" 
(2021-11-02 14:35:22 +0100)


MIPS patches queue

- Fine-grained MAINTAINERS sections
- Fix MSA MADDV.B / MSUBV.B opcodes
- Convert MSA opcodes to decodetree
- Correct Loongson-3A4000 MSAIR register
- Do not accept ELF nanoMIPS binaries on linux-user
- Use ISA instead of PCI interrupts in VT82C686 PCI device



BALATON Zoltan (4):
   usb/uhci: Misc clean up
   usb/uhci: Disallow user creating a vt82c686-uhci-pci device
   usb/uhci: Replace pci_set_irq with qemu_set_irq
   hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts

Philippe Mathieu-Daudé (37):
   MAINTAINERS: Add MIPS general architecture support entry
   MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware
   MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware
   target/mips: Fix MSA MADDV.B opcode
   target/mips: Fix MSA MSUBV.B opcode
   target/mips: Adjust style in msa_translate_init()
   target/mips: Use dup_const() to simplify
   target/mips: Have check_msa_access() return a boolean
   target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
   target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
   target/mips: Convert MSA LDI opcode to decodetree
   target/mips: Convert MSA I5 instruction format to decodetree
   target/mips: Convert MSA BIT instruction format to decodetree
   target/mips: Convert MSA SHF opcode to decodetree
   target/mips: Convert MSA I8 instruction format to decodetree
   target/mips: Convert MSA load/store instruction format to decodetree
   target/mips: Convert MSA 2RF instruction format to decodetree
   target/mips: Convert MSA FILL opcode to decodetree
   target/mips: Convert MSA 2R instruction format to decodetree
   target/mips: Convert MSA VEC instruction format to decodetree
   target/mips: Convert MSA 3RF instruction format to decodetree
 (DF_HALF)
   target/mips: Convert MSA 3RF instruction format to decodetree
 (DF_WORD)
   target/mips: Convert MSA 3R instruction format to decodetree (part
 1/4)
   target/mips: Convert MSA 3R instruction format to decodetree (part
 2/4)
   target/mips: Convert MSA 3R instruction format to decodetree (part
 3/4)
   target/mips: Convert MSA 3R instruction format to decodetree (part
 4/4)
   target/mips: Convert MSA ELM instruction format to decodetree
   target/mips: Convert MSA COPY_U opcode to decodetree
   target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
   target/mips: Convert MSA MOVE.V opcode to decodetree
   target/mips: Convert CFCMSA opcode to decodetree
   target/mips: Convert CTCMSA opcode to decodetree
   target/mips: Remove generic MSA opcode
   target/mips: Remove one MSA unnecessary decodetree overlap group
   target/mips: Fix Loongson-3A4000 MSAIR config register
   target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
   Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"

  hw/usb/hcd-uhci.h   |3 +-
  target/mips/tcg/msa.decode  |  243 ++-
  hw/usb/hcd-uhci.c   |   14 +-
  hw/usb/vt82c686-uhci-pci.c  |   15 +
  linux-user/elfload.c|2 -
  target/mips/tcg/msa_helper.c|   64 +-
  target/mips/tcg/msa_translate.c | 2743 +++
  target/mips/cpu-defs.c.inc  |2 +-
  MAINTAINERS |   37 +-
  9 files changed, 957 insertions(+), 2166 deletions(-)


Applied, thanks.

r~

[PULL 2/4] hw/core/machine: Add the missing delimiter in cpu_slot_to_string()

[Laurent Vivier]

From: Yanan Wang 

The expected output string from cpu_slot_to_string() ought to be
like "socket-id: *, die-id: *, core-id: *, thread-id: *", so add
the missing ", " before "die-id". This affects the readability
of the error message.

Fixes: 176d2cda0d ("i386/cpu: Consolidate die-id validity in smp context")
Signed-off-by: Yanan Wang 
Reviewed-by: Laurent Vivier 
Message-Id: <20211008075040.18028-1-wangyana...@huawei.com>
Signed-off-by: Laurent Vivier 
---
 hw/core/machine.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index b8d95eec32d4..0a23ae310606 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1157,6 +1157,9 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
 }
 if (cpu->props.has_die_id) {
+if (s->len) {
+g_string_append_printf(s, ", ");
+}
 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
 }
 if (cpu->props.has_core_id) {
-- 
2.31.1

[PATCH v2 26/30] bsd-user: add arm target build

[Warner Losh]

CC: Paolo Bonzini 
Signed-off-by: Warner Losh 
Acked-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 configs/targets/arm-bsd-user.mak | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 configs/targets/arm-bsd-user.mak

diff --git a/configs/targets/arm-bsd-user.mak b/configs/targets/arm-bsd-user.mak
new file mode 100644
index 00..90b6533195
--- /dev/null
+++ b/configs/targets/arm-bsd-user.mak
@@ -0,0 +1,2 @@
+TARGET_ARCH=arm
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml 
gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml 
gdb-xml/arm-m-profile.xml
-- 
2.33.0

[PULL 3/4] MAINTAINERS: Split HPPA TCG vs HPPA machines/hardware

[Laurent Vivier]

From: Philippe Mathieu-Daudé 

Hardware emulated models don't belong to the TCG MAINTAINERS
section. Move them to the 'HP-PARISC Machines' section.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Helge Deller 
Message-Id: <20211004083835.3802961-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier 
---
 MAINTAINERS | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 894dc4310526..6f2b20078032 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -205,10 +205,7 @@ HPPA (PA-RISC) TCG CPUs
 M: Richard Henderson 
 S: Maintained
 F: target/hppa/
-F: hw/hppa/
 F: disas/hppa.c
-F: hw/net/*i82596*
-F: include/hw/net/lasi_82596.h
 
 M68K TCG CPUs
 M: Laurent Vivier 
@@ -1099,6 +1096,8 @@ R: Helge Deller 
 S: Odd Fixes
 F: configs/devices/hppa-softmmu/default.mak
 F: hw/hppa/
+F: hw/net/*i82596*
+F: include/hw/net/lasi_82596.h
 F: pc-bios/hppa-firmware.img
 
 M68K Machines
-- 
2.31.1

[PATCH v2 24/30] bsd-user/arm/target_arch_signal.h: arm set_mcontext

[Warner Losh]

Move the machine context to the CPU state.

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_signal.h | 75 +++
 1 file changed, 75 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index b42d08402f..3b2f56ffab 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -179,4 +179,79 @@ static inline abi_long get_mcontext(CPUARMState *env, 
target_mcontext_t *mcp,
 return err;
 }
 
+/* Compare to arm/arm/exec_machdep.c set_mcontext() */
+static inline abi_long set_mcontext(CPUARMState *env, target_mcontext_t *mcp,
+int srflag)
+{
+int err = 0;
+const uint32_t *gr = mcp->__gregs;
+uint32_t cpsr, ccpsr = cpsr_read(env);
+uint32_t fpscr;
+
+cpsr = tswap32(gr[TARGET_REG_CPSR]);
+/*
+ * Only allow certain bits to change, reject attempted changes to non-user
+ * bits. In addition, make sure we're headed for user mode and none of the
+ * interrupt bits are set.
+ */
+if ((ccpsr & ~CPSR_USER) != (cpsr & ~CPSR_USER)) {
+return -TARGET_EINVAL;
+}
+if ((cpsr & CPSR_M) != ARM_CPU_MODE_USR ||
+(cpsr & (CPSR_I | CPSR_F)) != 0) {
+return -TARGET_EINVAL;
+}
+
+/*
+ * Make sure that we either have no vfp, or it's the correct size.
+ * FreeBSD just ignores it, though, so maybe we'll need to adjust
+ * things below instead.
+ */
+if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_size != 
sizeof(target_mcontext_vfp_t)) {
+return -TARGET_EINVAL;
+}
+/*
+ * Make sure T mode matches the PC's notion of thumb mode, although
+ * FreeBSD lets the processor sort this out, so we may need remove
+ * this check, or generate a signal...
+ */
+if (!!(tswap32(gr[TARGET_REG_PC]) & 1) != !!(cpsr & CPSR_T)) {
+return -TARGET_EINVAL;
+}
+
+env->regs[0] = tswap32(gr[TARGET_REG_R0]);
+env->regs[1] = tswap32(gr[TARGET_REG_R1]);
+env->regs[2] = tswap32(gr[TARGET_REG_R2]);
+env->regs[3] = tswap32(gr[TARGET_REG_R3]);
+env->regs[4] = tswap32(gr[TARGET_REG_R4]);
+env->regs[5] = tswap32(gr[TARGET_REG_R5]);
+env->regs[6] = tswap32(gr[TARGET_REG_R6]);
+env->regs[7] = tswap32(gr[TARGET_REG_R7]);
+env->regs[8] = tswap32(gr[TARGET_REG_R8]);
+env->regs[9] = tswap32(gr[TARGET_REG_R9]);
+env->regs[10] = tswap32(gr[TARGET_REG_R10]);
+env->regs[11] = tswap32(gr[TARGET_REG_R11]);
+env->regs[12] = tswap32(gr[TARGET_REG_R12]);
+
+env->regs[13] = tswap32(gr[TARGET_REG_SP]);
+env->regs[14] = tswap32(gr[TARGET_REG_LR]);
+env->regs[15] = tswap32(gr[TARGET_REG_PC]);
+if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_ptr != NULL) {
+/* see set_vfpcontext in sys/arm/arm/exec_machdep.c */
+target_mcontext_vfp_t *vfp = (target_mcontext_vfp_t *)mcp->mc_vfp_ptr;
+for (int i = 0; i < 32; i++) {
+*aa32_vfp_dreg(env, i) = tswap64(vfp->mcv_reg[i]);
+}
+fpscr =  tswap32(vfp->mcv_fpscr);
+vfp_set_fpscr(env, fpscr);
+/*
+ * linux-user sets fpexc, fpinst and fpinst2, but these aren't in
+ * FreeBSD's mcontext, what to do?
+ */
+}
+cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
+
+return err;
+}
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PULL 4/4] hw/input/lasips2: Fix typos in function names

[Laurent Vivier]

From: Philippe Mathieu-Daudé 

Artist is another device, this one is the Lasi PS/2.
Rename the functions accordingly.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Damien Hedde 
Message-Id: <20210920064048.2729397-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier 
---
 hw/input/lasips2.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index e7faf24058b4..68d741d34215 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -96,7 +96,7 @@ typedef enum {
 LASIPS2_STATUS_CLKSHD = 0x80,
 } lasips2_status_reg_t;
 
-static const char *artist_read_reg_name(uint64_t addr)
+static const char *lasips2_read_reg_name(uint64_t addr)
 {
 switch (addr & 0xc) {
 case REG_PS2_ID:
@@ -116,7 +116,7 @@ static const char *artist_read_reg_name(uint64_t addr)
 }
 }
 
-static const char *artist_write_reg_name(uint64_t addr)
+static const char *lasips2_write_reg_name(uint64_t addr)
 {
 switch (addr & 0x0c) {
 case REG_PS2_RESET:
@@ -145,7 +145,7 @@ static void lasips2_reg_write(void *opaque, hwaddr addr, 
uint64_t val,
 LASIPS2Port *port = opaque;
 
 trace_lasips2_reg_write(size, port->id, addr,
-artist_write_reg_name(addr), val);
+lasips2_write_reg_name(addr), val);
 
 switch (addr & 0xc) {
 case REG_PS2_CONTROL:
@@ -239,7 +239,7 @@ static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, 
unsigned size)
 break;
 }
 trace_lasips2_reg_read(size, port->id, addr,
-   artist_read_reg_name(addr), ret);
+   lasips2_read_reg_name(addr), ret);
 
 return ret;
 }
-- 
2.31.1

[PULL 0/4] Trivial branch for 6.2 patches

[Laurent Vivier]

The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:

  Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into 
staging (2021-10-30 11:31:41 -0700)

are available in the Git repository at:

  git://github.com/vivier/qemu.git tags/trivial-branch-for-6.2-pull-request

for you to fetch changes up to 5d2bd73588d14b5868129ace9c7912a777f06753:

  hw/input/lasips2: Fix typos in function names (2021-10-31 21:05:40 +0100)


Trivial patches branch pull request 20211101 v2



Markus Armbruster (1):
  monitor: Trim some trailing space from human-readable output

Philippe Mathieu-Daudé (2):
  MAINTAINERS: Split HPPA TCG vs HPPA machines/hardware
  hw/input/lasips2: Fix typos in function names

Yanan Wang (1):
  hw/core/machine: Add the missing delimiter in cpu_slot_to_string()

 MAINTAINERS| 5 ++---
 hw/core/machine.c  | 3 +++
 hw/input/lasips2.c | 8 
 monitor/hmp-cmds.c | 2 +-
 target/i386/cpu-dump.c | 4 ++--
 target/i386/cpu.c  | 2 +-
 target/ppc/cpu_init.c  | 2 +-
 target/s390x/cpu_models.c  | 4 ++--
 target/xtensa/mmu_helper.c | 2 +-
 9 files changed, 17 insertions(+), 15 deletions(-)

-- 
2.31.1

[PULL 1/4] monitor: Trim some trailing space from human-readable output

[Laurent Vivier]

From: Markus Armbruster 

I noticed -cpu help printing enough trailing spaces to make the output
at least 84 characters wide.  Looks ugly unless the terminal is wider.
Ugly or not, trailing spaces are stupid.

The culprit is this line in x86_cpu_list_entry():

qemu_printf("x86 %-20s  %-58s\n", name, desc);

This prints a string with minimum field left-justified right before a
newline.  Change it to

qemu_printf("x86 %-20s  %s\n", name, desc);

which avoids the trailing spaces and is simpler to boot.

A search for the pattern with "git-grep -E '%-[0-9]+s\\n'" found a few
more instances.  Change them similarly.

Signed-off-by: Markus Armbruster 
Reviewed-by: Richard Henderson 
Acked-by: Greg Kurz 
Reviewed-by: Philippe Mathieu-Daudé 
Acked-by: Max Filippov 
Message-Id: <20211009152401.2982862-1-arm...@redhat.com>
Signed-off-by: Laurent Vivier 
---
 monitor/hmp-cmds.c | 2 +-
 target/i386/cpu-dump.c | 4 ++--
 target/i386/cpu.c  | 2 +-
 target/ppc/cpu_init.c  | 2 +-
 target/s390x/cpu_models.c  | 4 ++--
 target/xtensa/mmu_helper.c | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c
index bcaa41350e9a..9e45a138a505 100644
--- a/monitor/hmp-cmds.c
+++ b/monitor/hmp-cmds.c
@@ -1945,7 +1945,7 @@ void hmp_rocker_ports(Monitor *mon, const QDict *qdict)
 monitor_printf(mon, "  port  linkduplex neg?\n");
 
 for (port = list; port; port = port->next) {
-monitor_printf(mon, "%10s  %-4s   %-3s  %2s  %-3s\n",
+monitor_printf(mon, "%10s  %-4s   %-3s  %2s  %s\n",
port->value->name,
port->value->enabled ? port->value->link_up ?
"up" : "down" : "!ena",
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
index 02b635a52cff..08ac957e99cf 100644
--- a/target/i386/cpu-dump.c
+++ b/target/i386/cpu-dump.c
@@ -464,13 +464,13 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
 #ifdef TARGET_X86_64
 if (env->hflags & HF_CS64_MASK) {
-qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
+qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%s\n",
  env->cc_src, env->cc_dst,
  cc_op_name);
 } else
 #endif
 {
-qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
+qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%s\n",
  (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
  cc_op_name);
 }
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 598d451dcf04..c5744ce08cf9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4878,7 +4878,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer 
user_data)
 desc = g_strdup_printf("%s", model_id);
 }
 
-qemu_printf("x86 %-20s  %-58s\n", name, desc);
+qemu_printf("x86 %-20s  %s\n", name, desc);
 }
 
 /* list available CPU models and flags */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 65545ba9ca8d..ba384a592bc1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -8734,7 +8734,7 @@ void ppc_cpu_list(void)
 
 #ifdef CONFIG_KVM
 qemu_printf("\n");
-qemu_printf("PowerPC %-16s\n", "host");
+qemu_printf("PowerPC %s\n", "host");
 #endif
 }
 
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 4e4598cc774c..11e06cc51fab 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -398,14 +398,14 @@ void s390_cpu_list(void)
 for (feat = 0; feat < S390_FEAT_MAX; feat++) {
 const S390FeatDef *def = s390_feat_def(feat);
 
-qemu_printf("%-20s %-50s\n", def->name, def->desc);
+qemu_printf("%-20s %s\n", def->name, def->desc);
 }
 
 qemu_printf("\nRecognized feature groups:\n");
 for (group = 0; group < S390_FEAT_GROUP_MAX; group++) {
 const S390FeatGroupDef *def = s390_feat_group_def(group);
 
-qemu_printf("%-20s %-50s\n", def->name, def->desc);
+qemu_printf("%-20s %s\n", def->name, def->desc);
 }
 }
 
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index b01ff9399ae6..57e319a1af3a 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -1098,7 +1098,7 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb)
 qemu_printf("\tVaddr   Paddr   ASID  Attr RWX 
Cache\n"
 "\t--  --     --- 
---\n");
 }
-qemu_printf("\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %-7s\n",
+qemu_printf("\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %s\n",
 entry->vaddr,
 entry->paddr,
 entry->asid,
-- 
2.31.1

[PATCH v2 1/4] ui/gtk-egl: un-tab and re-tab should destroy egl surface and context

[Dongwon Kim]

An old esurface should be destroyed and set to be NULL when doing
un-tab and re-tab so that a new esurface an context can be created
for the window widget that those will be bound to.

v2: enabling opengl specific routines only when CONFIG_OPENGL is set

Cc: Gerd Hoffmann 
Signed-off-by: Dongwon Kim 
Signed-off-by: Khairul Anuar Romli 
---
 ui/gtk.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/ui/gtk.c b/ui/gtk.c
index b0564d80c1..8da673c18c 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -1242,6 +1242,16 @@ static gboolean gd_tab_window_close(GtkWidget *widget, 
GdkEvent *event,
 vc->tab_item, vc->label);
 gtk_widget_destroy(vc->window);
 vc->window = NULL;
+#if defined(CONFIG_OPENGL)
+if (vc->gfx.esurface) {
+eglDestroySurface(qemu_egl_display, vc->gfx.esurface);
+vc->gfx.esurface = NULL;
+}
+if (vc->gfx.ectx) {
+eglDestroyContext(qemu_egl_display, vc->gfx.ectx);
+vc->gfx.ectx = NULL;
+}
+#endif
 return TRUE;
 }
 
@@ -1271,6 +1281,16 @@ static void gd_menu_untabify(GtkMenuItem *item, void 
*opaque)
 if (!vc->window) {
 gtk_widget_set_sensitive(vc->menu_item, false);
 vc->window = gtk_window_new(GTK_WINDOW_TOPLEVEL);
+#if defined(CONFIG_OPENGL)
+if (vc->gfx.esurface) {
+eglDestroySurface(qemu_egl_display, vc->gfx.esurface);
+vc->gfx.esurface = NULL;
+}
+if (vc->gfx.esurface) {
+eglDestroyContext(qemu_egl_display, vc->gfx.ectx);
+vc->gfx.ectx = NULL;
+}
+#endif
 gd_widget_reparent(s->notebook, vc->window, vc->tab_item);
 
 g_signal_connect(vc->window, "delete-event",
-- 
2.30.2

[PATCH 4/4] ui/gtk: gd_draw_event returns FALSE when no cairo surface is bound

[Dongwon Kim]

gd_draw_event shouldn't try to repaint if surface does not exist
for the VC.

Cc: Gerd Hoffmann 
Signed-off-by: Dongwon Kim 
---
 ui/gtk.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/ui/gtk.c b/ui/gtk.c
index 8da673c18c..d2892ea6b4 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -778,6 +778,9 @@ static gboolean gd_draw_event(GtkWidget *widget, cairo_t 
*cr, void *opaque)
 if (!vc->gfx.ds) {
 return FALSE;
 }
+if (!vc->gfx.surface) {
+return FALSE;
+}
 
 vc->gfx.dcl.update_interval =
 gd_monitor_update_interval(vc->window ? vc->window : s->window);
-- 
2.30.2

[PATCH v2 22/30] bsd-user/arm/target_arch_signal.h: arm set_sigtramp_args

[Warner Losh]

Implement set_sigtramp_args to setup the arguments to the sigtramp
calls.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_signal.h | 47 +++
 1 file changed, 47 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index 4bdfcbb8d7..61440b51b4 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -82,4 +82,51 @@ struct target_sigframe {
 target_mcontext_vfp_t sf_vfp; /* actual saved VFP context */
 };
 
+/*
+ * Compare to arm/arm/machdep.c sendsig()
+ * Assumes that target stack frame memory is locked.
+ */
+static inline abi_long
+set_sigtramp_args(CPUARMState *env, int sig, struct target_sigframe *frame,
+abi_ulong frame_addr, struct target_sigaction *ka)
+{
+abi_ulong cpsr;
+
+/*
+ * Arguments to signal handler:
+ *  r0 = signal number
+ *  r1 = siginfo pointer
+ *  r2 = ucontext pointer
+ *  r5 = ucontext pointer
+ *  pc = signal handler pointer
+ *  sp = sigframe struct pointer
+ *  lr = sigtramp at base of user stack
+ */
+
+env->regs[0] = sig;
+env->regs[1] = frame_addr +
+offsetof(struct target_sigframe, sf_si);
+env->regs[2] = frame_addr +
+offsetof(struct target_sigframe, sf_uc);
+
+/* the trampoline uses r5 as the uc address */
+env->regs[5] = frame_addr +
+offsetof(struct target_sigframe, sf_uc);
+env->regs[TARGET_REG_PC] = ka->_sa_handler & ~1;
+env->regs[TARGET_REG_SP] = frame_addr;
+env->regs[TARGET_REG_LR] = TARGET_PS_STRINGS - TARGET_SZSIGCODE;
+/*
+ * Low bit indicates whether or not we're entering thumb mode.
+ */
+cpsr = cpsr_read(env);
+if (ka->_sa_handler & 1) {
+cpsr |= CPSR_T;
+} else {
+cpsr &= ~CPSR_T;
+}
+cpsr_write(env, cpsr, CPSR_T, CPSRWriteByInstr);
+
+return 0;
+}
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 18/30] bsd-user/freebsd: Create common target_os_ucontext.h file

[Warner Losh]

FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from sys/_ucontext.h with the comments about layout removed
because we don't support ancient FreeBSD binaries.

Signed-off-by: Warner Losh 
---
 bsd-user/freebsd/target_os_signal.h   |  3 ---
 bsd-user/freebsd/target_os_ucontext.h | 26 ++
 2 files changed, 26 insertions(+), 3 deletions(-)
 create mode 100644 bsd-user/freebsd/target_os_ucontext.h

diff --git a/bsd-user/freebsd/target_os_signal.h 
b/bsd-user/freebsd/target_os_signal.h
index 1a4c5faf19..3ed454e086 100644
--- a/bsd-user/freebsd/target_os_signal.h
+++ b/bsd-user/freebsd/target_os_signal.h
@@ -1,9 +1,6 @@
 #ifndef _TARGET_OS_SIGNAL_H_
 #define _TARGET_OS_SIGNAL_H_
 
-/* FreeBSD's sys/ucontext.h defines this */
-#define TARGET_MC_GET_CLEAR_RET 0x0001
-
 #include "target_os_siginfo.h"
 #include "target_arch_signal.h"
 
diff --git a/bsd-user/freebsd/target_os_ucontext.h 
b/bsd-user/freebsd/target_os_ucontext.h
new file mode 100644
index 00..20b8a9188e
--- /dev/null
+++ b/bsd-user/freebsd/target_os_ucontext.h
@@ -0,0 +1,26 @@
+/*
+ * FreeBSD has a common ucontext definition for all architectures.
+ *
+ * Copyright 2021 Warner Losh 
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ */
+
+/*
+ * Defines the common bits for all of FreeBSD's architectures. Has to be
+ * included AFTER the MD target_mcontext_t is defined, however, so can't
+ * be in the grab-bag that is target_os_signal.h.
+ */
+
+/* See FreeBSD's sys/ucontext.h */
+#define TARGET_MC_GET_CLEAR_RET 0x0001
+
+/* FreeBSD's sys/_ucontext.h structures */
+typedef struct target_ucontext {
+target_sigset_t uc_sigmask;
+target_mcontext_t   uc_mcontext;
+abi_ulong   uc_link;
+target_stack_t  uc_stack;
+int32_t uc_flags;
+int32_t __spare__[4];
+} target_ucontext_t;
-- 
2.33.0

[PATCH v2 30/30] bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h

[Warner Losh]

Signed-off-by: Warner Losh 
---
 bsd-user/x86_64/target_arch_signal.h | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/bsd-user/x86_64/target_arch_signal.h 
b/bsd-user/x86_64/target_arch_signal.h
index 55f742b0a8..e84aff948c 100644
--- a/bsd-user/x86_64/target_arch_signal.h
+++ b/bsd-user/x86_64/target_arch_signal.h
@@ -30,14 +30,7 @@
 typedef struct target_mcontext {
 } target_mcontext_t;
 
-typedef struct target_ucontext {
-target_sigset_t   uc_sigmask;
-target_mcontext_t uc_mcontext;
-abi_ulong uc_link;
-target_stack_tuc_stack;
-int32_t   uc_flags;
-int32_t __spare__[4];
-} target_ucontext_t;
+#include "target_os_ucontext.h"
 
 struct target_sigframe {
 abi_ulong   sf_signum;
-- 
2.33.0

[PATCH v2 28/30] bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontext

[Warner Losh]

In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.

Signed-off-by: Warner Losh 
---
 bsd-user/x86_64/target_arch_signal.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/bsd-user/x86_64/target_arch_signal.h 
b/bsd-user/x86_64/target_arch_signal.h
index 4bb753b08b..55f742b0a8 100644
--- a/bsd-user/x86_64/target_arch_signal.h
+++ b/bsd-user/x86_64/target_arch_signal.h
@@ -27,10 +27,6 @@
 #define TARGET_MINSIGSTKSZ  (512 * 4)   /* min sig stack size */
 #define TARGET_SIGSTKSZ (MINSIGSTKSZ + 32768)   /* recommended size */
 
-struct target_sigcontext {
-/* to be added */
-};
-
 typedef struct target_mcontext {
 } target_mcontext_t;
 
-- 
2.33.0

[PATCH v2 29/30] bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.h

[Warner Losh]

Signed-off-by: Warner Losh 
---
 bsd-user/i386/target_arch_signal.h | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/bsd-user/i386/target_arch_signal.h 
b/bsd-user/i386/target_arch_signal.h
index e262667bda..bf7263c4f8 100644
--- a/bsd-user/i386/target_arch_signal.h
+++ b/bsd-user/i386/target_arch_signal.h
@@ -30,14 +30,7 @@
 typedef struct target_mcontext {
 } target_mcontext_t;
 
-typedef struct target_ucontext {
-target_sigset_t   uc_sigmask;
-target_mcontext_t uc_mcontext;
-abi_ulong uc_link;
-target_stack_tuc_stack;
-int32_t   uc_flags;
-int32_t __spare__[4];
-} target_ucontext_t;
+#include "target_os_ucontext.h"
 
 struct target_sigframe {
 abi_ulong   sf_signum;
-- 
2.33.0

[PATCH v2 25/30] bsd-user/arm/target_arch_signal.h: arm get_ucontext_sigreturn

[Warner Losh]

Update ucontext to implement sigreturn.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_signal.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index 3b2f56ffab..3db76c9201 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -254,4 +254,13 @@ static inline abi_long set_mcontext(CPUARMState *env, 
target_mcontext_t *mcp,
 return err;
 }
 
+/* Compare to arm/arm/machdep.c sys_sigreturn() */
+static inline abi_long get_ucontext_sigreturn(CPUARMState *env,
+abi_ulong target_sf, abi_ulong *target_uc)
+{
+*target_uc = target_sf;
+
+return 0;
+}
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 11/30] bsd-user/arm/target_arch_reg.h: Implement core dump register copying

[Warner Losh]

Implement the register copying routines to extract registers from the
cpu for core dump generation.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_reg.h | 60 ++
 1 file changed, 60 insertions(+)
 create mode 100644 bsd-user/arm/target_arch_reg.h

diff --git a/bsd-user/arm/target_arch_reg.h b/bsd-user/arm/target_arch_reg.h
new file mode 100644
index 00..ef5ed5154f
--- /dev/null
+++ b/bsd-user/arm/target_arch_reg.h
@@ -0,0 +1,60 @@
+/*
+ *  FreeBSD arm register structures
+ *
+ *  Copyright (c) 2015 Stacey Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+
+#ifndef _TARGET_ARCH_REG_H_
+#define _TARGET_ARCH_REG_H_
+
+/* See sys/arm/include/reg.h */
+typedef struct target_reg {
+uint32_tr[13];
+uint32_tr_sp;
+uint32_tr_lr;
+uint32_tr_pc;
+uint32_tr_cpsr;
+} target_reg_t;
+
+typedef struct target_fp_reg {
+uint32_tfp_exponent;
+uint32_tfp_mantissa_hi;
+u_int32_t   fp_mantissa_lo;
+} target_fp_reg_t;
+
+typedef struct target_fpreg {
+uint32_tfpr_fpsr;
+target_fp_reg_t fpr[8];
+} target_fpreg_t;
+
+#define tswapreg(ptr)   tswapal(ptr)
+
+static inline void target_copy_regs(target_reg_t *regs, const CPUARMState *env)
+{
+int i;
+
+for (i = 0; i < 13; i++) {
+regs->r[i] = tswapreg(env->regs[i + 1]);
+}
+regs->r_sp = tswapreg(env->regs[13]);
+regs->r_lr = tswapreg(env->regs[14]);
+regs->r_pc = tswapreg(env->regs[15]);
+regs->r_cpsr = tswapreg(cpsr_read((CPUARMState *)env));
+}
+
+#undef tswapreg
+
+#endif /* !_TARGET_ARCH_REG_H_ */
-- 
2.33.0

[PATCH v2 21/30] bsd-user/arm/target_arch_signal.h: arm user context and trapframe for signals

[Warner Losh]

Arm specific user context structures for signal handling and the closely
related trap frame.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_signal.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index 3aaced474b..4bdfcbb8d7 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -74,4 +74,12 @@ typedef struct target_mcontext {
 abi_int mc_spare[33];
 } target_mcontext_t;
 
+#include "target_os_ucontext.h"
+
+struct target_sigframe {
+target_siginfo_tsf_si;  /* saved siginfo */
+target_ucontext_t   sf_uc;  /* saved ucontext */
+target_mcontext_vfp_t sf_vfp; /* actual saved VFP context */
+};
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 23/30] bsd-user/arm/target_arch_signal.h: arm get_mcontext

[Warner Losh]

Get the machine context from the CPU state.

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_signal.h | 50 +++
 1 file changed, 50 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index 61440b51b4..b42d08402f 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -129,4 +129,54 @@ set_sigtramp_args(CPUARMState *env, int sig, struct 
target_sigframe *frame,
 return 0;
 }
 
+/*
+ * Compare to arm/arm/machdep.c get_mcontext()
+ * Assumes that the memory is locked if mcp points to user memory.
+ */
+static inline abi_long get_mcontext(CPUARMState *env, target_mcontext_t *mcp,
+int flags)
+{
+int err = 0;
+uint32_t *gr = mcp->__gregs;
+
+if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_size != 
sizeof(target_mcontext_vfp_t)) {
+return -TARGET_EINVAL;
+}
+
+gr[TARGET_REG_CPSR] = tswap32(cpsr_read(env));
+if (flags & TARGET_MC_GET_CLEAR_RET) {
+gr[TARGET_REG_R0] = 0;
+gr[TARGET_REG_CPSR] &= ~CPSR_C;
+} else {
+gr[TARGET_REG_R0] = tswap32(env->regs[0]);
+}
+
+gr[TARGET_REG_R1] = tswap32(env->regs[1]);
+gr[TARGET_REG_R2] = tswap32(env->regs[2]);
+gr[TARGET_REG_R3] = tswap32(env->regs[3]);
+gr[TARGET_REG_R4] = tswap32(env->regs[4]);
+gr[TARGET_REG_R5] = tswap32(env->regs[5]);
+gr[TARGET_REG_R6] = tswap32(env->regs[6]);
+gr[TARGET_REG_R7] = tswap32(env->regs[7]);
+gr[TARGET_REG_R8] = tswap32(env->regs[8]);
+gr[TARGET_REG_R9] = tswap32(env->regs[9]);
+gr[TARGET_REG_R10] = tswap32(env->regs[10]);
+gr[TARGET_REG_R11] = tswap32(env->regs[11]);
+gr[TARGET_REG_R12] = tswap32(env->regs[12]);
+
+gr[TARGET_REG_SP] = tswap32(env->regs[13]);
+gr[TARGET_REG_LR] = tswap32(env->regs[14]);
+gr[TARGET_REG_PC] = tswap32(env->regs[15]);
+
+if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_ptr != NULL) {
+/* see get_vfpcontext in sys/arm/arm/exec_machdep.c */
+target_mcontext_vfp_t *vfp = (target_mcontext_vfp_t *)mcp->mc_vfp_ptr;
+for (int i = 0; i < 32; i++) {
+vfp->mcv_reg[i] = tswap64(*aa32_vfp_dreg(env, i));
+}
+vfp->mcv_fpscr = tswap32(vfp_get_fpscr(env));
+}
+return err;
+}
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 10/30] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch

[Warner Losh]

Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_cpu.h | 94 ++
 1 file changed, 94 insertions(+)

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index cdb9440a65..e784c103a0 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -40,6 +40,7 @@ static inline void target_cpu_loop(CPUARMState *env)
 {
 int trapnr;
 target_siginfo_t info;
+unsigned int n;
 CPUState *cs = env_cpu(env);
 
 for (;;) {
@@ -87,6 +88,99 @@ static inline void target_cpu_loop(CPUARMState *env)
 }
 }
 break;
+case EXCP_SWI:
+case EXCP_BKPT:
+{
+/*
+ * system call
+ * See arm/arm/trap.c cpu_fetch_syscall_args()
+ */
+if (trapnr == EXCP_BKPT) {
+if (env->thumb) {
+env->regs[15] += 2;
+} else {
+env->regs[15] += 4;
+}
+}
+n = env->regs[7];
+if (bsd_type == target_freebsd) {
+int ret;
+abi_ulong params = get_sp_from_cpustate(env);
+int32_t syscall_nr = n;
+int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
+
+/* See arm/arm/trap.c cpu_fetch_syscall_args() */
+if (syscall_nr == TARGET_FREEBSD_NR_syscall) {
+syscall_nr = env->regs[0];
+arg1 = env->regs[1];
+arg2 = env->regs[2];
+arg3 = env->regs[3];
+get_user_s32(arg4, params);
+params += sizeof(int32_t);
+get_user_s32(arg5, params);
+params += sizeof(int32_t);
+get_user_s32(arg6, params);
+params += sizeof(int32_t);
+get_user_s32(arg7, params);
+arg8 = 0;
+} else if (syscall_nr == TARGET_FREEBSD_NR___syscall) {
+syscall_nr = env->regs[0];
+arg1 = env->regs[2];
+arg2 = env->regs[3];
+get_user_s32(arg3, params);
+params += sizeof(int32_t);
+get_user_s32(arg4, params);
+params += sizeof(int32_t);
+get_user_s32(arg5, params);
+params += sizeof(int32_t);
+get_user_s32(arg6, params);
+arg7 = 0;
+arg8 = 0;
+} else {
+arg1 = env->regs[0];
+arg2 = env->regs[1];
+arg3 = env->regs[2];
+arg4 = env->regs[3];
+get_user_s32(arg5, params);
+params += sizeof(int32_t);
+get_user_s32(arg6, params);
+params += sizeof(int32_t);
+get_user_s32(arg7, params);
+params += sizeof(int32_t);
+get_user_s32(arg8, params);
+}
+ret = do_freebsd_syscall(env, syscall_nr, arg1, arg2, arg3,
+arg4, arg5, arg6, arg7, arg8);
+/*
+ * Compare to arm/arm/vm_machdep.c
+ * cpu_set_syscall_retval()
+ */
+if (-TARGET_EJUSTRETURN == ret) {
+/*
+ * Returning from a successful sigreturn syscall.
+ * Avoid clobbering register state.
+ */
+break;
+}
+if (-TARGET_ERESTART == ret) {
+env->regs[15] -= env->thumb ? 2 : 4;
+break;
+}
+if ((unsigned int)ret >= (unsigned int)(-515)) {
+ret = -ret;
+cpsr_write(env, CPSR_C, CPSR_C, CPSRWriteByInstr);
+env->regs[0] = ret;
+} else {
+cpsr_write(env, 0, CPSR_C, CPSRWriteByInstr);
+env->regs[0] = ret; /* XXX need to handle lseek()? */
+/* env->regs[1] = 0; */
+}
+} else {
+fprintf(stderr, "qemu: bsd

[PATCH v2 19/30] bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack

[Warner Losh]

Defines for registers and stack layout related to signals.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_signal.h | 57 +++
 1 file changed, 57 insertions(+)
 create mode 100644 bsd-user/arm/target_arch_signal.h

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
new file mode 100644
index 00..973183d99c
--- /dev/null
+++ b/bsd-user/arm/target_arch_signal.h
@@ -0,0 +1,57 @@
+/*
+ *  arm signal definitions
+ *
+ *  Copyright (c) 2013 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#ifndef _TARGET_ARCH_SIGNAL_H_
+#define _TARGET_ARCH_SIGNAL_H_
+
+#include "cpu.h"
+
+#define TARGET_REG_R0   0
+#define TARGET_REG_R1   1
+#define TARGET_REG_R2   2
+#define TARGET_REG_R3   3
+#define TARGET_REG_R4   4
+#define TARGET_REG_R5   5
+#define TARGET_REG_R6   6
+#define TARGET_REG_R7   7
+#define TARGET_REG_R8   8
+#define TARGET_REG_R9   9
+#define TARGET_REG_R10  10
+#define TARGET_REG_R11  11
+#define TARGET_REG_R12  12
+#define TARGET_REG_R13  13
+#define TARGET_REG_R14  14
+#define TARGET_REG_R15  15
+#define TARGET_REG_CPSR 16
+#define TARGET__NGREG   17
+/* Convenience synonyms */
+#define TARGET_REG_FP   TARGET_REG_R11
+#define TARGET_REG_SP   TARGET_REG_R13
+#define TARGET_REG_LR   TARGET_REG_R14
+#define TARGET_REG_PC   TARGET_REG_R15
+
+#define TARGET_INSN_SIZE4   /* arm instruction size */
+
+/* Size of the signal trampolin code. See _sigtramp(). */
+#define TARGET_SZSIGCODE((abi_ulong)(9 * TARGET_INSN_SIZE))
+
+/* compare to arm/include/_limits.h */
+#define TARGET_MINSIGSTKSZ  (1024 * 4)  /* min sig stack size 
*/
+#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768)  /* recommended size 
*/
+
+#endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 09/30] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions

[Warner Losh]

Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
exceptions cause a SIGSEGV.

Signed-off-by: Kyle Evans 
Signed-off-by: Olivier Houchard 
Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_cpu.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 609b78b4e2..cdb9440a65 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -90,6 +90,17 @@ static inline void target_cpu_loop(CPUARMState *env)
 case EXCP_INTERRUPT:
 /* just indicate that signals should be handled asap */
 break;
+case EXCP_PREFETCH_ABORT:
+/* See arm/arm/trap.c prefetch_abort_handler() */
+case EXCP_DATA_ABORT:
+/* See arm/arm/trap.c data_abort_handler() */
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+/* XXX: check env->error_code */
+info.si_code = 0;
+info.si_addr = env->exception.vaddress;
+queue_signal(env, info.si_signo, &info);
+break;
 case EXCP_DEBUG:
 {
 
-- 
2.33.0

[PATCH v2 20/30] bsd-user/arm/target_arch_signal.h: arm machine context for signals

[Warner Losh]

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_signal.h | 20 
 1 file changed, 20 insertions(+)

diff --git a/bsd-user/arm/target_arch_signal.h 
b/bsd-user/arm/target_arch_signal.h
index 973183d99c..3aaced474b 100644
--- a/bsd-user/arm/target_arch_signal.h
+++ b/bsd-user/arm/target_arch_signal.h
@@ -54,4 +54,24 @@
 #define TARGET_MINSIGSTKSZ  (1024 * 4)  /* min sig stack size 
*/
 #define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768)  /* recommended size 
*/
 
+/*
+ * Floating point register state
+ */
+typedef struct target_mcontext_vfp {
+abi_ullong  mcv_reg[32];
+abi_ulong   mcv_fpscr;
+} target_mcontext_vfp_t;
+
+typedef struct target_mcontext {
+uint32_t__gregs[32];
+
+/*
+ * Originally, rest of this structure was named __fpu, 35 * 4 bytes
+ * long, never accessed from kernel.
+ */
+abi_longmc_vfp_size;
+abi_ptr *mc_vfp_ptr;
+abi_int mc_spare[33];
+} target_mcontext_t;
+
 #endif /* !_TARGET_ARCH_SIGNAL_H_ */
-- 
2.33.0

[PATCH v2 16/30] bsd-user/arm/target_arch_elf.h: arm get hwcap

[Warner Losh]

Implement get_elf_hwcap to get the first word of hardware capabilities.

Signed-off-by: Kyle Evans 
Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_elf.h | 72 +-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/bsd-user/arm/target_arch_elf.h b/bsd-user/arm/target_arch_elf.h
index 15b5c66511..02d25b8926 100644
--- a/bsd-user/arm/target_arch_elf.h
+++ b/bsd-user/arm/target_arch_elf.h
@@ -31,6 +31,76 @@
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE   4096
 
-#define ELF_HWCAP 0
+#define ELF_HWCAP get_elf_hwcap()
+
+#define GET_FEATURE(feat, hwcap) \
+do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
+
+#define GET_FEATURE_ID(feat, hwcap) \
+do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
+
+enum {
+ARM_HWCAP_ARM_SWP   = 1 << 0,
+ARM_HWCAP_ARM_HALF  = 1 << 1,
+ARM_HWCAP_ARM_THUMB = 1 << 2,
+ARM_HWCAP_ARM_26BIT = 1 << 3,
+ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
+ARM_HWCAP_ARM_FPA   = 1 << 5,
+ARM_HWCAP_ARM_VFP   = 1 << 6,
+ARM_HWCAP_ARM_EDSP  = 1 << 7,
+ARM_HWCAP_ARM_JAVA  = 1 << 8,
+ARM_HWCAP_ARM_IWMMXT= 1 << 9,
+ARM_HWCAP_ARM_CRUNCH= 1 << 10,
+ARM_HWCAP_ARM_THUMBEE   = 1 << 11,
+ARM_HWCAP_ARM_NEON  = 1 << 12,
+ARM_HWCAP_ARM_VFPv3 = 1 << 13,
+ARM_HWCAP_ARM_VFPv3D16  = 1 << 14,
+ARM_HWCAP_ARM_TLS   = 1 << 15,
+ARM_HWCAP_ARM_VFPv4 = 1 << 16,
+ARM_HWCAP_ARM_IDIVA = 1 << 17,
+ARM_HWCAP_ARM_IDIVT = 1 << 18,
+ARM_HWCAP_ARM_VFPD32= 1 << 19,
+ARM_HWCAP_ARM_LPAE  = 1 << 20,
+ARM_HWCAP_ARM_EVTSTRM   = 1 << 21,
+};
+
+static uint32_t get_elf_hwcap(void)
+{
+ARMCPU *cpu = ARM_CPU(thread_cpu);
+uint32_t hwcaps = 0;
+
+hwcaps |= ARM_HWCAP_ARM_SWP;
+hwcaps |= ARM_HWCAP_ARM_HALF;
+hwcaps |= ARM_HWCAP_ARM_THUMB;
+hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
+
+/* probe for the extra features */
+/* EDSP is in v5TE and above */
+GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
+GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
+GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
+GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
+GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
+GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
+GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
+GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
+GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
+
+if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
+cpu_isar_feature(aa32_fpdp_v3, cpu)) {
+hwcaps |= ARM_HWCAP_ARM_VFPv3;
+if (cpu_isar_feature(aa32_simd_r32, cpu)) {
+hwcaps |= ARM_HWCAP_ARM_VFPD32;
+} else {
+hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
+}
+}
+GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
+
+return hwcaps;
+}
+
+#undef GET_FEATURE
+#undef GET_FEATURE_ID
 
 #endif /* _TARGET_ARCH_ELF_H_ */
-- 
2.33.0

[PATCH v2 15/30] bsd-user/arm/target_arch_elf.h: arm defines for ELF

[Warner Losh]

Basic set of defines needed for arm ELF file activation.

Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_elf.h | 36 ++
 1 file changed, 36 insertions(+)
 create mode 100644 bsd-user/arm/target_arch_elf.h

diff --git a/bsd-user/arm/target_arch_elf.h b/bsd-user/arm/target_arch_elf.h
new file mode 100644
index 00..15b5c66511
--- /dev/null
+++ b/bsd-user/arm/target_arch_elf.h
@@ -0,0 +1,36 @@
+/*
+ *  arm ELF definitions
+ *
+ *  Copyright (c) 2013 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#ifndef _TARGET_ARCH_ELF_H_
+#define _TARGET_ARCH_ELF_H_
+
+#define ELF_START_MMAP 0x8000
+#define ELF_ET_DYN_LOAD_ADDR0x50
+
+#define elf_check_arch(x) ((x) == EM_ARM)
+
+#define ELF_CLASS   ELFCLASS32
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_ARM
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE   4096
+
+#define ELF_HWCAP 0
+
+#endif /* _TARGET_ARCH_ELF_H_ */
-- 
2.33.0

[PATCH 2/4] ui/gtk-egl: make sure the right context is set as the current

[Dongwon Kim]

Making the vc->gfx.ectx current before handling texture
associated with it

Cc: Gerd Hoffmann 
Signed-off-by: Dongwon Kim 
---
 ui/gtk-egl.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index 72ce5e1f8f..7c9629d6cc 100644
--- a/ui/gtk-egl.c
+++ b/ui/gtk-egl.c
@@ -139,6 +139,7 @@ void gd_egl_refresh(DisplayChangeListener *dcl)
 }
 vc->gfx.gls = qemu_gl_init_shader();
 if (vc->gfx.ds) {
+surface_gl_destroy_texture(vc->gfx.gls, vc->gfx.ds);
 surface_gl_create_texture(vc->gfx.gls, vc->gfx.ds);
 }
 }
@@ -165,6 +166,8 @@ void gd_egl_switch(DisplayChangeListener *dcl,
 surface_height(vc->gfx.ds) == surface_height(surface)) {
 resized = false;
 }
+eglMakeCurrent(qemu_egl_display, vc->gfx.esurface,
+   vc->gfx.esurface, vc->gfx.ectx);
 
 surface_gl_destroy_texture(vc->gfx.gls, vc->gfx.ds);
 vc->gfx.ds = surface;
@@ -224,6 +227,9 @@ void gd_egl_scanout_dmabuf(DisplayChangeListener *dcl,
 #ifdef CONFIG_GBM
 VirtualConsole *vc = container_of(dcl, VirtualConsole, gfx.dcl);
 
+eglMakeCurrent(qemu_egl_display, vc->gfx.esurface,
+   vc->gfx.esurface, vc->gfx.ectx);
+
 egl_dmabuf_import_texture(dmabuf);
 if (!dmabuf->texture) {
 return;
-- 
2.30.2

[PATCH v2 08/30] bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions

[Warner Losh]

Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.

Signed-off-by: Stacey Son 
Signed-off-by: Mikaël Urankar 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
---
 bsd-user/arm/target_arch_cpu.h | 58 ++
 1 file changed, 58 insertions(+)

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 2484bdc2f7..609b78b4e2 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -48,6 +48,64 @@ static inline void target_cpu_loop(CPUARMState *env)
 cpu_exec_end(cs);
 process_queued_cpu_work(cs);
 switch (trapnr) {
+case EXCP_UDEF:
+{
+/* See arm/arm/undefined.c undefinedinstruction(); */
+info.si_addr = env->regs[15];
+
+/*
+ * Make sure the PC is correctly aligned. (It should
+ * be.)
+ */
+if ((info.si_addr & 3) != 0) {
+info.si_signo = TARGET_SIGILL;
+info.si_errno = 0;
+info.si_code = TARGET_ILL_ILLADR;
+queue_signal(env, info.si_signo, &info);
+} else {
+int rc = 0;
+#ifdef NOT_YET
+uint32_t opcode;
+
+/*
+ * Get the opcode.
+ *
+ * FIXME - what to do if get_user() fails?
+ */
+get_user_u32(opcode, env->regs[15]);
+
+/* Check the opcode with CP handlers we may have. */
+rc = EmulateAll(opcode, &ts->fpa, env);
+#endif /* NOT_YET */
+if (rc == 0) {
+/* illegal instruction */
+info.si_signo = TARGET_SIGILL;
+info.si_errno = 0;
+info.si_code = TARGET_ILL_ILLOPC;
+queue_signal(env, info.si_signo, &info);
+}
+}
+}
+break;
+case EXCP_INTERRUPT:
+/* just indicate that signals should be handled asap */
+break;
+case EXCP_DEBUG:
+{
+
+info.si_signo = TARGET_SIGTRAP;
+info.si_errno = 0;
+info.si_code = TARGET_TRAP_BRKPT;
+info.si_addr = env->exception.vaddress;
+queue_signal(env, info.si_signo, &info);
+}
+break;
+case EXCP_ATOMIC:
+cpu_exec_step_atomic(cs);
+break;
+case EXCP_YIELD:
+/* nothing to do here for user-mode, just resume guest code */
+break;
 default:
 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
 trapnr);
-- 
2.33.0

[PATCH v2 12/30] bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space

[Warner Losh]

Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_vmparam.h | 48 ++
 1 file changed, 48 insertions(+)
 create mode 100644 bsd-user/arm/target_arch_vmparam.h

diff --git a/bsd-user/arm/target_arch_vmparam.h 
b/bsd-user/arm/target_arch_vmparam.h
new file mode 100644
index 00..4bbc04ddf5
--- /dev/null
+++ b/bsd-user/arm/target_arch_vmparam.h
@@ -0,0 +1,48 @@
+/*
+ *  arm VM parameters definitions
+ *
+ *  Copyright (c) 2013 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#ifndef _TARGET_ARCH_VMPARAM_H_
+#define _TARGET_ARCH_VMPARAM_H_
+
+#include "cpu.h"
+
+/* compare to sys/arm/include/vmparam.h */
+#define TARGET_MAXTSIZ  (64 * MiB)   /* max text size */
+#define TARGET_DFLDSIZ  (128 * MiB)  /* initial data size limit */
+#define TARGET_MAXDSIZ  (512 * MiB)  /* max data size */
+#define TARGET_DFLSSIZ  (4 * MiB)/* initial stack size limit */
+#define TARGET_MAXSSIZ  (64 * MiB)   /* max stack size */
+#define TARGET_SGROWSIZ (128 * KiB)  /* amount to grow stack */
+
+#define TARGET_RESERVED_VA  0xf700
+
+/* KERNBASE - 512 MB */
+#define TARGET_VM_MAXUSER_ADDRESS   (0xc000 - (512 * MiB))
+#define TARGET_USRSTACK TARGET_VM_MAXUSER_ADDRESS
+
+static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
+{
+return state->regs[13]; /* sp */
+}
+
+static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
+{
+state->regs[1] = retval2;
+}
+
+#endif  /* ! _TARGET_ARCH_VMPARAM_H_ */
-- 
2.33.0

[PATCH v2 14/30] bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread

[Warner Losh]

Implement target_thread_init (to create a thread) and target_set_upcall
(to switch to a thread) for arm.

Signed-off-by: Stacey Son 
Signed-off-by: Kyle Evans 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
---
 bsd-user/arm/target_arch_thread.h | 80 +++
 1 file changed, 80 insertions(+)
 create mode 100644 bsd-user/arm/target_arch_thread.h

diff --git a/bsd-user/arm/target_arch_thread.h 
b/bsd-user/arm/target_arch_thread.h
new file mode 100644
index 00..ae5b0d6c38
--- /dev/null
+++ b/bsd-user/arm/target_arch_thread.h
@@ -0,0 +1,80 @@
+/*
+ *  arm thread support
+ *
+ *  Copyright (c) 2013 Stacey D. Son
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see .
+ */
+#ifndef _TARGET_ARCH_THREAD_H_
+#define _TARGET_ARCH_THREAD_H_
+
+/* Compare to arm/arm/vm_machdep.c cpu_set_upcall_kse() */
+static inline void target_thread_set_upcall(CPUARMState *env, abi_ulong entry,
+abi_ulong arg, abi_ulong stack_base, abi_ulong stack_size)
+{
+abi_ulong sp;
+
+/*
+ * Make sure the stack is properly aligned.
+ * arm/include/param.h (STACKLIGN() macro)
+ */
+sp = (u_int)(stack_base + stack_size) & ~0x7;
+
+/* sp = stack base */
+env->regs[13] = sp;
+/* pc = start function entry */
+env->regs[15] = entry & 0xfffe;
+/* r0 = arg */
+env->regs[0] = arg;
+env->spsr = ARM_CPU_MODE_USR;
+/*
+ * Thumb mode is encoded by the low bit in the entry point (since ARM can't
+ * execute at odd addresses). When it's set, set the Thumb bit (T) in the
+ * CPSR.
+ */
+if (entry & 0x1) {
+cpsr_write(env, cpsr_read(env) | CPSR_T, CPSR_T, CPSRWriteByInstr);
+}
+}
+
+static inline void target_thread_init(struct target_pt_regs *regs,
+struct image_info *infop)
+{
+abi_long stack = infop->start_stack;
+memset(regs, 0, sizeof(*regs));
+regs->ARM_cpsr = 0x10;
+/*
+ * Thumb mode is encoded by the low bit in the entry point (since ARM can't
+ * execute at odd addresses). When it's set, set the Thumb bit (T) in the
+ * CPSR.
+ */
+if (infop->entry & 1) {
+regs->ARM_cpsr |= CPSR_T;
+}
+regs->ARM_pc = infop->entry & 0xfffe;
+regs->ARM_sp = infop->start_stack;
+if (bsd_type == target_freebsd) {
+regs->ARM_lr = infop->entry & 0xfffe;
+}
+/* FIXME - what to for failure of get_user()? */
+get_user_ual(regs->ARM_r2, stack + 8); /* envp */
+get_user_ual(regs->ARM_r1, stack + 4); /* envp */
+/* XXX: it seems that r0 is zeroed after ! */
+regs->ARM_r0 = 0;
+/* For uClinux PIC binaries.  */
+/* XXX: Linux does this only on ARM with no MMU (do we care ?) */
+regs->ARM_r10 = infop->start_data;
+}
+
+#endif /* !_TARGET_ARCH_THREAD_H_ */
-- 
2.33.0

[PATCH v2 07/30] bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation

[Warner Losh]

Add a boiler plate CPU loop that does nothing except return an error for
all traps.

Signed-off-by: Sean Bruno 
Signed-off-by: Stacey Son 
Signed-off-by: Warner Losh 
Reviewed-by: Kyle Evans 
Reviewed-by: Richard Henderson 
---
 bsd-user/arm/target_arch_cpu.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index fa45d9335d..2484bdc2f7 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -36,6 +36,28 @@ static inline void target_cpu_init(CPUARMState *env,
 }
 }
 
+static inline void target_cpu_loop(CPUARMState *env)
+{
+int trapnr;
+target_siginfo_t info;
+CPUState *cs = env_cpu(env);
+
+for (;;) {
+cpu_exec_start(cs);
+trapnr = cpu_exec(cs);
+cpu_exec_end(cs);
+process_queued_cpu_work(cs);
+switch (trapnr) {
+default:
+fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
+trapnr);
+cpu_dump_state(cs, stderr, 0);
+abort();
+} /* switch() */
+process_pending_signals(env);
+} /* for (;;) */
+}
+
 static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 {
 if (newsp) {
-- 
2.33.0