Re: [PATCH v2 4/6] target/riscv: add support for zdinx
在 2022/1/1 上午4:07, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
get_xl, not get_ol, two instances.
+#ifdef TARGET_RISCV32
+ {
+ TCGv_i64 t = ftemp_new(ctx);
+ tcg_gen_concat_i32_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num
+ 1]);
+ return t;
+ }
+#else
+ {
+ TCGv_i64 t = ftemp_new(ctx);
+ tcg_gen_deposit_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num +
1], 32, 32);
+ return t;
+ }
Unify these two cases and use tcg_gen_concat_tl_i64.
OK. I'll fix this.
r~
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
在 2022/1/1 上午4:06, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
+ if (reg_num != 0) {
+ switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not
get_ol.
Sorry. I don't know the difference between get_xl and get_ol. From gpr
register read/write function, It seems get_ol is used in register read,
and get_xl is used in register write.
However, "ctx->ol= ctx->xl;" is executed before translate instruction.
"
r~
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
Thanks for your comments.
在 2022/1/1 上午3:56, Richard Henderson 写道:
On 12/30/21 7:23 PM, Weiwei Li wrote:
@@ -363,6 +363,10 @@ static void riscv_cpu_reset(DeviceState *dev)
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus &= ~MSTATUS_FS;
+ }
This shouldn't be necessary because it should never have been set.
Yes, I think so. However, I have a question about MSTATUS_MIE and
MSTATUS_MPRV, will they be set before cpu reset?
- uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM|
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | MSTATUS_VS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ mstatus_mask |= MSTATUS_FS;
+ }
I would think it would be more correct to have a positive test for
RVF, rather than a negative test for ZFINX?
It may deviate from the original value of mstatus_mask with a positive
test for RVF.
r~
Re: [PULL 00/20] Machine-next patches for 2021-12-31
On 12/31/21 20:06, Richard Henderson wrote: > On 12/31/21 4:47 AM, Philippe Mathieu-Daudé wrote: >> The following changes since commit >> 69f153667fce723ee546d2f047d66d0cfa67c3cc: >> >> Machine core patches >> >> - Clarify qdev_connect_gpio_out() documentation >> - Rework test-smp-parse tests following QOM style >> - Introduce CPU cluster topology support (Yanan Wang) >> - MAINTAINERS updates (Yanan Wang, Li Zhijian, myself) >> >> > > Applied, thanks. Thanks :~)
Re: [PATCH v2 4/6] target/riscv: add support for zdinx
On 12/30/21 7:23 PM, Weiwei Li wrote:
+if (reg_num != 0) {
+switch (get_ol(ctx)) {
get_xl, not get_ol, two instances.
+#ifdef TARGET_RISCV32
+{
+TCGv_i64 t = ftemp_new(ctx);
+tcg_gen_concat_i32_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
+return t;
+}
+#else
+{
+TCGv_i64 t = ftemp_new(ctx);
+tcg_gen_deposit_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1], 32, 32);
+return t;
+}
Unify these two cases and use tcg_gen_concat_tl_i64.
r~
Re: [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin
On 12/30/21 7:23 PM, Weiwei Li wrote: From: liweiwei - update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN - update half float point register read/write - disable nanbox_h check Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/fpu_helper.c | 89 +++--- target/riscv/helper.h | 2 +- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++--- target/riscv/internals.h | 16 +- 4 files changed, 296 insertions(+), 143 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
On 12/30/21 7:23 PM, Weiwei Li wrote:
+if (reg_num != 0) {
+switch (get_ol(ctx)) {
Oh, you should be using get_xl here and elsewhere in this patch, not get_ol.
r~
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
On 12/30/21 7:23 PM, Weiwei Li wrote: From: liweiwei - update extension check REQUIRE_ZFINX_OR_F - update single float point register read/write - disable nanbox_s check Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/fpu_helper.c | 89 +++ target/riscv/helper.h | 2 +- target/riscv/insn_trans/trans_rvf.c.inc | 314 target/riscv/internals.h| 16 +- target/riscv/translate.c| 90 +++ 5 files changed, 367 insertions(+), 144 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
On 12/30/21 7:23 PM, Weiwei Li wrote:
@@ -363,6 +363,10 @@ static void riscv_cpu_reset(DeviceState *dev)
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+/* hardwire mstatus.FS to zero when enable zfinx */
+if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+env->mstatus &= ~MSTATUS_FS;
+}
This shouldn't be necessary because it should never have been set.
-uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM|
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | MSTATUS_VS;
+/* hardwire mstatus.FS to zero when enable zfinx */
+if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+mstatus_mask |= MSTATUS_FS;
+}
I would think it would be more correct to have a positive test for RVF, rather than a
negative test for ZFINX?
r~
[PATCH] meson: Unify mips and mips64 in host_arch
Fixes the build on a mips64 host. Prior to the break, we identified
the arch via the __mips__ define; afterward we use meson's
host_machine.cpu_family(). Restore the previous combination.
Fixes: 823eb013452e ("configure, meson: move ARCH to meson.build")
Reported-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 886f0a9343..53065e96ec 100644
--- a/meson.build
+++ b/meson.build
@@ -74,6 +74,8 @@ if cpu not in supported_cpus
host_arch = 'unknown'
elif cpu == 'x86'
host_arch = 'i386'
+elif cpu == 'mips64'
+ host_arch = 'mips'
else
host_arch = cpu
endif
--
2.25.1
Re: [PULL 00/20] Machine-next patches for 2021-12-31
On 12/31/21 4:47 AM, Philippe Mathieu-Daudé wrote: The following changes since commit 69f153667fce723ee546d2f047d66d0cfa67c3cc: Merge tag 'memory-api-20211231' of https://github.com/philmd/qemu into staging (2021-12-30 17:02:42 -0800) are available in the Git repository at: https://github.com/philmd/qemu.git tags/machine-core-20211231 for you to fetch changes up to 2ece6e64846e1929c4ed338c73328d3b126e48d3: MAINTAINERS: email address change (2021-12-31 13:42:54 +0100) Machine core patches - Clarify qdev_connect_gpio_out() documentation - Rework test-smp-parse tests following QOM style - Introduce CPU cluster topology support (Yanan Wang) - MAINTAINERS updates (Yanan Wang, Li Zhijian, myself) Li Zhijian (1): MAINTAINERS: email address change Philippe Mathieu-Daudé (13): hw/qdev: Cosmetic around documentation hw/qdev: Correct qdev_init_gpio_out_named() documentation hw/qdev: Correct qdev_connect_gpio_out_named() documentation hw/qdev: Rename qdev_connect_gpio_out*() 'input_pin' parameter tests/unit/test-smp-parse: Pass machine type as argument to tests tests/unit/test-smp-parse: Split the 'generic' test in valid / invalid tests/unit/test-smp-parse: Add 'smp-with-dies' machine type tests/unit/test-smp-parse: Add 'smp-generic-invalid' machine type tests/unit/test-smp-parse: Add 'smp-generic-valid' machine type tests/unit/test-smp-parse: Simplify pointer to compound literal use tests/unit/test-smp-parse: Constify some pointer/struct hw/core: Rename smp_parse() -> machine_parse_smp_config() MAINTAINERS: Change philmd's email address Yanan Wang (6): qemu-options: Improve readability of SMP related Docs hw/core/machine: Introduce CPU cluster topology support tests/unit/test-smp-parse: Add testcases for CPU clusters tests/unit/test-smp-parse: No need to explicitly zero MachineClass members tests/unit/test-smp-parse: Keep default MIN/MAX CPUs in machine_base_class_init MAINTAINERS: Self-recommended as reviewer of "Machine core" qapi/machine.json| 5 +- include/hw/boards.h | 9 +- include/hw/qdev-core.h | 24 ++- hw/core/gpio.c | 13 +- hw/core/machine-smp.c| 32 ++-- hw/core/machine.c| 5 +- softmmu/vl.c | 3 + tests/unit/test-smp-parse.c | 295 ++- .gitlab-ci.d/edk2/Dockerfile | 2 +- .mailmap | 1 + MAINTAINERS | 21 +-- qemu-options.hx | 79 +++--- 12 files changed, 358 insertions(+), 131 deletions(-) Applied, thanks. r~
Re: [PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
> On 31 Dec 2021, at 17:56, Alexander Orzechowski
> wrote:
>
>
> On 12/31/21 12:42, Carwyn Ellis wrote:
>> When switching between guest and host on a Mac using command-tab the
>> command key is sent to the guest which can trigger functionality in the
>> guest OS. Specifying left-command-key=off disables forwarding this key
>> to the guest. Defaults to enabled.
>>
>> When switching between guest and host on a Mac with a fullscreen guest
>> the host pointer will occasionally persist despite the ui code
>> requesting that it be hidden. Added cursor hide calls on left and right
>> mouse click to hide the cursor when the mouse is clicked.
>>
>> Also updated the cocoa display documentation to reference the new
>> left-command-key option along with the existing show-cursor option.
>> ---
>> qapi/ui.json| 17 +
>> qemu-options.hx | 12
>> ui/cocoa.m | 33 +
>> 3 files changed, 54 insertions(+), 8 deletions(-)
>>
>> diff --git a/qapi/ui.json b/qapi/ui.json
>> index 2b4371da37..764480e145 100644
>> --- a/qapi/ui.json
>> +++ b/qapi/ui.json
>> @@ -1107,6 +1107,22 @@
>>'data': { '*grab-on-hover' : 'bool',
>> '*zoom-to-fit' : 'bool' } }
>> +##
>> +# @DisplayCocoa:
>> +#
>> +# Cocoa display options.
>> +#
>> +# @left-command-key: Enable/disable forwarding of left command key to
>> +#guest. Allows command-tab window switching on the
>> +#host without sending this key to the guest when
>> +#"off". Defaults to "on"
>> +#
>> +# Since: 6.2.50
>> +#
>> +##
>> +{ 'struct' : 'DisplayCocoa',
>> + 'data': { '*left-command-key' : 'bool' } }
>> +
>> ##
>> # @DisplayEGLHeadless:
>> #
>> @@ -1254,6 +1270,7 @@
>>'discriminator' : 'type',
>>'data': {
>>'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
>> + 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
>>'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
>>'egl-headless': { 'type': 'DisplayEGLHeadless',
>> 'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 7d47510947..5214457676 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
>> #if defined(CONFIG_DBUS_DISPLAY)
>> "-display dbus[,addr=]\n"
>> " [,gl=on|core|es|off][,rendernode=]\n"
>> +#endif
>> +#if defined(CONFIG_COCOA)
>> +"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
>> #endif
>> "-display none\n"
>> "select display backend type\n"
>> @@ -1956,6 +1959,15 @@ SRST
>> ``charset=CP850`` for IBM CP850 encoding. The default is
>> ``CP437``.
>> +``cocoa``
>> +Display video output in a Cocoa window. Mac only. This interface
>> +provides drop-down menus and other UI elements to configure and
>> +control the VM during runtime. Valid parameters are:
>> +
>> +``show-cursor=on|off`` : Force showing the mouse cursor
>> +
>> +``left-command-key=on|off`` : Disable forwarding left command key
>> to host
>> +
>> ``egl-headless[,rendernode=]``
>> Offload all OpenGL operations to a local DRI device. For any
>> graphical display, this display needs to be paired with either
>> diff --git a/ui/cocoa.m b/ui/cocoa.m
>> index 69745c483b..10e492538a 100644
>> --- a/ui/cocoa.m
>> +++ b/ui/cocoa.m
>> @@ -95,6 +95,8 @@ static DisplayChangeListener dcl = {
>> };
>> static int last_buttons;
>> static int cursor_hide = 1;
>> +static bool cursor_visible = 1;
>> +static int left_command_key_enabled = 1;
>>static int gArgc;
>> static char **gArgv;
>> @@ -411,18 +413,18 @@ QemuCocoaView *cocoaView;
>>- (void) hideCursor
>> {
>> -if (!cursor_hide) {
>> -return;
>> +if (cursor_hide && cursor_visible) {
>> +cursor_visible = 0;
>> +[NSCursor hide];
>> }
>> -[NSCursor hide];
>> }
>>- (void) unhideCursor
>> {
>> -if (!cursor_hide) {
>> -return;
>> +if (cursor_hide && !cursor_visible) {
>> +cursor_visible = 1;
>> +[NSCursor unhide];
>> }
>> -[NSCursor unhide];
>> }
>>- (void) drawRect:(NSRect) rect
>> @@ -831,10 +833,14 @@ QemuCocoaView *cocoaView;
>> }
>> break;
>> -/* Don't pass command key changes to guest unless mouse is
>> grabbed */
>> +/*
>> +Don't pass command key changes to guest unless mouse is
>> grabbed
>> +or the key is explicitly disabled using the
>> left-command-key option
>> +*/
>> case kVK_Command:
>> if (isMouseGrabbed &&
>> -!!(modifiers & NSEventModifierFlagCommand)) {
>> +!
Re: [PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
On 12/31/21 12:42, Carwyn Ellis wrote:
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
When switching between guest and host on a Mac with a fullscreen guest
the host pointer will occasionally persist despite the ui code
requesting that it be hidden. Added cursor hide calls on left and right
mouse click to hide the cursor when the mouse is clicked.
Also updated the cocoa display documentation to reference the new
left-command-key option along with the existing show-cursor option.
---
qapi/ui.json| 17 +
qemu-options.hx | 12
ui/cocoa.m | 33 +
3 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 2b4371da37..764480e145 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1107,6 +1107,22 @@
'data': { '*grab-on-hover' : 'bool',
'*zoom-to-fit' : 'bool' } }
+##
+# @DisplayCocoa:
+#
+# Cocoa display options.
+#
+# @left-command-key: Enable/disable forwarding of left command key to
+#guest. Allows command-tab window switching on the
+#host without sending this key to the guest when
+#"off". Defaults to "on"
+#
+# Since: 6.2.50
+#
+##
+{ 'struct' : 'DisplayCocoa',
+ 'data': { '*left-command-key' : 'bool' } }
+
##
# @DisplayEGLHeadless:
#
@@ -1254,6 +1270,7 @@
'discriminator' : 'type',
'data': {
'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
+ 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
'egl-headless': { 'type': 'DisplayEGLHeadless',
'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
diff --git a/qemu-options.hx b/qemu-options.hx
index 7d47510947..5214457676 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
#if defined(CONFIG_DBUS_DISPLAY)
"-display dbus[,addr=]\n"
" [,gl=on|core|es|off][,rendernode=]\n"
+#endif
+#if defined(CONFIG_COCOA)
+"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
#endif
"-display none\n"
"select display backend type\n"
@@ -1956,6 +1959,15 @@ SRST
``charset=CP850`` for IBM CP850 encoding. The default is
``CP437``.
+``cocoa``
+Display video output in a Cocoa window. Mac only. This interface
+provides drop-down menus and other UI elements to configure and
+control the VM during runtime. Valid parameters are:
+
+``show-cursor=on|off`` : Force showing the mouse cursor
+
+``left-command-key=on|off`` : Disable forwarding left command key to
host
+
``egl-headless[,rendernode=]``
Offload all OpenGL operations to a local DRI device. For any
graphical display, this display needs to be paired with either
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..10e492538a 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -95,6 +95,8 @@ static DisplayChangeListener dcl = {
};
static int last_buttons;
static int cursor_hide = 1;
+static bool cursor_visible = 1;
+static int left_command_key_enabled = 1;
static int gArgc;
static char **gArgv;
@@ -411,18 +413,18 @@ QemuCocoaView *cocoaView;
- (void) hideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && cursor_visible) {
+cursor_visible = 0;
+[NSCursor hide];
}
-[NSCursor hide];
}
- (void) unhideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && !cursor_visible) {
+cursor_visible = 1;
+[NSCursor unhide];
}
-[NSCursor unhide];
}
- (void) drawRect:(NSRect) rect
@@ -831,10 +833,14 @@ QemuCocoaView *cocoaView;
}
break;
-/* Don't pass command key changes to guest unless mouse is grabbed */
+/*
+Don't pass command key changes to guest unless mouse is
grabbed
+or the key is explicitly disabled using the
left-command-key option
+*/
case kVK_Command:
if (isMouseGrabbed &&
-!!(modifiers & NSEventModifierFlagCommand)) {
+!!(modifiers & NSEventModifierFlagCommand) &&
+left_command_key_enabled) {
[self toggleKey:Q_KEY_CODE_META_L];
}
break;
@@ -923,10 +929,16 @@ QemuCocoaView *cocoaView;
case NSEventTypeLeftMouseDown:
buttons |= MOUSE_EVENT_LBUTTON;
mouse_event = true;
+if (is
Re: [PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
Ok cool, I’ll separate this out into 2 patches for the fullscreen and
left-command changes respectively.
Will aim to get this out at some point tomorrow.
Cheers
Carwyn
> On 31 Dec 2021, at 17:49, Alexander Orzechowski
> wrote:
>
>
> On 12/31/21 12:42, Carwyn Ellis wrote:
>> When switching between guest and host on a Mac using command-tab the
>> command key is sent to the guest which can trigger functionality in the
>> guest OS. Specifying left-command-key=off disables forwarding this key
>> to the guest. Defaults to enabled.
>>
>> When switching between guest and host on a Mac with a fullscreen guest
>> the host pointer will occasionally persist despite the ui code
>> requesting that it be hidden. Added cursor hide calls on left and right
>> mouse click to hide the cursor when the mouse is clicked.
>>
>> Also updated the cocoa display documentation to reference the new
>> left-command-key option along with the existing show-cursor option.
>> ---
>> qapi/ui.json| 17 +
>> qemu-options.hx | 12
>> ui/cocoa.m | 33 +
>> 3 files changed, 54 insertions(+), 8 deletions(-)
>>
>> diff --git a/qapi/ui.json b/qapi/ui.json
>> index 2b4371da37..764480e145 100644
>> --- a/qapi/ui.json
>> +++ b/qapi/ui.json
>> @@ -1107,6 +1107,22 @@
>>'data': { '*grab-on-hover' : 'bool',
>> '*zoom-to-fit' : 'bool' } }
>> +##
>> +# @DisplayCocoa:
>> +#
>> +# Cocoa display options.
>> +#
>> +# @left-command-key: Enable/disable forwarding of left command key to
>> +#guest. Allows command-tab window switching on the
>> +#host without sending this key to the guest when
>> +#"off". Defaults to "on"
>> +#
>> +# Since: 6.2.50
>> +#
>> +##
>> +{ 'struct' : 'DisplayCocoa',
>> + 'data': { '*left-command-key' : 'bool' } }
>> +
>> ##
>> # @DisplayEGLHeadless:
>> #
>> @@ -1254,6 +1270,7 @@
>>'discriminator' : 'type',
>>'data': {
>>'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
>> + 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
>>'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
>>'egl-headless': { 'type': 'DisplayEGLHeadless',
>> 'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 7d47510947..5214457676 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
>> #if defined(CONFIG_DBUS_DISPLAY)
>> "-display dbus[,addr=]\n"
>> " [,gl=on|core|es|off][,rendernode=]\n"
>> +#endif
>> +#if defined(CONFIG_COCOA)
>> +"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
>> #endif
>> "-display none\n"
>> "select display backend type\n"
>> @@ -1956,6 +1959,15 @@ SRST
>> ``charset=CP850`` for IBM CP850 encoding. The default is
>> ``CP437``.
>> +``cocoa``
>> +Display video output in a Cocoa window. Mac only. This interface
>> +provides drop-down menus and other UI elements to configure and
>> +control the VM during runtime. Valid parameters are:
>> +
>> +``show-cursor=on|off`` : Force showing the mouse cursor
>> +
>> +``left-command-key=on|off`` : Disable forwarding left command key
>> to host
>> +
>> ``egl-headless[,rendernode=]``
>> Offload all OpenGL operations to a local DRI device. For any
>> graphical display, this display needs to be paired with either
>> diff --git a/ui/cocoa.m b/ui/cocoa.m
>> index 69745c483b..10e492538a 100644
>> --- a/ui/cocoa.m
>> +++ b/ui/cocoa.m
>> @@ -95,6 +95,8 @@ static DisplayChangeListener dcl = {
>> };
>> static int last_buttons;
>> static int cursor_hide = 1;
>> +static bool cursor_visible = 1;
>> +static int left_command_key_enabled = 1;
>>static int gArgc;
>> static char **gArgv;
>> @@ -411,18 +413,18 @@ QemuCocoaView *cocoaView;
>>- (void) hideCursor
>> {
>> -if (!cursor_hide) {
>> -return;
>> +if (cursor_hide && cursor_visible) {
>> +cursor_visible = 0;
>> +[NSCursor hide];
>> }
>> -[NSCursor hide];
>> }
>>- (void) unhideCursor
>> {
>> -if (!cursor_hide) {
>> -return;
>> +if (cursor_hide && !cursor_visible) {
>> +cursor_visible = 1;
>> +[NSCursor unhide];
>> }
>> -[NSCursor unhide];
>> }
>>- (void) drawRect:(NSRect) rect
>> @@ -831,10 +833,14 @@ QemuCocoaView *cocoaView;
>> }
>> break;
>> -/* Don't pass command key changes to guest unless mouse is
>> grabbed */
>> +/*
>> +Don't pass command key changes to guest unless mouse is
>> grabbed
>> +or the key is explicitly disabled using the
>> left-command-key option
>> +*/
>>
Re: [PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
On 12/31/21 12:42, Carwyn Ellis wrote:
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
When switching between guest and host on a Mac with a fullscreen guest
the host pointer will occasionally persist despite the ui code
requesting that it be hidden. Added cursor hide calls on left and right
mouse click to hide the cursor when the mouse is clicked.
Also updated the cocoa display documentation to reference the new
left-command-key option along with the existing show-cursor option.
---
qapi/ui.json| 17 +
qemu-options.hx | 12
ui/cocoa.m | 33 +
3 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 2b4371da37..764480e145 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1107,6 +1107,22 @@
'data': { '*grab-on-hover' : 'bool',
'*zoom-to-fit' : 'bool' } }
+##
+# @DisplayCocoa:
+#
+# Cocoa display options.
+#
+# @left-command-key: Enable/disable forwarding of left command key to
+#guest. Allows command-tab window switching on the
+#host without sending this key to the guest when
+#"off". Defaults to "on"
+#
+# Since: 6.2.50
+#
+##
+{ 'struct' : 'DisplayCocoa',
+ 'data': { '*left-command-key' : 'bool' } }
+
##
# @DisplayEGLHeadless:
#
@@ -1254,6 +1270,7 @@
'discriminator' : 'type',
'data': {
'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
+ 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
'egl-headless': { 'type': 'DisplayEGLHeadless',
'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
diff --git a/qemu-options.hx b/qemu-options.hx
index 7d47510947..5214457676 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
#if defined(CONFIG_DBUS_DISPLAY)
"-display dbus[,addr=]\n"
" [,gl=on|core|es|off][,rendernode=]\n"
+#endif
+#if defined(CONFIG_COCOA)
+"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
#endif
"-display none\n"
"select display backend type\n"
@@ -1956,6 +1959,15 @@ SRST
``charset=CP850`` for IBM CP850 encoding. The default is
``CP437``.
+``cocoa``
+Display video output in a Cocoa window. Mac only. This interface
+provides drop-down menus and other UI elements to configure and
+control the VM during runtime. Valid parameters are:
+
+``show-cursor=on|off`` : Force showing the mouse cursor
+
+``left-command-key=on|off`` : Disable forwarding left command key to
host
+
``egl-headless[,rendernode=]``
Offload all OpenGL operations to a local DRI device. For any
graphical display, this display needs to be paired with either
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..10e492538a 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -95,6 +95,8 @@ static DisplayChangeListener dcl = {
};
static int last_buttons;
static int cursor_hide = 1;
+static bool cursor_visible = 1;
+static int left_command_key_enabled = 1;
static int gArgc;
static char **gArgv;
@@ -411,18 +413,18 @@ QemuCocoaView *cocoaView;
- (void) hideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && cursor_visible) {
+cursor_visible = 0;
+[NSCursor hide];
}
-[NSCursor hide];
}
- (void) unhideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && !cursor_visible) {
+cursor_visible = 1;
+[NSCursor unhide];
}
-[NSCursor unhide];
}
- (void) drawRect:(NSRect) rect
@@ -831,10 +833,14 @@ QemuCocoaView *cocoaView;
}
break;
-/* Don't pass command key changes to guest unless mouse is grabbed */
+/*
+Don't pass command key changes to guest unless mouse is
grabbed
+or the key is explicitly disabled using the
left-command-key option
+*/
case kVK_Command:
if (isMouseGrabbed &&
-!!(modifiers & NSEventModifierFlagCommand)) {
+!!(modifiers & NSEventModifierFlagCommand) &&
+left_command_key_enabled) {
[self toggleKey:Q_KEY_CODE_META_L];
}
break;
@@ -923,10 +929,16 @@ QemuCocoaView *cocoaView;
case NSEventTypeLeftMouseDown:
buttons |= MOUSE_EVENT_LBUTTON;
mouse_event = true;
+if (is
[PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
When switching between guest and host on a Mac with a fullscreen guest
the host pointer will occasionally persist despite the ui code
requesting that it be hidden. Added cursor hide calls on left and right
mouse click to hide the cursor when the mouse is clicked.
Also updated the cocoa display documentation to reference the new
left-command-key option along with the existing show-cursor option.
---
qapi/ui.json| 17 +
qemu-options.hx | 12
ui/cocoa.m | 33 +
3 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 2b4371da37..764480e145 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1107,6 +1107,22 @@
'data': { '*grab-on-hover' : 'bool',
'*zoom-to-fit' : 'bool' } }
+##
+# @DisplayCocoa:
+#
+# Cocoa display options.
+#
+# @left-command-key: Enable/disable forwarding of left command key to
+#guest. Allows command-tab window switching on the
+#host without sending this key to the guest when
+#"off". Defaults to "on"
+#
+# Since: 6.2.50
+#
+##
+{ 'struct' : 'DisplayCocoa',
+ 'data': { '*left-command-key' : 'bool' } }
+
##
# @DisplayEGLHeadless:
#
@@ -1254,6 +1270,7 @@
'discriminator' : 'type',
'data': {
'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
+ 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
'egl-headless': { 'type': 'DisplayEGLHeadless',
'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
diff --git a/qemu-options.hx b/qemu-options.hx
index 7d47510947..5214457676 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
#if defined(CONFIG_DBUS_DISPLAY)
"-display dbus[,addr=]\n"
" [,gl=on|core|es|off][,rendernode=]\n"
+#endif
+#if defined(CONFIG_COCOA)
+"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
#endif
"-display none\n"
"select display backend type\n"
@@ -1956,6 +1959,15 @@ SRST
``charset=CP850`` for IBM CP850 encoding. The default is
``CP437``.
+``cocoa``
+Display video output in a Cocoa window. Mac only. This interface
+provides drop-down menus and other UI elements to configure and
+control the VM during runtime. Valid parameters are:
+
+``show-cursor=on|off`` : Force showing the mouse cursor
+
+``left-command-key=on|off`` : Disable forwarding left command key to
host
+
``egl-headless[,rendernode=]``
Offload all OpenGL operations to a local DRI device. For any
graphical display, this display needs to be paired with either
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..10e492538a 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -95,6 +95,8 @@ static DisplayChangeListener dcl = {
};
static int last_buttons;
static int cursor_hide = 1;
+static bool cursor_visible = 1;
+static int left_command_key_enabled = 1;
static int gArgc;
static char **gArgv;
@@ -411,18 +413,18 @@ QemuCocoaView *cocoaView;
- (void) hideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && cursor_visible) {
+cursor_visible = 0;
+[NSCursor hide];
}
-[NSCursor hide];
}
- (void) unhideCursor
{
-if (!cursor_hide) {
-return;
+if (cursor_hide && !cursor_visible) {
+cursor_visible = 1;
+[NSCursor unhide];
}
-[NSCursor unhide];
}
- (void) drawRect:(NSRect) rect
@@ -831,10 +833,14 @@ QemuCocoaView *cocoaView;
}
break;
-/* Don't pass command key changes to guest unless mouse is
grabbed */
+/*
+Don't pass command key changes to guest unless mouse is
grabbed
+or the key is explicitly disabled using the
left-command-key option
+*/
case kVK_Command:
if (isMouseGrabbed &&
-!!(modifiers & NSEventModifierFlagCommand)) {
+!!(modifiers & NSEventModifierFlagCommand) &&
+left_command_key_enabled) {
[self toggleKey:Q_KEY_CODE_META_L];
}
break;
@@ -923,10 +929,16 @@ QemuCocoaView *cocoaView;
case NSEventTypeLeftMouseDown:
buttons |= MOUSE_EVENT_LBUTTON;
mouse_event = true;
+if (isFullscreen) {
+[self hideCursor];
+}
break;
case NSEvent
[PATCH 0/1] ui/cocoa: Add option to disable left command and hide cursor on click
Apologies for all the spam on what should be a simple change. Still getting the hang of all of this. :/ Please disregard my earlier submissions. After further testing I realised that the calls to cursor hide/unhide weren't balanced which broke the hide/unhide behaviour. I've added an additional static flag to track the cursor state so the cursor state is only updated where this would change the existing cursor state, ensuring the calls are now balanced. Having made the switch to an M1 Mac I needed to switch from VMware back to QEMU in order to run some intel guests. This patch addresses a couple of niggles with the cocoa UI, namely: - Using command-tab to switch between the guest OS and MacOS sends the command keypress to the guest which can be annoying e.g. on a windows guest this may trigger the start menu - Switching between the guest and MacOS sometimes leaves the MacOS mouse cursor visible with no way to hide it without switching windows again To address these issues I've made the following changes - Added a new cocoa display option left-command-key which can be used to disable the left command key in the guest. Default is on. - Added a call to hideCursor on left and right mouse clicks so if the cursor is visible after switching back to the guest a mouse click will hide the cursor again. - Also updated the command line docs to reference the show-cursor option which is also respected by the cocoa UI code. Carwyn Ellis (1): ui/cocoa: Add option to disable left command and hide cursor on click qapi/ui.json| 17 + qemu-options.hx | 12 ui/cocoa.m | 33 + 3 files changed, 54 insertions(+), 8 deletions(-) -- 2.34.1
Re: [PULL 00/20] Machine-next patches for 2021-12-31
On 12/31/21 18:07, Richard Henderson wrote: > On 12/31/21 4:47 AM, Philippe Mathieu-Daudé wrote: >> The following changes since commit >> 69f153667fce723ee546d2f047d66d0cfa67c3cc: >> >> Merge tag 'memory-api-20211231' ofhttps://github.com/philmd/qemu >> into staging (2021-12-30 17:02:42 -0800) >> >> are available in the Git repository at: >> >> https://github.com/philmd/qemu.git tags/machine-core-20211231 >> >> for you to fetch changes up to 2ece6e64846e1929c4ed338c73328d3b126e48d3: >> >> MAINTAINERS: email address change (2021-12-31 13:42:54 +0100) > > gpg: Signature made Fri 31 Dec 2021 04:45:35 AM PST > gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE > gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) > " [expired] > gpg: Note: This key has expired! > Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE > > Wanna push a refresh to your key? Oops =) Refreshed (pgp.mit.edu & keyserver.ubuntu.com). Thank you :)
Re: [PULL 00/20] Machine-next patches for 2021-12-31
On 12/31/21 4:47 AM, Philippe Mathieu-Daudé wrote: The following changes since commit 69f153667fce723ee546d2f047d66d0cfa67c3cc: Merge tag 'memory-api-20211231' ofhttps://github.com/philmd/qemu into staging (2021-12-30 17:02:42 -0800) are available in the Git repository at: https://github.com/philmd/qemu.git tags/machine-core-20211231 for you to fetch changes up to 2ece6e64846e1929c4ed338c73328d3b126e48d3: MAINTAINERS: email address change (2021-12-31 13:42:54 +0100) gpg: Signature made Fri 31 Dec 2021 04:45:35 AM PST gpg:using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) " [expired] gpg: Note: This key has expired! Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE Wanna push a refresh to your key? r~
[PATCH] target/arm: Add missing FEAT_TLBIOS instructions
Some of the instructions added by the FEAT_TLBIOS extension were forgotten
when the extension was originally added to QEMU.
Fixes: 7113d618505b ("target/arm: Add support for FEAT_TLBIOS")
Signed-off-by: Idan Horowitz
---
target/arm/helper.c | 32
1 file changed, 32 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index db837d53bd..cfca0f5ba6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6964,18 +6964,42 @@ static const ARMCPRegInfo tlbios_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
+{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
+{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
+ .access = PL1_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae1is_write },
+{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
+ .access = PL1_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae1is_write },
+{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
+ .access = PL1_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle2is_write },
+{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2is_write },
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
+{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2is_write },
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -6996,6 +7020,14 @@ static const ARMCPRegInfo tlbios_reginfo[] = {
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle3is_write },
+{ .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae3is_write },
+{ .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae3is_write },
REGINFO_SENTINEL
};
--
2.33.1
[PATCH 0/1] ui/cocoa: Add option to disable left command and hide cursor on click
Having made the switch to an M1 Mac I needed to switch from VMware back to QEMU in order to run some intel guests. This patch addresses a couple of niggles with the cocoa UI, namely: - Using command-tab to switch between the guest OS and MacOS sends the command keypress to the guest which can be annoying e.g. on a windows guest this may trigger the start menu - Switching between the guest and MacOS sometimes leaves the MacOS mouse cursor visible with no way to hide it without switching windows again To address these issues I've made the following changes - Added a new cocoa display option left-command-key which can be used to disable the left command key in the guest. Default is on. - Added a call to hideCursor on left and right mouse clicks so if the cursor is visible after switching back to the guest a mouse click will hide the cursor again. - Also updated the command line docs to reference the show-cursor option which is also respected by the cocoa UI code. Carwyn Ellis (1): ui/cocoa: Add option to disable left command and hide cursor on click qapi/ui.json| 17 + qemu-options.hx | 12 ui/cocoa.m | 16 ++-- 3 files changed, 43 insertions(+), 2 deletions(-) -- 2.34.1
[PATCH 1/1] ui/cocoa: Add option to disable left command and hide cursor on click
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
When switching between guest and host on a Mac with a fullscreen guest
the host pointer will occasionally persist despite the ui code
requesting that it be hidden. Added cursor hide calls on left and right
mouse click to hide the cursor when the mouse is clicked.
Also updated the cocoa display documentation to reference the new
left-command-key option along with the existing show-cursor option.
---
qapi/ui.json| 17 +
qemu-options.hx | 12
ui/cocoa.m | 16 ++--
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 2b4371da37..dd1569ed4b 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1107,6 +1107,22 @@
'data': { '*grab-on-hover' : 'bool',
'*zoom-to-fit' : 'bool' } }
+##
+# @DisplayCocoa:
+#
+# Cocoa display options.
+#
+# @left-command-key: Enable/disable forwarding of left command key to
+#guest. Allows command-tab window switching on the
+#host without sending this key to the guest when
+#"off". Defaults to "on"
+#
+# Since: 6.2.50
+#
+##
+{ 'struct' : 'DisplayCocoa',
+ 'data': { '*left-command-key' : 'bool' } }
+
##
# @DisplayEGLHeadless:
#
@@ -1254,6 +1270,7 @@
'discriminator' : 'type',
'data': {
'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
+ 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
'egl-headless': { 'type': 'DisplayEGLHeadless',
'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
diff --git a/qemu-options.hx b/qemu-options.hx
index 7d47510947..5214457676 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1869,6 +1869,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
#if defined(CONFIG_DBUS_DISPLAY)
"-display dbus[,addr=]\n"
" [,gl=on|core|es|off][,rendernode=]\n"
+#endif
+#if defined(CONFIG_COCOA)
+"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
#endif
"-display none\n"
"select display backend type\n"
@@ -1956,6 +1959,15 @@ SRST
``charset=CP850`` for IBM CP850 encoding. The default is
``CP437``.
+``cocoa``
+Display video output in a Cocoa window. Mac only. This interface
+provides drop-down menus and other UI elements to configure and
+control the VM during runtime. Valid parameters are:
+
+``show-cursor=on|off`` : Force showing the mouse cursor
+
+``left-command-key=on|off`` : Disable forwarding left command key to
host
+
``egl-headless[,rendernode=]``
Offload all OpenGL operations to a local DRI device. For any
graphical display, this display needs to be paired with either
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..105b742831 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -95,6 +95,7 @@ static DisplayChangeListener dcl = {
};
static int last_buttons;
static int cursor_hide = 1;
+static int left_command_key_enabled = 1;
static int gArgc;
static char **gArgv;
@@ -831,10 +832,14 @@ QemuCocoaView *cocoaView;
}
break;
-/* Don't pass command key changes to guest unless mouse is
grabbed */
+/*
+Don't pass command key changes to guest unless mouse is
grabbed
+or the key is explicitly disabled using the
left-command-key option
+*/
case kVK_Command:
if (isMouseGrabbed &&
-!!(modifiers & NSEventModifierFlagCommand)) {
+!!(modifiers & NSEventModifierFlagCommand) &&
+left_command_key_enabled) {
[self toggleKey:Q_KEY_CODE_META_L];
}
break;
@@ -923,10 +928,12 @@ QemuCocoaView *cocoaView;
case NSEventTypeLeftMouseDown:
buttons |= MOUSE_EVENT_LBUTTON;
mouse_event = true;
+[self hideCursor];
break;
case NSEventTypeRightMouseDown:
buttons |= MOUSE_EVENT_RBUTTON;
mouse_event = true;
+[self hideCursor];
break;
case NSEventTypeOtherMouseDown:
buttons |= MOUSE_EVENT_MBUTTON;
@@ -2050,10 +2057,15 @@ static void cocoa_display_init(DisplayState *ds,
DisplayOptions *opts)
[(QemuCocoaAppController *)[[NSApplication sharedApplication]
delegate] toggleFullScreen: nil];
});
}
+
if (opts->has_show_cursor && opts->show_cursor) {
cursor_hide = 0;
}
+if (opts->u.cocoa.has_left_
[PULL 16/20] tests/unit/test-smp-parse: No need to explicitly zero MachineClass members
From: Yanan Wang
The default value of the MachineClass members is 0, which
means we don't have to explicitly zero them. Also the value
of "mc->smp_props.prefer_sockets" will be taken care of by
smp_parse_test(), we don't necessarily need the statement
in machine_base_class_init() either.
Signed-off-by: Yanan Wang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211228092221.21068-6-wangyana...@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 331719bbc4b..72d83d1bbc9 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -523,8 +523,6 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc->smp_props.prefer_sockets = true;
-
mc->name = g_strdup(SMP_MACHINE_NAME);
}
@@ -534,9 +532,6 @@ static void machine_generic_valid_class_init(ObjectClass
*oc, void *data)
mc->min_cpus = MIN_CPUS;
mc->max_cpus = MAX_CPUS;
-
-mc->smp_props.dies_supported = false;
-mc->smp_props.clusters_supported = false;
}
static void machine_generic_invalid_class_init(ObjectClass *oc, void *data)
@@ -546,9 +541,6 @@ static void machine_generic_invalid_class_init(ObjectClass
*oc, void *data)
/* Force invalid min CPUs and max CPUs */
mc->min_cpus = 2;
mc->max_cpus = 511;
-
-mc->smp_props.dies_supported = false;
-mc->smp_props.clusters_supported = false;
}
static void machine_with_dies_class_init(ObjectClass *oc, void *data)
@@ -559,7 +551,6 @@ static void machine_with_dies_class_init(ObjectClass *oc,
void *data)
mc->max_cpus = MAX_CPUS;
mc->smp_props.dies_supported = true;
-mc->smp_props.clusters_supported = false;
}
static void machine_with_clusters_class_init(ObjectClass *oc, void *data)
@@ -570,7 +561,6 @@ static void machine_with_clusters_class_init(ObjectClass
*oc, void *data)
mc->max_cpus = MAX_CPUS;
mc->smp_props.clusters_supported = true;
-mc->smp_props.dies_supported = false;
}
static void test_generic_valid(const void *opaque)
--
2.33.1
[PULL 13/20] qemu-options: Improve readability of SMP related Docs
From: Yanan Wang
We have a description in qemu-options.hx for each CPU topology
parameter to explain what it exactly means, and also an extra
declaration for the target-specific one, e.g. "for PC only"
when describing "dies", and "for PC, it's on one die" when
describing "cores".
Now we are going to introduce one more non-generic parameter
"clusters", it will make the Doc less readable and if we still
continue to use the legacy way to describe it.
So let's at first make two tweaks of the Docs to improve the
readability and also scalability:
1) In the -help text: Delete the extra specific declaration and
describe each topology parameter level by level. Then add a
note to declare that different machines may support different
subsets and the actual meaning of the supported parameters
will vary accordingly.
2) In the rST text: List all the sub-hierarchies currently
supported in QEMU, and correspondingly give an example of
-smp configuration for each of them.
Signed-off-by: Yanan Wang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211228092221.21068-2-wangyana...@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé
---
qemu-options.hx | 74 ++---
1 file changed, 58 insertions(+), 16 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 7d475109478..b39377de3fc 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -207,14 +207,26 @@ ERST
DEF("smp", HAS_ARG, QEMU_OPTION_smp,
"-smp
[[cpus=]n][,maxcpus=maxcpus][,sockets=sockets][,dies=dies][,cores=cores][,threads=threads]\n"
-"set the number of CPUs to 'n' [default=1]\n"
+"set the number of initial CPUs to 'n' [default=1]\n"
"maxcpus= maximum number of total CPUs, including\n"
"offline CPUs for hotplug, etc\n"
-"sockets= number of discrete sockets in the system\n"
-"dies= number of CPU dies on one socket (for PC only)\n"
-"cores= number of CPU cores on one socket (for PC, it's on
one die)\n"
-"threads= number of threads on one CPU core\n",
-QEMU_ARCH_ALL)
+"sockets= number of sockets on the machine board\n"
+"dies= number of dies in one socket\n"
+"cores= number of cores in one die\n"
+"threads= number of threads in one core\n"
+"Note: Different machines may have different subsets of the CPU topology\n"
+" parameters supported, so the actual meaning of the supported
parameters\n"
+" will vary accordingly. For example, for a machine type that
supports a\n"
+" three-level CPU hierarchy of sockets/cores/threads, the parameters
will\n"
+" sequentially mean as below:\n"
+"sockets means the number of sockets on the machine
board\n"
+"cores means the number of cores in one socket\n"
+"threads means the number of threads in one core\n"
+" For a particular machine type board, an expected CPU topology
hierarchy\n"
+" can be defined through the supported sub-option. Unsupported
parameters\n"
+" can also be provided in addition to the sub-option, but their
values\n"
+" must be set as 1 in the purpose of correct parsing.\n",
+QEMU_ARCH_ALL)
SRST
``-smp
[[cpus=]n][,maxcpus=maxcpus][,sockets=sockets][,dies=dies][,cores=cores][,threads=threads]``
Simulate a SMP system with '\ ``n``\ ' CPUs initially present on
@@ -225,27 +237,57 @@ SRST
initial CPU count will match the maximum number. When only one of them
is given then the omitted one will be set to its counterpart's value.
Both parameters may be specified, but the maximum number of CPUs must
-be equal to or greater than the initial CPU count. Both parameters are
-subject to an upper limit that is determined by the specific machine
-type chosen.
+be equal to or greater than the initial CPU count. Product of the
+CPU topology hierarchy must be equal to the maximum number of CPUs.
+Both parameters are subject to an upper limit that is determined by
+the specific machine type chosen.
-To control reporting of CPU topology information, the number of sockets,
-dies per socket, cores per die, and threads per core can be specified.
-The sum `` sockets * cores * dies * threads `` must be equal to the
-maximum CPU count. CPU targets may only support a subset of the topology
-parameters. Where a CPU target does not support use of a particular
-topology parameter, its value should be assumed to be 1 for the purpose
-of computing the CPU maximum count.
+To control reporting of CPU topology information, values of the topology
+parameters can be specified. Machines may only support a subset of the
+parameters and different machines may have different subsets supported
+
[PULL 20/20] MAINTAINERS: email address change
From: Li Zhijian Fujitsu's mail service has migrated to O365 months ago, the lizhij...@cn.fujitsu.com address will stop working on 2022-06-01, change it to my new email address lizhij...@fujitsu.com. Signed-off-by: Li Zhijian Acked-by: Zhang Chen Message-Id: <20211231050901.360-1-lizhij...@cn.fujitsu.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index ae6c74f3ff5..f871d759fdf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2982,7 +2982,7 @@ F: docs/COLO-FT.txt COLO Proxy M: Zhang Chen -M: Li Zhijian +M: Li Zhijian S: Supported F: docs/colo-proxy.txt F: net/colo* -- 2.33.1
[PULL 14/20] hw/core/machine: Introduce CPU cluster topology support
From: Yanan Wang
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit the scheduling performance (e.g.
load balance and wake_affine strategy) on both x86_64 and AArch64.
So now in Linux 5.16 we have four-level arch-neutral CPU topology
definition like below and a new scheduler level for clusters.
struct cpu_topology {
int thread_id;
int core_id;
int cluster_id;
int package_id;
int llc_id;
cpumask_t thread_sibling;
cpumask_t core_sibling;
cpumask_t cluster_sibling;
cpumask_t llc_sibling;
}
A cluster generally means a group of CPU cores which share L2 cache
or other mid-level resources, and it is the shared resources that
is used to improve scheduler's behavior. From the point of view of
the size range, it's between CPU die and CPU core. For example, on
some ARM64 Kunpeng servers, we have 6 clusters in each NUMA node,
and 4 CPU cores in each cluster. The 4 CPU cores share a separate
L2 cache and a L3 cache tag, which brings cache affinity advantage.
In virtualization, on the Hosts which have pClusters (physical
clusters), if we can design a vCPU topology with cluster level for
guest kernel and have a dedicated vCPU pinning. A Cluster-Aware
Guest kernel can also make use of the cache affinity of CPU clusters
to gain similar scheduling performance.
This patch adds infrastructure for CPU cluster level topology
configuration and parsing, so that the user can specify cluster
parameter if their machines support it.
Signed-off-by: Yanan Wang
Message-Id: <20211228092221.21068-3-wangyana...@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé
[PMD: Added '(since 7.0)' to @clusters in qapi/machine.json]
Signed-off-by: Philippe Mathieu-Daudé
---
qapi/machine.json | 5 -
include/hw/boards.h | 6 +-
hw/core/machine-smp.c | 26 +++---
hw/core/machine.c | 3 +++
softmmu/vl.c | 3 +++
qemu-options.hx | 7 ---
6 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index edeab6084b7..372535b3482 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1404,7 +1404,9 @@
#
# @dies: number of dies per socket in the CPU topology
#
-# @cores: number of cores per die in the CPU topology
+# @clusters: number of clusters per die in the CPU topology (since 7.0)
+#
+# @cores: number of cores per cluster in the CPU topology
#
# @threads: number of threads per core in the CPU topology
#
@@ -1416,6 +1418,7 @@
'*cpus': 'int',
'*sockets': 'int',
'*dies': 'int',
+ '*clusters': 'int',
'*cores': 'int',
'*threads': 'int',
'*maxcpus': 'int' } }
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 7597cec4400..f49a2578ead 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -129,10 +129,12 @@ typedef struct {
* SMPCompatProps:
* @prefer_sockets - whether sockets are preferred over cores in smp parsing
* @dies_supported - whether dies are supported by the machine
+ * @clusters_supported - whether clusters are supported by the machine
*/
typedef struct {
bool prefer_sockets;
bool dies_supported;
+bool clusters_supported;
} SMPCompatProps;
/**
@@ -299,7 +301,8 @@ typedef struct DeviceMemoryState {
* @cpus: the number of present logical processors on the machine
* @sockets: the number of sockets on the machine
* @dies: the number of dies in one socket
- * @cores: the number of cores in one die
+ * @clusters: the number of clusters in one die
+ * @cores: the number of cores in one cluster
* @threads: the number of threads in one core
* @max_cpus: the maximum number of logical processors on the machine
*/
@@ -307,6 +310,7 @@ typedef struct CpuTopology {
unsigned int cpus;
unsigned int sockets;
unsigned int dies;
+unsigned int clusters;
unsigned int cores;
unsigned int threads;
unsigned int max_cpus;
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 2cbfd574293..b39ed21e654 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -37,6 +37,10 @@ static char *cpu_hierarchy_to_string(MachineState *ms)
g_string_append_printf(s, " * dies (%u)", ms->smp.dies);
}
+if (mc->smp_props.clusters_supported) {
+g_string_append_printf(s, " * clusters (%u)", ms->smp.clusters);
+}
+
g_string_append_printf(s, " * cores (%u)", ms->smp.cores);
g_string_append_printf(s, " * threads (%u)", ms->smp.threads);
@@ -71,6 +75,7 @@ void machine_parse_smp_config(MachineState *ms,
unsigned cpus= config->has_cpus ? config->cpus : 0;
unsigned sockets = config->has_sockets ? config->sockets : 0;
unsigned dies= config->has_dies ? config->dies : 0;
+unsigned clusters = config->has_clusters ? config->clusters : 0;
unsigned cores = config->has_cores ? config->cores : 0;
unsigned threads = config->has_threads ? config->threads : 0;
unsigned maxcpus =
[PULL 12/20] hw/core: Rename smp_parse() -> machine_parse_smp_config()
All methods related to MachineState are prefixed with "machine_".
smp_parse() does not need to be an exception. Rename it and
const'ify the SMPConfiguration argument, since it doesn't need
to be modified.
Reviewed-by: Andrew Jones
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Tested-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-9-phi...@redhat.com>
---
include/hw/boards.h | 3 ++-
hw/core/machine-smp.c | 6 --
hw/core/machine.c | 2 +-
tests/unit/test-smp-parse.c | 8
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 9c1c1901046..7597cec4400 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -34,7 +34,8 @@ HotpluggableCPUList
*machine_query_hotpluggable_cpus(MachineState *machine);
void machine_set_cpu_numa_node(MachineState *machine,
const CpuInstanceProperties *props,
Error **errp);
-void smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp);
+void machine_parse_smp_config(MachineState *ms,
+ const SMPConfiguration *config, Error **errp);
/**
* machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 116a0cbbfab..2cbfd574293 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -44,7 +44,8 @@ static char *cpu_hierarchy_to_string(MachineState *ms)
}
/*
- * smp_parse - Generic function used to parse the given SMP configuration
+ * machine_parse_smp_config: Generic function used to parse the given
+ * SMP configuration
*
* Any missing parameter in "cpus/maxcpus/sockets/cores/threads" will be
* automatically computed based on the provided ones.
@@ -63,7 +64,8 @@ static char *cpu_hierarchy_to_string(MachineState *ms)
* introduced topology members which are likely to be target specific should
* be directly set as 1 if they are omitted (e.g. dies for PC since 4.1).
*/
-void smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp)
+void machine_parse_smp_config(MachineState *ms,
+ const SMPConfiguration *config, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
unsigned cpus= config->has_cpus ? config->cpus : 0;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 53a99abc560..3993c534b90 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -761,7 +761,7 @@ static void machine_set_smp(Object *obj, Visitor *v, const
char *name,
return;
}
-smp_parse(ms, config, errp);
+machine_parse_smp_config(ms, config, errp);
}
static void machine_class_init(ObjectClass *oc, void *data)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 0f98c9509ee..b6df8137fcc 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -337,7 +337,7 @@ static const struct SMPTestData data_with_dies_invalid[] = {
},
};
-static char *smp_config_to_string(SMPConfiguration *config)
+static char *smp_config_to_string(const SMPConfiguration *config)
{
return g_strdup_printf(
"(SMPConfiguration) {\n"
@@ -371,7 +371,7 @@ static char *cpu_topology_to_string(const CpuTopology *topo)
topo->cores, topo->threads, topo->max_cpus);
}
-static void check_parse(MachineState *ms, SMPConfiguration *config,
+static void check_parse(MachineState *ms, const SMPConfiguration *config,
const CpuTopology *expect_topo, const char *expect_err,
bool is_valid)
{
@@ -380,8 +380,8 @@ static void check_parse(MachineState *ms, SMPConfiguration
*config,
g_autofree char *output_topo_str = NULL;
Error *err = NULL;
-/* call the generic parser smp_parse() */
-smp_parse(ms, config, &err);
+/* call the generic parser */
+machine_parse_smp_config(ms, config, &err);
output_topo_str = cpu_topology_to_string(&ms->smp);
--
2.33.1
[PULL 09/20] tests/unit/test-smp-parse: Add 'smp-generic-valid' machine type
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new class: "smp-generic-valid".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Yanan Wang
Message-Id: <20211216132015.815493-6-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 47e11089e22..b20bf2c2359 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -478,13 +478,19 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+mc->smp_props.prefer_sockets = true;
+
+mc->name = g_strdup(SMP_MACHINE_NAME);
+}
+
+static void machine_generic_valid_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+
mc->min_cpus = MIN_CPUS;
mc->max_cpus = MAX_CPUS;
-mc->smp_props.prefer_sockets = true;
mc->smp_props.dies_supported = false;
-
-mc->name = g_strdup(SMP_MACHINE_NAME);
}
static void machine_generic_invalid_class_init(ObjectClass *oc, void *data)
@@ -606,9 +612,14 @@ static const TypeInfo smp_machine_types[] = {
{
.name = TYPE_MACHINE,
.parent = TYPE_OBJECT,
+.abstract = true,
.class_init = machine_base_class_init,
.class_size = sizeof(MachineClass),
.instance_size = sizeof(MachineState),
+}, {
+.name = MACHINE_TYPE_NAME("smp-generic-valid"),
+.parent = TYPE_MACHINE,
+.class_init = machine_generic_valid_class_init,
}, {
.name = MACHINE_TYPE_NAME("smp-generic-invalid"),
.parent = TYPE_MACHINE,
@@ -629,7 +640,7 @@ int main(int argc, char *argv[])
g_test_init(&argc, &argv, NULL);
g_test_add_data_func("/test-smp-parse/generic/valid",
- TYPE_MACHINE,
+ MACHINE_TYPE_NAME("smp-generic-valid"),
test_generic_valid);
g_test_add_data_func("/test-smp-parse/generic/invalid",
MACHINE_TYPE_NAME("smp-generic-invalid"),
--
2.33.1
[PULL 11/20] tests/unit/test-smp-parse: Constify some pointer/struct
Declare structures const when we don't need to modify
them at runtime.
Reviewed-by: Andrew Jones
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Tested-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-8-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 395929b66cf..0f98c9509ee 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -83,7 +83,7 @@ typedef struct SMPTestData {
* then test the automatic calculation algorithm of the missing
* values in the parser.
*/
-static struct SMPTestData data_generic_valid[] = {
+static const struct SMPTestData data_generic_valid[] = {
{
/* config: no configuration provided
* expect: cpus=1,sockets=1,cores=1,threads=1,maxcpus=1 */
@@ -285,7 +285,7 @@ static struct SMPTestData data_generic_valid[] = {
},
};
-static struct SMPTestData data_generic_invalid[] = {
+static const struct SMPTestData data_generic_invalid[] = {
{
/* config: -smp 2,dies=2 */
.config = SMP_CONFIG_WITH_DIES(T, 2, F, 0, T, 2, F, 0, F, 0, F, 0),
@@ -319,7 +319,7 @@ static struct SMPTestData data_generic_invalid[] = {
},
};
-static struct SMPTestData data_with_dies_invalid[] = {
+static const struct SMPTestData data_with_dies_invalid[] = {
{
/* config: -smp 16,sockets=2,dies=2,cores=4,threads=2,maxcpus=16 */
.config = SMP_CONFIG_WITH_DIES(T, 16, T, 2, T, 2, T, 4, T, 2, T, 16),
@@ -356,7 +356,7 @@ static char *smp_config_to_string(SMPConfiguration *config)
config->has_maxcpus ? "true" : "false", config->maxcpus);
}
-static char *cpu_topology_to_string(CpuTopology *topo)
+static char *cpu_topology_to_string(const CpuTopology *topo)
{
return g_strdup_printf(
"(CpuTopology) {\n"
@@ -372,7 +372,7 @@ static char *cpu_topology_to_string(CpuTopology *topo)
}
static void check_parse(MachineState *ms, SMPConfiguration *config,
-CpuTopology *expect_topo, const char *expect_err,
+const CpuTopology *expect_topo, const char *expect_err,
bool is_valid)
{
g_autofree char *config_str = smp_config_to_string(config);
@@ -466,7 +466,7 @@ static void smp_parse_test(MachineState *ms, SMPTestData
*data, bool is_valid)
}
/* The parsed results of the unsupported parameters should be 1 */
-static void unsupported_params_init(MachineClass *mc, SMPTestData *data)
+static void unsupported_params_init(const MachineClass *mc, SMPTestData *data)
{
if (!mc->smp_props.dies_supported) {
data->expect_prefer_sockets.dies = 1;
--
2.33.1
[PULL 07/20] tests/unit/test-smp-parse: Add 'smp-with-dies' machine type
Avoid modifying the MachineClass internals by adding the
'smp-with-dies' machine, which inherits from TYPE_MACHINE.
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Tested-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-4-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 425ed6b6b92..f66cf7bb598 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -487,6 +487,16 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
mc->name = g_strdup(SMP_MACHINE_NAME);
}
+static void machine_with_dies_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+
+mc->min_cpus = MIN_CPUS;
+mc->max_cpus = MAX_CPUS;
+
+mc->smp_props.dies_supported = true;
+}
+
static void test_generic_valid(const void *opaque)
{
const char *machine_type = opaque;
@@ -548,9 +558,6 @@ static void test_with_dies(const void *opaque)
unsigned int num_dies = 2;
int i;
-/* Force the SMP compat properties */
-mc->smp_props.dies_supported = true;
-
for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
*data = data_generic_valid[i];
unsupported_params_init(mc, data);
@@ -588,9 +595,6 @@ static void test_with_dies(const void *opaque)
smp_parse_test(ms, data, false);
}
-/* Restore the SMP compat properties */
-mc->smp_props.dies_supported = false;
-
object_unref(obj);
}
@@ -602,6 +606,10 @@ static const TypeInfo smp_machine_types[] = {
.class_init = machine_base_class_init,
.class_size = sizeof(MachineClass),
.instance_size = sizeof(MachineState),
+}, {
+.name = MACHINE_TYPE_NAME("smp-with-dies"),
+.parent = TYPE_MACHINE,
+.class_init = machine_with_dies_class_init,
}
};
@@ -620,7 +628,7 @@ int main(int argc, char *argv[])
TYPE_MACHINE,
test_generic_invalid);
g_test_add_data_func("/test-smp-parse/with_dies",
- TYPE_MACHINE,
+ MACHINE_TYPE_NAME("smp-with-dies"),
test_with_dies);
g_test_run();
--
2.33.1
[PULL 18/20] MAINTAINERS: Self-recommended as reviewer of "Machine core"
From: Yanan Wang I've built interests in the generic machine subsystem and have also been working on projects related to this part, self-recommand myself as a reviewer so that I can help to review some patches familiar to me, and have a chance to learn more continuously. Signed-off-by: Yanan Wang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211228092221.21068-8-wangyana...@huawei.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 54565368054..fe5eea76f67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1631,6 +1631,7 @@ Machine core M: Eduardo Habkost M: Marcel Apfelbaum R: Philippe Mathieu-Daudé +R: Yanan Wang S: Supported F: cpu.c F: hw/core/cpu.c -- 2.33.1
[PULL 08/20] tests/unit/test-smp-parse: Add 'smp-generic-invalid' machine type
Avoid modifying the MachineClass internals by adding the
'smp-generic-invalid' machine, which inherits from TYPE_MACHINE.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Yanan Wang
Message-Id: <20211216132015.815493-5-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index f66cf7bb598..47e11089e22 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -487,6 +487,17 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
mc->name = g_strdup(SMP_MACHINE_NAME);
}
+static void machine_generic_invalid_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+
+/* Force invalid min CPUs and max CPUs */
+mc->min_cpus = 2;
+mc->max_cpus = 511;
+
+mc->smp_props.dies_supported = false;
+}
+
static void machine_with_dies_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -530,10 +541,6 @@ static void test_generic_invalid(const void *opaque)
SMPTestData *data = &(SMPTestData){};
int i;
-/* Force invalid min CPUs and max CPUs */
-mc->min_cpus = 2;
-mc->max_cpus = 511;
-
for (i = 0; i < ARRAY_SIZE(data_generic_invalid); i++) {
*data = data_generic_invalid[i];
unsupported_params_init(mc, data);
@@ -541,10 +548,6 @@ static void test_generic_invalid(const void *opaque)
smp_parse_test(ms, data, false);
}
-/* Reset the supported min CPUs and max CPUs */
-mc->min_cpus = MIN_CPUS;
-mc->max_cpus = MAX_CPUS;
-
object_unref(obj);
}
@@ -606,6 +609,10 @@ static const TypeInfo smp_machine_types[] = {
.class_init = machine_base_class_init,
.class_size = sizeof(MachineClass),
.instance_size = sizeof(MachineState),
+}, {
+.name = MACHINE_TYPE_NAME("smp-generic-invalid"),
+.parent = TYPE_MACHINE,
+.class_init = machine_generic_invalid_class_init,
}, {
.name = MACHINE_TYPE_NAME("smp-with-dies"),
.parent = TYPE_MACHINE,
@@ -625,7 +632,7 @@ int main(int argc, char *argv[])
TYPE_MACHINE,
test_generic_valid);
g_test_add_data_func("/test-smp-parse/generic/invalid",
- TYPE_MACHINE,
+ MACHINE_TYPE_NAME("smp-generic-invalid"),
test_generic_invalid);
g_test_add_data_func("/test-smp-parse/with_dies",
MACHINE_TYPE_NAME("smp-with-dies"),
--
2.33.1
[PULL 19/20] MAINTAINERS: Change philmd's email address
The phi...@redhat.com email address will stop working on 2022-01-01, change it to my personal email address. Update .mailmap in case anyone wants to send me an email because of some past commit I authored. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211231000759.707519-1-phi...@redhat.com> --- .gitlab-ci.d/edk2/Dockerfile | 2 +- .mailmap | 1 + MAINTAINERS | 18 +- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/.gitlab-ci.d/edk2/Dockerfile b/.gitlab-ci.d/edk2/Dockerfile index b4584d1cf64..13029310f6d 100644 --- a/.gitlab-ci.d/edk2/Dockerfile +++ b/.gitlab-ci.d/edk2/Dockerfile @@ -3,7 +3,7 @@ # FROM ubuntu:16.04 -MAINTAINER Philippe Mathieu-Daudé +MAINTAINER Philippe Mathieu-Daudé # Install packages required to build EDK2 RUN apt update \ diff --git a/.mailmap b/.mailmap index c45d1c53014..5113f55b3a0 100644 --- a/.mailmap +++ b/.mailmap @@ -63,6 +63,7 @@ Paul Burton Paul Burton Paul Burton Paul Burton +Philippe Mathieu-Daudé Stefan Brankovic Yongbok Kim diff --git a/MAINTAINERS b/MAINTAINERS index fe5eea76f67..ae6c74f3ff5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1630,7 +1630,7 @@ F: pc-bios/bios-microvm.bin Machine core M: Eduardo Habkost M: Marcel Apfelbaum -R: Philippe Mathieu-Daudé +R: Philippe Mathieu-Daudé R: Yanan Wang S: Supported F: cpu.c @@ -1811,7 +1811,7 @@ F: docs/virtio-net-failover.rst T: git https://github.com/jasowang/qemu.git net Parallel NOR Flash devices -M: Philippe Mathieu-Daudé +M: Philippe Mathieu-Daudé T: git https://gitlab.com/philmd/qemu.git pflash-next S: Maintained F: hw/block/pflash_cfi*.c @@ -2227,7 +2227,7 @@ F: hw/isa/piix4.c F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) -M: Philippe Mathieu-Daudé +M: Philippe Mathieu-Daudé R: Gerd Hoffmann S: Supported F: docs/specs/fw_cfg.txt @@ -2525,7 +2525,7 @@ F: scripts/coccinelle/errp-guard.cocci GDB stub M: Alex Bennée -R: Philippe Mathieu-Daudé +R: Philippe Mathieu-Daudé S: Maintained F: gdbstub* F: include/exec/gdbstub.h @@ -2536,7 +2536,7 @@ Memory API M: Paolo Bonzini M: Peter Xu M: David Hildenbrand -R: Philippe Mathieu-Daudé +R: Philippe Mathieu-Daudé S: Supported F: include/exec/ioport.h F: include/exec/memop.h @@ -3030,14 +3030,14 @@ F: include/hw/i2c/smbus_slave.h F: include/hw/i2c/smbus_eeprom.h Firmware schema specifications -M: Philippe Mathieu-Daudé +M: Philippe Mathieu-Daudé R: Daniel P. Berrange R: Kashyap Chamarthy S: Maintained F: docs/interop/firmware.json EDK2 Firmware -M: Philippe Mathieu-Daudé +M: Philippe Mathieu-Daudé R: Gerd Hoffmann S: Supported F: hw/i386/*ovmf* @@ -3275,7 +3275,7 @@ F: block/null.c NVMe Block Driver M: Stefan Hajnoczi R: Fam Zheng -R: Philippe Mathieu-Daudé +R: Philippe Mathieu-Daudé L: qemu-bl...@nongnu.org S: Supported F: block/nvme* @@ -3518,7 +3518,7 @@ F: tests/tcg/Makefile.include Integration Testing with the Avocado framework W: https://trello.com/b/6Qi1pxVn/avocado-qemu R: Cleber Rosa -R: Philippe Mathieu-Daudé +R: Philippe Mathieu-Daudé R: Wainer dos Santos Moschetta R: Beraldo Leal S: Odd Fixes -- 2.33.1
[PULL 06/20] tests/unit/test-smp-parse: Split the 'generic' test in valid / invalid
Split the 'generic' test in two tests: 'valid' and 'invalid'.
This will allow us to remove the hack which modifies the
MachineClass internal state.
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-3-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 37c6b4981db..425ed6b6b92 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -487,7 +487,7 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
mc->name = g_strdup(SMP_MACHINE_NAME);
}
-static void test_generic(const void *opaque)
+static void test_generic_valid(const void *opaque)
{
const char *machine_type = opaque;
Object *obj = object_new(machine_type);
@@ -508,6 +508,18 @@ static void test_generic(const void *opaque)
smp_parse_test(ms, data, true);
}
+object_unref(obj);
+}
+
+static void test_generic_invalid(const void *opaque)
+{
+const char *machine_type = opaque;
+Object *obj = object_new(machine_type);
+MachineState *ms = MACHINE(obj);
+MachineClass *mc = MACHINE_GET_CLASS(obj);
+SMPTestData *data = &(SMPTestData){};
+int i;
+
/* Force invalid min CPUs and max CPUs */
mc->min_cpus = 2;
mc->max_cpus = 511;
@@ -601,9 +613,12 @@ int main(int argc, char *argv[])
g_test_init(&argc, &argv, NULL);
-g_test_add_data_func("/test-smp-parse/generic",
+g_test_add_data_func("/test-smp-parse/generic/valid",
TYPE_MACHINE,
- test_generic);
+ test_generic_valid);
+g_test_add_data_func("/test-smp-parse/generic/invalid",
+ TYPE_MACHINE,
+ test_generic_invalid);
g_test_add_data_func("/test-smp-parse/with_dies",
TYPE_MACHINE,
test_with_dies);
--
2.33.1
[PULL 17/20] tests/unit/test-smp-parse: Keep default MIN/MAX CPUs in machine_base_class_init
From: Yanan Wang
Most machine types in test-smp-parse will be OK to have the default
MIN/MAX CPUs except "smp-generic-invalid", let's keep the default
values in machine_base_class_init which will be inherited. And if
we hope a different value for a specific machine, modify it in its
own initialization function.
Signed-off-by: Yanan Wang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211228092221.21068-7-wangyana...@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 72d83d1bbc9..fdc39a846ca 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -523,15 +523,10 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc->name = g_strdup(SMP_MACHINE_NAME);
-}
-
-static void machine_generic_valid_class_init(ObjectClass *oc, void *data)
-{
-MachineClass *mc = MACHINE_CLASS(oc);
-
mc->min_cpus = MIN_CPUS;
mc->max_cpus = MAX_CPUS;
+
+mc->name = g_strdup(SMP_MACHINE_NAME);
}
static void machine_generic_invalid_class_init(ObjectClass *oc, void *data)
@@ -547,9 +542,6 @@ static void machine_with_dies_class_init(ObjectClass *oc,
void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc->min_cpus = MIN_CPUS;
-mc->max_cpus = MAX_CPUS;
-
mc->smp_props.dies_supported = true;
}
@@ -557,9 +549,6 @@ static void machine_with_clusters_class_init(ObjectClass
*oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc->min_cpus = MIN_CPUS;
-mc->max_cpus = MAX_CPUS;
-
mc->smp_props.clusters_supported = true;
}
@@ -718,7 +707,6 @@ static const TypeInfo smp_machine_types[] = {
}, {
.name = MACHINE_TYPE_NAME("smp-generic-valid"),
.parent = TYPE_MACHINE,
-.class_init = machine_generic_valid_class_init,
}, {
.name = MACHINE_TYPE_NAME("smp-generic-invalid"),
.parent = TYPE_MACHINE,
--
2.33.1
[PULL 10/20] tests/unit/test-smp-parse: Simplify pointer to compound literal use
We can simply use a local variable (and pass its pointer) instead
of a pointer to a compound literal.
Reviewed-by: Andrew Jones
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Tested-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-7-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 66 ++---
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index b20bf2c2359..395929b66cf 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -520,19 +520,19 @@ static void test_generic_valid(const void *opaque)
Object *obj = object_new(machine_type);
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
-SMPTestData *data = &(SMPTestData){{ }};
+SMPTestData data = {};
int i;
for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
-*data = data_generic_valid[i];
-unsupported_params_init(mc, data);
+data = data_generic_valid[i];
+unsupported_params_init(mc, &data);
-smp_parse_test(ms, data, true);
+smp_parse_test(ms, &data, true);
/* Unsupported parameters can be provided with their values as 1 */
-data->config.has_dies = true;
-data->config.dies = 1;
-smp_parse_test(ms, data, true);
+data.config.has_dies = true;
+data.config.dies = 1;
+smp_parse_test(ms, &data, true);
}
object_unref(obj);
@@ -544,14 +544,14 @@ static void test_generic_invalid(const void *opaque)
Object *obj = object_new(machine_type);
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
-SMPTestData *data = &(SMPTestData){};
+SMPTestData data = {};
int i;
for (i = 0; i < ARRAY_SIZE(data_generic_invalid); i++) {
-*data = data_generic_invalid[i];
-unsupported_params_init(mc, data);
+data = data_generic_invalid[i];
+unsupported_params_init(mc, &data);
-smp_parse_test(ms, data, false);
+smp_parse_test(ms, &data, false);
}
object_unref(obj);
@@ -563,45 +563,45 @@ static void test_with_dies(const void *opaque)
Object *obj = object_new(machine_type);
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
-SMPTestData *data = &(SMPTestData){{ }};
+SMPTestData data = {};
unsigned int num_dies = 2;
int i;
for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
-*data = data_generic_valid[i];
-unsupported_params_init(mc, data);
+data = data_generic_valid[i];
+unsupported_params_init(mc, &data);
/* when dies parameter is omitted, it will be set as 1 */
-data->expect_prefer_sockets.dies = 1;
-data->expect_prefer_cores.dies = 1;
+data.expect_prefer_sockets.dies = 1;
+data.expect_prefer_cores.dies = 1;
-smp_parse_test(ms, data, true);
+smp_parse_test(ms, &data, true);
/* when dies parameter is specified */
-data->config.has_dies = true;
-data->config.dies = num_dies;
-if (data->config.has_cpus) {
-data->config.cpus *= num_dies;
+data.config.has_dies = true;
+data.config.dies = num_dies;
+if (data.config.has_cpus) {
+data.config.cpus *= num_dies;
}
-if (data->config.has_maxcpus) {
-data->config.maxcpus *= num_dies;
+if (data.config.has_maxcpus) {
+data.config.maxcpus *= num_dies;
}
-data->expect_prefer_sockets.dies = num_dies;
-data->expect_prefer_sockets.cpus *= num_dies;
-data->expect_prefer_sockets.max_cpus *= num_dies;
-data->expect_prefer_cores.dies = num_dies;
-data->expect_prefer_cores.cpus *= num_dies;
-data->expect_prefer_cores.max_cpus *= num_dies;
+data.expect_prefer_sockets.dies = num_dies;
+data.expect_prefer_sockets.cpus *= num_dies;
+data.expect_prefer_sockets.max_cpus *= num_dies;
+data.expect_prefer_cores.dies = num_dies;
+data.expect_prefer_cores.cpus *= num_dies;
+data.expect_prefer_cores.max_cpus *= num_dies;
-smp_parse_test(ms, data, true);
+smp_parse_test(ms, &data, true);
}
for (i = 0; i < ARRAY_SIZE(data_with_dies_invalid); i++) {
-*data = data_with_dies_invalid[i];
-unsupported_params_init(mc, data);
+data = data_with_dies_invalid[i];
+unsupported_params_init(mc, &data);
-smp_parse_test(ms, data, false);
+smp_parse_test(ms, &data, false);
}
object_unref(obj);
--
2.33.1
[PULL 04/20] hw/qdev: Rename qdev_connect_gpio_out*() 'input_pin' parameter
From: Philippe Mathieu-Daudé
@pin is an input where we connect a device output.
Rename it @input_pin to simplify the documentation.
Reviewed-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211218130437.1516929-5-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 6 +++---
hw/core/gpio.c | 13 +++--
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 424c48daf6e..d19c9417520 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -476,7 +476,7 @@ qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const
char *name, int n);
* qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
* @dev: Device whose GPIO to connect
* @n: Number of the anonymous output GPIO line (which must be in range)
- * @pin: qemu_irq to connect the output line to
+ * @input_pin: qemu_irq to connect the output line to
*
* This function connects an anonymous output GPIO line on a device
* up to an arbitrary qemu_irq, so that when the device asserts that
@@ -509,7 +509,7 @@ void qdev_connect_gpio_out(DeviceState *dev, int n,
qemu_irq pin);
* @dev: Device whose GPIO to connect
* @name: Name of the output GPIO array
* @n: Number of the anonymous output GPIO line (which must be in range)
- * @pin: qemu_irq to connect the output line to
+ * @input_pin: qemu_irq to connect the output line to
*
* This function connects an anonymous output GPIO line on a device
* up to an arbitrary qemu_irq, so that when the device asserts that
@@ -530,7 +530,7 @@ void qdev_connect_gpio_out(DeviceState *dev, int n,
qemu_irq pin);
* For anonymous output GPIO lines, use qdev_connect_gpio_out().
*/
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
- qemu_irq pin);
+ qemu_irq input_pin);
/**
* qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
diff --git a/hw/core/gpio.c b/hw/core/gpio.c
index 8e6b4f5edf3..80d07a6ec99 100644
--- a/hw/core/gpio.c
+++ b/hw/core/gpio.c
@@ -115,17 +115,18 @@ qemu_irq qdev_get_gpio_in(DeviceState *dev, int n)
}
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
- qemu_irq pin)
+ qemu_irq input_pin)
{
char *propname = g_strdup_printf("%s[%d]",
name ? name : "unnamed-gpio-out", n);
-if (pin && !OBJECT(pin)->parent) {
+if (input_pin && !OBJECT(input_pin)->parent) {
/* We need a name for object_property_set_link to work */
object_property_add_child(container_get(qdev_get_machine(),
"/unattached"),
- "non-qdev-gpio[*]", OBJECT(pin));
+ "non-qdev-gpio[*]", OBJECT(input_pin));
}
-object_property_set_link(OBJECT(dev), propname, OBJECT(pin), &error_abort);
+object_property_set_link(OBJECT(dev), propname,
+ OBJECT(input_pin), &error_abort);
g_free(propname);
}
@@ -165,9 +166,9 @@ qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq
icpt,
return disconnected;
}
-void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin)
+void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq input_pin)
{
-qdev_connect_gpio_out_named(dev, NULL, n, pin);
+qdev_connect_gpio_out_named(dev, NULL, n, input_pin);
}
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
--
2.33.1
[PULL 05/20] tests/unit/test-smp-parse: Pass machine type as argument to tests
Use g_test_add_data_func() instead of g_test_add_func() so we can
pass the machine type to the tests (we will soon have different
machine types).
Reviewed-by: Richard Henderson
Reviewed-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211216132015.815493-2-phi...@redhat.com>
---
tests/unit/test-smp-parse.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index b02450e25a3..37c6b4981db 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -487,9 +487,10 @@ static void machine_base_class_init(ObjectClass *oc, void
*data)
mc->name = g_strdup(SMP_MACHINE_NAME);
}
-static void test_generic(void)
+static void test_generic(const void *opaque)
{
-Object *obj = object_new(TYPE_MACHINE);
+const char *machine_type = opaque;
+Object *obj = object_new(machine_type);
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
SMPTestData *data = &(SMPTestData){{ }};
@@ -525,9 +526,10 @@ static void test_generic(void)
object_unref(obj);
}
-static void test_with_dies(void)
+static void test_with_dies(const void *opaque)
{
-Object *obj = object_new(TYPE_MACHINE);
+const char *machine_type = opaque;
+Object *obj = object_new(machine_type);
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
SMPTestData *data = &(SMPTestData){{ }};
@@ -599,8 +601,12 @@ int main(int argc, char *argv[])
g_test_init(&argc, &argv, NULL);
-g_test_add_func("/test-smp-parse/generic", test_generic);
-g_test_add_func("/test-smp-parse/with_dies", test_with_dies);
+g_test_add_data_func("/test-smp-parse/generic",
+ TYPE_MACHINE,
+ test_generic);
+g_test_add_data_func("/test-smp-parse/with_dies",
+ TYPE_MACHINE,
+ test_with_dies);
g_test_run();
--
2.33.1
[PULL 15/20] tests/unit/test-smp-parse: Add testcases for CPU clusters
From: Yanan Wang
Add testcases for parsing of the four-level CPU topology hierarchy,
ie sockets/clusters/cores/threads, which will be supported on ARM
virt machines.
Signed-off-by: Yanan Wang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211228092221.21068-5-wangyana...@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 130 ++--
1 file changed, 123 insertions(+), 7 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index b6df8137fcc..331719bbc4b 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -61,6 +61,20 @@
.has_maxcpus = hf, .maxcpus = f, \
}
+/*
+ * Currently a 4-level topology hierarchy is supported on ARM virt machines
+ * -sockets/clusters/cores/threads
+ */
+#define SMP_CONFIG_WITH_CLUSTERS(ha, a, hb, b, hc, c, hd, d, he, e, hf, f) \
+{ \
+.has_cpus = ha, .cpus = a,\
+.has_sockets = hb, .sockets = b,\
+.has_clusters = hc, .clusters = c,\
+.has_cores= hd, .cores= d,\
+.has_threads = he, .threads = e,\
+.has_maxcpus = hf, .maxcpus = f,\
+}
+
/**
* @config - the given SMP configuration
* @expect_prefer_sockets - the expected parsing result for the
@@ -290,6 +304,10 @@ static const struct SMPTestData data_generic_invalid[] = {
/* config: -smp 2,dies=2 */
.config = SMP_CONFIG_WITH_DIES(T, 2, F, 0, T, 2, F, 0, F, 0, F, 0),
.expect_error = "dies not supported by this machine's CPU topology",
+}, {
+/* config: -smp 2,clusters=2 */
+.config = SMP_CONFIG_WITH_CLUSTERS(T, 2, F, 0, T, 2, F, 0, F, 0, F, 0),
+.expect_error = "clusters not supported by this machine's CPU
topology",
}, {
/* config: -smp 8,sockets=2,cores=4,threads=2,maxcpus=8 */
.config = SMP_CONFIG_GENERIC(T, 8, T, 2, T, 4, T, 2, T, 8),
@@ -337,20 +355,40 @@ static const struct SMPTestData data_with_dies_invalid[]
= {
},
};
+static const struct SMPTestData data_with_clusters_invalid[] = {
+{
+/* config: -smp 16,sockets=2,clusters=2,cores=4,threads=2,maxcpus=16 */
+.config = SMP_CONFIG_WITH_CLUSTERS(T, 16, T, 2, T, 2, T, 4, T, 2, T,
16),
+.expect_error = "Invalid CPU topology: "
+"product of the hierarchy must match maxcpus: "
+"sockets (2) * clusters (2) * cores (4) * threads (2) "
+"!= maxcpus (16)",
+}, {
+/* config: -smp 34,sockets=2,clusters=2,cores=4,threads=2,maxcpus=32 */
+.config = SMP_CONFIG_WITH_CLUSTERS(T, 34, T, 2, T, 2, T, 4, T, 2, T,
32),
+.expect_error = "Invalid CPU topology: "
+"maxcpus must be equal to or greater than smp: "
+"sockets (2) * clusters (2) * cores (4) * threads (2) "
+"== maxcpus (32) < smp_cpus (34)",
+},
+};
+
static char *smp_config_to_string(const SMPConfiguration *config)
{
return g_strdup_printf(
"(SMPConfiguration) {\n"
-".has_cpus= %5s, cpus= %" PRId64 ",\n"
-".has_sockets = %5s, sockets = %" PRId64 ",\n"
-".has_dies= %5s, dies= %" PRId64 ",\n"
-".has_cores = %5s, cores = %" PRId64 ",\n"
-".has_threads = %5s, threads = %" PRId64 ",\n"
-".has_maxcpus = %5s, maxcpus = %" PRId64 ",\n"
+".has_cpus = %5s, cpus = %" PRId64 ",\n"
+".has_sockets = %5s, sockets = %" PRId64 ",\n"
+".has_dies = %5s, dies = %" PRId64 ",\n"
+".has_clusters = %5s, clusters = %" PRId64 ",\n"
+".has_cores= %5s, cores= %" PRId64 ",\n"
+".has_threads = %5s, threads = %" PRId64 ",\n"
+".has_maxcpus = %5s, maxcpus = %" PRId64 ",\n"
"}",
config->has_cpus ? "true" : "false", config->cpus,
config->has_sockets ? "true" : "false", config->sockets,
config->has_dies ? "true" : "false", config->dies,
+config->has_clusters ? "true" : "false", config->clusters,
config->has_cores ? "true" : "false", config->cores,
config->has_threads ? "true" : "false", config->threads,
config->has_maxcpus ? "true" : "false", config->maxcpus);
@@ -363,11 +401,12 @@ static char *cpu_topology_to_string(const CpuTopology
*topo)
".cpus = %u,\n"
".sockets = %u,\n"
".dies = %u,\n"
+".clusters = %u,\n"
".cores= %u,\n"
".threads = %u,\n"
".max_cpus = %u,\n"
"}",
-topo->cpus, topo->sockets, topo->dies,
+topo->cpus, topo->sockets, topo->die
[PULL 01/20] hw/qdev: Cosmetic around documentation
From: Philippe Mathieu-Daudé
Add empty lines to have a clearer distinction between different
functions declarations.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Yanan Wang
Message-Id: <20211218130437.1516929-2-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 20d3066595e..59a822ffceb 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -321,6 +321,7 @@ compat_props_add(GPtrArray *arr,
* The returned object has a reference count of 1.
*/
DeviceState *qdev_new(const char *name);
+
/**
* qdev_try_new: Try to create a device on the heap
* @name: device type to create
@@ -329,6 +330,7 @@ DeviceState *qdev_new(const char *name);
* does not exist, rather than asserting.
*/
DeviceState *qdev_try_new(const char *name);
+
/**
* qdev_realize: Realize @dev.
* @dev: device to realize
@@ -347,6 +349,7 @@ DeviceState *qdev_try_new(const char *name);
* qdev_realize_and_unref() instead.
*/
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
+
/**
* qdev_realize_and_unref: Realize @dev and drop a reference
* @dev: device to realize
@@ -372,6 +375,7 @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error
**errp);
* would be incorrect. For that use case you want qdev_realize().
*/
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
+
/**
* qdev_unrealize: Unrealize a device
* @dev: device to unrealize
@@ -450,6 +454,7 @@ typedef enum {
* For named input GPIO lines, use qdev_get_gpio_in_named().
*/
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
+
/**
* qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
* @dev: Device whose GPIO we want
@@ -497,6 +502,7 @@ qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const
char *name, int n);
* For named output GPIO lines, use qdev_connect_gpio_out_named().
*/
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
+
/**
* qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
* @dev: Device whose GPIO to connect
@@ -524,6 +530,7 @@ void qdev_connect_gpio_out(DeviceState *dev, int n,
qemu_irq pin);
*/
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
qemu_irq pin);
+
/**
* qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
* @dev: Device whose output GPIO we are interested in
@@ -541,6 +548,7 @@ void qdev_connect_gpio_out_named(DeviceState *dev, const
char *name, int n,
* by the platform-bus subsystem.
*/
qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int
n);
+
/**
* qdev_intercept_gpio_out: Intercept an existing GPIO connection
* @dev: Device to intercept the outbound GPIO line from
@@ -582,6 +590,7 @@ BusState *qdev_get_child_bus(DeviceState *dev, const char
*name);
* hold of an input GPIO line to manipulate it.
*/
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
+
/**
* qdev_init_gpio_out: create an array of anonymous output GPIO lines
* @dev: Device to create output GPIOs for
@@ -610,6 +619,7 @@ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler
handler, int n);
* handler.
*/
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
+
/**
* qdev_init_gpio_out: create an array of named output GPIO lines
* @dev: Device to create output GPIOs for
@@ -623,6 +633,7 @@ void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins,
int n);
*/
void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
const char *name, int n);
+
/**
* qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines
* for the specified device
--
2.33.1
[PULL 03/20] hw/qdev: Correct qdev_connect_gpio_out_named() documentation
From: Philippe Mathieu-Daudé qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Yanan Wang Message-Id: <20211218130437.1516929-4-f4...@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index dcf20c69b89..424c48daf6e 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -504,7 +504,8 @@ qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n); void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); /** - * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines + * qdev_connect_gpio_out_named: Connect one of a device's named output + * GPIO lines * @dev: Device whose GPIO to connect * @name: Name of the output GPIO array * @n: Number of the anonymous output GPIO line (which must be in range) @@ -526,7 +527,7 @@ void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); * qemu_irqs at once, or to connect multiple outbound GPIOs to the * same qemu_irq; see qdev_connect_gpio_out() for details. * - * For named output GPIO lines, use qdev_connect_gpio_out_named(). + * For anonymous output GPIO lines, use qdev_connect_gpio_out(). */ void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n, qemu_irq pin); -- 2.33.1
[PULL 02/20] hw/qdev: Correct qdev_init_gpio_out_named() documentation
From: Philippe Mathieu-Daudé qdev_init_gpio_out_named() is described as qdev_init_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Reported-by: Yanan Wang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Yanan Wang Message-Id: <20211218130437.1516929-3-f4...@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 59a822ffceb..dcf20c69b89 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -621,7 +621,7 @@ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); /** - * qdev_init_gpio_out: create an array of named output GPIO lines + * qdev_init_gpio_out_named: create an array of named output GPIO lines * @dev: Device to create output GPIOs for * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines * @name: Name to give this array of GPIO lines -- 2.33.1
[PULL 00/20] Machine-next patches for 2021-12-31
The following changes since commit 69f153667fce723ee546d2f047d66d0cfa67c3cc: Merge tag 'memory-api-20211231' of https://github.com/philmd/qemu into staging (2021-12-30 17:02:42 -0800) are available in the Git repository at: https://github.com/philmd/qemu.git tags/machine-core-20211231 for you to fetch changes up to 2ece6e64846e1929c4ed338c73328d3b126e48d3: MAINTAINERS: email address change (2021-12-31 13:42:54 +0100) Machine core patches - Clarify qdev_connect_gpio_out() documentation - Rework test-smp-parse tests following QOM style - Introduce CPU cluster topology support (Yanan Wang) - MAINTAINERS updates (Yanan Wang, Li Zhijian, myself) Li Zhijian (1): MAINTAINERS: email address change Philippe Mathieu-Daudé (13): hw/qdev: Cosmetic around documentation hw/qdev: Correct qdev_init_gpio_out_named() documentation hw/qdev: Correct qdev_connect_gpio_out_named() documentation hw/qdev: Rename qdev_connect_gpio_out*() 'input_pin' parameter tests/unit/test-smp-parse: Pass machine type as argument to tests tests/unit/test-smp-parse: Split the 'generic' test in valid / invalid tests/unit/test-smp-parse: Add 'smp-with-dies' machine type tests/unit/test-smp-parse: Add 'smp-generic-invalid' machine type tests/unit/test-smp-parse: Add 'smp-generic-valid' machine type tests/unit/test-smp-parse: Simplify pointer to compound literal use tests/unit/test-smp-parse: Constify some pointer/struct hw/core: Rename smp_parse() -> machine_parse_smp_config() MAINTAINERS: Change philmd's email address Yanan Wang (6): qemu-options: Improve readability of SMP related Docs hw/core/machine: Introduce CPU cluster topology support tests/unit/test-smp-parse: Add testcases for CPU clusters tests/unit/test-smp-parse: No need to explicitly zero MachineClass members tests/unit/test-smp-parse: Keep default MIN/MAX CPUs in machine_base_class_init MAINTAINERS: Self-recommended as reviewer of "Machine core" qapi/machine.json| 5 +- include/hw/boards.h | 9 +- include/hw/qdev-core.h | 24 ++- hw/core/gpio.c | 13 +- hw/core/machine-smp.c| 32 ++-- hw/core/machine.c| 5 +- softmmu/vl.c | 3 + tests/unit/test-smp-parse.c | 295 ++- .gitlab-ci.d/edk2/Dockerfile | 2 +- .mailmap | 1 + MAINTAINERS | 21 +-- qemu-options.hx | 79 +++--- 12 files changed, 358 insertions(+), 131 deletions(-) -- 2.33.1
Re: [PATCH v6 0/8] tests/unit: Rework test-smp-parse tests
> Philippe Mathieu-Daudé (8): > tests/unit/test-smp-parse: Pass machine type as argument to tests > tests/unit/test-smp-parse: Split the 'generic' test in valid / invalid > tests/unit/test-smp-parse: Add 'smp-with-dies' machine type > tests/unit/test-smp-parse: Add 'smp-generic-invalid' machine type > tests/unit/test-smp-parse: Add 'smp-generic-valid' machine type > tests/unit/test-smp-parse: Simplify pointer to compound literal use > tests/unit/test-smp-parse: Constify some pointer/struct > hw/core: Rename smp_parse() -> machine_parse_smp_config() Series queued to machine-next.
Re: [PATCH v2 0/5] hw/qdev: Clarify qdev_connect_gpio_out() documentation
On 12/18/21 14:04, Philippe Mathieu-Daudé wrote: > Trivial patches clarifying qdev_connect_gpio_out() use, > basically that the qemu_irq argument is an input. > > Since v1: > - Addressed Yanan Wang and Peter Maydell comments: > - Correct qdev_init_gpio_out_named() doc > - Drop i8042_setup_a20_line() wrapper > > Philippe Mathieu-Daudé (5): > hw/qdev: Cosmetic around documentation > hw/qdev: Correct qdev_init_gpio_out_named() documentation > hw/qdev: Correct qdev_connect_gpio_out_named() documentation > hw/qdev: Rename qdev_connect_gpio_out*() 'input_pin' parameter > hw/input/pckbd: Open-code i8042_setup_a20_line() wrapper Queuing patches 1-4 via machine-next.
Re: [PATCH 1/3] hw/qdev: Restrict qdev_get_gpio_out_connector() to qdev-internal.h
On 12/31/21 08:30, wangyanan (Y) wrote: > Hi, > > On 2021/12/30 6:52, Philippe Mathieu-Daudé wrote: >> qdev_get_gpio_out_connector() is called by sysbus_get_connected_irq() >> which is only used by platform-bus.c; restrict it to hw/core/ by >> adding a local "qdev-internal.h" header. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/core/qdev-internal.h | 15 +++ >> include/hw/qdev-core.h | 18 -- >> hw/core/gpio.c | 1 + >> hw/core/sysbus.c | 1 + >> 4 files changed, 17 insertions(+), 18 deletions(-) >> create mode 100644 hw/core/qdev-internal.h >> >> diff --git a/hw/core/qdev-internal.h b/hw/core/qdev-internal.h >> new file mode 100644 >> index 000..6ec17d0ea70 >> --- /dev/null >> +++ b/hw/core/qdev-internal.h >> @@ -0,0 +1,15 @@ >> +/* SPDX-License-Identifier: GPL-2.0-or-later */ >> +/* >> + * qdev internal helpers >> + * >> + * Copyright (c) 2009-2021 QEMU contributors >> + */ >> +#ifndef HW_CORE_QDEV_INTERNAL_H >> +#define HW_CORE_QDEV_INTERNAL_H >> + >> +#include "hw/qdev-core.h" >> + >> +/* Following functions are only used by the platform-bus subsystem */ > Could it be better to also keep the original function comment here? We could, but this include being now internal, it seems superfluous. Since Peter documented this function, let see if he has an preference. >> +qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char >> *name, int n); >> + >> +#endif /* HW_CORE_QDEV_INTERNAL_H */ >> diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h >> index d19c9417520..655899654bb 100644 >> --- a/include/hw/qdev-core.h >> +++ b/include/hw/qdev-core.h >> @@ -532,24 +532,6 @@ void qdev_connect_gpio_out(DeviceState *dev, int >> n, qemu_irq pin); >> void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, >> int n, >> qemu_irq input_pin); >> -/** >> - * qdev_get_gpio_out_connector: Get the qemu_irq connected to an >> output GPIO >> - * @dev: Device whose output GPIO we are interested in >> - * @name: Name of the output GPIO array >> - * @n: Number of the output GPIO line within that array >> - * >> - * Returns whatever qemu_irq is currently connected to the specified >> - * output GPIO line of @dev. This will be NULL if the output GPIO line >> - * has never been wired up to the anything. Note that the qemu_irq >> - * returned does not belong to @dev -- it will be the input GPIO or >> - * IRQ of whichever device the board code has connected up to @dev's >> - * output GPIO. >> - * >> - * You probably don't need to use this function -- it is used only >> - * by the platform-bus subsystem. >> - */ >> -qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char >> *name, int n); >> - >> /** >> * qdev_intercept_gpio_out: Intercept an existing GPIO connection >> * @dev: Device to intercept the outbound GPIO line from >> diff --git a/hw/core/gpio.c b/hw/core/gpio.c >> index 80d07a6ec99..513ccbd1062 100644 >> --- a/hw/core/gpio.c >> +++ b/hw/core/gpio.c >> @@ -21,6 +21,7 @@ >> #include "hw/qdev-core.h" >> #include "hw/irq.h" >> #include "qapi/error.h" >> +#include "qdev-internal.h" >> static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, >> const char *name) >> diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c >> index 05c1da3d311..0e6773c8df7 100644 >> --- a/hw/core/sysbus.c >> +++ b/hw/core/sysbus.c >> @@ -23,6 +23,7 @@ >> #include "hw/sysbus.h" >> #include "monitor/monitor.h" >> #include "exec/address-spaces.h" >> +#include "qdev-internal.h" >> static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int >> indent); >> static char *sysbus_get_fw_dev_path(DeviceState *dev); > Otherwise, the tweak looks reasonable: > Reviewed-by: Yanan Wang Thanks, Phil.
Re: [PATCH v2] MAINTAINERS: Change philmd's email address
On 12/31/21 01:07, Philippe Mathieu-Daudé wrote: > The phi...@redhat.com email address will stop working on > 2022-01-01, change it to my personal email address. > > Update .mailmap in case anyone wants to send me an email > because of some past commit I authored. > > Reviewed-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > v2: Fixed .mailmap (Richard) > --- > .gitlab-ci.d/edk2/Dockerfile | 2 +- > .mailmap | 1 + > MAINTAINERS | 18 +- > 3 files changed, 11 insertions(+), 10 deletions(-) Patch queued.
Re: [PATCH] MAINTAINERS: email address change
Hi, On 12/31/21 06:09, Li Zhijian wrote: > Fujitsu's mail service has migrated to O365 months ago, the > lizhij...@cn.fujitsu.com address will stop working on 2022-06-01, > change it to my new email address lizhij...@fujitsu.com. > > Signed-off-by: Li Zhijian > --- > MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Since I'm preparing a pull request modifying MAINTAINERS, I am queuing this patch. Regards, Phil.
Re: [PATCH v5 00/14] ARM virt: Introduce CPU clusters topology support
On 12/28/21 10:22, Yanan Wang wrote: > Hi, > > This series introduces the new CPU clusters topology parameter > and enable the support for it on ARM virt machines. > Yanan Wang (14): > qemu-options: Improve readability of SMP related Docs > hw/core/machine: Introduce CPU cluster topology support > hw/core/machine: Wrap target specific parameters together > tests/unit/test-smp-parse: Add testcases for CPU clusters > tests/unit/test-smp-parse: No need to explicitly zero MachineClass > members > tests/unit/test-smp-parse: Keep default MIN/MAX CPUs in > machine_base_class_init > MAINTAINERS: Self-recommended as reviewer of "Machine core" Patches 1, 2, 4-7 queued, thanks.
[RFC] virtio_pmem: enable live migration support
From: Pankaj Gupta >
Enable live migration support for virtio-pmem device.
Tested this: with live migration on same host.
Need suggestion on below points to support virtio-pmem live migration
between two separate host systems:
- There is still possibility of stale page cache page at the
destination host which we cannot invalidate currently as done in 1]
for write-back mode because virtio-pmem memory backend file is mmaped
in guest address space and invalidating corresponding page cache pages
would also fault all the other userspace process mappings on the same file.
Or we make it strict no other process would mmap this backing file?
-- In commit 1] we first fsync and then invalidate all the pages from
destination
page cache. fsync would sync the stale dirty page cache page, Is this the
right
thing to do as we might end up in data discrepency?
- Thinking, alternatively if we transfer active corresponding guest page cache
pages information from active LRU list source to destination host and refault
those pages. This would also help to enable hot page cache in destination host
for the guest and solve stale page cache issue as well. How we can achieve
this
so that we make sure we get rid of all the stale page cache pages in
destination
host?
Looking for suggestions on recommended and feasible solution we can implement?
Thank you!
1] dd577a26ff ("block/file-posix: implement bdrv_co_invalidate_cache() on
Linux")
Signed-off-by: Pankaj Gupta
---
hw/virtio/virtio-pmem.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c
index d1aeb90a31..a19619a387 100644
--- a/hw/virtio/virtio-pmem.c
+++ b/hw/virtio/virtio-pmem.c
@@ -123,6 +123,7 @@ static void virtio_pmem_realize(DeviceState *dev, Error
**errp)
}
host_memory_backend_set_mapped(pmem->memdev, true);
+vmstate_register_ram(&pmem->memdev->mr, DEVICE(pmem));
virtio_init(vdev, TYPE_VIRTIO_PMEM, VIRTIO_ID_PMEM,
sizeof(struct virtio_pmem_config));
pmem->rq_vq = virtio_add_queue(vdev, 128, virtio_pmem_flush);
@@ -133,6 +134,7 @@ static void virtio_pmem_unrealize(DeviceState *dev)
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
VirtIOPMEM *pmem = VIRTIO_PMEM(dev);
+vmstate_unregister_ram(&pmem->memdev->mr, DEVICE(pmem));
host_memory_backend_set_mapped(pmem->memdev, false);
virtio_delete_queue(pmem->rq_vq);
virtio_cleanup(vdev);
@@ -157,6 +159,16 @@ static MemoryRegion
*virtio_pmem_get_memory_region(VirtIOPMEM *pmem,
return &pmem->memdev->mr;
}
+static const VMStateDescription vmstate_virtio_pmem = {
+.name = "virtio-pmem",
+.minimum_version_id = 1,
+.version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_VIRTIO_DEVICE,
+VMSTATE_END_OF_LIST()
+},
+};
+
static Property virtio_pmem_properties[] = {
DEFINE_PROP_UINT64(VIRTIO_PMEM_ADDR_PROP, VirtIOPMEM, start, 0),
DEFINE_PROP_LINK(VIRTIO_PMEM_MEMDEV_PROP, VirtIOPMEM, memdev,
@@ -171,6 +183,7 @@ static void virtio_pmem_class_init(ObjectClass *klass, void
*data)
VirtIOPMEMClass *vpc = VIRTIO_PMEM_CLASS(klass);
device_class_set_props(dc, virtio_pmem_properties);
+dc->vmsd = &vmstate_virtio_pmem;
vdc->realize = virtio_pmem_realize;
vdc->unrealize = virtio_pmem_unrealize;
--
2.25.1
[PATCH 6/8] hw/scsi: Rename SCSIRequest::resid as 'residual'
The 'resid' field is slightly confusing and could be
interpreted as some ID. Rename it as 'residual' which
is clearer to review. No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/scsi/scsi.h | 4 ++--
hw/scsi/megasas.c | 42 +-
hw/scsi/scsi-bus.c | 10 +-
hw/scsi/scsi-disk.c| 4 ++--
softmmu/dma-helpers.c | 26 +-
5 files changed, 47 insertions(+), 39 deletions(-)
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
index 2ef80af6dca..b27d133b113 100644
--- a/include/hw/scsi/scsi.h
+++ b/include/hw/scsi/scsi.h
@@ -30,7 +30,7 @@ struct SCSIRequest {
int16_t status;
int16_t host_status;
void *hba_private;
-size_tresid;
+size_tresidual;
SCSICommand cmd;
NotifierList cancel_notifiers;
@@ -125,7 +125,7 @@ struct SCSIBusInfo {
void *hba_private);
void (*transfer_data)(SCSIRequest *req, uint32_t arg);
void (*fail)(SCSIRequest *req);
-void (*complete)(SCSIRequest *req, size_t resid);
+void (*complete)(SCSIRequest *req, size_t residual);
void (*cancel)(SCSIRequest *req);
void (*change)(SCSIBus *bus, SCSIDevice *dev, SCSISense sense);
QEMUSGList *(*get_sg_list)(SCSIRequest *req);
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index dc9bbdb740e..cb019549371 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -1045,7 +1045,8 @@ static int megasas_pd_get_info_submit(SCSIDevice *sdev,
int lun,
uint64_t pd_size;
uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
uint8_t cmdbuf[6];
-size_t len, resid;
+size_t len;
+size_t residual;
if (!cmd->iov_buf) {
cmd->iov_buf = g_malloc0(dcmd_size);
@@ -1112,9 +1113,10 @@ static int megasas_pd_get_info_submit(SCSIDevice *sdev,
int lun,
info->connected_port_bitmap = 0x1;
info->device_speed = 1;
info->link_speed = 1;
-resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg,
MEMTXATTRS_UNSPECIFIED);
+residual = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg,
+MEMTXATTRS_UNSPECIFIED);
g_free(cmd->iov_buf);
-cmd->iov_size = dcmd_size - resid;
+cmd->iov_size = dcmd_size - residual;
cmd->iov_buf = NULL;
return MFI_STAT_OK;
}
@@ -1149,7 +1151,8 @@ static int megasas_dcmd_pd_get_info(MegasasState *s,
MegasasCmd *cmd)
static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_ld_list info;
-size_t dcmd_size = sizeof(info), resid;
+size_t dcmd_size = sizeof(info);
+size_t residual;
uint32_t num_ld_disks = 0, max_ld_disks;
uint64_t ld_size;
BusChild *kid;
@@ -1184,8 +1187,9 @@ static int megasas_dcmd_ld_get_list(MegasasState *s,
MegasasCmd *cmd)
info.ld_count = cpu_to_le32(num_ld_disks);
trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
-resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
-cmd->iov_size = dcmd_size - resid;
+residual = dma_buf_read(&info, dcmd_size, &cmd->qsg,
+MEMTXATTRS_UNSPECIFIED);
+cmd->iov_size = dcmd_size - residual;
return MFI_STAT_OK;
}
@@ -1193,7 +1197,8 @@ static int megasas_dcmd_ld_list_query(MegasasState *s,
MegasasCmd *cmd)
{
uint16_t flags;
struct mfi_ld_targetid_list info;
-size_t dcmd_size = sizeof(info), resid;
+size_t dcmd_size = sizeof(info);
+size_t residual;
uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
BusChild *kid;
@@ -1233,8 +1238,9 @@ static int megasas_dcmd_ld_list_query(MegasasState *s,
MegasasCmd *cmd)
info.size = dcmd_size;
trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
-resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
-cmd->iov_size = dcmd_size - resid;
+residual = dma_buf_read(&info, dcmd_size, &cmd->qsg,
+MEMTXATTRS_UNSPECIFIED);
+cmd->iov_size = dcmd_size - residual;
return MFI_STAT_OK;
}
@@ -1244,7 +1250,8 @@ static int megasas_ld_get_info_submit(SCSIDevice *sdev,
int lun,
struct mfi_ld_info *info = cmd->iov_buf;
size_t dcmd_size = sizeof(struct mfi_ld_info);
uint8_t cdb[6];
-ssize_t len, resid;
+ssize_t len;
+size_t residual;
uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
uint64_t ld_size;
@@ -1283,9 +1290,10 @@ static int megasas_ld_get_info_submit(SCSIDevice *sdev,
int lun,
info->ld_config.span[0].num_blocks = info->size;
info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
-resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg,
MEMTXATTRS_UNSPECIFIED);
+residual = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg,
+MEMTXATTRS_UNSPECIFIED);
g_free(cmd->iov_buf);
-cmd->iov_size = dcmd_size -
[PATCH 7/8] hw/dma: Introduce dma_size_t type definition
The DMA API defines the dma_addr_t type for DMA addresses.
Some sizes related to the API also use this type, which is
a bit confusing when reviewing.
Add a similar 'dma_size_t' definition (and its format string).
Update the obvious places where dma_size_t should be used,
and adapt a pair of format strings.
Move QEMUSGList declaration after dma_size_t definition
so this structure can use the new type.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rdma/rdma_utils.h | 4 ++--
include/hw/pci/pci.h | 10
include/sysemu/dma.h | 50 ---
hw/ide/ahci.c | 2 +-
hw/nvme/ctrl.c| 2 +-
hw/nvram/fw_cfg.c | 2 +-
hw/rdma/rdma_utils.c | 6 ++---
hw/rdma/vmw/pvrdma_main.c | 2 +-
hw/scsi/lsi53c895a.c | 4 ++--
hw/scsi/megasas.c | 10
hw/usb/libhw.c| 4 ++--
softmmu/dma-helpers.c | 10
hw/rdma/trace-events | 2 +-
13 files changed, 55 insertions(+), 53 deletions(-)
diff --git a/hw/rdma/rdma_utils.h b/hw/rdma/rdma_utils.h
index 0c6414e7e0a..5446e4e2500 100644
--- a/hw/rdma/rdma_utils.h
+++ b/hw/rdma/rdma_utils.h
@@ -38,8 +38,8 @@ typedef struct RdmaProtectedGSList {
GSList *list;
} RdmaProtectedGSList;
-void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t len);
-void rdma_pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len);
+void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_size_t len);
+void rdma_pci_dma_unmap(PCIDevice *dev, void *buffer, dma_size_t len);
void rdma_protected_gqueue_init(RdmaProtectedGQueue *list);
void rdma_protected_gqueue_destroy(RdmaProtectedGQueue *list);
void rdma_protected_gqueue_append_int64(RdmaProtectedGQueue *list,
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index f0d707efb8c..f2257b2cd8c 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -805,7 +805,7 @@ static inline AddressSpace *pci_get_address_space(PCIDevice
*dev)
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
- void *buf, dma_addr_t len,
+ void *buf, dma_size_t len,
DMADirection dir, MemTxAttrs attrs)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
@@ -825,7 +825,7 @@ static inline MemTxResult pci_dma_rw(PCIDevice *dev,
dma_addr_t addr,
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
- void *buf, dma_addr_t len)
+ void *buf, dma_size_t len)
{
return pci_dma_rw(dev, addr, buf, len,
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
@@ -844,7 +844,7 @@ static inline MemTxResult pci_dma_read(PCIDevice *dev,
dma_addr_t addr,
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
-const void *buf, dma_addr_t len)
+const void *buf, dma_size_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len,
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
@@ -889,7 +889,7 @@ PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
* @dir: indicates the transfer direction
*/
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
-dma_addr_t *plen, DMADirection dir)
+dma_size_t *plen, DMADirection dir)
{
void *buf;
@@ -898,7 +898,7 @@ static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t
addr,
return buf;
}
-static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
+static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_size_t len,
DMADirection dir, dma_addr_t access_len)
{
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index 0db2478a506..45a2567848c 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -15,22 +15,11 @@
#include "block/block.h"
#include "block/accounting.h"
-typedef struct ScatterGatherEntry ScatterGatherEntry;
-
typedef enum {
DMA_DIRECTION_TO_DEVICE = 0,
DMA_DIRECTION_FROM_DEVICE = 1,
} DMADirection;
-struct QEMUSGList {
-ScatterGatherEntry *sg;
-int nsg;
-int nalloc;
-size_t size;
-DeviceState *dev;
-AddressSpace *as;
-};
-
/*
* When an IOMMU is present, bus addresses become distinct from
* CPU/memory physical addresses and may be a different size. Because
@@ -39,9 +28,22 @@ struct QEMUSGList {
* least most) cases.
*/
typedef uint64_t dma_addr_t;
+typedef uint64_t dma_size_t;
#define DMA_ADDR_BITS 64
#define DMA_ADDR_FMT "%" PRIx64
+#define DMA_SIZE_FMT "%" PR
[PATCH 2/8] hw/pci: Restrict pci-bus stub to sysemu
Neither tools nor user-mode emulation require the PCI bus stub.
Signed-off-by: Philippe Mathieu-Daudé
---
stubs/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/stubs/meson.build b/stubs/meson.build
index 363f6fa785d..d359cbe1ad7 100644
--- a/stubs/meson.build
+++ b/stubs/meson.build
@@ -26,7 +26,6 @@
stub_ss.add(files('module-opts.c'))
stub_ss.add(files('monitor.c'))
stub_ss.add(files('monitor-core.c'))
-stub_ss.add(files('pci-bus.c'))
stub_ss.add(files('qemu-timer-notify-cb.c'))
stub_ss.add(files('qmp_memory_device.c'))
stub_ss.add(files('qmp-command-available.c'))
@@ -51,6 +50,7 @@
endif
if have_system
stub_ss.add(files('fw_cfg.c'))
+ stub_ss.add(files('pci-bus.c'))
stub_ss.add(files('semihost.c'))
stub_ss.add(files('usb-dev-stub.c'))
stub_ss.add(files('xen-hw-stub.c'))
--
2.33.1
[PATCH 1/8] hw/nvram: Restrict stub to sysemu and tools
User-mode emulation doesn't need the fw_cfg stub.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/meson.build | 6 --
stubs/meson.build| 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 202a5466e63..f5ee9f6b88c 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -1,5 +1,7 @@
-# QOM interfaces must be available anytime QOM is used.
-qom_ss.add(files('fw_cfg-interface.c'))
+if have_system or have_tools
+ # QOM interfaces must be available anytime QOM is used.
+ qom_ss.add(files('fw_cfg-interface.c'))
+endif
softmmu_ss.add(files('fw_cfg.c'))
softmmu_ss.add(when: 'CONFIG_CHRP_NVRAM', if_true: files('chrp_nvram.c'))
diff --git a/stubs/meson.build b/stubs/meson.build
index 71469c1d50a..363f6fa785d 100644
--- a/stubs/meson.build
+++ b/stubs/meson.build
@@ -11,7 +11,6 @@
stub_ss.add(files('dump.c'))
stub_ss.add(files('error-printf.c'))
stub_ss.add(files('fdset.c'))
-stub_ss.add(files('fw_cfg.c'))
stub_ss.add(files('gdbstub.c'))
stub_ss.add(files('get-vm-name.c'))
if linux_io_uring.found()
@@ -51,6 +50,7 @@
stub_ss.add(files('replay-tools.c'))
endif
if have_system
+ stub_ss.add(files('fw_cfg.c'))
stub_ss.add(files('semihost.c'))
stub_ss.add(files('usb-dev-stub.c'))
stub_ss.add(files('xen-hw-stub.c'))
--
2.33.1
[PATCH 5/8] hw/rdma/rdma_utils: Rename rdma_pci_dma_map 'len' argument
Various APIs use 'pval' naming for 'pointer to val'.
rdma_pci_dma_map() uses 'plen' for 'PCI length', but since
'PCI' is already explicit in the function name, simplify
and rename the argument 'len'. No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rdma/rdma_utils.h | 2 +-
hw/rdma/rdma_utils.c | 14 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/rdma/rdma_utils.h b/hw/rdma/rdma_utils.h
index 9fd0efd940b..0c6414e7e0a 100644
--- a/hw/rdma/rdma_utils.h
+++ b/hw/rdma/rdma_utils.h
@@ -38,7 +38,7 @@ typedef struct RdmaProtectedGSList {
GSList *list;
} RdmaProtectedGSList;
-void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t plen);
+void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t len);
void rdma_pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len);
void rdma_protected_gqueue_init(RdmaProtectedGQueue *list);
void rdma_protected_gqueue_destroy(RdmaProtectedGQueue *list);
diff --git a/hw/rdma/rdma_utils.c b/hw/rdma/rdma_utils.c
index 98df58f6897..61cb8ede0fd 100644
--- a/hw/rdma/rdma_utils.c
+++ b/hw/rdma/rdma_utils.c
@@ -17,29 +17,29 @@
#include "trace.h"
#include "rdma_utils.h"
-void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t plen)
+void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t len)
{
void *p;
-hwaddr len = plen;
+hwaddr pci_len = len;
if (!addr) {
rdma_error_report("addr is NULL");
return NULL;
}
-p = pci_dma_map(dev, addr, &len, DMA_DIRECTION_TO_DEVICE);
+p = pci_dma_map(dev, addr, &pci_len, DMA_DIRECTION_TO_DEVICE);
if (!p) {
rdma_error_report("pci_dma_map fail, addr=0x%"PRIx64", len=%"PRId64,
- addr, len);
+ addr, pci_len);
return NULL;
}
-if (len != plen) {
-rdma_pci_dma_unmap(dev, p, len);
+if (pci_len != len) {
+rdma_pci_dma_unmap(dev, p, pci_len);
return NULL;
}
-trace_rdma_pci_dma_map(addr, p, len);
+trace_rdma_pci_dma_map(addr, p, pci_len);
return p;
}
--
2.33.1
[PATCH 8/8] hw/dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult
Since the previous commit, dma_buf_rw() returns a MemTxResult
type. Do not discard it, return it to the caller.
Since both dma_buf_read/dma_buf_write functions were previously
returning the QEMUSGList size not consumed, add an extra argument
where the unconsummed size can be stored.
Update the few callers.
Reviewed-by: Klaus Jensen
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/scsi/scsi.h | 2 +-
include/sysemu/dma.h | 6 +++--
hw/ide/ahci.c | 8 +++---
hw/nvme/ctrl.c | 4 +--
hw/scsi/megasas.c | 59 ++
hw/scsi/scsi-bus.c | 6 +++--
softmmu/dma-helpers.c | 18 +
7 files changed, 63 insertions(+), 40 deletions(-)
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
index b27d133b113..1ffb367f94f 100644
--- a/include/hw/scsi/scsi.h
+++ b/include/hw/scsi/scsi.h
@@ -30,7 +30,7 @@ struct SCSIRequest {
int16_t status;
int16_t host_status;
void *hba_private;
-size_tresidual;
+uint64_t residual;
SCSICommand cmd;
NotifierList cancel_notifiers;
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index 45a2567848c..77a346d5ed1 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -303,8 +303,10 @@ BlockAIOCB *dma_blk_read(BlockBackend *blk,
BlockAIOCB *dma_blk_write(BlockBackend *blk,
QEMUSGList *sg, uint64_t offset, uint32_t align,
BlockCompletionFunc *cb, void *opaque);
-uint64_t dma_buf_read(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs
attrs);
-uint64_t dma_buf_write(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs
attrs);
+MemTxResult dma_buf_read(void *ptr, dma_size_t len, dma_size_t *residual,
+ QEMUSGList *sg, MemTxAttrs attrs);
+MemTxResult dma_buf_write(void *ptr, dma_size_t len, dma_size_t *residual,
+ QEMUSGList *sg, MemTxAttrs attrs);
void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
QEMUSGList *sg, enum BlockAcctType type);
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 256bbc377ce..564293fd492 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1384,9 +1384,9 @@ static void ahci_pio_transfer(const IDEDMA *dma)
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
if (is_write) {
-dma_buf_write(s->data_ptr, size, &s->sg, attrs);
+dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs);
} else {
-dma_buf_read(s->data_ptr, size, &s->sg, attrs);
+dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs);
}
}
@@ -1479,9 +1479,9 @@ static int ahci_dma_rw_buf(const IDEDMA *dma, bool
is_write)
}
if (is_write) {
-dma_buf_read(p, l, &s->sg, MEMTXATTRS_UNSPECIFIED);
+dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
} else {
-dma_buf_write(p, l, &s->sg, MEMTXATTRS_UNSPECIFIED);
+dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
}
/* free sglist, update byte count */
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 4620e662fc9..72faa94a4a3 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -1150,9 +1150,9 @@ static uint16_t nvme_tx(NvmeCtrl *n, NvmeSg *sg, uint8_t
*ptr, uint32_t len,
dma_size_t residual;
if (dir == NVME_TX_DIRECTION_TO_DEVICE) {
-residual = dma_buf_write(ptr, len, &sg->qsg, attrs);
+dma_buf_write(ptr, len, &residual, &sg->qsg, attrs);
} else {
-residual = dma_buf_read(ptr, len, &sg->qsg, attrs);
+dma_buf_read(ptr, len, &residual, &sg->qsg, attrs);
}
if (unlikely(residual)) {
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 7456a25970a..f2daeeb7005 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -750,6 +750,7 @@ static int megasas_ctrl_get_info(MegasasState *s,
MegasasCmd *cmd)
size_t dcmd_size = sizeof(info);
BusChild *kid;
int num_pd_disks = 0;
+dma_size_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -860,7 +861,9 @@ static int megasas_ctrl_get_info(MegasasState *s,
MegasasCmd *cmd)
MFI_INFO_PDMIX_SATA |
MFI_INFO_PDMIX_LD);
-cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg,
MEMTXATTRS_UNSPECIFIED);
+dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -868,6 +871,7 @@ static int megasas_mfc_get_defaults(MegasasState *s,
MegasasCmd *cmd)
{
struct mfi_defaults info;
size_t dcmd_size = sizeof(struct mfi_defaults);
+dma_size_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -890,7 +894,9 @@ static int megasas_mfc_get_defaults(MegasasSt
Re: [PATCH 8/8] hw/dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult
On 12/31/21 12:49, Philippe Mathieu-Daudé wrote:
> Since the previous commit, dma_buf_rw() returns a MemTxResult
> type. Do not discard it, return it to the caller.
>
> Since both dma_buf_read/dma_buf_write functions were previously
> returning the QEMUSGList size not consumed, add an extra argument
> where the unconsummed size can be stored.
>
> Update the few callers.
>
> Reviewed-by: Klaus Jensen
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/scsi/scsi.h | 2 +-
> include/sysemu/dma.h | 6 +++--
> hw/ide/ahci.c | 8 +++---
> hw/nvme/ctrl.c | 4 +--
> hw/scsi/megasas.c | 59 ++
> hw/scsi/scsi-bus.c | 6 +++--
> softmmu/dma-helpers.c | 18 +
> 7 files changed, 63 insertions(+), 40 deletions(-)
>
> diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
> index b27d133b113..1ffb367f94f 100644
> --- a/include/hw/scsi/scsi.h
> +++ b/include/hw/scsi/scsi.h
> @@ -30,7 +30,7 @@ struct SCSIRequest {
> int16_t status;
> int16_t host_status;
> void *hba_private;
> -size_tresidual;
> +uint64_t residual;
Oops I forgot to mention this change since the previous version.
> SCSICommand cmd;
> NotifierList cancel_notifiers;
>
> diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
> index 45a2567848c..77a346d5ed1 100644
> --- a/include/sysemu/dma.h
> +++ b/include/sysemu/dma.h
> @@ -303,8 +303,10 @@ BlockAIOCB *dma_blk_read(BlockBackend *blk,
> BlockAIOCB *dma_blk_write(BlockBackend *blk,
>QEMUSGList *sg, uint64_t offset, uint32_t align,
>BlockCompletionFunc *cb, void *opaque);
> -uint64_t dma_buf_read(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs
> attrs);
> -uint64_t dma_buf_write(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs
> attrs);
> +MemTxResult dma_buf_read(void *ptr, dma_size_t len, dma_size_t *residual,
> + QEMUSGList *sg, MemTxAttrs attrs);
> +MemTxResult dma_buf_write(void *ptr, dma_size_t len, dma_size_t *residual,
> + QEMUSGList *sg, MemTxAttrs attrs);
>
[PATCH 4/8] hw/dma: Remove CONFIG_USER_ONLY check
DMA API should not be included in user-mode emulation.
If so, build should fail. Remove the CONFIG_USER_ONLY check.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/dma.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index b3faef41b2f..0db2478a506 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -31,8 +31,6 @@ struct QEMUSGList {
AddressSpace *as;
};
-#ifndef CONFIG_USER_ONLY
-
/*
* When an IOMMU is present, bus addresses become distinct from
* CPU/memory physical addresses and may be a different size. Because
@@ -288,7 +286,6 @@ void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev,
int alloc_hint,
AddressSpace *as);
void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
void qemu_sglist_destroy(QEMUSGList *qsg);
-#endif
typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov,
BlockCompletionFunc *cb, void *cb_opaque,
--
2.33.1
[PATCH 3/8] hw/pci: Document pci_dma_map()
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 5b36334a28a..f0d707efb8c 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -876,6 +876,18 @@ PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
#undef PCI_DMA_DEFINE_LDST
+/**
+ * pci_dma_map: Map a physical memory region into a device PCI address space.
+ *
+ * May map a subset of the requested range, given by and returned in @plen.
+ * May return %NULL and set *@plen to zero(0), if resources needed to perform
+ * the mapping are exhausted.
+ *
+ * @dev: #PCIDevice to be accessed
+ * @addr: address within that device's address space
+ * @plen: pointer to length of buffer; updated on return
+ * @dir: indicates the transfer direction
+ */
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
--
2.33.1
[PATCH 0/8] hw/dma: Introduce dma_size_t type definition
Hi, This series aims to clarify a bit the DMA API, in particular the 'size' argument which is not clear enough (as we use multiple types for it). The clarification is trivial: add a dma_size_t typedef, similar to the dma_addr_t one. This helps avoiding build failures on 32-bit host [*] (and likely overflows calculation too IMO). Some units using the DMA API are first removed from user-mode emulation to avoid build failure (they shouldn't be there in the first place). Then some variables are renamed for clarity (no functional change). Finally the dma_size_t typedef is added, and the previous patch which failed on 32-bit host applied on top (not failing anymore). Regards, Phil. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg858825.html Philippe Mathieu-Daudé (8): hw/nvram: Restrict stub to sysemu and tools hw/pci: Restrict pci-bus stub to sysemu hw/pci: Document pci_dma_map() hw/dma: Remove CONFIG_USER_ONLY check hw/rdma/rdma_utils: Rename rdma_pci_dma_map 'len' argument hw/scsi: Rename SCSIRequest::resid as 'residual' hw/dma: Introduce dma_size_t type definition hw/dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult hw/rdma/rdma_utils.h | 4 +- include/hw/pci/pci.h | 22 +++--- include/hw/scsi/scsi.h| 4 +- include/sysemu/dma.h | 59 ++- hw/ide/ahci.c | 10 ++--- hw/nvme/ctrl.c| 6 +-- hw/nvram/fw_cfg.c | 2 +- hw/rdma/rdma_utils.c | 16 hw/rdma/vmw/pvrdma_main.c | 2 +- hw/scsi/lsi53c895a.c | 4 +- hw/scsi/megasas.c | 85 +++ hw/scsi/scsi-bus.c| 12 +++--- hw/scsi/scsi-disk.c | 4 +- hw/usb/libhw.c| 4 +- softmmu/dma-helpers.c | 38 - hw/nvram/meson.build | 6 ++- hw/rdma/trace-events | 2 +- stubs/meson.build | 4 +- 18 files changed, 164 insertions(+), 120 deletions(-) -- 2.33.1
Thoughts on CONFIG_TOOLS & CONFIG_USER_ONLY
Hi, The CONFIG_USER_ONLY definition allows limiting user-mode code to user emulation (in contrast to system emulation). We often use it in common code. Often the negative form (to *exclude* user-mode) is used. This works fine with system emulation in mind, but it could introduce subtle bugs when neither user nor system emulation are used, for example with tools. There is a CONFIG_TOOLS definition, but it is not used in C: config-host.mak:CONFIG_TOOLS=y config-host.h:#define CONFIG_TOOLS 1 Not sure how to clarify / improve, this is a bit confusing. Just thinking loudly :) Regards, Phil.
[PATCH v2 0/3] support subsets of virtual memory extension
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. Specification: https://github.com/riscv/virtual-memory/tree/main/specs The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v2 To test this implementation, specify cpu argument with 'x-svinval=true,x-svnapot=true,x-svpbmt=true'. This implementation can pass the riscv-tests for rv64ssvnapot. v2: * add extension check for svnapot and svpbmt Weiwei Li (3): target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension target/riscv/cpu.c | 3 + target/riscv/cpu.h | 3 + target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_helper.c | 27 ++-- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 + target/riscv/translate.c| 1 + 7 files changed, 116 insertions(+), 4 deletions(-) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc -- 2.17.1
[PATCH v2 1/3] target/riscv: add support for svnapot extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 20
4 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bce..cbcb7f522b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dc10f27093..1fbbde28c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1e31f4d35f..1156c941cb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,6 +483,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT0x300 /* Reserved for Software */
+#define PTE_N 0x8000 /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10f3baba53..e044153986 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,9 +619,12 @@ restart:
return TRANSLATE_FAIL;
}
-hwaddr ppn = pte >> PTE_PPN_SHIFT;
+hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
-if (!(pte & PTE_V)) {
+RISCVCPU *cpu = env_archcpu(env);
+if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+return TRANSLATE_FAIL;
+} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
@@ -699,8 +702,17 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
-*physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
-(addr & ~TARGET_PAGE_MASK);
+
+int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
+if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1 ||
+(napot_bits != 0 && napot_bits != 4)) {
+return TRANSLATE_FAIL;
+}
+
+*physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
[PATCH v2 2/3] target/riscv: add support for svinval extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +
target/riscv/translate.c| 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cbcb7f522b..77ef0f85fe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1fbbde28c6..5dd9e53293 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+bool ext_svinval;
bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8617307b29..809464113a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 . ... . 1010011 @r2_rm
fcvt_lu_h 1100010 00011 . ... . 1010011 @r2_rm
fcvt_h_l 1101010 00010 . ... . 1010011 @r2_rm
fcvt_h_lu 1101010 00011 . ... . 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma0001011 . . 000 0 1110011 @sfence_vma
+sfence_w_inval0001100 0 0 000 0 1110011
+sfence_inval_ir 0001100 1 0 000 0 1110011
+hinval_vvma 0011011 . . 000 0 1110011 @hfence_vvma
+hinval_gvma 0111011 . . 000 0 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc
b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 00..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see
[PATCH v2 3/3] target/riscv: add support for svpbmt extension
It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is
sequentially consistent and doesn't model PMAs currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Tested-by: Heiko Stuebner
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 9 -
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 77ef0f85fe..743bcfe297 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
+DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5dd9e53293..6656b8a4f3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_svinval;
bool ext_svnapot;
+bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1156c941cb..3dae358aa5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,7 +483,10 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT0x300 /* Reserved for Software */
+#define PTE_RSVD0x1FC0 /* Reserved for future use */
+#define PTE_PBMT0x6000 /* Page-based memory types */
#define PTE_N 0x8000 /* NAPOT translation */
+#define PTE_ATTR0xFFC0 /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e044153986..41d04675b3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,16 +619,23 @@ restart:
return TRANSLATE_FAIL;
}
-hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
+hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
return TRANSLATE_FAIL;
+} else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+return TRANSLATE_FAIL;
+} else if (pte & PTE_RSVD) {
+return TRANSLATE_FAIL;
} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
+return TRANSLATE_FAIL;
+}
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
