Re: [PATCH 0/3] Reorg ppc64 pmu insn counting
On 12/30/21 23:12, Daniel Henrique Barboza wrote: On 12/23/21 18:19, Richard Henderson wrote: On 12/23/21 12:36 PM, Daniel Henrique Barboza wrote: This reorg is breaking PMU-EBB tests, unfortunately. These tests are run from the kernel tree [1] and I test them inside a pSeries TCG guest. You'll need to apply patches 9 and 10 of [2] beforehand (they apply cleanly in current master) because they aren't upstream yet and EBB needs it. The tests that are breaking consistently with this reorg are: back_to_back_ebbs_test.c cpu_event_pinned_vs_ebb_test.c cycles_test.c task_event_pinned_vs_ebb_test.c In which case perhaps drop my first patch for now, and instead simply replicate your tcg algorithm in c exactly -- using none of the helpers that currently exist. We can improve the code, and the use of pmc_get_event from hreg_compute_hregs_value second. While attempting to do that I figured what was off with this series and ended up fixing it. It's now working with the event-based branch interrupt tests and Avocado seems happy as well. It took some small adjustments/fixes in patches 1/2 and an extra patch of mine tuning the existing logic after the reorg. I'll clean it up and re-send it next week/year. Shouldn't we merge this series first ? It is really improving emulation and keeps the check-avocado tests under the timeout limit (which I find important). Thanks, C.
Re: [PATCH 1/4] acpi: fix QEMU crash when started with SLIC table
CCing, qemu-stable@
On Mon, 27 Dec 2021 14:31:17 -0500
Igor Mammedov wrote:
> if QEMU is started with used provided SLIC table blob,
>
> -acpitable sig=SLIC,oem_id='CRASH
> ',oem_table_id="ME",oem_rev=2210,asl_compiler_id="",asl_compiler_rev=,data=/dev/null
> it will assert with:
>
> hw/acpi/aml-build.c:61:build_append_padded_str: assertion failed: (len <=
> maxlen)
>
> and following backtrace:
>
> ...
> build_append_padded_str (array=0x56afe320, str=0x56afdb2e "CRASH
> ME", maxlen=0x6, pad=0x20) at hw/acpi/aml-build.c:61
> acpi_table_begin (desc=0x7fffd1b0, array=0x56afe320) at
> hw/acpi/aml-build.c:1727
> build_fadt (tbl=0x56afe320, linker=0x57ca3830, f=0x7fffd318,
> oem_id=0x56afdb2e "CRASH ME", oem_table_id=0x56afdb34 "ME") at
> hw/acpi/aml-build.c:2064
> ...
>
> which happens due to acpi_table_begin() expecting NULL terminated
> oem_id and oem_table_id strings, which is normally the case, but
> in case of user provided SLIC table, oem_id points to table's blob
> directly and as result oem_id became longer than expected.
>
> Fix issue by handling oem_id consistently and make acpi_get_slic_oem()
> return NULL terminated strings.
>
> PS:
> After [1] refactoring, oem_id semantics became inconsistent, where
> NULL terminated string was coming from machine and old way pointer
> into byte array coming from -acpitable option. That used to work
> since build_header() wasn't expecting NULL terminated string and
> blindly copied the 1st 6 bytes only.
>
> However commit [2] broke that by replacing build_header() with
> acpi_table_begin(), which was expecting NULL terminated string
> and was checking oem_id size.
>
> 1) 602b45820 ("acpi: Permit OEM ID and OEM table ID fields to be changed")
> 2)
> Fixes: 4b56e1e4eb08 ("acpi: build_fadt: use
> acpi_table_begin()/acpi_table_end() instead of build_header()")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/786
> Signed-off-by: Igor Mammedov
> ---
> hw/acpi/core.c | 4 ++--
> hw/i386/acpi-build.c | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/acpi/core.c b/hw/acpi/core.c
> index 1e004d0078..3e811bf03c 100644
> --- a/hw/acpi/core.c
> +++ b/hw/acpi/core.c
> @@ -345,8 +345,8 @@ int acpi_get_slic_oem(AcpiSlicOem *oem)
> struct acpi_table_header *hdr = (void *)(u - sizeof(hdr->_length));
>
> if (memcmp(hdr->sig, "SLIC", 4) == 0) {
> -oem->id = hdr->oem_id;
> -oem->table_id = hdr->oem_table_id;
> +oem->id = g_strndup(hdr->oem_id, 6);
> +oem->table_id = g_strndup(hdr->oem_table_id, 8);
> return 0;
> }
> }
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 8383b83ee3..0234fe7588 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -2723,6 +2723,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState
> *machine)
>
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> +g_free(slic_oem.id);
> +g_free(slic_oem.table_id);
> }
>
> static void acpi_ram_update(MemoryRegion *mr, GArray *data)
Re: [PATCH v2 0/5] Re-write PPC64 PMU instruction count using TCG Ops
On 12/23/21 21:18, Daniel Henrique Barboza wrote: Hi, In this version the tedious repetition was taken away from the code by using a helper that increments the PMCs based on specified conditions. As far as Avocado test goes, the performance is the same as the previous version. All PMU-EBB kernel selftests are also passing. Basically we have the same benefits from v1 but 150+ lines shorter. changes from v1: - former patches 2-6: removed - new patch 2: * added inc_spr_if_cond() helper - new patch 3: * add insn count for PMCs 1-4 - patch 4 (former 7): * use a loop to reduce code repetition when checking for counter overflows - v1 link: https://lists.gnu.org/archive/html/qemu-devel/2021-12/msg03871.html I understand that you are going to rebase on top of Richard's patchset. and so this series is now obsolete ? Thanks, C.
[PATCH v2 5/9] ppc/ppc405: Restore TCR and STR write handlers
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :
SPR_BOOKE_TSR (0x150)
SPR_BOOKE_TCR (0x154)
SPR_40x_TSR (0x3D8)
SPR_40x_TCR (0x3DA)
Cc: Christophe Leroy
Fixes: ddd1055b07fd ("PPC: booke timers")
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/spr_tcg.h | 2 ++
hw/ppc/ppc.c | 25 +
target/ppc/cpu_init.c| 4 ++--
target/ppc/timebase_helper.c | 10 ++
target/ppc/translate.c | 12
hw/ppc/trace-events | 2 ++
8 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fc66c3561dab..4808e10ebe8b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1399,6 +1399,8 @@ target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
void store_40x_sler(CPUPPCState *env, uint32_t val);
+void store_40x_tcr(CPUPPCState *env, target_ulong val);
+void store_40x_tsr(CPUPPCState *env, target_ulong val);
void store_booke_tcr(CPUPPCState *env, target_ulong val);
void store_booke_tsr(CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all(CPUPPCState *env);
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fb6cac38b4c5..f9c72dcd504d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -706,6 +706,8 @@ DEF_HELPER_2(store_hid0_601, void, env, tl)
DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index f98d97c0ba17..64cf5302cb86 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -87,6 +87,8 @@ void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 818d75798584..cca99cb86f81 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1300,6 +1300,31 @@ target_ulong load_40x_pit (CPUPPCState *env)
return cpu_ppc_load_decr(env);
}
+void store_40x_tsr(CPUPPCState *env, target_ulong val)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+
+trace_ppc40x_store_tcr(val);
+
+env->spr[SPR_40x_TSR] &= ~(val & 0xFC00);
+if (val & 0x8000) {
+ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
+}
+}
+
+void store_40x_tcr(CPUPPCState *env, target_ulong val)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+ppc_tb_t *tb_env;
+
+trace_ppc40x_store_tsr(val);
+
+tb_env = env->tb_env;
+env->spr[SPR_40x_TCR] = val & 0xFFC0;
+start_stop_pit(env, tb_env, 1);
+cpu_4xx_wdt_cb(cpu);
+}
+
static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
{
CPUPPCState *env = opaque;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 06ef15cd9e4e..b5e2fde9ec4d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1440,11 +1440,11 @@ static void register_40x_sprs(CPUPPCState *env)
0x);
spr_register(env, SPR_40x_TCR, "TCR",
SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_booke_tcr,
+ _read_generic, _write_40x_tcr,
0x);
spr_register(env, SPR_40x_TSR, "TSR",
SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_booke_tsr,
+ _read_generic, _write_40x_tsr,
0x);
}
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 8ff4080eb91e..af378318c19c 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -144,6 +144,16 @@ void helper_store_40x_pit(CPUPPCState *env, target_ulong
val)
store_40x_pit(env, val);
}
+void helper_store_40x_tcr(CPUPPCState *env, target_ulong val)
+{
+store_40x_tcr(env, val);
+}
+
+void
[PATCH v2 3/9] ppc/ppc4xx: Convert printfs()
Use a QEMU log primitive for errors and trace events for debug.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-3-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/mpc8544_guts.c | 9 ++---
hw/ppc/ppc4xx_devs.c | 39 +++
hw/ppc/ppc4xx_pci.c | 11 +++
hw/ppc/trace-events | 5 +
4 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index e8d2d51c20c0..a26e83d0484b 100644
--- a/hw/ppc/mpc8544_guts.c
+++ b/hw/ppc/mpc8544_guts.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#include "sysemu/runstate.h"
#include "cpu.h"
#include "hw/sysbus.h"
@@ -82,7 +83,9 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
value = env->spr[SPR_E500_SVR];
break;
default:
-fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unknown register 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
break;
}
@@ -101,8 +104,8 @@ static void mpc8544_guts_write(void *opaque, hwaddr addr,
}
break;
default:
-fprintf(stderr, "guts: Unknown register write: %x = %x\n",
-(int)addr, (unsigned)value);
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown register 0x%" HWADDR_PRIx
+ " = 0x%" PRIx64 "\n", __func__, addr, value);
break;
}
}
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 980c48944fc7..e7d82ae5016c 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -35,14 +35,7 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
-
-/*#define DEBUG_UIC*/
-
-#ifdef DEBUG_UIC
-# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
-#else
-# define LOG_UIC(...) do { } while (0)
-#endif
+#include "trace.h"
static void ppc4xx_reset(void *opaque)
{
@@ -137,8 +130,9 @@ static uint32_t sdram_bcr (hwaddr ram_base,
bcr = 0x000C;
break;
default:
-printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
- ram_size);
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
+ ram_size);
return 0x;
}
bcr |= ram_base & 0xFF80;
@@ -171,10 +165,8 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
{
if (sdram->bcr[i] & 0x0001) {
/* Unmap RAM */
-#ifdef DEBUG_SDRAM
-printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
- __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
-#endif
+trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
+ sdram_size(sdram->bcr[i]));
memory_region_del_subregion(get_system_memory(),
>containers[i]);
memory_region_del_subregion(>containers[i],
@@ -183,10 +175,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
sdram->bcr[i] = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x0001)) {
-#ifdef DEBUG_SDRAM
-printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
- __func__, sdram_base(bcr), sdram_size(bcr));
-#endif
+trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr));
memory_region_init(>containers[i], NULL, "sdram-containers",
sdram_size(bcr));
memory_region_add_subregion(>containers[i], 0,
@@ -216,10 +205,8 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
-#ifdef DEBUG_SDRAM
-printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
- __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
-#endif
+trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
+ sdram_size(sdram->bcr[i]));
memory_region_del_subregion(get_system_memory(),
>ram_memories[i]);
}
@@ -316,16 +303,12 @@ static void dcr_write_sdram (void *opaque, int dcrn,
uint32_t val)
case 0x20: /* SDRAM_CFG */
val &= 0xFFE0;
if (!(sdram->cfg & 0x8000) && (val & 0x8000)) {
-#ifdef DEBUG_SDRAM
-printf("%s: enable SDRAM controller\n", __func__);
-#endif
+trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
sdram_map_bcr(sdram);
sdram->status &= ~0x8000;
} else if ((sdram->cfg & 0x8000) && !(val & 0x8000)) {
-#ifdef DEBUG_SDRAM
-printf("%s: disable SDRAM controller\n", __func__);
-#endif
+
[PATCH v2 6/9] ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU
This is a small cleanup to ease reading. It includes the removal of a
check done on the returned value of g_malloc0(), which can not fail.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c | 42 +++---
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index cca99cb86f81..bb5bee9a3382 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1124,14 +1124,12 @@ struct ppc40x_timer_t {
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
-PowerPCCPU *cpu;
-CPUPPCState *env;
+PowerPCCPU *cpu = opaque;
+CPUPPCState *env = >env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
-env = opaque;
-cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -1193,13 +1191,11 @@ static void start_stop_pit (CPUPPCState *env, ppc_tb_t
*tb_env, int is_excp)
static void cpu_4xx_pit_cb (void *opaque)
{
-PowerPCCPU *cpu;
-CPUPPCState *env;
+PowerPCCPU *cpu = opaque;
+CPUPPCState *env = >env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
-env = opaque;
-cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
env->spr[SPR_40x_TSR] |= 1 << 27;
@@ -1216,14 +1212,12 @@ static void cpu_4xx_pit_cb (void *opaque)
/* Watchdog timer */
static void cpu_4xx_wdt_cb (void *opaque)
{
-PowerPCCPU *cpu;
-CPUPPCState *env;
+PowerPCCPU *cpu = opaque;
+CPUPPCState *env = >env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
-env = opaque;
-cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -1341,24 +1335,26 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env,
uint32_t freq,
{
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
+PowerPCCPU *cpu = env_archcpu(env);
+
+trace_ppc40x_timers_init(freq);
tb_env = g_malloc0(sizeof(ppc_tb_t));
+ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
+
env->tb_env = tb_env;
tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
-ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
tb_env->opaque = ppc40x_timer;
-trace_ppc40x_timers_init(freq);
-if (ppc40x_timer != NULL) {
-/* We use decr timer for PIT */
-tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_pit_cb,
env);
-ppc40x_timer->fit_timer =
-timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_fit_cb, env);
-ppc40x_timer->wdt_timer =
-timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_wdt_cb, env);
-ppc40x_timer->decr_excp = decr_excp;
-}
+
+/* We use decr timer for PIT */
+tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_pit_cb,
cpu);
+ppc40x_timer->fit_timer =
+timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_fit_cb, cpu);
+ppc40x_timer->wdt_timer =
+timer_new_ns(QEMU_CLOCK_VIRTUAL, _4xx_wdt_cb, cpu);
+ppc40x_timer->decr_excp = decr_excp;
return _40x_set_tb_clk;
}
--
2.31.1
[PATCH v2 4/9] ppc/ppc405: Activate MMU logs
There is no need to deactivate MMU logging at compile time. Remove all
use of defines. Only keep DUMP_PAGE_TABLES for another series since
page tables could be dumped from the monitor.
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/mmu_common.c | 164 +++-
target/ppc/mmu_helper.c | 97 +++-
2 files changed, 122 insertions(+), 139 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 4e278365ca55..91270c1f17eb 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -34,29 +34,7 @@
#include "mmu-book3s-v3.h"
#include "mmu-radix64.h"
-/* #define DEBUG_MMU */
-/* #define DEBUG_BATS */
-/* #define DEBUG_SOFTWARE_TLB */
/* #define DUMP_PAGE_TABLES */
-/* #define FLUSH_ALL_TLBS */
-
-#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0)
-#else
-# define LOG_MMU_STATE(cpu) do { } while (0)
-#endif
-
-#ifdef DEBUG_SOFTWARE_TLB
-# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
-#else
-# define LOG_SWTLB(...) do { } while (0)
-#endif
-
-#ifdef DEBUG_BATS
-# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
-#else
-# define LOG_BATS(...) do { } while (0)
-#endif
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
@@ -231,18 +209,20 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t
*ctx,
tlb = >tlb.tlb6[nr];
/* This test "emulates" the PTE index match for hardware TLBs */
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
-LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
- "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
+qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx
+ " " TARGET_FMT_lx "] <> " TARGET_FMT_lx "\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
continue;
}
-LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
- TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, eaddr, tlb->pte1,
- access_type == MMU_DATA_STORE ? 'S' : 'L',
- access_type == MMU_INST_FETCH ? 'I' : 'D');
+qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s " TARGET_FMT_lx " <> "
+ TARGET_FMT_lx " " TARGET_FMT_lx " %c %c\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, eaddr, tlb->pte1,
+ access_type == MMU_DATA_STORE ? 'S' : 'L',
+ access_type == MMU_INST_FETCH ? 'I' : 'D');
switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1,
0, access_type)) {
case -3:
@@ -272,8 +252,9 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t
*ctx,
}
if (best != -1) {
done:
-LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
- ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
+qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx
+ " prot=%01x ret=%d\n",
+ ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
pte_update_flags(ctx, >tlb.tlb6[best].pte1, ret, access_type);
}
@@ -317,7 +298,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
int ret = -1;
bool ifetch = access_type == MMU_INST_FETCH;
-LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
+ qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
ifetch ? 'I' : 'D', virtual);
if (ifetch) {
BATlt = env->IBAT[1];
@@ -332,9 +313,9 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
BEPIu = *BATu & 0xF000;
BEPIl = *BATu & 0x0FFE;
bat_size_prot(env, , , , BATu, BATl);
-LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
- " BATl " TARGET_FMT_lx "\n", __func__,
- ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
+ qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
+ TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
+ ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF000) == BEPIu &&
((virtual & 0x0FFE) & ~bl) == BEPIl) {
/* BAT matches */
@@ -347,32 +328,33 @@ static int get_bat_6xx_tlb(CPUPPCState
[PATCH v2 7/9] ppc/ppc405: Fix timer initialization
Timers are already initialized in ppc4xx_init(). No need to do it a
second time with a wrong set.
Fixes: d715ea961254 ("PPC: 405: Fix ppc405ep initialization")
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-7-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ec97b22bd019..8aacd275a652 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1461,8 +1461,6 @@ PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
ppc4xx_pob_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
-/* Initialize timers */
-ppc_booke_timers_init(cpu, sysclk, 0);
/* Universal interrupt controller */
uicdev = qdev_new(TYPE_PPC_UIC);
uicsbd = SYS_BUS_DEVICE(uicdev);
--
2.31.1
[PATCH v2 9/9] ppc/ppc405: Dump specific registers
Rework slightly ppc_cpu_dump_state() to replace the various 'if'
statements with a 'switch'.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9ef9a1a5ddd5..25970bd79f20 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -8648,16 +8648,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
+switch (env->excp_model) {
#if defined(TARGET_PPC64)
-if (env->excp_model == POWERPC_EXCP_POWER7 ||
-env->excp_model == POWERPC_EXCP_POWER8 ||
-env->excp_model == POWERPC_EXCP_POWER9 ||
-env->excp_model == POWERPC_EXCP_POWER10) {
+case POWERPC_EXCP_POWER7:
+case POWERPC_EXCP_POWER8:
+case POWERPC_EXCP_POWER9:
+case POWERPC_EXCP_POWER10:
qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
-}
+break;
#endif
-if (env->excp_model == POWERPC_EXCP_BOOKE) {
+case POWERPC_EXCP_BOOKE:
qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
" MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
@@ -8688,6 +8689,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
* IVORs are left out as they are large and do not change often --
* they can be read with "p $ivor0", "p $ivor1", etc.
*/
+break;
+case POWERPC_EXCP_40x:
+qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
+ "ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
+ env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
+ env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
+
+qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
+ " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
+ env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
+ env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
+break;
+default:
+break;
}
#if defined(TARGET_PPC64)
--
2.31.1
[PATCH v2 1/9] target/ppc: Remove static inline
The compiler should know better how to inline code if necessary.
Suggested-by: Richard Henderson
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f90e616aacda..8ba93d25aee6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -36,7 +36,7 @@
/* Exception processing */
#if !defined(CONFIG_USER_ONLY)
-static inline void dump_syscall(CPUPPCState *env)
+static void dump_syscall(CPUPPCState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
" r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
@@ -48,7 +48,7 @@ static inline void dump_syscall(CPUPPCState *env)
ppc_dump_gpr(env, 8), env->nip);
}
-static inline void dump_hcall(CPUPPCState *env)
+static void dump_hcall(CPUPPCState *env)
{
qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64
" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
@@ -161,7 +161,7 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState
*env, int excp,
* | a | h | 11 | 1 | 1 | h |
* ++
*/
-static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int
excp,
+static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
target_ulong msr,
target_ulong *new_msr,
target_ulong *vector)
@@ -258,7 +258,7 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int
excp_model, int excp,
#endif
}
-static inline void powerpc_set_excp_state(PowerPCCPU *cpu,
+static void powerpc_set_excp_state(PowerPCCPU *cpu,
target_ulong vector, target_ulong
msr)
{
CPUState *cs = CPU(cpu);
@@ -293,7 +293,7 @@ static inline void powerpc_set_excp_state(PowerPCCPU *cpu,
* Note that this function should be greatly optimized when called
* with a constant excp, from ppc_hw_interrupt
*/
-static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
+static void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = >env;
@@ -1167,7 +1167,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t
insn)
#endif /* defined(TARGET_PPC64) */
#endif /* CONFIG_TCG */
-static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
+static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
CPUState *cs = env_cpu(env);
--
2.31.1
[PATCH v2 0/9] ppc/ppc405: Fixes
Hello, The series starts with a couple of cleanups helping debug. It then adds back support for 405 timers which was broken 10 years ago. Thanks, C. Changes in v2: - removed inlining from powerpc_excp() routines - fixed a compile breakage with CONFIG_USER_ONLY - removed all DEBUG defines from MMU models Cédric Le Goater (9): target/ppc: Remove static inline target/ppc: Print out literal exception names in logs ppc/ppc4xx: Convert printfs() ppc/ppc405: Activate MMU logs ppc/ppc405: Restore TCR and STR write handlers ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU ppc/ppc405: Fix timer initialization ppc/ppc405: Introduce a store helper for SPR_40x_PID ppc/ppc405: Dump specific registers target/ppc/cpu.h | 2 + target/ppc/helper.h | 2 + target/ppc/spr_tcg.h | 3 + hw/ppc/mpc8544_guts.c| 9 +- hw/ppc/ppc.c | 67 +- hw/ppc/ppc405_uc.c | 2 - hw/ppc/ppc4xx_devs.c | 39 +++-- hw/ppc/ppc4xx_pci.c | 11 ++- target/ppc/cpu_init.c| 33 +-- target/ppc/excp_helper.c | 87 +-- target/ppc/mmu_common.c | 164 --- target/ppc/mmu_helper.c | 97 ++--- target/ppc/timebase_helper.c | 10 +++ target/ppc/translate.c | 20 + hw/ppc/trace-events | 7 ++ 15 files changed, 338 insertions(+), 215 deletions(-) -- 2.31.1
[PATCH v2 8/9] ppc/ppc405: Introduce a store helper for SPR_40x_PID
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-8-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/translate.c | 8
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 64cf5302cb86..89ff111724dc 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -89,6 +89,7 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int
gprn);
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index b5e2fde9ec4d..9ef9a1a5ddd5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1454,7 +1454,7 @@ static void register_405_sprs(CPUPPCState *env)
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
+ _read_generic, _write_40x_pid,
0x);
spr_register(env, SPR_4xx_CCR0, "CCR0",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eb45f679d34f..cb8ab4d67635 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -890,6 +890,14 @@ void spr_write_40x_tsr(DisasContext *ctx, int sprn, int
gprn)
gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
}
+void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
+{
+TCGv t0 = tcg_temp_new();
+tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
+gen_store_spr(SPR_40x_PID, t0);
+tcg_temp_free(t0);
+}
+
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
--
2.31.1
[PATCH v2 2/9] target/ppc: Print out literal exception names in logs
It facilitates reading the logs when mask CPU_LOG_INT is activated. We
should do the same for error codes.
Cc: Fabiano Rosas
Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-2-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 75 +++-
1 file changed, 74 insertions(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8ba93d25aee6..e3380722c5c4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -36,6 +36,78 @@
/* Exception processing */
#if !defined(CONFIG_USER_ONLY)
+static const char *powerpc_excp_name(int excp)
+{
+switch (excp) {
+case POWERPC_EXCP_CRITICAL: return "CRITICAL";
+case POWERPC_EXCP_MCHECK: return "MCHECK";
+case POWERPC_EXCP_DSI: return "DSI";
+case POWERPC_EXCP_ISI: return "ISI";
+case POWERPC_EXCP_EXTERNAL: return "EXTERNAL";
+case POWERPC_EXCP_ALIGN:return "ALIGN";
+case POWERPC_EXCP_PROGRAM: return "PROGRAM";
+case POWERPC_EXCP_FPU: return "FPU";
+case POWERPC_EXCP_SYSCALL: return "SYSCALL";
+case POWERPC_EXCP_APU: return "APU";
+case POWERPC_EXCP_DECR: return "DECR";
+case POWERPC_EXCP_FIT: return "FIT";
+case POWERPC_EXCP_WDT: return "WDT";
+case POWERPC_EXCP_DTLB: return "DTLB";
+case POWERPC_EXCP_ITLB: return "ITLB";
+case POWERPC_EXCP_DEBUG:return "DEBUG";
+case POWERPC_EXCP_SPEU: return "SPEU";
+case POWERPC_EXCP_EFPDI:return "EFPDI";
+case POWERPC_EXCP_EFPRI:return "EFPRI";
+case POWERPC_EXCP_EPERFM: return "EPERFM";
+case POWERPC_EXCP_DOORI:return "DOORI";
+case POWERPC_EXCP_DOORCI: return "DOORCI";
+case POWERPC_EXCP_GDOORI: return "GDOORI";
+case POWERPC_EXCP_GDOORCI: return "GDOORCI";
+case POWERPC_EXCP_HYPPRIV: return "HYPPRIV";
+case POWERPC_EXCP_RESET:return "RESET";
+case POWERPC_EXCP_DSEG: return "DSEG";
+case POWERPC_EXCP_ISEG: return "ISEG";
+case POWERPC_EXCP_HDECR:return "HDECR";
+case POWERPC_EXCP_TRACE:return "TRACE";
+case POWERPC_EXCP_HDSI: return "HDSI";
+case POWERPC_EXCP_HISI: return "HISI";
+case POWERPC_EXCP_HDSEG:return "HDSEG";
+case POWERPC_EXCP_HISEG:return "HISEG";
+case POWERPC_EXCP_VPU: return "VPU";
+case POWERPC_EXCP_PIT: return "PIT";
+case POWERPC_EXCP_IO: return "IO";
+case POWERPC_EXCP_RUNM: return "RUNM";
+case POWERPC_EXCP_EMUL: return "EMUL";
+case POWERPC_EXCP_IFTLB:return "IFTLB";
+case POWERPC_EXCP_DLTLB:return "DLTLB";
+case POWERPC_EXCP_DSTLB:return "DSTLB";
+case POWERPC_EXCP_FPA: return "FPA";
+case POWERPC_EXCP_DABR: return "DABR";
+case POWERPC_EXCP_IABR: return "IABR";
+case POWERPC_EXCP_SMI: return "SMI";
+case POWERPC_EXCP_PERFM:return "PERFM";
+case POWERPC_EXCP_THERM:return "THERM";
+case POWERPC_EXCP_VPUA: return "VPUA";
+case POWERPC_EXCP_SOFTP:return "SOFTP";
+case POWERPC_EXCP_MAINT:return "MAINT";
+case POWERPC_EXCP_MEXTBR: return "MEXTBR";
+case POWERPC_EXCP_NMEXTBR: return "NMEXTBR";
+case POWERPC_EXCP_ITLBE:return "ITLBE";
+case POWERPC_EXCP_DTLBE:return "DTLBE";
+case POWERPC_EXCP_VSXU: return "VSXU";
+case POWERPC_EXCP_FU: return "FU";
+case POWERPC_EXCP_HV_EMU: return "HV_EMU";
+case POWERPC_EXCP_HV_MAINT: return "HV_MAINT";
+case POWERPC_EXCP_HV_FU:return "HV_FU";
+case POWERPC_EXCP_SDOOR:return "SDOOR";
+case POWERPC_EXCP_SDOOR_HV: return "SDOOR_HV";
+case POWERPC_EXCP_HVIRT:return "HVIRT";
+case POWERPC_EXCP_SYSCALL_VECTORED: return "SYSCALL_VECTORED";
+default:
+g_assert_not_reached();
+}
+}
+
static void dump_syscall(CPUPPCState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
@@ -301,7 +373,8 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp_model,
int excp)
int srr0, srr1, asrr0, asrr1, lev = -1;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %08x (%02x)\n", env->nip, excp, env->error_code);
+ " => %s (%d) error=%02x\n", env->nip,
powerpc_excp_name(excp),
+ excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
if (excp_model == POWERPC_EXCP_BOOKE) {
--
2.31.1
Re: check-python-tox failures
On Wed, Dec 29, 2021 at 7:03 PM Philippe Mathieu-Daudé wrote: > On 12/23/21 05:11, Richard Henderson wrote: > > Hi John, > > > > This test has been failing for quite a while. While it is allowed to > > fail, can we either fix this or disable it, to allow the ci to go proper > > green? > > This job not only fails on the mainstream pipelines, but also on > all forks recently rebased. This is very annoying, I am in favor > of disabling the job until someone figure out what is wrong. > > Phil. > > I've been away on holiday, and will be away for another week. Looks like a few dependencies were updated in the python ecosystem and broke a few things. I tried to fix it in a few hurried minutes, but ... it looks pretty broken: (33/33) tests/pylint.sh: FAIL: Exited with status: '1', stdout: "* \nqemu/__init__.py:1:0: F0010: error while code parsing: Unable to load file qemu/__init__.py:\n[Errno 2] No such file or directory: 'qemu/__init__.py' (parse-error)\n", stderr: "* \nqemu/__init_... (0.54 s) I am not sure why on god's green earth Pylint has decided it doesn't know how to import namespaced modules anymore. I probably won't be able to fix this until next week, so just disable it for now and I'll fix it when I get back. --js. (ps: attempted fix here https://gitlab.com/jsnow/qemu/-/pipelines/440208449 but there seems to be something very wrong with pylint in the tox environment -- I suspect a dependency of pylint's was updated and is breaking things. I'll have to identify which one it is and update the package reqs to exclude it, but ATM I have no idea which it is.) (pps, Cleber, what happened to the avocado output here? It's not showing error logs from the failed tests anymore. Did avocado update and break these options?)
Re: [PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t
Am Sonntag, 19. Dezember 2021, 00:32:09 CET schrieb Matthias Schiffer:
> On 23/10/2021 21:59, Matthias Schiffer wrote:
> > When converting a siginfo_t from waitid(), the interpretation of si_status
> > depends on the value of si_code: For CLD_EXITED, it is an exit code and
> > should be copied verbatim. For other codes, it is a signal number
> > (possibly with additional high bits from ptrace) that should be mapped.
> >
> > This code was previously changed in commit 1c3dfb506ea3
> > ("linux-user/signal: Decode waitid si_code"), but the fix was
> > incomplete.
>
> ping
>
Sorry I can't say anything about this.
The hangs that I experience seem to be unrelated to the patch (no improvement,
but also no worsening).
--
Andreas K. Hüttel
dilfri...@gentoo.org
Gentoo Linux developer
(council, qa, toolchain, base-system, perl, libreoffice)
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Description: This is a digitally signed message part.
Re: [PATCH 4/4] hw/arm: kudo add lm75s on bus 13
On 2/1/22 22:58, Patrick Venture wrote: Add the four lm75s behind the mux on bus 13. Tested by booting the firmware: lm75 42-0048: hwmon0: sensor 'lm75' lm75 43-0049: supply vs not found, using dummy regulator lm75 43-0049: hwmon1: sensor 'lm75' lm75 44-0048: supply vs not found, using dummy regulator lm75 44-0048: hwmon2: sensor 'lm75' lm75 45-0049: supply vs not found, using dummy regulator lm75 45-0049: hwmon3: sensor 'lm75' Signed-off-by: Patrick Venture Reviewed-by: Titus Rwantare --- hw/arm/npcm7xx_boards.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé
[PATCH 3/4] hw/arm: add i2c muxes to kudo-bmc
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 257bf638fd..4cd58972c5 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -330,8 +330,17 @@ static void quanta_gbs_i2c_init(NPCM7xxState *soc)
static void kudo_bmc_i2c_init(NPCM7xxState *soc)
{
+i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x75);
+i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77);
+
+i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
+
at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
+
+i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13), TYPE_PCA9548, 0x77);
+
at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
+
/* TODO: Add remaining i2c devices. */
}
--
2.34.1.448.ga2b2bfdf31-goog
Re: [PATCH 1/4] hw/arm: Add kudo i2c eeproms.
On 2/1/22 22:58, Patrick Venture wrote: From: Chris Rauer Signed-off-by: Chris Rauer Reviewed-by: Hao Wu Reviewed-by: Patrick Venture --- hw/arm/npcm7xx_boards.c | 8 1 file changed, 8 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
[PATCH 2/4] hw/arm: attach MMC to kudo-bmc
From: Shengtan Mao Signed-off-by: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer --- hw/arm/npcm7xx_boards.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 37de9fef43..257bf638fd 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -399,6 +399,7 @@ static void kudo_bmc_init(MachineState *machine) drive_get(IF_MTD, 3, 0)); kudo_bmc_i2c_init(soc); +sdhci_attach_drive(>mmc.sdhci, 0); npcm7xx_load_kernel(machine, soc); } -- 2.34.1.448.ga2b2bfdf31-goog
[PATCH 0/4] hw/arm: Add more devices to kudo-bmc
This series of patches adds various devices that are defined in the device-tree for this board. Chris Rauer (1): hw/arm: Add kudo i2c eeproms. Patrick Venture (2): hw/arm: add i2c muxes to kudo-bmc hw/arm: kudo add lm75s on bus 13 Shengtan Mao (1): hw/arm: attach MMC to kudo-bmc hw/arm/npcm7xx_boards.c | 27 +++ 1 file changed, 27 insertions(+) -- 2.34.1.448.ga2b2bfdf31-goog
[PATCH 4/4] hw/arm: kudo add lm75s on bus 13
Add the four lm75s behind the mux on bus 13.
Tested by booting the firmware:
lm75 42-0048: hwmon0: sensor 'lm75'
lm75 43-0049: supply vs not found, using dummy regulator
lm75 43-0049: hwmon1: sensor 'lm75'
lm75 44-0048: supply vs not found, using dummy regulator
lm75 44-0048: hwmon2: sensor 'lm75'
lm75 45-0049: supply vs not found, using dummy regulator
lm75 45-0049: hwmon3: sensor 'lm75'
Signed-off-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/arm/npcm7xx_boards.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 4cd58972c5..7d0f3148be 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -330,6 +330,8 @@ static void quanta_gbs_i2c_init(NPCM7xxState *soc)
static void kudo_bmc_i2c_init(NPCM7xxState *soc)
{
+I2CSlave *i2c_mux;
+
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x75);
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77);
@@ -337,7 +339,14 @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
-i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13), TYPE_PCA9548, 0x77);
+i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
+ TYPE_PCA9548, 0x77);
+
+/* tmp105 is compatible with the lm75 */
+i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "tmp105", 0x48);
+i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "tmp105", 0x49);
+i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
+i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
--
2.34.1.448.ga2b2bfdf31-goog
[PATCH 1/4] hw/arm: Add kudo i2c eeproms.
From: Chris Rauer
Signed-off-by: Chris Rauer
Reviewed-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 0866d2f4f0..37de9fef43 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -328,6 +328,13 @@ static void quanta_gbs_i2c_init(NPCM7xxState *soc)
*/
}
+static void kudo_bmc_i2c_init(NPCM7xxState *soc)
+{
+at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
+at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
+/* TODO: Add remaining i2c devices. */
+}
+
static void npcm750_evb_init(MachineState *machine)
{
NPCM7xxState *soc;
@@ -391,6 +398,7 @@ static void kudo_bmc_init(MachineState *machine)
npcm7xx_connect_flash(>fiu[1], 0, "mx66u51235f",
drive_get(IF_MTD, 3, 0));
+kudo_bmc_i2c_init(soc);
npcm7xx_load_kernel(machine, soc);
}
--
2.34.1.448.ga2b2bfdf31-goog
Re: [PATCH v2] hw/sd: Add SDHC support for SD card SPI-mode
On 12/28/21 13:57, frank.ch...@sifive.com wrote: > From: Frank Chang > > In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit > is not set to 1 correclty when the assigned SD image size is larger > than 2GB (SDHC). This will cause the SD card to be indentified as SDSC > incorrectly. CCS bit should be set to 1 if we are using SDHC. > > Also, as there's no power up emulation in SPI-mode. > The OCR register: Card power up status bit bit (busy) should also > be set to 1 when reset. (busy bit is set to LOW if the card has not > finished the power up routine.) > > Signed-off-by: Frank Chang > Reviewed-by: Jim Shu > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/sd/sd.c | 24 +--- > 1 file changed, 17 insertions(+), 7 deletions(-) Thanks, queued to sdmmc-next.
[PATCH 1/2] ui/cocoa: add option to disable left-command forwarding to guest
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest. Defaults to enabled.
Also updated the cocoa display documentation to reference the new
left-command-key option along with the existing show-cursor option.
Signed-off-by: Carwyn Ellis
---
qapi/ui.json| 17 +
qemu-options.hx | 12
ui/cocoa.m | 8 +++-
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 2b4371da37..764480e145 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1107,6 +1107,22 @@
'data': { '*grab-on-hover' : 'bool',
'*zoom-to-fit' : 'bool' } }
+##
+# @DisplayCocoa:
+#
+# Cocoa display options.
+#
+# @left-command-key: Enable/disable forwarding of left command key to
+#guest. Allows command-tab window switching on the
+#host without sending this key to the guest when
+#"off". Defaults to "on"
+#
+# Since: 6.2.50
+#
+##
+{ 'struct' : 'DisplayCocoa',
+ 'data': { '*left-command-key' : 'bool' } }
+
##
# @DisplayEGLHeadless:
#
@@ -1254,6 +1270,7 @@
'discriminator' : 'type',
'data': {
'gtk': { 'type': 'DisplayGTK', 'if': 'CONFIG_GTK' },
+ 'cocoa': { 'type': 'DisplayCocoa', 'if': 'CONFIG_COCOA' },
'curses': { 'type': 'DisplayCurses', 'if': 'CONFIG_CURSES' },
'egl-headless': { 'type': 'DisplayEGLHeadless',
'if': { 'all': ['CONFIG_OPENGL', 'CONFIG_GBM'] } },
diff --git a/qemu-options.hx b/qemu-options.hx
index fd1f8135fb..6fa9c38c83 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1912,6 +1912,9 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
#if defined(CONFIG_DBUS_DISPLAY)
"-display dbus[,addr=]\n"
" [,gl=on|core|es|off][,rendernode=]\n"
+#endif
+#if defined(CONFIG_COCOA)
+"-display cocoa[,show-cursor=on|off][,left-command-key=on|off]\n"
#endif
"-display none\n"
"select display backend type\n"
@@ -1999,6 +2002,15 @@ SRST
``charset=CP850`` for IBM CP850 encoding. The default is
``CP437``.
+``cocoa``
+Display video output in a Cocoa window. Mac only. This interface
+provides drop-down menus and other UI elements to configure and
+control the VM during runtime. Valid parameters are:
+
+``show-cursor=on|off`` : Force showing the mouse cursor
+
+``left-command-key=on|off`` : Disable forwarding left command key to
host
+
``egl-headless[,rendernode=]``
Offload all OpenGL operations to a local DRI device. For any
graphical display, this display needs to be paired with either
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..01045d6698 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -95,6 +95,7 @@ static DisplayChangeListener dcl = {
};
static int last_buttons;
static int cursor_hide = 1;
+static int left_command_key_enabled = 1;
static int gArgc;
static char **gArgv;
@@ -834,7 +835,8 @@ QemuCocoaView *cocoaView;
/* Don't pass command key changes to guest unless mouse is
grabbed */
case kVK_Command:
if (isMouseGrabbed &&
-!!(modifiers & NSEventModifierFlagCommand)) {
+!!(modifiers & NSEventModifierFlagCommand) &&
+left_command_key_enabled) {
[self toggleKey:Q_KEY_CODE_META_L];
}
break;
@@ -2054,6 +2056,10 @@ static void cocoa_display_init(DisplayState *ds,
DisplayOptions *opts)
cursor_hide = 0;
}
+if (opts->u.cocoa.has_left_command_key && !opts->u.cocoa.left_command_key)
{
+left_command_key_enabled = 0;
+}
+
// register vga output callbacks
register_displaychangelistener();
--
2.34.1
[PATCH 2/2] ui/cocoa: release mouse when user switches away from QEMU window
This resolves an issue where using command-tab to switch between QEMU
and other windows on the host can leave the mouse pointer visible.
By releasing the mouse when the user switches away, the user must left
click on the QEMU window when switching back in order to hide the
pointer and return control to the guest.
This appraoch ensures that the calls to NSCursor hide and unhide are
always balanced and thus work correctly when invoked.
Signed-off-by: Carwyn Ellis
---
ui/cocoa.m | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 01045d6698..3f7af4a8fa 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -1243,6 +1243,7 @@ QemuCocoaView *cocoaView;
- (void) applicationWillResignActive: (NSNotification *)aNotification
{
COCOA_DEBUG("QemuCocoaAppController: applicationWillResignActive\n");
+[cocoaView ungrabMouse];
[cocoaView raiseAllKeys];
}
@@ -2052,6 +2053,7 @@ static void cocoa_display_init(DisplayState *ds,
DisplayOptions *opts)
[(QemuCocoaAppController *)[[NSApplication sharedApplication]
delegate] toggleFullScreen: nil];
});
}
+
if (opts->has_show_cursor && opts->show_cursor) {
cursor_hide = 0;
}
--
2.34.1
[PATCH 0/2] ui/cocoa: Add option to disable left command and hide cursor on click
Supersedes earlier submissions and splits the patch into two separate patches covering - addition of left-command-key option to disable forwarding this key to the guest - fix for persistent mouse cursor when switching from and back to the QEMU window Having made the switch to an M1 Mac I needed to switch from VMware back to QEMU in order to run some intel guests. This patch addresses a couple of niggles with the cocoa UI, namely: - Using command-tab to switch between the guest OS and MacOS sends the command keypress to the guest which can be annoying e.g. on a windows guest this may trigger the start menu - Switching between the guest and MacOS sometimes leaves the MacOS mouse cursor visible with no way to hide it without switching windows again I've made the following changes - Added a new cocoa display option left-command-key which can be used to disable the left command key in the guest. Default is on. - Added a call to ungrabMouse in the applicationWillResignActive method which frees the mouse and unhides the cursor when switching away from the QEMU window. When switching back the user must left-click in to grab the mouse and hide the cursor again. After testing several different approaches this was the only way I could find to reliably hide the cursor every time the user returns to QEMU after switching to another app on the host machine. - Updated the command line docs to reference the show-cursor option which is also respected by the cocoa UI code. Carwyn Ellis (2): ui/cocoa: add option to disable left-command forwarding to guest ui/cocoa: release mouse when user switches away from QEMU window qapi/ui.json| 17 + qemu-options.hx | 12 ui/cocoa.m | 10 +- 3 files changed, 38 insertions(+), 1 deletion(-) -- 2.34.1
[PATCH v1 0/5] Improve RISC-V debugging support.
1) Make the QEMU monitor `info registers' command more informative 2) Implement the QEMU monitor `print $register' 3) Introduce a new command `info gmem' to the QEMU monitor, which displays a RISC-V hypervisor's guest's 2nd level paging tables similarly to the existing `info mem' command. 4) Improve QEMU RISC-V target descriptions for GDB. In particular, add type information for many control and status registers. 5) Extend the virtual `priv' register with hypervisor virtualization status. Konrad Schwarz (5): RISC-V: larger and more consistent register set for 'info registers' RISC-V: monitor's print register functionality RISC-V: 'info gmem' to show hypervisor guest -> physical address translations RISC-V: Typed CSRs in gdbserver RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register gdb-xml/riscv-32bit-virtual.xml | 30 ++- gdb-xml/riscv-64bit-virtual.xml | 30 ++- hmp-commands-info.hx | 16 ++ include/monitor/hmp-target.h | 2 + target/riscv/cpu.c| 327 ++--- target/riscv/csr.c| 2 + target/riscv/csr32-op-gdbserver.h | 109 ++ target/riscv/csr64-op-gdbserver.h | 76 +++ target/riscv/gdb_csr_types.c | 333 ++ target/riscv/gdb_csr_types.h | 3 + target/riscv/gdbstub.c| 31 ++- target/riscv/meson.build | 4 +- target/riscv/monitor.c| 204 ++ 13 files changed, 1096 insertions(+), 71 deletions(-) create mode 100644 target/riscv/csr32-op-gdbserver.h create mode 100644 target/riscv/csr64-op-gdbserver.h create mode 100644 target/riscv/gdb_csr_types.c create mode 100644 target/riscv/gdb_csr_types.h base-commit: 8627edfb3f1fca24a96a0954148885c3241c10f8 -- Konrad Schwarz
[PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver
GDB target descriptions support typed registers;
such that `info register X' displays not only the hex value of
register `X', but also the individual bitfields the register
comprises (if any), using textual labels if possible.
This patch includes type information for GDB for
a large subset of the RISC-V Control and Status Registers (CSRs).
Signed-off-by: Konrad Schwarz
---
target/riscv/csr.c| 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++
target/riscv/csr64-op-gdbserver.h | 76 +++
target/riscv/gdb_csr_types.c | 333 ++
target/riscv/gdb_csr_types.h | 3 +
target/riscv/gdbstub.c| 26 ++-
target/riscv/meson.build | 4 +-
7 files changed, 547 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/csr32-op-gdbserver.h
create mode 100644 target/riscv/csr64-op-gdbserver.h
create mode 100644 target/riscv/gdb_csr_types.c
create mode 100644 target/riscv/gdb_csr_types.h
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..557b4afe0e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -2094,5 +2095,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
+
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/csr32-op-gdbserver.h
b/target/riscv/csr32-op-gdbserver.h
new file mode 100644
index 00..e8ec527f23
--- /dev/null
+++ b/target/riscv/csr32-op-gdbserver.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com */
+
+ [CSR_USTATUS] { .gdb_type = "sstatus-fields", .gdb_group = "user" },
+ [CSR_UIE] { .gdb_type = "sie-fields", .gdb_group = "user" },
+ [CSR_UTVEC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+ [CSR_USCRATCH] { .gdb_type = "data_ptr", .gdb_group = "user" },
+ [CSR_UEPC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+ [CSR_UCAUSE] { .gdb_type = "scause-fields", .gdb_group = "user" },
+ [CSR_UTVAL] { .gdb_type = "data_ptr", .gdb_group = "user" },
+ [CSR_UIP] { .gdb_type = "code_ptr", .gdb_group = "user" },
+ [CSR_CYCLE] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_TIME] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_INSTRET] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_HPMCOUNTER3] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER4] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER5] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER6] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER7] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER8] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER9] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER10] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER11] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER12] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER13] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER14] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER15] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER16] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER17] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER18] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER19] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER20] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER21] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER22] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER23] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER24] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER25] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER26] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER27] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER28] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER29] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER30] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER31] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_CYCLEH] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_TIMEH] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_INSTRETH] { .gdb_type = "uint32", .gdb_group = "user" },
+ [CSR_HPMCOUNTER3H] { .gdb_type = "int", .gdb_group = "user" },
+ [CSR_HPMCOUNTER4H] { .gdb_type = "int", .gdb_group = "user"
[PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +--
3 files changed, 117 insertions(+), 36 deletions(-)
diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
index 407a1da800..fa519f0129 100644
--- a/hmp-commands-info.hx
+++ b/hmp-commands-info.hx
@@ -237,6 +237,22 @@ SRST
Show the active virtual memory mappings.
ERST
+#if defined TARGET_RISCV
+{
+.name = "gmem",
+.args_type = "",
+.params = "",
+.help = "show the hypervisor guest's physical address"
+ " translation",
+.cmd= hmp_info_gmem,
+},
+#endif
+
+SRST
+ ``info gmem``
+Show the hypervisor guest's physical address translation.
+ERST
+
{
.name = "mtree",
.args_type = "flatview:-f,dispatch_tree:-d,owner:-o,disabled:-D",
diff --git a/include/monitor/hmp-target.h b/include/monitor/hmp-target.h
index ffdc15a34b..9f2dd976f6 100644
--- a/include/monitor/hmp-target.h
+++ b/include/monitor/hmp-target.h
@@ -2,6 +2,7 @@
* QEMU monitor
*
* Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
deal
@@ -45,6 +46,7 @@ CPUArchState *mon_get_cpu_env(Monitor *mon);
CPUState *mon_get_cpu(Monitor *mon);
void hmp_info_mem(Monitor *mon, const QDict *qdict);
+void hmp_info_gmem(Monitor *mon, const QDict *qdict);
void hmp_info_tlb(Monitor *mon, const QDict *qdict);
void hmp_mce(Monitor *mon, const QDict *qdict);
void hmp_info_local_apic(Monitor *mon, const QDict *qdict);
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 3f74ea9934..ad58bdf9ca 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -25,16 +25,6 @@
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
-#ifdef TARGET_RISCV64
-#define PTE_HEADER_FIELDS "vaddrpaddr"\
-"size attr\n"
-#define PTE_HEADER_DELIMITER" "\
-" ---\n"
-#else
-#define PTE_HEADER_FIELDS "vaddrpaddrsize attr\n"
-#define PTE_HEADER_DELIMITER" ---\n"
-#endif
-
/* Perform linear address sign extension */
static target_ulong addr_canonical(int va_bits, target_ulong addr)
{
@@ -47,10 +37,34 @@ static target_ulong addr_canonical(int va_bits,
target_ulong addr)
return addr;
}
-static void print_pte_header(Monitor *mon)
+static void print_pte_header(Monitor *mon,
+char const vaddr_char, char const paddr_char)
{
-monitor_printf(mon, PTE_HEADER_FIELDS);
-monitor_printf(mon, PTE_HEADER_DELIMITER);
+
+# defineVIRTUAL_WIDTH\
+((int) ((sizeof "ff" - sizeof "") * sizeof(target_ulong)))
+# definePHYSICAL_WIDTH\
+((int) ((sizeof "ff" - sizeof "") * sizeof(hwaddr)))
+# defineATTRIBUTE_WIDTH ((int) (sizeof "rwxugad" - sizeof ""))
+
+# defineVIRTUAL_COLUMN_WIDTH(1 + VIRTUAL_WIDTH)
+# definePHYSICAL_COLUMN_WIDTH (1 + PHYSICAL_WIDTH)
+
+static char const dashes[PHYSICAL_WIDTH] = "";
+
+monitor_printf(mon,
+"%c%-*s%c%-*s%-*s%-*s\n"
+"%-*.*s%-*.*s%-*.*s%-*.*s\n",
+
+vaddr_char, VIRTUAL_COLUMN_WIDTH - 1, "addr",
+paddr_char, PHYSICAL_COLUMN_WIDTH - 1, "addr",
+VIRTUAL_COLUMN_WIDTH, "size",
+ATTRIBUTE_WIDTH, "attr",
+
+VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, dashes,
+PHYSICAL_COLUMN_WIDTH, PHYSICAL_WIDTH, dashes,
+VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, dashes,
+ATTRIBUTE_WIDTH, ATTRIBUTE_WIDTH, dashes);
}
static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
@@ -65,21 +79,36 @@ static void print_pte(Monitor *mon, int va_bits,
target_ulong vaddr,
return;
}
-monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
- " %c%c%c%c%c%c%c\n",
- addr_canonical(va_bits, vaddr),
- paddr, size,
- attr & PTE_R ? 'r' : '-',
- attr & PTE_W ? 'w' : '-',
- attr & PTE_X ? 'x' : '-',
- attr & PTE_U ? 'u' : '-',
- attr & PTE_G ? 'g' : '-',
- attr & PTE_A ? 'a' : '-',
- attr & PTE_D ? 'd' : '-');
+# if 4 == TARGET_LONG_SIZE
+# define TARGET_xFMT PRIx32
+# elif 8 == TARGET_LONG_SIZE
+# define TARGET_xFMT PRIx64
+# else
+# error TARGET_LONG_SIZE not handled
[PATCH v1 2/5] RISC-V: monitor's print register functionality
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69 ++
1 file changed, 69 insertions(+)
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 7efb4b62c1..3f74ea9934 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -2,6 +2,7 @@
* QEMU monitor for RISC-V
*
* Copyright (c) 2019 Bin Meng
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
*
* RISC-V specific monitor commands implementation
*
@@ -234,3 +235,71 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
mem_info_svxx(mon, env);
}
+
+static const MonitorDef monitor_defs[] = {
+# define MONITORDEF_RISCV_GPR(NO, ALIAS)\
+{ "x" #NO #ALIAS, offsetof(CPURISCVState, gpr[NO]) },
+
+MONITORDEF_RISCV_GPR(0, |zero)
+MONITORDEF_RISCV_GPR(1, |ra)
+MONITORDEF_RISCV_GPR(2, |sp)
+MONITORDEF_RISCV_GPR(3, |gp)
+MONITORDEF_RISCV_GPR(4, |tp)
+MONITORDEF_RISCV_GPR(5, |t0)
+MONITORDEF_RISCV_GPR(6, |t1)
+MONITORDEF_RISCV_GPR(7, |t2)
+MONITORDEF_RISCV_GPR(8, |s0|fp)
+MONITORDEF_RISCV_GPR(9, |s1)
+MONITORDEF_RISCV_GPR(10, |a0)
+MONITORDEF_RISCV_GPR(11, |a1)
+MONITORDEF_RISCV_GPR(12, |a2)
+MONITORDEF_RISCV_GPR(13, |a3)
+MONITORDEF_RISCV_GPR(14, |a4)
+MONITORDEF_RISCV_GPR(15, |a5)
+MONITORDEF_RISCV_GPR(16, |a6)
+MONITORDEF_RISCV_GPR(17, |a7)
+MONITORDEF_RISCV_GPR(18, |s2)
+MONITORDEF_RISCV_GPR(19, |s3)
+MONITORDEF_RISCV_GPR(20, |s4)
+MONITORDEF_RISCV_GPR(21, |s5)
+MONITORDEF_RISCV_GPR(22, |s6)
+MONITORDEF_RISCV_GPR(23, |s7)
+MONITORDEF_RISCV_GPR(24, |s8)
+MONITORDEF_RISCV_GPR(25, |s9)
+MONITORDEF_RISCV_GPR(26, |s10)
+MONITORDEF_RISCV_GPR(27, |s11)
+MONITORDEF_RISCV_GPR(28, |t3)
+MONITORDEF_RISCV_GPR(29, |t4)
+MONITORDEF_RISCV_GPR(30, |t5)
+MONITORDEF_RISCV_GPR(31, |t6)
+
+{ },
+};
+
+const MonitorDef *target_monitor_defs(void)
+{
+return monitor_defs;
+}
+
+int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
+{
+
+target_ulong ret_value;
+CPURISCVState *const env = _CPU (cs)->env;
+riscv_csr_operations *op;
+for (op = csr_ops; 1[_ops] > op; ++op) {
+if (!op->name) {
+continue;
+}
+if (!strcmp(name, op->name)) {
+if (RISCV_EXCP_NONE != riscv_csrrw_debug(env, op - csr_ops,
+ _value,
+ 0 /* new_value */,
+ 0 /* write_mask */))
+return -1;
+*pval = ret_value;
+return 0;
+}
+}
+return -1;
+}
--
Konrad Schwarz
[PATCH v1 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register
The RISC-V Debug Support specification suggests debuggers provide "virtual debug registers" to show state not directly visible in the ISA, and defines one such register, `priv', which encodes the processor's current operating mode in the two least significant bits. GDB represents virtual debug registers in the `org.gnu.gdb.riscv.virtual' feature of RISC-V target descriptions. This patch adds the `v' (hypervisor virtualization mode) bit to `priv' as specified by section 4.9.1 of version 1.0 of the RISC-V Debug Support specification. Signed-off-by: Konrad Schwarz --- gdb-xml/riscv-32bit-virtual.xml | 30 -- gdb-xml/riscv-64bit-virtual.xml | 30 -- target/riscv/gdbstub.c | 5 - 3 files changed, 60 insertions(+), 5 deletions(-) diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml index 905f1c555d..7dad42cd67 100644 --- a/gdb-xml/riscv-32bit-virtual.xml +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -5,7 +5,33 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + - - + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml index 62d86c237b..02c234670d 100644 --- a/gdb-xml/riscv-64bit-virtual.xml +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -5,7 +5,33 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> + + - - + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9c3f68eeaf..b3fa9f864e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -136,7 +136,10 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) #ifdef CONFIG_USER_ONLY return gdb_get_regl(buf, 0); #else -return gdb_get_regl(buf, cs->priv); + RISCVCPU *const cpu = RISCV_CPU(cs); + CPURISCVState *const env = >env; +return gdb_get_regl(buf, riscv_cpu_virt_enabled(env) << 2 | cs->priv); + /* per RISCV Debug Spec 1.0, 4.9.1 */ #endif } return 0; -- Konrad Schwarz
[PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers'
Display more CSRs in the 'info registers' command
and group them according to function.
The number of CSRs in RISC-V is so large to make it impractical
for all CSRs to be displayed by 'info registers'.
The code uses conditional compilation directives around register
groups; advanced users can enable/disable register
groups as required.
Signed-off-by: Konrad Schwarz
---
target/riscv/cpu.c | 327 +
1 file changed, 303 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..eb9518fc16 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -244,40 +245,318 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
#ifndef CONFIG_USER_ONLY
{
static const int dump_csrs[] = {
+
+# if 0
+CSR_USTATUS,
+CSR_UIE,
+CSR_UTVEC,
+
+/* User Trap Handling */
+CSR_USCRATCH,
+CSR_UEPC,
+CSR_UCAUSE,
+CSR_UTVAL,
+CSR_UIP,
+# endif
+
+/* User Floating-Point CSRs */
+CSR_FFLAGS,
+CSR_FRM,
+CSR_FCSR,
+
+/* User Vector CSRs */
+CSR_VSTART,
+CSR_VXSAT,
+CSR_VXRM,
+CSR_VL,
+CSR_VTYPE,
+
+# if 0
+/* User Timers and Counters */
+CSR_CYCLE,
+CSR_TIME,
+CSR_INSTRET,
+CSR_HPMCOUNTER3,
+CSR_HPMCOUNTER4,
+CSR_HPMCOUNTER5,
+CSR_HPMCOUNTER6,
+CSR_HPMCOUNTER7,
+CSR_HPMCOUNTER8,
+CSR_HPMCOUNTER9,
+CSR_HPMCOUNTER10,
+CSR_HPMCOUNTER11,
+CSR_HPMCOUNTER12,
+CSR_HPMCOUNTER13,
+CSR_HPMCOUNTER14,
+CSR_HPMCOUNTER15,
+CSR_HPMCOUNTER16,
+CSR_HPMCOUNTER17,
+CSR_HPMCOUNTER18,
+CSR_HPMCOUNTER19,
+CSR_HPMCOUNTER20,
+CSR_HPMCOUNTER21,
+CSR_HPMCOUNTER22,
+CSR_HPMCOUNTER23,
+CSR_HPMCOUNTER24,
+CSR_HPMCOUNTER25,
+CSR_HPMCOUNTER26,
+CSR_HPMCOUNTER27,
+CSR_HPMCOUNTER28,
+CSR_HPMCOUNTER29,
+CSR_HPMCOUNTER30,
+CSR_HPMCOUNTER31,
+CSR_CYCLEH,
+CSR_TIMEH,
+CSR_INSTRETH,
+CSR_HPMCOUNTER3H,
+CSR_HPMCOUNTER4H,
+CSR_HPMCOUNTER5H,
+CSR_HPMCOUNTER6H,
+CSR_HPMCOUNTER7H,
+CSR_HPMCOUNTER8H,
+CSR_HPMCOUNTER9H,
+CSR_HPMCOUNTER10H,
+CSR_HPMCOUNTER11H,
+CSR_HPMCOUNTER12H,
+CSR_HPMCOUNTER13H,
+CSR_HPMCOUNTER14H,
+CSR_HPMCOUNTER15H,
+CSR_HPMCOUNTER16H,
+CSR_HPMCOUNTER17H,
+CSR_HPMCOUNTER18H,
+CSR_HPMCOUNTER19H,
+CSR_HPMCOUNTER20H,
+CSR_HPMCOUNTER21H,
+CSR_HPMCOUNTER22H,
+CSR_HPMCOUNTER23H,
+CSR_HPMCOUNTER24H,
+CSR_HPMCOUNTER25H,
+CSR_HPMCOUNTER26H,
+CSR_HPMCOUNTER27H,
+CSR_HPMCOUNTER28H,
+CSR_HPMCOUNTER29H,
+CSR_HPMCOUNTER30H,
+CSR_HPMCOUNTER31H,
+# endif
+
+# if 0
+/* Machine Timers and Counters */
+CSR_MCYCLE,
+CSR_MINSTRET,
+CSR_MCYCLEH,
+CSR_MINSTRETH,
+# endif
+
+/* Machine Information Registers */
+CSR_MVENDORID,
+CSR_MARCHID,
+CSR_MIMPID,
CSR_MHARTID,
+
+/* Machine Trap Setup */
CSR_MSTATUS,
-CSR_MSTATUSH,
-CSR_HSTATUS,
-CSR_VSSTATUS,
-CSR_MIP,
-CSR_MIE,
-CSR_MIDELEG,
-CSR_HIDELEG,
+CSR_MISA,
CSR_MEDELEG,
-CSR_HEDELEG,
+CSR_MIDELEG,
+CSR_MIE,
CSR_MTVEC,
-CSR_STVEC,
-CSR_VSTVEC,
+CSR_MCOUNTEREN,
+
+# if defined TARGET_RISCV32
+/* 32-bit only */
+CSR_MSTATUSH,
+# endif
+
+/* Machine Trap Handling */
+CSR_MSCRATCH,
CSR_MEPC,
-CSR_SEPC,
-CSR_VSEPC,
CSR_MCAUSE,
-CSR_SCAUSE,
-CSR_VSCAUSE,
CSR_MTVAL,
+CSR_MIP,
+
+/* Supervisor Trap Setup */
+CSR_SSTATUS,
+CSR_SEDELEG,
+CSR_SIDELEG,
+CSR_SIE,
+CSR_STVEC,
+CSR_SCOUNTEREN,
+
+/* Supervisor Trap Handling */
+
