Re: [PATCH V2 2/4] intel-iommu: drop VTDBus
On Fri, Apr 22, 2022 at 9:17 AM Peter Xu wrote:
>
> Hi, Jason,
>
> Mostly good to me, just a few nitpicks below.
>
> On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> > We introduce VTDBus structure as an intermediate step for searching
> > the address space. This works well with SID based matching/lookup. But
> > when we want to support SID plus PASID based address space lookup,
> > this intermediate steps turns out to be a burden. So the patch simply
> > drops the VTDBus structure and use the PCIBus and devfn as the key for
> > the g_hash_table(). This simplifies the codes and the future PASID
> > extension.
> >
> > To prevent being slower for past vtd_find_as_from_bus_num() callers, a
> > vtd_as cache indexed by the bus number is introduced to store the last
> > recent search result of a vtd_as belongs to a specific bus.
> >
> > Signed-off-by: Jason Wang
> > ---
> > hw/i386/intel_iommu.c | 238 +-
> > include/hw/i386/intel_iommu.h | 11 +-
> > 2 files changed, 123 insertions(+), 126 deletions(-)
> >
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 90964b201c..5851a17d0e 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -61,6 +61,16 @@
> > }
> >\
> > }
> >
> > +/*
> > + * PCI bus number (or SID) is not reliable since the device is usaully
> > + * initalized before guest can configure the PCI bridge
> > + * (SECONDARY_BUS_NUMBER).
> > + */
> > +struct vtd_as_key {
> > +PCIBus *bus;
> > +uint8_t devfn;
> > +};
> > +
> > static void vtd_address_space_refresh_all(IntelIOMMUState *s);
> > static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
> >
> > @@ -210,6 +220,31 @@ static guint vtd_uint64_hash(gconstpointer v)
> > return (guint)*(const uint64_t *)v;
> > }
> >
> > +static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2)
> > +{
> > +const struct vtd_as_key *key1 = v1;
> > +const struct vtd_as_key *key2 = v2;
> > +
> > +return (key1->bus == key2->bus) && (key1->devfn == key2->devfn);
> > +}
> > +
> > +static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
> > +{
> > +return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
> > +}
>
> Nit: we could directly drop this one and use PCI_BUILD_BDF().
Will fix.
>
> > +
> > +/*
> > + * Note that we use pointer to PCIBus as the key, so hashing/shifting
> > + * based on the pointer value is intended.
>
> Thanks for the comment; that helps.
>
> Should we also mention that this hash is not the only interface to identify
> two vtd_as*, say, even if on a 32bit system we got last 24 bits collapsed
> on two vtd_as* pointers, we can still have vtd_as_equal() to guard us?
Ok. let me add that in the next version.
>
> > + */
> > +static guint vtd_as_hash(gconstpointer v)
> > +{
> > +const struct vtd_as_key *key = v;
> > +guint value = (guint)(uintptr_t)key->bus;
> > +
> > +return (guint)(value << 8 | key->devfn);
> > +}
> > +
> > static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
> >gpointer user_data)
> > {
> > @@ -248,22 +283,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key,
> > gpointer value,
> > static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
> > {
> > VTDAddressSpace *vtd_as;
> > -VTDBus *vtd_bus;
> > -GHashTableIter bus_it;
> > -uint32_t devfn_it;
> > +GHashTableIter as_it;
> >
> > trace_vtd_context_cache_reset();
> >
> > -g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
> > +g_hash_table_iter_init(&as_it, s->vtd_as);
> >
> > -while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
> > -for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
> > -vtd_as = vtd_bus->dev_as[devfn_it];
> > -if (!vtd_as) {
> > -continue;
> > -}
> > -vtd_as->context_cache_entry.context_cache_gen = 0;
> > -}
> > +while (g_hash_table_iter_next (&as_it, NULL, (void**)&vtd_as)) {
> > +vtd_as->context_cache_entry.context_cache_gen = 0;
> > }
> > s->context_cache_gen = 1;
> > }
> > @@ -993,32 +1020,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte,
> > uint32_t level)
> > return slpte & rsvd_mask;
> > }
> >
> > -/* Find the VTD address space associated with a given bus number */
> > -static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t
> > bus_num)
> > -{
> > -VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
> > -GHashTableIter iter;
> > -
> > -if (vtd_bus) {
> > -return vtd_bus;
> > -}
> > -
> > -/*
> > - * Iterate over the registered buses to find the one which
> > - * currently holds this bus number and update the bus_num
> > - * lookup table.
> > - */
> > -g_hash_table_iter_init(&iter, s->vtd_
Re: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry
On Fri, Apr 22, 2022 at 8:13 AM Peter Xu wrote: > > On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote: > > > If not, do we want to apply this version scheme only when it > > > reaches the production quality or also in the experimental phase? > > > > Yes. E.g if we think scalable mode is mature, we can enable 3.0. > > Sorry to come back to the discussion late.. > > I'd say unless someone (or some organization) strongly ask for a stable > interface for scalable mode (better with some developer looking after it > along with the organization), until then we start with versioning. > > Otherwise I hope we can be free to break the interface assuming things are > still evolving, just like the spec. Right, according to the discussion, as long as we don't think it's mature enough to be capable of version X. We won't introduce the version. Thanks > > Thanks, > > -- > Peter Xu >
[PATCH v2 1/1] hw/i386/amd_iommu: Fix IOMMU event log encoding errors
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID 1487116/1487200/1487190/1487232/1487115/1487258
Reported-by: Peter Maydell
Signed-off-by: Wei Huang
---
hw/i386/amd_iommu.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index ea8eaeb330b6..725f69095b9e 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -201,15 +201,18 @@ static void amdvi_setevent_bits(uint64_t *buffer,
uint64_t value, int start,
/*
* AMDVi event structure
*0:15 -> DeviceID
- *55:63 -> event type + miscellaneous info
- *63:127 -> related address
+ *48:63 -> event type + miscellaneous info
+ *64:127 -> related address
*/
static void amdvi_encode_event(uint64_t *evt, uint16_t devid, uint64_t addr,
uint16_t info)
{
+evt[0] = 0;
+evt[1] = 0;
+
amdvi_setevent_bits(evt, devid, 0, 16);
-amdvi_setevent_bits(evt, info, 55, 8);
-amdvi_setevent_bits(evt, addr, 63, 64);
+amdvi_setevent_bits(evt, info, 48, 16);
+amdvi_setevent_bits(evt, addr, 64, 64);
}
/* log an error encountered during a page walk
*
@@ -218,7 +221,7 @@ static void amdvi_encode_event(uint64_t *evt, uint16_t
devid, uint64_t addr,
static void amdvi_page_fault(AMDVIState *s, uint16_t devid,
hwaddr addr, uint16_t info)
{
-uint64_t evt[4];
+uint64_t evt[2];
info |= AMDVI_EVENT_IOPF_I | AMDVI_EVENT_IOPF;
amdvi_encode_event(evt, devid, addr, info);
@@ -234,7 +237,7 @@ static void amdvi_page_fault(AMDVIState *s, uint16_t devid,
static void amdvi_log_devtab_error(AMDVIState *s, uint16_t devid,
hwaddr devtab, uint16_t info)
{
-uint64_t evt[4];
+uint64_t evt[2];
info |= AMDVI_EVENT_DEV_TAB_HW_ERROR;
@@ -248,7 +251,8 @@ static void amdvi_log_devtab_error(AMDVIState *s, uint16_t
devid,
*/
static void amdvi_log_command_error(AMDVIState *s, hwaddr addr)
{
-uint64_t evt[4], info = AMDVI_EVENT_COMMAND_HW_ERROR;
+uint64_t evt[2];
+uint16_t info = AMDVI_EVENT_COMMAND_HW_ERROR;
amdvi_encode_event(evt, 0, addr, info);
amdvi_log_event(s, evt);
@@ -261,7 +265,7 @@ static void amdvi_log_command_error(AMDVIState *s, hwaddr
addr)
static void amdvi_log_illegalcom_error(AMDVIState *s, uint16_t info,
hwaddr addr)
{
-uint64_t evt[4];
+uint64_t evt[2];
info |= AMDVI_EVENT_ILLEGAL_COMMAND_ERROR;
amdvi_encode_event(evt, 0, addr, info);
@@ -276,7 +280,7 @@ static void amdvi_log_illegalcom_error(AMDVIState *s,
uint16_t info,
static void amdvi_log_illegaldevtab_error(AMDVIState *s, uint16_t devid,
hwaddr addr, uint16_t info)
{
-uint64_t evt[4];
+uint64_t evt[2];
info |= AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY;
amdvi_encode_event(evt, devid, addr, info);
@@ -288,7 +292,7 @@ static void amdvi_log_illegaldevtab_error(AMDVIState *s,
uint16_t devid,
static void amdvi_log_pagetab_error(AMDVIState *s, uint16_t devid,
hwaddr addr, uint16_t info)
{
-uint64_t evt[4];
+uint64_t evt[2];
info |= AMDVI_EVENT_PAGE_TAB_HW_ERROR;
amdvi_encode_event(evt, devid, addr, info);
--
2.35.1
Re: [libvirt] [PATCH RESEND v2 0/4] re-introduce
On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote: > > On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote: > > > > Change log: > > v2: rebased the patchset. Laine's response is appended at the end. > > > > I am re-introducing the patchset for which got > > reverted here few months back: > > > > https://www.spinics.net/linux/fedora/libvir/msg224089.html > > > > The reason for the reversal was that there seemed to be some > > instability/issues around the use of the qemu commandline which this > > patchset tries to support. In particular, some guest operating systems > > did not like the way QEMU was trying to disable native hotplug on pcie > > root ports. Subsequently, in QEMU 6.2, we have changed our mechanism > > using which we disable native hotplug. As I understand, we do not have > > any reported issues so far in 6.2 around this area. QEMU will enter a > > soft feature freeze in the first week of march in prep for 7.0 release. > > Right. But unfortunately we did not yet really work on > a sane interface for this. Ok so are we going to do something about this? I am still very unclear as to what would be a sane interface both for i440fx and q35 (pci and pcie). > > The way I see it, at high level we thinkably need two flags > - disable ACPI hotplug > - enable native hotplug (maybe separately for pci and pcie?) > > and with both enabled guests actually can switch between > the two. > > This will at least reflect the hardware, so has a chance to be > stable. > > The big question however would be what is the actual use-case. > Without that this begs the question of why do we bother at all. > To allow hotplug of bridges? If it is really necessary for us then > we should think hard about questions that surround this: > > - how does one hotplug a pcie switch? > - any way to use e.g. dynamic ACPI to support hotplug of bridges? > - do we want to bite the bullet and create an option for management > to fully control guest memory layout including all pci devices? > > > > > Libvirt is also entering a new release cycle phaze. Hence, I am > > introducing this patchset early enough in the release cycles so that if > > we do see any issues on the qemu side during the rc0, rc1 cycles and if > > reversal of this patchset is again required, it can be done in time > > before the next libvirt release end of March. > > > > All the patches in this series had been previously reviewed. Some > > subsequent fixes were made after my initial patches were pushed. I have > > squashed all those fixes and consolidated them into four patches. I have > > also updated the documentation to reflect the new changes from the QEMU > > side and rebased my changes fixing the tests in the process. > > > > What changed in QEMU post version 6.1 ? > > = > > > > We have made basically two major changes in QEMU. First is this change: > > > > (1) commit 211afe5c69b597acf85fdd577eb497f5be1ffbd8 > > Author: Julia Suvorova > > Date: Fri Nov 12 06:08:56 2021 -0500 > > > > hw/i386/acpi-build: Deny control on PCIe Native Hot-plug in _OSC > > > > There are two ways to enable ACPI PCI Hot-plug: > > > > * Disable the Hot-plug Capable bit on PCIe slots. > > > > This was the first approach which led to regression [1-2], as > > I/O space for a port is allocated only when it is hot-pluggable, > > which is determined by HPC bit. > > > > * Leave the HPC bit on and disable PCIe Native Hot-plug in _OSC > > method. > > > > This removes the (future) ability of hot-plugging switches with PCIe > > Native hotplug since ACPI PCI Hot-plug only works with cold-plugged > > bridges. If the user wants to explicitely use this feature, they can > > disable ACPI PCI Hot-plug with: > > --global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off > > > > Change the bit in _OSC method so that the OS selects ACPI PCI Hot-plug > > instead of PCIe Native. > > > > [1] https://gitlab.com/qemu-project/qemu/-/issues/641 > > [2] https://bugzilla.redhat.com/show_bug.cgi?id=2006409 > > > > Signed-off-by: Julia Suvorova > > Signed-off-by: Igor Mammedov > > Message-Id: <2022110857.3116853-5-imamm...@redhat.com> > > Reviewed-by: Ani Sinha > > Reviewed-by: Michael S. Tsirkin > > Signed-off-by: Michael S. Tsirkin > > > > > > The patch description says it all. Instead of masking out the HPC bit in > > pcie slots, we keep them turned on. Instead, we do not advertize native > > hotplug capability for PCIE using _OSC control method. See section > > 6.2.11 in ACPI spec 6.2. At the same time, we turn on ACPI hotplug for > > these slots so now the guest OS can select ACPI hotplug instead. > > > > The second change is introduction of a property with which we keep the > > existing behavior for pc-q35-6.1 machines. This means HPC bit is masked > > and ACPI hotplug is enabled by default for pcie root ports. > > The QEMU
[PATCH v5 0/3] aspeed/hace: Support AST2600 HACE
This patch series implements ast2600 hace engine with accumulative mode and unit test against to it. Verified with following models - AST2600 with OpenBmc VERSION_ID=2.12.0-dev-660-g4c7b3e692-dirty - check hash verification in uboot and check whether qemu crashed during openbmc web gui login. - AST1030 with ASPEED zephyr SDK v1.04 - run `hash sha256` command in zephyr shell to verify aspeed hace. Please help to review. Thanks, Steven Changes in v5: - Move iov cache related variables into AspeedHACEState. - Update vmstate and reset_handler for new added attributes in AspeedHACEState. Steven Lee (3): aspeed/hace: Support HMAC Key Buffer register. aspeed/hace: Support AST2600 HACE tests/qtest: Add test for Aspeed HACE accumulative mode hw/misc/aspeed_hace.c | 139 +-- include/hw/misc/aspeed_hace.h | 5 ++ tests/qtest/aspeed_hace-test.c | 145 + 3 files changed, 284 insertions(+), 5 deletions(-) -- 2.17.1
[PATCH v5 1/3] aspeed/hace: Support HMAC Key Buffer register.
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 10f00e65f4..59fe5bfca2 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -27,6 +27,7 @@
#define R_HASH_SRC (0x20 / 4)
#define R_HASH_DEST (0x24 / 4)
+#define R_HASH_KEY_BUFF (0x28 / 4)
#define R_HASH_SRC_LEN (0x2c / 4)
#define R_HASH_CMD (0x30 / 4)
@@ -210,6 +211,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr,
uint64_t data,
case R_HASH_DEST:
data &= ahc->dest_mask;
break;
+case R_HASH_KEY_BUFF:
+data &= ahc->key_mask;
+break;
case R_HASH_SRC_LEN:
data &= 0x0FFF;
break;
@@ -333,6 +337,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x0FFF;
ahc->dest_mask = 0x0FF8;
+ahc->key_mask = 0x0FC0;
ahc->hash_mask = 0x03ff; /* No SG or SHA512 modes */
}
@@ -351,6 +356,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x3fff;
ahc->dest_mask = 0x3ff8;
+ahc->key_mask = 0x3FC0;
ahc->hash_mask = 0x03ff; /* No SG or SHA512 modes */
}
@@ -369,6 +375,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x7FFF;
ahc->dest_mask = 0x7FF8;
+ahc->key_mask = 0x7FF8;
ahc->hash_mask = 0x00147FFF;
}
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 94d5ada95f..2242945eb4 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -37,6 +37,7 @@ struct AspeedHACEClass {
uint32_t src_mask;
uint32_t dest_mask;
+uint32_t key_mask;
uint32_t hash_mask;
};
--
2.17.1
[PATCH v5 2/3] aspeed/hace: Support AST2600 HACE
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the initial state is already set by
crypto library (gcrypt/glib/...), so skip this step.
2. Calculating accumulative hash digest.
(a) When receiving the last accumulative data, software need to add
padding message at the end of the accumulative data. Padding
message described in specific of MD5, SHA-1, SHA224, SHA256,
SHA512, SHA512/224, SHA512/256.
* Since the crypto library (gcrypt/glib) already pad the
padding message internally.
* This patch is to remove the padding message which fed byguest
machine driver.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 132 --
include/hw/misc/aspeed_hace.h | 4 ++
2 files changed, 131 insertions(+), 5 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 59fe5bfca2..3164f6 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -65,7 +65,6 @@
#define SG_LIST_ADDR_SIZE 4
#define SG_LIST_ADDR_MASK 0x7FFF
#define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE)
-#define ASPEED_HACE_MAX_SG 256/* max number of entries */
static const struct {
uint32_t mask;
@@ -95,11 +94,104 @@ static int hash_algo_lookup(uint32_t reg)
return -1;
}
-static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)
+/**
+ * Check whether the request contains padding message.
+ *
+ * @param s aspeed hace state object
+ * @param iov iov of current request
+ * @param req_len length of the current request
+ * @param total_msg_len length of all acc_mode requests(excluding padding msg)
+ * @param pad_offsetstart offset of padding message
+ */
+static bool has_padding(AspeedHACEState *s, struct iovec *iov,
+hwaddr req_len, uint32_t *total_msg_len,
+uint32_t *pad_offset)
+{
+*total_msg_len = (uint32_t)(ldq_be_p(iov->iov_base + req_len - 8) / 8);
+/*
+ * SG_LIST_LEN_LAST asserted in the request length doesn't mean it is the
+ * last request. The last request should contain padding message.
+ * We check whether message contains padding by
+ * 1. Get total message length. If the current message contains
+ * padding, the last 8 bytes are total message length.
+ * 2. Check whether the total message length is valid.
+ * If it is valid, the value should less than or equal to
+ * total_req_len.
+ * 3. Current request len - padding_size to get padding offset.
+ * The padding message's first byte should be 0x80
+ */
+if (*total_msg_len <= s->total_req_len) {
+uint32_t padding_size = s->total_req_len - *total_msg_len;
+uint8_t *padding = iov->iov_base;
+*pad_offset = req_len - padding_size;
+if (padding[*pad_offset] == 0x80) {
+return true;
+}
+}
+
+return false;
+}
+
+static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id,
+ uint32_t *pad_offset)
+{
+int i, iov_count;
+if (pad_offset != 0) {
+s->iov_cache[s->iov_count].iov_base = iov[id].iov_base;
+s->iov_cache[s->iov_count].iov_len = *pad_offset;
+++s->iov_count;
+}
+for (i = 0; i < s->iov_count; i++) {
+iov[i].iov_base = s->iov_cache[i].iov_base;
+iov[i].iov_len = s->iov_cache[i].iov_len;
+}
+iov_count = s->iov_count;
+s->iov_count = 0;
+s->total_req_len = 0;
+return iov_count;
+}
+
+/**
+ * Generate iov for accumulative mode.
+ *
+ * @param s aspeed hace state object
+ * @param iov iov of the current request
+ * @param idindex of the current iov
+ * @param req_len length of the current request
+ *
+ * @return count of iov
+ */
+static int gen_acc_mode_iov(AspeedHACEState *s, struct iovec *iov, int id,
+hwaddr *req_len)
+{
+uint32_t pad_offset;
+uint32_t total_msg_len;
+s->total_req_len += *req_len;
+
+if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {
+if (s->iov_count) {
+return reconstruct_iov(s, iov, id, &pad_offset);
+}
+
+*req_len -= s->total_req_len - total_msg_len;
+s->total_req_len = 0;
+iov[id].iov_len = *req_len;
+} else {
+s->iov_cache[s->iov_count].iov_base = iov->iov_base;
+s->iov_cache[s->iov_count].iov_len = *req_len;
+++s->iov_count;
+}
+
+return id + 1;
+}
+
+static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
+
[PATCH v5 3/3] tests/qtest: Add test for Aspeed HACE accumulative mode
This add two addition test cases for accumulative mode under sg enabled.
The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).
The result was calculated by command line sha512sum/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Acked-by: Thomas Huth
Reviewed-by: Joel Stanley
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
index 58aa22014d..85d705ec50 100644
--- a/tests/qtest/aspeed_hace-test.c
+++ b/tests/qtest/aspeed_hace-test.c
@@ -20,6 +20,7 @@
#define HACE_ALGO_SHA512(BIT(5) | BIT(6))
#define HACE_ALGO_SHA384(BIT(5) | BIT(6) | BIT(10))
#define HACE_SG_EN BIT(18)
+#define HACE_ACCUM_EN BIT(8)
#define HACE_STS 0x1c
#define HACE_RSA_ISRBIT(13)
@@ -95,6 +96,57 @@ static const uint8_t test_result_sg_sha256[] = {
0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3,
0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4};
+/*
+ * The accumulative mode requires firmware to provide internal initial state
+ * and message padding (including length L at the end of padding).
+ *
+ * This test vector is a ascii text "abc" with padding message.
+ *
+ * Expected results were generated using command line utitiles:
+ *
+ * echo -n -e 'abc' | dd of=/tmp/test
+ * for hash in sha512sum sha256sum; do $hash /tmp/test; done
+ */
+static const uint8_t test_vector_accum_512[] = {
+0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};
+
+static const uint8_t test_vector_accum_256[] = {
+0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};
+
+static const uint8_t test_result_accum_sha512[] = {
+0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
+0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
+0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
+0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
+0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
+0xa5, 0x4c, 0xa4, 0x9f};
+
+static const uint8_t test_result_accum_sha256[] = {
+0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde,
+0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
+0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
static void write_regs(QTestState *s, uint32_t base, uint32_t src,
uint32_t length, uint32_t out, uint32_t method)
@@ -307,6 +359,86 @@ static void test_sha512_sg(const char *machine, const
uint32_t base,
qtest_quit(s);
}
+static void test_sha256_accum(const char *machine, const uint32_t base,
+const uint32_t src_addr)
+{
+QTestState *s = qtest_init(machine);
+
+const uint32_t buffer_addr = src_addr + 0x100;
+const uint32_t digest_addr = src_addr + 0x400;
+uint8_t digest[32] = {0};
+struct AspeedSgList array[] = {
+{ cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
+ cpu_to_le32(buffer_addr) },
+};
+
+/* Check engine is idle, no busy or irq bits set */
+g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
+
+/* Write test vector into memory */
+qtest_memwrite(s, buffer_addr, test_vector_accum_256,
sizeof(test_vector_accum_256));
+qtest_memwrite(s, src_addr, array, sizeof(array));
+
+write_regs(s, base, src_addr, sizeof(test_vector_accum_256),
+ digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN);
+
+/* Check hash IRQ status is asserted */
+
Re: [PATCH v8 02/17] qdev: unplug blocker for devices
Jag Raman writes:
>> On Apr 21, 2022, at 10:55 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Add blocker to prevent hot-unplug of devices
>>
>> Why do you need this? I'm not doubting you do, I just want to read your
>> reasons here :)
>
> Hi Markus, :)
>
> The x-vfio-user-server depends on an attached PCIDevice. As long as
> x-vfio-user-server
> is used, we don’t want the PCIDevice to be unplugged. This blocker prevents
> an user
> from removing PCIDevice while the vfio-user server is in use.
Please work that into your commit message. Perhaps along the lines of
One of the next commits will do . will happen when
the PCI device is unplugged. Create the means to prevent that.
>>> Signed-off-by: Elena Ufimtseva
>>> Signed-off-by: John G Johnson
>>> Signed-off-by: Jagannathan Raman
>
> I recall receiving a “Reviewed-by” from Stefan previously.
>
> I’m very sorry I didn’t add that here. I’ll go over all the patches once
> again to confirm that
> the “Reviewed-by” status reflects accurately.
>
>>> ---
>>> include/hw/qdev-core.h | 29 +
>>> hw/core/qdev.c | 24
>>> softmmu/qdev-monitor.c | 4
>>> 3 files changed, 57 insertions(+)
>>>
>>> diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
>>> index 92c3d65208..1b9fa25e5c 100644
>>> --- a/include/hw/qdev-core.h
>>> +++ b/include/hw/qdev-core.h
>>> @@ -193,6 +193,7 @@ struct DeviceState {
>>> int instance_id_alias;
>>> int alias_required_for_version;
>>> ResettableState reset;
>>> +GSList *unplug_blockers;
>>> };
>>>
>>> struct DeviceListener {
>>> @@ -419,6 +420,34 @@ void qdev_simple_device_unplug_cb(HotplugHandler
>>> *hotplug_dev,
>>> void qdev_machine_creation_done(void);
>>> bool qdev_machine_modified(void);
>>>
>>> +/*
>>> + * qdev_add_unplug_blocker: Adds an unplug blocker to a device
>>> + *
>>> + * @dev: Device to be blocked from unplug
>>> + * @reason: Reason for blocking
>>> + */
>>> +void qdev_add_unplug_blocker(DeviceState *dev, Error *reason);
>>> +
>>> +/*
>>> + * qdev_del_unplug_blocker: Removes an unplug blocker from a device
>>> + *
>>> + * @dev: Device to be unblocked
>>> + * @reason: Pointer to the Error used with qdev_add_unplug_blocker.
>>> + * Used as a handle to lookup the blocker for deletion.
>>> + */
>>> +void qdev_del_unplug_blocker(DeviceState *dev, Error *reason);
>>> +
>>> +/*
>>> + * qdev_unplug_blocked: Confirms if a device is blocked from unplug
>>> + *
>>> + * @dev: Device to be tested
>>> + * @reason: Returns one of the reasons why the device is blocked,
>>> + * if any
>>> + *
>>> + * Returns: true if device is blocked from unplug, false otherwise
>>> + */
>>> +bool qdev_unplug_blocked(DeviceState *dev, Error **errp);
>>> +
>>> /**
>>> * GpioPolarity: Polarity of a GPIO line
>>> *
>>> diff --git a/hw/core/qdev.c b/hw/core/qdev.c
>>> index 84f3019440..0806d8fcaa 100644
>>> --- a/hw/core/qdev.c
>>> +++ b/hw/core/qdev.c
>>> @@ -468,6 +468,28 @@ char *qdev_get_dev_path(DeviceState *dev)
>>> return NULL;
>>> }
>>>
>>> +void qdev_add_unplug_blocker(DeviceState *dev, Error *reason)
>>> +{
>>> +dev->unplug_blockers = g_slist_prepend(dev->unplug_blockers, reason);
>>> +}
>>> +
>>> +void qdev_del_unplug_blocker(DeviceState *dev, Error *reason)
>>> +{
>>> +dev->unplug_blockers = g_slist_remove(dev->unplug_blockers, reason);
>>> +}
>>> +
>>> +bool qdev_unplug_blocked(DeviceState *dev, Error **errp)
>>> +{
>>> +ERRP_GUARD();
>>> +
>>> +if (dev->unplug_blockers) {
>>> +error_propagate(errp, error_copy(dev->unplug_blockers->data));
>>> +return true;
>>> +}
>>> +
>>> +return false;
>>> +}
>>
>> This cites the most recently added blocker as reason. Your function
>> comment covers it: "Returns one of the reasons". Okay.
>
> I could change the comment to say that it returns the recently added reason.
Up to you.
Re: [PATCH v8 10/17] vfio-user: run vfio-user context
Jag Raman writes:
>> On Apr 21, 2022, at 10:59 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Setup a handler to run vfio-user context. The context is driven by
>>> messages to the file descriptor associated with it - get the fd for
>>> the context and hook up the handler with it
>>>
>>> Signed-off-by: Elena Ufimtseva
>>> Signed-off-by: John G Johnson
>>> Signed-off-by: Jagannathan Raman
>>> Reviewed-by: Stefan Hajnoczi
>>> ---
>>> qapi/misc.json| 23 ++
>>> hw/remote/vfio-user-obj.c | 95 ++-
>>> 2 files changed, 117 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/qapi/misc.json b/qapi/misc.json
>>> index b83cc39029..f3cc4a4854 100644
>>> --- a/qapi/misc.json
>>> +++ b/qapi/misc.json
>>> @@ -553,3 +553,26 @@
>>> ##
>>> { 'event': 'RTC_CHANGE',
>>> 'data': { 'offset': 'int', 'qom-path': 'str' } }
>>> +
>>> +##
>>> +# @VFU_CLIENT_HANGUP:
>>> +#
>>> +# Emitted when the client of a TYPE_VFIO_USER_SERVER closes the
>>> +# communication channel
>>> +#
>>> +# @id: ID of the TYPE_VFIO_USER_SERVER object
>>> +#
>>> +# @device: ID of attached PCI device
>>
>> Is this the ID set with -device id=... and such?
>
> Yes, that is correct. It’s the ID set with the “-device id=…” option/
What happens when the device was added *without* id=...? DeviceState
member @id is null then.
I figure we need to make @device optional here, present if the device
has an ID. I recommend to also add a member @qom-path, like we did for
MEMORY_DEVICE_SIZE_CHANGE in commit d89dd28f0e2.
Re: [PULL 00/18] migration queue
On 4/21/22 11:40, Dr. David Alan Gilbert (git) wrote: From: "Dr. David Alan Gilbert" The following changes since commit 28298069afff3eb696e4995e63b2579b27adf378: Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-04-21 09:27:54 -0700) are available in the Git repository at: https://gitlab.com/dagrh/qemu.git tags/pull-migration-20220421a for you to fetch changes up to 552de79bfdd5e9e53847eb3c6d6e4cd898a4370e: migration: Read state once (2022-04-21 19:36:46 +0100) V2: Migration pull 2022-04-21 Dan: Test fixes and improvements (TLS mostly) Peter: Postcopy improvements Me: Race fix for info migrate, and compilation fix V2: Fixed checkpatch nit of unneeded NULL check Signed-off-by: Dr. David Alan Gilbert Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Daniel P. Berrangé (9): tests: improve error message when saving TLS PSK file fails tests: support QTEST_TRACE env variable tests: print newline after QMP response in qtest logs migration: fix use of TLS PSK credentials with a UNIX socket tests: switch MigrateStart struct to be stack allocated tests: merge code for UNIX and TCP migration pre-copy tests tests: introduce ability to provide hooks for migration precopy test tests: switch migration FD passing test to use common precopy helper tests: expand the migration precopy helper to support failures Dr. David Alan Gilbert (2): migration: Fix operator type migration: Read state once Peter Xu (7): migration: Postpone releasing MigrationState.hostname migration: Drop multifd tls_hostname cache migration: Add pss.postcopy_requested status migration: Move migrate_allow_multifd and helpers into migration.c migration: Export ram_load_postcopy() migration: Move channel setup out of postcopy_try_recover() migration: Allow migrate-recover to run multiple times migration/channel.c | 1 - migration/migration.c | 66 --- migration/migration.h | 4 +- migration/multifd.c | 29 +-- migration/multifd.h | 4 - migration/ram.c | 10 +- migration/ram.h | 1 + migration/savevm.c | 3 - migration/tls.c | 4 - tests/qtest/libqtest.c | 13 +- tests/qtest/migration-test.c| 368 tests/unit/crypto-tls-psk-helpers.c | 2 +- 12 files changed, 267 insertions(+), 238 deletions(-)
[PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 9 +
target/riscv/cpu.h | 4
target/riscv/csr.c | 38 ++
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c774056c5..ace68ed855 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
+ (QEMU_VERSION_MINOR << 8) | \
+ (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
@@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34c22d5d3b..46c66fbf8e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -393,6 +393,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+uint32_t mvendorid;
+uint64_t marchid;
+uint64_t mipid;
+
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ba85e7b5d..1c2d3f7193 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+*val = cpu->cfg.mvendorid;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+*val = cpu->cfg.marchid;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+*val = cpu->cfg.mipid;
+return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
-[CSR_MVENDORID] = { "mvendorid", any, read_zero},
-[CSR_MARCHID] = { "marchid", any, read_zero},
-[CSR_MIMPID]= { "mimpid",any, read_zero},
-[CSR_MHARTID] = { "mhartid", any, read_mhartid },
+[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
+[CSR_MARCHID] = { "marchid", any, read_marchid },
+[CSR_MIMPID]= { "mimpid",any, read_mipid },
+[CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
.min_priv_ver = PRIV_VERSION_1_12_0 },
--
2.35.1
Re: [PATCH v2 1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01
+Richard On Wed, Apr 20, 2022 at 4:16 PM Bin Meng wrote: > > On Tue, Apr 12, 2022 at 9:11 AM Bin Meng wrote: > > > > On Thu, Mar 24, 2022 at 9:48 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > Sync uboot_image.h from upstream U-Boot v2022.01 release [1]. > > > > > > [1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h > > > > > > Signed-off-by: Bin Meng > > > --- > > > > > > (no changes since v1) > > > > > > hw/core/uboot_image.h | 213 -- > > > 1 file changed, 142 insertions(+), 71 deletions(-) > > > > > > > Ping? > > Ping? Richard, is that you to pick up this series? Regards, Bin
Re: [PATCH v2] target/riscv: Fix incorrect PTE merge in walk_pte
On Fri, Apr 22, 2022 at 10:53 AM Bin Meng wrote:
>
> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
> wrote:
> >
> > Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> > case, walk_pte will erroneously merge them.
> >
> > Enforce the split up, by tracking the virtual base address.
> >
> > Let's say we have the mapping:
> > 0x8120 -> 0x89623000 (4K)
> > 0x8120f000 -> 0x89624000 (4K)
> >
> > Before, walk_pte would have shown:
> >
> > vaddrpaddrsize attr
> > ---
> > 8120 89623000 2000 rwxu-ad
> >
> > as it only checks for subsequent paddrs. With this patch, it becomes:
> >
> > vaddrpaddrsize attr
> > ---
> > 8120 89623000 1000 rwxu-ad
> > 8120f000 89624000 1000 rwxu-ad
> >
> > Signed-off-by: Ralf Ramsauer
> > ---
> > target/riscv/monitor.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> > index 7efb4b62c1..9dc4cb1156 100644
> > --- a/target/riscv/monitor.c
> > +++ b/target/riscv/monitor.c
> > @@ -84,6 +84,7 @@ static void walk_pte(Monitor *mon, hwaddr base,
> > target_ulong start,
> > {
> > hwaddr pte_addr;
> > hwaddr paddr;
> > +target_ulong last_start = -1;
> > target_ulong pgsize;
> > target_ulong pte;
> > int ptshift;
> > @@ -116,7 +117,8 @@ static void walk_pte(Monitor *mon, hwaddr base,
> > target_ulong start,
> > * contiguous mapped block details.
> > */
>
> Please also update the comments above to mention the new case you added here.
>
Otherwise,
Reviewed-by: Bin Meng
Re: [PATCH v2] target/riscv: Fix incorrect PTE merge in walk_pte
On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000 (4K)
> 0x8120f000 -> 0x89624000 (4K)
>
> Before, walk_pte would have shown:
>
> vaddrpaddrsize attr
> ---
> 8120 89623000 2000 rwxu-ad
>
> as it only checks for subsequent paddrs. With this patch, it becomes:
>
> vaddrpaddrsize attr
> ---
> 8120 89623000 1000 rwxu-ad
> 8120f000 89624000 1000 rwxu-ad
>
> Signed-off-by: Ralf Ramsauer
> ---
> target/riscv/monitor.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index 7efb4b62c1..9dc4cb1156 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -84,6 +84,7 @@ static void walk_pte(Monitor *mon, hwaddr base,
> target_ulong start,
> {
> hwaddr pte_addr;
> hwaddr paddr;
> +target_ulong last_start = -1;
> target_ulong pgsize;
> target_ulong pte;
> int ptshift;
> @@ -116,7 +117,8 @@ static void walk_pte(Monitor *mon, hwaddr base,
> target_ulong start,
> * contiguous mapped block details.
> */
Please also update the comments above to mention the new case you added here.
> if ((*last_attr != attr) ||
> -(*last_paddr + *last_size != paddr)) {
> +(*last_paddr + *last_size != paddr) ||
> +(last_start + *last_size != start)) {
> print_pte(mon, va_bits, *vbase, *pbase,
>*last_paddr + *last_size - *pbase, *last_attr);
>
> @@ -125,6 +127,7 @@ static void walk_pte(Monitor *mon, hwaddr base,
> target_ulong start,
> *last_attr = attr;
> }
>
> +last_start = start;
> *last_paddr = paddr;
> *last_size = pgsize;
> } else {
> --
Regards,
Bin
Re: [PATCH v2 2/5] 9pfs: fix qemu_mknodat(S_IFSOCK) on macOS
On 2022/04/22 0:07, Christian Schoenebeck wrote:
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and chmod() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by: Christian Schoenebeck
Reviewed-by: Will Cohen
---
hw/9pfs/9p-util-darwin.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/9pfs/9p-util-darwin.c b/hw/9pfs/9p-util-darwin.c
index e24d09763a..39308f2a45 100644
--- a/hw/9pfs/9p-util-darwin.c
+++ b/hw/9pfs/9p-util-darwin.c
@@ -74,6 +74,27 @@ int fsetxattrat_nofollow(int dirfd, const char *filename,
const char *name,
*/
#if defined CONFIG_PTHREAD_FCHDIR_NP
+static int create_socket_file_at_cwd(const char *filename, mode_t mode) {
+int fd, err;
+struct sockaddr_un addr = {
+.sun_family = AF_UNIX
+};
+
+fd = socket(PF_UNIX, SOCK_DGRAM, 0);
+if (fd == -1) {
+return fd;
+}
+snprintf(addr.sun_path, sizeof(addr.sun_path), "./%s", filename);
It would result in an incorrect path if the path does not fit in
addr.sun_path. It should report an explicit error instead.
+err = bind(fd, (struct sockaddr *) &addr, sizeof(addr));
+if (err == -1) {
+goto out;
You may close(fd) as soon as bind() returns (before checking the
returned value) and eliminate goto.
+}
+err = chmod(addr.sun_path, mode);
I'm not sure if it is fine to have a time window between bind() and
chmod(). Do you have some rationale?
Regards,
Akihiko Odaki
+out:
+close(fd);
+return err;
+}
+
int qemu_mknodat(int dirfd, const char *filename, mode_t mode, dev_t dev)
{
int preserved_errno, err;
@@ -93,7 +114,11 @@ int qemu_mknodat(int dirfd, const char *filename, mode_t
mode, dev_t dev)
if (pthread_fchdir_np(dirfd) < 0) {
return -1;
}
-err = mknod(filename, mode, dev);
+if (S_ISSOCK(mode)) {
+err = create_socket_file_at_cwd(filename, mode);
+} else {
+err = mknod(filename, mode, dev);
+}
preserved_errno = errno;
/* Stop using the thread-local cwd */
pthread_fchdir_np(-1);
Re: [PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
On Mon, Apr 18, 2022 at 5:13 AM Ben Dooks wrote: > > Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify > the code. > > Signed-off-by; Ben Dooks ; should be replaced to : Not sure how you did that, but you can do with "git commit -s" and git will take care of the SoB tag. > --- > hw/riscv/sifive_u.c | 20 +++- > 1 file changed, 7 insertions(+), 13 deletions(-) > Regards, Bin
Re: [PATCH v4 6/6] hw/riscv: Enable TPM backends
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis wrote: > > From: Alistair Francis > > Imply the TPM sysbus devices. This allows users to add TPM devices to > the RISC-V virt board. > > This was tested by first creating an emulated TPM device: > > swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ > --ctrl type=unixio,path=swtpm-sock > > Then launching QEMU with: > > -chardev socket,id=chrtpm,path=swtpm-sock \ > -tpmdev emulator,id=tpm0,chardev=chrtpm \ > -device tpm-tis-device,tpmdev=tpm0 > > The TPM device can be seen in the memory tree and the generated device > tree. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942 > Signed-off-by: Alistair Francis > Reviewed-by: Edgar E. Iglesias > --- > hw/riscv/virt.c | 4 > hw/riscv/Kconfig | 1 + > 2 files changed, 5 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v4 5/6] hw/riscv: virt: Add device plug support
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis wrote: > > From: Alistair Francis > > Add support for plugging in devices, this was tested with the TPM > device. > > Signed-off-by: Alistair Francis > Reviewed-by: Edgar E. Iglesias > --- > hw/riscv/virt.c | 35 +++ > 1 file changed, 35 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v4 4/6] hw/riscv: virt: Add support for generating platform FDT entries
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis wrote: > > From: Alistair Francis > > Similar to the ARM virt machine add support for adding device tree > entries for dynamically created devices. > > Signed-off-by: Alistair Francis > Reviewed-by: Edgar E. Iglesias > --- > hw/riscv/virt.c | 25 + > 1 file changed, 25 insertions(+) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 169da70350..e4a5c6c28b 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -28,6 +28,7 @@ > #include "hw/qdev-properties.h" > #include "hw/char/serial.h" > #include "target/riscv/cpu.h" > +#include "hw/core/sysbus-fdt.h" > #include "hw/riscv/riscv_hart.h" > #include "hw/riscv/virt.h" > #include "hw/riscv/boot.h" > @@ -411,6 +412,12 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); > qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + > +platform_bus_add_all_fdt_nodes(mc->fdt, name, > + memmap[VIRT_PLATFORM_BUS].base, > + memmap[VIRT_PLATFORM_BUS].size, > + VIRT_PLATFORM_BUS_IRQ); This one is not needed. > + > g_free(name); > } > > @@ -469,6 +476,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", > plic_phandles[socket]); > + > +platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, > + memmap[VIRT_PLATFORM_BUS].base, > + memmap[VIRT_PLATFORM_BUS].size, > + VIRT_PLATFORM_BUS_IRQ); > + > g_free(plic_name); > > g_free(plic_cells); > @@ -546,6 +559,12 @@ static void create_fdt_imsic(RISCVVirtState *s, const > MemMapEntry *memmap, > IMSIC_MMIO_GROUP_MIN_SHIFT); > } > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); > + > +platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name, > + memmap[VIRT_PLATFORM_BUS].base, > + memmap[VIRT_PLATFORM_BUS].size, > + VIRT_PLATFORM_BUS_IRQ); > + > g_free(imsic_name); > > /* S-level IMSIC node */ > @@ -683,6 +702,12 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, > VIRT_IRQCHIP_NUM_SOURCES); > riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); > + > +platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, > + memmap[VIRT_PLATFORM_BUS].base, > + memmap[VIRT_PLATFORM_BUS].size, > + VIRT_PLATFORM_BUS_IRQ); > + > g_free(aplic_name); > > g_free(aplic_cells); > -- Regards, Bin
Re: [PULL 0/7] target/rx patch queue
On 4/21/22 10:31, Richard Henderson wrote: The following changes since commit 401d46789410e88e9e90d76a11f46e8e9f358d55: Merge tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-21 08:04:43 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-rx-20220421 for you to fetch changes up to 724eaecec6d22cf3842f896684bdc5b79492f093: target/rx: update PC correctly in wait instruction (2022-04-21 10:09:12 -0700) Fix usp/isp swapping upon clrpsw/setpsw. Fix psw.i/pc upon wait. Align dtb in ram. Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Richard Henderson (4): target/rx: Put tb_flags into DisasContext target/rx: Store PSW.U in tb->flags target/rx: Move DISAS_UPDATE check for write to PSW target/rx: Swap stack pointers on clrpsw/setpsw instruction Tomoaki Kawada (2): target/rx: set PSW.I when executing wait instruction target/rx: update PC correctly in wait instruction Yoshinori Sato (1): hw/rx: rx-gdbsim DTB load address aligned of 16byte. target/rx/cpu.h | 1 + hw/rx/rx-gdbsim.c | 2 +- target/rx/op_helper.c | 1 + target/rx/translate.c | 69 +++ 4 files changed, 40 insertions(+), 33 deletions(-)
Re: [PATCH v4 3/6] hw/riscv: virt: Create a platform bus
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis wrote: > > From: Alistair Francis > > Create a platform bus to allow dynamic devices to be connected. This is > based on the ARM implementation. > > Signed-off-by: Alistair Francis > Reviewed-by: Edgar E. Iglesias > --- > include/hw/riscv/virt.h | 7 - > hw/riscv/virt.c | 68 + > hw/riscv/Kconfig| 1 + > 3 files changed, 56 insertions(+), 20 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v2] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis wrote: > On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote: > > > > On Wed, Apr 20, 2022 at 5:57 PM wrote: > > > > > > From: Frank Chang > > > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > > -cpu command line option. > > > > > > The default values of marchid and mipid are built with QEMU's version > > > numbers. > > > > > > Signed-off-by: Frank Chang > > > Reviewed-by: Jim Shu > > > Reviewed-by: Alistair Francis > > > --- > > > target/riscv/cpu.c | 9 + > > > target/riscv/cpu.h | 4 > > > target/riscv/csr.c | 38 ++ > > > 3 files changed, 47 insertions(+), 4 deletions(-) > > > > > > > Reviewed-by: Bin Meng > > Do you mind rebasing this on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next ? > Sure, will do. Regards, Frank Chang > > I have sent a PR and hopefully it should be merged into master soon > > Alistair > > > >
Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
On Thu, Apr 21, 2022 at 11:51 PM Richard Henderson wrote: > > On 4/20/22 16:46, Bin Meng wrote: > > It seems you were trying to build every commit for bisectabliity? Is > > there an easy way to do such automatically? > > git rebase --exec "cd build && make" > This works! Thanks Richard. Regards, Bin
Re: [PATCH V2 2/4] intel-iommu: drop VTDBus
Hi, Jason,
Mostly good to me, just a few nitpicks below.
On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> We introduce VTDBus structure as an intermediate step for searching
> the address space. This works well with SID based matching/lookup. But
> when we want to support SID plus PASID based address space lookup,
> this intermediate steps turns out to be a burden. So the patch simply
> drops the VTDBus structure and use the PCIBus and devfn as the key for
> the g_hash_table(). This simplifies the codes and the future PASID
> extension.
>
> To prevent being slower for past vtd_find_as_from_bus_num() callers, a
> vtd_as cache indexed by the bus number is introduced to store the last
> recent search result of a vtd_as belongs to a specific bus.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 238 +-
> include/hw/i386/intel_iommu.h | 11 +-
> 2 files changed, 123 insertions(+), 126 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 90964b201c..5851a17d0e 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -61,6 +61,16 @@
> }
> \
> }
>
> +/*
> + * PCI bus number (or SID) is not reliable since the device is usaully
> + * initalized before guest can configure the PCI bridge
> + * (SECONDARY_BUS_NUMBER).
> + */
> +struct vtd_as_key {
> +PCIBus *bus;
> +uint8_t devfn;
> +};
> +
> static void vtd_address_space_refresh_all(IntelIOMMUState *s);
> static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
>
> @@ -210,6 +220,31 @@ static guint vtd_uint64_hash(gconstpointer v)
> return (guint)*(const uint64_t *)v;
> }
>
> +static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2)
> +{
> +const struct vtd_as_key *key1 = v1;
> +const struct vtd_as_key *key2 = v2;
> +
> +return (key1->bus == key2->bus) && (key1->devfn == key2->devfn);
> +}
> +
> +static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
> +{
> +return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
> +}
Nit: we could directly drop this one and use PCI_BUILD_BDF().
> +
> +/*
> + * Note that we use pointer to PCIBus as the key, so hashing/shifting
> + * based on the pointer value is intended.
Thanks for the comment; that helps.
Should we also mention that this hash is not the only interface to identify
two vtd_as*, say, even if on a 32bit system we got last 24 bits collapsed
on two vtd_as* pointers, we can still have vtd_as_equal() to guard us?
> + */
> +static guint vtd_as_hash(gconstpointer v)
> +{
> +const struct vtd_as_key *key = v;
> +guint value = (guint)(uintptr_t)key->bus;
> +
> +return (guint)(value << 8 | key->devfn);
> +}
> +
> static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
>gpointer user_data)
> {
> @@ -248,22 +283,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key,
> gpointer value,
> static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
> {
> VTDAddressSpace *vtd_as;
> -VTDBus *vtd_bus;
> -GHashTableIter bus_it;
> -uint32_t devfn_it;
> +GHashTableIter as_it;
>
> trace_vtd_context_cache_reset();
>
> -g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
> +g_hash_table_iter_init(&as_it, s->vtd_as);
>
> -while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
> -for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
> -vtd_as = vtd_bus->dev_as[devfn_it];
> -if (!vtd_as) {
> -continue;
> -}
> -vtd_as->context_cache_entry.context_cache_gen = 0;
> -}
> +while (g_hash_table_iter_next (&as_it, NULL, (void**)&vtd_as)) {
> +vtd_as->context_cache_entry.context_cache_gen = 0;
> }
> s->context_cache_gen = 1;
> }
> @@ -993,32 +1020,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte,
> uint32_t level)
> return slpte & rsvd_mask;
> }
>
> -/* Find the VTD address space associated with a given bus number */
> -static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
> -{
> -VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
> -GHashTableIter iter;
> -
> -if (vtd_bus) {
> -return vtd_bus;
> -}
> -
> -/*
> - * Iterate over the registered buses to find the one which
> - * currently holds this bus number and update the bus_num
> - * lookup table.
> - */
> -g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
> -while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
> -if (pci_bus_num(vtd_bus->bus) == bus_num) {
> -s->vtd_as_by_bus_num[bus_num] = vtd_bus;
> -return vtd_bus;
> -}
> -}
> -
> -return NULL;
> -}
> -
> /* Given the @iova, get relevant @slptep. @slpte_level will be the last
[PULL v2 29/31] target/riscv: cpu: Enable native debug feature
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-6-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 85656cdcc3..0c774056c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
+DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.35.1
[PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-7-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index fbe6b76764..78c6c6635d 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.35.1
[PULL v2 28/31] target/riscv: machine: Add debug state description
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-5-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/machine.c | 32
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 243f567949..2a437b29a1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+VMSTATE_END_OF_LIST()
+}
+};
+
+static bool debug_needed(void *opaque)
+{
+RISCVCPU *cpu = opaque;
+CPURISCVState *env = &cpu->env;
+
+return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+.name = "cpu/debug/type2",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+VMSTATE_UINTTL(maddress, type2_trigger_t),
+VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+.name = "cpu/debug",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = debug_needed,
+.fields = (VMStateField[]) {
+VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_rv128,
&vmstate_kvmtimer,
&vmstate_envcfg,
+&vmstate_debug,
NULL
}
};
--
2.35.1
[PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/debug.h | 4 +++
target/riscv/cpu.c | 3 ++
target/riscv/debug.c | 75
3 files changed, 82 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fbc5f946e2..fb21706e1c 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong
val);
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
+void riscv_cpu_debug_excp_handler(CPUState *cs);
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 94f9434411..8919928f4f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -880,6 +880,9 @@ static const struct TCGCPUOps riscv_tcg_ops = {
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
+.debug_excp_handler = riscv_cpu_debug_excp_handler,
+.debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c8cec39217..1a9392645e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index,
target_ulong val)
return write_func(env, env->trigger_cur, tdata_index, val);
}
+
+void riscv_cpu_debug_excp_handler(CPUState *cs)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = &cpu->env;
+
+if (cs->watchpoint_hit) {
+if (cs->watchpoint_hit->flags & BP_CPU) {
+cs->watchpoint_hit = NULL;
+riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+}
+} else {
+if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
+riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+}
+}
+}
+
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = &cpu->env;
+CPUBreakpoint *bp;
+target_ulong ctrl;
+target_ulong pc;
+int i;
+
+QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ctrl = env->type2_trig[i].mcontrol;
+pc = env->type2_trig[i].maddress;
+
+if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+/* check U/S/M bit against current privilege level */
+if ((ctrl >> 3) & BIT(env->priv)) {
+return true;
+}
+}
+}
+}
+
+return false;
+}
+
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = &cpu->env;
+target_ulong ctrl;
+target_ulong addr;
+int flags;
+int i;
+
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ctrl = env->type2_trig[i].mcontrol;
+addr = env->type2_trig[i].maddress;
+flags = 0;
+
+if (ctrl & TYPE2_LOAD) {
+flags |= BP_MEM_READ;
+}
+if (ctrl & TYPE2_STORE) {
+flags |= BP_MEM_WRITE;
+}
+
+if ((wp->flags & flags) && (wp->vaddr == addr)) {
+/* check U/S/M bit against current privilege level */
+if ((ctrl >> 3) & BIT(env->priv)) {
+return true;
+}
+}
+}
+
+return false;
+}
--
2.35.1
Re: [PATCH 2/2] hw/riscv: Don't add empty bootargs to device tree
On Thu, Apr 21, 2022 at 3:58 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the changes were entirely useless, due to MachineState::kernel_cmdline
> can't be NULL at all as the default value is given as an empty string.
> (see hw/core/machine.c::machine_initfn()).
>
> Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
> a segfault had already been observed by dereferencing the NULL pointer.
> It should be worded as *empty" bootargs.
>
> Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/sifive_u.c| 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c| 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index cafd1fc9ae..10a5d0e501 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -571,7 +571,7 @@ static void
> microchip_icicle_kit_machine_init(MachineState *machine)
>"linux,initrd-end", end);
> }
>
> -if (machine->kernel_cmdline) {
> +if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> qemu_fdt_setprop_string(machine->fdt, "/chosen",
> "bootargs", machine->kernel_cmdline);
> }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7fbc7dea42..cc8c7637cb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -511,7 +511,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
> *memmap,
> g_free(nodename);
>
> update_bootargs:
> -if (cmdline) {
> +if (cmdline && *cmdline) {
> qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> }
> }
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 1562b000bb..068ba3493e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -177,7 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
> *memmap,
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
>
> -if (cmdline) {
> +if (cmdline && *cmdline) {
> qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> }
> }
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index da50cbed43..a628a3abdf 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -998,7 +998,7 @@ static void create_fdt(RISCVVirtState *s, const
> MemMapEntry *memmap,
> create_fdt_flash(s, memmap);
>
> update_bootargs:
> -if (cmdline) {
> +if (cmdline && *cmdline) {
> qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
> }
> }
> --
> 2.25.1
>
>
[PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220420080901.14655-5-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
hw/intc/riscv_aclint.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 3b3ab548f6..0412edc982 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev,
Error **errp)
}
}
+static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
+{
+/*
+ * According to RISC-V ACLINT spec:
+ * - On MTIMER device reset, the MTIME register is cleared to zero.
+ * - On MTIMER device reset, the MTIMECMP registers are in unknown state.
+ */
+RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);
+
+/*
+ * Clear mtime register by writing to 0 it.
+ * Pending mtime interrupts will also be cleared at the same time.
+ */
+riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
+}
+
static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_mtimer_realize;
device_class_set_props(dc, riscv_aclint_mtimer_properties);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
+rc->phases.enter = riscv_aclint_mtimer_reset_enter;
}
static const TypeInfo riscv_aclint_mtimer_info = {
@@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev,
Error **errp)
}
}
+static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)
+{
+/*
+ * According to RISC-V ACLINT spec:
+ * - On MSWI device reset, each MSIP register is cleared to zero.
+ *
+ * p.s. SSWI device reset does nothing since SETSIP register always reads
0.
+ */
+RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj);
+int i;
+
+if (!swi->sswi) {
+for (i = 0; i < swi->num_harts; i++) {
+/* Clear MSIP registers by lowering software interrupts. */
+qemu_irq_lower(swi->soft_irqs[i]);
+}
+}
+}
+
static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_swi_realize;
device_class_set_props(dc, riscv_aclint_swi_properties);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
+rc->phases.enter = riscv_aclint_swi_reset_enter;
}
static const TypeInfo riscv_aclint_swi_info = {
--
2.35.1
[PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to perform both 32/64-bit read/write accesses to both
mtimecmp and mtime registers.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Jim Shu
Message-Id: <20220420080901.14655-3-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
hw/intc/riscv_aclint.c | 42 +++---
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 37e9ace801..ff082090fe 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -126,9 +126,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque,
hwaddr addr,
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
-/* timecmp_lo */
+/* timecmp_lo for RV32/RV64 or timecmp for RV64 */
uint64_t timecmp = env->timecmp;
-return timecmp & 0x;
+return (size == 4) ? (timecmp & 0x) : timecmp;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
uint64_t timecmp = env->timecmp;
@@ -139,8 +139,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque,
hwaddr addr,
return 0;
}
} else if (addr == mtimer->time_base) {
-/* time_lo */
-return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0x;
+/* time_lo for RV32/RV64 or timecmp for RV64 */
+uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
+return (size == 4) ? (rtc & 0x) : rtc;
} else if (addr == mtimer->time_base + 4) {
/* time_hi */
return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0x;
@@ -167,18 +168,29 @@ static void riscv_aclint_mtimer_write(void *opaque,
hwaddr addr,
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
-/* timecmp_lo */
-uint64_t timecmp_hi = env->timecmp >> 32;
-riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
-timecmp_hi << 32 | (value & 0x),
-mtimer->timebase_freq);
-return;
+if (size == 4) {
+/* timecmp_lo for RV32/RV64 */
+uint64_t timecmp_hi = env->timecmp >> 32;
+riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
hartid,
+timecmp_hi << 32 | (value & 0x),
+mtimer->timebase_freq);
+} else {
+/* timecmp for RV64 */
+riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
hartid,
+ value,
mtimer->timebase_freq);
+}
} else if ((addr & 0x7) == 4) {
-/* timecmp_hi */
-uint64_t timecmp_lo = env->timecmp;
-riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
-value << 32 | (timecmp_lo & 0x),
-mtimer->timebase_freq);
+if (size == 4) {
+/* timecmp_hi for RV32/RV64 */
+uint64_t timecmp_lo = env->timecmp;
+riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
hartid,
+value << 32 | (timecmp_lo & 0x),
+mtimer->timebase_freq);
+} else {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "aclint-mtimer: invalid timecmp_hi write: %08x",
+ (uint32_t)addr);
+}
} else {
qemu_log_mask(LOG_UNIMP,
"aclint-mtimer: invalid timecmp write: %08x",
--
2.35.1
Re: [PATCH 1/2] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
On Thu, Apr 21, 2022 at 3:57 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the adding '/chosen/stdout-path' property in device tree
> is determined by whether a kernel command line is provided, which is
> wrong. It should be added unconditionally.
>
> Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/spike.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index d059a67f9b..1562b000bb 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -174,10 +174,11 @@ static void create_fdt(SpikeState *s, const MemMapEntry
> *memmap,
>
> riscv_socket_fdt_write_distance_matrix(mc, fdt);
>
> +qemu_fdt_add_subnode(fdt, "/chosen");
> +qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
> +
> if (cmdline) {
> -qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> -qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
> }
> }
>
> --
> 2.25.1
>
>
[PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
From: Niklas Cassel
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
option is disabled using rv32,mmu=off or rv64,mmu=off.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
Signed-off-by: Niklas Cassel
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220414155510.1364147-1-niklas.cas...@wdc.com>
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 09609c96e8..b49c5361bd 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -230,8 +230,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(mc->fdt, cpu_name);
-qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
-(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_MMU)) {
+qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+} else {
+qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+"riscv,none");
+}
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.35.1
[PULL v2 26/31] target/riscv: cpu: Add a config option for native debug
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-3-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 4 +++-
target/riscv/cpu.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5d1259d4ae..34c22d5d3b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -79,7 +79,8 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
-RISCV_FEATURE_AIA
+RISCV_FEATURE_AIA,
+RISCV_FEATURE_DEBUG
};
/* Privileged specification version */
@@ -405,6 +406,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool aia;
+bool debug;
uint64_t resetvec;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8919928f4f..477961b619 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -548,6 +548,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
+if (cpu->cfg.debug) {
+riscv_set_feature(env, RISCV_FEATURE_DEBUG);
+}
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -795,6 +799,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.35.1
Re: [PATCH RESEND v1 0/2] i386: Make PIT and PIC the property of common x86 base machine type
On 3/10/2022 9:07 PM, Michael S. Tsirkin wrote:
On Thu, Mar 10, 2022 at 08:28:09PM +0800, Xiaoyao Li wrote:
For PIT, it's straightforward to merge microvm::pit and
pc_machine::pit_enabled into x86ms::pit
For PIC, move microvm::pic to x86ms:pic, which gives PC machine the
ability to dis-/en-able PIC and it's the preparation for future TDX
support.
Looks ok but we are in freeze. I will tag this but pls do ping me
after the release to make sure it's not lost. Thanks!
Michael,
Hope they won't get lost :)
---
Resend:
- collect Reviewed-by;
- rebase to 2048c4eba2b4 ("Merge remote-tracking branch
'remotes/philmd/tags/pmbus-20220308' into staging")
Xiaoyao Li (2):
hw/i386: Make pit a property of common x86 base machine type
hw/i386: Make pic a property of common x86 base machine type
hw/i386/microvm.c | 54 ++-
hw/i386/pc.c | 24 +++--
hw/i386/pc_piix.c | 4 ++-
hw/i386/pc_q35.c | 4 ++-
hw/i386/x86.c | 50
include/hw/i386/microvm.h | 4 ---
include/hw/i386/pc.h | 2 --
include/hw/i386/x86.h | 4 +++
8 files changed, 65 insertions(+), 81 deletions(-)
--
2.27.0
[PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM
From: Ralf Ramsauer
The -bios option is silently ignored if used in combination with -enable-kvm.
The reason is that the machine starts in S-Mode, and the bios typically runs in
M-Mode.
Better exit in that case to not confuse the user.
Signed-off-by: Ralf Ramsauer
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Anup Patel
Message-Id: <20220401121842.2791796-1-ralf.ramsa...@oth-regensburg.de>
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index da50cbed43..09609c96e8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1308,12 +1308,18 @@ static void virt_machine_init(MachineState *machine)
/*
* Only direct boot kernel is currently supported for KVM VM,
- * so the "-bios" parameter is ignored and treated like "-bios none"
- * when KVM is enabled.
+ * so the "-bios" parameter is not supported when KVM is enabled.
*/
if (kvm_enabled()) {
-g_free(machine->firmware);
-machine->firmware = g_strdup("none");
+if (machine->firmware) {
+if (strcmp(machine->firmware, "none")) {
+error_report("Machine mode firmware is not supported in "
+ "combination with KVM.");
+exit(1);
+}
+} else {
+machine->firmware = g_strdup("none");
+}
}
if (riscv_is_32bit(&s->soc[0])) {
--
2.35.1
Re: [PATCH v2] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote: > > On Wed, Apr 20, 2022 at 5:57 PM wrote: > > > > From: Frank Chang > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > The default values of marchid and mipid are built with QEMU's version > > numbers. > > > > Signed-off-by: Frank Chang > > Reviewed-by: Jim Shu > > Reviewed-by: Alistair Francis > > --- > > target/riscv/cpu.c | 9 + > > target/riscv/cpu.h | 4 > > target/riscv/csr.c | 38 ++ > > 3 files changed, 47 insertions(+), 4 deletions(-) > > > > Reviewed-by: Bin Meng Do you mind rebasing this on https://github.com/alistair23/qemu/tree/riscv-to-apply.next ? I have sent a PR and hopefully it should be merged into master soon Alistair >
[PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address.
From: Dylan Jhong
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec() also needs to be modified
Signed-off-by: Dylan Jhong
Reviewed-by: Alistair Francis
Message-Id: <20220419115945.37945-1-dy...@andestech.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h | 4 ++--
hw/riscv/boot.c | 12 +++-
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index d937c5c224..d2db29721a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -46,12 +46,12 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
-uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
+uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState
*harts,
hwaddr saddr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
- uint32_t fdt_load_addr, void *fdt);
+ uint64_t fdt_load_addr, void *fdt);
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0f179d3601..57a41df8e9 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -212,9 +212,9 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t
mem_size,
return *start + size;
}
-uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
{
-uint32_t temp, fdt_addr;
+uint64_t temp, fdt_addr;
hwaddr dram_end = dram_base + mem_size;
int ret, fdtsize = fdt_totalsize(fdt);
@@ -229,7 +229,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
mem_size, void *fdt)
* Thus, put it at an 16MB aligned address that less than fdt size from the
* end of dram or 3GB whichever is lesser.
*/
-temp = MIN(dram_end, 3072 * MiB);
+temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
ret = fdt_pack(fdt);
@@ -285,13 +285,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
RISCVHartArrayState *harts
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
- uint32_t fdt_load_addr, void *fdt)
+ uint64_t fdt_load_addr, void *fdt)
{
int i;
uint32_t start_addr_hi32 = 0x;
+uint32_t fdt_load_addr_hi32 = 0x;
if (!riscv_is_32bit(harts)) {
start_addr_hi32 = start_addr >> 32;
+fdt_load_addr_hi32 = fdt_load_addr >> 32;
}
/* reset vector */
uint32_t reset_vec[10] = {
@@ -304,7 +306,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
RISCVHartArrayState *harts
start_addr, /* start: .dword */
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
-0x,
+fdt_load_addr_hi32,
/* fw_dyn: */
};
if (riscv_is_32bit(harts)) {
--
2.35.1
[PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults
From: Richard Henderson The riscv_raise_exception function stores its argument into exception_index and then exits to the main loop. When we have already set exception_index, we can just exit directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220401125948.79292-2-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1c60fb2e80..126251d5da 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); -riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); +cpu_loop_exit_restore(cs, retaddr); } void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); -riscv_raise_exception(env, cs->exception_index, retaddr); +cpu_loop_exit_restore(cs, retaddr); } bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, first_stage_error, riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx)); -riscv_raise_exception(env, cs->exception_index, retaddr); +cpu_loop_exit_restore(cs, retaddr); } return true; -- 2.35.1
[PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension
From: Bin Meng
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220315065529.62198-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/debug.h | 108 +
target/riscv/debug.c | 339 +++
target/riscv/meson.build | 1 +
4 files changed, 453 insertions(+)
create mode 100644 target/riscv/debug.h
create mode 100644 target/riscv/debug.c
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b90ca8268e..ff3eee4087 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -106,6 +106,7 @@ typedef struct CPUArchState CPURISCVState;
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
+#include "debug.h"
#endif
#define RV_VLEN_MAX 1024
@@ -279,6 +280,10 @@ struct CPUArchState {
pmp_table_t pmp_state;
target_ulong mseccfg;
+/* trigger module */
+target_ulong trigger_cur;
+type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
+
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(uint32_t);
uint32_t rdtime_fn_arg;
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
new file mode 100644
index 00..fbc5f946e2
--- /dev/null
+++ b/target/riscv/debug.h
@@ -0,0 +1,108 @@
+/*
+ * QEMU RISC-V Native Debug Support
+ *
+ * Copyright (c) 2022 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see
[PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time delta value
between the mtime value to be written and the timer value at the time
mtime is written. Time delta value is then added back whenever the timer
value is retrieved.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Message-Id: <20220420080901.14655-4-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
include/hw/intc/riscv_aclint.h | 1 +
target/riscv/cpu.h | 8 ++--
hw/intc/riscv_aclint.c | 71 --
target/riscv/cpu_helper.c | 4 +-
4 files changed, 57 insertions(+), 27 deletions(-)
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 229bd08d25..26d4048687 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -31,6 +31,7 @@
typedef struct RISCVAclintMTimerState {
/*< private >*/
SysBusDevice parent_obj;
+uint64_t time_delta;
/*< public >*/
MemoryRegion mmio;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ff3eee4087..5d1259d4ae 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,8 +285,8 @@ struct CPUArchState {
type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
/* machine specific rdtime callback */
-uint64_t (*rdtime_fn)(uint32_t);
-uint32_t rdtime_fn_arg;
+uint64_t (*rdtime_fn)(void *);
+void *rdtime_fn_arg;
/* machine specific AIA ireg read-modify-write callback */
#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
@@ -496,8 +496,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
- uint32_t arg);
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
+ void *arg);
void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
int (*rmw_fn)(void *arg,
target_ulong reg,
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index ff082090fe..3b3ab548f6 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback {
int num;
} riscv_aclint_mtimer_callback;
-static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
+static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
timebase_freq, NANOSECONDS_PER_SECOND);
}
+static uint64_t cpu_riscv_read_rtc(void *opaque)
+{
+RISCVAclintMTimerState *mtimer = opaque;
+return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta;
+}
+
/*
* Called when timecmp is written to update the QEMU timer or immediately
* trigger timer interrupt if mtimecmp <= current timer value.
@@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
RISCVCPU *cpu,
int hartid,
- uint64_t value,
- uint32_t timebase_freq)
+ uint64_t value)
{
+uint32_t timebase_freq = mtimer->timebase_freq;
uint64_t next;
uint64_t diff;
-uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
+uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
cpu->env.timecmp = value;
if (cpu->env.timecmp <= rtc_r) {
@@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque,
hwaddr addr,
}
} else if (addr == mtimer->time_base) {
/* time_lo for RV32/RV64 or timecmp for RV64 */
-uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
+uint64_t rtc = cpu_riscv_read_rtc(mtimer);
return (size == 4) ? (rtc & 0x) : rtc;
} else if (addr == mtimer->time_base + 4) {
/* time_hi */
-return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0x;
+return (cpu_riscv_read_rtc(mtimer) >> 32) & 0x;
}
qemu_log_mask(LOG_UNIMP,
@@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr
addr,
uint64_t value, unsigned size)
{
RISCVAclintMTimerState *mtimer = opaque;
+int i;
if (addr >= mtimer->timecmp_base &&
[PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-4-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4
target/riscv/csr.c | 57
target/riscv/debug.c | 27 +
4 files changed, 90 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fb21706e1c..27b9cac6b4 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+void riscv_trigger_init(CPURISCVState *env);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 477961b619..85656cdcc3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -466,6 +466,10 @@ static void riscv_cpu_reset(DeviceState *dev)
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
+if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+riscv_trigger_init(env);
+}
+
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a09126a011..6ba85e7b5d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException debug(CPURISCVState *env, int csrno)
+{
+if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+return RISCV_EXCP_NONE;
+}
+
+return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
/* User Floating-Point CSRs */
@@ -2677,6 +2686,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_tselect(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = tselect_csr_read(env);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tselect(CPURISCVState *env, int csrno,
+target_ulong val)
+{
+tselect_csr_write(env, val);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_tdata(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+/* return 0 in tdata1 to end the trigger enumeration */
+if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
+*val = 0;
+return RISCV_EXCP_NONE;
+}
+
+if (!tdata_available(env, csrno - CSR_TDATA1)) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+*val = tdata_csr_read(env, csrno - CSR_TDATA1);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tdata(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+if (!tdata_available(env, csrno - CSR_TDATA1)) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+tdata_csr_write(env, csrno - CSR_TDATA1, val);
+return RISCV_EXCP_NONE;
+}
+
/*
* Functions to access Pointer Masking feature registers
* We have to check if current priv lvl could modify
@@ -3418,6 +3469,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+/* Debug CSRs */
+[CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
+[CSR_TDATA1]= { "tdata1", debug, read_tdata, write_tdata },
+[CSR_TDATA2]= { "tdata2", debug, read_tdata, write_tdata },
+[CSR_TDATA3]= { "tdata3", debug, read_tdata, write_tdata },
+
/* User Pointer Masking */
[CSR_UMTE]={ "umte",pointer_masking, read_umte,write_umte
},
[CSR_UPMMASK] ={ "upmmask", pointer_masking, read_upmmask,
write_upmmask },
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1a9392645e..2f2a51c732 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
return false;
}
+
+void riscv_trigger_init(CPURISCVState *env)
+{
+target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+int i;
+
+/* type 2 triggers */
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+/*
+ * type = TRIGGER_TYPE_AD_MATCH
+ * dmode = 0 (both debug and M-mode can write tdata)
+ * maskmax = 0 (unimplemented, always 0)
+ * sizehi = 0 (match against any size, RV64 only)
+ * hit = 0 (unimplemented, always 0)
+ * select = 0 (always 0, perform match on address)
+ * timing = 0 (always 0, trigger before instruction)
+ * sizelo = 0 (match against any size)
+ * action = 0 (always 0, raise a breakpoint exception)
+
[PULL v2 14/31] target/riscv: misa to ISA string conversion fix
From: Tsukasa OI
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-letter extensions.
This commit also removes all reserved/dropped single-letter "extensions"
from the list.
- "B": Not going to be a single-letter extension (misa.B is reserved).
- "J": Not going to be a single-letter extension (misa.J is reserved).
- "K": Not going to be a single-letter extension (misa.K is reserved).
- "L": Dropped.
- "N": Dropped.
- "T": Dropped.
It also clarifies that the variable `riscv_single_letter_exts' is a
single-letter extension order list.
Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
Message-Id:
<4a4c11213a161a7eedabe46abe58b351bb0e2ef2.1648473008.git.research_tra...@irq.a4lg.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cfdfe787de..edc33c44dd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,7 +34,7 @@
/* RISC-V CPU definitions */
-static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
+static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
@@ -911,12 +911,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
-const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
+const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
char *isa_str = g_new(char, maxlen);
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
-for (i = 0; i < sizeof(riscv_exts); i++) {
-if (cpu->env.misa_ext & RV(riscv_exts[i])) {
-*p++ = qemu_tolower(riscv_exts[i]);
+for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
+if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
+*p++ = qemu_tolower(riscv_single_letter_exts[i]);
}
}
*p = '\0';
--
2.35.1
[PULL v2 13/31] target/riscv: optimize helper for vmvr.v
From: Weiwei Li
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
the same helper
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220325085902.29500-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/vector_helper.c| 29 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +--
3 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 26bbab2fab..a669d0187b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7a6ce0a3bc..99f3134aa0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
/* Vector Whole Register Move */
-#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
-void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
- uint32_t desc) \
-{ \
-/* EEW = 8 */ \
-uint32_t maxsz = simd_maxsz(desc); \
-uint32_t i = env->vstart; \
- \
-memcpy((uint8_t *)vd + H1(i), \
- (uint8_t *)vs2 + H1(i), \
- maxsz - env->vstart); \
- \
-env->vstart = 0; \
-}
+void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
+{
+/* EEW = 8 */
+uint32_t maxsz = simd_maxsz(desc);
+uint32_t i = env->vstart;
+
+memcpy((uint8_t *)vd + H1(i),
+ (uint8_t *)vs2 + H1(i),
+ maxsz - env->vstart);
-GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
-GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
-GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
-GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
+env->vstart = 0;
+}
/* Vector Integer Extension */
#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1)\
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index b336d57270..90327509f7 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
* Whole Vector Register Move Instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 16.6)
*/
-#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
@@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME *
a) \
} else {\
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
-\
-static gen_helper_gvec_2_ptr * const fns[4] = { \
-gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
-gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
-}; \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
- cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
+ cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \
gen_set_label(over);\
} \
@@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s,
[PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow
From: Nicolas Pitre
There is an overflow with the current code where a pmpaddr value of
0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0x.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper results.
Signed-off-by: Nicolas Pitre
Reviewed-by: Alistair Francis
Message-Id:
Signed-off-by: Alistair Francis
---
target/riscv/pmp.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 81b61bb65c..151da3fa08 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -141,17 +141,9 @@ static void pmp_decode_napot(target_ulong a, target_ulong
*sa, target_ulong *ea)
0111... 2^(XLEN+2)-byte NAPOT range
... Reserved
*/
-if (a == -1) {
-*sa = 0u;
-*ea = -1;
-return;
-} else {
-target_ulong t1 = ctz64(~a);
-target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
-target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
-*sa = base;
-*ea = base + range;
-}
+a = (a << 2) | 0x3;
+*sa = a & (a + 1);
+*ea = a | (a + 1);
}
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
--
2.35.1
[PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesses.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Jim Shu
Message-Id: <20220420080901.14655-2-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
hw/intc/riscv_aclint.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e43b050e92..37e9ace801 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = {
.valid = {
.min_access_size = 4,
.max_access_size = 8
+},
+.impl = {
+.min_access_size = 4,
+.max_access_size = 8,
}
};
--
2.35.1
[PULL v2 08/31] target/riscv: Enable privileged spec version 1.12
From: Atish Patra
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-7-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 8 +---
target/riscv/csr.c | 5 +
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..c3fd018ecb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
-set_priv_version(env, PRIV_VERSION_1_11_0);
+set_priv_version(env, PRIV_VERSION_1_12_0);
}
#if defined(TARGET_RISCV64)
@@ -503,7 +503,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.priv_spec) {
-if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+priv_version = PRIV_VERSION_1_12_0;
+} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
@@ -518,7 +520,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (priv_version) {
set_priv_version(env, priv_version);
} else if (!env->priv_ver) {
-set_priv_version(env, PRIV_VERSION_1_11_0);
+set_priv_version(env, PRIV_VERSION_1_12_0);
}
if (cpu->cfg.mmu) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 84a398b205..8b6a1b90f1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2975,6 +2975,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
int read_only = get_field(csrno, 0xC00) == 3;
+int csr_min_priv = csr_ops[csrno].min_priv_ver;
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
@@ -3007,6 +3008,10 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+if (env->priv_ver < csr_min_priv) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
return csr_ops[csrno].predicate(env, csrno);
}
--
2.35.1
[PULL v2 09/31] target/riscv: cpu: Fixup indentation
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-2-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c3fd018ecb..78fc7b22ed 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -569,18 +569,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
- return;
- }
+return;
+}
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
error_setg(errp,
"Either I or E extension must be set");
- return;
- }
+return;
+}
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
- cpu->cfg.ext_a & cpu->cfg.ext_f &
- cpu->cfg.ext_d)) {
+if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+cpu->cfg.ext_a & cpu->cfg.ext_f &
+cpu->cfg.ext_d)) {
warn_report("Setting G will also set IMAFD");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
@@ -711,11 +711,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
- if (kvm_enabled()) {
+if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
- } else {
+} else {
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
- }
+}
break;
default:
g_assert_not_reached();
--
2.35.1
[PULL v2 16/31] target/riscv: fix start byte for vmvr.v when vstart != 0
From: Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Message-Id: <20220330021316.18223-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 99f3134aa0..576b14e5a3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
/* Vector Whole Register Move */
void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
{
-/* EEW = 8 */
+/* EEW = SEW */
uint32_t maxsz = simd_maxsz(desc);
-uint32_t i = env->vstart;
+uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
+uint32_t startb = env->vstart * sewb;
+uint32_t i = startb;
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
- maxsz - env->vstart);
+ maxsz - startb);
env->vstart = 0;
}
--
2.35.1
[PULL v2 12/31] target/riscv: optimize condition assign for scale < 0
From: Weiwei Li
for some cases, scale is always equal or less than 0, since lmul is not larger
than 3
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20220325085902.29500-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8d675db9a2..b336d57270 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
static inline uint32_t MAXSZ(DisasContext *s)
{
int scale = s->lmul - 3;
-return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+return s->cfg_ptr->vlen >> -scale;
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
-int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+int vlmax = s->cfg_ptr->vlen >> -scale;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
-int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+int vlmax = s->cfg_ptr->vlen >> -scale;
if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
--
2.35.1
[PULL v2 07/31] target/riscv: Add *envcfg* CSRs support
From: Atish Patra
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-6-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h | 39 +++
target/riscv/csr.c | 107
target/riscv/machine.c | 23 +
4 files changed, 174 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5139110c4f..e129c3da7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -304,6 +304,11 @@ struct CPUArchState {
target_ulong spmbase;
target_ulong upmmask;
target_ulong upmbase;
+
+/* CSRs for execution enviornment configuration */
+uint64_t menvcfg;
+target_ulong senvcfg;
+uint64_t henvcfg;
#endif
target_ulong cur_pmmask;
target_ulong cur_pmbase;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 48d92a81c3..4a9e4f7d09 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -202,6 +202,9 @@
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
+/* Supervisor Configuration CSRs */
+#define CSR_SENVCFG 0x10A
+
/* Supervisor Trap Handling */
#define CSR_SSCRATCH0x140
#define CSR_SEPC0x141
@@ -247,6 +250,10 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
+/* Hypervisor Configuration CSRs */
+#define CSR_HENVCFG 0x60A
+#define CSR_HENVCFGH0x61A
+
/* Virtual CSRs */
#define CSR_VSSTATUS0x200
#define CSR_VSIE0x204
@@ -290,6 +297,10 @@
#define CSR_VSIEH 0x214
#define CSR_VSIPH 0x254
+/* Machine Configuration CSRs */
+#define CSR_MENVCFG 0x30A
+#define CSR_MENVCFGH0x31A
+
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH0x757
@@ -663,6 +674,34 @@ typedef enum RISCVException {
#define PM_EXT_CLEAN0x0002ULL
#define PM_EXT_DIRTY0x0003ULL
+/* Execution enviornment configuration bits */
+#define MENVCFG_FIOM BIT(0)
+#define MENVCFG_CBIE (3UL << 4)
+#define MENVCFG_CBCFE BIT(6)
+#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_PBMTE (1ULL << 62)
+#define MENVCFG_STCE (1ULL << 63)
+
+/* For RV32 */
+#define MENVCFGH_PBMTE BIT(30)
+#define MENVCFGH_STCE BIT(31)
+
+#define SENVCFG_FIOM MENVCFG_FIOM
+#define SENVCFG_CBIE MENVCFG_CBIE
+#define SENVCFG_CBCFE MENVCFG_CBCFE
+#define SENVCFG_CBZE MENVCFG_CBZE
+
+#define HENVCFG_FIOM MENVCFG_FIOM
+#define HENVCFG_CBIE MENVCFG_CBIE
+#define HENVCFG_CBCFE MENVCFG_CBCFE
+#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_PBMTE MENVCFG_PBMTE
+#define HENVCFG_STCE MENVCFG_STCE
+
+/* For RV32 */
+#define HENVCFGH_PBMTE MENVCFGH_PBMTE
+#define HENVCFGH_STCE MENVCFGH_STCE
+
/* Offsets for every pair of control bits per each priv level */
#define XS_OFFSET0ULL
#define U_OFFSET 2ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6590cc8aa7..84a398b205 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1398,6 +1398,101 @@ static RISCVException write_mtval(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+/* Execution environment configuration setup */
+static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = env->menvcfg;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
+
+if (riscv_cpu_mxl(env) == MXL_RV64) {
+mask |= MENVCFG_PBMTE | MENVCFG_STCE;
+}
+env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = env->menvcfg >> 32;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+uint64_t valh = (uint64_t)val << 32;
+
+env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_senvcfg
[PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops.
From: Atish Patra
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
However, it doesn't enforce the privilege version in this commit.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-4-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 2 +
target/riscv/csr.c | 103 ++---
2 files changed, 70 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 19c3b6610b..5139110c4f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -658,6 +658,8 @@ typedef struct {
riscv_csr_op_fn op;
riscv_csr_read128_fn read128;
riscv_csr_write128_fn write128;
+/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
+uint32_t min_priv_ver;
} riscv_csr_operations;
/* CSR function table constants */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 341c2e6f23..1400027158 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3070,13 +3070,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm},
[CSR_FCSR] = { "fcsr", fs, read_fcsr,write_fcsr },
/* Vector CSRs */
-[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
-[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat },
-[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm },
-[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr },
-[CSR_VL] = { "vl", vs, read_vl},
-[CSR_VTYPE]= { "vtype",vs, read_vtype },
-[CSR_VLENB]= { "vlenb",vs, read_vlenb },
+[CSR_VSTART] = { "vstart", vs,read_vstart, write_vstart,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VXSAT]= { "vxsat",vs,read_vxsat, write_vxsat,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VXRM] = { "vxrm", vs,read_vxrm,write_vxrm,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VCSR] = { "vcsr", vs,read_vcsr,write_vcsr,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VL] = { "vl", vs,read_vl,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VTYPE]= { "vtype",vs,read_vtype,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VLENB]= { "vlenb",vs,read_vlenb,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
/* User Timers and Counters */
[CSR_CYCLE]= { "cycle",ctr,read_instret },
[CSR_INSTRET] = { "instret", ctr,read_instret },
@@ -3185,33 +3192,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
-[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
write_hstatus },
-[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
write_hedeleg },
-[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
rmw_hideleg },
-[CSR_HVIP]= { "hvip",hmode, NULL, NULL, rmw_hvip
},
-[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip
},
-[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie
},
-[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
write_hcounteren },
-[CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
write_hgeie },
-[CSR_HTVAL] = { "htval", hmode, read_htval,
write_htval },
-[CSR_HTINST] = { "htinst", hmode, read_htinst,
write_htinst },
-[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
},
-[CSR_HGATP] = { "hgatp", hmode, read_hgatp,
write_hgatp },
-[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta },
-[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
write_htimedeltah },
-
-[CSR_VSSTATUS]= { "vsstatus",hmode, read_vsstatus,
write_vsstatus},
-[CSR_VSIP]= { "vsip",hmode, NULL,NULL,rmw_vsip
},
-[CSR_VSIE]= { "vsie",hmode, NULL,NULL,rmw_vsie
},
-[CSR_VSTVEC]
[PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree
From: Atish Patra
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by appending the available ISA extensions
to the "riscv,isa" string if it is enabled so that kernel can process it.
[1] https://lkml.org/lkml/2022/2/15/263
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Atish Patra
Suggested-by: Heiko Stubner
Signed-off-by: Atish Patra
Message-Id: <20220329195657.1725425-1-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 60 ++
1 file changed, 60 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index edc33c44dd..94f9434411 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -36,6 +36,11 @@
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+struct isa_ext_data {
+const char *name;
+bool enabled;
+};
+
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -908,6 +913,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
device_class_set_props(dc, riscv_cpu_properties);
}
+#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
+
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int
max_str_len)
+{
+char *old = *isa_str;
+char *new = *isa_str;
+int i;
+
+/**
+ * Here are the ordering rules of extension naming defined by RISC-V
+ * specification :
+ * 1. All extensions should be separated from other multi-letter extensions
+ *by an underscore.
+ * 2. The first letter following the 'Z' conventionally indicates the most
+ *closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ *If multiple 'Z' extensions are named, they should be ordered first
+ *by category, then alphabetically within a category.
+ * 3. Standard supervisor-level extensions (starts with 'S') should be
+ *listed after standard unprivileged extensions. If multiple
+ *supervisor-level extensions are listed, they should be ordered
+ *alphabetically.
+ * 4. Non-standard extensions (starts with 'X') must be listed after all
+ *standard extensions. They must be separated from other multi-letter
+ *extensions by an underscore.
+ */
+struct isa_ext_data isa_edata_arr[] = {
+ISA_EDATA_ENTRY(zfh, ext_zfh),
+ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+ISA_EDATA_ENTRY(zdinx, ext_zdinx),
+ISA_EDATA_ENTRY(zba, ext_zba),
+ISA_EDATA_ENTRY(zbb, ext_zbb),
+ISA_EDATA_ENTRY(zbc, ext_zbc),
+ISA_EDATA_ENTRY(zbs, ext_zbs),
+ISA_EDATA_ENTRY(zve32f, ext_zve32f),
+ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+ISA_EDATA_ENTRY(svinval, ext_svinval),
+ISA_EDATA_ENTRY(svnapot, ext_svnapot),
+ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+};
+
+for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+if (isa_edata_arr[i].enabled) {
+new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+g_free(old);
+old = new;
+}
+}
+
+*isa_str = new;
+}
+
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
@@ -920,6 +979,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
}
}
*p = '\0';
+riscv_isa_string_ext(cpu, &isa_str, maxlen);
return isa_str;
}
--
2.35.1
[PULL v2 10/31] target/riscv: Allow software access to MIP SEIP
From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or software to
set the bit, which is incorrect.
This patch removes the miclaim mask when writing MIP to allow M-mode
software to inject interrupts, even with an interrupt controller.
We then also need to keep track of which source is setting MIP_SEIP. The
final value is a OR of both, so we add two bools and use that to keep
track of the current state. This way either source can change without
losing the correct value.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-3-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.h | 8
target/riscv/cpu.c | 10 +-
target/riscv/csr.c | 8 ++--
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e129c3da7d..b90ca8268e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -177,6 +177,14 @@ struct CPUArchState {
uint64_t mstatus;
uint64_t mip;
+/*
+ * MIP contains the software writable version of SEIP ORed with the
+ * external interrupt value. The MIP register is always up-to-date.
+ * To keep track of the current source, we also save booleans of the values
+ * here.
+ */
+bool external_seip;
+bool software_seip;
uint64_t miclaim;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 78fc7b22ed..cfdfe787de 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -708,7 +708,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
case IRQ_VS_TIMER:
case IRQ_M_TIMER:
case IRQ_U_EXT:
-case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
if (kvm_enabled()) {
@@ -717,6 +716,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
}
break;
+case IRQ_S_EXT:
+if (kvm_enabled()) {
+kvm_riscv_set_irq(cpu, irq, level);
+} else {
+env->external_seip = level;
+riscv_cpu_update_mip(cpu, 1 << irq,
+ BOOL_TO_MASK(level | env->software_seip));
+}
+break;
default:
g_assert_not_reached();
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8b6a1b90f1..a09126a011 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1498,10 +1498,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int
csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVCPU *cpu = env_archcpu(env);
-/* Allow software control of delegable interrupts not claimed by hardware
*/
-uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
+uint64_t old_mip, mask = wr_mask & delegable_ints;
uint32_t gin;
+if (mask & MIP_SEIP) {
+env->software_seip = new_val & MIP_SEIP;
+new_val |= env->external_seip * MIP_SEIP;
+}
+
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
} else {
--
2.35.1
[PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering
From: Atish Patra
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-2-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 72f1c9451e..345ec2c773 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,8 +82,11 @@ enum {
RISCV_FEATURE_AIA
};
-#define PRIV_VERSION_1_10_0 0x00011000
-#define PRIV_VERSION_1_11_0 0x00011100
+/* Privileged specification version */
+enum {
+PRIV_VERSION_1_10_0 = 0,
+PRIV_VERSION_1_11_0,
+};
#define VEXT_VERSION_1_00_0 0x0001
--
2.35.1
[PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0
From: Atish Patra
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 345ec2c773..19c3b6610b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,6 +86,7 @@ enum {
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
+PRIV_VERSION_1_12_0,
};
#define VEXT_VERSION_1_00_0 0x0001
--
2.35.1
[PULL v2 01/31] hw/ssi: Add Ibex SPI device model
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220303045426.511588-1-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
include/hw/ssi/ibex_spi_host.h | 94 +
hw/ssi/ibex_spi_host.c | 612 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events| 7 +
4 files changed, 714 insertions(+)
create mode 100644 include/hw/ssi/ibex_spi_host.h
create mode 100644 hw/ssi/ibex_spi_host.c
diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h
new file mode 100644
index 00..3fedcb6805
--- /dev/null
+++ b/include/hw/ssi/ibex_spi_host.h
@@ -0,0 +1,94 @@
+
+/*
+ * QEMU model of the Ibex SPI Controller
+ * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
+ *
+ * Copyright (C) 2022 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef IBEX_SPI_HOST_H
+#define IBEX_SPI_HOST_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo8.h"
+#include "qom/object.h"
+#include "hw/registerfields.h"
+#include "qemu/timer.h"
+
+#define TYPE_IBEX_SPI_HOST "ibex-spi"
+#define IBEX_SPI_HOST(obj) \
+OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
+
+/* SPI Registers */
+#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */
+#define IBEX_SPI_HOST_INTR_ENABLE(0x04 / 4) /* rw */
+#define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */
+#define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */
+#define IBEX_SPI_HOST_CONTROL(0x10 / 4) /* rw */
+#define IBEX_SPI_HOST_STATUS (0x14 / 4) /* ro */
+#define IBEX_SPI_HOST_CONFIGOPTS (0x18 / 4) /* rw */
+#define IBEX_SPI_HOST_CSID (0x1c / 4) /* rw */
+#define IBEX_SPI_HOST_COMMAND(0x20 / 4) /* wo */
+/* RX/TX Modelled by FIFO */
+#define IBEX_SPI_HOST_RXDATA (0x24 / 4)
+#define IBEX_SPI_HOST_TXDATA (0x28 / 4)
+
+#define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */
+#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */
+#define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */
+
+/* FIFO Len in Bytes */
+#define IBEX_SPI_HOST_TXFIFO_LEN 288
+#define IBEX_SPI_HOST_RXFIFO_LEN 256
+
+/* Max Register (Based on addr) */
+#define IBEX_SPI_HOST_MAX_REGS (IBEX_SPI_HOST_EVENT_ENABLE + 1)
+
+/* MISC */
+#define TX_INTERRUPT_TRIGGER_DELAY_NS100
+#define BIDIRECTIONAL_TRANSFER 3
+
+typedef struct {
+/* */
+SysBusDevice parent_obj;
+
+/* */
+MemoryRegion mmio;
+uint32_t regs[IBEX_SPI_HOST_MAX_REGS];
+/* Multi-reg that sets config opts per CS */
+uint32_t *config_opts;
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+QEMUTimer *fifo_trigger_handle;
+
+qemu_irq event;
+qemu_irq host_err;
+uint32_t num_cs;
+qemu_irq *cs_lines;
+SSIBus *ssi;
+
+/* Used to track the init status, for replicating TXDATA ghost writes */
+bool init_status;
+} IbexSPIHostState;
+
+#endif
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
new file mode 100644
index 00..d14580b409
--- /dev/null
+++ b/hw/ssi/ibex_spi_host.c
@@ -0,0 +1,612 @@
+/*
+ * QEMU model of the Ibex SPI Controller
+ * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
+ *
+ * Copyright (C) 2022 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify,
[PULL v2 00/31] riscv-to-apply queue
From: Alistair Francis The following changes since commit da5006445a92bb7801f54a93452fac63ca2f634c: Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2022-04-21 15:16:52 -0700) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220422-1 for you to fetch changes up to faee5441a038898f64b335dbaecab102ba406552: hw/riscv: boot: Support 64bit fdt address. (2022-04-22 10:35:16 +1000) First RISC-V PR for QEMU 7.1 * Add support for Ibex SPI to OpenTitan * Add support for privileged spec version 1.12.0 * Use privileged spec version 1.12.0 for virt machine by default * Allow software access to MIP SEIP * Add initial support for the Sdtrig extension * Optimisations for vector extensions * Improvements to the misa ISA string * Add isa extenstion strings to the device tree * Don't allow `-bios` options with KVM machines * Fix NAPOT range computation overflow * Fix DT property mmu-type when CPU mmu option is disabled * Make RISC-V ACLINT mtime MMIO register writable * Add and enable native debug feature * Support 64bit fdt address. Alistair Francis (2): target/riscv: cpu: Fixup indentation target/riscv: Allow software access to MIP SEIP Atish Patra (7): target/riscv: Define simpler privileged spec version numbering target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in the CSR ops. target/riscv: Add support for mconfigptr target/riscv: Add *envcfg* CSRs support target/riscv: Enable privileged spec version 1.12 target/riscv: Add isa extenstion strings to the device tree Bin Meng (7): target/riscv: Add initial support for the Sdtrig extension target/riscv: debug: Implement debug related TCGCPUOps target/riscv: cpu: Add a config option for native debug target/riscv: csr: Hook debug CSR read/write target/riscv: machine: Add debug state description target/riscv: cpu: Enable native debug feature hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Dylan Jhong (1): hw/riscv: boot: Support 64bit fdt address. Frank Chang (3): hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT hw/intc: Make RISC-V ACLINT mtime MMIO register writable Jim Shu (1): hw/intc: riscv_aclint: Add reset function of ACLINT devices Nicolas Pitre (1): target/riscv/pmp: fix NAPOT range computation overflow Niklas Cassel (1): hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Ralf Ramsauer (1): hw/riscv: virt: Exit if the user provided -bios in combination with KVM Richard Henderson (1): target/riscv: Use cpu_loop_exit_restore directly from mmu faults Tsukasa OI (1): target/riscv: misa to ISA string conversion fix Weiwei Li (3): target/riscv: optimize condition assign for scale < 0 target/riscv: optimize helper for vmvr.v target/riscv: fix start byte for vmvr.v when vstart != 0 Wilfred Mallawa (2): hw/ssi: Add Ibex SPI device model riscv: opentitan: Connect opentitan SPI Host include/hw/core/tcg-cpu-ops.h | 1 + include/hw/intc/riscv_aclint.h | 1 + include/hw/riscv/boot.h | 4 +- include/hw/riscv/opentitan.h| 30 +- include/hw/ssi/ibex_spi_host.h | 94 + target/riscv/cpu.h | 40 ++- target/riscv/cpu_bits.h | 40 +++ target/riscv/debug.h| 114 ++ target/riscv/helper.h | 5 +- hw/intc/riscv_aclint.c | 144 ++-- hw/riscv/boot.c | 12 +- hw/riscv/opentitan.c| 36 +- hw/riscv/virt.c | 24 +- hw/ssi/ibex_spi_host.c | 612 target/riscv/cpu.c | 120 ++- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 282 +-- target/riscv/debug.c| 441 +++ target/riscv/machine.c | 55 +++ target/riscv/pmp.c | 14 +- target/riscv/vector_helper.c| 31 +- target/riscv/insn_trans/trans_rvv.c.inc | 25 +- hw/ssi/meson.build | 1 + hw/ssi/trace-events | 7 + target/riscv/meson.build| 1 + 25 files changed, 1971 insertions(+), 173 deletions(-) create mode 100644 include/hw/ssi/ibex_spi_host.h create mode 100644 target/riscv/debug.h create mode 100644 hw/ssi/ibex_spi_host.c create mode 100644 target/riscv/debug.c
[PULL v2 06/31] target/riscv: Add support for mconfigptr
From: Atish Patra
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-5-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0fe01d7da5..48d92a81c3 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -148,6 +148,7 @@
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+#define CSR_MCONFIGPTR 0xf15
/* Machine Trap Setup */
#define CSR_MSTATUS 0x300
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1400027158..6590cc8aa7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3110,6 +3110,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIMPID]= { "mimpid",any, read_zero},
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
+[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
+.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Machine Trap Setup */
[CSR_MSTATUS] = { "mstatus",any, read_mstatus,
write_mstatus, NULL,
read_mstatus_i128
},
--
2.35.1
[PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host
From: Wilfred Mallawa
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220303045426.511588-2-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan.h | 30 +-
hw/riscv/opentitan.c | 36
2 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 00da9ded43..68892cd8e5 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -23,11 +23,18 @@
#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
+#include "hw/ssi/ibex_spi_host.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
+enum {
+OPENTITAN_SPI_HOST0,
+OPENTITAN_SPI_HOST1,
+OPENTITAN_NUM_SPI_HOSTS,
+};
+
struct LowRISCIbexSoCState {
/*< private >*/
SysBusDevice parent_obj;
@@ -37,6 +44,7 @@ struct LowRISCIbexSoCState {
SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
+IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
MemoryRegion flash_mem;
MemoryRegion rom;
@@ -89,15 +97,19 @@ enum {
};
enum {
-IBEX_TIMER_TIMEREXPIRED0_0 = 126,
-IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
-IBEX_UART0_RX_TIMEOUT_IRQ = 7,
-IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
-IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
-IBEX_UART0_RX_OVERFLOW_IRQ = 4,
-IBEX_UART0_TX_EMPTY_IRQ = 3,
-IBEX_UART0_RX_WATERMARK_IRQ = 2,
-IBEX_UART0_TX_WATERMARK_IRQ = 1,
+IBEX_UART0_TX_WATERMARK_IRQ = 1,
+IBEX_UART0_RX_WATERMARK_IRQ = 2,
+IBEX_UART0_TX_EMPTY_IRQ = 3,
+IBEX_UART0_RX_OVERFLOW_IRQ= 4,
+IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+IBEX_TIMER_TIMEREXPIRED0_0= 126,
+IBEX_SPI_HOST0_ERR_IRQ= 150,
+IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
+IBEX_SPI_HOST1_ERR_IRQ= 152,
+IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
};
#endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 833624d66c..2d401dcb23 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -120,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
+
+for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
+object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
+TYPE_IBEX_SPI_HOST);
+}
}
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
const MemMapEntry *memmap = ibex_memmap;
+DeviceState *dev;
+SysBusDevice *busdev;
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
@@ -209,14 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
IRQ_M_TIMER));
+/* SPI-Hosts */
+for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
+dev = DEVICE(&(s->spi_host[i]));
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
+return;
+}
+busdev = SYS_BUS_DEVICE(dev);
+sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
+
+switch (i) {
+case OPENTITAN_SPI_HOST0:
+sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
+IBEX_SPI_HOST0_ERR_IRQ));
+sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
+IBEX_SPI_HOST0_SPI_EVENT_IRQ));
+break;
+case OPENTITAN_SPI_HOST1:
+sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
+IBEX_SPI_HOST1_ERR_IRQ));
+sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
+IBEX_SPI_HOST1_SPI_EVENT_IRQ));
+break;
+}
+}
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
-create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
-memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
-create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
-memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
Re: [PATCH v11 12/14] target/riscv: rvk: add CSR support for Zkr
On Tue, Apr 19, 2022 at 12:06 PM Weiwei Li wrote:
>
> - add SEED CSR which must be accessed with a read-write instruction:
>A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
> with uimm=0 will raise an illegal instruction exception.
> - add USEED, SSEED fields for MSECCFG CSR
>
> Co-authored-by: Ruibo Lu
> Co-authored-by: Zewen Ye
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 9 +
> target/riscv/csr.c | 80
> target/riscv/op_helper.c | 9 +
> target/riscv/pmp.h | 8 ++--
> 4 files changed, 103 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bb47cf7e77..d401100f47 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -458,6 +458,9 @@
> #define CSR_VSPMMASK0x2c1
> #define CSR_VSPMBASE0x2c2
>
> +/* Crypto Extension */
> +#define CSR_SEED0x015
> +
> /* mstatus CSR bits */
> #define MSTATUS_UIE 0x0001
> #define MSTATUS_SIE 0x0002
> @@ -800,4 +803,10 @@ typedef enum RISCVException {
> #define HVICTL_VALID_MASK \
> (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
>
> +/* seed CSR bits */
> +#define SEED_OPST(0b11 << 30)
> +#define SEED_OPST_BIST (0b00 << 30)
> +#define SEED_OPST_WAIT (0b01 << 30)
> +#define SEED_OPST_ES16 (0b10 << 30)
> +#define SEED_OPST_DEAD (0b11 << 30)
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e10f691a99..865ffb36ce 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -24,6 +24,8 @@
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
> #include "sysemu/cpu-timers.h"
> +#include "qemu/guest-random.h"
> +#include "qapi/error.h"
>
> /* CSR function table public API */
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> @@ -301,6 +303,46 @@ static RISCVException debug(CPURISCVState *env, int
> csrno)
> }
> #endif
>
> +static RISCVException seed(CPURISCVState *env, int csrno)
> +{
> +RISCVCPU *cpu = env_archcpu(env);
> +
> +if (!cpu->cfg.ext_zkr) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +/*
> + * With a CSR read-write instruction:
> + * 1) The seed CSR is always available in machine mode as normal.
> + * 2) Attempted access to seed from virtual modes VS and VU always raises
> + * an exception(virtual instruction exception only if mseccfg.sseed=1).
> + * 3) Without the corresponding access control bit set to 1, any
> attempted
> + * access to seed from U, S or HS modes will raise an illegal instruction
> + * exception.
> + */
> +if (env->priv == PRV_M) {
> +return RISCV_EXCP_NONE;
> +} else if (riscv_cpu_virt_enabled(env)) {
> +if (env->mseccfg & MSECCFG_SSEED) {
> +return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> +} else {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +} else {
> +if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
> +return RISCV_EXCP_NONE;
> +} else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
> +return RISCV_EXCP_NONE;
> +} else {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +}
> +#else
> +return RISCV_EXCP_NONE;
> +#endif
> +}
> +
> /* User Floating-Point CSRs */
> static RISCVException read_fflags(CPURISCVState *env, int csrno,
>target_ulong *val)
> @@ -3014,6 +3056,41 @@ static RISCVException write_upmbase(CPURISCVState
> *env, int csrno,
>
> #endif
>
> +/* Crypto Extension */
> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
> + target_ulong *ret_value,
> + target_ulong new_value,
> + target_ulong write_mask)
> +{
> +uint16_t random_v;
> +Error *random_e = NULL;
> +int random_r;
> +target_ulong rval;
> +
> +random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
> +if (unlikely(random_r < 0)) {
> +/*
> + * Failed, for unknown reasons in the crypto subsystem.
> + * The best we can do is log the reason and return a
> + * failure indication to the guest. There is no reason
> + * we know to expect the failure to be transitory, so
> + * indicate DEAD to avoid having the guest spin on WAIT.
> + */
> +qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
> + __func__, error_get_pretty(random_e));
> +error_free(random_e);
> +rval = SEED_OPST_DEAD;
> +} else {
> +rval = random_v | SEED_OPST_ES16;
> +}
> +
> +if (ret_value) {
> +
Re: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry
On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote: > > If not, do we want to apply this version scheme only when it > > reaches the production quality or also in the experimental phase? > > Yes. E.g if we think scalable mode is mature, we can enable 3.0. Sorry to come back to the discussion late.. I'd say unless someone (or some organization) strongly ask for a stable interface for scalable mode (better with some developer looking after it along with the organization), until then we start with versioning. Otherwise I hope we can be free to break the interface assuming things are still evolving, just like the spec. Thanks, -- Peter Xu
Re: [PULL 00/17] Python patches
On 4/21/22 08:15, John Snow wrote:
The following changes since commit b1efff6bf031a93b5b8bf3912ddc720cc1653a61:
Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into
staging (2022-04-20 21:54:24 -0700)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/python-pull-request
for you to fetch changes up to 47430775ed1a48d7beb2c7b8d7feaab73104ec46:
python/qmp: remove pylint workaround from legacy.py (2022-04-21 11:01:00
-0400)
Python patches
This PR finalizes the switch from Luiz's QMP library to mine.
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
John Snow (17):
python/machine: permanently switch to AQMP
scripts/bench-block-job: switch to AQMP
iotests/mirror-top-perms: switch to AQMP
iotests: switch to AQMP
python/aqmp: add explicit GPLv2 license to legacy.py
python/aqmp: relicense as LGPLv2+
python/qmp-shell: relicense as LGPLv2+
python/aqmp-tui: relicense as LGPLv2+
python: temporarily silence pylint duplicate-code warnings
python/aqmp: take QMPBadPortError and parse_address from qemu.qmp
python/aqmp: fully separate from qmp.QEMUMonitorProtocol
python/aqmp: copy qmp docstrings to qemu.aqmp.legacy
python: remove the old QMP package
python: re-enable pylint duplicate-code warnings
python: rename qemu.aqmp to qemu.qmp
python: rename 'aqmp-tui' to 'qmp-tui'
python/qmp: remove pylint workaround from legacy.py
python/README.rst | 2 +-
python/qemu/qmp/README.rst| 9 -
python/qemu/aqmp/__init__.py | 59 ---
python/qemu/aqmp/legacy.py| 177 ---
python/qemu/aqmp/py.typed | 0
python/qemu/machine/machine.py| 18 +-
python/qemu/machine/qtest.py | 2 +-
python/qemu/qmp/__init__.py | 445 ++
python/qemu/{aqmp => qmp}/error.py| 0
python/qemu/{aqmp => qmp}/events.py | 2 +-
python/qemu/qmp/legacy.py | 315 +
python/qemu/{aqmp => qmp}/message.py | 0
python/qemu/{aqmp => qmp}/models.py | 0
python/qemu/{aqmp => qmp}/protocol.py | 4 +-
python/qemu/{aqmp => qmp}/qmp_client.py | 16 +-
python/qemu/{aqmp => qmp}/qmp_shell.py| 11 +-
.../qemu/{aqmp/aqmp_tui.py => qmp/qmp_tui.py} | 17 +-
python/qemu/{aqmp => qmp}/util.py | 0
python/qemu/utils/qemu_ga_client.py | 4 +-
python/qemu/utils/qom.py | 2 +-
python/qemu/utils/qom_common.py | 4 +-
python/qemu/utils/qom_fuse.py | 2 +-
python/setup.cfg | 11 +-
python/tests/protocol.py | 14 +-
scripts/cpu-x86-uarch-abi.py | 2 +-
scripts/device-crash-test | 4 +-
scripts/qmp/qmp-shell | 2 +-
scripts/qmp/qmp-shell-wrap| 2 +-
scripts/render_block_graph.py | 4 +-
scripts/simplebench/bench_block_job.py| 5 +-
tests/qemu-iotests/iotests.py | 3 +-
tests/qemu-iotests/tests/mirror-top-perms | 11 +-
32 files changed, 422 insertions(+), 725 deletions(-)
delete mode 100644 python/qemu/qmp/README.rst
delete mode 100644 python/qemu/aqmp/__init__.py
delete mode 100644 python/qemu/aqmp/legacy.py
delete mode 100644 python/qemu/aqmp/py.typed
rename python/qemu/{aqmp => qmp}/error.py (100%)
rename python/qemu/{aqmp => qmp}/events.py (99%)
create mode 100644 python/qemu/qmp/legacy.py
rename python/qemu/{aqmp => qmp}/message.py (100%)
rename python/qemu/{aqmp => qmp}/models.py (100%)
rename python/qemu/{aqmp => qmp}/protocol.py (99%)
rename python/qemu/{aqmp => qmp}/qmp_client.py (97%)
rename python/qemu/{aqmp => qmp}/qmp_shell.py (98%)
rename python/qemu/{aqmp/aqmp_tui.py => qmp/qmp_tui.py} (98%)
rename python/qemu/{aqmp => qmp}/util.py (100%)
Re: [PATCH 01/50] dino: checkpatch fixes
On 4/21/22 12:30, Mark Cave-Ayland wrote: Signed-off-by: Mark Cave-Ayland --- hw/hppa/dino.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PULL 0/7] QAPI patches patches for 2022-04-21
On 4/21/22 07:31, Markus Armbruster wrote: The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b: Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700) are available in the Git repository at: git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2022-04-21 for you to fetch changes up to de7371bc7c39ccacb963acb5129b261087967070: qapi: Fix version of cpu0-id field (2022-04-21 10:23:06 +0200) QAPI patches patches for 2022-04-21 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Andrea Bolognani (3): docs: qapi: Remove outdated reference to simple unions qapi: Fix documentation for query-xen-replication-status qapi: Fix typo Dov Murik (1): qapi: Fix version of cpu0-id field Paolo Bonzini (3): qapi-schema: support alternates with array type qapi-schema: test: add a qapi-schema-test for array alternates qapi-schema: test: add a unit test for parsing array alternates docs/devel/qapi-code-gen.rst| 4 +-- qapi/migration.json | 2 +- qapi/misc-target.json | 2 +- qapi/sockets.json | 2 +- tests/unit/test-qobject-input-visitor.c | 40 + scripts/qapi/expr.py| 2 +- scripts/qapi/schema.py | 4 +++ tests/qapi-schema/alternate-array.err | 2 -- tests/qapi-schema/alternate-array.json | 2 -- tests/qapi-schema/alternate-array.out | 18 +++ tests/qapi-schema/alternate-conflict-lists.err | 2 ++ tests/qapi-schema/alternate-conflict-lists.json | 6 tests/qapi-schema/alternate-conflict-lists.out | 0 tests/qapi-schema/meson.build | 1 + tests/qapi-schema/qapi-schema-test.json | 1 + tests/qapi-schema/qapi-schema-test.out | 4 +++ 16 files changed, 82 insertions(+), 10 deletions(-) create mode 100644 tests/qapi-schema/alternate-conflict-lists.err create mode 100644 tests/qapi-schema/alternate-conflict-lists.json create mode 100644 tests/qapi-schema/alternate-conflict-lists.out
Re: [PATCH 3/6] scsi-disk: add MODE_PAGE_APPLE quirk for Macintosh
On Thu, 21 Apr 2022, Richard Henderson wrote: On 4/21/22 08:29, Mark Cave-Ayland wrote: You need (1 << SCSI_DISK_QUIRK_MODE_PAGE_APPLE) instead. Doh, you're absolutely right. I believe the current recommendation is to use the BIT() macro in these cases. I think it's not a recommendation (as in code style) but it often makes things simpler by reducing the number of parenthesis so using it is probably a good idea for readability. But if you never need the bit number only the value then you could define the quirks constants as that in the first place. (Otherwise if you want bit numbers maybe make it an enum.) We probably need to fix BIT() to use 1ULL. At present it's using 1UL, to match the other (unfortunate) uses of unsigned long within bitops.h. The use of BIT() for things unrelated to bitops.h just bit a recent risc-v pull request, in that it failed to build on all 32-bit hosts. There's already a BIT_ULL(nr) when ULL is needed but in this case quirks was declared uint32_t so probably OK with UL as well. (Was this bitops.h taken from Linux? Keeping it compatible then may be a good idea to avoid confusion.) Regards, BALATON Zoltan
Re: [PATCH 5/6] target/xtensa: use tcg_constant_* for FPU conversion opcodes
On 4/21/22 14:39, Max Filippov wrote: FPU conversion opcodes pass scale (range 0..15) and rounding mode to their helpers. Use tcg_constant_* for them. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes
On 4/21/22 14:39, Max Filippov wrote:
+TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+
+if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+gen_io_start();
+}
+gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+tcg_temp_free(pc);
Missed conversion to tcg_constant_i32 for pc.
Otherwise,
Reviewed-by: Richard Henderson
r~
Re: [PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers
On 4/21/22 14:39, Max Filippov wrote: Numbered special registers are small arrays of consecutive SRs. Use tcg_constant_* for the SR index. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 2/6] target/xtensa: use tcg_constant_* for exceptions
On 4/21/22 14:39, Max Filippov wrote: Exception number, exception cause and debug cause codes are small numbers, use tcg_contant_* for them. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 3/6] target/xtensa: use tcg_constant_* for TLB opcodes
On 4/21/22 14:39, Max Filippov wrote: dtlb is a boolean flag, use tcg_constant_* for it. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 1/6] target/xtensa: use tcg_contatnt_* for numeric literals
On 4/21/22 14:39, Max Filippov wrote: Replace tcg_const_* for numeric literals with tcg_constant_*. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 28 +--- 1 file changed, 9 insertions(+), 19 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH] target/xtensa: add missing tcg_temp_free to gen_window_check
On 4/21/22 13:21, Max Filippov wrote:
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Add missing tcg_temp_free for pc, use tcg_constant_i32
for w.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index b1491ed625e5..f4dac27507fd 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -572,9 +572,10 @@ static bool gen_window_check(DisasContext *dc, uint32_t
mask)
if (r / 4 > dc->window) {
TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 w = tcg_const_i32(r / 4);
+TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
+tcg_temp_free(pc);
Should use tcg_constant_i32 for both of them, and not add the free for pc.
r~
[PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- gen_callw_slot uses callinc (1..3);
- translate_entry passes stack register number (0..15) to the helper;
- gen_check_exclusive passes boolean to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 44 ---
1 file changed, 13 insertions(+), 31 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index fb4d80669c47..b3f8348dee26 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -406,11 +406,8 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int
slot)
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
-TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
-tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
-tcg_temp_free(tcallinc);
+tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fff));
gen_jump_slot(dc, dest, slot);
@@ -456,9 +453,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
-TCGv_i32 tmp = tcg_const_i32(t1);
-gen_brcond(dc, cond, t0, tmp, addr);
-tcg_temp_free(tmp);
+gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@@ -543,21 +538,6 @@ static MemOp gen_load_store_alignment(DisasContext *dc,
MemOp mop,
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
-TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
-TCGv_i32 intlevel = tcg_const_i32(imm4);
-
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
-gen_helper_waiti(cpu_env, pc, intlevel);
-tcg_temp_free(pc);
-tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
@@ -1663,11 +1643,10 @@ static void translate_entry(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 s = tcg_const_i32(arg[0].imm);
+TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_const_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
tcg_temp_free(imm);
-tcg_temp_free(s);
tcg_temp_free(pc);
}
@@ -1749,11 +1728,10 @@ static void gen_check_exclusive(DisasContext *dc,
TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 write = tcg_const_i32(is_write);
-gen_helper_check_exclusive(cpu_env, tpc, addr, write);
+gen_helper_check_exclusive(cpu_env, tpc, addr,
+ tcg_constant_i32(is_write));
tcg_temp_free(tpc);
-tcg_temp_free(write);
}
}
#endif
@@ -2517,9 +2495,7 @@ static void translate_ssa8l(DisasContext *dc, const
OpcodeArg arg[],
static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
-gen_right_shift_sar(dc, tmp);
-tcg_temp_free(tmp);
+gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm));
}
static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
@@ -2553,7 +2529,13 @@ static void translate_waiti(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-gen_waiti(dc, arg[0].imm);
+TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+
+if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+gen_io_start();
+}
+gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+tcg_temp_free(pc);
#endif
}
--
2.30.2
[PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 82a0dbf46d7c..c4991735ead7 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2615,15 +2615,13 @@ static void translate_wsr_ccompare(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
uint32_t id = par[0] - CCOMPARE;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
-gen_helper_update_ccompare(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
#endif
}
@@ -2643,11 +2641,9 @@ static void translate_wsr_dbreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2656,11 +2652,9 @@ static void translate_wsr_dbreakc(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKC;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2669,11 +2663,9 @@ static void translate_wsr_ibreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - IBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
-gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
--
2.30.2
[PATCH 5/6] target/xtensa: use tcg_constant_* for FPU conversion opcodes
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index c4991735ead7..fb4d80669c47 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -6515,20 +6515,19 @@ static void translate_const_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
} else {
gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
}
-tcg_temp_free(scale);
}
static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
OpcodeArg arg32[1];
get_f32_o1(arg, arg32, 0);
@@ -6538,14 +6537,13 @@ static void translate_float_s(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
-tcg_temp_free(scale);
}
static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
@@ -6554,15 +6552,13 @@ static void translate_ftoi_d(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
rounding_mode, scale);
}
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
OpcodeArg arg32[2];
get_f32_i1(arg, arg32, 1);
@@ -6574,8 +6570,6 @@ static void translate_ftoi_s(DisasContext *dc, const
OpcodeArg arg[],
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
--
2.30.2
[PATCH 1/6] target/xtensa: use tcg_contatnt_* for numeric literals
Replace tcg_const_* for numeric literals with tcg_constant_*.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f4dac27507fd..3379fc1fc774 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -306,16 +306,14 @@ static void gen_right_shift_sar(DisasContext *dc,
TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
-TCGv_i32 tmp = tcg_const_i32(32);
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
-tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
+tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
-tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
@@ -1957,11 +1955,10 @@ static void translate_mov(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
-tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
@@ -1973,7 +1970,7 @@ static void translate_movi(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@@ -1981,7 +1978,6 @@ static void translate_movp(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
-tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
@@ -6444,7 +6440,7 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6456,7 +6452,6 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6476,7 +6471,7 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6490,7 +6485,6 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -,14 +6660,13 @@ static void translate_mov_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i64 zero = tcg_const_i64(0);
+TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
-tcg_temp_free_i64(zero);
tcg_temp_free_i64(arg2);
}
@@ -6681,12 +6674,11 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
-tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
@@ -6695,7 +6687,7 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
[PATCH 2/6] target/xtensa: use tcg_constant_* for exceptions
Exception number, exception cause and debug cause codes are small
numbers, use tcg_contant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 3379fc1fc774..77d2e1303746 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -318,18 +318,14 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32
sa)
static void gen_exception(DisasContext *dc, int excp)
{
-TCGv_i32 tmp = tcg_const_i32(excp);
-gen_helper_exception(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_exception_cause(cpu_env, tpc, tcause);
+gen_helper_exception_cause(cpu_env, tpc, tcg_constant_i32(cause));
tcg_temp_free(tpc);
-tcg_temp_free(tcause);
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
@@ -339,10 +335,8 @@ static void gen_exception_cause(DisasContext *dc, uint32_t
cause)
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_debug_exception(cpu_env, tpc, tcause);
+gen_helper_debug_exception(cpu_env, tpc, tcg_constant_i32(cause));
tcg_temp_free(tpc);
-tcg_temp_free(tcause);
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.30.2
[PATCH 3/6] target/xtensa: use tcg_constant_* for TLB opcodes
dtlb is a boolean flag, use tcg_constant_* for it.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 77d2e1303746..82a0dbf46d7c 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1710,10 +1710,9 @@ static void translate_itlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_itlb(cpu_env, arg[0].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2050,11 +2049,10 @@ static void translate_ptlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2253,10 +2251,9 @@ static void translate_rtlb(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_rtlb0,
gen_helper_rtlb1,
};
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2564,10 +2561,9 @@ static void translate_wtlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
--
2.30.2
[PATCH 0/6] target/xtensa: use tcg_constant_* where possible
Hello, this series replaces tcg_const_* with tcg_constant_* in the xtensa front end. Max Filippov (6): target/xtensa: use tcg_contatnt_* for numeric literals target/xtensa: use tcg_constant_* for exceptions target/xtensa: use tcg_constant_* for TLB opcodes target/xtensa: use tcg_constant_* for numbered special registers target/xtensa: use tcg_constant_* for FPU conversion opcodes target/xtensa: use tcg_constant_* for remaining opcodes target/xtensa/translate.c | 130 -- 1 file changed, 39 insertions(+), 91 deletions(-) -- 2.30.2
Re: [PATCH v3 18/60] target/arm: Use tcg_constant in translate-m-nocp.c
On 4/21/22 12:03, Peter Maydell wrote:
On Sun, 17 Apr 2022 at 19:02, Richard Henderson
wrote:
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-m-nocp.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index d9e144e8eb..27363a7b4e 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
}
/* Zero the Sregs from btmreg to topreg inclusive. */
-zero = tcg_const_i64(0);
+zero = tcg_constant_i64(0);
if (btmreg & 1) {
write_neon_element64(zero, btmreg >> 1, 1, MO_32);
btmreg++;
Looks like we were previously leaking the TCGv for this one?
Yes. I'll update the commit message to mention that.
r~
Re: Create qemu-project/py-qemu.qmp repo
On Thu, Apr 21, 2022, 2:00 PM Andrea Bolognani wrote: > On Thu, Apr 21, 2022 at 12:46:48PM -0400, John Snow wrote: > > Hi Alex: do you have the ability to create a blank/empty "py-qemu.qmp" > > repo under the qemu-project grouping, and add me and Cleber as > > maintainers for it? There weren't any objections when I floated the > > idea [1]. > > > > (Though I suggested "py-qemu.qmp" and Dan suggested "python-qemu.qmp". > > I don't think we explicitly reconciled the difference. I like the > > shorter one.) > > Since you CC'd me to this message, I'm going to assume you're > explicitly welcoming my input on what specific shade this bikeshed > should be painted ;) > More of a "Speak now or forever hold your peace" 😅 I think I would go with "python-qemu-qmp". Having a dot in the name > of a git repo is not very common AFAICT, and I wouldn't rule out the > possibility of some GitLab feature or other tooling breaking or > misbehaving because of it. > > If you're really keen on saving those few extra keystrokes, maybe > "pyqemu" is a better prefix than "py-qemu"? I don't know, it just > looks more natural to me. > The idea is to have the repo name resemble the Python package name, which is "qemu.qmp". For Python, it's customary to have the package name match the import name. The import name is "qemu.qmp". I tested this name on GitLab and it appears to work just fine. I'd add "py:" as a prefix, but the colon doesn't work as a filename in many places, so I suggested "py-". Thus, all together, "py-qemu.qmp". (I could spell out "python", I just prefer the shorter prefix because it's explanatory enough as-is and I like keeping git checkout names short. My favorite color of bike shed is blue.) > -- > Andrea Bolognani / Red Hat / Virtualization > >
Re: [PATCH] target/xtensa: import core lx106
Hi Simon, On Thu, Apr 21, 2022 at 1:04 PM Simon Safar via wrote: > > This is the core used in e.g. ESP8266 chips. Importing them > using import_core.sh, with the required files sourced from > > https://github.com/espressif/xtensa-overlays > > core-lx106.c was generated by the script; the only change is removing > the reference to core-matmap.h which doesn't seem to be available. > > Signed-off-by: Simon Safar > --- > target/xtensa/core-lx106.c| 52 + > target/xtensa/core-lx106/core-isa.h | 470 + > target/xtensa/core-lx106/gdb-config.c.inc | 83 + > target/xtensa/core-lx106/xtensa-modules.c.inc | 7668 + > 4 files changed, 8273 insertions(+) > create mode 100644 target/xtensa/core-lx106.c > create mode 100644 target/xtensa/core-lx106/core-isa.h > create mode 100644 target/xtensa/core-lx106/gdb-config.c.inc > create mode 100644 target/xtensa/core-lx106/xtensa-modules.c.inc An update to target/xtensa/cores.list is needed for this core to be built in qemu-6.2+. Please keep that file alphabetically sorted. With that addressed: Reviewed-by: Max Filippov I'm curious how is it supposed to be used? -- Thanks. -- Max
[PATCH] target/xtensa: add missing tcg_temp_free to gen_window_check
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Add missing tcg_temp_free for pc, use tcg_constant_i32
for w.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index b1491ed625e5..f4dac27507fd 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -572,9 +572,10 @@ static bool gen_window_check(DisasContext *dc, uint32_t
mask)
if (r / 4 > dc->window) {
TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 w = tcg_const_i32(r / 4);
+TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
+tcg_temp_free(pc);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
--
2.30.2
[PATCH 50/50] hppa: simplify machine function names in machine.c
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/machine.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 3176c7897e..292867a063 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -446,7 +446,7 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error
**errp)
}
}
-static void machine_hppa_machine_init_class_init(ObjectClass *oc, void *data)
+static void hppa_machine_init_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
@@ -466,19 +466,19 @@ static void
machine_hppa_machine_init_class_init(ObjectClass *oc, void *data)
nc->nmi_monitor_handler = hppa_nmi;
}
-static const TypeInfo machine_hppa_machine_init_typeinfo = {
+static const TypeInfo hppa_machine_init_typeinfo = {
.name = MACHINE_TYPE_NAME("hppa"),
.parent = TYPE_MACHINE,
-.class_init = machine_hppa_machine_init_class_init,
+.class_init = hppa_machine_init_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NMI },
{ }
},
};
-static void machine_hppa_machine_init_register_types(void)
+static void hppa_machine_init_register_types(void)
{
-type_register_static(&machine_hppa_machine_init_typeinfo);
+type_register_static(&hppa_machine_init_typeinfo);
}
-type_init(machine_hppa_machine_init_register_types)
+type_init(hppa_machine_init_register_types)
--
2.20.1
Re: [PATCH v3] hw/misc: applesmc: use host osk as default on macs
Hi, Daniel!
Ok, thank you - then I'll wait until compat machines
for 7.1 are added (after release) and send a new
patch.
Regards,
Vladislav
вт, 19 апр. 2022 г. в 19:03, Daniel P. Berrangé :
> On Sun, Apr 17, 2022 at 04:43:14PM +0300, Vladislav Yaroshchuk wrote:
> > I've CCed all the people from previous threads.
> >
> >
> > > [...]
> > > +static bool applesmc_read_osk(uint8_t *osk)
> > > +{
> > > +#if defined(__APPLE__) && defined(__MACH__)
> > > +struct AppleSMCParams {
> > > +uint32_t key;
> > > +uint8_t __pad0[16];
> > > +uint8_t result;
> > > +uint8_t __pad1[7];
> > > +uint32_t size;
> > > +uint8_t __pad2[10];
> > > +uint8_t data8;
> > > +uint8_t __pad3[5];
> > > +uint8_t output[32];
> > > +};
> > > +
> > > +io_service_t svc;
> > > +io_connect_t conn;
> > > +kern_return_t ret;
> > > +size_t size = sizeof(struct AppleSMCParams);
> > > +struct AppleSMCParams params_in = { .size = 32, .data8 = 5 };
> >
> > Maybe it's better to name this magic number '5'
> >
> > > +struct AppleSMCParams params_out = {};
> > > +
> >
> > params_in and params_out can be the same variable, see
> >
> https://patchew.org/QEMU/20211022161448.81579-1-yaroshchuk2...@gmail.com/
> >
> > > +svc = IOServiceGetMatchingService(0,
> IOServiceMatching("AppleSMC"));
> > > +if (svc == 0) {
> > > +return false;
> > > +}
> > > +
> > > +ret = IOServiceOpen(svc, mach_task_self(), 0, &conn);
> > > +if (ret != 0) {
> > > +return false;
> > > +}
> > > +
> > > +for (params_in.key = 'OSK0'; params_in.key <= 'OSK1';
> > ++params_in.key) {
> > > +ret = IOConnectCallStructMethod(conn, 2, ¶ms_in, size,
> > ¶ms_out, &size);
> >
> > Same about this magic number '2'.
> >
> > > +if (ret != 0) {
> > > +return false;
> > > +}
> > > +
> > > +if (params_out.result != 0) {
> > > +return false;
> > > +}
> > > +memcpy(osk, params_out.output, params_in.size);
> > > +
> > > +osk += params_in.size;
> > > + }
> > > +
> >
> > Cleanup IOServiceClose and IOObjectReturn are not called at the
> > end of the procedure.
> >
> > This is also mentioned in Phil Dennis-Jordan's instruction you noted
> (stage
> > 5):
> > https://lists.nongnu.org/archive/html/qemu-devel/2021-10/msg02843.html
> >
> > > +return true;
> > > +#else
> > > +return false;
> > > +#endif
> > > +}
> > > +
> > > [...]
> > >
> > > static void applesmc_isa_realize(DeviceState *dev, Error **errp)
> > > {
> > > AppleSMCState *s = APPLE_SMC(dev);
> > > +bool valid_osk = false;
> > >
> > > memory_region_init_io(&s->io_data, OBJECT(s),
> &applesmc_data_io_ops,
> > s,
> > >"applesmc-data", 1);
> > > @@ -331,8 +393,17 @@ static void applesmc_isa_realize(DeviceState *dev,
> > Error **errp)
> > > isa_register_ioport(&s->parent_obj, &s->io_err,
> > > s->iobase + APPLESMC_ERR_PORT);
> > >
> > > -if (!s->osk || (strlen(s->osk) != 64)) {
> > > -warn_report("Using AppleSMC with invalid key");
> > > +if (s->osk) {
> > > +valid_osk = strlen(s->osk) == 64;
> > > +} else {
> > > +valid_osk = applesmc_read_osk((uint8_t *) default_osk);
> > > +if (valid_osk) {
> > > +warn_report("Using AppleSMC with host OSK");
> > > +s->osk = default_osk;
> > > +}
> > > +}
> > > +if (!valid_osk) {
> > > +warn_report("Using AppleSMC with invalid OSK");
> > > s->osk = default_osk;
> > > }
> > > [...]
> >
> > After the previous discussion we've decided (if i don't confuse anything)
> > to have a way to enable/disable host OSK reading with new property:
> > 1. properties osk=$key and hostosk=on cannot be used together (fail hard)
> > 2. for QEMU machine > 7.0 - hostosk=on by default.
> > If unable to read - fail hard with error_setg.
> > 3. for QEMU machine <= 7.0 - hostosk=off by default,
> >the dummy OSK is used (as previously).
> >
> > BTW since my patches lost 7.0, I planned to wait until compat machines
> > for 7.1 are added (after 7.0 release) and then rebase the patches,
> > adding required changes into `hw/core/machine.c`
> >
> > Now we have two versions of host OSK forwarding implementations,
> > Pedro's (this one) and mine (
> >
> https://patchew.org/QEMU/20220113152836.60398-1-yaroshchuk2...@gmail.com/#
> )
> >
> > Do we still want to add this feature? If yes - whose version is
> preferred?
> > (I'm still ready to work on this)
>
> I prefer yours, since the feature is introspectable by mgmt apps,
> given the existance of the 'hostosk' property
>
> With regards,
> Daniel
> --
> |: https://berrange.com -o-
> https://www.flickr.com/photos/dberrange :|
> |: https://libvirt.org -o-
> https://fstop138.berrange.com :|
> |: https://entangle-photo.org-o-
> https://www.instagram.com/dberrange :|
>
>
[PATCH 46/50] hppa: move enable_lan() define from hppa_sys.h to machine.c
Now that the board configuration is in one place, the define is only needed when
wiring up the board in machine.c.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/machine.c | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index 17e2c6dec1..e7f65cad75 100644
--- a/hw/hppa/hppa_sys.h
+++ b/hw/hppa/hppa_sys.h
@@ -5,6 +5,4 @@
#include "hppa_hardware.h"
-#define enable_lasi_lan() 0
-
#endif
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 7fb41ff0e7..d61e2ea4e4 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -36,6 +36,9 @@
#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
+#define enable_lasi_lan() 0
+
+
static void hppa_powerdown_req(Notifier *n, void *opaque)
{
hwaddr soft_power_reg = HPA_POWER_BUTTON;
--
2.20.1
[PATCH 44/50] hppa: remove hw/hppa/pci.c
The functions and definitions in this file are not used anywhere within the
generic hppa machine.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 6
hw/hppa/meson.build | 2 +-
hw/hppa/pci.c| 65
hw/hppa/trace-events | 3 --
4 files changed, 1 insertion(+), 75 deletions(-)
delete mode 100644 hw/hppa/pci.c
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index d984b2895d..17e2c6dec1 100644
--- a/hw/hppa/hppa_sys.h
+++ b/hw/hppa/hppa_sys.h
@@ -3,14 +3,8 @@
#ifndef HW_HPPA_SYS_H
#define HW_HPPA_SYS_H
-#include "hw/boards.h"
-
#include "hppa_hardware.h"
#define enable_lasi_lan() 0
-/* hppa_pci.c. */
-extern const MemoryRegionOps hppa_pci_conf1_ops;
-extern const MemoryRegionOps hppa_pci_iack_ops;
-
#endif
diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build
index 92878d9ac1..28175d27a4 100644
--- a/hw/hppa/meson.build
+++ b/hw/hppa/meson.build
@@ -1,4 +1,4 @@
hppa_ss = ss.source_set()
-hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('pci.c', 'machine.c'))
+hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('machine.c'))
hw_arch += {'hppa': hppa_ss}
diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c
deleted file mode 100644
index 4d62d54c22..00
--- a/hw/hppa/pci.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * QEMU HP-PARISC PCI support functions.
- *
- */
-
-#include "qemu/osdep.h"
-#include "hppa_sys.h"
-#include "qemu/log.h"
-#include "hw/pci/pci.h"
-#include "hw/pci/pci_host.h"
-#include "hw/intc/i8259.h"
-#include "trace.h"
-
-
-/* PCI config space reads/writes, to byte-word addressable memory. */
-static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
- unsigned size)
-{
-PCIBus *b = opaque;
-return pci_data_read(b, addr, size);
-}
-
-static void bw_conf1_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
-{
-PCIBus *b = opaque;
-pci_data_write(b, addr, val, size);
-}
-
-const MemoryRegionOps hppa_pci_conf1_ops = {
-.read = bw_conf1_read,
-.write = bw_conf1_write,
-.endianness = DEVICE_BIG_ENDIAN,
-.impl = {
-.min_access_size = 1,
-.max_access_size = 4,
-},
-};
-
-/* PCI/EISA Interrupt Acknowledge Cycle. */
-
-static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
-{
-return pic_read_irq(isa_pic);
-}
-
-static void special_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
-{
-trace_hppa_pci_iack_write();
-}
-
-const MemoryRegionOps hppa_pci_iack_ops = {
-.read = iack_read,
-.write = special_write,
-.endianness = DEVICE_BIG_ENDIAN,
-.valid = {
-.min_access_size = 4,
-.max_access_size = 4,
-},
-.impl = {
-.min_access_size = 4,
-.max_access_size = 4,
-},
-};
diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events
index 1a4fbe2fa8..23bc9b19b9 100644
--- a/hw/hppa/trace-events
+++ b/hw/hppa/trace-events
@@ -1,4 +1 @@
# See docs/devel/tracing.rst for syntax documentation.
-
-# pci.c
-hppa_pci_iack_write(void) ""
--
2.20.1
[PATCH 39/50] lasi: use constants for device register offsets
Instead of generating the offset based upon the physical address of the register, add constants for each of the device registers to lasi.h and update lasi.c to use them. Signed-off-by: Mark Cave-Ayland --- hw/hppa/lasi.c | 28 ++-- hw/hppa/lasi.h | 5 + 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c index ad50880a13..11ca33fba3 100644 --- a/hw/hppa/lasi.c +++ b/hw/hppa/lasi.c @@ -36,10 +36,10 @@ static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, case LASI_ICR: case LASI_IAR: -case (LASI_LAN_HPA - LASI_HPA): -case (LASI_LPT_HPA - LASI_HPA): -case (LASI_UART_HPA - LASI_HPA): -case (LASI_RTC_HPA - LASI_HPA): +case LASI_LPT: +case LASI_UART: +case LASI_LAN: +case LASI_RTC: case LASI_PCR ... LASI_AMR: ret = true; @@ -76,12 +76,12 @@ static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, val = s->iar; break; -case (LASI_LAN_HPA - LASI_HPA): -case (LASI_LPT_HPA - LASI_HPA): -case (LASI_UART_HPA - LASI_HPA): +case LASI_LPT: +case LASI_UART: +case LASI_LAN: val = 0; break; -case (LASI_RTC_HPA - LASI_HPA): +case LASI_RTC: val = time(NULL); val += s->rtc_ref; break; @@ -141,16 +141,16 @@ static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, s->iar = val; break; -case (LASI_LAN_HPA - LASI_HPA): -/* XXX: reset LAN card */ -break; -case (LASI_LPT_HPA - LASI_HPA): +case LASI_LPT: /* XXX: reset parallel port */ break; -case (LASI_UART_HPA - LASI_HPA): +case LASI_UART: /* XXX: reset serial port */ break; -case (LASI_RTC_HPA - LASI_HPA): +case LASI_LAN: +/* XXX: reset LAN card */ +break; +case LASI_RTC: s->rtc_ref = val - time(NULL); break; diff --git a/hw/hppa/lasi.h b/hw/hppa/lasi.h index 63a2be3740..11cf7d6b0b 100644 --- a/hw/hppa/lasi.h +++ b/hw/hppa/lasi.h @@ -21,6 +21,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP) #define LASI_ICR0x0c #define LASI_IAR0x10 +#define LASI_LPT0x02000 +#define LASI_UART 0x05000 +#define LASI_LAN0x07000 +#define LASI_RTC0x09000 + #define LASI_PCR0x0C000 /* LASI Power Control register */ #define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ #define LASI_VER0x0C008 /* LASI Version Control register */ -- 2.20.1
[PATCH 48/50] hppa: use MACHINE QOM macros for defining the hppa machine
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/machine.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 13942ec596..dc9950d5d5 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -471,8 +471,8 @@ static void
machine_hppa_machine_init_class_init(ObjectClass *oc, void *data)
}
static const TypeInfo machine_hppa_machine_init_typeinfo = {
-.name = ("hppa" "-machine"),
-.parent = "machine",
+.name = MACHINE_TYPE_NAME("hppa"),
+.parent = TYPE_MACHINE,
.class_init = machine_hppa_machine_init_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NMI },
--
2.20.1
[PATCH 35/50] lasi: move second serial port initialisation to machine.c
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c| 8
hw/hppa/machine.c | 7 +++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 6faa98dca5..753a08d454 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -18,7 +18,6 @@
#include "sysemu/sysemu.h"
#include "sysemu/runstate.h"
#include "hppa_sys.h"
-#include "hw/char/serial.h"
#include "hw/input/lasips2.h"
#include "migration/vmstate.h"
#include "qom/object.h"
@@ -236,13 +235,6 @@ LasiState *lasi_initfn(MemoryRegion *address_space)
dev = qdev_new(TYPE_LASI_CHIP);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-if (serial_hd(1)) {
-/* Serial port */
-serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
-qdev_get_gpio_in(dev, LASI_IRQ_UART_HPA), 800 / 16,
-serial_hd(1), DEVICE_BIG_ENDIAN);
-}
-
/* PS/2 Keyboard/Mouse */
lasips2_init(address_space, LASI_PS2KBD_HPA,
qdev_get_gpio_in(dev, LASI_IRQ_PS2KBD_HPA));
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index c03312c301..1ef9ac5d8f 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -205,6 +205,13 @@ static void machine_hppa_init(MachineState *machine)
115200, serial_hd(0), DEVICE_BIG_ENDIAN);
}
+if (serial_hd(1)) {
+/* Serial port */
+serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0,
+qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 800 / 16,
+serial_hd(1), DEVICE_BIG_ENDIAN);
+}
+
/* Parallel port */
parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0,
qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA),
--
2.20.1
[PATCH 45/50] hppa: remove unused trace-events from from hw/hppa
Now that there are no longer any devices in hw/hppa the trace-events file is empty and can be removed. Signed-off-by: Mark Cave-Ayland --- hw/hppa/trace-events | 1 - meson.build | 1 - 2 files changed, 2 deletions(-) delete mode 100644 hw/hppa/trace-events diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events deleted file mode 100644 index 23bc9b19b9..00 --- a/hw/hppa/trace-events +++ /dev/null @@ -1 +0,0 @@ -# See docs/devel/tracing.rst for syntax documentation. diff --git a/meson.build b/meson.build index d083c6b7bf..8e6b97ba19 100644 --- a/meson.build +++ b/meson.build @@ -2713,7 +2713,6 @@ if have_system 'hw/char', 'hw/display', 'hw/dma', -'hw/hppa', 'hw/hyperv', 'hw/i2c', 'hw/i386', -- 2.20.1
[PATCH 33/50] lasi: move LAN initialisation to machine.c
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c| 7 ---
hw/hppa/machine.c | 5 +
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 65139bb29b..88ff9141e4 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -18,7 +18,6 @@
#include "sysemu/sysemu.h"
#include "sysemu/runstate.h"
#include "hppa_sys.h"
-#include "hw/net/lasi_82596.h"
#include "hw/char/parallel.h"
#include "hw/char/serial.h"
#include "hw/input/lasips2.h"
@@ -238,12 +237,6 @@ LasiState *lasi_initfn(MemoryRegion *address_space)
dev = qdev_new(TYPE_LASI_CHIP);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-/* LAN */
-if (enable_lasi_lan()) {
-lasi_82596_init(address_space, LASI_LAN_HPA,
-qdev_get_gpio_in(dev, LASI_IRQ_LAN_HPA));
-}
-
/* Parallel port */
parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
qdev_get_gpio_in(dev, LASI_IRQ_LAN_HPA),
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index be311294a8..c29528d03b 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -221,6 +221,11 @@ static void machine_hppa_init(MachineState *machine)
}
/* Network setup. */
+if (enable_lasi_lan()) {
+lasi_82596_init(addr_space, LASI_LAN_HPA,
+qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA));
+}
+
for (i = 0; i < nb_nics; i++) {
if (!enable_lasi_lan()) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "tulip", NULL);
--
2.20.1
[PATCH 42/50] lasi: move from hw/hppa to hw/misc
Move the LASI device implementation from hw/hppa to hw/misc so that it is
located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 ++
hw/hppa/Kconfig | 1 +
hw/hppa/machine.c | 2 +-
hw/hppa/meson.build | 2 +-
hw/hppa/trace-events| 5 -
hw/misc/Kconfig | 3 +++
hw/{hppa => misc}/lasi.c| 3 +--
hw/misc/meson.build | 3 +++
hw/misc/trace-events| 5 +
{hw/hppa => include/hw/misc}/lasi.h | 0
10 files changed, 17 insertions(+), 9 deletions(-)
rename hw/{hppa => misc}/lasi.c (99%)
rename {hw/hppa => include/hw/misc}/lasi.h (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 07f85829b0..162a1732d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1114,7 +1114,9 @@ S: Odd Fixes
F: configs/devices/hppa-softmmu/default.mak
F: hw/hppa/
F: hw/net/*i82596*
+F: hw/misc/lasi.c
F: hw/pci-host/dino.c
+F: include/hw/misc/lasi.h
F: include/hw/net/lasi_82596.h
F: include/hw/pci-host/dino.h
F: pc-bios/hppa-firmware.img
diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig
index 666a7319d6..99cc483263 100644
--- a/hw/hppa/Kconfig
+++ b/hw/hppa/Kconfig
@@ -4,6 +4,7 @@ config HPPA_GENERIC
imply E1000_PCI
imply VIRTIO_VGA
select DINO
+select LASI
select SERIAL
select ISA_BUS
select I8259
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index ebf447a9eb..98ba7b65dc 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -22,7 +22,7 @@
#include "hw/nmi.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/dino.h"
-#include "lasi.h"
+#include "hw/misc/lasi.h"
#include "hppa_sys.h"
#include "qemu/units.h"
#include "qapi/error.h"
diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build
index d3f839c6aa..92878d9ac1 100644
--- a/hw/hppa/meson.build
+++ b/hw/hppa/meson.build
@@ -1,4 +1,4 @@
hppa_ss = ss.source_set()
-hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('pci.c', 'machine.c',
'lasi.c'))
+hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('pci.c', 'machine.c'))
hw_arch += {'hppa': hppa_ss}
diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events
index 871a473771..1a4fbe2fa8 100644
--- a/hw/hppa/trace-events
+++ b/hw/hppa/trace-events
@@ -2,8 +2,3 @@
# pci.c
hppa_pci_iack_write(void) ""
-
-# lasi.c
-lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64"
is %d"
-lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
-lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 507058d8bf..cbabe9f78c 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -171,4 +171,7 @@ config SIFIVE_U_PRCI
config VIRT_CTRL
bool
+config LASI
+bool
+
source macio/Kconfig
diff --git a/hw/hppa/lasi.c b/hw/misc/lasi.c
similarity index 99%
rename from hw/hppa/lasi.c
rename to hw/misc/lasi.c
index 5ef36f3f58..23a7634a8c 100644
--- a/hw/hppa/lasi.c
+++ b/hw/misc/lasi.c
@@ -17,10 +17,9 @@
#include "hw/irq.h"
#include "sysemu/sysemu.h"
#include "sysemu/runstate.h"
-#include "hppa_sys.h"
#include "migration/vmstate.h"
#include "qom/object.h"
-#include "lasi.h"
+#include "hw/misc/lasi.h"
static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 2ff05c7afa..132b7b7344 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -134,3 +134,6 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true:
files('mips_cmgcr.c', 'mips_cp
specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
+
+# HPPA devices
+softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 4e0c7973a4..c5e37b0154 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -263,3 +263,8 @@ virt_ctrl_write(void *dev, unsigned int addr, unsigned int
size, uint64_t value)
virt_ctrl_reset(void *dev) "ctrl: %p"
virt_ctrl_realize(void *dev) "ctrl: %p"
virt_ctrl_instance_init(void *dev) "ctrl: %p"
+
+# lasi.c
+lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64"
is %d"
+lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
+lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
diff --git a/hw/hppa/lasi.h b/include/hw/misc/lasi.h
similarity index 100%
rename from hw/hppa/lasi.h
rename to include/hw/misc/lasi.h
--
2.20.1
[PATCH 40/50] lasi: use numerical constant for iar reset value
This is to allow us to decouple the LASI device from the board logic. If it is
decided later that this value needs to be configurable then it can easily be
converted to a qdev property.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/lasi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 11ca33fba3..5ef36f3f58 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -231,7 +231,7 @@ static void lasi_reset(DeviceState *dev)
{
LasiState *s = LASI_CHIP(dev);
-s->iar = CPU_HPA + 3;
+s->iar = 0xFFFB + 3; /* CPU_HPA + 3 */
/* Real time clock (RTC), it's only one 32-bit counter @9000 */
s->rtc = time(NULL);
--
2.20.1
[PATCH 22/50] dino: move from hw/hppa to hw/pci-host
Move the DINO device implementation from hw/hppa to hw/pci-host so that it is
located with all the other PCI host bridges.
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 ++
hw/hppa/Kconfig | 2 +-
hw/hppa/machine.c | 2 +-
hw/hppa/meson.build | 2 +-
hw/hppa/trace-events| 5 -
hw/pci-host/Kconfig | 4
hw/{hppa => pci-host}/dino.c| 3 +--
hw/pci-host/meson.build | 3 +++
hw/pci-host/trace-events| 5 +
{hw/hppa => include/hw/pci-host}/dino.h | 0
10 files changed, 18 insertions(+), 10 deletions(-)
rename hw/{hppa => pci-host}/dino.c (99%)
rename {hw/hppa => include/hw/pci-host}/dino.h (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 294c88ace9..07f85829b0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1114,7 +1114,9 @@ S: Odd Fixes
F: configs/devices/hppa-softmmu/default.mak
F: hw/hppa/
F: hw/net/*i82596*
+F: hw/pci-host/dino.c
F: include/hw/net/lasi_82596.h
+F: include/hw/pci-host/dino.h
F: pc-bios/hppa-firmware.img
M68K Machines
diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig
index 02e101f139..666a7319d6 100644
--- a/hw/hppa/Kconfig
+++ b/hw/hppa/Kconfig
@@ -3,7 +3,7 @@ config HPPA_GENERIC
imply PCI_DEVICES
imply E1000_PCI
imply VIRTIO_VGA
-select PCI
+select DINO
select SERIAL
select ISA_BUS
select I8259
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 7b8cfce3c9..b66e95982e 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -17,7 +17,7 @@
#include "hw/char/serial.h"
#include "hw/net/lasi_82596.h"
#include "hw/nmi.h"
-#include "dino.h"
+#include "hw/pci-host/dino.h"
#include "hppa_sys.h"
#include "qemu/units.h"
#include "qapi/error.h"
diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build
index af37b4469e..d3f839c6aa 100644
--- a/hw/hppa/meson.build
+++ b/hw/hppa/meson.build
@@ -1,4 +1,4 @@
hppa_ss = ss.source_set()
-hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('pci.c', 'machine.c',
'dino.c', 'lasi.c'))
+hppa_ss.add(when: 'CONFIG_HPPA_GENERIC', if_true: files('pci.c', 'machine.c',
'lasi.c'))
hw_arch += {'hppa': hppa_ss}
diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events
index 3f42be9056..871a473771 100644
--- a/hw/hppa/trace-events
+++ b/hw/hppa/trace-events
@@ -3,11 +3,6 @@
# pci.c
hppa_pci_iack_write(void) ""
-# dino.c
-dino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64"
is %d"
-dino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
-dino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
-
# lasi.c
lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64"
is %d"
lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 2b5f7d58cc..38fd2ee8f3 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -77,3 +77,7 @@ config MV64361
bool
select PCI
select I8259
+
+config DINO
+bool
+select PCI
diff --git a/hw/hppa/dino.c b/hw/pci-host/dino.c
similarity index 99%
rename from hw/hppa/dino.c
rename to hw/pci-host/dino.c
index aa7f812e22..f257c24e64 100644
--- a/hw/hppa/dino.c
+++ b/hw/pci-host/dino.c
@@ -18,9 +18,8 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"
-#include "dino.h"
+#include "hw/pci-host/dino.h"
#include "migration/vmstate.h"
-#include "hppa_sys.h"
#include "trace.h"
#include "qom/object.h"
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 4c4f39c15c..c07596d0d1 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -25,6 +25,9 @@ pci_ss.add(when: 'CONFIG_MV64361', if_true:
files('mv64361.c'))
# ARM devices
pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c'))
+# HPPA devices
+pci_ss.add(when: 'CONFIG_DINO', if_true: files('dino.c'))
+
softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 6e5d8d3355..437e66ff50 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -34,3 +34,8 @@ unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 "
val=0x%"PRIx64
pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64"
data=0x%"PRIx64
pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data) "addr=@0x%"PRIx64"
data=0x%"PRIx64
pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data)
"notif=@0x%"PRIx64" data=0x%"PRIx64
+
+# dino.c
+dino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64"
is %d"
+dino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
+dino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
diff --git a/hw/hppa/dino.h b/include/hw/pci-host/dino.h
similarity index 100%
rena
[PATCH 38/50] lasi: move lasi_initfn() to machine.c
Move the simplified lasi_initfn() back to machine.c whilst also renaming it
back to its original lasi_init() name.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 --
hw/hppa/lasi.c | 10 --
hw/hppa/machine.c | 12 +++-
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index 31e3856059..f7a127be19 100644
--- a/hw/hppa/hppa_sys.h
+++ b/hw/hppa/hppa_sys.h
@@ -7,11 +7,9 @@
#include "hw/pci/pci_host.h"
#include "hw/boards.h"
#include "hw/intc/i8259.h"
-#include "lasi.h"
#include "hppa_hardware.h"
-LasiState *lasi_initfn(void);
#define enable_lasi_lan() 0
/* hppa_pci.c. */
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 81c8e4d2d9..ad50880a13 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -227,16 +227,6 @@ static void lasi_set_irq(void *opaque, int irq, int level)
}
}
-LasiState *lasi_initfn(void)
-{
-DeviceState *dev;
-
-dev = qdev_new(TYPE_LASI_CHIP);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-
-return LASI_CHIP(dev);
-}
-
static void lasi_reset(DeviceState *dev)
{
LasiState *s = LASI_CHIP(dev);
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index c4b2e69241..c8eee6398a 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -125,6 +125,16 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
return fw_cfg;
}
+static LasiState *lasi_init(void)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_LASI_CHIP);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+return LASI_CHIP(dev);
+}
+
static DinoState *dino_init(MemoryRegion *addr_space)
{
DeviceState *dev;
@@ -178,7 +188,7 @@ static void machine_hppa_init(MachineState *machine)
/* Init Lasi chip */
-lasi_dev = DEVICE(lasi_initfn());
+lasi_dev = DEVICE(lasi_init());
memory_region_add_subregion(addr_space, LASI_HPA,
sysbus_mmio_get_region(
SYS_BUS_DEVICE(lasi_dev), 0));
--
2.20.1
[PATCH 21/50] dino: move DINO HPA constants from hppa_hardware.h to dino.h
This is to allow us to decouple the DINO device from the board logic.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/dino.h | 5 +
hw/hppa/hppa_hardware.h | 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/hppa/dino.h b/hw/hppa/dino.h
index ca380515f2..a1b0184940 100644
--- a/hw/hppa/dino.h
+++ b/hw/hppa/dino.h
@@ -101,6 +101,11 @@ static const uint32_t reg800_keep_bits[DINO800_REGS] = {
MAKE_64BIT_MASK(0, 9), /* TLTIM */
};
+/* offsets to DINO HPA: */
+#define DINO_PCI_ADDR 0x064
+#define DINO_CONFIG_DATA0x068
+#define DINO_IO_DATA0x06c
+
struct DinoState {
PCIHostState parent_obj;
diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h
index 5edf577563..8b6b9222cb 100644
--- a/hw/hppa/hppa_hardware.h
+++ b/hw/hppa/hppa_hardware.h
@@ -30,11 +30,6 @@
#define PCI_HPA DINO_HPA/* PCI bus */
#define IDE_HPA 0xf900 /* Boot disc controller */
-/* offsets to DINO HPA: */
-#define DINO_PCI_ADDR 0x064
-#define DINO_CONFIG_DATA0x068
-#define DINO_IO_DATA0x06c
-
#define PORT_PCI_CMD(PCI_HPA + DINO_PCI_ADDR)
#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA)
--
2.20.1
[PATCH 37/50] lasi: remove address space parameter from lasi_initfn()
Now that all of the LASI devices are mapped by the board, this parameter is no
longer required.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 2 +-
hw/hppa/lasi.c | 2 +-
hw/hppa/machine.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index 3832b787d1..31e3856059 100644
--- a/hw/hppa/hppa_sys.h
+++ b/hw/hppa/hppa_sys.h
@@ -11,7 +11,7 @@
#include "hppa_hardware.h"
-LasiState *lasi_initfn(MemoryRegion *);
+LasiState *lasi_initfn(void);
#define enable_lasi_lan() 0
/* hppa_pci.c. */
diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c
index 9d8c9e3936..81c8e4d2d9 100644
--- a/hw/hppa/lasi.c
+++ b/hw/hppa/lasi.c
@@ -227,7 +227,7 @@ static void lasi_set_irq(void *opaque, int irq, int level)
}
}
-LasiState *lasi_initfn(MemoryRegion *address_space)
+LasiState *lasi_initfn(void)
{
DeviceState *dev;
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 094f5138b4..c4b2e69241 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -178,7 +178,7 @@ static void machine_hppa_init(MachineState *machine)
/* Init Lasi chip */
-lasi_dev = DEVICE(lasi_initfn(addr_space));
+lasi_dev = DEVICE(lasi_initfn());
memory_region_add_subregion(addr_space, LASI_HPA,
sysbus_mmio_get_region(
SYS_BUS_DEVICE(lasi_dev), 0));
--
2.20.1
