Re: [PATCH v7 05/20] linux-user: Clear translations and tb_jmp_cache on mprotect()
On 8/31/22 00:17, Ilya Leoshkevich wrote:
page_set_flags(start, start + len, page_flags);
+ tb_invalidate_phys_range(start, start + len);
+
+ CPU_FOREACH(cpu) {
+ cpu_tb_jmp_cache_clear(cpu);
+ }
+
mmap_unlock();
return 0;
error:
I think adding tb_invalidate_phys_range() obviates the need for
cpu_tb_jmp_cache_clear()? The lookup may still find an invalidated tb,
but it will have CF_INVALID set.
Quite right. And we definitely don't want to have to touch a list of all threads if its
not necessary.
r~
[PULL 4/4] target/avr: Disable interrupts when env->skip set
This bit is not saved across interrupts, so we must
delay delivering the interrupt until the skip has
been processed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1118
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c| 9 +
target/avr/translate.c | 26 ++
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 34f1cbffb2..156dde4e92 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -31,6 +31,15 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = >env;
+/*
+ * We cannot separate a skip from the next instruction,
+ * as the skip would not be preserved across the interrupt.
+ * Separating the two insn normally only happens at page boundaries.
+ */
+if (env->skip) {
+return false;
+}
+
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
diff --git a/target/avr/translate.c b/target/avr/translate.c
index dc9c3d6bcc..026753c963 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2971,8 +2971,18 @@ static void avr_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
if (skip_label) {
canonicalize_skip(ctx);
gen_set_label(skip_label);
-if (ctx->base.is_jmp == DISAS_NORETURN) {
+
+switch (ctx->base.is_jmp) {
+case DISAS_NORETURN:
ctx->base.is_jmp = DISAS_CHAIN;
+break;
+case DISAS_NEXT:
+if (ctx->base.tb->flags & TB_FLAGS_SKIP) {
+ctx->base.is_jmp = DISAS_TOO_MANY;
+}
+break;
+default:
+break;
}
}
@@ -2989,6 +2999,11 @@ static void avr_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
bool nonconst_skip = canonicalize_skip(ctx);
+/*
+ * Because we disable interrupts while env->skip is set,
+ * we must return to the main loop to re-evaluate afterward.
+ */
+bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP;
switch (ctx->base.is_jmp) {
case DISAS_NORETURN:
@@ -2997,7 +3012,7 @@ static void avr_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
case DISAS_NEXT:
case DISAS_TOO_MANY:
case DISAS_CHAIN:
-if (!nonconst_skip) {
+if (!nonconst_skip && !force_exit) {
/* Note gen_goto_tb checks singlestep. */
gen_goto_tb(ctx, 1, ctx->npc);
break;
@@ -3005,8 +3020,11 @@ static void avr_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
tcg_gen_movi_tl(cpu_pc, ctx->npc);
/* fall through */
case DISAS_LOOKUP:
-tcg_gen_lookup_and_goto_ptr();
-break;
+if (!force_exit) {
+tcg_gen_lookup_and_goto_ptr();
+break;
+}
+/* fall through */
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
--
2.34.1
[PULL 3/4] target/avr: Only execute one interrupt at a time
We cannot deliver two interrupts simultaneously;
the first interrupt handler must execute first.
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 9614ccf3e4..34f1cbffb2 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -28,7 +28,6 @@
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
-bool ret = false;
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = >env;
@@ -38,8 +37,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
avr_cpu_do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
-
-ret = true;
+return true;
}
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -52,11 +50,10 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (!env->intsrc) {
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
}
-
-ret = true;
+return true;
}
}
-return ret;
+return false;
}
void avr_cpu_do_interrupt(CPUState *cs)
--
2.34.1
[PULL 2/4] target/avr: Call avr_cpu_do_interrupt directly
There is no need to go through cc->tcg_ops when
we know what value that must have.
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 82284f8997..9614ccf3e4 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -29,14 +29,13 @@
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
bool ret = false;
-CPUClass *cc = CPU_GET_CLASS(cs);
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = >env;
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
-cc->tcg_ops->do_interrupt(cs);
+avr_cpu_do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -47,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
-cc->tcg_ops->do_interrupt(cs);
+avr_cpu_do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
if (!env->intsrc) {
--
2.34.1
[PULL 1/4] target/avr: Support probe argument to tlb_fill
While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.
Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 46 -
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index db76452f9a..82284f8997 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -102,38 +102,50 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
-int prot = 0;
-MemTxAttrs attrs = {};
+int prot, page_size = TARGET_PAGE_SIZE;
uint32_t paddr;
address &= TARGET_PAGE_MASK;
if (mmu_idx == MMU_CODE_IDX) {
-/* access to code in flash */
+/* Access to code in flash. */
paddr = OFFSET_CODE + address;
prot = PAGE_READ | PAGE_EXEC;
-if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
+if (paddr >= OFFSET_DATA) {
+/*
+ * This should not be possible via any architectural operations.
+ * There is certainly not an exception that we can deliver.
+ * Accept probing that might come from generic code.
+ */
+if (probe) {
+return false;
+}
error_report("execution left flash memory");
abort();
}
-} else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
-/*
- * access to CPU registers, exit and rebuilt this TB to use full access
- * incase it touches specially handled registers like SREG or SP
- */
-AVRCPU *cpu = AVR_CPU(cs);
-CPUAVRState *env = >env;
-env->fullacc = 1;
-cpu_loop_exit_restore(cs, retaddr);
} else {
-/* access to memory. nothing special */
+/* Access to memory. */
paddr = OFFSET_DATA + address;
prot = PAGE_READ | PAGE_WRITE;
+if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
+/*
+ * Access to CPU registers, exit and rebuilt this TB to use
+ * full access in case it touches specially handled registers
+ * like SREG or SP. For probing, set page_size = 1, in order
+ * to force tlb_fill to be called for the next access.
+ */
+if (probe) {
+page_size = 1;
+} else {
+AVRCPU *cpu = AVR_CPU(cs);
+CPUAVRState *env = >env;
+env->fullacc = 1;
+cpu_loop_exit_restore(cs, retaddr);
+}
+}
}
-tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
-mmu_idx, TARGET_PAGE_SIZE);
-
+tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
return true;
}
--
2.34.1
[PULL 0/4] target/avr patch queue
The following changes since commit e93ded1bf6c94ab95015b33e188bc8b0b0c32670: Merge tag 'testing-pull-request-2022-08-30' of https://gitlab.com/thuth/qemu into staging (2022-08-31 18:19:03 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-avr-20220901 for you to fetch changes up to 36027c70974fef1392e6c73dfb94c3f94f0930bc: target/avr: Disable interrupts when env->skip set (2022-09-01 06:42:21 +0100) Fix avr_cpu_tlb_fill use of probe argument Fix skip instructions being separated from the next insn (#1118) Richard Henderson (4): target/avr: Support probe argument to tlb_fill target/avr: Call avr_cpu_do_interrupt directly target/avr: Only execute one interrupt at a time target/avr: Disable interrupts when env->skip set target/avr/helper.c| 69 +++--- target/avr/translate.c | 26 --- 2 files changed, 65 insertions(+), 30 deletions(-)
Re: [PATCH for-7.2 v4 15/21] qmp/hmp, device_tree.c: introduce 'info fdt' command
On Tue, Aug 30, 2022 at 12:43:23PM +0200, Markus Armbruster wrote:
> David Gibson writes:
>
> > On Mon, Aug 29, 2022 at 07:00:55PM -0300, Daniel Henrique Barboza wrote:
> >>
> >>
> >> On 8/29/22 00:34, David Gibson wrote:
> >> > On Fri, Aug 26, 2022 at 11:11:44AM -0300, Daniel Henrique Barboza wrote:
> >> > > Reading the FDT requires that the user saves the fdt_blob and then use
> >> > > 'dtc' to read the contents. Saving the file and using 'dtc' is a strong
> >> > > use case when we need to compare two FDTs, but it's a lot of steps if
> >> > > you want to do quick check on a certain node or property.
> >> > >
> >> > > 'info fdt' retrieves FDT nodes (and properties, later on) and print it
> >> > > to the user. This can be used to check the FDT on running machines
> >> > > without having to save the blob and use 'dtc'.
> >> > >
> >> > > The implementation is based on the premise that the machine thas a FDT
> >> > > created using libfdt and pointed by 'machine->fdt'. As long as this
> >> > > pre-requisite is met the machine should be able to support it.
> >> > >
> >> > > For now we're going to add the required QMP/HMP boilerplate and the
> >> > > capability of printing the name of the properties of a given node. Next
> >> > > patches will extend 'info fdt' to be able to print nodes recursively,
> >> > > and then individual properties.
> >> > >
> >> > > This command will always be executed in-band (i.e. holding BQL),
> >> > > avoiding potential race conditions with machines that might change the
> >> > > FDT during runtime (e.g. PowerPC 'pseries' machine).
> >> > >
> >> > > 'info fdt' is not something that we expect to be used aside from
> >> > > debugging,
> >> > > so we're implementing it in QMP as 'x-query-fdt'.
> >> > >
> >> > > This is an example of 'info fdt' fetching the '/chosen' node of the
> >> > > pSeries machine:
> >> > >
> >> > > (qemu) info fdt /chosen
> >> > > chosen {
> >> > > ibm,architecture-vec-5;
> >> > > rng-seed;
> >> > > ibm,arch-vec-5-platform-support;
> >> > > linux,pci-probe-only;
> >> > > stdout-path;
> >> > > linux,stdout-path;
> >> > > qemu,graphic-depth;
> >> > > qemu,graphic-height;
> >> > > qemu,graphic-width;
> >> > > };
> >> > >
> >> > > And the same node for the aarch64 'virt' machine:
> >> > >
> >> > > (qemu) info fdt /chosen
> >> > > chosen {
> >> > > stdout-path;
> >> > > rng-seed;
> >> > > kaslr-seed;
> >> > > };
> >> >
> >> > So, I'm reasonably convinced allowing dumping the whole dtb from
> >> > qmp/hmp is useful. I'm less convined that info fdt is worth the
> >> > additional complexity it incurs. Note that as well as being able to
> >> > decompile a whole dtb using dtc, you can also extract and list
> >> > specific properties from a dtb blob using the 'fdtget' tool which is
> >> > part of the dtc tree.
> >>
> >> What's your opinion on patch 21/21, where 'dumpdtb' can write a formatted
> >> FDT in a file with an extra option? That was possible because of the
> >> format helpers introduced for 'info fdt'. The idea is that since we're
> >> able to format a FDT in DTS format, we can also write the FDT in text
> >> format without relying on DTC to decode it.
> >
> > Since it's mostly the same code, I think it's reasonable to throw in
> > if the info fdt stuff is there, but I don't think it's worth including
> > without that. As a whole, I remain dubious that (info fdt + dumpdts)
> > is worth the complexity cost.
>
> How much code does it take, and who's going to maintain it?
It's not especially big, but it's not negligible. Perhaps the part
that I'm most uncomfortable about is that it requires a bunch of messy
heuristics to guess how to format the output - DT properties are just
bytestrings, any internal interpretation is based on the specific
bindings for them.
dtc already has these and I don't love having a second, potentially
different copy of necessarily imperfect heuristics out in the wild.
> > People with more practical experience debugging the embedded ARM
> > platforms might have a different opinion if they thing info fdt would
> > be really useful though.
>
> They better speak up then :)
Just so.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
Re: [RFC] hw/registerfields: add `FIELDx_1CLEAR()` macro
On 9/1/22 02:02, Wilfred Mallawa wrote:
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the respective field is cleared and returned to `data`.
If ALL bits of the bitfield are not set, then no change and
val is returned.
Signed-off-by: Wilfred Mallawa
Why do these operations need to go into hw/registerfields.h?
It's not a common operation, since we've never needed it so far.
r~
---
include/hw/registerfields.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 1330ca77de..5a804f72e3 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -115,6 +115,34 @@
R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
_d; })
+/* Get the max value (uint) discribed by `num_bits` bits */
+#define MAX_N_BITS(num_bits) ((1 << (num_bits)) - 1)
+
+/*
+ * Clear the specified field in reg_val if
+ * all field bits are set, else no changes made. Implements
+ * single/multi-bit `rw1c`
+ */
+#define FIELD8_1CLEAR(reg_val, reg, field)\
+((FIELD_EX8(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP8(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD16_1CLEAR(reg_val, reg, field) \
+((FIELD_EX16(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP16(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD32_1CLEAR(reg_val, reg, field) \
+((FIELD_EX32(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP32(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD64_1CLEAR(reg_val, reg, field) \
+((FIELD_EX64(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP64(reg_val, reg, field, 0x00) : reg_val)
+
#define FIELD_SDP8(storage, reg, field, val) ({ \
struct { \
signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
Re: TCG IR extraction
On 8/31/22 19:11, Tom Clark wrote: I've done a lot of digging in the source and found the code_gen_buffer and determined that's where the IR generation is being written to That's not IR generation, but the JIT compiler output. There's no sequential "byte" format. There's struct TCGOp, which is the double-linked list of operations and its parameters, which are (encoded) TCGTemp and constants, and you need tcg_op_defs[] to interpret them. See e.g. tcg_optimize() for how to iterate through the list and interpret each opcode. r~
Re: [PATCH 2/2] util/log: add timestamp to logs via qemu_log()
Hi Markus and Richard,
Thank you very much for the feedback. I agree this is not a good solution. I
will look for alternatives to add timestamp.
Thank you very much!
Dongli Zhang
On 8/30/22 8:31 AM, Richard Henderson wrote:
> On 8/30/22 04:09, Markus Armbruster wrote:
>> Dongli Zhang writes:
>>
>>> The qemu_log is very helpful for diagnostic. Add the timestamp to the log
>>> when it is enabled (e.g., "-msg timestamp=on").
>>>
>>> While there are many other places that may print to log file, this patch is
>>> only for qemu_log(), e.g., the developer may add qemu_log/qemu_log_mask to
>>> selected locations to diagnose QEMU issue.
>>
>> Opinions on the new feature, anyone?
>>
>>> Cc: Joe Jin
>>> Signed-off-by: Dongli Zhang
>>> ---
>>> Please let me know if we should use 'error_with_guestname' as well.
>>>
>>> util/log.c | 7 +++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/util/log.c b/util/log.c
>>> index d6eb037..f0a081a 100644
>>> --- a/util/log.c
>>> +++ b/util/log.c
>>> @@ -129,8 +129,15 @@ void qemu_log(const char *fmt, ...)
>>> {
>>> FILE *f = qemu_log_trylock();
>>> if (f) {
>>> + gchar *timestr;
>>> va_list ap;
>>> + if (message_with_timestamp) {
>>> + timestr = real_time_iso8601();
>>> + fprintf(f, "%s ", timestr);
>>> + g_free(timestr);
>>> + }
>>> +
>>> va_start(ap, fmt);
>>> vfprintf(f, fmt, ap);
>>> va_end(ap);
>>
>> This extends -msg timestamp=on to apply to log messages without
>> documenting it in -help or anywhere else. Needs fixing.
>
> I think this is a poor place to add the timestamp.
>
> You'll find that qemu_log is used many times to assemble pieces, e.g.
>
> linux-user/thunk.c:360: qemu_log("%" PRIu64, tswap64(val));
>
> linux-user/thunk.c:376: qemu_log("\"");
>
> linux-user/thunk.c:379: qemu_log("[");
>
> linux-user/thunk.c:384: qemu_log(",");
>
> linux-user/thunk.c:391: qemu_log("\"");
>
> linux-user/thunk.c:393: qemu_log("]");
>
> linux-user/thunk.c:417: qemu_log("{");
>
> linux-user/thunk.c:420: qemu_log(",");
>
> linux-user/thunk.c:424: qemu_log("}");
>
>
> Not the best idea, really, but the replacement for this is to avoid qemu_log
> entirely, and use
>
> f = qemu_log_trylock();
> if (f) {
> fprintf
> some
> stuff
> qemu_log_unlock(f);
> }
>
> at which point you don't get your timestamp either. You'd need to explicitly
> add timestamps to individual locations.
>
> It would probably be easier to add timestamps to tracepoints, which are always
> emitted as a unit.
>
>
> r~
>
[PATCH v3 5/5] test/acpi/bios-tables-test: SSDT: update golden master binaries
And empty bios-tables-test-allowed-diff.h.
Diff of ASL form, cited from qtest testlog.txt:
--- /tmp/asl-0WHMR1.dsl 2022-08-30 11:38:09.406635934 +0800
+++ /tmp/asl-APDMR1.dsl 2022-08-30 11:38:09.403635663 +0800
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Tue Aug 30 11:38:09 2022
+ * Disassembly of /tmp/aml-1AEMR1, Tue Aug 30 11:38:09 2022
*
* Original Table Header:
* Signature"SSDT"
- * Length 0x02DE (734)
+ * Length 0x0765 (1893)
* Revision 0x01
- * Checksum 0x56
+ * Checksum 0x36
* OEM ID "BOCHS "
* OEM Table ID "NVDIMM"
* OEM Revision 0x0001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x0001 (1)
*/
DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x0001)
{
Scope (\_SB)
{
Device (NVDR)
{
Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID:
Hardware ID
Method (NCAL, 5, Serialized)
{
Local6 = MEMA /* \MEMA */
@@ -49,52 +49,52 @@
ODAT, 32736
}
If ((Arg4 == Zero))
{
Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba")
}
ElseIf ((Arg4 == 0x0001))
{
Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62")
}
Else
{
Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66")
}
-If (((Local6 == Zero) | (Arg0 != Local0)))
+If (((Local6 == Zero) || (Arg0 != Local0)))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x00
// .
})
}
Return (Buffer (One)
{
0x01 // .
})
}
HDLE = Arg4
REVS = Arg1
FUNC = Arg2
-If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
+If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One)))
{
Local2 = Arg3 [Zero]
Local3 = DerefOf (Local2)
FARG = Local3
}
NTFI = Local6
Local1 = (RLEN - 0x04)
If ((Local1 < 0x08))
{
Local2 = Zero
Name (TBUF, Buffer (One)
{
0x00 // .
})
Local7 = Buffer (Zero){}
@@ -161,45 +161,234 @@
Else
{
If ((Local1 == Zero))
{
Return (Local2)
}
Local3 += Local1
Concatenate (Local2, Local0, Local2)
}
}
}
Device (NV00)
{
Name (_ADR, One) // _ADR: Address
+Method (_LSI, 0, Serialized) // _LSI: Label Storage
Information
+{
+Local0 = NCAL (ToUUID
("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x04, Zero, One)
+CreateDWordField (Local0, Zero, STTS)
+CreateDWordField (Local0, 0x04, SLSA)
+CreateDWordField (Local0, 0x08, MAXT)
+Name (RET, Package (0x03)
+{
+STTS,
+SLSA,
+MAXT
+})
+Return (RET) /* \_SB_.NVDR.NV00._LSI.RET_ */
+}
+
+Method (_LSR, 2, Serialized) // _LSR: Label Storage Read
+{
+Name (INPT, Buffer (0x08)
+{
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 //
+})
+CreateDWordField (INPT, Zero, OFST)
+CreateDWordField (INPT, 0x04, LEN)
+OFST = Arg0
+LEN = Arg1
+Name (PKG1, Package (0x01)
+{
+INPT
+})
+Local3 = NCAL (ToUUID
[PATCH v3 3/5] acpi/nvdimm: define macro for NVDIMM Device _DSM
Since it will be heavily used in next patch, define macro
NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is
NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec,
Section 3. [1]
No functional changes in this patch.
[1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
Signed-off-by: Robert Hoo
Reviewed-by: Jingqi Liu
---
hw/acpi/nvdimm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index 201317c611..afff911c1e 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -922,6 +922,7 @@ void nvdimm_init_acpi_state(NVDIMMState *state,
MemoryRegion *io,
#define NVDIMM_DSM_RFIT_STATUS "RSTA"
#define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62"
+#define NVDIMM_DEVICE_DSM_UUID "4309AC30-0D11-11E4-9191-0800200C9A66"
static void nvdimm_build_common_dsm(Aml *dev,
NVDIMMState *nvdimm_state)
@@ -1029,8 +1030,7 @@ static void nvdimm_build_common_dsm(Aml *dev,
/* UUID for QEMU internal use */), expected_uuid));
aml_append(elsectx, ifctx);
elsectx2 = aml_else();
-aml_append(elsectx2, aml_store(
- aml_touuid("4309AC30-0D11-11E4-9191-0800200C9A66")
+aml_append(elsectx2, aml_store(aml_touuid(NVDIMM_DEVICE_DSM_UUID)
/* UUID for NVDIMM Devices */, expected_uuid));
aml_append(elsectx, elsectx2);
aml_append(method, elsectx);
--
2.31.1
[PATCH v3 4/5] acpi/nvdimm: Implement ACPI NVDIMM Label Methods
Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which
deprecates corresponding _DSM Functions defined by PMEM _DSM Interface spec
[2].
Since the semantics of the new Label Methods are same as old _DSM
methods, the implementations here simply wrapper old ones.
ASL form diff can be found in next patch of updating golden master
binaries.
[1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods
https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
[2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions
https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
Signed-off-by: Robert Hoo
Reviewed-by: Jingqi Liu
---
hw/acpi/nvdimm.c | 91
1 file changed, 91 insertions(+)
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index afff911c1e..516acfe53b 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -1243,6 +1243,7 @@ static void nvdimm_build_fit(Aml *dev)
static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots)
{
uint32_t slot;
+Aml *method, *pkg, *field, *com_call;
for (slot = 0; slot < ram_slots; slot++) {
uint32_t handle = nvdimm_slot_to_handle(slot);
@@ -1260,6 +1261,96 @@ static void nvdimm_build_nvdimm_devices(Aml *root_dev,
uint32_t ram_slots)
*/
aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
+/*
+ * ACPI v6.4: Section 6.5.10 NVDIMM Label Methods
+ */
+/* _LSI */
+method = aml_method("_LSI", 0, AML_SERIALIZED);
+com_call = aml_call5(NVDIMM_COMMON_DSM,
+aml_touuid(NVDIMM_DEVICE_DSM_UUID),
+aml_int(1), aml_int(4), aml_int(0),
+aml_int(handle));
+aml_append(method, aml_store(com_call, aml_local(0)));
+
+aml_append(method, aml_create_dword_field(aml_local(0),
+ aml_int(0), "STTS"));
+aml_append(method, aml_create_dword_field(aml_local(0), aml_int(4),
+ "SLSA"));
+aml_append(method, aml_create_dword_field(aml_local(0), aml_int(8),
+ "MAXT"));
+
+pkg = aml_package(3);
+aml_append(pkg, aml_name("STTS"));
+aml_append(pkg, aml_name("SLSA"));
+aml_append(pkg, aml_name("MAXT"));
+aml_append(method, aml_name_decl("RET", pkg));
+aml_append(method, aml_return(aml_name("RET")));
+
+aml_append(nvdimm_dev, method);
+
+/* _LSR */
+method = aml_method("_LSR", 2, AML_SERIALIZED);
+aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL)));
+
+aml_append(method, aml_create_dword_field(aml_name("INPT"),
+ aml_int(0), "OFST"));
+aml_append(method, aml_create_dword_field(aml_name("INPT"),
+ aml_int(4), "LEN"));
+aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
+aml_append(method, aml_store(aml_arg(1), aml_name("LEN")));
+
+pkg = aml_package(1);
+aml_append(pkg, aml_name("INPT"));
+aml_append(method, aml_name_decl("PKG1", pkg));
+
+com_call = aml_call5(NVDIMM_COMMON_DSM,
+aml_touuid(NVDIMM_DEVICE_DSM_UUID),
+aml_int(1), aml_int(5), aml_name("PKG1"),
+aml_int(handle));
+aml_append(method, aml_store(com_call, aml_local(3)));
+field = aml_create_dword_field(aml_local(3), aml_int(0), "STTS");
+aml_append(method, field);
+field = aml_create_field(aml_local(3), aml_int(32),
+ aml_shiftleft(aml_name("LEN"), aml_int(3)),
+ "LDAT");
+aml_append(method, field);
+aml_append(method, aml_name_decl("LSA", aml_buffer(0, NULL)));
+aml_append(method, aml_to_buffer(aml_name("LDAT"), aml_name("LSA")));
+pkg = aml_package(2);
+aml_append(pkg, aml_name("STTS"));
+aml_append(pkg, aml_name("LSA"));
+aml_append(method, aml_name_decl("RET", pkg));
+aml_append(method, aml_return(aml_name("RET")));
+aml_append(nvdimm_dev, method);
+
+/* _LSW */
+method = aml_method("_LSW", 3, AML_SERIALIZED);
+aml_append(method, aml_store(aml_arg(2), aml_local(2)));
+aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL)));
+field = aml_create_dword_field(aml_name("INPT"),
+ aml_int(0), "OFST");
+aml_append(method, field);
+field = aml_create_dword_field(aml_name("INPT"),
+ aml_int(4), "TLEN");
+aml_append(method, field);
+aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
+aml_append(method,
[PATCH v3 2/5] acpi/ssdt: Fix aml_or() and aml_and() in if clause
In If condition, using bitwise and/or, rather than logical and/or.
The result change in AML code:
If (((Local6 == Zero) | (Arg0 != Local0)))
==>
If (((Local6 == Zero) || (Arg0 != Local0)))
If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
==>
If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One)))
Fixes: 90623ebf603 ("nvdimm acpi: check UUID")
Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method")
Signed-off-by: Robert Hoo
Reviewed-by: Jingqi Liu
Reviewed-by: Igor Mammedov
---
hw/acpi/nvdimm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index 31e46df0bd..201317c611 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -1037,7 +1037,7 @@ static void nvdimm_build_common_dsm(Aml *dev,
uuid_invalid = aml_lnot(aml_equal(uuid, expected_uuid));
-unsupport = aml_if(aml_or(unpatched, uuid_invalid, NULL));
+unsupport = aml_if(aml_lor(unpatched, uuid_invalid));
/*
* function 0 is called to inquire what functions are supported by
@@ -1069,10 +1069,9 @@ static void nvdimm_build_common_dsm(Aml *dev,
* in the DSM Spec.
*/
pckg = aml_arg(3);
-ifctx = aml_if(aml_and(aml_equal(aml_object_type(pckg),
+ifctx = aml_if(aml_land(aml_equal(aml_object_type(pckg),
aml_int(4 /* Package */)) /* It is a Package? */,
- aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */,
- NULL));
+ aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */));
pckg_index = aml_local(2);
pckg_buf = aml_local(3);
--
2.31.1
[PATCH v3 1/5] tests/acpi: allow SSDT changes
Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..eb8bae1407 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/q35/SSDT.dimmpxm", -- 2.31.1
[PATCH v3 0/5] Support ACPI NVDIMM Label Methods
Originally NVDIMM Label methods was defined in Intel PMEM _DSM Interface
Spec [1], of function index 4, 5 and 6.
Recent ACPI spec [2] has deprecated those _DSM methods with ACPI NVDIMM
Label Methods _LS{I,R,W}. The essence of these functions has no changes.
This patch set is to update QEMU emulation on this, as well as update
bios-table-test golden binaries.
[1] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions
https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
[2] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods
https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
---
Change Log:
v2 --> v3:
Patch of nvdimm_debug() --> qemu trace, has been separated and already
upstream'ed.
Patch of accepting _DSM rev.2 is dropped, as unnecessary.
Roll back implementation to the idea of simply wrapper _DSM.
v1 --> v2:
Almost rewritten
Separate Patch 2
Dance with tests/qtest/bios-table-tests
Add trace event
Robert Hoo (5):
tests/acpi: allow SSDT changes
acpi/ssdt: Fix aml_or() and aml_and() in if clause
acpi/nvdimm: define macro for NVDIMM Device _DSM
acpi/nvdimm: Implement ACPI NVDIMM Label Methods
test/acpi/bios-tables-test: SSDT: update golden master binaries
hw/acpi/nvdimm.c | 102 +--
tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 1893 bytes
tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 1893 bytes
3 files changed, 96 insertions(+), 6 deletions(-)
--
2.31.1
回复：Any interest in a QEMU emulation BoF at KVM Forum?
These topics are interesting. I have two questions. 1. Can we join it on online? If so, could you share the meeting link before the meeting. 2. If it is only offline, could you share the meeting content to the public? Thanks, Zhiwei -- 发件人：Alex Bennée 发送时间：2022年9月1日(星期四) 01:08 收件人：qemu-devel@nongnu.org 抄 送：Mark Burton ; Edgar E. Iglesias ; Richard Henderson ; Paolo Bonzini ; Peter Maydell ; Song Gao ; Xiaojuan Yang ; "Cédric Le Goater" ; Palmer Dabbelt ; Alistair Francis ; Bin Meng ; David Gibson ; Markus Armbruster ; Michael Roth ; Luc Michel ; Damien Hedde ; Alessandro Di Federico 主 题：Re: Any interest in a QEMU emulation BoF at KVM Forum? Alex Bennée writes: qemu-devel keeps bouncing the message so replying with a cut down CC list. > Hi, > > Given our slowly growing range of TCG emulations and the evident > interest in keeping up with modern processor architectures is it worth > having an emulation focused BoF at the up-coming KVM Forum? > > Some potential topics for discussion I could think of might include: > > * Progress towards heterogeneous vCPU emulation > > We've been making slow progress in removing assumptions from the > various front-ends about their global nature and adding accel:TCG > abstractions and support for the translator loop. We can already have > CPUs from the same architecture family in a model. What else do we need > to do so we can have those funky ARM+RiscV+Tricore heterogeneous > models? Is it library or something else? > > * External Device Models > > I know this is a contentious topic given the potential for GPL > end-runs. However there are also good arguments for enabling the > testing of open source designs without having forcing the > implementation of a separate C model to test software. For example if > we hypothetically modelled a Pi Pico would it make sense to model the > PIO in C if we could just compile the Verilog for it into a SystemC > model? Would a plethora of closed device models be the inevitable > consequence of such an approach? Would it matter if we just > concentrated on supporting useful open source solutions? > > * Dynamic Machine Models > > While we try and avoid modelling bespoke virtual HW in QEMU > (virt/goldfish not withstanding ;-) there is obviously a desire in the > EDA space to allow such experimentation. Is this something we can > provide so aspiring HW engineers can experiment with system > architectures without having to form QEMU and learn QOM. There have > been suggestions about consuming device trees or maybe translating to > QMP calls and adding support for wiring devices together. Given the > number of forks that exist is this something that could be better > supported upstream without degenerating into messy hacks? > > * A sense of time > > Currently we have the fairly limited support for -icount in QEMU. At > the same time we have no desire to start expanding frontends with > the details cost models required for a more realistic sense of time to > be presented. One suggestion is to expand the TCG plugin interface to > allow for the plugin to control time allowing as much or little logic > to be pushed there as we like and freeing up frontends from ever having > to consider it. > > Are any of these topics of interest? Are there any other emulation > topics people would like to discuss? -- Alex Bennée
Re: [PATCH for-7.2 v2 10/20] hw/ppc: set machine->fdt in spapr machine
On Mon, Aug 22, 2022 at 07:30:36AM -0300, Daniel Henrique Barboza wrote: > > > On 8/22/22 00:29, Alexey Kardashevskiy wrote: > > > > > > On 22/08/2022 13:05, David Gibson wrote: > > > On Fri, Aug 19, 2022 at 06:42:34AM -0300, Daniel Henrique Barboza wrote: > > > > > > > > > > > > On 8/18/22 23:11, Alexey Kardashevskiy wrote: > > > > > > > > > > > > > > > On 05/08/2022 19:39, Daniel Henrique Barboza wrote: > > > > > > The pSeries machine never bothered with the common machine->fdt > > > > > > attribute. We do all the FDT related work using spapr->fdt_blob. > > > > > > > > > > > > We're going to introduce HMP commands to read and save the FDT, > > > > > > which > > > > > > will rely on setting machine->fdt properly to work across all > > > > > > machine > > > > > > archs/types. > > > > > > > > > > > > > > > Out of curiosity - why new HMP command, is not QOM'ing this ms::fdt > > > > > property enough? > > > > > > > > I tried to do the minimal changes needed for the commands to work. > > > > ms::fdt is > > > > one of the few MachineState fields that hasn't been QOMified by > > > > machine_class_init() yet. All pre-existing code that uses ms::fdt are > > > > using the > > > > pointer directly. To make a QOMified use of it would require extra > > > > patches > > > > in machine.c to QOMify the property first. > > > > > > > > There's also the issue with how each machine is creating the FDT. Most > > > > are using > > > > helpers from device_tree.c, some are creating it from scratch, others > > > > required > > > > a .dtb file, most of them are not doing a fdt_pack() and so on. To > > > > really QOMify > > > > the use of ms::fdt we would need some machine hooks that standardize > > > > all that. > > > > I believe it's worth the trouble, but it would be too much to do > > > > right now. > > > > > > Hmm.. I think this depends on what you mean by "QOM"ify exactly. If > > > you're meaning make the full DT representation QOM objects, that you > > > can look into in detail, then, yes, that's pretty complicated. > > > > > > I suspect what Alexey was suggesting though, was merely to make > > > ms::fdt accessible as a single bytestring property on the machine QOM > > > object. Effectively it's just "dumpdtb" but as a property get. > > > > > > Yes, I meant the bytestream, as DTC can easily decompile it onto a DTS. > > > > > > > I'm not 100% certain if QOM can safely represent arbitrary bytestrings > > > as QOM properties, which would need checking. > > > > I am not sure either but rather than adding another command to HMP, I'd > > explore this option first. > > > I'm not sure what you mean by that. The HMP version of 'dumpdtb' is more > flexible > that the current "-machine dumpdtb", an extra machine option that would cause > the guest to exit after writing the dtb. And 'info fdt' is a new command that > makes it easier to inspect specific nodes/props. > > I don't see how making ms::fdt being retrievable by object_property_get() > internally > (remember that ms::fdt it's not fully QOMified, so there's no introspection > of its > value from the QEMU monitor) would make any of these new HMP commands > obsolete. I believe what we were thinking is if the dtb (as a single bytestring) can be retrieved with a qom-get on a suitable property on the machine, that might make things marginally simpler than adding a new command. I'm not certain if the JSON format of the QMP responses can safely encode an arbitrary bytestring, though (as opoosed to a Unicode string). -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson signature.asc Description: PGP signature
Re: [Qemu-devel] [RFC PATCH] Add qemu .clang-format
On 8/31/2022 6:39 PM, Daniel P. Berrangé wrote: On Wed, Aug 31, 2022 at 05:18:34PM +0800, Wang, Lei wrote: On 8/31/2022 4:49 PM, Daniel P. Berrangé wrote: On Wed, Aug 31, 2022 at 02:23:51PM +0800, Wang, Lei wrote: On 10/2/2015 1:30 AM, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau clang-format is awesome to reflow your code according to qemu coding style in an editor (in the region you modify). (note: clang-tidy should be able to add missing braces around statements, but I haven't tried it, it's quite recent) Signed-off-by: Marc-André Lureau --- .clang-format | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 .clang-format diff --git a/.clang-format b/.clang-format new file mode 100644 index 000..6422547 --- /dev/null +++ b/.clang-format @@ -0,0 +1,6 @@ +BasedOnStyle: LLVM +IndentWidth: 4 +UseTab: Never +BreakBeforeBraces: Linux +AllowShortIfStatementsOnASingleLine: false +IndentCaseLabels: false Hi, any progress on this? I also found a gist on GitHub which can be a reference: https://gist.github.com/elmarco/aa5e0b23567f46fb7f0e73cde586a0c1 clang-format is a great tool and I'd highly recommend its use on any newly started projects, and even retrospectively on existing projects which are small scale. Adding it to large existing projects is problematic though. None of the QEMU code complies with it today and indeed there is quite a bit of style variance across different parts of QEMU. If we add this config file, and someone makes a 1 line change in a file, clang-format will reformat the entire file contents. The only practical way to introduce use of clang-format would be to do a bulk reformat of the entire codebase. That is something that is quite disruptive to both people with patches they're working on but not submitted yet, as well as people wanting to cherry-pick new commits back to old code branches. With regards, Daniel I think the benefits of introducing clang-format mainly for its ability to format a code range, which means for any future contributions, we could encourage a range format before the patch is generated. This can extensively simplify my workflow, especially because I use the Neovim + LSP combination, which supports a built-in function "lua vim.lsp.buf.range_formatting()". IMHO partial format conversions are even worse than full conversions, because they would make code inconsistent within the scope of a file. So you mean when we're adding new code in an old file, the coding style should also be the old one? That sounds a bit unreasonable. I thought we are shifting the coding style in an on-demand way, so we can finally achieve to the new style mildly, if each time we're using the old coding style, that could be impossible. I have no interest in reformatting the existing code and also think using it to reformat an entire file shouldn't be encouraged, but, we can leverage this tool to give future contributions a better experience. It's also important to note that the kernel already has a ".clang-format" file, so I think we can give it a try:) The mere action of introducing a .clang-format file in the root of the repository will cause some contributors' editors to automatically reformat files every time they are saved. IOW even if you don't want intend to do reformatting, that will be a net result. With regards, Daniel I think that depends on developer's configuration, as far as I know, format on save is a feature which can be easily disabled on most of the IDE's, such as VSCode.
[RFC] hw/registerfields: add `FIELDx_1CLEAR()` macro
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the respective field is cleared and returned to `data`.
If ALL bits of the bitfield are not set, then no change and
val is returned.
Signed-off-by: Wilfred Mallawa
---
include/hw/registerfields.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 1330ca77de..5a804f72e3 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -115,6 +115,34 @@
R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
_d; })
+/* Get the max value (uint) discribed by `num_bits` bits */
+#define MAX_N_BITS(num_bits) ((1 << (num_bits)) - 1)
+
+/*
+ * Clear the specified field in reg_val if
+ * all field bits are set, else no changes made. Implements
+ * single/multi-bit `rw1c`
+ */
+#define FIELD8_1CLEAR(reg_val, reg, field)\
+((FIELD_EX8(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP8(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD16_1CLEAR(reg_val, reg, field) \
+((FIELD_EX16(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP16(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD32_1CLEAR(reg_val, reg, field) \
+((FIELD_EX32(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP32(reg_val, reg, field, 0x00) : reg_val)
+
+#define FIELD64_1CLEAR(reg_val, reg, field) \
+((FIELD_EX64(reg_val, reg, field) == \
+ MAX_N_BITS(R_ ## reg ## _ ## field ## _LENGTH)) ? \
+ FIELD_DP64(reg_val, reg, field, 0x00) : reg_val)
+
#define FIELD_SDP8(storage, reg, field, val) ({ \
struct { \
signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
--
2.37.2
Re: [PULL 00/23] First testing patches for QEMU 7.2
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL 0/6] First s390x updates for QEMU 7.2
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
[PATCH v3 1/1] monitor/hmp: print trace as option in help for log command
The below is printed when printing help information in qemu-system-x86_64
command line, and when CONFIG_TRACE_LOG is enabled:
$ qemu-system-x86_64 -d help
... ...
trace:PATTERN enable trace events
Use "-d trace:help" to get a list of trace events.
However, the options of "trace:PATTERN" are only printed by
"qemu-system-x86_64 -d help", but missing in hmp "help log" command.
Fixes: c84ea00dc2 ("log: add "-d trace:PATTERN"")
Cc: Joe Jin
Signed-off-by: Dongli Zhang
---
Changed since v1:
- change format for "none" as well.
Changed since v2:
- use "log trace:help" in help message.
- add more clarification in commit message.
- add 'Fixes' tag.
---
monitor/hmp.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/monitor/hmp.c b/monitor/hmp.c
index 15ca04735c..a3375d0341 100644
--- a/monitor/hmp.c
+++ b/monitor/hmp.c
@@ -285,10 +285,15 @@ void help_cmd(Monitor *mon, const char *name)
if (!strcmp(name, "log")) {
const QEMULogItem *item;
monitor_printf(mon, "Log items (comma separated):\n");
-monitor_printf(mon, "%-10s %s\n", "none", "remove all logs");
+monitor_printf(mon, "%-15s %s\n", "none", "remove all logs");
for (item = qemu_log_items; item->mask != 0; item++) {
-monitor_printf(mon, "%-10s %s\n", item->name, item->help);
+monitor_printf(mon, "%-15s %s\n", item->name, item->help);
}
+#ifdef CONFIG_TRACE_LOG
+monitor_printf(mon, "trace:PATTERN enable trace events\n");
+monitor_printf(mon, "\nUse \"log trace:help\" to get a list of "
+ "trace events.\n\n");
+#endif
return;
}
--
2.17.1
[PULL v2 00/60] ppc queue
The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36: Open 7.2 development tree (2022-08-30 09:40:41 -0700) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831 for you to fetch changes up to 95e22932870f523765910b01c2dc5b845b8bec85: ppc4xx: Fix code style problems reported by checkpatch (2022-08-31 17:05:15 -0300) ppc patch queue for 2022-08-31: In the first 7.2 queue we have changes in the powernv pnv-phb handling, the start of the QOMification of the ppc405 model, the removal of the taihu machine, a new SLOF image and others. Alexey Kardashevskiy (1): pseries: Update SLOF firmware image BALATON Zoltan (9): ppc4xx: Move PLB model to ppc4xx_devs.c ppc4xx: Rename ppc405-plb to ppc4xx-plb ppc4xx: Move EBC model to ppc4xx_devs.c ppc4xx: Rename ppc405-ebc to ppc4xx-ebc hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device ppc405: Move machine specific code to ppc405_boards.c hw/ppc/sam460ex: Remove PPC405 dependency from sam460ex hw/ppc/Kconfig: Move imply before select ppc4xx: Fix code style problems reported by checkpatch Cédric Le Goater (22): ppc/ppc405: Remove taihu machine ppc/ppc405: Introduce a PPC405 generic machine ppc/ppc405: Move devices under the ref405ep machine ppc/ppc405: Move SRAM under the ref405ep machine ppc/ppc405: Introduce a PPC405 SoC ppc/ppc405: Start QOMification of the SoC ppc/ppc405: QOM'ify CPU ppc/ppc4xx: Introduce a DCR device model ppc/ppc405: QOM'ify CPC ppc/ppc405: QOM'ify GPT ppc/ppc405: QOM'ify OCM ppc/ppc405: QOM'ify GPIO ppc/ppc405: QOM'ify DMA ppc/ppc405: QOM'ify EBC ppc/ppc405: QOM'ify OPBA ppc/ppc405: QOM'ify POB ppc/ppc405: QOM'ify PLB ppc/ppc405: QOM'ify MAL ppc/ppc405: Use an embedded PPCUIC model in SoC state ppc/ppc405: Use an explicit I2C object ppc/ppc405: QOM'ify FPGA ppc/ppc4xx: Fix sdram trace events Daniel Henrique Barboza (24): ppc/pnv: add PHB3 bus init helper ppc/pnv: add PnvPHB base/proxy device ppc/pnv: turn PnvPHB3 into a PnvPHB backend ppc/pnv: add PHB4 bus init helper ppc/pnv: turn PnvPHB4 into a PnvPHB backend ppc/pnv: add pnv-phb-root-port device ppc/pnv: remove pnv-phb3-root-port ppc/pnv: remove pnv-phb4-root-port ppc/pnv: remove root port name from pnv_phb_attach_root_port() ppc/pnv: remove pecc->rp_model ppc/pnv: remove PnvPHB4.version ppc/pnv: move attach_root_port helper to pnv-phb.c ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties ppc/pnv: set root port chassis and slot using Bus properties ppc/pnv: add helpers for pnv-phb user devices ppc/pnv: turn chip8->phbs[] into a PnvPHB* array ppc/pnv: enable user created pnv-phb for powernv8 ppc/pnv: add PHB4 helpers for user created pnv-phb ppc/pnv: enable user created pnv-phb for powernv9 ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs ppc/pnv: user creatable pnv-phb for powernv10 ppc/pnv: consolidate pnv_parent_*_fixup() helpers ppc/pnv: fix QOM parenting of user creatable root ports Lucas Mateus Castro (alqotel) (2): fpu: Add rebias bool, value and operation target/ppc: Bugfix FP when OE/UE are set Nicholas Piggin (2): target/ppc: Fix host PVR matching for KVM ppc/pnv: Add initial P9/10 SBE model MAINTAINERS |2 +- docs/about/deprecated.rst |9 - docs/about/removed-features.rst |6 + docs/system/ppc/embedded.rst|1 - docs/system/ppc/pseries.rst |2 +- fpu/softfloat-parts.c.inc | 21 +- fpu/softfloat.c |2 + hw/intc/ppc-uic.c | 26 +- hw/pci-host/meson.build |3 +- hw/pci-host/pnv_phb.c | 337 hw/pci-host/pnv_phb.h | 55 ++ hw/pci-host/pnv_phb3.c | 152 +++-- hw/pci-host/pnv_phb4.c | 191 +++ hw/pci-host/pnv_phb4_pec.c | 11 +- hw/ppc/Kconfig |3 +- hw/ppc/meson.build |1 + hw/ppc/pnv.c| 188 +-- hw/ppc/pnv_sbe.c| 414 ++ hw/ppc/pnv_xscom.c |3 + hw/ppc/ppc405.h | 200 +-- hw/ppc/ppc405_boards.c | 552 +-- hw/ppc/ppc405_uc.c | 1156 ++- hw/ppc/ppc440_bamboo.c | 34 +- hw/ppc/ppc440_uc.c |3 +- hw/ppc/ppc4xx_devs.c| 554 ++- hw/ppc/ppc4xx_pci.c | 31 +- hw/ppc/sam460ex.c | 38 +
Re: [PULL 00/60] ppc queue
On 8/31/22 16:37, BALATON Zoltan wrote: On Wed, 31 Aug 2022, Daniel Henrique Barboza wrote: The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36: Open 7.2 development tree (2022-08-30 09:40:41 -0700) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831 for you to fetch changes up to 2d9c27ac5c035823315f68c227ca1cc6313e9842: ppc4xx: Fix code style problems reported by checkpatch (2022-08-31 14:08:06 -0300) ppc patch queue for 2022-08-31: In the first 7.2 queue we have changes in the powernv pnv-phb handling, the start of the QOMification of the ppc405 model, the removal of the taihu machine, a new SLOF image and others. Alexey Kardashevskiy (1): pseries: Update SLOF firmware image BALATON Zoltan (9): ppc4xx: Move PLB model to ppc4xx_devs.c ppc4xx: Rename ppc405-plb to ppc4xx-plb ppc4xx: Move EBC model to ppc4xx_devs.c ppc4xx: Rename ppc405-ebc to ppc4xx-ebc hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device ppc405: Move machine specific code to ppc405_boards.c hw/ppc/sam3460ex: Remove PPC405 dependency from sam460ex Seems like we have a typo in this patch title, sam3460ex should be sam460ex That completely went under the radar during 2-3 reviewed versions. Impressive :) Richard/Peter, I've fixed the commit name and recreated the tag. I'll send just the cover-letter as a v2 since there were no code changes made. Thanks, Daniel Regards, BALATON Zoltan hw/ppc/Kconfig: Move imply before select ppc4xx: Fix code style problems reported by checkpatch Cédric Le Goater (22): ppc/ppc405: Remove taihu machine ppc/ppc405: Introduce a PPC405 generic machine ppc/ppc405: Move devices under the ref405ep machine ppc/ppc405: Move SRAM under the ref405ep machine ppc/ppc405: Introduce a PPC405 SoC ppc/ppc405: Start QOMification of the SoC ppc/ppc405: QOM'ify CPU ppc/ppc4xx: Introduce a DCR device model ppc/ppc405: QOM'ify CPC ppc/ppc405: QOM'ify GPT ppc/ppc405: QOM'ify OCM ppc/ppc405: QOM'ify GPIO ppc/ppc405: QOM'ify DMA ppc/ppc405: QOM'ify EBC ppc/ppc405: QOM'ify OPBA ppc/ppc405: QOM'ify POB ppc/ppc405: QOM'ify PLB ppc/ppc405: QOM'ify MAL ppc/ppc405: Use an embedded PPCUIC model in SoC state ppc/ppc405: Use an explicit I2C object ppc/ppc405: QOM'ify FPGA ppc/ppc4xx: Fix sdram trace events Daniel Henrique Barboza (24): ppc/pnv: add PHB3 bus init helper ppc/pnv: add PnvPHB base/proxy device ppc/pnv: turn PnvPHB3 into a PnvPHB backend ppc/pnv: add PHB4 bus init helper ppc/pnv: turn PnvPHB4 into a PnvPHB backend ppc/pnv: add pnv-phb-root-port device ppc/pnv: remove pnv-phb3-root-port ppc/pnv: remove pnv-phb4-root-port ppc/pnv: remove root port name from pnv_phb_attach_root_port() ppc/pnv: remove pecc->rp_model ppc/pnv: remove PnvPHB4.version ppc/pnv: move attach_root_port helper to pnv-phb.c ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties ppc/pnv: set root port chassis and slot using Bus properties ppc/pnv: add helpers for pnv-phb user devices ppc/pnv: turn chip8->phbs[] into a PnvPHB* array ppc/pnv: enable user created pnv-phb for powernv8 ppc/pnv: add PHB4 helpers for user created pnv-phb ppc/pnv: enable user created pnv-phb for powernv9 ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs ppc/pnv: user creatable pnv-phb for powernv10 ppc/pnv: consolidate pnv_parent_*_fixup() helpers ppc/pnv: fix QOM parenting of user creatable root ports Lucas Mateus Castro (alqotel) (2): fpu: Add rebias bool, value and operation target/ppc: Bugfix FP when OE/UE are set Nicholas Piggin (2): target/ppc: Fix host PVR matching for KVM ppc/pnv: Add initial P9/10 SBE model MAINTAINERS | 2 +- docs/about/deprecated.rst | 9 - docs/about/removed-features.rst | 6 + docs/system/ppc/embedded.rst | 1 - docs/system/ppc/pseries.rst | 2 +- fpu/softfloat-parts.c.inc | 21 +- fpu/softfloat.c | 2 + hw/intc/ppc-uic.c | 26 +- hw/pci-host/meson.build | 3 +- hw/pci-host/pnv_phb.c | 337 hw/pci-host/pnv_phb.h | 55 ++ hw/pci-host/pnv_phb3.c | 152 +++-- hw/pci-host/pnv_phb4.c | 191 +++ hw/pci-host/pnv_phb4_pec.c | 11 +- hw/ppc/Kconfig | 3 +- hw/ppc/meson.build | 1 + hw/ppc/pnv.c | 188 +-- hw/ppc/pnv_sbe.c | 414 ++ hw/ppc/pnv_xscom.c | 3 + hw/ppc/ppc405.h | 200 +
Re: [PATCH v4 12/12] hw/isa/vt82c686: Create rtc-time alias in boards instead
Am 31. August 2022 16:30:10 UTC schrieb BALATON Zoltan :
>On Wed, 31 Aug 2022, Bernhard Beschow wrote:
>> According to good QOM practice, an object should only deal with objects
>> of its own sub tree. Having devices create an alias on the machine
>> object doesn't respect this good practice. To resolve this, create the
>> alias in the machine's code.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> hw/isa/vt82c686.c | 2 --
>> hw/mips/fuloong2e.c | 4
>> hw/ppc/pegasos2.c | 4
>> 3 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
>> index 48cd4d0036..3f9bd0c04d 100644
>> --- a/hw/isa/vt82c686.c
>> +++ b/hw/isa/vt82c686.c
>> @@ -632,8 +632,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
>> if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
>> return;
>> }
>> -object_property_add_alias(qdev_get_machine(), "rtc-time",
>> OBJECT(>rtc),
>> - "date");
>> isa_connect_gpio_out(ISA_DEVICE(>rtc), 0, s->rtc.isairq);
>>
>> for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
>> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
>> index 2d8723ab74..0f4cfe1188 100644
>> --- a/hw/mips/fuloong2e.c
>> +++ b/hw/mips/fuloong2e.c
>> @@ -203,6 +203,10 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus,
>> int slot, qemu_irq intc,
>>
>> via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), true,
>> TYPE_VT82C686B_ISA);
>> +object_property_add_alias(qdev_get_machine(), "rtc-time",
>> + object_resolve_path_component(OBJECT(via),
>> +"rtc"),
>> + "date");
>> qdev_connect_gpio_out(DEVICE(via), 0, intc);
>>
>> dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "ide"));
>> diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
>> index 09fdb7557f..f50e1d8b3f 100644
>> --- a/hw/ppc/pegasos2.c
>> +++ b/hw/ppc/pegasos2.c
>> @@ -161,6 +161,10 @@ static void pegasos2_init(MachineState *machine)
>> /* VIA VT8231 South Bridge (multifunction PCI device) */
>> via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
>> TYPE_VT8231_ISA);
>> +object_property_add_alias(qdev_get_machine(), "rtc-time",
>
>I did not check it in previous version but Phillppe noted this
>qdev_get_machine() should be machine (the parameter to pegasos2_init) instead
>and I agree with that.
Sounds good! I'm all about removing access to globals.
>Also if you get rid of the now very much cut down vt82c686b_southbridge_init
>func in fuloong2e and just inline what's left of it at the only call site then
>the same machine pointer could be used there too and would be simpler then
>going through the function now that it's moved to via-isa mostly.
Sure, I'll add another patch on top.
>Sorry that this needs another respin but that's the last, I won't look at it
>again :-)
No worries. It's very convenient with git-publish.
>You can also add to the whole series:
>
>Reviewed-by: BALATON Zoltan
Will do. Thanks for your quick replies!
Regards,
Bernhard
>Regards,
>BALATON Zoltan
>
>> + object_resolve_path_component(OBJECT(via),
>> +"rtc"),
>> + "date");
>> qdev_connect_gpio_out(DEVICE(via), 0,
>> qdev_get_gpio_in_named(pm->mv, "gpp", 31));
>>
>>
Re: [PULL 00/60] ppc queue
On Wed, 31 Aug 2022, Daniel Henrique Barboza wrote: The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36: Open 7.2 development tree (2022-08-30 09:40:41 -0700) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831 for you to fetch changes up to 2d9c27ac5c035823315f68c227ca1cc6313e9842: ppc4xx: Fix code style problems reported by checkpatch (2022-08-31 14:08:06 -0300) ppc patch queue for 2022-08-31: In the first 7.2 queue we have changes in the powernv pnv-phb handling, the start of the QOMification of the ppc405 model, the removal of the taihu machine, a new SLOF image and others. Alexey Kardashevskiy (1): pseries: Update SLOF firmware image BALATON Zoltan (9): ppc4xx: Move PLB model to ppc4xx_devs.c ppc4xx: Rename ppc405-plb to ppc4xx-plb ppc4xx: Move EBC model to ppc4xx_devs.c ppc4xx: Rename ppc405-ebc to ppc4xx-ebc hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device ppc405: Move machine specific code to ppc405_boards.c hw/ppc/sam3460ex: Remove PPC405 dependency from sam460ex Seems like we have a typo in this patch title, sam3460ex should be sam460ex Regards, BALATON Zoltan hw/ppc/Kconfig: Move imply before select ppc4xx: Fix code style problems reported by checkpatch Cédric Le Goater (22): ppc/ppc405: Remove taihu machine ppc/ppc405: Introduce a PPC405 generic machine ppc/ppc405: Move devices under the ref405ep machine ppc/ppc405: Move SRAM under the ref405ep machine ppc/ppc405: Introduce a PPC405 SoC ppc/ppc405: Start QOMification of the SoC ppc/ppc405: QOM'ify CPU ppc/ppc4xx: Introduce a DCR device model ppc/ppc405: QOM'ify CPC ppc/ppc405: QOM'ify GPT ppc/ppc405: QOM'ify OCM ppc/ppc405: QOM'ify GPIO ppc/ppc405: QOM'ify DMA ppc/ppc405: QOM'ify EBC ppc/ppc405: QOM'ify OPBA ppc/ppc405: QOM'ify POB ppc/ppc405: QOM'ify PLB ppc/ppc405: QOM'ify MAL ppc/ppc405: Use an embedded PPCUIC model in SoC state ppc/ppc405: Use an explicit I2C object ppc/ppc405: QOM'ify FPGA ppc/ppc4xx: Fix sdram trace events Daniel Henrique Barboza (24): ppc/pnv: add PHB3 bus init helper ppc/pnv: add PnvPHB base/proxy device ppc/pnv: turn PnvPHB3 into a PnvPHB backend ppc/pnv: add PHB4 bus init helper ppc/pnv: turn PnvPHB4 into a PnvPHB backend ppc/pnv: add pnv-phb-root-port device ppc/pnv: remove pnv-phb3-root-port ppc/pnv: remove pnv-phb4-root-port ppc/pnv: remove root port name from pnv_phb_attach_root_port() ppc/pnv: remove pecc->rp_model ppc/pnv: remove PnvPHB4.version ppc/pnv: move attach_root_port helper to pnv-phb.c ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties ppc/pnv: set root port chassis and slot using Bus properties ppc/pnv: add helpers for pnv-phb user devices ppc/pnv: turn chip8->phbs[] into a PnvPHB* array ppc/pnv: enable user created pnv-phb for powernv8 ppc/pnv: add PHB4 helpers for user created pnv-phb ppc/pnv: enable user created pnv-phb for powernv9 ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs ppc/pnv: user creatable pnv-phb for powernv10 ppc/pnv: consolidate pnv_parent_*_fixup() helpers ppc/pnv: fix QOM parenting of user creatable root ports Lucas Mateus Castro (alqotel) (2): fpu: Add rebias bool, value and operation target/ppc: Bugfix FP when OE/UE are set Nicholas Piggin (2): target/ppc: Fix host PVR matching for KVM ppc/pnv: Add initial P9/10 SBE model MAINTAINERS |2 +- docs/about/deprecated.rst |9 - docs/about/removed-features.rst |6 + docs/system/ppc/embedded.rst|1 - docs/system/ppc/pseries.rst |2 +- fpu/softfloat-parts.c.inc | 21 +- fpu/softfloat.c |2 + hw/intc/ppc-uic.c | 26 +- hw/pci-host/meson.build |3 +- hw/pci-host/pnv_phb.c | 337 hw/pci-host/pnv_phb.h | 55 ++ hw/pci-host/pnv_phb3.c | 152 +++-- hw/pci-host/pnv_phb4.c | 191 +++ hw/pci-host/pnv_phb4_pec.c | 11 +- hw/ppc/Kconfig |3 +- hw/ppc/meson.build |1 + hw/ppc/pnv.c| 188 +-- hw/ppc/pnv_sbe.c| 414 ++ hw/ppc/pnv_xscom.c |3 + hw/ppc/ppc405.h | 200 +-- hw/ppc/ppc405_boards.c | 552 +-- hw/ppc/ppc405_uc.c | 1156 ++- hw/ppc/ppc440_bamboo.c | 34 +- hw/ppc/ppc440_uc.c |3 +- hw/ppc/ppc4xx_devs.c| 554 ++- hw/ppc/ppc
[PULL 59/60] ppc/ppc4xx: Fix sdram trace events
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
Message-Id:
<0a3e454eb7fd5f2b807a9c752c28693f27829f1d.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 37e3b87c2e..27ebbb2ffc 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -142,7 +142,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
sdram->bcr[i] = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x0001)) {
-trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr));
+trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(>containers[i], NULL, "sdram-containers",
sdram_size(bcr));
memory_region_add_subregion(>containers[i], 0,
--
2.37.2
TCG IR extraction
Hello, Thanks so much for reading this and I appreciate any and all time you put into this. I'm a dev working on a project that's using QEMU as its basis. I'm interested in extracting the IR representation of translation blocks, preferably at the instruction level, to do some analysis on it. In various documentation around the web I see lots of references to textual examples of the IR so I assumed it would be possible to extract it in byte format and convert to textual myself. I've done a lot of digging in the source and found the code_gen_buffer and determined that's where the IR generation is being written to, but I'm having trouble cross referencing DisasContext, etc, with that global to actually identify individual lines of code. I'm also assuming there's some kind of framing going on, so I don't think that I can even expect it to be a simple buffer of bytes. So my - is this reasonable to even attempt, and if so, how would you go about doing it? Regards, -T
Re: [PATCH v2 1/1] monitor/hmp: print trace as option in help for log command
Hi Markus,
On 8/30/22 4:04 AM, Markus Armbruster wrote:
> Dongli Zhang writes:
>
>> The below is printed when printing help information in qemu-system-x86_64
>> command line, and when CONFIG_TRACE_LOG is enabled:
>>
>> $ qemu-system-x86_64 -d help
>> ... ...
>> trace:PATTERN enable trace events
>>
>> Use "-d trace:help" to get a list of trace events.
>>
>> However, they are not printed in hmp "help log" command.
>
> This leaves me guessing what exactly the patch tries to do.
I will clarify in the commit message.
>
>> Cc: Joe Jin
>> Signed-off-by: Dongli Zhang
>> ---
>> Changed since v1:
>> - change format for "none" as well.
>>
>> monitor/hmp.c | 9 +++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/monitor/hmp.c b/monitor/hmp.c
>> index 15ca047..467fc84 100644
>> --- a/monitor/hmp.c
>> +++ b/monitor/hmp.c
>> @@ -285,10 +285,15 @@ void help_cmd(Monitor *mon, const char *name)
>> if (!strcmp(name, "log")) {
>> const QEMULogItem *item;
>> monitor_printf(mon, "Log items (comma separated):\n");
>> -monitor_printf(mon, "%-10s %s\n", "none", "remove all logs");
>> +monitor_printf(mon, "%-15s %s\n", "none", "remove all logs");
>> for (item = qemu_log_items; item->mask != 0; item++) {
>> -monitor_printf(mon, "%-10s %s\n", item->name, item->help);
>> +monitor_printf(mon, "%-15s %s\n", item->name, item->help);
>> }
>> +#ifdef CONFIG_TRACE_LOG
>> +monitor_printf(mon, "trace:PATTERN enable trace events\n");
>> +monitor_printf(mon, "\nUse \"info trace-events\" to get a list
>> of "
>> +"trace events.\n\n");
>
> Aha: it fixes help to show "log trace:PATTERN". Was that forgotten in
> Paolo's commit c84ea00dc2 'log: add "-d trace:PATTERN"'?
I will add the Fixes tag.
>
> "info trace-events", hmmm... it shows trace events and their state.
> "log trace:help" also lists them, less their state, and in opposite
> order. Why do we need both?
I will print "log trace:help" in the help output.
>
> What about showing them in alphabetical order?
The order is following how they are defined in the qemu_log_items[] array. To
re-order them in the array may introduce more conflicts when backporting a
util/log patch to QEMU old version.
Please let me know if you prefer to re-order. Otherwise, I prefer to avoid that.
Thank you very much for the suggestions!
Dongli Zhang
>
>> +#endif
>> return;
>> }
>
[PULL 58/60] hw/ppc/Kconfig: Move imply before select
From: BALATON Zoltan In pegasos2 section move imply before select to match other sections. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater Message-Id: <4d46dde64c2e5df6db3f92426fb3ae885939c2b0.1660746880.git.bala...@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 205f9f98d7..3a4418a69e 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -71,6 +71,7 @@ config SAM460EX config PEGASOS2 bool +imply ATI_VGA select MV64361 select VT82C686 select IDE_VIA @@ -78,7 +79,6 @@ config PEGASOS2 select VOF # This should come with VT82C686 select ACPI_X86 -imply ATI_VGA config PREP bool -- 2.37.2
[PULL 54/60] ppc/ppc405: Use an explicit I2C object
From: Cédric Le Goater
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Symplify sysbus device casts for readibility]
Signed-off-by: BALATON Zoltan
Message-Id:
<68eb8b5ac408ca8cc981ebf53a3e154c0d34c7f6.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 2 ++
hw/ppc/ppc405_uc.c | 10 --
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 67f4c14f50..efa29fdfb1 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -28,6 +28,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/intc/ppc-uic.h"
+#include "hw/i2c/ppc4xx_i2c.h"
#define PPC405EP_SDRAM_BASE 0x
#define PPC405EP_NVRAM_BASE 0xF000
@@ -215,6 +216,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+PPC4xxI2CState i2c;
Ppc4xxEbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index dc17d5bdb5..189f49a138 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1096,6 +1096,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", >dma, TYPE_PPC405_DMA);
+object_initialize_child(obj, "i2c", >i2c, TYPE_PPC4xx_I2C);
+
object_initialize_child(obj, "ebc", >ebc, TYPE_PPC4xx_EBC);
object_initialize_child(obj, "opba", >opba, TYPE_PPC405_OPBA);
@@ -1188,8 +1190,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
/* I2C controller */
-sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(DEVICE(>uic), 2));
+sbd = SYS_BUS_DEVICE(>i2c);
+if (!sysbus_realize(sbd, errp)) {
+return;
+}
+sysbus_mmio_map(sbd, 0, 0xef600500);
+sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(>uic), 2));
/* GPIO */
sbd = SYS_BUS_DEVICE(>gpio);
--
2.37.2
[PULL 56/60] ppc405: Move machine specific code to ppc405_boards.c
From: BALATON Zoltan
These are only used by the board code so move out from the shared SoC
model and put it in the boards file.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
<2b23bcaaf191f96b217cbd06a6038694024862c3.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 38 -
hw/ppc/ppc405_boards.c | 375 +++--
hw/ppc/ppc405_uc.c | 92 --
3 files changed, 251 insertions(+), 254 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index efa29fdfb1..1e558c7831 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -30,41 +30,6 @@
#include "hw/intc/ppc-uic.h"
#include "hw/i2c/ppc4xx_i2c.h"
-#define PPC405EP_SDRAM_BASE 0x
-#define PPC405EP_NVRAM_BASE 0xF000
-#define PPC405EP_FPGA_BASE 0xF030
-#define PPC405EP_SRAM_BASE 0xFFF0
-#define PPC405EP_SRAM_SIZE (512 * KiB)
-#define PPC405EP_FLASH_BASE 0xFFF8
-
-/* Bootinfo as set-up by u-boot */
-typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
-struct ppc4xx_bd_info_t {
-uint32_t bi_memstart;
-uint32_t bi_memsize;
-uint32_t bi_flashstart;
-uint32_t bi_flashsize;
-uint32_t bi_flashoffset; /* 0x10 */
-uint32_t bi_sramstart;
-uint32_t bi_sramsize;
-uint32_t bi_bootflags;
-uint32_t bi_ipaddr; /* 0x20 */
-uint8_t bi_enetaddr[6];
-uint16_t bi_ethspeed;
-uint32_t bi_intfreq;
-uint32_t bi_busfreq; /* 0x30 */
-uint32_t bi_baudrate;
-uint8_t bi_s_version[4];
-uint8_t bi_r_version[32];
-uint32_t bi_procfreq;
-uint32_t bi_plb_busfreq;
-uint32_t bi_pci_busfreq;
-uint8_t bi_pci_enetaddr[6];
-uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
-uint32_t bi_opbfreq;
-uint32_t bi_iic_fast[2];
-};
-
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -224,7 +189,4 @@ struct Ppc405SoCState {
Ppc4xxMalState mal;
};
-/* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 7af0d7feef..083f12b23e 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -48,6 +48,10 @@
#define KERNEL_LOAD_ADDR 0x0100
#define INITRD_LOAD_ADDR 0x0180
+#define PPC405EP_SDRAM_BASE 0x
+#define PPC405EP_SRAM_BASE 0xFFF0
+#define PPC405EP_SRAM_SIZE (512 * KiB)
+
#define USE_FLASH_BIOS
#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
@@ -61,112 +65,7 @@ struct Ppc405MachineState {
Ppc405SoCState soc;
};
-/*/
-/* PPC405EP reference board (IBM) */
-/* Standalone board with:
- * - PowerPC 405EP CPU
- * - SDRAM (0x)
- * - Flash (0xFFF8)
- * - SRAM (0xFFF0)
- * - NVRAM (0xF000)
- * - FPGA (0xF030)
- */
-
-#define TYPE_REF405EP_FPGA "ref405ep-fpga"
-OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
-struct Ref405epFpgaState {
-SysBusDevice parent_obj;
-
-MemoryRegion iomem;
-
-uint8_t reg0;
-uint8_t reg1;
-};
-
-static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
-{
-Ref405epFpgaState *fpga = opaque;
-uint32_t ret;
-
-switch (addr) {
-case 0x0:
-ret = fpga->reg0;
-break;
-case 0x1:
-ret = fpga->reg1;
-break;
-default:
-ret = 0;
-break;
-}
-
-return ret;
-}
-
-static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
-Ref405epFpgaState *fpga = opaque;
-
-switch (addr) {
-case 0x0:
-/* Read only */
-break;
-case 0x1:
-fpga->reg1 = value;
-break;
-default:
-break;
-}
-}
-
-static const MemoryRegionOps ref405ep_fpga_ops = {
-.read = ref405ep_fpga_readb,
-.write = ref405ep_fpga_writeb,
-.impl.min_access_size = 1,
-.impl.max_access_size = 1,
-.valid.min_access_size = 1,
-.valid.max_access_size = 4,
-.endianness = DEVICE_BIG_ENDIAN,
-};
-
-static void ref405ep_fpga_reset(DeviceState *dev)
-{
-Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
-
-fpga->reg0 = 0x00;
-fpga->reg1 = 0x0F;
-}
-
-static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
-{
-Ref405epFpgaState *s = REF405EP_FPGA(dev);
-
-memory_region_init_io(>iomem, OBJECT(s), _fpga_ops, s,
- "fpga", 0x0100);
-sysbus_init_mmio(SYS_BUS_DEVICE(s), >iomem);
-}
-
-static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(oc);
-
-dc->realize = ref405ep_fpga_realize;
-dc->reset = ref405ep_fpga_reset;
-/* Reason: only works as part of a ppc405 board */
-dc->user_creatable = false;
-}
-
-static const TypeInfo ref405ep_fpga_type = {
-
[PULL 49/60] ppc4xx: Rename ppc405-plb to ppc4xx-plb
From: BALATON Zoltan
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<5b13ebfd12a71a28035bed5a915cbeee81cf21d1.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc4xx_devs.c| 12 ++--
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 6 +++---
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d85c595f9d..8521be317d 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -232,7 +232,7 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
-Ppc405PlbState plb;
+Ppc4xxPlbState plb;
Ppc4xxMalState mal;
};
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3382ed3252..b7f6d1c9c1 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1286,7 +1286,7 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", >pob, TYPE_PPC405_POB);
-object_initialize_child(obj, "plb", >plb, TYPE_PPC405_PLB);
+object_initialize_child(obj, "plb", >plb, TYPE_PPC4xx_PLB);
object_initialize_child(obj, "mal", >mal, TYPE_PPC4xx_MAL);
}
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 843d759b1b..3baa2fa2b3 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -671,7 +671,7 @@ enum {
static uint32_t dcr_read_plb(void *opaque, int dcrn)
{
-Ppc405PlbState *plb = opaque;
+Ppc4xxPlbState *plb = opaque;
uint32_t ret;
switch (dcrn) {
@@ -695,7 +695,7 @@ static uint32_t dcr_read_plb(void *opaque, int dcrn)
static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
{
-Ppc405PlbState *plb = opaque;
+Ppc4xxPlbState *plb = opaque;
switch (dcrn) {
case PLB0_ACR:
@@ -717,7 +717,7 @@ static void dcr_write_plb(void *opaque, int dcrn, uint32_t
val)
static void ppc405_plb_reset(DeviceState *dev)
{
-Ppc405PlbState *plb = PPC405_PLB(dev);
+Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
plb->acr = 0x;
plb->bear = 0x;
@@ -726,7 +726,7 @@ static void ppc405_plb_reset(DeviceState *dev)
static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
-Ppc405PlbState *plb = PPC405_PLB(dev);
+Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, _read_plb, _write_plb);
@@ -784,9 +784,9 @@ static const TypeInfo ppc4xx_types[] = {
.instance_finalize = ppc4xx_mal_finalize,
.class_init = ppc4xx_mal_class_init,
}, {
-.name = TYPE_PPC405_PLB,
+.name = TYPE_PPC4xx_PLB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
-.instance_size = sizeof(Ppc405PlbState),
+.instance_size = sizeof(Ppc4xxPlbState),
.class_init = ppc405_plb_class_init,
}, {
.name = TYPE_PPC4xx_DCR_DEVICE,
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index c16303462d..6b1c843eeb 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -308,7 +308,7 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
-dev = qdev_new(TYPE_PPC405_PLB);
+dev = qdev_new(TYPE_PPC4xx_PLB);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, _fatal);
object_unref(OBJECT(dev));
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index e696e159f3..b19e59271b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -84,9 +84,9 @@ struct Ppc4xxMalState {
};
/* Peripheral local bus arbitrer */
-#define TYPE_PPC405_PLB "ppc405-plb"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
-struct Ppc405PlbState {
+#define TYPE_PPC4xx_PLB "ppc4xx-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB);
+struct Ppc4xxPlbState {
Ppc4xxDcrDeviceState parent_obj;
uint32_t acr;
--
2.37.2
[PULL 60/60] ppc4xx: Fix code style problems reported by checkpatch
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
<62798fbe9c200da3e0c870601ed9162b1c3a50a5.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_uc.c | 5 +++--
hw/ppc/ppc440_bamboo.c | 27 ++--
hw/ppc/ppc440_uc.c | 3 ++-
hw/ppc/ppc4xx_devs.c | 48 +++---
hw/ppc/ppc4xx_pci.c| 31 +--
5 files changed, 67 insertions(+), 47 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 74d27250a7..2ca42fdef6 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -540,10 +540,11 @@ static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
mask = 0x8000;
for (i = 0; i < 5; i++) {
-if (gpt->is & gpt->im & mask)
+if (gpt->is & gpt->im & mask) {
qemu_irq_raise(gpt->irqs[i]);
-else
+} else {
qemu_irq_lower(gpt->irqs[i]);
+}
mask = mask >> 1;
}
}
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index b14a9ef776..ea945a1c99 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -84,27 +84,30 @@ static int bamboo_load_device_tree(hwaddr addr,
ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
sizeof(mem_reg_property));
-if (ret < 0)
+if (ret < 0) {
fprintf(stderr, "couldn't set /memory/reg\n");
-
+}
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
initrd_base);
-if (ret < 0)
+if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
-
+}
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
-if (ret < 0)
+if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
-
+}
ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
kernel_cmdline);
-if (ret < 0)
+if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/bootargs\n");
+}
-/* Copy data from the host device tree into the guest. Since the guest can
+/*
+ * Copy data from the host device tree into the guest. Since the guest can
* directly access the timebase without host involvement, we must expose
- * the correct frequencies. */
+ * the correct frequencies.
+ */
if (kvm_enabled()) {
tb_freq = kvmppc_get_tbfreq();
clock_freq = kvmppc_get_clockfreq();
@@ -246,8 +249,10 @@ static void bamboo_init(MachineState *machine)
if (pcibus) {
/* Register network interfaces. */
for (i = 0; i < nb_nics; i++) {
-/* There are no PCI NICs on the Bamboo board, but there are
- * PCI slots, so we can pick whatever default model we want. */
+/*
+ * There are no PCI NICs on the Bamboo board, but there are
+ * PCI slots, so we can pick whatever default model we want.
+ */
pci_nic_init_nofail(_table[i], pcibus, "e1000", NULL);
}
}
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 11fdb88c22..53e981ddf4 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -1028,7 +1028,8 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
/*/
/* PCI Express controller */
-/* FIXME: This is not complete and does not work, only implemented partially
+/*
+ * FIXME: This is not complete and does not work, only implemented partially
* to allow firmware and guests to find an empty bus. Cards should use PCI.
*/
#include "hw/pci/pcie_host.h"
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 27ebbb2ffc..ce38ae65e6 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -65,12 +65,12 @@ enum {
SDRAM0_CFGDATA = 0x011,
};
-/* XXX: TOFIX: some patches have made this code become inconsistent:
+/*
+ * XXX: TOFIX: some patches have made this code become inconsistent:
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (hwaddr ram_base,
- hwaddr ram_size)
+static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -113,16 +113,17 @@ static inline hwaddr sdram_base(uint32_t bcr)
return bcr & 0xFF80;
}
-static target_ulong sdram_size (uint32_t bcr)
+static target_ulong sdram_size(uint32_t bcr)
{
target_ulong size;
int sh;
sh = (bcr >> 17) & 0x7;
-if (sh == 7)
+if (sh == 7) {
size = -1;
-else
+} else {
size = (4 * MiB) << sh;
+}
return size;
}
@@ -153,7 +154,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
}
-static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
[PULL 48/60] ppc4xx: Move PLB model to ppc4xx_devs.c
From: BALATON Zoltan
The PLB is shared between 405 and 440 so move it to the shared file.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<2498384bf3e18959ee8cb984d72fb66b8a6ecadc.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 11 -
hw/ppc/ppc405_uc.c | 93
hw/ppc/ppc4xx_devs.c| 94 +
include/hw/ppc/ppc4xx.h | 11 +
4 files changed, 105 insertions(+), 104 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 31c94e4742..d85c595f9d 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
-/* Peripheral local bus arbitrer */
-#define TYPE_PPC405_PLB "ppc405-plb"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
-struct Ppc405PlbState {
-Ppc4xxDcrDeviceState parent_obj;
-
-uint32_t acr;
-uint32_t bear;
-uint32_t besr;
-};
-
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b02dab05b3..3382ed3252 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env,
ram_addr_t ram_size)
/*/
/* Shared peripherals */
-/*/
-/* Peripheral local bus arbitrer */
-enum {
-PLB3A0_ACR = 0x077,
-PLB4A0_ACR = 0x081,
-PLB0_BESR = 0x084,
-PLB0_BEAR = 0x086,
-PLB0_ACR = 0x087,
-PLB4A1_ACR = 0x089,
-};
-
-static uint32_t dcr_read_plb(void *opaque, int dcrn)
-{
-Ppc405PlbState *plb = opaque;
-uint32_t ret;
-
-switch (dcrn) {
-case PLB0_ACR:
-ret = plb->acr;
-break;
-case PLB0_BEAR:
-ret = plb->bear;
-break;
-case PLB0_BESR:
-ret = plb->besr;
-break;
-default:
-/* Avoid gcc warning */
-ret = 0;
-break;
-}
-
-return ret;
-}
-
-static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
-{
-Ppc405PlbState *plb = opaque;
-
-switch (dcrn) {
-case PLB0_ACR:
-/* We don't care about the actual parameters written as
- * we don't manage any priorities on the bus
- */
-plb->acr = val & 0xF800;
-break;
-case PLB0_BEAR:
-/* Read only */
-break;
-case PLB0_BESR:
-/* Write-clear */
-plb->besr &= ~val;
-break;
-}
-}
-
-static void ppc405_plb_reset(DeviceState *dev)
-{
-Ppc405PlbState *plb = PPC405_PLB(dev);
-
-plb->acr = 0x;
-plb->bear = 0x;
-plb->besr = 0x;
-}
-
-static void ppc405_plb_realize(DeviceState *dev, Error **errp)
-{
-Ppc405PlbState *plb = PPC405_PLB(dev);
-Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
-ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, _read_plb, _write_plb);
-ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, _read_plb, _write_plb);
-ppc4xx_dcr_register(dcr, PLB0_ACR, plb, _read_plb, _write_plb);
-ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, _read_plb, _write_plb);
-ppc4xx_dcr_register(dcr, PLB0_BESR, plb, _read_plb, _write_plb);
-ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, _read_plb, _write_plb);
-}
-
-static void ppc405_plb_class_init(ObjectClass *oc, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(oc);
-
-dc->realize = ppc405_plb_realize;
-dc->reset = ppc405_plb_reset;
-/* Reason: only works as function of a ppc4xx SoC */
-dc->user_creatable = false;
-}
-
/*/
/* PLB to OPB bridge */
enum {
@@ -1538,11 +1450,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
-.name = TYPE_PPC405_PLB,
-.parent = TYPE_PPC4xx_DCR_DEVICE,
-.instance_size = sizeof(Ppc405PlbState),
-.class_init = ppc405_plb_class_init,
-}, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 7d40c1b68a..843d759b1b 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc, void
*data)
device_class_set_props(dc, ppc4xx_mal_properties);
}
+/*/
+/* Peripheral local bus arbitrer */
+enum {
+PLB3A0_ACR = 0x077,
+PLB4A0_ACR = 0x081,
+PLB0_BESR = 0x084,
+PLB0_BEAR = 0x086,
+PLB0_ACR = 0x087,
+PLB4A1_ACR = 0x089,
+};
+
+static uint32_t dcr_read_plb(void *opaque,
[PULL 57/60] hw/ppc/sam3460ex: Remove PPC405 dependency from sam460ex
From: BALATON Zoltan Now that shared PPC4xx devices are separated from PPC405 ones we can drop this depencency. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater Message-Id: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/Kconfig| 1 - hw/ppc/sam460ex.c | 1 - 2 files changed, 2 deletions(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 400511c6b7..205f9f98d7 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -58,7 +58,6 @@ config PPC4XX config SAM460EX bool -select PPC405 select PFLASH_CFI01 select IDE_SII3112 select M41T80 diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 348ed27211..850bb3b817 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -25,7 +25,6 @@ #include "elf.h" #include "exec/memory.h" #include "ppc440.h" -#include "ppc405.h" #include "hw/block/flash.h" #include "sysemu/sysemu.h" #include "sysemu/reset.h" -- 2.37.2
[PULL 53/60] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
From: BALATON Zoltan
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/intc/ppc-uic.c | 26 ++
hw/ppc/ppc405_uc.c| 6 ++
hw/ppc/ppc440_bamboo.c| 7 ++-
hw/ppc/ppc4xx_devs.c | 1 -
hw/ppc/sam460ex.c | 17 +++--
hw/ppc/virtex_ml507.c | 7 ++-
include/hw/intc/ppc-uic.h | 6 ++
7 files changed, 21 insertions(+), 49 deletions(-)
diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c
index 60013f2dde..dcf5de5d43 100644
--- a/hw/intc/ppc-uic.c
+++ b/hw/intc/ppc-uic.c
@@ -25,11 +25,8 @@
#include "qemu/osdep.h"
#include "hw/intc/ppc-uic.h"
#include "hw/irq.h"
-#include "cpu.h"
-#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
-#include "qapi/error.h"
enum {
DCR_UICSR = 0x000,
@@ -105,10 +102,9 @@ static void ppcuic_trigger_irq(PPCUIC *uic)
static void ppcuic_set_irq(void *opaque, int irq_num, int level)
{
-PPCUIC *uic;
+PPCUIC *uic = opaque;
uint32_t mask, sr;
-uic = opaque;
mask = 1U << (31 - irq_num);
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
@@ -144,10 +140,9 @@ static void ppcuic_set_irq(void *opaque, int irq_num, int
level)
static uint32_t dcr_read_uic(void *opaque, int dcrn)
{
-PPCUIC *uic;
+PPCUIC *uic = opaque;
uint32_t ret;
-uic = opaque;
dcrn -= uic->dcr_base;
switch (dcrn) {
case DCR_UICSR:
@@ -192,9 +187,8 @@ static uint32_t dcr_read_uic(void *opaque, int dcrn)
static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
{
-PPCUIC *uic;
+PPCUIC *uic = opaque;
-uic = opaque;
dcrn -= uic->dcr_base;
LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
@@ -251,19 +245,12 @@ static void ppc_uic_reset(DeviceState *dev)
static void ppc_uic_realize(DeviceState *dev, Error **errp)
{
PPCUIC *uic = PPC_UIC(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-PowerPCCPU *cpu;
int i;
-if (!uic->cpu) {
-/* This is a programming error in the code using this device */
-error_setg(errp, "ppc-uic 'cpu' link property was not set");
-return;
-}
-
-cpu = POWERPC_CPU(uic->cpu);
for (i = 0; i < DCR_UICMAX; i++) {
-ppc_dcr_register(>env, uic->dcr_base + i, uic,
+ppc4xx_dcr_register(dcr, uic->dcr_base + i, uic,
_read_uic, _write_uic);
}
@@ -273,7 +260,6 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp)
}
static Property ppc_uic_properties[] = {
-DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0),
DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
DEFINE_PROP_END_OF_LIST()
@@ -308,7 +294,7 @@ static void ppc_uic_class_init(ObjectClass *klass, void
*data)
static const TypeInfo ppc_uic_info = {
.name = TYPE_PPC_UIC,
-.parent = TYPE_SYS_BUS_DEVICE,
+.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(PPCUIC),
.class_init = ppc_uic_class_init,
};
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 47bb9f534a..dc17d5bdb5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1152,12 +1152,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
-object_property_set_link(OBJECT(>uic), "cpu", OBJECT(>cpu),
- _fatal);
-sbd = SYS_BUS_DEVICE(>uic);
-if (!sysbus_realize(sbd, errp)) {
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(>uic), >cpu, errp)) {
return;
}
+sbd = SYS_BUS_DEVICE(>uic);
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(>cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 873f930c77..b14a9ef776 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -193,12 +193,9 @@ static void bamboo_init(MachineState *machine)
/* interrupt controller */
uicdev = qdev_new(TYPE_PPC_UIC);
+ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, _fatal);
+object_unref(OBJECT(uicdev));
uicsbd = SYS_BUS_DEVICE(uicdev);
-
-object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
- _fatal);
-sysbus_realize_and_unref(uicsbd, _fatal);
-
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
diff --git
[PULL 42/60] ppc/ppc405: QOM'ify DMA
From: Cédric Le Goater
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<4738b3c7cf18c328f05aaaddc555a46219431335.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 19 ++
hw/ppc/ppc405_uc.c | 141 -
2 files changed, 81 insertions(+), 79 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 21f6cb3585..c75e4c7cb5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,24 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* DMA controller */
+#define TYPE_PPC405_DMA "ppc405-dma"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
+struct Ppc405DmaState {
+Ppc4xxDcrDeviceState parent_obj;
+
+qemu_irq irqs[4];
+uint32_t cr[4];
+uint32_t ct[4];
+uint32_t da[4];
+uint32_t sa[4];
+uint32_t sg[4];
+uint32_t sr;
+uint32_t sgc;
+uint32_t slp;
+uint32_t pol;
+};
+
/* GPIO */
#define TYPE_PPC405_GPIO "ppc405-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
@@ -173,6 +191,7 @@ struct Ppc405SoCState {
Ppc405GptState gpt;
Ppc405OcmState ocm;
Ppc405GpioState gpio;
+Ppc405DmaState dma;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3f4a5b36f5..3845c0fec1 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -613,35 +613,20 @@ enum {
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma_t ppc405_dma_t;
-struct ppc405_dma_t {
-qemu_irq irqs[4];
-uint32_t cr[4];
-uint32_t ct[4];
-uint32_t da[4];
-uint32_t sa[4];
-uint32_t sg[4];
-uint32_t sr;
-uint32_t sgc;
-uint32_t slp;
-uint32_t pol;
-};
-
-static uint32_t dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma(void *opaque, int dcrn)
{
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
{
}
-static void ppc405_dma_reset (void *opaque)
+static void ppc405_dma_reset(DeviceState *dev)
{
-ppc405_dma_t *dma;
+Ppc405DmaState *dma = PPC405_DMA(dev);
int i;
-dma = opaque;
for (i = 0; i < 4; i++) {
dma->cr[i] = 0x;
dma->ct[i] = 0x;
@@ -655,61 +640,50 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x;
}
-static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
+static void ppc405_dma_realize(DeviceState *dev, Error **errp)
+{
+Ppc405DmaState *dma = PPC405_DMA(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+int i;
+
+for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
+sysbus_init_irq(SYS_BUS_DEVICE(dma), >irqs[i]);
+}
+
+ppc4xx_dcr_register(dcr, DMA0_CR0, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CT0, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_DA0, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SA0, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SG0, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CR1, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CT1, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_DA1, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SA1, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SG1, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CR2, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CT2, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_DA2, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SA2, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SG2, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CR3, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_CT3, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_DA3, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SA3, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SG3, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SR, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SGC, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_SLP, dma, _read_dma, _write_dma);
+ppc4xx_dcr_register(dcr, DMA0_POL, dma, _read_dma, _write_dma);
+}
+
+static void ppc405_dma_class_init(ObjectClass *oc, void *data)
{
-ppc405_dma_t *dma;
-
-dma = g_new0(ppc405_dma_t, 1);
-memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
-qemu_register_reset(_dma_reset, dma);
-ppc_dcr_register(env, DMA0_CR0,
- dma, _read_dma, _write_dma);
-ppc_dcr_register(env, DMA0_CT0,
- dma, _read_dma, _write_dma);
-
[PULL 55/60] ppc/ppc405: QOM'ify FPGA
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 56 +-
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 3677793adc..7af0d7feef 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -71,18 +71,23 @@ struct Ppc405MachineState {
* - NVRAM (0xF000)
* - FPGA (0xF030)
*/
-typedef struct ref405ep_fpga_t ref405ep_fpga_t;
-struct ref405ep_fpga_t {
+
+#define TYPE_REF405EP_FPGA "ref405ep-fpga"
+OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
+struct Ref405epFpgaState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+
uint8_t reg0;
uint8_t reg1;
};
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
-ref405ep_fpga_t *fpga;
+Ref405epFpgaState *fpga = opaque;
uint32_t ret;
-fpga = opaque;
switch (addr) {
case 0x0:
ret = fpga->reg0;
@@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr
addr, unsigned size)
static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
-ref405ep_fpga_t *fpga;
+Ref405epFpgaState *fpga = opaque;
-fpga = opaque;
switch (addr) {
case 0x0:
/* Read only */
@@ -126,27 +130,40 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ref405ep_fpga_reset (void *opaque)
+static void ref405ep_fpga_reset(DeviceState *dev)
{
-ref405ep_fpga_t *fpga;
+Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
-fpga = opaque;
fpga->reg0 = 0x00;
fpga->reg1 = 0x0F;
}
-static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
+static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
{
-ref405ep_fpga_t *fpga;
-MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
+Ref405epFpgaState *s = REF405EP_FPGA(dev);
-fpga = g_new0(ref405ep_fpga_t, 1);
-memory_region_init_io(fpga_memory, NULL, _fpga_ops, fpga,
+memory_region_init_io(>iomem, OBJECT(s), _fpga_ops, s,
"fpga", 0x0100);
-memory_region_add_subregion(sysmem, base, fpga_memory);
-qemu_register_reset(_fpga_reset, fpga);
+sysbus_init_mmio(SYS_BUS_DEVICE(s), >iomem);
+}
+
+static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = ref405ep_fpga_realize;
+dc->reset = ref405ep_fpga_reset;
+/* Reason: only works as part of a ppc405 board */
+dc->user_creatable = false;
}
+static const TypeInfo ref405ep_fpga_type = {
+.name = TYPE_REF405EP_FPGA,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(Ref405epFpgaState),
+.class_init = ref405ep_fpga_class_init,
+};
+
/*
* CPU reset handler when booting directly from a loaded kernel
*/
@@ -331,7 +348,11 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
/* Register FPGA */
-ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+dev = qdev_new(TYPE_REF405EP_FPGA);
+object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
+sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
+
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
@@ -376,6 +397,7 @@ static void ppc405_machine_init(void)
{
type_register_static(_machine_type);
type_register_static(_type);
+type_register_static(_fpga_type);
}
type_init(ppc405_machine_init)
--
2.37.2
[PULL 51/60] ppc4xx: Rename ppc405-ebc to ppc4xx-ebc
From: BALATON Zoltan
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<63d9b14c8ff5f73e35bffca1036394b5235735ee.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc4xx_devs.c| 12 ++--
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 6 +++---
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 57e1494b05..343a84c98e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -214,7 +214,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
-Ppc405EbcState ebc;
+Ppc4xxEbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc4xxPlbState plb;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index c7bc40ba08..247c4f3fa8 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1094,7 +1094,7 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", >dma, TYPE_PPC405_DMA);
-object_initialize_child(obj, "ebc", >ebc, TYPE_PPC405_EBC);
+object_initialize_child(obj, "ebc", >ebc, TYPE_PPC4xx_EBC);
object_initialize_child(obj, "opba", >opba, TYPE_PPC405_OPBA);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 00bb3fe974..fbfb21c8e8 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -756,7 +756,7 @@ enum {
static uint32_t dcr_read_ebc(void *opaque, int dcrn)
{
-Ppc405EbcState *ebc = opaque;
+Ppc4xxEbcState *ebc = opaque;
uint32_t ret;
switch (dcrn) {
@@ -840,7 +840,7 @@ static uint32_t dcr_read_ebc(void *opaque, int dcrn)
static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
{
-Ppc405EbcState *ebc = opaque;
+Ppc4xxEbcState *ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
@@ -899,7 +899,7 @@ static void dcr_write_ebc(void *opaque, int dcrn, uint32_t
val)
static void ppc405_ebc_reset(DeviceState *dev)
{
-Ppc405EbcState *ebc = PPC405_EBC(dev);
+Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
int i;
ebc->addr = 0x;
@@ -916,7 +916,7 @@ static void ppc405_ebc_reset(DeviceState *dev)
static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
{
-Ppc405EbcState *ebc = PPC405_EBC(dev);
+Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, _read_ebc, _write_ebc);
@@ -975,9 +975,9 @@ static const TypeInfo ppc4xx_types[] = {
.instance_size = sizeof(Ppc4xxPlbState),
.class_init = ppc405_plb_class_init,
}, {
-.name = TYPE_PPC405_EBC,
+.name = TYPE_PPC4xx_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
-.instance_size = sizeof(Ppc405EbcState),
+.instance_size = sizeof(Ppc4xxEbcState),
.class_init = ppc405_ebc_class_init,
}, {
.name = TYPE_PPC4xx_DCR_DEVICE,
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 6b1c843eeb..0d9259f0f2 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -372,7 +372,7 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 3));
/* External bus controller */
-dev = qdev_new(TYPE_PPC405_EBC);
+dev = qdev_new(TYPE_PPC4xx_EBC);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, _fatal);
object_unref(OBJECT(dev));
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 4472ec254e..a1781afa8e 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -95,9 +95,9 @@ struct Ppc4xxPlbState {
};
/* Peripheral controller */
-#define TYPE_PPC405_EBC "ppc405-ebc"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
-struct Ppc405EbcState {
+#define TYPE_PPC4xx_EBC "ppc4xx-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC);
+struct Ppc4xxEbcState {
Ppc4xxDcrDeviceState parent_obj;
uint32_t addr;
--
2.37.2
[PULL 40/60] ppc/ppc405: QOM'ify OCM
From: Cédric Le Goater
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 16 ++
hw/ppc/ppc405_uc.c | 77 +++---
2 files changed, 55 insertions(+), 38 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index bcf55e4f6b..a5b493d3e7 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* On Chip Memory */
+#define TYPE_PPC405_OCM "ppc405-ocm"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
+struct Ppc405OcmState {
+Ppc4xxDcrDeviceState parent_obj;
+
+MemoryRegion ram;
+MemoryRegion isarc_ram;
+MemoryRegion dsarc_ram;
+uint32_t isarc;
+uint32_t isacntl;
+uint32_t dsarc;
+uint32_t dsacntl;
+};
+
/* General purpose timers */
#define TYPE_PPC405_GPT "ppc405-gpt"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
@@ -136,6 +151,7 @@ struct Ppc405SoCState {
DeviceState *uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
+Ppc405OcmState ocm;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1994801abe..8ee0357ac3 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -773,20 +773,9 @@ enum {
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm_t ppc405_ocm_t;
-struct ppc405_ocm_t {
-MemoryRegion ram;
-MemoryRegion isarc_ram;
-MemoryRegion dsarc_ram;
-uint32_t isarc;
-uint32_t isacntl;
-uint32_t dsarc;
-uint32_t dsacntl;
-};
-
-static void ocm_update_mappings (ppc405_ocm_t *ocm,
- uint32_t isarc, uint32_t isacntl,
- uint32_t dsarc, uint32_t dsacntl)
+static void ocm_update_mappings(Ppc405OcmState *ocm,
+uint32_t isarc, uint32_t isacntl,
+uint32_t dsarc, uint32_t dsacntl)
{
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
@@ -828,12 +817,11 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
}
}
-static uint32_t dcr_read_ocm (void *opaque, int dcrn)
+static uint32_t dcr_read_ocm(void *opaque, int dcrn)
{
-ppc405_ocm_t *ocm;
+Ppc405OcmState *ocm = opaque;
uint32_t ret;
-ocm = opaque;
switch (dcrn) {
case OCM0_ISARC:
ret = ocm->isarc;
@@ -855,12 +843,11 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val)
{
-ppc405_ocm_t *ocm;
+Ppc405OcmState *ocm = opaque;
uint32_t isarc, dsarc, isacntl, dsacntl;
-ocm = opaque;
isarc = ocm->isarc;
dsarc = ocm->dsarc;
isacntl = ocm->isacntl;
@@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn,
uint32_t val)
ocm->dsacntl = dsacntl;
}
-static void ocm_reset (void *opaque)
+static void ppc405_ocm_reset(DeviceState *dev)
{
-ppc405_ocm_t *ocm;
+Ppc405OcmState *ocm = PPC405_OCM(dev);
uint32_t isarc, dsarc, isacntl, dsacntl;
-ocm = opaque;
isarc = 0x;
isacntl = 0x;
dsarc = 0x;
@@ -903,25 +889,31 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUPPCState *env)
+static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
{
-ppc405_ocm_t *ocm;
+Ppc405OcmState *ocm = PPC405_OCM(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-ocm = g_new0(ppc405_ocm_t, 1);
/* XXX: Size is 4096 or 0x0400 */
-memory_region_init_ram(>isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
+memory_region_init_ram(>isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
_fatal);
-memory_region_init_alias(>dsarc_ram, NULL, "ppc405.dsarc",
+memory_region_init_alias(>dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
>isarc_ram, 0, 4 * KiB);
-qemu_register_reset(_reset, ocm);
-ppc_dcr_register(env, OCM0_ISARC,
- ocm, _read_ocm, _write_ocm);
-ppc_dcr_register(env, OCM0_ISACNTL,
- ocm, _read_ocm, _write_ocm);
-ppc_dcr_register(env, OCM0_DSARC,
- ocm, _read_ocm, _write_ocm);
-ppc_dcr_register(env, OCM0_DSACNTL,
- ocm, _read_ocm, _write_ocm);
+
+ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, _read_ocm, _write_ocm);
+ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, _read_ocm, _write_ocm);
+ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, _read_ocm, _write_ocm);
+ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm,
[PULL 52/60] ppc/ppc405: Use an embedded PPCUIC model in SoC state
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 28 ++--
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 343a84c98e..67f4c14f50 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
+#include "hw/intc/ppc-uic.h"
#define PPC405EP_SDRAM_BASE 0x
#define PPC405EP_NVRAM_BASE 0xF000
@@ -208,7 +209,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
PowerPCCPU cpu;
-DeviceState *uic;
+PPCUIC uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 247c4f3fa8..47bb9f534a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1083,6 +1083,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", >cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+object_initialize_child(obj, "uic", >uic, TYPE_PPC_UIC);
+
object_initialize_child(obj, "cpc", >cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(>cpc), "sys-clk");
@@ -1150,17 +1152,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
-s->uic = qdev_new(TYPE_PPC_UIC);
-
-object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(>cpu),
+object_property_set_link(OBJECT(>uic), "cpu", OBJECT(>cpu),
_fatal);
-if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+sbd = SYS_BUS_DEVICE(>uic);
+if (!sysbus_realize(sbd, errp)) {
return;
}
-
-sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(>cpu), PPC40x_INPUT_INT));
-sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(>cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
@@ -1171,7 +1171,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
"ppc405.sdram0", s->dram_mr,
s->ram_bases[0], s->ram_sizes[0]);
-ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
+ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(>uic), 17), 1,
s->ram_banks, s->ram_bases, s->ram_sizes,
s->do_dram_init);
@@ -1186,12 +1186,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
sbd = SYS_BUS_DEVICE(>dma);
for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
-sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i));
+sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(>uic), 5 + i));
}
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(s->uic, 2));
+ qdev_get_gpio_in(DEVICE(>uic), 2));
/* GPIO */
sbd = SYS_BUS_DEVICE(>gpio);
@@ -1203,13 +1203,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
/* Serial ports */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0,
- qdev_get_gpio_in(s->uic, 0),
+ qdev_get_gpio_in(DEVICE(>uic), 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0,
- qdev_get_gpio_in(s->uic, 1),
+ qdev_get_gpio_in(DEVICE(>uic), 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
@@ -1226,7 +1226,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
sysbus_mmio_map(sbd, 0, 0xef60);
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
-sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i));
+sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(>uic), 19 + i));
}
/* MAL */
@@ -1237,7 +1237,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
sbd = SYS_BUS_DEVICE(>mal);
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
-sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i));
+sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(>uic), 11 + i));
}
/* Ethernet */
--
2.37.2
[PULL 44/60] ppc/ppc405: QOM'ify OPBA
From: Cédric Le Goater
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<38476bc43d2332db2f09dbede9eff5234d6ce217.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 12 +++
hw/ppc/ppc405_uc.c | 49 +++--
hw/ppc/trace-events | 1 -
3 files changed, 41 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 82bf8dae93..d63c2acdc7 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* OPB arbitrer */
+#define TYPE_PPC405_OPBA "ppc405-opba"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
+struct Ppc405OpbaState {
+SysBusDevice parent_obj;
+
+MemoryRegion io;
+uint8_t cr;
+uint8_t pr;
+};
+
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@@ -208,6 +219,7 @@ struct Ppc405SoCState {
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
+Ppc405OpbaState opba;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ff81fb3e20..2c482bc25c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -310,16 +310,9 @@ static void ppc4xx_pob_init(CPUPPCState *env)
/*/
/* OPB arbitrer */
-typedef struct ppc4xx_opba_t ppc4xx_opba_t;
-struct ppc4xx_opba_t {
-MemoryRegion io;
-uint8_t cr;
-uint8_t pr;
-};
-
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
-ppc4xx_opba_t *opba = opaque;
+Ppc405OpbaState *opba = opaque;
uint32_t ret;
switch (addr) {
@@ -341,7 +334,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr,
unsigned size)
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
-ppc4xx_opba_t *opba = opaque;
+Ppc405OpbaState *opba = opaque;
trace_opba_writeb(addr, value);
@@ -366,25 +359,30 @@ static const MemoryRegionOps opba_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ppc4xx_opba_reset (void *opaque)
+static void ppc405_opba_reset(DeviceState *dev)
{
-ppc4xx_opba_t *opba;
+Ppc405OpbaState *opba = PPC405_OPBA(dev);
-opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(hwaddr base)
+static void ppc405_opba_realize(DeviceState *dev, Error **errp)
{
-ppc4xx_opba_t *opba;
+Ppc405OpbaState *s = PPC405_OPBA(dev);
+
+memory_region_init_io(>io, OBJECT(s), _ops, s, "opba", 2);
+sysbus_init_mmio(SYS_BUS_DEVICE(s), >io);
+}
-trace_opba_init(base);
+static void ppc405_opba_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
-opba = g_new0(ppc4xx_opba_t, 1);
-memory_region_init_io(>io, NULL, _ops, opba, "opba", 0x002);
-memory_region_add_subregion(get_system_memory(), base, >io);
-qemu_register_reset(ppc4xx_opba_reset, opba);
+dc->realize = ppc405_opba_realize;
+dc->reset = ppc405_opba_reset;
+/* Reason: only works as function of a ppc4xx SoC */
+dc->user_creatable = false;
}
/*/
@@ -1373,6 +1371,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", >dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", >ebc, TYPE_PPC405_EBC);
+
+object_initialize_child(obj, "opba", >opba, TYPE_PPC405_OPBA);
}
static void ppc405_reset(void *opaque)
@@ -1410,7 +1410,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
ppc4xx_pob_init(env);
/* OBP arbitrer */
-ppc4xx_opba_init(0xef600600);
+sbd = SYS_BUS_DEVICE(>opba);
+if (!sysbus_realize(sbd, errp)) {
+return;
+}
+sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
@@ -1523,6 +1527,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+.name = TYPE_PPC405_OPBA,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(Ppc405OpbaState),
+.class_init = ppc405_opba_class_init,
+}, {
.name = TYPE_PPC405_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405EbcState),
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 69a95f9f57..a07d5aca0f 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -161,7 +161,6 @@ ppc440_pcix_reg_write(uint64_t addr, uint32_t
[PULL 39/60] ppc/ppc405: QOM'ify GPT
From: Cédric Le Goater
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan
Message-Id:
<8950ab26e78173f94ba65bc61bcfd0631de1fe61.1660746880.git.bala...@eik.bme.hu>
[danielhb: check if timer != NULL in ppc405_gpt_finalize()]
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 22 ++
hw/ppc/ppc405_uc.c | 102
hw/ppc/trace-events | 1 -
3 files changed, 78 insertions(+), 47 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 2ba829988d..bcf55e4f6b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* General purpose timers */
+#define TYPE_PPC405_GPT "ppc405-gpt"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
+struct Ppc405GptState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+
+int64_t tb_offset;
+uint32_t tb_freq;
+QEMUTimer *timer;
+qemu_irq irqs[5];
+uint32_t oe;
+uint32_t ol;
+uint32_t im;
+uint32_t is;
+uint32_t ie;
+uint32_t comp[5];
+uint32_t mask[5];
+};
+
#define TYPE_PPC405_CPC "ppc405-cpc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
@@ -114,6 +135,7 @@ struct Ppc405SoCState {
PowerPCCPU cpu;
DeviceState *uic;
Ppc405CpcState cpc;
+Ppc405GptState gpt;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ec83c292a5..1994801abe 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
/*/
/* General purpose timers */
-typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
-struct ppc4xx_gpt_t {
-MemoryRegion iomem;
-int64_t tb_offset;
-uint32_t tb_freq;
-QEMUTimer *timer;
-qemu_irq irqs[5];
-uint32_t oe;
-uint32_t ol;
-uint32_t im;
-uint32_t is;
-uint32_t ie;
-uint32_t comp[5];
-uint32_t mask[5];
-};
-
-static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
+static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
+static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
{
/* XXX: TODO */
}
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
-ppc4xx_gpt_t *gpt = opaque;
+Ppc405GptState *gpt = opaque;
uint32_t ret;
int idx;
@@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr
addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
-ppc4xx_gpt_t *gpt = opaque;
+Ppc405GptState *gpt = opaque;
int idx;
trace_ppc4xx_gpt_write(addr, size, value);
@@ -1114,22 +1098,20 @@ static const MemoryRegionOps gpt_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc4xx_gpt_cb (void *opaque)
+static void ppc4xx_gpt_cb(void *opaque)
{
-ppc4xx_gpt_t *gpt;
+Ppc405GptState *gpt = opaque;
-gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
ppc4xx_gpt_set_outputs(gpt);
ppc4xx_gpt_compute_timer(gpt);
}
-static void ppc4xx_gpt_reset (void *opaque)
+static void ppc405_gpt_reset(DeviceState *dev)
{
-ppc4xx_gpt_t *gpt;
+Ppc405GptState *gpt = PPC405_GPT(dev);
int i;
-gpt = opaque;
timer_del(gpt->timer);
gpt->oe = 0x;
gpt->ol = 0x;
@@ -1142,21 +1124,37 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
+static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
{
-ppc4xx_gpt_t *gpt;
+Ppc405GptState *s = PPC405_GPT(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
-trace_ppc4xx_gpt_init(base);
+s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, _gpt_cb, s);
+memory_region_init_io(>iomem, OBJECT(s), _ops, s, "gpt", 0xd4);
+sysbus_init_mmio(sbd, >iomem);
-gpt = g_new0(ppc4xx_gpt_t, 1);
-for (i = 0; i < 5; i++) {
Re: [RFC v4 00/11] blkio: add libblkio BlockDriver
On Tue, Aug 23, 2022 at 08:31:03PM +0300, Vladimir Sementsov-Ogievskiy wrote: > On 8/23/22 01:23, Stefan Hajnoczi wrote: > > The remainder of the patch series reworks the existing QEMU > > bdrv_register_buf() > > API so virtio-blk emulation efficiently map guest RAM for libblkio - some > > libblkio drivers require that I/O buffer memory is pre-registered (think > > VFIO, > > vhost, etc). > > Hi! > > So patches 01-11 are for performance optimization? Don't you have some > performance measurements for it? Hi Vladimir, I ran the patches against qemu-storage-daemon's vhost-user-blk export with iodepth=1 bs=512 to see the per-request overhead due to bounce buffer allocation/mapping: Name IOPS Error bounce-buf 4373.81 ± 0.01% registered-buf 13062.80 ± 0.67% The BDRV_REQ_REGISTERED_BUF optimization version is about 3x faster. Note that IOPS is low because the vhost-user-blk vq is not passed through to the guest yet (Stefano is working on this). The guest is also using interrupts, not polling (recent Linux virtio_blk.ko drivers support poll queues). I'll also include performance results in the next revision of the patch series. Stefan signature.asc Description: PGP signature
[PULL 50/60] ppc4xx: Move EBC model to ppc4xx_devs.c
From: BALATON Zoltan
The EBC is shared between 405 and 440 so move it to shared file.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<10eae70509ca4bd74858fc2c0a0f0e4eb9330199.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 15
hw/ppc/ppc405_uc.c | 191
hw/ppc/ppc4xx_devs.c| 191
include/hw/ppc/ppc4xx.h | 15
4 files changed, 206 insertions(+), 206 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8521be317d..57e1494b05 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -85,21 +85,6 @@ struct Ppc405OpbaState {
uint8_t pr;
};
-/* Peripheral controller */
-#define TYPE_PPC405_EBC "ppc405-ebc"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
-struct Ppc405EbcState {
-Ppc4xxDcrDeviceState parent_obj;
-
-uint32_t addr;
-uint32_t bcr[8];
-uint32_t bap[8];
-uint32_t bear;
-uint32_t besr0;
-uint32_t besr1;
-uint32_t cfg;
-};
-
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b7f6d1c9c1..c7bc40ba08 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -299,192 +299,6 @@ static void ppc405_opba_class_init(ObjectClass *oc, void
*data)
/* Code decompression controller */
/* XXX: TODO */
-/*/
-/* Peripheral controller */
-enum {
-EBC0_CFGADDR = 0x012,
-EBC0_CFGDATA = 0x013,
-};
-
-static uint32_t dcr_read_ebc(void *opaque, int dcrn)
-{
-Ppc405EbcState *ebc = opaque;
-uint32_t ret;
-
-switch (dcrn) {
-case EBC0_CFGADDR:
-ret = ebc->addr;
-break;
-case EBC0_CFGDATA:
-switch (ebc->addr) {
-case 0x00: /* B0CR */
-ret = ebc->bcr[0];
-break;
-case 0x01: /* B1CR */
-ret = ebc->bcr[1];
-break;
-case 0x02: /* B2CR */
-ret = ebc->bcr[2];
-break;
-case 0x03: /* B3CR */
-ret = ebc->bcr[3];
-break;
-case 0x04: /* B4CR */
-ret = ebc->bcr[4];
-break;
-case 0x05: /* B5CR */
-ret = ebc->bcr[5];
-break;
-case 0x06: /* B6CR */
-ret = ebc->bcr[6];
-break;
-case 0x07: /* B7CR */
-ret = ebc->bcr[7];
-break;
-case 0x10: /* B0AP */
-ret = ebc->bap[0];
-break;
-case 0x11: /* B1AP */
-ret = ebc->bap[1];
-break;
-case 0x12: /* B2AP */
-ret = ebc->bap[2];
-break;
-case 0x13: /* B3AP */
-ret = ebc->bap[3];
-break;
-case 0x14: /* B4AP */
-ret = ebc->bap[4];
-break;
-case 0x15: /* B5AP */
-ret = ebc->bap[5];
-break;
-case 0x16: /* B6AP */
-ret = ebc->bap[6];
-break;
-case 0x17: /* B7AP */
-ret = ebc->bap[7];
-break;
-case 0x20: /* BEAR */
-ret = ebc->bear;
-break;
-case 0x21: /* BESR0 */
-ret = ebc->besr0;
-break;
-case 0x22: /* BESR1 */
-ret = ebc->besr1;
-break;
-case 0x23: /* CFG */
-ret = ebc->cfg;
-break;
-default:
-ret = 0x;
-break;
-}
-break;
-default:
-ret = 0x;
-break;
-}
-
-return ret;
-}
-
-static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
-{
-Ppc405EbcState *ebc = opaque;
-
-switch (dcrn) {
-case EBC0_CFGADDR:
-ebc->addr = val;
-break;
-case EBC0_CFGDATA:
-switch (ebc->addr) {
-case 0x00: /* B0CR */
-break;
-case 0x01: /* B1CR */
-break;
-case 0x02: /* B2CR */
-break;
-case 0x03: /* B3CR */
-break;
-case 0x04: /* B4CR */
-break;
-case 0x05: /* B5CR */
-break;
-case 0x06: /* B6CR */
-break;
-case 0x07: /* B7CR */
-break;
-case 0x10: /* B0AP */
-break;
-case 0x11: /* B1AP */
-break;
-case 0x12: /* B2AP */
-break;
-case 0x13: /* B3AP */
-break;
-case 0x14: /* B4AP */
-break;
-case 0x15: /* B5AP */
-break;
-case 0x16: /* B6AP */
-break;
-case 0x17: /* B7AP */
-break;
-case 0x20: /* BEAR */
-break;
-case 0x21: /* BESR0 */
-break;
-case 0x22: /* BESR1 */
-break;
-case
[PULL 36/60] ppc/ppc405: QOM'ify CPU
From: Cédric Le Goater
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CPU families needing it.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153904.485018-8-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 40 ++--
hw/ppc/ppc4xx_devs.c| 32
include/hw/ppc/ppc4xx.h | 5 -
5 files changed, 32 insertions(+), 49 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index dc862bc861..8cc76cc8b3 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -79,7 +79,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
uint32_t sysclk;
-PowerPCCPU *cpu;
+PowerPCCPU cpu;
DeviceState *uic;
};
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b93e85b5d9..3677793adc 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
-boot_from_kernel(machine, ppc405->soc.cpu);
+boot_from_kernel(machine, >soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index c05ab60436..14a525b2eb 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,22 +1432,41 @@ static void ppc405ep_cpc_init (CPUPPCState *env,
clk_setup_t clk_setup[8],
#endif
}
+static void ppc405_soc_instance_init(Object *obj)
+{
+Ppc405SoCState *s = PPC405_SOC(obj);
+
+object_initialize_child(obj, "cpu", >cpu,
+POWERPC_CPU_TYPE_NAME("405ep"));
+}
+
+static void ppc405_reset(void *opaque)
+{
+cpu_reset(CPU(opaque));
+}
+
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
-clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
+clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
memset(clk_setup, 0, sizeof(clk_setup));
/* init CPUs */
-s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
- _setup[PPC405EP_CPU_CLK],
- _clk_setup, s->sysclk);
-env = >cpu->env;
-clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
-clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
+if (!qdev_realize(DEVICE(>cpu), NULL, errp)) {
+return;
+}
+qemu_register_reset(ppc405_reset, >cpu);
+
+env = >cpu.env;
+
+clk_setup[PPC405EP_CPU_CLK].cb =
+ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
+clk_setup[PPC405EP_CPU_CLK].opaque = env;
+
+ppc_dcr_init(env, NULL, NULL);
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, s->sysclk);
@@ -1464,16 +1483,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
-object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu),
+object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(>cpu),
_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT));
+ qdev_get_gpio_in(DEVICE(>cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT));
+ qdev_get_gpio_in(DEVICE(>cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
@@ -1563,6 +1582,7 @@ static const TypeInfo ppc405_types[] = {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
+.instance_init = ppc405_soc_instance_init,
.class_init = ppc405_soc_class_init,
}
};
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 737c0896b4..069b511951 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -37,38 +37,6 @@
#include "qapi/error.h"
#include "trace.h"
-static void ppc4xx_reset(void *opaque)
-{
-PowerPCCPU *cpu = opaque;
-
-cpu_reset(CPU(cpu));
-}
-
-/*/
-/* Generic PowerPC 4xx processor instantiation */
-PowerPCCPU *ppc4xx_init(const char *cpu_type,
-clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
-uint32_t
[PULL 37/60] ppc/ppc4xx: Introduce a DCR device model
From: Cédric Le Goater
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead, introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
to install the device model in the overall SoC.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Explicit opaque parameter for dcr callbacks]
Signed-off-by: BALATON Zoltan
Message-Id:
<9b21bdf55e0a728f093bad299e030d98f302ded0.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc4xx_devs.c| 41 +
include/hw/ppc/ppc4xx.h | 17 +
2 files changed, 58 insertions(+)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 069b511951..f4d7ae9567 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
mal, _read_mal, _write_mal);
}
}
+
+/* PPC4xx_DCR_DEVICE */
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+assert(dev->cpu);
+ppc_dcr_register(>cpu->env, dcrn, opaque, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+Error **errp)
+{
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), _abort);
+return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+static Property ppc4xx_dcr_properties[] = {
+DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+{
+.name = TYPE_PPC4xx_DCR_DEVICE,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(Ppc4xxDcrDeviceState),
+.class_init = ppc4xx_dcr_class_init,
+.abstract = true,
+}
+};
+
+DEFINE_TYPES(ppc4xx_types)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 591e2421a3..a537a5567b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
#include "hw/ppc/ppc.h"
#include "exec/memory.h"
+#include "hw/sysbus.h"
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
@@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+SysBusDevice parent_obj;
+
+PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+Error **errp);
+
#endif /* PPC4XX_H */
--
2.37.2
[PULL 47/60] ppc/ppc405: QOM'ify MAL
From: Cédric Le Goater
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 1 +
hw/ppc/ppc405_uc.c | 17 +++--
hw/ppc/ppc4xx_devs.c| 145
hw/ppc/sam460ex.c | 12 ++--
include/hw/ppc/ppc4xx.h | 28 +++-
5 files changed, 117 insertions(+), 86 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index cb34792daf..31c94e4742 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -244,6 +244,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
+Ppc4xxMalState mal;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 9ed3ce4ebe..b02dab05b3 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1375,6 +1375,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", >pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", >plb, TYPE_PPC405_PLB);
+
+object_initialize_child(obj, "mal", >mal, TYPE_PPC4xx_MAL);
}
static void ppc405_reset(void *opaque)
@@ -1385,7 +1387,6 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
-qemu_irq mal_irqs[4];
CPUPPCState *env;
SysBusDevice *sbd;
int i;
@@ -1503,11 +1504,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
/* MAL */
-mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
-mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
-mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
-mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
-ppc4xx_mal_init(env, 4, 2, mal_irqs);
+object_property_set_int(OBJECT(>mal), "txc-num", 4, _abort);
+object_property_set_int(OBJECT(>mal), "rxc-num", 2, _abort);
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(>mal), >cpu, errp)) {
+return;
+}
+sbd = SYS_BUS_DEVICE(>mal);
+for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
+sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i));
+}
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f4d7ae9567..7d40c1b68a 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -459,32 +459,10 @@ enum {
MAL0_RCBS1= 0x1E1,
};
-typedef struct ppc4xx_mal_t ppc4xx_mal_t;
-struct ppc4xx_mal_t {
-qemu_irq irqs[4];
-uint32_t cfg;
-uint32_t esr;
-uint32_t ier;
-uint32_t txcasr;
-uint32_t txcarr;
-uint32_t txeobisr;
-uint32_t txdeir;
-uint32_t rxcasr;
-uint32_t rxcarr;
-uint32_t rxeobisr;
-uint32_t rxdeir;
-uint32_t *txctpr;
-uint32_t *rxctpr;
-uint32_t *rcbs;
-uint8_t txcnum;
-uint8_t rxcnum;
-};
-
-static void ppc4xx_mal_reset(void *opaque)
+static void ppc4xx_mal_reset(DeviceState *dev)
{
-ppc4xx_mal_t *mal;
+Ppc4xxMalState *mal = PPC4xx_MAL(dev);
-mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x;
mal->ier = 0x;
@@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
-ppc4xx_mal_t *mal;
+Ppc4xxMalState *mal = opaque;
uint32_t ret;
-mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
@@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
-ppc4xx_mal_t *mal;
+Ppc4xxMalState *mal = opaque;
-mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x8000) {
-ppc4xx_mal_reset(mal);
+ppc4xx_mal_reset(DEVICE(mal));
}
mal->cfg = val & 0x00FFC087;
break;
@@ -612,59 +588,76 @@ static void dcr_write_mal(void *opaque, int dcrn,
uint32_t val)
}
}
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4])
+static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
{
-ppc4xx_mal_t *mal;
+Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
int i;
-assert(txcnum <= 32 && rxcnum <= 32);
-mal = g_malloc0(sizeof(*mal));
-mal->txcnum = txcnum;
-mal->rxcnum = rxcnum;
-mal->txctpr = g_new0(uint32_t, txcnum);
-mal->rxctpr = g_new0(uint32_t, rxcnum);
-mal->rcbs = g_new0(uint32_t, rxcnum);
-for (i = 0; i < 4; i++) {
-mal->irqs[i] = irqs[i];
+if (mal->txcnum > 32 || mal->rxcnum > 32) {
+error_setg(errp, "invalid TXC/RXC number");
+
[PULL 38/60] ppc/ppc405: QOM'ify CPC
From: Cédric Le Goater
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 35 ++-
hw/ppc/ppc405_uc.c | 141 -
2 files changed, 95 insertions(+), 81 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8cc76cc8b3..2ba829988d 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_CPC "ppc405-cpc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
+
+enum {
+PPC405EP_CPU_CLK = 0,
+PPC405EP_PLB_CLK = 1,
+PPC405EP_OPB_CLK = 2,
+PPC405EP_EBC_CLK = 3,
+PPC405EP_MAL_CLK = 4,
+PPC405EP_PCI_CLK = 5,
+PPC405EP_UART0_CLK = 6,
+PPC405EP_UART1_CLK = 7,
+PPC405EP_CLK_NB= 8,
+};
+
+struct Ppc405CpcState {
+Ppc4xxDcrDeviceState parent_obj;
+
+uint32_t sysclk;
+clk_setup_t clk_setup[PPC405EP_CLK_NB];
+uint32_t boot;
+uint32_t epctl;
+uint32_t pllmr[2];
+uint32_t ucr;
+uint32_t srr;
+uint32_t jtagid;
+uint32_t pci;
+/* Clock and power management */
+uint32_t er;
+uint32_t fr;
+uint32_t sr;
+};
+
#define TYPE_PPC405_SOC "ppc405-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
@@ -78,9 +111,9 @@ struct Ppc405SoCState {
MemoryRegion *dram_mr;
hwaddr ram_size;
-uint32_t sysclk;
PowerPCCPU cpu;
DeviceState *uic;
+Ppc405CpcState cpc;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 14a525b2eb..ec83c292a5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1178,36 +1178,7 @@ enum {
#endif
};
-enum {
-PPC405EP_CPU_CLK = 0,
-PPC405EP_PLB_CLK = 1,
-PPC405EP_OPB_CLK = 2,
-PPC405EP_EBC_CLK = 3,
-PPC405EP_MAL_CLK = 4,
-PPC405EP_PCI_CLK = 5,
-PPC405EP_UART0_CLK = 6,
-PPC405EP_UART1_CLK = 7,
-PPC405EP_CLK_NB= 8,
-};
-
-typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
-struct ppc405ep_cpc_t {
-uint32_t sysclk;
-clk_setup_t clk_setup[PPC405EP_CLK_NB];
-uint32_t boot;
-uint32_t epctl;
-uint32_t pllmr[2];
-uint32_t ucr;
-uint32_t srr;
-uint32_t jtagid;
-uint32_t pci;
-/* Clock and power management */
-uint32_t er;
-uint32_t fr;
-uint32_t sr;
-};
-
-static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
+static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
@@ -1300,12 +1271,11 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t
*cpc)
clk_setup(>clk_setup[PPC405EP_UART1_CLK], UART1_clk);
}
-static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
{
-ppc405ep_cpc_t *cpc;
+Ppc405CpcState *cpc = opaque;
uint32_t ret;
-cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
ret = cpc->boot;
@@ -1340,11 +1310,10 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val)
{
-ppc405ep_cpc_t *cpc;
+Ppc405CpcState *cpc = opaque;
-cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
/* Read-only register */
@@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc405ep_cpc_reset (void *opaque)
+static void ppc405_cpc_reset(DeviceState *dev)
{
-ppc405ep_cpc_t *cpc = opaque;
+Ppc405CpcState *cpc = PPC405_CPC(dev);
cpc->boot = 0x0010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x;
@@ -1391,53 +1360,66 @@ static void ppc405ep_cpc_reset (void *opaque)
cpc->er = 0x;
cpc->fr = 0x;
cpc->sr = 0x;
+cpc->jtagid = 0x20267049;
ppc405ep_compute_clocks(cpc);
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
- uint32_t sysclk)
+static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
{
-ppc405ep_cpc_t *cpc;
+Ppc405CpcState *cpc = PPC405_CPC(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+assert(dcr->cpu);
+cpc->clk_setup[PPC405EP_CPU_CLK].cb =
+ppc_40x_timers_init(>cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT);
+
[PULL 30/60] ppc/ppc405: Remove taihu machine
From: Cédric Le Goater
It has been deprecated since 7.0.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-2-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
MAINTAINERS | 2 +-
docs/about/deprecated.rst | 9 --
docs/about/removed-features.rst | 6 +
docs/system/ppc/embedded.rst| 1 -
hw/ppc/ppc405_boards.c | 232
5 files changed, 7 insertions(+), 243 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ce4227ff6..1729c0901c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1282,7 +1282,7 @@ F: hw/openrisc/openrisc_sim.c
PowerPC Machines
-405 (ref405ep and taihu)
+405 (ref405ep)
L: qemu-...@nongnu.org
S: Orphan
F: hw/ppc/ppc405_boards.c
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 91b03115ee..c75a25daad 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -233,15 +233,6 @@ deprecated; use the new name ``dtb-randomness`` instead.
The new name
better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node.
-PPC 405 ``taihu`` machine (since 7.0)
-'
-
-The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
-except for some external periphery. However, the periphery of the ``taihu``
-machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
-been implemented), so there is not much value added by this board. Use the
-``ref405ep`` machine instead.
-
``pc-i440fx-1.4`` up to ``pc-i440fx-1.7`` (since 7.0)
'
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index 925e22016f..a4aa3dca69 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -668,6 +668,12 @@ Aspeed ``swift-bmc`` machine (removed in 7.0)
This machine was removed because it was unused. Alternative AST2500 based
OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
+ppc ``taihu`` machine (removed in 7.2)
+'
+
+This machine was removed because it was partially emulated and 405
+machines are very similar. Use the ``ref405ep`` machine instead.
+
linux-user mode CPUs
diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
index cfffbda24d..af3b3d9fa4 100644
--- a/docs/system/ppc/embedded.rst
+++ b/docs/system/ppc/embedded.rst
@@ -6,5 +6,4 @@ Embedded family boards
- ``ppce500`` generic paravirt e500 platform
- ``ref405ep`` ref405ep
- ``sam460ex`` aCube Sam460ex
-- ``taihu``taihu
- ``virtex-ml507`` Xilinx Virtex ML507 reference design
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index a66ad05e3a..1a4e7588c5 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -342,241 +342,9 @@ static const TypeInfo ref405ep_type = {
.class_init = ref405ep_class_init,
};
-/*/
-/* AMCC Taihu evaluation board */
-/* - PowerPC 405EP processor
- * - SDRAM 128 MB at 0x
- * - Boot flash 2 MB at 0xFFE0
- * - Application flash 32 MB at 0xFC00
- * - 2 serial ports
- * - 2 ethernet PHY
- * - 1 USB 1.1 device0x5000
- * - 1 LCD display 0x5010
- * - 1 CPLD 0x5010
- * - 1 I2C EEPROM
- * - 1 I2C thermal sensor
- * - a set of LEDs
- * - bit-bang SPI port using GPIOs
- * - 1 EBC interface connector 0 0x5020
- * - 1 cardbus controller + expansion slot.
- * - 1 PCI expansion slot.
- */
-typedef struct taihu_cpld_t taihu_cpld_t;
-struct taihu_cpld_t {
-uint8_t reg0;
-uint8_t reg1;
-};
-
-static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
-{
-taihu_cpld_t *cpld;
-uint32_t ret;
-
-cpld = opaque;
-switch (addr) {
-case 0x0:
-ret = cpld->reg0;
-break;
-case 0x1:
-ret = cpld->reg1;
-break;
-default:
-ret = 0;
-break;
-}
-
-return ret;
-}
-
-static void taihu_cpld_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
-{
-taihu_cpld_t *cpld;
-
-cpld = opaque;
-switch (addr) {
-case 0x0:
-/* Read only */
-break;
-case 0x1:
-cpld->reg1 = value;
-break;
-default:
-break;
-}
-}
-
-static const MemoryRegionOps taihu_cpld_ops = {
-.read = taihu_cpld_read,
-.write = taihu_cpld_write,
-.impl = {
-.min_access_size = 1,
-.max_access_size = 1,
-},
-.endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void taihu_cpld_reset (void *opaque)
-{
-taihu_cpld_t *cpld;
-
-cpld = opaque;
-cpld->reg0 = 0x01;
-cpld->reg1 =
[PULL 34/60] ppc/ppc405: Introduce a PPC405 SoC
From: Cédric Le Goater
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153904.485018-6-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 16
hw/ppc/ppc405_boards.c | 23 ---
hw/ppc/ppc405_uc.c | 40
3 files changed, 68 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 83f156f585..66dc21cdfe 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -25,6 +25,7 @@
#ifndef PPC405_H
#define PPC405_H
+#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x
@@ -62,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_SOC "ppc405-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
+
+struct Ppc405SoCState {
+/* Private */
+DeviceState parent_obj;
+
+/* Public */
+MemoryRegion ram_banks[2];
+hwaddr ram_bases[2], ram_sizes[2];
+
+MemoryRegion *dram_mr;
+hwaddr ram_size;
+};
+
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 381f39aa94..f029d6f415 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -57,6 +57,8 @@ struct Ppc405MachineState {
/* Private */
MachineState parent_obj;
/* Public */
+
+Ppc405SoCState soc;
};
/*/
@@ -232,11 +234,10 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
+Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
-MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
-hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -247,16 +248,16 @@ static void ppc405_init(MachineState *machine)
exit(EXIT_FAILURE);
}
-/* XXX: fix this */
-memory_region_init_alias(_memories[0], NULL, "ef405ep.ram.alias",
- machine->ram, 0, machine->ram_size);
-ram_bases[0] = 0;
-ram_sizes[0] = machine->ram_size;
-memory_region_init(_memories[1], NULL, "ef405ep.ram1", 0);
-ram_bases[1] = 0x;
-ram_sizes[1] = 0x;
+object_initialize_child(OBJECT(machine), "soc", >soc,
+TYPE_PPC405_SOC);
+object_property_set_uint(OBJECT(>soc), "ram-size",
+ machine->ram_size, _fatal);
+object_property_set_link(OBJECT(>soc), "dram",
+ OBJECT(machine->ram), _abort);
+qdev_realize(DEVICE(>soc), NULL, _fatal);
-cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
+ppc405->soc.ram_sizes,
, , kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6420c88d3..adadb3a0ae 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1530,3 +1531,42 @@ PowerPCCPU *ppc405ep_init(MemoryRegion
*address_space_mem,
return cpu;
}
+
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
+{
+Ppc405SoCState *s = PPC405_SOC(dev);
+
+/* Initialize only one bank */
+s->ram_bases[0] = 0;
+s->ram_sizes[0] = s->ram_size;
+memory_region_init_alias(>ram_banks[0], OBJECT(s),
+ "ppc405.sdram0", s->dram_mr,
+ s->ram_bases[0], s->ram_sizes[0]);
+}
+
+static Property ppc405_soc_properties[] = {
+DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = ppc405_soc_realize;
+dc->user_creatable = false;
+device_class_set_props(dc, ppc405_soc_properties);
+}
+
+static const TypeInfo ppc405_types[] = {
+
[PULL 46/60] ppc/ppc405: QOM'ify PLB
From: Cédric Le Goater
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 14 --
hw/ppc/ppc405_uc.c | 64 ++
hw/ppc/sam460ex.c | 4 ++-
3 files changed, 51 insertions(+), 31 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4140e811d5..cb34792daf 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+Ppc4xxDcrDeviceState parent_obj;
+
+uint32_t acr;
+uint32_t bear;
+uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -232,11 +243,10 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+Ppc405PlbState plb;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-void ppc4xx_plb_init(CPUPPCState *env);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e5604c3421..9ed3ce4ebe 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
-uint32_t acr;
-uint32_t bear;
-uint32_t besr;
-};
-
-static uint32_t dcr_read_plb (void *opaque, int dcrn)
+static uint32_t dcr_read_plb(void *opaque, int dcrn)
{
-ppc4xx_plb_t *plb;
+Ppc405PlbState *plb = opaque;
uint32_t ret;
-plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -180,11 +172,10 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
{
-ppc4xx_plb_t *plb;
+Ppc405PlbState *plb = opaque;
-plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,36 @@ static void dcr_write_plb (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *dev)
{
-ppc4xx_plb_t *plb;
+Ppc405PlbState *plb = PPC405_PLB(dev);
-plb = opaque;
plb->acr = 0x;
plb->bear = 0x;
plb->besr = 0x;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
+{
+Ppc405PlbState *plb = PPC405_PLB(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, _read_plb, _write_plb);
+ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, _read_plb, _write_plb);
+ppc4xx_dcr_register(dcr, PLB0_ACR, plb, _read_plb, _write_plb);
+ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, _read_plb, _write_plb);
+ppc4xx_dcr_register(dcr, PLB0_BESR, plb, _read_plb, _write_plb);
+ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, _read_plb, _write_plb);
+}
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
{
-ppc4xx_plb_t *plb;
-
-plb = g_new0(ppc4xx_plb_t, 1);
-ppc_dcr_register(env, PLB3A0_ACR, plb, _read_plb, _write_plb);
-ppc_dcr_register(env, PLB4A0_ACR, plb, _read_plb, _write_plb);
-ppc_dcr_register(env, PLB0_ACR, plb, _read_plb, _write_plb);
-ppc_dcr_register(env, PLB0_BEAR, plb, _read_plb, _write_plb);
-ppc_dcr_register(env, PLB0_BESR, plb, _read_plb, _write_plb);
-ppc_dcr_register(env, PLB4A1_ACR, plb, _read_plb, _write_plb);
-qemu_register_reset(ppc4xx_plb_reset, plb);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = ppc405_plb_realize;
+dc->reset = ppc405_plb_reset;
+/* Reason: only works as function of a ppc4xx SoC */
+dc->user_creatable = false;
}
/*/
@@ -1374,6 +1373,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", >opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", >pob, TYPE_PPC405_POB);
+
+object_initialize_child(obj, "plb", >plb, TYPE_PPC405_PLB);
}
static void ppc405_reset(void *opaque)
@@ -1405,7 +1406,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
/* PLB arbitrer */
-ppc4xx_plb_init(env);
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(>plb), >cpu, errp)) {
+return;
+}
/* PLB to OPB bridge */
if
[PULL 32/60] ppc/ppc405: Move devices under the ref405ep machine
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: BALATON Zoltan
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-4-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 96700be74d..f4794ba40c 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -230,13 +230,11 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
env->load_info = _info;
}
-static void ref405ep_init(MachineState *machine)
+static void ppc405_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
-DeviceState *dev;
-SysBusDevice *s;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
@@ -294,15 +292,6 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
}
-/* Register FPGA */
-ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
-/* Register NVRAM */
-dev = qdev_new("sysbus-m48t08");
-qdev_prop_set_int32(dev, "base-year", 1968);
-s = SYS_BUS_DEVICE(dev);
-sysbus_realize_and_unref(s, _fatal);
-sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
-
/* Load kernel and initrd using U-Boot images */
if (kernel_filename && machine->firmware) {
target_ulong kernel_base, initrd_base;
@@ -335,6 +324,23 @@ static void ref405ep_init(MachineState *machine)
}
}
+static void ref405ep_init(MachineState *machine)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+ppc405_init(machine);
+
+/* Register FPGA */
+ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+/* Register NVRAM */
+dev = qdev_new("sysbus-m48t08");
+qdev_prop_set_int32(dev, "base-year", 1968);
+s = SYS_BUS_DEVICE(dev);
+sysbus_realize_and_unref(s, _fatal);
+sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
+}
+
static void ref405ep_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -354,6 +360,7 @@ static void ppc405_machine_class_init(ObjectClass *oc, void
*data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "PPC405 generic machine";
+mc->init = ppc405_init;
mc->default_ram_size = 128 * MiB;
mc->default_ram_id = "ppc405.ram";
}
--
2.37.2
[PULL 27/60] ppc/pnv: user creatable pnv-phb for powernv10
Given that powernv9 and powernv10 uses the same pnv-phb backend, the logic to allow user created pnv-phbs for powernv10 is already in place. Let's flip the switch. Reviewed-by: Cédric Le Goater Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Message-Id: <20220811163950.578927-11-danielhb...@gmail.com> --- hw/ppc/pnv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c063d01f8d..354aa289d1 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2251,6 +2251,8 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) pmc->dt_power_mgt = pnv_dt_power_mgt; xfc->match_nvt = pnv10_xive_match_nvt; + +machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } static bool pnv_machine_get_hb(Object *obj, Error **errp) -- 2.37.2
[PULL 33/60] ppc/ppc405: Move SRAM under the ref405ep machine
From: Cédric Le Goater
It doesn't belong to the generic machine nor the SoC. Fix a typo in
the name while we are at it.
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153904.485018-5-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index f4794ba40c..381f39aa94 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -235,7 +235,6 @@ static void ppc405_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
-MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
@@ -260,11 +259,6 @@ static void ppc405_init(MachineState *machine)
cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
, , kernel_filename == NULL ? 0 : 1);
-/* allocate SRAM */
-memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
- _fatal);
-memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -328,9 +322,15 @@ static void ref405ep_init(MachineState *machine)
{
DeviceState *dev;
SysBusDevice *s;
+MemoryRegion *sram = g_new(MemoryRegion, 1);
ppc405_init(machine);
+/* allocate SRAM */
+memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE,
+ _fatal);
+memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
+
/* Register FPGA */
ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
/* Register NVRAM */
--
2.37.2
[PULL 45/60] ppc/ppc405: QOM'ify POB
From: Cédric Le Goater
POB is currently modeled as a simple DCR device.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<2bb1a89182523059ecb0e8d20c22a293534dec17.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 12 ++
hw/ppc/ppc405_uc.c | 56 ++
2 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d63c2acdc7..4140e811d5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+Ppc4xxDcrDeviceState parent_obj;
+
+uint32_t bear;
+uint32_t besr0;
+uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -220,6 +231,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2c482bc25c..e5604c3421 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
-uint32_t bear;
-uint32_t besr0;
-uint32_t besr1;
-};
-
-static uint32_t dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob(void *opaque, int dcrn)
{
-ppc4xx_pob_t *pob;
+Ppc405PobState *pob = opaque;
uint32_t ret;
-pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -266,11 +258,10 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
{
-ppc4xx_pob_t *pob;
+Ppc405PobState *pob = opaque;
-pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,34 @@ static void dcr_write_pob (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
{
-ppc4xx_pob_t *pob;
+Ppc405PobState *pob = PPC405_POB(dev);
-pob = opaque;
/* No error */
pob->bear = 0x;
pob->besr0 = 0x000;
pob->besr1 = 0x000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
+{
+Ppc405PobState *pob = PPC405_POB(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ppc4xx_dcr_register(dcr, POB0_BEAR, pob, _read_pob, _write_pob);
+ppc4xx_dcr_register(dcr, POB0_BESR0, pob, _read_pob, _write_pob);
+ppc4xx_dcr_register(dcr, POB0_BESR1, pob, _read_pob, _write_pob);
+}
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
{
-ppc4xx_pob_t *pob;
+DeviceClass *dc = DEVICE_CLASS(oc);
-pob = g_new0(ppc4xx_pob_t, 1);
-ppc_dcr_register(env, POB0_BEAR, pob, _read_pob, _write_pob);
-ppc_dcr_register(env, POB0_BESR0, pob, _read_pob, _write_pob);
-ppc_dcr_register(env, POB0_BESR1, pob, _read_pob, _write_pob);
-qemu_register_reset(ppc4xx_pob_reset, pob);
+dc->realize = ppc405_pob_realize;
+dc->reset = ppc405_pob_reset;
+/* Reason: only works as function of a ppc4xx SoC */
+dc->user_creatable = false;
}
/*/
@@ -1373,6 +1372,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", >ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", >opba, TYPE_PPC405_OPBA);
+
+object_initialize_child(obj, "pob", >pob, TYPE_PPC405_POB);
}
static void ppc405_reset(void *opaque)
@@ -1407,7 +1408,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
-ppc4xx_pob_init(env);
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(>pob), >cpu, errp)) {
+return;
+}
/* OBP arbitrer */
sbd = SYS_BUS_DEVICE(>opba);
@@ -1527,6 +1530,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+.name = TYPE_PPC405_POB,
+.parent = TYPE_PPC4xx_DCR_DEVICE,
+.instance_size = sizeof(Ppc405PobState),
+.class_init = ppc405_pob_class_init,
+}, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
--
2.37.2
[PULL 25/60] ppc/pnv: enable user created pnv-phb for powernv9
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-9-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb4_pec.c | 6 --
hw/ppc/pnv.c | 2 ++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 1f53ff77c5..17d9960aa1 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -167,7 +167,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
-if (phb->version == 3 && !defaults_enabled()) {
+if (!defaults_enabled()) {
return;
}
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 8dc363d69c..9871f462cd 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -146,8 +146,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
pec->num_phbs = pecc->num_phbs[pec->index];
/* Create PHBs if running with defaults */
-for (i = 0; i < pec->num_phbs; i++) {
-pnv_pec_default_phb_realize(pec, i, errp);
+if (defaults_enabled()) {
+for (i = 0; i < pec->num_phbs; i++) {
+pnv_pec_default_phb_realize(pec, i, errp);
+}
}
/* Initialize the XSCOM regions for the PEC registers */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c34967cac7..f45f02be4c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2213,6 +2213,8 @@ static void pnv_machine_power9_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->dt_power_mgt = pnv_dt_power_mgt;
+
+machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
--
2.37.2
[PULL 43/60] ppc/ppc405: QOM'ify EBC
From: Cédric Le Goater
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<51a0769ab605c5158f4f2f1c896725d5fe7a073b.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 17 -
hw/ppc/ppc405_uc.c | 62 --
hw/ppc/sam460ex.c | 4 ++-
3 files changed, 51 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c75e4c7cb5..82bf8dae93 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral controller */
+#define TYPE_PPC405_EBC "ppc405-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
+struct Ppc405EbcState {
+Ppc4xxDcrDeviceState parent_obj;
+
+uint32_t addr;
+uint32_t bcr[8];
+uint32_t bap[8];
+uint32_t bear;
+uint32_t besr0;
+uint32_t besr1;
+uint32_t cfg;
+};
+
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
@@ -192,12 +207,12 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+Ppc405EbcState ebc;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
-void ppc405_ebc_init(CPUPPCState *env);
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3845c0fec1..ff81fb3e20 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -393,28 +393,16 @@ static void ppc4xx_opba_init(hwaddr base)
/*/
/* Peripheral controller */
-typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
-struct ppc4xx_ebc_t {
-uint32_t addr;
-uint32_t bcr[8];
-uint32_t bap[8];
-uint32_t bear;
-uint32_t besr0;
-uint32_t besr1;
-uint32_t cfg;
-};
-
enum {
EBC0_CFGADDR = 0x012,
EBC0_CFGDATA = 0x013,
};
-static uint32_t dcr_read_ebc (void *opaque, int dcrn)
+static uint32_t dcr_read_ebc(void *opaque, int dcrn)
{
-ppc4xx_ebc_t *ebc;
+Ppc405EbcState *ebc = opaque;
uint32_t ret;
-ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ret = ebc->addr;
@@ -494,11 +482,10 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
{
-ppc4xx_ebc_t *ebc;
+Ppc405EbcState *ebc = opaque;
-ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ebc->addr = val;
@@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ebc_reset (void *opaque)
+static void ppc405_ebc_reset(DeviceState *dev)
{
-ppc4xx_ebc_t *ebc;
+Ppc405EbcState *ebc = PPC405_EBC(dev);
int i;
-ebc = opaque;
ebc->addr = 0x;
ebc->bap[0] = 0x7F8FFE80;
ebc->bcr[0] = 0xFFE28000;
@@ -572,16 +558,23 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x8040;
}
-void ppc405_ebc_init(CPUPPCState *env)
+static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
{
-ppc4xx_ebc_t *ebc;
-
-ebc = g_new0(ppc4xx_ebc_t, 1);
-qemu_register_reset(_reset, ebc);
-ppc_dcr_register(env, EBC0_CFGADDR,
- ebc, _read_ebc, _write_ebc);
-ppc_dcr_register(env, EBC0_CFGDATA,
- ebc, _read_ebc, _write_ebc);
+Ppc405EbcState *ebc = PPC405_EBC(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, _read_ebc, _write_ebc);
+ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, _read_ebc, _write_ebc);
+}
+
+static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = ppc405_ebc_realize;
+dc->reset = ppc405_ebc_reset;
+/* Reason: only works as function of a ppc4xx SoC */
+dc->user_creatable = false;
}
/*/
@@ -1378,6 +1371,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpio", >gpio, TYPE_PPC405_GPIO);
object_initialize_child(obj, "dma", >dma, TYPE_PPC405_DMA);
+
+object_initialize_child(obj, "ebc", >ebc, TYPE_PPC405_EBC);
}
static void ppc405_reset(void *opaque)
@@ -1444,7 +1439,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
s->do_dram_init);
/* External bus controller */
-ppc405_ebc_init(env);
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(>ebc), >cpu, errp)) {
+return;
+}
/* DMA
[PULL 29/60] ppc/pnv: fix QOM parenting of user creatable root ports
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy similar to what we have with default root
ports, i.e. the root port must be parented by the pnv-root-bus. To do
that we change the qom and bus parent of the root port during
root_port_realize(). The realize() is shared by the default root port
code path, so we can remove the code inside pnv_phb_attach_root_port()
that was adding the root port as a child of the bus as well.
After all that, remove pnv_phb_attach_root_port() and create the root
port explictly in the 'default_enabled()' case of pnv_phb_realize().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20220819094748.400578-3-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 47 ++-
1 file changed, 20 insertions(+), 27 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 4ea33fb6ba..7b11f1e8dd 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -62,29 +62,6 @@ static bool pnv_parent_fixup(Object *parent, BusState
*parent_bus,
return true;
}
-/*
- * Attach a root port device.
- *
- * 'index' will be used both as a PCIE slot value and to calculate
- * QOM id. 'chip_id' is going to be used as PCIE chassis for the
- * root port.
- */
-static void pnv_phb_attach_root_port(PCIHostState *pci)
-{
-PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
-const char *dev_id = DEVICE(root)->id;
-g_autofree char *default_id = NULL;
-int index;
-
-index = object_property_get_int(OBJECT(pci->bus), "phb-id", _fatal);
-default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index);
-
-object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
- OBJECT(root));
-
-pci_realize_and_unref(root, pci->bus, _fatal);
-}
-
/*
* User created devices won't have the initial setup that default
* devices have. This setup consists of assigning a parent device
@@ -180,11 +157,11 @@ static void pnv_phb_realize(DeviceState *dev, Error
**errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
-if (!defaults_enabled()) {
-return;
-}
+if (defaults_enabled()) {
+PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
-pnv_phb_attach_root_port(pci);
+pci_realize_and_unref(root, pci->bus, errp);
+}
}
static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
@@ -259,6 +236,11 @@ static void pnv_phb_root_port_realize(DeviceState *dev,
Error **errp)
Error *local_err = NULL;
int chip_id, index;
+/*
+ * 'index' will be used both as a PCIE slot value and to calculate
+ * QOM id. 'chip_id' is going to be used as PCIE chassis for the
+ * root port.
+ */
chip_id = object_property_get_int(OBJECT(bus), "chip-id", _fatal);
index = object_property_get_int(OBJECT(bus), "phb-id", _fatal);
@@ -266,6 +248,17 @@ static void pnv_phb_root_port_realize(DeviceState *dev,
Error **errp)
qdev_prop_set_uint8(dev, "chassis", chip_id);
qdev_prop_set_uint16(dev, "slot", index);
+/*
+ * User created root ports are QOM parented to one of
+ * the peripheral containers but it's already at the right
+ * parent bus. Change the QOM parent to be the same as the
+ * parent bus it's already assigned to.
+ */
+if (!pnv_parent_fixup(OBJECT(bus), BUS(bus), OBJECT(dev),
+ index, errp)) {
+return;
+}
+
rpc->parent_realize(dev, _err);
if (local_err) {
error_propagate(errp, local_err);
--
2.37.2
[PULL 28/60] ppc/pnv: consolidate pnv_parent_*_fixup() helpers
We have 2 helpers that amends the QOM and parent bus of a given object,
repectively. These 2 helpers are called together, and not by accident.
Due to QOM internals, doing an object_unparent() will result in the
device being removed from its parent bus. This means that changing the
QOM parent requires reassigning the parent bus again.
Create a single helper called pnv_parent_fixup(), documenting some of
the QOM specifics that we're dealing with the unparenting/parenting
mechanics, and handle both the QOM and the parent bus assignment.
Next patch will make use of this function to handle a case where we need
to change the QOM parent while keeping the same parent bus assigned
beforehand.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220819094748.400578-2-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 17d9960aa1..4ea33fb6ba 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -21,34 +21,45 @@
/*
- * Set the QOM parent of an object child. If the device state
- * associated with the child has an id, use it as QOM id. Otherwise
- * use object_typename[index] as QOM id.
+ * Set the QOM parent and parent bus of an object child. If the device
+ * state associated with the child has an id, use it as QOM id.
+ * Otherwise use object_typename[index] as QOM id.
+ *
+ * This helper does both operations at the same time because seting
+ * a new QOM child will erase the bus parent of the device. This happens
+ * because object_unparent() will call object_property_del_child(),
+ * which in turn calls the property release callback prop->release if
+ * it's defined. In our case this callback is set to
+ * object_finalize_child_property(), which was assigned during the
+ * first object_property_add_child() call. This callback will end up
+ * calling device_unparent(), and this function removes the device
+ * from its parent bus.
+ *
+ * The QOM and parent bus to be set aren´t necessarily related, so
+ * let's receive both as arguments.
*/
-static void pnv_parent_qom_fixup(Object *parent, Object *child, int index)
+static bool pnv_parent_fixup(Object *parent, BusState *parent_bus,
+ Object *child, int index,
+ Error **errp)
{
g_autofree char *default_id =
g_strdup_printf("%s[%d]", object_get_typename(child), index);
const char *dev_id = DEVICE(child)->id;
if (child->parent == parent) {
-return;
+return true;
}
object_ref(child);
object_unparent(child);
object_property_add_child(parent, dev_id ? dev_id : default_id, child);
object_unref(child);
-}
-
-static void pnv_parent_bus_fixup(DeviceState *parent, DeviceState *child,
- Error **errp)
-{
-BusState *parent_bus = qdev_get_parent_bus(parent);
-if (!qdev_set_parent_bus(child, parent_bus, errp)) {
-return;
+if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) {
+return false;
}
+
+return true;
}
/*
@@ -101,8 +112,10 @@ static bool pnv_phb_user_device_init(PnvPHB *phb, Error
**errp)
* correctly the device tree. pnv_xscom_dt() needs every
* PHB to be a child of the chip to build the DT correctly.
*/
-pnv_parent_qom_fixup(parent, OBJECT(phb), phb->phb_id);
-pnv_parent_bus_fixup(DEVICE(chip), DEVICE(phb), errp);
+if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)),
+ OBJECT(phb), phb->phb_id, errp)) {
+return false;
+}
return true;
}
--
2.37.2
[PULL 22/60] ppc/pnv: turn chip8->phbs[] into a PnvPHB* array
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is assigned during pnv_chip_power8_realize(),
while the user created needs to search which chip it belongs to.
Aside from that there shouldn't be any difference. Making the default
PHBs behave in line with the user created ones will make it easier to
re-introduce them later on. It will also make the code easier to follow
since we are dealing with them in equal manner.
The first step is to turn chip8->phbs[] into a PnvPHB3 pointer array.
This will allow us to assign user created PHBs into it later on. The way
we initilize the default case is now more in line with that would happen
with the user created case: the object is created, parented by the chip
because pnv_xscom_dt() relies on it, and then assigned to the array.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-6-danielhb...@gmail.com>
---
hw/ppc/pnv.c | 27 ++-
include/hw/ppc/pnv.h | 6 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 737dee4980..0208517f1a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -294,6 +294,13 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t
pir,
Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
{
if (phb->version == 3) {
+Pnv8Chip *chip8 = PNV8_CHIP(chip);
+
+phb->chip = chip;
+
+chip8->phbs[chip8->num_phbs] = phb;
+chip8->num_phbs++;
+
return OBJECT(chip);
} else {
/* phb4 support will be added later */
@@ -681,7 +688,7 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip,
Monitor *mon)
ics_pic_print_info(>psi.ics, mon);
for (i = 0; i < chip8->num_phbs; i++) {
-PnvPHB *phb = >phbs[i];
+PnvPHB *phb = chip8->phbs[i];
PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
pnv_phb3_msi_pic_print_info(>msis, mon);
@@ -1174,7 +1181,17 @@ static void pnv_chip_power8_instance_init(Object *obj)
chip8->num_phbs = pcc->num_phbs;
for (i = 0; i < chip8->num_phbs; i++) {
-object_initialize_child(obj, "phb[*]", >phbs[i], TYPE_PNV_PHB);
+Object *phb = object_new(TYPE_PNV_PHB);
+
+/*
+ * We need the chip to parent the PHB to allow the DT
+ * to build correctly (via pnv_xscom_dt()).
+ *
+ * TODO: the PHB should be parented by a PEC device that, at
+ * this moment, is not modelled powernv8/phb3.
+ */
+object_property_add_child(obj, "phb[*]", phb);
+chip8->phbs[i] = PNV_PHB(phb);
}
}
@@ -1290,7 +1307,7 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
/* PHB controllers */
for (i = 0; i < chip8->num_phbs; i++) {
-PnvPHB *phb = >phbs[i];
+PnvPHB *phb = chip8->phbs[i];
object_property_set_int(OBJECT(phb), "index", i, _fatal);
object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
@@ -1983,7 +2000,7 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
}
for (j = 0; j < chip8->num_phbs; j++) {
-PnvPHB *phb = >phbs[j];
+PnvPHB *phb = chip8->phbs[j];
PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
if (ics_valid_irq(>lsis, irq)) {
@@ -2022,7 +2039,7 @@ static void pnv_ics_resend(XICSFabric *xi)
ics_resend(>psi.ics);
for (j = 0; j < chip8->num_phbs; j++) {
-PnvPHB *phb = >phbs[j];
+PnvPHB *phb = chip8->phbs[j];
PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
ics_resend(>lsis);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index c44f357bce..9ef7e2d0dc 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -82,7 +82,11 @@ struct Pnv8Chip {
PnvHomer homer;
#define PNV8_CHIP_PHB3_MAX 4
-PnvPHB phbs[PNV8_CHIP_PHB3_MAX];
+/*
+ * The array is used to allow quick access to the phbs by
+ * pnv_ics_get_child() and pnv_ics_resend_child().
+ */
+PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
uint32_t num_phbs;
XICSFabric*xics;
--
2.37.2
[PULL 41/60] ppc/ppc405: QOM'ify GPIO
From: Cédric Le Goater
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h | 21 +++
hw/ppc/ppc405_uc.c | 50 ++---
hw/ppc/trace-events | 1 -
3 files changed, 45 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a5b493d3e7..21f6cb3585 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* GPIO */
+#define TYPE_PPC405_GPIO "ppc405-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
+struct Ppc405GpioState {
+SysBusDevice parent_obj;
+
+MemoryRegion io;
+uint32_t or;
+uint32_t tcr;
+uint32_t osrh;
+uint32_t osrl;
+uint32_t tsrh;
+uint32_t tsrl;
+uint32_t odr;
+uint32_t ir;
+uint32_t rr1;
+uint32_t isr1h;
+uint32_t isr1l;
+};
+
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
@@ -152,6 +172,7 @@ struct Ppc405SoCState {
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
+Ppc405GpioState gpio;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8ee0357ac3..3f4a5b36f5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -714,22 +714,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq
irqs[4])
/*/
/* GPIO */
-typedef struct ppc405_gpio_t ppc405_gpio_t;
-struct ppc405_gpio_t {
-MemoryRegion io;
-uint32_t or;
-uint32_t tcr;
-uint32_t osrh;
-uint32_t osrl;
-uint32_t tsrh;
-uint32_t tsrl;
-uint32_t odr;
-uint32_t ir;
-uint32_t rr1;
-uint32_t isr1h;
-uint32_t isr1l;
-};
-
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
trace_ppc405_gpio_read(addr, size);
@@ -748,20 +732,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc405_gpio_reset (void *opaque)
+static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
{
+Ppc405GpioState *s = PPC405_GPIO(dev);
+
+memory_region_init_io(>io, OBJECT(s), _gpio_ops, s, "gpio",
+ 0x38);
+sysbus_init_mmio(SYS_BUS_DEVICE(s), >io);
}
-static void ppc405_gpio_init(hwaddr base)
+static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
{
-ppc405_gpio_t *gpio;
-
-trace_ppc405_gpio_init(base);
+DeviceClass *dc = DEVICE_CLASS(oc);
-gpio = g_new0(ppc405_gpio_t, 1);
-memory_region_init_io(>io, NULL, _gpio_ops, gpio, "pgio",
0x038);
-memory_region_add_subregion(get_system_memory(), base, >io);
-qemu_register_reset(_gpio_reset, gpio);
+dc->realize = ppc405_gpio_realize;
+/* Reason: only works as function of a ppc4xx SoC */
+dc->user_creatable = false;
}
/*/
@@ -1414,6 +1400,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpt", >gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", >ocm, TYPE_PPC405_OCM);
+
+object_initialize_child(obj, "gpio", >gpio, TYPE_PPC405_GPIO);
}
static void ppc405_reset(void *opaque)
@@ -1492,8 +1480,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2));
+
/* GPIO */
-ppc405_gpio_init(0xef600700);
+sbd = SYS_BUS_DEVICE(>gpio);
+if (!sysbus_realize(sbd, errp)) {
+return;
+}
+sysbus_mmio_map(sbd, 0, 0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
@@ -1555,6 +1548,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+.name = TYPE_PPC405_GPIO,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(Ppc405GpioState),
+.class_init = ppc405_gpio_class_init,
+}, {
.name = TYPE_PPC405_OCM,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405OcmState),
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 8d35521bf7..69a95f9f57 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -165,7 +165,6 @@ opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%"
PRIx64 " size %d = 0x%" PRIx64
-ppc405_gpio_init(uint64_t addr)
[PULL 19/60] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so. Unifying the root ports
presents a clear user QOL change when we enable user created devices back.
The buses objects, aside from having a different QOM name, is transparent
to the user;
- we leave a door opened in case we want to increase the root port limit
for phb4/5 later on without having to deal with phb3 code.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-3-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb4.c | 51 ++
include/hw/pci-host/pnv_phb4.h | 10 +++
2 files changed, 61 insertions(+)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index b98c394713..824e1a73fb 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1551,6 +1551,12 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
>pci_mmio, >pci_io,
0, 4, TYPE_PNV_PHB4_ROOT_BUS);
+
+object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id,
+_abort);
+object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id,
+_abort);
+
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
}
@@ -1708,10 +1714,55 @@ static const TypeInfo pnv_phb5_type_info = {
.instance_size = sizeof(PnvPHB4),
};
+static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
+uint64_t value = 0;
+
+if (strcmp(name, "phb-id") == 0) {
+value = bus->phb_id;
+} else {
+value = bus->chip_id;
+}
+
+visit_type_size(v, name, , errp);
+}
+
+static void pnv_phb4_root_bus_set_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+
+{
+PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj);
+uint64_t value;
+
+if (!visit_type_size(v, name, , errp)) {
+return;
+}
+
+if (strcmp(name, "phb-id") == 0) {
+bus->phb_id = value;
+} else {
+bus->chip_id = value;
+}
+}
+
static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
+object_class_property_add(klass, "phb-id", "int",
+ pnv_phb4_root_bus_get_prop,
+ pnv_phb4_root_bus_set_prop,
+ NULL, NULL);
+
+object_class_property_add(klass, "chip-id", "int",
+ pnv_phb4_root_bus_get_prop,
+ pnv_phb4_root_bus_set_prop,
+ NULL, NULL);
+
/*
* PHB4 has only a single root complex. Enforce the limit on the
* parent bus
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 20aa4819d3..50d4faa001 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -45,7 +45,17 @@ typedef struct PnvPhb4DMASpace {
QLIST_ENTRY(PnvPhb4DMASpace) list;
} PnvPhb4DMASpace;
+/*
+ * PHB4 PCIe Root Bus
+ */
#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
+struct PnvPHB4RootBus {
+PCIBus parent;
+
+uint32_t chip_id;
+uint32_t phb_id;
+};
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
/*
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
--
2.37.2
[PULL 24/60] ppc/pnv: add PHB4 helpers for user created pnv-phb
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
reverted by commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5}
devices". We'll use it to determine the appropriate PEC for a given user
created pnv-phb that uses a PHB4 backend.
This is done during realize() time, in pnv_phb_user_device_init().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-8-danielhb...@gmail.com>
---
hw/ppc/pnv.c | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 9ce1ae7752..c34967cac7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -281,6 +281,34 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t
pir,
g_free(reg);
}
+static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
+ Error **errp)
+{
+Pnv9Chip *chip9 = PNV9_CHIP(chip);
+int chip_id = phb->chip_id;
+int index = phb->phb_id;
+int i, j;
+
+for (i = 0; i < chip->num_pecs; i++) {
+/*
+ * For each PEC, check the amount of phbs it supports
+ * and see if the given phb4 index matches an index.
+ */
+PnvPhb4PecState *pec = >pecs[i];
+
+for (j = 0; j < pec->num_phbs; j++) {
+if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
+return pec;
+}
+}
+}
+error_setg(errp,
+ "pnv-phb4 chip-id %d index %d didn't match any existing PEC",
+ chip_id, index);
+
+return NULL;
+}
+
/*
* Adds a PnvPHB to the chip. Returns the parent obj of the
* PHB which varies with each version (phb version 3 is parented
@@ -302,10 +330,11 @@ Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb,
Error **errp)
chip8->num_phbs++;
return OBJECT(chip);
-} else {
-/* phb4 support will be added later */
-return NULL;
}
+
+phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp);
+
+return OBJECT(phb->pec);
}
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
--
2.37.2
[PULL 20/60] ppc/pnv: set root port chassis and slot using Bus properties
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have access to the PHB phb-id/chip-id
values.
In earlier patches we've added phb-id and chip-id to pnv-phb-root-bus
objects. We're now able to use the bus to retrieve them. The bus is
reachable for both user created and default devices, so we're changing
all the code paths. This also allow us to validate these changes with
the existing default devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-4-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index c47ed92462..826c0c144e 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -25,21 +25,19 @@
* QOM id. 'chip_id' is going to be used as PCIE chassis for the
* root port.
*/
-static void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
+static void pnv_phb_attach_root_port(PCIHostState *pci)
{
PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
-g_autofree char *default_id = g_strdup_printf("%s[%d]",
- TYPE_PNV_PHB_ROOT_PORT,
- index);
const char *dev_id = DEVICE(root)->id;
+g_autofree char *default_id = NULL;
+int index;
+
+index = object_property_get_int(OBJECT(pci->bus), "phb-id", _fatal);
+default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index);
object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
OBJECT(root));
-/* Set unique chassis/slot values for the root port */
-qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
-qdev_prop_set_uint16(DEVICE(root), "slot", index);
-
pci_realize_and_unref(root, pci->bus, _fatal);
}
@@ -93,7 +91,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
-pnv_phb_attach_root_port(pci, phb->phb_id, phb->chip_id);
+pnv_phb_attach_root_port(pci);
}
static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
@@ -162,9 +160,18 @@ static void pnv_phb_root_port_realize(DeviceState *dev,
Error **errp)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
+PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev));
PCIDevice *pci = PCI_DEVICE(dev);
uint16_t device_id = 0;
Error *local_err = NULL;
+int chip_id, index;
+
+chip_id = object_property_get_int(OBJECT(bus), "chip-id", _fatal);
+index = object_property_get_int(OBJECT(bus), "phb-id", _fatal);
+
+/* Set unique chassis/slot values for the root port */
+qdev_prop_set_uint8(dev, "chassis", chip_id);
+qdev_prop_set_uint16(dev, "slot", index);
rpc->parent_realize(dev, _err);
if (local_err) {
--
2.37.2
[PULL 35/60] ppc/ppc405: Start QOMification of the SoC
From: Cédric Le Goater
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153904.485018-7-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 12 ++--
hw/ppc/ppc405_boards.c | 12 ++--
hw/ppc/ppc405_uc.c | 124 -
3 files changed, 71 insertions(+), 77 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 66dc21cdfe..dc862bc861 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -73,9 +73,14 @@ struct Ppc405SoCState {
/* Public */
MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2];
+bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
+
+uint32_t sysclk;
+PowerPCCPU *cpu;
+DeviceState *uic;
};
/* PowerPC 405 core */
@@ -84,11 +89,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t
ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
-MemoryRegion ram_memories[2],
-hwaddr ram_bases[2],
-hwaddr ram_sizes[2],
-uint32_t sysclk, DeviceState **uicdev,
-int do_init);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index f029d6f415..b93e85b5d9 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -237,9 +237,7 @@ static void ppc405_init(MachineState *machine)
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
-PowerPCCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
-DeviceState *uicdev;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -254,12 +252,12 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, _fatal);
object_property_set_link(OBJECT(>soc), "dram",
OBJECT(machine->ram), _abort);
+object_property_set_bool(OBJECT(>soc), "dram-init",
+ kernel_filename != NULL, _abort);
+object_property_set_uint(OBJECT(>soc), "sys-clk", ,
+ _abort);
qdev_realize(DEVICE(>soc), NULL, _fatal);
-cpu = ppc405ep_init(sysmem, ppc405->soc.ram_banks, ppc405->soc.ram_bases,
-ppc405->soc.ram_sizes,
-, , kernel_filename == NULL ? 0 : 1);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -315,7 +313,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
-boot_from_kernel(machine, cpu);
+boot_from_kernel(machine, ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index adadb3a0ae..c05ab60436 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1432,121 +1432,118 @@ static void ppc405ep_cpc_init (CPUPPCState *env,
clk_setup_t clk_setup[8],
#endif
}
-PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
-MemoryRegion ram_memories[2],
-hwaddr ram_bases[2],
-hwaddr ram_sizes[2],
-uint32_t sysclk, DeviceState **uicdevp,
-int do_init)
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
+Ppc405SoCState *s = PPC405_SOC(dev);
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
-PowerPCCPU *cpu;
CPUPPCState *env;
-DeviceState *uicdev;
-SysBusDevice *uicsbd;
memset(clk_setup, 0, sizeof(clk_setup));
+
/* init CPUs */
-cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
+s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
_setup[PPC405EP_CPU_CLK],
- _clk_setup, sysclk);
-env = >env;
+ _clk_setup, s->sysclk);
+env = >cpu->env;
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
-/* Internal devices init */
-/* Memory mapped devices registers */
+
+/* CPU control */
+ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+
/* PLB arbitrer */
ppc4xx_plb_init(env);
+
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
+
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
+
/* Universal interrupt controller */
-uicdev = qdev_new(TYPE_PPC_UIC);
-
[PULL 17/60] ppc/pnv: move attach_root_port helper to pnv-phb.c
The helper is only used in this file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-13-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 24
hw/ppc/pnv.c | 25 -
include/hw/ppc/pnv.h | 1 -
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index cc15a949c9..c47ed92462 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -18,6 +18,30 @@
#include "hw/qdev-properties.h"
#include "qom/object.h"
+/*
+ * Attach a root port device.
+ *
+ * 'index' will be used both as a PCIE slot value and to calculate
+ * QOM id. 'chip_id' is going to be used as PCIE chassis for the
+ * root port.
+ */
+static void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
+{
+PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
+g_autofree char *default_id = g_strdup_printf("%s[%d]",
+ TYPE_PNV_PHB_ROOT_PORT,
+ index);
+const char *dev_id = DEVICE(root)->id;
+
+object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
+ OBJECT(root));
+
+/* Set unique chassis/slot values for the root port */
+qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
+qdev_prop_set_uint16(DEVICE(root), "slot", index);
+
+pci_realize_and_unref(root, pci->bus, _fatal);
+}
static void pnv_phb_realize(DeviceState *dev, Error **errp)
{
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6b94c373d1..758e36132d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1188,31 +1188,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error
**errp)
}
}
-/*
- * Attach a root port device.
- *
- * 'index' will be used both as a PCIE slot value and to calculate
- * QOM id. 'chip_id' is going to be used as PCIE chassis for the
- * root port.
- */
-void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
-{
-PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
-g_autofree char *default_id = g_strdup_printf("%s[%d]",
- TYPE_PNV_PHB_ROOT_PORT,
- index);
-const char *dev_id = DEVICE(root)->id;
-
-object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
- OBJECT(root));
-
-/* Set unique chassis/slot values for the root port */
-qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
-qdev_prop_set_uint16(DEVICE(root), "slot", index);
-
-pci_realize_and_unref(root, pci->bus, _fatal);
-}
-
static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 0eda47da0c..290adac76c 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -193,7 +193,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.37.2
[PULL 18/60] ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via the 'index' and 'chip-id' of the
pnv_phb_attach_root_port() helper.
If we want to implement user created root ports we have a problem. The
user created root port will not be aware of which PHB it belongs to,
unless we're willing to violate QOM best practices and access the PHB
via dev->parent_bus->parent. What we can do is to access the root bus
parent bus.
Since we're already assigning the root port as QOM child of the bus, and
the bus is initiated using PHB properties, let's add phb-id and chip-id
as properties of the bus. This will allow us trivial access to them, for
both user-created and default root ports, without doing anything too
shady with QOM.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-2-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb3.c | 50 ++
include/hw/pci-host/pnv_phb3.h | 9 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index d4c04a281a..af8575c007 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1006,6 +1006,11 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
>pci_mmio, >pci_io,
0, 4, TYPE_PNV_PHB3_ROOT_BUS);
+object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id,
+_abort);
+object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id,
+_abort);
+
pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
}
@@ -1105,10 +1110,55 @@ static const TypeInfo pnv_phb3_type_info = {
.instance_init = pnv_phb3_instance_init,
};
+static void pnv_phb3_root_bus_get_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj);
+uint64_t value = 0;
+
+if (strcmp(name, "phb-id") == 0) {
+value = bus->phb_id;
+} else {
+value = bus->chip_id;
+}
+
+visit_type_size(v, name, , errp);
+}
+
+static void pnv_phb3_root_bus_set_prop(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+
+{
+PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj);
+uint64_t value;
+
+if (!visit_type_size(v, name, , errp)) {
+return;
+}
+
+if (strcmp(name, "phb-id") == 0) {
+bus->phb_id = value;
+} else {
+bus->chip_id = value;
+}
+}
+
static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
+object_class_property_add(klass, "phb-id", "int",
+ pnv_phb3_root_bus_get_prop,
+ pnv_phb3_root_bus_set_prop,
+ NULL, NULL);
+
+object_class_property_add(klass, "chip-id", "int",
+ pnv_phb3_root_bus_get_prop,
+ pnv_phb3_root_bus_set_prop,
+ NULL, NULL);
+
/*
* PHB3 has only a single root complex. Enforce the limit on the
* parent bus
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index bff69201d9..4854f6d2f6 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -104,9 +104,16 @@ struct PnvPBCQState {
};
/*
- * PHB3 PCIe Root port
+ * PHB3 PCIe Root Bus
*/
#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root"
+struct PnvPHB3RootBus {
+PCIBus parent;
+
+uint32_t chip_id;
+uint32_t phb_id;
+};
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3RootBus, PNV_PHB3_ROOT_BUS)
/*
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
--
2.37.2
[PULL 23/60] ppc/pnv: enable user created pnv-phb for powernv8
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-7-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 9 +++--
hw/ppc/pnv.c | 32 ++--
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 5dc44f45d1..1f53ff77c5 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -17,6 +17,7 @@
#include "hw/ppc/pnv.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
+#include "sysemu/sysemu.h"
/*
@@ -166,6 +167,10 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
+if (phb->version == 3 && !defaults_enabled()) {
+return;
+}
+
pnv_phb_attach_root_port(pci);
}
@@ -201,7 +206,7 @@ static void pnv_phb_class_init(ObjectClass *klass, void
*data)
dc->realize = pnv_phb_realize;
device_class_set_props(dc, pnv_phb_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
-dc->user_creatable = false;
+dc->user_creatable = true;
}
static void pnv_phb_root_port_reset(DeviceState *dev)
@@ -292,7 +297,7 @@ static void pnv_phb_root_port_class_init(ObjectClass
*klass, void *data)
device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
>parent_reset);
dc->reset = _phb_root_port_reset;
-dc->user_creatable = false;
+dc->user_creatable = true;
k->vendor_id = PCI_VENDOR_ID_IBM;
/* device_id will be written during realize() */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0208517f1a..9ce1ae7752 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1178,20 +1178,22 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "homer", >homer, TYPE_PNV8_HOMER);
-chip8->num_phbs = pcc->num_phbs;
-
-for (i = 0; i < chip8->num_phbs; i++) {
-Object *phb = object_new(TYPE_PNV_PHB);
-
-/*
- * We need the chip to parent the PHB to allow the DT
- * to build correctly (via pnv_xscom_dt()).
- *
- * TODO: the PHB should be parented by a PEC device that, at
- * this moment, is not modelled powernv8/phb3.
- */
-object_property_add_child(obj, "phb[*]", phb);
-chip8->phbs[i] = PNV_PHB(phb);
+if (defaults_enabled()) {
+chip8->num_phbs = pcc->num_phbs;
+
+for (i = 0; i < chip8->num_phbs; i++) {
+Object *phb = object_new(TYPE_PNV_PHB);
+
+/*
+ * We need the chip to parent the PHB to allow the DT
+ * to build correctly (via pnv_xscom_dt()).
+ *
+ * TODO: the PHB should be parented by a PEC device that, at
+ * this moment, is not modelled powernv8/phb3.
+ */
+object_property_add_child(obj, "phb[*]", phb);
+chip8->phbs[i] = PNV_PHB(phb);
+}
}
}
@@ -2155,6 +2157,8 @@ static void pnv_machine_power8_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+
+machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
--
2.37.2
[PULL 31/60] ppc/ppc405: Introduce a PPC405 generic machine
From: Cédric Le Goater
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Reviewed-by: BALATON Zoltan
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-3-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1a4e7588c5..96700be74d 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -50,6 +50,15 @@
#define USE_FLASH_BIOS
+#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
+
+struct Ppc405MachineState {
+/* Private */
+MachineState parent_obj;
+/* Public */
+};
+
/*/
/* PPC405EP reference board (IBM) */
/* Standalone board with:
@@ -332,18 +341,34 @@ static void ref405ep_class_init(ObjectClass *oc, void
*data)
mc->desc = "ref405ep";
mc->init = ref405ep_init;
-mc->default_ram_size = 0x0800;
-mc->default_ram_id = "ef405ep.ram";
}
static const TypeInfo ref405ep_type = {
.name = MACHINE_TYPE_NAME("ref405ep"),
-.parent = TYPE_MACHINE,
+.parent = TYPE_PPC405_MACHINE,
.class_init = ref405ep_class_init,
};
+static void ppc405_machine_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+
+mc->desc = "PPC405 generic machine";
+mc->default_ram_size = 128 * MiB;
+mc->default_ram_id = "ppc405.ram";
+}
+
+static const TypeInfo ppc405_machine_type = {
+.name = TYPE_PPC405_MACHINE,
+.parent = TYPE_MACHINE,
+.instance_size = sizeof(Ppc405MachineState),
+.class_init = ppc405_machine_class_init,
+.abstract = true,
+};
+
static void ppc405_machine_init(void)
{
+type_register_static(_machine_type);
type_register_static(_type);
}
--
2.37.2
[PULL 08/60] ppc/pnv: turn PnvPHB3 into a PnvPHB backend
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to access the PCI bus, so a
phb_base pointer is added to allow access to the parent PnvPHB. The
PnvPHB3 root port will now be connected to a PnvPHB object.
In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB
objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3
backend from the PnvPHB child. A global property is added in
pnv_machine_power8_class_init() to ensure that all PnvPHBs are created
with phb->version = 3.
After all these changes we're still able to boot a powernv8 machine with
default settings. The real gain will come with user created PnvPHB
devices, coming up next.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-4-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb3.c | 27 +--
hw/ppc/pnv.c | 21 +++--
include/hw/pci-host/pnv_phb3.h | 5 -
include/hw/ppc/pnv.h | 3 ++-
4 files changed, 26 insertions(+), 30 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 058cbab555..ad9e983fe9 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -11,6 +11,7 @@
#include "qapi/visitor.h"
#include "qapi/error.h"
#include "hw/pci-host/pnv_phb3_regs.h"
+#include "hw/pci-host/pnv_phb.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
@@ -26,7 +27,7 @@
static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb)
{
-PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
uint8_t bus, devfn;
@@ -590,7 +591,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t
val, unsigned size)
uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
{
PnvPHB3 *phb = opaque;
-PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t val;
if ((off & 0xfffc) == PHB_CONFIG_DATA) {
@@ -1011,7 +1012,6 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
static void pnv_phb3_realize(DeviceState *dev, Error **errp)
{
PnvPHB3 *phb = PNV_PHB3(dev);
-PCIHostState *pci = PCI_HOST_BRIDGE(dev);
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@@ -1056,11 +1056,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error
**errp)
/* Controller Registers */
memory_region_init_io(>mr_regs, OBJECT(phb), _phb3_reg_ops, phb,
"phb3-regs", 0x1000);
-
-pnv_phb3_bus_init(dev, phb);
-
-pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
- phb->phb_id, phb->chip_id);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
@@ -1085,38 +1080,26 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
pnv_phb3_check_all_m64s(phb);
}
-static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge,
- PCIBus *rootbus)
-{
-PnvPHB3 *phb = PNV_PHB3(host_bridge);
-
-snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
- phb->chip_id, phb->phb_id);
-return phb->bus_path;
-}
-
static Property pnv_phb3_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
+DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_phb3_class_init(ObjectClass *klass, void *data)
{
-PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
-hc->root_bus_path = pnv_phb3_root_bus_path;
dc->realize = pnv_phb3_realize;
device_class_set_props(dc, pnv_phb3_properties);
-set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = false;
}
static const TypeInfo pnv_phb3_type_info = {
.name = TYPE_PNV_PHB3,
-.parent= TYPE_PCIE_HOST_BRIDGE,
+.parent= TYPE_DEVICE,
.instance_size = sizeof(PnvPHB3),
.class_init= pnv_phb3_class_init,
.instance_init = pnv_phb3_instance_init,
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0c3aad430b..5b60735c7a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -43,6 +43,7 @@
#include "hw/ipmi/ipmi.h"
#include "target/ppc/mmu-hash64.h"
#include "hw/pci/msi.h"
+#include "hw/pci-host/pnv_phb.h"
#include "hw/ppc/xics.h"
#include "hw/qdev-properties.h"
@@ -660,7 +661,8 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip,
Monitor *mon)
ics_pic_print_info(>psi.ics,
[PULL 21/60] ppc/pnv: add helpers for pnv-phb user devices
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs, matching them with default
pnv-phbs.
A new helper pnv_phb_user_device_init() is created to handle
user-created devices setup. We're going to call it inside
pnv_phb_realize() in case we're realizing an user created device. This
will centralize all user device realated in a single spot, leaving the
realize functions of the phb3/phb4 backends untouched.
Another helper called pnv_chip_add_phb() was added to handle the
particularities of each chip version when adding a new PHB.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-5-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 75 +++
hw/ppc/pnv.c | 20
include/hw/ppc/pnv.h | 1 +
3 files changed, 96 insertions(+)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 826c0c144e..5dc44f45d1 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -18,6 +18,38 @@
#include "hw/qdev-properties.h"
#include "qom/object.h"
+
+/*
+ * Set the QOM parent of an object child. If the device state
+ * associated with the child has an id, use it as QOM id. Otherwise
+ * use object_typename[index] as QOM id.
+ */
+static void pnv_parent_qom_fixup(Object *parent, Object *child, int index)
+{
+g_autofree char *default_id =
+g_strdup_printf("%s[%d]", object_get_typename(child), index);
+const char *dev_id = DEVICE(child)->id;
+
+if (child->parent == parent) {
+return;
+}
+
+object_ref(child);
+object_unparent(child);
+object_property_add_child(parent, dev_id ? dev_id : default_id, child);
+object_unref(child);
+}
+
+static void pnv_parent_bus_fixup(DeviceState *parent, DeviceState *child,
+ Error **errp)
+{
+BusState *parent_bus = qdev_get_parent_bus(parent);
+
+if (!qdev_set_parent_bus(child, parent_bus, errp)) {
+return;
+}
+}
+
/*
* Attach a root port device.
*
@@ -41,6 +73,39 @@ static void pnv_phb_attach_root_port(PCIHostState *pci)
pci_realize_and_unref(root, pci->bus, _fatal);
}
+/*
+ * User created devices won't have the initial setup that default
+ * devices have. This setup consists of assigning a parent device
+ * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent
+ * of the PHB.
+ */
+static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp)
+{
+PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
+Object *parent = NULL;
+
+if (!chip) {
+error_setg(errp, "invalid chip id: %d", phb->chip_id);
+return false;
+}
+
+parent = pnv_chip_add_phb(chip, phb, errp);
+if (!parent) {
+return false;
+}
+
+/*
+ * Reparent user created devices to the chip to build
+ * correctly the device tree. pnv_xscom_dt() needs every
+ * PHB to be a child of the chip to build the DT correctly.
+ */
+pnv_parent_qom_fixup(parent, OBJECT(phb), phb->phb_id);
+pnv_parent_bus_fixup(DEVICE(chip), DEVICE(phb), errp);
+
+return true;
+}
+
static void pnv_phb_realize(DeviceState *dev, Error **errp)
{
PnvPHB *phb = PNV_PHB(dev);
@@ -74,6 +139,16 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
+/*
+ * Handle user created devices. User devices will not have a
+ * pointer to a chip (PHB3) and a PEC (PHB4/5).
+ */
+if (!phb->chip && !phb->pec) {
+if (!pnv_phb_user_device_init(phb, errp)) {
+return;
+}
+}
+
if (phb->version == 3) {
object_property_set_link(phb->backend, "chip",
OBJECT(phb->chip), errp);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 758e36132d..737dee4980 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -281,6 +281,26 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t
pir,
g_free(reg);
}
+/*
+ * Adds a PnvPHB to the chip. Returns the parent obj of the
+ * PHB which varies with each version (phb version 3 is parented
+ * by the chip, version 4 and 5 are parented by the PEC
+ * device).
+ *
+ * TODO: for version 3 we're still parenting the PHB with the
+ * chip. We should parent with a (so far not implemented)
+ * PHB3 PEC device.
+ */
+Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
+{
+if (phb->version == 3) {
+return OBJECT(chip);
+} else {
+/* phb4 support will be added later */
+return NULL;
+}
+}
+
static void pnv_chip_power8_dt_populate(PnvChip *chip, void
[PULL 16/60] ppc/pnv: remove PnvPHB4.version
It's unused.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-12-danielhb...@gmail.com>
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 61a0cb9989..20aa4819d3 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -77,8 +77,6 @@ struct PnvPHB4 {
uint32_t chip_id;
uint32_t phb_id;
-uint64_t version;
-
/* The owner PEC */
PnvPhb4PecState *pec;
--
2.37.2
[PULL 06/60] ppc/pnv: add PHB3 bus init helper
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pnv_phb3_bus_init() helper will be used by the parent to init
the bus when using the PHB3 backend.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-2-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb3.c | 39 --
include/hw/pci-host/pnv_phb3.h | 1 +
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index d58d3c1701..058cbab555 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
}
+void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
+{
+PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+
+/*
+ * PHB3 doesn't support IO space. However, qemu gets very upset if
+ * we don't have an IO region to anchor IO BARs onto so we just
+ * initialize one which we never hook up to anything
+ */
+memory_region_init(>pci_io, OBJECT(phb), "pci-io", 0x1);
+memory_region_init(>pci_mmio, OBJECT(phb), "pci-mmio",
+ PCI_MMIO_TOTAL_SIZE);
+
+pci->bus = pci_register_root_bus(dev,
+ dev->id ? dev->id : NULL,
+ pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
+ >pci_mmio, >pci_io,
+ 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
+
+pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
+}
+
static void pnv_phb3_realize(DeviceState *dev, Error **errp)
{
PnvPHB3 *phb = PNV_PHB3(dev);
@@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error
**errp)
memory_region_init_io(>mr_regs, OBJECT(phb), _phb3_reg_ops, phb,
"phb3-regs", 0x1000);
-/*
- * PHB3 doesn't support IO space. However, qemu gets very upset if
- * we don't have an IO region to anchor IO BARs onto so we just
- * initialize one which we never hook up to anything
- */
-memory_region_init(>pci_io, OBJECT(phb), "pci-io", 0x1);
-memory_region_init(>pci_mmio, OBJECT(phb), "pci-mmio",
- PCI_MMIO_TOTAL_SIZE);
-
-pci->bus = pci_register_root_bus(dev,
- dev->id ? dev->id : NULL,
- pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
- >pci_mmio, >pci_io,
- 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
-
-pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
+pnv_phb3_bus_init(dev, phb);
pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
phb->phb_id, phb->chip_id);
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index af6ec83cf6..1375f18fc1 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off,
unsigned size);
void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
void pnv_phb3_update_regions(PnvPHB3 *phb);
void pnv_phb3_remap_irqs(PnvPHB3 *phb);
+void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
#endif /* PCI_HOST_PNV_PHB3_H */
--
2.37.2
[PULL 26/60] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-10-danielhb...@gmail.com>
---
hw/ppc/pnv.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f45f02be4c..c063d01f8d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -284,17 +284,30 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t
pir,
static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
Error **errp)
{
-Pnv9Chip *chip9 = PNV9_CHIP(chip);
+PnvPHB *phb_base = phb->phb_base;
+PnvPhb4PecState *pecs = NULL;
int chip_id = phb->chip_id;
int index = phb->phb_id;
int i, j;
+if (phb_base->version == 4) {
+Pnv9Chip *chip9 = PNV9_CHIP(chip);
+
+pecs = chip9->pecs;
+} else if (phb_base->version == 5) {
+Pnv10Chip *chip10 = PNV10_CHIP(chip);
+
+pecs = chip10->pecs;
+} else {
+g_assert_not_reached();
+}
+
for (i = 0; i < chip->num_pecs; i++) {
/*
* For each PEC, check the amount of phbs it supports
* and see if the given phb4 index matches an index.
*/
-PnvPhb4PecState *pec = >pecs[i];
+PnvPhb4PecState *pec = [i];
for (j = 0; j < pec->num_phbs; j++) {
if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
--
2.37.2
[PULL 13/60] ppc/pnv: remove pnv-phb4-root-port
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-9-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 4 +-
hw/pci-host/pnv_phb4.c | 85 --
hw/pci-host/pnv_phb4_pec.c | 4 +-
hw/ppc/pnv.c | 2 +
include/hw/pci-host/pnv_phb4.h | 9
5 files changed, 6 insertions(+), 98 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index cdddc6a389..da729e89e7 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -38,11 +38,11 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 5:
phb_typename = g_strdup(TYPE_PNV_PHB5);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
default:
g_assert_not_reached();
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 144c437025..b98c394713 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1725,94 +1725,9 @@ static const TypeInfo pnv_phb4_root_bus_info = {
.class_init = pnv_phb4_root_bus_class_init,
};
-static void pnv_phb4_root_port_reset(DeviceState *dev)
-{
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-PCIDevice *d = PCI_DEVICE(dev);
-uint8_t *conf = d->config;
-
-rpc->parent_reset(dev);
-
-pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
- PCI_IO_RANGE_MASK & 0xff);
-pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
- PCI_IO_RANGE_MASK & 0xff);
-pci_set_word(conf + PCI_MEMORY_BASE, 0);
-pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
-pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
-pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
-pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
-pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0x);
-pci_config_set_interrupt_pin(conf, 0);
-}
-
-static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
-{
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-Error *local_err = NULL;
-
-rpc->parent_realize(dev, _err);
-if (local_err) {
-error_propagate(errp, local_err);
-return;
-}
-}
-
-static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
-
-dc->desc = "IBM PHB4 PCIE Root Port";
-dc->user_creatable = false;
-
-device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
->parent_realize);
-device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
- >parent_reset);
-
-k->vendor_id = PCI_VENDOR_ID_IBM;
-k->device_id = PNV_PHB4_DEVICE_ID;
-k->revision = 0;
-
-rpc->exp_offset = 0x48;
-rpc->aer_offset = 0x100;
-
-dc->reset = _phb4_root_port_reset;
-}
-
-static const TypeInfo pnv_phb4_root_port_info = {
-.name = TYPE_PNV_PHB4_ROOT_PORT,
-.parent= TYPE_PCIE_ROOT_PORT,
-.instance_size = sizeof(PnvPHB4RootPort),
-.class_init= pnv_phb4_root_port_class_init,
-};
-
-static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-dc->desc = "IBM PHB5 PCIE Root Port";
-dc->user_creatable = false;
-
-k->vendor_id = PCI_VENDOR_ID_IBM;
-k->device_id = PNV_PHB5_DEVICE_ID;
-}
-
-static const TypeInfo pnv_phb5_root_port_info = {
-.name = TYPE_PNV_PHB5_ROOT_PORT,
-.parent= TYPE_PNV_PHB4_ROOT_PORT,
-.instance_size = sizeof(PnvPHB4RootPort),
-.class_init= pnv_phb5_root_port_class_init,
-};
-
static void pnv_phb4_register_types(void)
{
type_register_static(_phb4_root_bus_info);
-type_register_static(_phb5_root_port_info);
-type_register_static(_phb4_root_port_info);
type_register_static(_phb4_type_info);
type_register_static(_phb5_type_info);
type_register_static(_phb4_iommu_memory_region_info);
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 4a0a9fbe8b..0ef66b9a9b 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -260,7 +260,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void
*data)
pecc->version = PNV_PHB4_VERSION;
pecc->phb_type =
[PULL 14/60] ppc/pnv: remove root port name from pnv_phb_attach_root_port()
We support only a single root port, PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-10-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 7 +--
hw/ppc/pnv.c | 9 +
include/hw/ppc/pnv.h | 3 +--
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index da729e89e7..cc15a949c9 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -24,7 +24,6 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
PnvPHB *phb = PNV_PHB(dev);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
g_autofree char *phb_typename = NULL;
-g_autofree char *phb_rootport_typename = NULL;
if (!phb->version) {
error_setg(errp, "version not specified");
@@ -34,15 +33,12 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
switch (phb->version) {
case 3:
phb_typename = g_strdup(TYPE_PNV_PHB3);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 5:
phb_typename = g_strdup(TYPE_PNV_PHB5);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
default:
g_assert_not_reached();
@@ -73,8 +69,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
-pnv_phb_attach_root_port(pci, phb_rootport_typename,
- phb->phb_id, phb->chip_id);
+pnv_phb_attach_root_port(pci, phb->phb_id, phb->chip_id);
}
static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 576c0013ed..6b94c373d1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1195,11 +1195,12 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error
**errp)
* QOM id. 'chip_id' is going to be used as PCIE chassis for the
* root port.
*/
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
- int index, int chip_id)
+void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
{
-PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
-g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
+PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
+g_autofree char *default_id = g_strdup_printf("%s[%d]",
+ TYPE_PNV_PHB_ROOT_PORT,
+ index);
const char *dev_id = DEVICE(root)->id;
object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 21fa90aaff..0eda47da0c 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -193,8 +193,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
- int index, int chip_id);
+void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.37.2
[PULL 05/60] target/ppc: Bugfix FP when OE/UE are set
From: "Lucas Mateus Castro (alqotel)"
When an overflow exception occurs and OE is set the intermediate result
should be adjusted (by subtracting from the exponent) to avoid rounding
to inf. The same applies to an underflow exceptionion and UE (but adding
to the exponent). To do this set the fp_status.rebias_overflow when OE
is set and fp_status.rebias_underflow when UE is set as the FPU will
recalculate in case of a overflow/underflow if the according rebias* is
set.
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
Message-Id: <20220805141522.412864-3-lucas.ara...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.c| 2 ++
target/ppc/fpu_helper.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 401b6f9e63..0ebac04bc4 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -120,6 +120,8 @@ void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
val |= FP_FEX;
}
env->fpscr = val;
+env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false;
+env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;
if (tcg_enabled()) {
fpscr_set_rounding_mode(env);
}
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 7ab6beadad..0f045b70f8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -348,7 +348,6 @@ static inline int float_overflow_excp(CPUPPCState *env)
bool overflow_enabled = !!(env->fpscr & FP_OE);
if (overflow_enabled) {
-/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
/* We must update the target FPR before raising the exception */
@@ -367,7 +366,6 @@ static inline void float_underflow_excp(CPUPPCState *env)
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
if (env->fpscr & FP_UE) {
-/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
/* We must update the target FPR before raising the exception */
--
2.37.2
[PULL 15/60] ppc/pnv: remove pecc->rp_model
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-11-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 0ef66b9a9b..8dc363d69c 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -260,7 +260,6 @@ static void pnv_pec_class_init(ObjectClass *klass, void
*data)
pecc->version = PNV_PHB4_VERSION;
pecc->phb_type = TYPE_PNV_PHB4;
pecc->num_phbs = pnv_pec_num_phbs;
-pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_pec_type_info = {
@@ -313,7 +312,6 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass,
void *data)
pecc->version = PNV_PHB5_VERSION;
pecc->phb_type = TYPE_PNV_PHB5;
pecc->num_phbs = pnv_phb5_pec_num_stacks;
-pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_phb5_pec_type_info = {
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 29c49ac79c..61a0cb9989 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -200,7 +200,6 @@ struct PnvPhb4PecClass {
uint64_t version;
const char *phb_type;
const uint32_t *num_phbs;
-const char *rp_model;
};
/*
--
2.37.2
[PULL 12/60] ppc/pnv: remove pnv-phb3-root-port
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-8-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb3.c | 42 --
hw/ppc/pnv.c | 1 +
include/hw/pci-host/pnv_phb3.h | 6 -
4 files changed, 2 insertions(+), 49 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 5e61f85614..cdddc6a389 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -34,7 +34,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
switch (phb->version) {
case 3:
phb_typename = g_strdup(TYPE_PNV_PHB3);
-phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index ad9e983fe9..d4c04a281a 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1122,51 +1122,9 @@ static const TypeInfo pnv_phb3_root_bus_info = {
.class_init = pnv_phb3_root_bus_class_init,
};
-static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
-{
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
-PCIDevice *pci = PCI_DEVICE(dev);
-Error *local_err = NULL;
-
-rpc->parent_realize(dev, _err);
-if (local_err) {
-error_propagate(errp, local_err);
-return;
-}
-pci_config_set_interrupt_pin(pci->config, 0);
-}
-
-static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
-
-dc->desc = "IBM PHB3 PCIE Root Port";
-
-device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
->parent_realize);
-dc->user_creatable = false;
-
-k->vendor_id = PCI_VENDOR_ID_IBM;
-k->device_id = 0x03dc;
-k->revision = 0;
-
-rpc->exp_offset = 0x48;
-rpc->aer_offset = 0x100;
-}
-
-static const TypeInfo pnv_phb3_root_port_info = {
-.name = TYPE_PNV_PHB3_ROOT_PORT,
-.parent= TYPE_PCIE_ROOT_PORT,
-.instance_size = sizeof(PnvPHB3RootPort),
-.class_init= pnv_phb3_root_port_class_init,
-};
-
static void pnv_phb3_register_types(void)
{
type_register_static(_phb3_root_bus_info);
-type_register_static(_phb3_root_port_info);
type_register_static(_phb3_type_info);
type_register_static(_phb3_iommu_memory_region_info);
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ae6cd14a8a..672227a0e1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2129,6 +2129,7 @@ static void pnv_machine_power8_class_init(ObjectClass
*oc, void *data)
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "3" },
+{ TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index 3b9ff1096a..bff69201d9 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -108,12 +108,6 @@ struct PnvPBCQState {
*/
#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root"
-#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
-
-typedef struct PnvPHB3RootPort {
-PCIESlot parent_obj;
-} PnvPHB3RootPort;
-
/*
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
--
2.37.2
[PULL 09/60] ppc/pnv: add PHB4 bus init helper
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-5-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 ++
hw/pci-host/pnv_phb4.c | 39 --
include/hw/pci-host/pnv_phb4.h | 1 +
3 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 6fefff7d44..abcbcca445 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -69,6 +69,8 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
if (phb->version == 3) {
pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
+} else {
+pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
pnv_phb_attach_root_port(pci, phb_rootport_typename,
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 67ddde4a6e..a7425927fb 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1528,30 +1528,16 @@ static void pnv_phb4_instance_init(Object *obj)
object_initialize_child(obj, "source", >xsrc, TYPE_XIVE_SOURCE);
}
-static void pnv_phb4_realize(DeviceState *dev, Error **errp)
+void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
{
-PnvPHB4 *phb = PNV_PHB4(dev);
-PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
-XiveSource *xsrc = >xsrc;
-int nr_irqs;
char name[32];
-/* Set the "big_phb" flag */
-phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
-
-/* Controller Registers */
-snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
- phb->phb_id);
-memory_region_init_io(>mr_regs, OBJECT(phb), _phb4_reg_ops, phb,
- name, 0x2000);
-
/*
* PHB4 doesn't support IO space. However, qemu gets very upset if
* we don't have an IO region to anchor IO BARs onto so we just
* initialize one which we never hook up to anything
*/
-
snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id,
phb->phb_id);
memory_region_init(>pci_io, OBJECT(phb), name, 0x1);
@@ -1561,12 +1547,33 @@ static void pnv_phb4_realize(DeviceState *dev, Error
**errp)
memory_region_init(>pci_mmio, OBJECT(phb), name,
PCI_MMIO_TOTAL_SIZE);
-pci->bus = pci_register_root_bus(dev, dev->id,
+pci->bus = pci_register_root_bus(dev, dev->id ? dev->id : NULL,
pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
>pci_mmio, >pci_io,
0, 4, TYPE_PNV_PHB4_ROOT_BUS);
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+}
+
+static void pnv_phb4_realize(DeviceState *dev, Error **errp)
+{
+PnvPHB4 *phb = PNV_PHB4(dev);
+PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
+PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+XiveSource *xsrc = >xsrc;
+int nr_irqs;
+char name[32];
+
+/* Set the "big_phb" flag */
+phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
+
+/* Controller Registers */
+snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
+ phb->phb_id);
+memory_region_init_io(>mr_regs, OBJECT(phb), _phb4_reg_ops, phb,
+ name, 0x2000);
+
+pnv_phb4_bus_init(dev, phb);
/* Add a single Root port if running with defaults */
pnv_phb_attach_root_port(pci, pecc->rp_model,
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 19dcbd6f87..90843ac3a9 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -157,6 +157,7 @@ struct PnvPHB4 {
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
+void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);
extern const MemoryRegionOps pnv_phb4_xscom_ops;
/*
--
2.37.2
[PULL 10/60] ppc/pnv: turn PnvPHB4 into a PnvPHB backend
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class will create PnvPHB devices with version '4'.
powernv10 will create using version '5'. Both are using global machine
properties in their class_init() to do that.
These changes will benefit us when adding PnvPHB user creatable devices
for powernv9 and powernv10.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-6-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb4.c | 30 +-
hw/pci-host/pnv_phb4_pec.c | 3 +--
hw/ppc/pnv.c | 20 +---
include/hw/pci-host/pnv_phb4.h | 5 -
4 files changed, 27 insertions(+), 31 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index a7425927fb..144c437025 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -33,7 +33,7 @@
static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
{
-PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
uint8_t bus, devfn;
@@ -129,7 +129,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned
off,
static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
unsigned size, uint64_t val)
{
-PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
if (size != 4) {
@@ -150,7 +150,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned
off,
static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
unsigned size)
{
-PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
uint64_t val;
@@ -1558,8 +1558,6 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
-PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
-PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = >xsrc;
int nr_irqs;
char name[32];
@@ -1573,12 +1571,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error
**errp)
memory_region_init_io(>mr_regs, OBJECT(phb), _phb4_reg_ops, phb,
name, 0x2000);
-pnv_phb4_bus_init(dev, phb);
-
-/* Add a single Root port if running with defaults */
-pnv_phb_attach_root_port(pci, pecc->rp_model,
- phb->phb_id, phb->chip_id);
-
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
@@ -1598,16 +1590,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error
**errp)
pnv_phb4_xscom_realize(phb);
}
-static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
- PCIBus *rootbus)
-{
-PnvPHB4 *phb = PNV_PHB4(host_bridge);
-
-snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
- phb->chip_id, phb->phb_id);
-return phb->bus_path;
-}
-
/*
* Address base trigger mode (POWER10)
*
@@ -1692,19 +1674,17 @@ static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
PnvPhb4PecState *),
+DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_phb4_class_init(ObjectClass *klass, void *data)
{
-PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
-hc->root_bus_path = pnv_phb4_root_bus_path;
dc->realize = pnv_phb4_realize;
device_class_set_props(dc, pnv_phb4_properties);
-set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = false;
xfc->notify = pnv_phb4_xive_notify;
@@ -1712,7 +1692,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void
*data)
static const TypeInfo pnv_phb4_type_info = {
.name = TYPE_PNV_PHB4,
-.parent= TYPE_PCIE_HOST_BRIDGE,
+.parent= TYPE_DEVICE,
.instance_init = pnv_phb4_instance_init,
.instance_size = sizeof(PnvPHB4),
.class_init= pnv_phb4_class_init,
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index c9aaf1c28e..4a0a9fbe8b 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState
*pec,
[PULL 03/60] ppc/pnv: Add initial P9/10 SBE model
From: Nicholas Piggin
The SBE (Self Boot Engine) are on-chip microcontrollers that perform
early boot steps, as well as provide some runtime facilities (e.g.,
timer, secure register access, MPIPL). The latter facilities are
accessed mostly via a message system called SBEFIFO.
This driver provides initial emulation for the SBE runtime registers
and a very basic SBEFIFO implementation that provides the timer
command. This covers the basic SBE behaviour expected by skiboot when
booting.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-Id: <20220811093726.1442343-1-npig...@gmail.com>
[danielhb: fixed SBE_HOST_RESPONSE_MASK long line]
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv.c | 25 +++
hw/ppc/pnv_sbe.c | 414 +
hw/ppc/pnv_xscom.c | 3 +
hw/ppc/trace-events| 11 +
include/hw/ppc/pnv.h | 3 +
include/hw/ppc/pnv_sbe.h | 55 +
include/hw/ppc/pnv_xscom.h | 12 ++
8 files changed, 524 insertions(+)
create mode 100644 hw/ppc/pnv_sbe.c
create mode 100644 include/hw/ppc/pnv_sbe.h
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index aa4c8e6a2e..62801923f3 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -46,6 +46,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_lpc.c',
'pnv_psi.c',
'pnv_occ.c',
+ 'pnv_sbe.c',
'pnv_bmc.c',
'pnv_homer.c',
'pnv_pnor.c',
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a4cb4cf10b..0c3aad430b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1397,6 +1397,8 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "occ", >occ, TYPE_PNV9_OCC);
+object_initialize_child(obj, "sbe", >sbe, TYPE_PNV9_SBE);
+
object_initialize_child(obj, "homer", >homer, TYPE_PNV9_HOMER);
/* Number of PECs is the chip default */
@@ -1549,6 +1551,17 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
memory_region_add_subregion(get_system_memory(),
PNV9_OCC_SENSOR_BASE(chip),
>occ.sram_regs);
+/* SBE */
+if (!qdev_realize(DEVICE(>sbe), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
+>sbe.xscom_ctrl_regs);
+pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
+>sbe.xscom_mbox_regs);
+qdev_connect_gpio_out(DEVICE(>sbe), 0, qdev_get_gpio_in(
+ DEVICE(>psi), PSIHB9_IRQ_PSU));
+
/* HOMER */
object_property_set_link(OBJECT(>homer), "chip", OBJECT(chip),
_abort);
@@ -1613,6 +1626,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", >psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", >lpc, TYPE_PNV10_LPC);
object_initialize_child(obj, "occ", >occ, TYPE_PNV10_OCC);
+object_initialize_child(obj, "sbe", >sbe, TYPE_PNV10_SBE);
object_initialize_child(obj, "homer", >homer, TYPE_PNV10_HOMER);
chip->num_pecs = pcc->num_pecs;
@@ -1754,6 +1768,17 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
PNV10_OCC_SENSOR_BASE(chip),
>occ.sram_regs);
+/* SBE */
+if (!qdev_realize(DEVICE(>sbe), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
+>sbe.xscom_ctrl_regs);
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
+>sbe.xscom_mbox_regs);
+qdev_connect_gpio_out(DEVICE(>sbe), 0, qdev_get_gpio_in(
+ DEVICE(>psi), PSIHB9_IRQ_PSU));
+
/* HOMER */
object_property_set_link(OBJECT(>homer), "chip", OBJECT(chip),
_abort);
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
new file mode 100644
index 00..1c7812a135
--- /dev/null
+++ b/hw/ppc/pnv_sbe.c
@@ -0,0 +1,414 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of some SBE behaviour
+ *
+ * Copyright (c) 2022, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
[PULL 11/60] ppc/pnv: add pnv-phb-root-port device
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_reset() callback. All
other differences can be merged in a single device without too much
trouble.
This patch introduces the unified pnv-phb-root-port that, in time, will
be used as the default root port for the pnv-phb device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-7-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 115 +++---
hw/pci-host/pnv_phb.h | 16 ++
2 files changed, 123 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index abcbcca445..5e61f85614 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -112,15 +112,114 @@ static void pnv_phb_class_init(ObjectClass *klass, void
*data)
dc->user_creatable = false;
}
-static void pnv_phb_register_type(void)
+static void pnv_phb_root_port_reset(DeviceState *dev)
{
-static const TypeInfo pnv_phb_type_info = {
-.name = TYPE_PNV_PHB,
-.parent= TYPE_PCIE_HOST_BRIDGE,
-.instance_size = sizeof(PnvPHB),
-.class_init= pnv_phb_class_init,
-};
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
+PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
+PCIDevice *d = PCI_DEVICE(dev);
+uint8_t *conf = d->config;
+rpc->parent_reset(dev);
+
+if (phb_rp->version == 3) {
+return;
+}
+
+/* PHB4 and later requires these extra reset steps */
+pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
+ PCI_IO_RANGE_MASK & 0xff);
+pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
+ PCI_IO_RANGE_MASK & 0xff);
+pci_set_word(conf + PCI_MEMORY_BASE, 0);
+pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
+pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
+pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
+pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
+pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0x);
+pci_config_set_interrupt_pin(conf, 0);
+}
+
+static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
+{
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
+PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
+PCIDevice *pci = PCI_DEVICE(dev);
+uint16_t device_id = 0;
+Error *local_err = NULL;
+
+rpc->parent_realize(dev, _err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+
+switch (phb_rp->version) {
+case 3:
+device_id = PNV_PHB3_DEVICE_ID;
+break;
+case 4:
+device_id = PNV_PHB4_DEVICE_ID;
+break;
+case 5:
+device_id = PNV_PHB5_DEVICE_ID;
+break;
+default:
+g_assert_not_reached();
+}
+
+pci_config_set_device_id(pci->config, device_id);
+pci_config_set_interrupt_pin(pci->config, 0);
+}
+
+static Property pnv_phb_root_port_properties[] = {
+DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
+
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
+
+dc->desc = "IBM PHB PCIE Root Port";
+
+device_class_set_props(dc, pnv_phb_root_port_properties);
+device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
+>parent_realize);
+device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
+ >parent_reset);
+dc->reset = _phb_root_port_reset;
+dc->user_creatable = false;
+
+k->vendor_id = PCI_VENDOR_ID_IBM;
+/* device_id will be written during realize() */
+k->device_id = 0;
+k->revision = 0;
+
+rpc->exp_offset = 0x48;
+rpc->aer_offset = 0x100;
+}
+
+static const TypeInfo pnv_phb_type_info = {
+.name = TYPE_PNV_PHB,
+.parent= TYPE_PCIE_HOST_BRIDGE,
+.instance_size = sizeof(PnvPHB),
+.class_init= pnv_phb_class_init,
+};
+
+static const TypeInfo pnv_phb_root_port_info = {
+.name = TYPE_PNV_PHB_ROOT_PORT,
+.parent= TYPE_PCIE_ROOT_PORT,
+.instance_size = sizeof(PnvPHBRootPort),
+.class_init= pnv_phb_root_port_class_init,
+};
+
+static void pnv_phb_register_types(void)
+{
type_register_static(_phb_type_info);
+type_register_static(_phb_root_port_info);
}
-type_init(pnv_phb_register_type)
+
+type_init(pnv_phb_register_types)
diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h
index a7cc8610e2..58ebd6dd0f 100644
---
[PULL 02/60] target/ppc: Fix host PVR matching for KVM
From: Nicholas Piggin
ppc_cpu_compare_class_pvr_mask() should match the best CPU class in the
family, because it is used by the KVM subsystem to find the host CPU
class. Since commit 03ae4133ab8 ("target-ppc: Add pvr_match()
callback"), it matches any class in the family (the first one in the
comparison list).
Since commit f30c843ced5 ("ppc/pnv: Introduce PowerNV machines with
fixed CPU models"), pnv has relied on pnv_match having these new
semantics to check machine compatibility with a CPU family.
Resolve this by adding a parameter to the pvr_match function to select
the best or any match, and restore the old behaviour for the KVM case.
Prior to this fix, e.g., a POWER9 DD2.3 KVM host matches to the
power9_v1.0 class (because that happens to be the first POWER9 family
CPU compared). After the patch, it matches the power9_v2.0 class.
This approach requires pnv_match contain knowledge of the CPU classes
implemented in the same family, which feels ugly. But pushing the 'best'
match down to the class would still require they know about one another
which is not obviously much better. For now this gets things working.
Fixes: 03ae4133ab8 ("target-ppc: Add pvr_match() callback")
Signed-off-by: Nicholas Piggin
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220731013358.170187-1-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 +-
target/ppc/cpu-qom.h | 6 ++-
target/ppc/cpu_init.c | 91 +--
target/ppc/machine.c | 2 +-
4 files changed, 77 insertions(+), 24 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d3f77c8367..a4cb4cf10b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -714,7 +714,7 @@ static bool pnv_match_cpu(const char *default_type, const
char *cpu_type)
PowerPCCPUClass *ppc =
POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
-return ppc_default->pvr_match(ppc_default, ppc->pvr);
+return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
}
static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index ad7e3c3db9..89ff88f28c 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -158,7 +158,11 @@ struct PowerPCCPUClass {
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;
-bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
+/*
+ * If @best is false, match if pcc is in the family of pvr
+ * Else match only if pcc is the best match for pvr in this family.
+ */
+bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
uint64_t pcr_mask; /* Available bits in PCR register */
uint64_t pcr_supported; /* Bits for supported PowerISA versions */
uint32_t svr;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d1493a660c..899c4a586e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5912,15 +5912,25 @@ static void init_proc_POWER7(CPUPPCState *env)
ppcPOWER7_irq_init(env_archcpu(env));
}
-static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
+static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
{
-if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
-return true;
+uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
+uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
+
+if (!best) {
+if (base == CPU_POWERPC_POWER7_BASE) {
+return true;
+}
+if (base == CPU_POWERPC_POWER7P_BASE) {
+return true;
+}
}
-if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
-return true;
+
+if (base != pcc_base) {
+return false;
}
-return false;
+
+return true;
}
static bool cpu_has_work_POWER7(CPUState *cs)
@@ -6073,18 +6083,27 @@ static void init_proc_POWER8(CPUPPCState *env)
ppcPOWER7_irq_init(env_archcpu(env));
}
-static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
+static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
{
-if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
-return true;
-}
-if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
-return true;
+uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
+uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
+
+if (!best) {
+if (base == CPU_POWERPC_POWER8_BASE) {
+return true;
+}
+if (base == CPU_POWERPC_POWER8E_BASE) {
+return true;
+}
+if (base == CPU_POWERPC_POWER8NVL_BASE) {
+return true;
+}
}
-if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
-return true;
+if (base != pcc_base) {
+return false;
}
-
[PULL 07/60] ppc/pnv: add PnvPHB base/proxy device
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementation that the device is going to use.
The initialization of the PHB backend is done by checking the PHB
version via a 'version' attribute that can be set via a global machine
property. The 'version' field will be used to make adjustments based on
the running version, e.g. PHB3 uses a 'chip' reference while PHB4 uses
'pec'. To init the PnvPHB bus we'll rely on helpers for each version.
The version 3 helper is already added (pnv_phb3_bus_init), the PHB4
helper will be added later on.
For now let's add the basic logic of the PnvPHB object, which consists
mostly of pnv_phb_realize() doing all the work of checking the
phb->version set, initializing the proper backend, passing through its
attributes to the chosen backend, finalizing the backend realize and
adding a root port in the end.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-3-danielhb...@gmail.com>
---
hw/pci-host/meson.build | 3 +-
hw/pci-host/pnv_phb.c | 124
hw/pci-host/pnv_phb.h | 39 +
3 files changed, 165 insertions(+), 1 deletion(-)
create mode 100644 hw/pci-host/pnv_phb.c
create mode 100644 hw/pci-host/pnv_phb.h
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index c07596d0d1..e832babc9d 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -35,5 +35,6 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
'pnv_phb3_msi.c',
'pnv_phb3_pbcq.c',
'pnv_phb4.c',
- 'pnv_phb4_pec.c'
+ 'pnv_phb4_pec.c',
+ 'pnv_phb.c',
))
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
new file mode 100644
index 00..6fefff7d44
--- /dev/null
+++ b/hw/pci-host/pnv_phb.c
@@ -0,0 +1,124 @@
+/*
+ * QEMU PowerPC PowerNV Proxy PHB model
+ *
+ * Copyright (c) 2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
+#include "hw/pci-host/pnv_phb.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv.h"
+#include "hw/qdev-properties.h"
+#include "qom/object.h"
+
+
+static void pnv_phb_realize(DeviceState *dev, Error **errp)
+{
+PnvPHB *phb = PNV_PHB(dev);
+PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+g_autofree char *phb_typename = NULL;
+g_autofree char *phb_rootport_typename = NULL;
+
+if (!phb->version) {
+error_setg(errp, "version not specified");
+return;
+}
+
+switch (phb->version) {
+case 3:
+phb_typename = g_strdup(TYPE_PNV_PHB3);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
+break;
+case 4:
+phb_typename = g_strdup(TYPE_PNV_PHB4);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
+break;
+case 5:
+phb_typename = g_strdup(TYPE_PNV_PHB5);
+phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
+break;
+default:
+g_assert_not_reached();
+}
+
+phb->backend = object_new(phb_typename);
+object_property_add_child(OBJECT(dev), "phb-backend", phb->backend);
+
+/* Passthrough child device properties to the proxy device */
+object_property_set_uint(phb->backend, "index", phb->phb_id, errp);
+object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
+object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
+
+if (phb->version == 3) {
+object_property_set_link(phb->backend, "chip",
+ OBJECT(phb->chip), errp);
+} else {
+object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp);
+}
+
+if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) {
+return;
+}
+
+if (phb->version == 3) {
+pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
+}
+
+pnv_phb_attach_root_port(pci, phb_rootport_typename,
+ phb->phb_id, phb->chip_id);
+}
+
+static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
+ PCIBus *rootbus)
+{
+PnvPHB *phb = PNV_PHB(host_bridge);
+
+snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
+ phb->chip_id, phb->phb_id);
+return phb->bus_path;
+}
+
+static Property pnv_phb_properties[] = {
+DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
+DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
+DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
+
+DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *),
+
+
[PULL 04/60] fpu: Add rebias bool, value and operation
From: "Lucas Mateus Castro (alqotel)"
Added the possibility of recalculating a result if it overflows or
underflows, if the result overflow and the rebias bool is true then the
intermediate result should have 3/4 of the total range subtracted from
the exponent. The same for underflow but it should be added to the
exponent of the intermediate number instead.
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
Message-Id: <20220805141522.412864-2-lucas.ara...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat-parts.c.inc | 21 +++--
fpu/softfloat.c | 2 ++
include/fpu/softfloat-types.h | 4
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index bbeadaa189..a9f268fcab 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -214,18 +214,35 @@ static void partsN(uncanon_normal)(FloatPartsN *p,
float_status *s,
p->frac_lo &= ~round_mask;
}
} else if (unlikely(exp >= exp_max)) {
-flags |= float_flag_overflow | float_flag_inexact;
-if (overflow_norm) {
+flags |= float_flag_overflow;
+if (s->rebias_overflow) {
+exp -= fmt->exp_re_bias;
+} else if (overflow_norm) {
+flags |= float_flag_inexact;
exp = exp_max - 1;
frac_allones(p);
p->frac_lo &= ~round_mask;
} else {
+flags |= float_flag_inexact;
p->cls = float_class_inf;
exp = exp_max;
frac_clear(p);
}
}
frac_shr(p, frac_shift);
+} else if (unlikely(s->rebias_underflow)) {
+flags |= float_flag_underflow;
+exp += fmt->exp_re_bias;
+if (p->frac_lo & round_mask) {
+flags |= float_flag_inexact;
+if (frac_addi(p, p, inc)) {
+frac_shr(p, 1);
+p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;
+exp++;
+}
+p->frac_lo &= ~round_mask;
+}
+frac_shr(p, frac_shift);
} else if (s->flush_to_zero) {
flags |= float_flag_output_denormal;
p->cls = float_class_zero;
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 4a871ef2a1..c7454c3eb1 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -521,6 +521,7 @@ typedef struct {
typedef struct {
int exp_size;
int exp_bias;
+int exp_re_bias;
int exp_max;
int frac_size;
int frac_shift;
@@ -532,6 +533,7 @@ typedef struct {
#define FLOAT_PARAMS_(E)\
.exp_size = E,\
.exp_bias = ((1 << E) - 1) >> 1, \
+.exp_re_bias= (1 << (E - 1)) + (1 << (E - 2)), \
.exp_max= (1 << E) - 1
#define FLOAT_PARAMS(E, F) \
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 7a6ea881d8..0884ec4ef7 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -195,6 +195,10 @@ typedef struct float_status {
bool snan_bit_is_one;
bool use_first_nan;
bool no_signaling_nans;
+/* should overflowed results subtract re_bias to its exponent? */
+bool rebias_overflow;
+/* should underflowed results add re_bias to its exponent? */
+bool rebias_underflow;
} float_status;
#endif /* SOFTFLOAT_TYPES_H */
--
2.37.2
[PULL 00/60] ppc queue
The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36: Open 7.2 development tree (2022-08-30 09:40:41 -0700) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831 for you to fetch changes up to 2d9c27ac5c035823315f68c227ca1cc6313e9842: ppc4xx: Fix code style problems reported by checkpatch (2022-08-31 14:08:06 -0300) ppc patch queue for 2022-08-31: In the first 7.2 queue we have changes in the powernv pnv-phb handling, the start of the QOMification of the ppc405 model, the removal of the taihu machine, a new SLOF image and others. Alexey Kardashevskiy (1): pseries: Update SLOF firmware image BALATON Zoltan (9): ppc4xx: Move PLB model to ppc4xx_devs.c ppc4xx: Rename ppc405-plb to ppc4xx-plb ppc4xx: Move EBC model to ppc4xx_devs.c ppc4xx: Rename ppc405-ebc to ppc4xx-ebc hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device ppc405: Move machine specific code to ppc405_boards.c hw/ppc/sam3460ex: Remove PPC405 dependency from sam460ex hw/ppc/Kconfig: Move imply before select ppc4xx: Fix code style problems reported by checkpatch Cédric Le Goater (22): ppc/ppc405: Remove taihu machine ppc/ppc405: Introduce a PPC405 generic machine ppc/ppc405: Move devices under the ref405ep machine ppc/ppc405: Move SRAM under the ref405ep machine ppc/ppc405: Introduce a PPC405 SoC ppc/ppc405: Start QOMification of the SoC ppc/ppc405: QOM'ify CPU ppc/ppc4xx: Introduce a DCR device model ppc/ppc405: QOM'ify CPC ppc/ppc405: QOM'ify GPT ppc/ppc405: QOM'ify OCM ppc/ppc405: QOM'ify GPIO ppc/ppc405: QOM'ify DMA ppc/ppc405: QOM'ify EBC ppc/ppc405: QOM'ify OPBA ppc/ppc405: QOM'ify POB ppc/ppc405: QOM'ify PLB ppc/ppc405: QOM'ify MAL ppc/ppc405: Use an embedded PPCUIC model in SoC state ppc/ppc405: Use an explicit I2C object ppc/ppc405: QOM'ify FPGA ppc/ppc4xx: Fix sdram trace events Daniel Henrique Barboza (24): ppc/pnv: add PHB3 bus init helper ppc/pnv: add PnvPHB base/proxy device ppc/pnv: turn PnvPHB3 into a PnvPHB backend ppc/pnv: add PHB4 bus init helper ppc/pnv: turn PnvPHB4 into a PnvPHB backend ppc/pnv: add pnv-phb-root-port device ppc/pnv: remove pnv-phb3-root-port ppc/pnv: remove pnv-phb4-root-port ppc/pnv: remove root port name from pnv_phb_attach_root_port() ppc/pnv: remove pecc->rp_model ppc/pnv: remove PnvPHB4.version ppc/pnv: move attach_root_port helper to pnv-phb.c ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties ppc/pnv: set root port chassis and slot using Bus properties ppc/pnv: add helpers for pnv-phb user devices ppc/pnv: turn chip8->phbs[] into a PnvPHB* array ppc/pnv: enable user created pnv-phb for powernv8 ppc/pnv: add PHB4 helpers for user created pnv-phb ppc/pnv: enable user created pnv-phb for powernv9 ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs ppc/pnv: user creatable pnv-phb for powernv10 ppc/pnv: consolidate pnv_parent_*_fixup() helpers ppc/pnv: fix QOM parenting of user creatable root ports Lucas Mateus Castro (alqotel) (2): fpu: Add rebias bool, value and operation target/ppc: Bugfix FP when OE/UE are set Nicholas Piggin (2): target/ppc: Fix host PVR matching for KVM ppc/pnv: Add initial P9/10 SBE model MAINTAINERS |2 +- docs/about/deprecated.rst |9 - docs/about/removed-features.rst |6 + docs/system/ppc/embedded.rst|1 - docs/system/ppc/pseries.rst |2 +- fpu/softfloat-parts.c.inc | 21 +- fpu/softfloat.c |2 + hw/intc/ppc-uic.c | 26 +- hw/pci-host/meson.build |3 +- hw/pci-host/pnv_phb.c | 337 hw/pci-host/pnv_phb.h | 55 ++ hw/pci-host/pnv_phb3.c | 152 +++-- hw/pci-host/pnv_phb4.c | 191 +++ hw/pci-host/pnv_phb4_pec.c | 11 +- hw/ppc/Kconfig |3 +- hw/ppc/meson.build |1 + hw/ppc/pnv.c| 188 +-- hw/ppc/pnv_sbe.c| 414 ++ hw/ppc/pnv_xscom.c |3 + hw/ppc/ppc405.h | 200 +-- hw/ppc/ppc405_boards.c | 552 +-- hw/ppc/ppc405_uc.c | 1156 ++- hw/ppc/ppc440_bamboo.c | 34 +- hw/ppc/ppc440_uc.c |3 +- hw/ppc/ppc4xx_devs.c| 554 ++- hw/ppc/ppc4xx_pci.c | 31 +- hw/ppc/sam460ex.c | 38 +
Re: [PATCH v1 02/25] tests/avocado: reduce the default timeout to 120s
Thomas Huth writes: > On 26/08/2022 19.21, Alex Bennée wrote: >> We should be aiming to keep our tests under 2 minutes so lets reduce >> the default timeout to that. Tests that we know take longer should >> explicitly set a longer timeout. >> Signed-off-by: Alex Bennée >> --- >> tests/avocado/avocado_qemu/__init__.py | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> diff --git a/tests/avocado/avocado_qemu/__init__.py >> b/tests/avocado/avocado_qemu/__init__.py >> index 9d17a287cf..0efd2bd212 100644 >> --- a/tests/avocado/avocado_qemu/__init__.py >> +++ b/tests/avocado/avocado_qemu/__init__.py >> @@ -229,7 +229,7 @@ def exec_command_and_wait_for_pattern(test, command, >> class QemuBaseTest(avocado.Test): >> # default timeout for all tests, can be overridden >> -timeout = 900 >> +timeout = 120 > > Did you try this on gitlab already? I guess it will fail in > some cases, e.g.: > > https://gitlab.com/qemu-project/qemu/-/jobs/2928561388 > > there are some tests that run definitely longer, e.g.: > > (005/192) tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2: > PASS (342.26 s) > (006/192) tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3: > PASS (330.37 s) > > and I can't spot a "timeout = ..." in that file. I've added some patches for that, ppc64le and s390 into v2 > > Thomas -- Alex Bennée
Re: QEMU 7.2 release schedule
On 8/30/22 14:12, Stefan Hajnoczi wrote: Please check the proposed release schedule and let me know if they fall on inconvenient dates: - 2022-08-30: Beginning of development phase - 2022-11-1: Soft feature freeze. Only bug fixes after this point. All feature changes must be already in a sub maintainer tree and all pull requests from submaintainers must have been sent to the list by this date. - 2022-11-8: Hard feature freeze. Tag rc0 - 2022-11-15: Tag rc1 - 2022-11-22: Tag rc2 - 2022-11-29: Tag rc3 - 2022-12-06: Release; or tag rc4 if needed - 2022-12-13: Release if we needed an rc4 Looks good to me, matching the 6.2 cycle well in having the release completed with a comfortable margin before the Christmas & New Year's seasons. r~
Re: Any interest in a QEMU emulation BoF at KVM Forum?
Alex Bennée writes: qemu-devel keeps bouncing the message so replying with a cut down CC list. > Hi, > > Given our slowly growing range of TCG emulations and the evident > interest in keeping up with modern processor architectures is it worth > having an emulation focused BoF at the up-coming KVM Forum? > > Some potential topics for discussion I could think of might include: > > * Progress towards heterogeneous vCPU emulation > > We've been making slow progress in removing assumptions from the > various front-ends about their global nature and adding accel:TCG > abstractions and support for the translator loop. We can already have > CPUs from the same architecture family in a model. What else do we need > to do so we can have those funky ARM+RiscV+Tricore heterogeneous > models? Is it library or something else? > > * External Device Models > > I know this is a contentious topic given the potential for GPL > end-runs. However there are also good arguments for enabling the > testing of open source designs without having forcing the > implementation of a separate C model to test software. For example if > we hypothetically modelled a Pi Pico would it make sense to model the > PIO in C if we could just compile the Verilog for it into a SystemC > model? Would a plethora of closed device models be the inevitable > consequence of such an approach? Would it matter if we just > concentrated on supporting useful open source solutions? > > * Dynamic Machine Models > > While we try and avoid modelling bespoke virtual HW in QEMU > (virt/goldfish not withstanding ;-) there is obviously a desire in the > EDA space to allow such experimentation. Is this something we can > provide so aspiring HW engineers can experiment with system > architectures without having to form QEMU and learn QOM. There have > been suggestions about consuming device trees or maybe translating to > QMP calls and adding support for wiring devices together. Given the > number of forks that exist is this something that could be better > supported upstream without degenerating into messy hacks? > > * A sense of time > > Currently we have the fairly limited support for -icount in QEMU. At > the same time we have no desire to start expanding frontends with > the details cost models required for a more realistic sense of time to > be presented. One suggestion is to expand the TCG plugin interface to > allow for the plugin to control time allowing as much or little logic > to be pushed there as we like and freeing up frontends from ever having > to consider it. > > Are any of these topics of interest? Are there any other emulation > topics people would like to discuss? -- Alex Bennée
Re: [PATCH] target/sh4: Fix TB_FLAG_UNALIGN
On 8/31/22 01:30, Yoshinori Sato wrote: +/* gUSA information field in CPUArchState.flags */ +/* + b16 - b23: Exclusive region range (negative) + b24: pc in exclusive region flag (use normal decode) +*/ +#define GUSA_SHIFT 16 +#define GUSA_EXCLUSIVE (1 << 24) No good. These now overlap *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ the fpscr bits. r~
Re: [PATCH] target/sh4: Fix TB_FLAG_UNALIGN
On 8/30/22 18:30, Yoshinori Sato wrote:
On Tue, 30 Aug 2022 01:10:29 +0900,
Richard Henderson wrote:
On 8/29/22 02:05, BALATON Zoltan wrote:
On Sun, 28 Aug 2022, Richard Henderson wrote:
The value previously chosen overlaps GUSA_MASK.
Cc: qemu-sta...@nongnu.org
Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9f15ef913c..e79cbc59e2 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -84,7 +84,7 @@
#define DELAY_SLOT_RTE (1 << 2)
#define TB_FLAG_PENDING_MOVCA (1 << 3)
-#define TB_FLAG_UNALIGN (1 << 4)
+#define TB_FLAG_UNALIGN (1 << 13)
Is it worth a comment to note why that value to avoid the same
problem if another flag is added in the future?
Hmm, or perhaps move it down below, so that we see bit 3 used, then bits 4-12,
then bit 13.
r~
It looks like the gUSA and unalign access flags are mixed.
I think the flags should also be separated as the two features are not related.
Well, of course. That's what the first patch is fixing.
Balaton is merely discussing the order in which the bits
are defined.
r~
Re: [PATCH 31/51] tests/qtest: Support libqtest to build and run on Windows
Hi
On Wed, Aug 24, 2022 at 2:46 PM Bin Meng wrote:
> From: Bin Meng
>
> At present the libqtest codes were written to depend on several
> POSIX APIs, including fork(), kill() and waitpid(). Unfortunately
> these APIs are not available on Windows.
>
> This commit implements the corresponding functionalities using
> win32 native APIs. With this change, all qtest cases can build
> successfully on a Windows host, and we can start qtest testing
> on Windows now.
>
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
> ---
>
> tests/qtest/libqtest.c | 101 +++-
> tests/qtest/meson.build | 5 +-
> 2 files changed, 101 insertions(+), 5 deletions(-)
>
> diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
> index 70d7578740..99e52ff571 100644
> --- a/tests/qtest/libqtest.c
> +++ b/tests/qtest/libqtest.c
> @@ -16,9 +16,11 @@
>
> #include "qemu/osdep.h"
>
> +#ifndef _WIN32
> #include
> #include
> #include
> +#endif /* _WIN32 */
> #ifdef __linux__
> #include
> #endif /* __linux__ */
> @@ -27,6 +29,7 @@
> #include "libqmp.h"
> #include "qemu/ctype.h"
> #include "qemu/cutils.h"
> +#include "qemu/sockets.h"
> #include "qapi/qmp/qdict.h"
> #include "qapi/qmp/qjson.h"
> #include "qapi/qmp/qlist.h"
> @@ -35,6 +38,16 @@
> #define MAX_IRQ 256
> #define SOCKET_TIMEOUT 50
>
> +#ifndef _WIN32
> +# define CMD_EXEC "exec "
> +# define DEV_STDERR "/dev/fd/2"
> +# define DEV_NULL "/dev/null"
> +#else
> +# define CMD_EXEC ""
> +# define DEV_STDERR "2"
> +# define DEV_NULL "nul"
> +#endif
> +
> typedef void (*QTestSendFn)(QTestState *s, const char *buf);
> typedef void (*ExternalSendFn)(void *s, const char *buf);
> typedef GString* (*QTestRecvFn)(QTestState *);
> @@ -68,6 +81,9 @@ struct QTestState
> QTestState *global_qtest;
>
> static GHookList abrt_hooks;
> +#ifdef _WIN32
> +typedef void (*sighandler_t)(int);
> +#endif
> static sighandler_t sighandler_old;
>
> static int qtest_query_target_endianness(QTestState *s);
> @@ -120,10 +136,18 @@ bool qtest_probe_child(QTestState *s)
> pid_t pid = s->qemu_pid;
>
> if (pid != -1) {
> +#ifndef _WIN32
> pid = waitpid(pid, >wstatus, WNOHANG);
> if (pid == 0) {
> return true;
> }
> +#else
> +DWORD exit_code;
> +GetExitCodeProcess((HANDLE)pid, _code);
> +if (exit_code == STILL_ACTIVE) {
> +return true;
> +}
> +#endif
> s->qemu_pid = -1;
> }
> return false;
> @@ -137,13 +161,23 @@ void qtest_set_expected_status(QTestState *s, int
> status)
> void qtest_kill_qemu(QTestState *s)
> {
> pid_t pid = s->qemu_pid;
> +#ifndef _WIN32
> int wstatus;
> +#else
> +DWORD ret, exit_code;
> +#endif
>
> /* Skip wait if qtest_probe_child already reaped. */
> if (pid != -1) {
> +#ifndef _WIN32
> kill(pid, SIGTERM);
> TFR(pid = waitpid(s->qemu_pid, >wstatus, 0));
> assert(pid == s->qemu_pid);
> +#else
> +TerminateProcess((HANDLE)pid, s->expected_status);
> +ret = WaitForSingleObject((HANDLE)pid, INFINITE);
> +assert(ret == WAIT_OBJECT_0);
> +#endif
> s->qemu_pid = -1;
> }
>
> @@ -151,6 +185,7 @@ void qtest_kill_qemu(QTestState *s)
> * Check whether qemu exited with expected exit status; anything else
> is
> * fishy and should be logged with as much detail as possible.
> */
> +#ifndef _WIN32
> wstatus = s->wstatus;
> if (WIFEXITED(wstatus) && WEXITSTATUS(wstatus) != s->expected_status)
> {
> fprintf(stderr, "%s:%d: kill_qemu() tried to terminate QEMU "
> @@ -167,6 +202,16 @@ void qtest_kill_qemu(QTestState *s)
> __FILE__, __LINE__, sig, signame, dump);
> abort();
> }
> +#else
> +GetExitCodeProcess((HANDLE)pid, _code);
> +CloseHandle((HANDLE)pid);
> +if (exit_code != s->expected_status) {
> +fprintf(stderr, "%s:%d: kill_qemu() tried to terminate QEMU "
> +"process but encountered exit status %ld (expected %d)\n",
> +__FILE__, __LINE__, exit_code, s->expected_status);
> +abort();
> +}
> +#endif
> }
>
> static void kill_qemu_hook_func(void *s)
> @@ -245,6 +290,38 @@ static const char *qtest_qemu_binary(void)
> return qemu_bin;
> }
>
> +#ifdef _WIN32
> +static pid_t qtest_create_process(char *cmd)
> +{
> +STARTUPINFO si;
> +PROCESS_INFORMATION pi;
> +BOOL ret;
> +
> +ZeroMemory(, sizeof(si));
> +si.cb = sizeof(si);
> +ZeroMemory(, sizeof(pi));
> +
> +ret = CreateProcess(NULL, /* module name */
> +cmd,/* command line */
> +NULL, /* process handle not inheritable */
> +NULL, /* thread handle not inheritable */
> +FALSE, /* set handle inheritance to FALSE */
> +0, /* No creation flags */
> +NULL, /* use
Re: [PATCH v4 12/12] hw/isa/vt82c686: Create rtc-time alias in boards instead
On Wed, 31 Aug 2022, Bernhard Beschow wrote:
According to good QOM practice, an object should only deal with objects
of its own sub tree. Having devices create an alias on the machine
object doesn't respect this good practice. To resolve this, create the
alias in the machine's code.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 --
hw/mips/fuloong2e.c | 4
hw/ppc/pegasos2.c | 4
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 48cd4d0036..3f9bd0c04d 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -632,8 +632,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
return;
}
-object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(>rtc),
- "date");
isa_connect_gpio_out(ISA_DEVICE(>rtc), 0, s->rtc.isairq);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 2d8723ab74..0f4cfe1188 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -203,6 +203,10 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus,
int slot, qemu_irq intc,
via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), true,
TYPE_VT82C686B_ISA);
+object_property_add_alias(qdev_get_machine(), "rtc-time",
+ object_resolve_path_component(OBJECT(via),
+"rtc"),
+ "date");
qdev_connect_gpio_out(DEVICE(via), 0, intc);
dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "ide"));
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 09fdb7557f..f50e1d8b3f 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -161,6 +161,10 @@ static void pegasos2_init(MachineState *machine)
/* VIA VT8231 South Bridge (multifunction PCI device) */
via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
TYPE_VT8231_ISA);
+object_property_add_alias(qdev_get_machine(), "rtc-time",
I did not check it in previous version but Phillppe noted this
qdev_get_machine() should be machine (the parameter to pegasos2_init)
instead and I agree with that.
Also if you get rid of the now very much cut down
vt82c686b_southbridge_init func in fuloong2e and just inline what's left
of it at the only call site then the same machine pointer could be used
there too and would be simpler then going through the function now that
it's moved to via-isa mostly.
Sorry that this needs another respin but that's the last, I won't look at
it again :-) You can also add to the whole series:
Reviewed-by: BALATON Zoltan
Regards,
BALATON Zoltan
+ object_resolve_path_component(OBJECT(via),
+"rtc"),
+ "date");
qdev_connect_gpio_out(DEVICE(via), 0,
qdev_get_gpio_in_named(pm->mv, "gpp", 31));
Re: Any interest in a QEMU emulation BoF at KVM Forum?
On Wed, Aug 31, 2022 at 03:35:19PM +0100, Alex Bennée wrote: > Hi, > > Given our slowly growing range of TCG emulations and the evident > interest in keeping up with modern processor architectures is it worth > having an emulation focused BoF at the up-coming KVM Forum? Hi Alex, Yes, I'd be interested in all topics you mention. Best regards, Edgar > > Some potential topics for discussion I could think of might include: > > * Progress towards heterogeneous vCPU emulation > > We've been making slow progress in removing assumptions from the > various front-ends about their global nature and adding accel:TCG > abstractions and support for the translator loop. We can already have > CPUs from the same architecture family in a model. What else do we need > to do so we can have those funky ARM+RiscV+Tricore heterogeneous > models? Is it library or something else? > > * External Device Models > > I know this is a contentious topic given the potential for GPL > end-runs. However there are also good arguments for enabling the > testing of open source designs without having forcing the > implementation of a separate C model to test software. For example if > we hypothetically modelled a Pi Pico would it make sense to model the > PIO in C if we could just compile the Verilog for it into a SystemC > model? Would a plethora of closed device models be the inevitable > consequence of such an approach? Would it matter if we just > concentrated on supporting useful open source solutions? > > * Dynamic Machine Models > > While we try and avoid modelling bespoke virtual HW in QEMU > (virt/goldfish not withstanding ;-) there is obviously a desire in the > EDA space to allow such experimentation. Is this something we can > provide so aspiring HW engineers can experiment with system > architectures without having to form QEMU and learn QOM. There have > been suggestions about consuming device trees or maybe translating to > QMP calls and adding support for wiring devices together. Given the > number of forks that exist is this something that could be better > supported upstream without degenerating into messy hacks? > > * A sense of time > > Currently we have the fairly limited support for -icount in QEMU. At > the same time we have no desire to start expanding frontends with > the details cost models required for a more realistic sense of time to > be presented. One suggestion is to expand the TCG plugin interface to > allow for the plugin to control time allowing as much or little logic > to be pushed there as we like and freeing up frontends from ever having > to consider it. > > Are any of these topics of interest? Are there any other emulation > topics people would like to discuss? > > -- > Alex Bennée
Re: [PATCH v3 06/10] hw/isa/vt82c686: Instantiate USB functions in host device
On Wed, 31 Aug 2022, BB wrote:
Am 31. August 2022 17:03:35 MESZ schrieb BALATON Zoltan :
On Wed, 31 Aug 2022, BB wrote:
Am 31. August 2022 15:23:37 MESZ schrieb BALATON Zoltan :
On Wed, 31 Aug 2022, Bernhard Beschow wrote:
The USB functions can be enabled/disabled through the ISA function. Also
its interrupt routing can be influenced there.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 12
hw/mips/fuloong2e.c | 3 ---
hw/ppc/pegasos2.c | 4
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 9d946cea54..66a4b9c230 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -23,6 +23,7 @@
#include "hw/intc/i8259.h"
#include "hw/irq.h"
#include "hw/dma/i8257.h"
+#include "hw/usb/hcd-uhci.h"
#include "hw/timer/i8254.h"
#include "hw/rtc/mc146818rtc.h"
#include "migration/vmstate.h"
@@ -546,6 +547,7 @@ struct ViaISAState {
qemu_irq *isa_irqs;
ViaSuperIOState via_sio;
PCIIDEState ide;
+UHCIState uhci[2];
};
static const VMStateDescription vmstate_via = {
@@ -563,6 +565,8 @@ static void via_isa_init(Object *obj)
ViaISAState *s = VIA_ISA(obj);
object_initialize_child(obj, "ide", >ide, "via-ide");
+object_initialize_child(obj, "uhci1", >uhci[0], "vt82c686b-usb-uhci");
+object_initialize_child(obj, "uhci2", >uhci[1], "vt82c686b-usb-uhci");
Sorry for not saying this yesterday, this can also be done separately so no
need for another version of this series if not needed for another reason but
could we add a define for vt82c686b-usb-uhci in include/hw/isa/vt82c686.h and
use that here and in hw/usb/vt82c686-uhci-pci.c ?
Would creating a dedicated header work, too? Board code doesn't need to see the
define any longer.
I don't think it needs a separate header just for this so I'd put it in
vt82c686.h but I don't mind either way.
Alright, I'll take the easy route for now. Splitting in dedicated headers (also
for the other devices) could be done in a separate series.
I'll do this for via-ac97 when rabasing my WIP patch:
https://osdn.net/projects/qmiga/scm/git/qemu/commits
as I'll need to move ViaAC97State there too for embedding in ViaISAState.
The other ones
can stay in vt82c686.h I think.
(The reason this is still WIP is that it does not work and I'm not sure
why, Maybe I need to test with a Linux guest to find out more but I
haven't got to that yet.)
Regards,
BALATON Zoltan
Re: Any interest in a QEMU emulation BoF at KVM Forum?
I am VERY interested in these topics from a Qualcomm perspective. I’ll be there from Tuesday morning, I think a “BoF” would be very helpful … Cheers Mark. On 31/08/2022, 17:20, "Alex Bennée" wrote: WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros. Hi, Given our slowly growing range of TCG emulations and the evident interest in keeping up with modern processor architectures is it worth having an emulation focused BoF at the up-coming KVM Forum? Some potential topics for discussion I could think of might include: * Progress towards heterogeneous vCPU emulation We've been making slow progress in removing assumptions from the various front-ends about their global nature and adding accel:TCG abstractions and support for the translator loop. We can already have CPUs from the same architecture family in a model. What else do we need to do so we can have those funky ARM+RiscV+Tricore heterogeneous models? Is it library or something else? * External Device Models I know this is a contentious topic given the potential for GPL end-runs. However there are also good arguments for enabling the testing of open source designs without having forcing the implementation of a separate C model to test software. For example if we hypothetically modelled a Pi Pico would it make sense to model the PIO in C if we could just compile the Verilog for it into a SystemC model? Would a plethora of closed device models be the inevitable consequence of such an approach? Would it matter if we just concentrated on supporting useful open source solutions? * Dynamic Machine Models While we try and avoid modelling bespoke virtual HW in QEMU (virt/goldfish not withstanding ;-) there is obviously a desire in the EDA space to allow such experimentation. Is this something we can provide so aspiring HW engineers can experiment with system architectures without having to form QEMU and learn QOM. There have been suggestions about consuming device trees or maybe translating to QMP calls and adding support for wiring devices together. Given the number of forks that exist is this something that could be better supported upstream without degenerating into messy hacks? * A sense of time Currently we have the fairly limited support for -icount in QEMU. At the same time we have no desire to start expanding frontends with the details cost models required for a more realistic sense of time to be presented. One suggestion is to expand the TCG plugin interface to allow for the plugin to control time allowing as much or little logic to be pushed there as we like and freeing up frontends from ever having to consider it. Are any of these topics of interest? Are there any other emulation topics people would like to discuss? -- Alex Bennée
