Re: tests/qtest: Is vnc-display-test supposed to work on Darwin?
Hi On Fri, Dec 2, 2022 at 1:51 PM Philippe Mathieu-Daudé wrote: > > Hi, > > The vnc-display-test is failing on Darwin: > > tests/qtest/vnc-display-test:45038): ERROR **: 10:42:35.488: vnc-error: > Unsupported auth type 17973672 It is supposed to pass. Can you share more details? It doesn't look like an endianness issue, at first sight.. > Is it supposed to pass, or should we skip it similarly to Windows? (I hope it'll cover Windows soon) -- Marc-André Lureau
Re: [PULL for 7.2-rc4 0/1] loongarch for 7.2-rc4 patch
On 2/12/22 11:25, Song Gao wrote: The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece: Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221202 for you to fetch changes up to 14dccc8ea6ece7ee63273144fb55e4770a05e0fd: hw/loongarch/virt: Add cfi01 pflash device (2022-12-02 18:03:05 +0800) pull for 7.2-rc4 We need this patch. FTR this is not a security/regression fix, but a mere feature. Certainly not justified for a rc4 IMO. Xiaojuan Yang (1): hw/loongarch/virt: Add cfi01 pflash device hw/loongarch/Kconfig| 1 + hw/loongarch/acpi-build.c | 18 + hw/loongarch/virt.c | 62 + include/hw/loongarch/virt.h | 5 4 files changed, 86 insertions(+)
Re: [PATCH] net: Fix qemu crash when hot-pluging a vhost-net failed.
On 5/12/22 07:37, Jason Wang wrote: On Mon, Dec 5, 2022 at 2:23 PM Yangming wrote: Dear all: I found a bug of qemu: hot-pluging a vhost-net may cause virtual machine crash in following steps: 1. Starting a vm without any net device. 2. Hot-pluging 70 memory devices. 3. Hot-pluging a vhost-net device. After the 3rd step, the qemu crashed with following messages: vhost backend memory slots limit is less than current number of present memory slots warning: vhost-net requested but could not be initialized qemu-system-x86_64: ../net/net.c:1106: net_client_init1: Assertion `nc' failed. 2022-12-05 03:14:08.794+: shutting down, reason=crashed This commit is used to fix the mentioned problem. It is based on commit a33c25399f9bc3dcf83064adeba2a82e61bf4608 of master branch. Thanks for the patch, would you please send a formal patch (not as an attachment), you can do it via git-send-email. You can find some help on how to proceed here: https://www.qemu.org/docs/master/devel/submitting-a-patch.html
Re: [RFC PATCH] migration: reduce time of loading non-iterable vmstate
Peter, I'm sorry I didn't reply to your email in time, because I was busy with other work last week. Here is my latest progress. On 2022/11/29 上午1:41, Peter Xu wrote: On Mon, Nov 28, 2022 at 05:42:43PM +0800, Chuang Xu wrote: On 2022/11/25 上午12:40, Peter Xu wrote: On Fri, Nov 18, 2022 at 04:36:48PM +0800, Chuang Xu wrote: The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop and ending with the timestamp of target qemu start). Most of the time is spent committing memory region changes repeatedly. This patch packs all the changes to memory region during the period of loading non-iterable vmstate in a single memory transaction. With the increase of devices, this patch will greatly improve the performance. Here are the test results: test vm info: - 32 CPUs 128GB RAM - 8 16-queue vhost-net device - 16 4-queue vhost-user-blk device. time of loading non-iterable vmstate before about 210 ms after about 40 ms Signed-off-by: Chuang Xu This is an interesting idea.. I think it means at least the address space operations will all be messed up if happening during the precopy loading Sorry, I don't quite understand the meaning of "messed up" here.. Maybe I need more information about how the address space operations will be messed up. AFAIK the major thing we do during commit of memory regions is to apply the memory region changes to the rest (flatviews, or ioeventfds), basically it makes everything matching with the new memory region layout. If we allow memory region commit to be postponed for the whole loading process, it means at least from flat view pov any further things like: address_space_write(_space_memory, ...) Could write to wrong places because the flat views are not updated. I have tested migration on normal qemu and optimized qemu repeatedly, I haven't trace any other operation on target qemu's mr (such as address_space_write...) happens so far. progress, but I don't directly see its happening either. For example, in most post_load()s of vmsd I think the devices should just write directly to its buffers, accessing MRs directly, even if they want DMAs or just update fields to correct states. Even so, I'm not super confident that holds And I'm not sure whether the "its happening" means "begin/commit happening" or "messed up happening"? If it's the former, Here are what I observe: the stage of loading iterable vmstate doesn't call begin/commit, but the stage of loading noniterable vmstate calls a large amount of begin/commit in field->info->get() operation. For example: #0 memory_region_transaction_commit () at ../softmmu/memory.c:1085 #1 0x559b6f683523 in pci_update_mappings (d=d@entry=0x7f5cd8682010) at ../hw/pci/pci.c:1361 #2 0x559b6f683a1f in get_pci_config_device (f=, pv=0x7f5cd86820a0, size=256, field=) at ../hw/pci/pci.c:545 #3 0x559b6f5fcd86 in vmstate_load_state (f=f@entry=0x559b757eb4b0, vmsd=vmsd@entry=0x559b70909d40 , opaque=opaque@entry=0x7f5cd8682010, version_id=2) at ../migration/vmstate.c:143 #4 0x559b6f68466f in pci_device_load (s=s@entry=0x7f5cd8682010, f=f@entry=0x559b757eb4b0) at ../hw/pci/pci.c:664 #5 0x559b6f6ad38a in virtio_pci_load_config (d=0x7f5cd8682010, f=0x559b757eb4b0) at ../hw/virtio/virtio-pci.c:181 #6 0x559b6f7dfe91 in virtio_load (vdev=0x7f5cd868a1a0, f=0x559b757eb4b0, version_id=1) at ../hw/virtio/virtio.c:3071 #7 0x559b6f5fcd86 in vmstate_load_state (f=f@entry=0x559b757eb4b0, vmsd=0x559b709ae260 , opaque=0x7f5cd868a1a0, version_id=1) at ../migration/vmstate.c:143 #8 0x559b6f62da48 in vmstate_load (f=0x559b757eb4b0, se=0x559b7591c010) at ../migration/savevm.c:913 #9 0x559b6f631334 in qemu_loadvm_section_start_full (mis=0x559b73f1a580, f=0x559b757eb4b0) at ../migration/savevm.c:2741 #10 qemu_loadvm_state_main (f=f@entry=0x559b757eb4b0, mis=mis@entry=0x559b73f1a580) at ../migration/savevm.c:2937 #11 0x559b6f632faa in qemu_loadvm_state (f=0x559b757eb4b0) at ../migration/savevm.c:3018 #12 0x559b6f6d2ece in process_incoming_migration_co (opaque=) at ../migration/migration.c:574 #13 0x559b6f9f9f0b in coroutine_trampoline (i0=, i1=) at ../util/coroutine-ucontext.c:173 #14 0x7f5cfeecf000 in ?? () from /lib/x86_64-linux-gnu/libc.so.6 #15 0x7fff04a2e8f0 in ?? () #16 0x in ?? () true, not to mention any other side effects (e.g., would we release bql during precopy for any reason?). Copy Paolo and PeterM for some extra eyes. What I observe is that during the loading process, migration thread will call Condwait to wait for the vcpu threads to complete tasks, such as kvm_apic_post_load, and rcu thread will acquire the bql to do the flatview_destroy operation. So far, I haven't seen the side effects of these two situations. Yes that's something I'd worry about. The current memory API should be defined as: when we release the bql we should
[PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault exception.
At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.
Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is
configured")
Signed-off-by: Bin Meng
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 09f1f5185d..d7af7f056b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
-riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
--
2.34.1
Re: [PATCH] net: Fix qemu crash when hot-pluging a vhost-net failed.
On Mon, Dec 5, 2022 at 2:23 PM Yangming wrote: > > Dear all: > > > > I found a bug of qemu: hot-pluging a vhost-net may cause virtual machine > crash in following steps: > 1. Starting a vm without any net device. > 2. Hot-pluging 70 memory devices. > 3. Hot-pluging a vhost-net device. > > > > After the 3rd step, the qemu crashed with following messages: > > > > vhost backend memory slots limit is less than current number of present > memory slots > > warning: vhost-net requested but could not be initialized > > qemu-system-x86_64: ../net/net.c:1106: net_client_init1: Assertion `nc' > failed. > > 2022-12-05 03:14:08.794+: shutting down, reason=crashed > > > > This commit is used to fix the mentioned problem. It is based on commit > a33c25399f9bc3dcf83064adeba2a82e61bf4608 of master branch. Thanks for the patch, would you please send a formal patch (not as an attachment), you can do it via git-send-email. Thanks > > > > Kind regards. > >
Re: [PATCH v2 3/4] vdpa: handle VIRTIO_NET_CTRL_ANNOUNCE in vhost_vdpa_net_handle_ctrl_avail
On Thu, Dec 1, 2022 at 5:29 PM Eugenio Perez Martin wrote:
>
> On Thu, Dec 1, 2022 at 9:39 AM Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 3:07 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, Nov 30, 2022 at 8:02 AM Jason Wang wrote:
> > > >
> > > > On Fri, Nov 25, 2022 at 1:33 AM Eugenio Pérez
> > > > wrote:
> > > > >
> > > > > Since this capability is emulated by qemu shadowed CVQ cannot forward
> > > > > it
> > > > > to the device. Process all that command within qemu.
> > > > >
> > > > > Signed-off-by: Eugenio Pérez
> > > > > ---
> > > > > net/vhost-vdpa.c | 15 ---
> > > > > 1 file changed, 12 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
> > > > > index 2b4b85d8f8..8172aa8449 100644
> > > > > --- a/net/vhost-vdpa.c
> > > > > +++ b/net/vhost-vdpa.c
> > > > > @@ -489,9 +489,18 @@ static int
> > > > > vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
> > > > > out.iov_len = iov_to_buf(elem->out_sg, elem->out_num, 0,
> > > > > s->cvq_cmd_out_buffer,
> > > > > vhost_vdpa_net_cvq_cmd_len());
> > > > > -dev_written = vhost_vdpa_net_cvq_add(s, out.iov_len,
> > > > > sizeof(status));
> > > > > -if (unlikely(dev_written < 0)) {
> > > > > -goto out;
> > > > > +if (*(uint8_t *)s->cvq_cmd_out_buffer ==
> > > > > VIRTIO_NET_CTRL_ANNOUNCE) {
> > > > > +/*
> > > > > + * Guest announce capability is emulated by qemu, so dont
> > > > > forward to
> > > >
> > > > s/dont/don't/
> > > >
> > >
> > > I'll correct it, thanks!
> > >
> > > > > + * the device.
> > > > > + */
> > > > > +dev_written = sizeof(status);
> > > > > +*s->status = VIRTIO_NET_OK;
> > > >
> > > > I wonder if we should avoid negotiating ANNOUNCE with vDPA parents if
> > > > we do this?
> > > >
> > >
> > > I can re-check, but the next patch should avoid it.
> >
> > Kind of, it makes sure guest can always see _F_ANNOUNCE. But does it
> > prevent _F_ANNOUNCE from being negotiated?
> >
>
> It should go like:
> * vhost_net_ack_features calls vhost_ack_features with feature_bits =
> vdpa_feature_bits and features = guest acked features.
> vhost_ack_features stores in hdev->acked_features only the features
> that met features & bit_mask, so it will not store _F_ANNOUNCE.
> * vhost_vdpa_set_features is called from vhost_dev_set_features with
> features = dev->acked_features. Both functions can add features by
> themselves (VHOST_F_LOG_ALL, VIRTIO_F_IOMMU_PLATFORM), but no
> _F_ANNOUNCE.
>
> Still untested.
Ok.
>
> > > Even if
> > > negotiated, the parent should never set the announce status bit, since
> > > we never tell the device is a destination device.
> >
> > That's the point, do we have such a guarantee? Or I wonder if there's
> > any parent that supports _F_ANNOUNCE if yes, how it is supposed to
> > work?
> >
>
> At the moment it is impossible to work since there is no support for
> config interrupt from the device. Even with config interrupt,
> something external from qemu should make the device enable the status
> bit, since the current migration protocol makes no difference between
> to be a migration destination and to start the device from scratch.
> Unless it enables the bit maliciously or by mistake.
>
> Just for completion, the current method works with no need of vdpa
> device config interrupt support thanks to being 100% emulated in qemu,
> which has the support of injecting config interrupts.
Ok, rethink this feature, I think I can find one use case for
_F_ANNOUNCE, that is, the migration is totally done through the vDPA
device (DPU) itself.
I think we can go forward and revisit this issue in the future.
Thanks
>
> Thanks!
>
Re: [PATCH for 8.0 v8 06/12] vdpa: extract vhost_vdpa_svq_allocate_iova_tree
On Thu, Dec 1, 2022 at 5:50 PM Eugenio Perez Martin wrote:
>
> On Thu, Dec 1, 2022 at 9:45 AM Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 3:40 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, Nov 30, 2022 at 7:43 AM Jason Wang wrote:
> > > >
> > > > On Thu, Nov 24, 2022 at 11:52 PM Eugenio Pérez
> > > > wrote:
> > > > >
> > > > > It can be allocated either if all virtqueues must be shadowed or if
> > > > > vdpa-net detects it can shadow only cvq.
> > > > >
> > > > > Extract in its own function so we can reuse it.
> > > > >
> > > > > Signed-off-by: Eugenio Pérez
> > > > > ---
> > > > > net/vhost-vdpa.c | 29 +
> > > > > 1 file changed, 17 insertions(+), 12 deletions(-)
> > > > >
> > > > > diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
> > > > > index 88e0eec5fa..9ee3bc4cd3 100644
> > > > > --- a/net/vhost-vdpa.c
> > > > > +++ b/net/vhost-vdpa.c
> > > > > @@ -240,6 +240,22 @@ static NetClientInfo net_vhost_vdpa_info = {
> > > > > .check_peer_type = vhost_vdpa_check_peer_type,
> > > > > };
> > > > >
> > > > > +static int vhost_vdpa_get_iova_range(int fd,
> > > > > + struct vhost_vdpa_iova_range
> > > > > *iova_range)
> > > > > +{
> > > > > +int ret = ioctl(fd, VHOST_VDPA_GET_IOVA_RANGE, iova_range);
> > > > > +
> > > > > +return ret < 0 ? -errno : 0;
> > > > > +}
> > > >
> > > > I don't get why this needs to be moved to net specific code.
> > > >
> > >
> > > It was already in net, this code just extracted it in its own function.
> >
> > Ok, there's similar function that in vhost-vdpa.c:
> >
> > static void vhost_vdpa_get_iova_range(struct vhost_vdpa *v)
> > {
> > int ret = vhost_vdpa_call(v->dev, VHOST_VDPA_GET_IOVA_RANGE,
> > >iova_range);
> > if (ret != 0) {
> > v->iova_range.first = 0;
> > v->iova_range.last = UINT64_MAX;
> > }
> >
> > trace_vhost_vdpa_get_iova_range(v->dev, v->iova_range.first,
> > v->iova_range.last);
> > }
> >
> > I think we can reuse that.
> >
>
> That's right, but I'd do the reverse: I would store iova_min, iova_max
> in VhostVDPAState and would set it to vhost_vdpa at
> net_vhost_vdpa_init. That way, we only have one ioctl call at the
> beginning instead of having (#vq pairs + cvq) calls each time the
> device starts. I can send it in a new change if you see it ok.
>
> There are a few functions like that we can reuse in net/. To get the
> features and the backend features are two other examples. Even if we
> don't cache them since device initialization mandates the read, we
> could reduce code duplication that way.
>
> However, they use vhost_dev or vhost_vdpa instead of directly the file
> descriptor. Not a big deal but it's an extra step.
>
> What do you think?
I'm fine with this.
Thanks
>
> Thanks!
>
Re: [PATCH] intel-iommu: Document iova_tree
On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
>
> It seems not super clear on when iova_tree is used, and why. Add a rich
> comment above iova_tree to track why we needed the iova_tree, and when we
> need it.
>
> Suggested-by: Jason Wang
> Signed-off-by: Peter Xu
> ---
> include/hw/i386/intel_iommu.h | 30 +-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index 46d973e629..8d130ab2e3 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -109,7 +109,35 @@ struct VTDAddressSpace {
> QLIST_ENTRY(VTDAddressSpace) next;
> /* Superset of notifier flags that this address space has */
> IOMMUNotifierFlag notifier_flags;
> -IOVATree *iova_tree; /* Traces mapped IOVA ranges */
> +/*
> + * @iova_tree traces mapped IOVA ranges.
> + *
> + * The tree is not needed if no MAP notifiers is registered with
> + * current VTD address space, because all UNMAP (including iotlb or
> + * dev-iotlb) events can be transparently delivered to !MAP iommu
> + * notifiers.
So this means the UNMAP notifier doesn't need to be as accurate as
MAP. (Should we document it in the notifier headers)?
For MAP[a, b] MAP[b, c] we can do a UNMAP[a. c].
> + *
> + * The tree OTOH is required for MAP typed iommu notifiers for a few
> + * reasons.
> + *
> + * Firstly, there's no way to identify whether an PSI event is MAP or
> + * UNMAP within the PSI message itself. Without having prior knowledge
> + * of existing state vIOMMU doesn't know whether it should notify MAP
> + * or UNMAP for a PSI message it received.
> + *
> + * Secondly, PSI received from guest driver (or even a large PSI can
> + * grow into a DSI at least with Linux intel-iommu driver) can be
> + * larger in range than the newly mapped ranges for either MAP or UNMAP
> + * events.
Yes, so I think we need a document that the UNMAP handler should be
prepared for this.
Thanks
> If it directly pass-throughs any such event it may confuse
> + * the registered drivers (e.g. vfio-pci) on either: (1) trying to map
> + * the same region more than once (for VFIO_IOMMU_MAP_DMA, -EEXIST will
> + * trigger), or (2) trying to UNMAP a range that is still partially
> + * mapped. That accuracy is not required for UNMAP-only notifiers, but
> + * it is a must-to-have for MAP-inclusive notifiers, because the vIOMMU
> + * needs to make sure the shadow page table is always in sync with the
> + * guest IOMMU pgtables for a device.
> + */
> +IOVATree *iova_tree;
> };
>
> struct VTDIOTLBEntry {
> --
> 2.37.3
>
Re: [PATCH] vhost: Not return fail while the device does not support send_iotlb_msg
On Sat, Dec 3, 2022 at 3:38 PM Cindy Lu wrote:
>
> On Thu, 1 Dec 2022 at 16:49, Jason Wang wrote:
> >
> > On Wed, Nov 30, 2022 at 4:11 PM Cindy Lu wrote:
> > >
> > > Some device does not support vhost_send_device_iotlb_msg()
> > > such as vDPA device, which is as expected. So we should not
> > > return fail here.
I don't see why vDPA doesn't support this function?
> >
> > Please explain in which case you may hit the -ENODEV and what's the
> > side effect of this.
> >
> > Thanks
> >
> this issue was found during the test of virtio-iommu
> the step is
> 1. while load the VM with qemu
> -device virtio-iommu-pci \
> -device
> virtio-net-pci,netdev=vhost-vdpa0,disable-legacy=on,disable-modern=off,iommu_platform=on\
> -netdev type=vhost-vdpa,vhostdev=/dev/vhost-vdpa-0,id=vhost-vdpa0\
> 2. the guest vm's CMDLINE //proc/cmdline don't have iommu=pt
> there will be a lot error message during loading VM/runing traffic
> ysteqemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> mqemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> dqemu-system-x86_64: Fail to invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> -resolved.…e - Network Name Resolution...qemu-system-x86_64: Fail to
> invalidate device iotlb
> qemu-system-x86_64: Fail to invalidate device iotlb
> .
> and the vdpa port in guest VM doesn't working well
>
> With this fix the guest VM load without error message and the vdpa
> port working correctly at the
> same setting
> [root@ubuntunew ~]# ping 111.1.1.2
> PING 111.1.1.2 (111.1.1.2) 56(84) bytes of data.
> 64 bytes from 111.1.1.2: icmp_seq=1 ttl=64 time=25.0 ms
> 64 bytes from 111.1.1.2: icmp_seq=2 ttl=64 time=22.0 ms
> 64 bytes from 111.1.1.2: icmp_seq=3 ttl=64 time=24.3 ms
>
> Thansk
> Cindy
>
> > >
> > > Signed-off-by: Cindy Lu
> > > ---
> > > hw/virtio/vhost-backend.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/hw/virtio/vhost-backend.c b/hw/virtio/vhost-backend.c
> > > index 8e581575c9..9321ed9031 100644
> > > --- a/hw/virtio/vhost-backend.c
> > > +++ b/hw/virtio/vhost-backend.c
> > > @@ -360,7 +360,7 @@ int vhost_backend_update_device_iotlb(struct
> > > vhost_dev *dev,
> > > if (dev->vhost_ops && dev->vhost_ops->vhost_send_device_iotlb_msg)
> > > return dev->vhost_ops->vhost_send_device_iotlb_msg(dev, );
We need to figure out why we can get vhost_iotlb_miss() here. And if
it is needed, we need to implement the ops or document why it is not
needed here.
It seems to be here:
/* Update used ring information for IOTLB to work correctly,
* vhost-kernel code requires for this.*/
for (i = 0; i < hdev->nvqs; ++i) {
struct vhost_virtqueue *vq = hdev->vqs + i;
=> vhost_device_iotlb_miss(hdev, vq->used_phys, true);
}
The code is only needed for the kernel backend (vhost_init_used()
requires it), so let's try to skip it for other backeds here.
Thanks
> > >
> > > -return -ENODEV;
> > > +return 0;
> > > }
> > >
> > > int vhost_backend_invalidate_device_iotlb(struct vhost_dev *dev,
> > > @@ -375,7 +375,7 @@ int vhost_backend_invalidate_device_iotlb(struct
> > > vhost_dev *dev,
> > > if (dev->vhost_ops && dev->vhost_ops->vhost_send_device_iotlb_msg)
> > > return dev->vhost_ops->vhost_send_device_iotlb_msg(dev, );
> > >
> > > -return -ENODEV;
> > > +return 0;
> > > }
> > >
> > > int vhost_backend_handle_iotlb_msg(struct vhost_dev *dev,
> > > --
> > > 2.34.3
> > >
> >
>
Re: [PATCH 3/3] intel-iommu: build iova tree during IOMMU translation
`
On Thu, Dec 1, 2022 at 10:59 PM Peter Xu wrote:
>
> On Thu, Dec 01, 2022 at 04:35:48PM +0800, Jason Wang wrote:
> > On Wed, Nov 30, 2022 at 11:17 PM Peter Xu wrote:
> > >
> > > On Wed, Nov 30, 2022 at 02:33:51PM +0800, Jason Wang wrote:
> > > > On Tue, Nov 29, 2022 at 11:57 PM Peter Xu wrote:
> > > > >
> > > > > On Tue, Nov 29, 2022 at 04:10:37PM +0800, Jason Wang wrote:
> > > > > > The IOVA tree is only built during page walk this breaks the device
> > > > > > that tries to use UNMAP notifier only. One example is vhost-net, it
> > > > > > tries to use UNMAP notifier when vIOMMU doesn't support
> > > > > > DEVIOTLB_UNMAP
> > > > > > notifier (e.g when dt mode is not enabled). The interesting part is
> > > > > > that it doesn't use MAP since it can query the IOMMU translation by
> > > > > > itself upon a IOTLB miss.
> > > > > >
> > > > > > This doesn't work since Qemu doesn't build IOVA tree in IOMMU
> > > > > > translation which means the UNMAP notifier won't be triggered during
> > > > > > the page walk since Qemu think it is never mapped. This could be
> > > > > > noticed when vIOMMU is used with vhost_net but dt is disabled.
> > > > > >
> > > > > > Fixing this by build the iova tree during IOMMU translation, this
> > > > > > makes sure the UNMAP notifier event could be identified during page
> > > > > > walk. And we need to walk page table not only for UNMAP notifier but
> > > > > > for MAP notifier during PSI.
> > > > > >
> > > > > > Signed-off-by: Jason Wang
> > > > > > ---
> > > > > > hw/i386/intel_iommu.c | 43
> > > > > > ++-
> > > > > > 1 file changed, 18 insertions(+), 25 deletions(-)
> > > > > >
> > > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > > > > index d025ef2873..edeb62f4b2 100644
> > > > > > --- a/hw/i386/intel_iommu.c
> > > > > > +++ b/hw/i386/intel_iommu.c
> > > > > > @@ -1834,6 +1834,8 @@ static bool
> > > > > > vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
> > > > > > uint8_t access_flags;
> > > > > > bool rid2pasid = (pasid == PCI_NO_PASID) && s->root_scalable;
> > > > > > VTDIOTLBEntry *iotlb_entry;
> > > > > > +const DMAMap *mapped;
> > > > > > +DMAMap target;
> > > > > >
> > > > > > /*
> > > > > > * We have standalone memory region for interrupt addresses, we
> > > > > > @@ -1954,6 +1956,21 @@ out:
> > > > > > entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits)
> > > > > > & page_mask;
> > > > > > entry->addr_mask = ~page_mask;
> > > > > > entry->perm = access_flags;
> > > > > > +
> > > > > > +target.iova = entry->iova;
> > > > > > +target.size = entry->addr_mask;
> > > > > > +target.translated_addr = entry->translated_addr;
> > > > > > +target.perm = entry->perm;
> > > > > > +
> > > > > > +mapped = iova_tree_find(vtd_as->iova_tree, );
> > > > > > +if (!mapped) {
> > > > > > +/* To make UNMAP notifier work, we need build iova tree
> > > > > > here
> > > > > > + * in order to have the UNMAP iommu notifier to be
> > > > > > triggered
> > > > > > + * during the page walk.
> > > > > > + */
> > > > > > +iova_tree_insert(vtd_as->iova_tree, );
> > > > > > +}
> > > > > > +
> > > > > > return true;
> > > > > >
> > > > > > error:
> > > > > > @@ -2161,31 +2178,7 @@ static void
> > > > > > vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
> > > > > > ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
> > > > > > vtd_as->devfn, );
> > > > > > if (!ret && domain_id == vtd_get_domain_id(s, ,
> > > > > > vtd_as->pasid)) {
> > > > > > -if (vtd_as_has_map_notifier(vtd_as)) {
> > > > > > -/*
> > > > > > - * As long as we have MAP notifications registered
> > > > > > in
> > > > > > - * any of our IOMMU notifiers, we need to sync the
> > > > > > - * shadow page table.
> > > > > > - */
> > > > > > -vtd_sync_shadow_page_table_range(vtd_as, ,
> > > > > > addr, size);
> > > > > > -} else {
> > > > > > -/*
> > > > > > - * For UNMAP-only notifiers, we don't need to walk
> > > > > > the
> > > > > > - * page tables. We just deliver the PSI down to
> > > > > > - * invalidate caches.
> > > > > > - */
> > > > > > -IOMMUTLBEvent event = {
> > > > > > -.type = IOMMU_NOTIFIER_UNMAP,
> > > > > > -.entry = {
> > > > > > -.target_as = _space_memory,
> > > > > > -.iova = addr,
> > > > > > -.translated_addr = 0,
> > > > > > -.addr_mask = size - 1,
> > > > > > -.perm = IOMMU_NONE,
> > > > > > -},
> > > > > > -};
> >
Re: [PATCH] configure: Add --enable-lto
On 12/4/22 11:40, Peter Maydell wrote:
On Sun, 4 Dec 2022 at 00:04, Richard Henderson
wrote:
Separately control b_lto without --enable-cfi.
Also add --disable-lto for completeness.
Before this patch, CFI defaults to false and therefore LTO
also defaults to false. After this patch, LTO defaults to
true even if CFI is false. Intentional change ?
Nope. Oops.
Do we have figures for whether LTO produces an interesting
performance improvement ?
No idea. I wrote this after finding a bug report in which someone tried to add -flto via
--extra-cflags.
We should probably complain if the user tries '--enable-cfi --disable-lto'
rather than silently doing something that presumably doesn't work.
We do, in meson.build:
if get_option('cfi')
cfi_flags=[]
# Check for dependency on LTO
if not get_option('b_lto')
error('Selected Control-Flow Integrity but LTO is disabled')
r~
Re: [PULL for-7.2 0/2] TCG/i386 fixes for QEMU 7.2-rc4
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL 0/5] virtio: regression fix
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL for-7.2 0/5] hw/nvme fixes
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL for 7.2-rc4 0/1] loongarch for 7.2-rc4 patch
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL 0/3] Optional fixes for inclusion into QEMU 7.2.0-rc4
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PATCH 0/3] python: testing fixes
On Fri, 2022-12-02 at 19:52 -0500, John Snow wrote: > A few tiny touchups needed for cutting edge 'flake8' tooling, a minor > type touchup in iotests, and extending the python tests to cover the > recently released Python 3.11. > > John Snow (3): > Python: fix flake8 config > iotests/check: Fix typing for sys.exit() value > python: add 3.11 to supported list > > python/setup.cfg | 6 -- > tests/qemu-iotests/check | 2 +- > 2 files changed, 5 insertions(+), 3 deletions(-) > > -- > 2.38.1 > I see you've left Westeros! xD Reviewed-by: Wilfred Mallawa > >
Re: [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H
On Fri, Dec 2, 2022 at 12:15 AM Bin Meng wrote:
>
> H-mode has been removed since priv spec 1.10. Drop it.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> include/hw/intc/sifive_plic.h | 1 -
> hw/intc/sifive_plic.c | 1 -
> 2 files changed, 2 deletions(-)
>
> diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
> index 134cf39a96..d3f45ec248 100644
> --- a/include/hw/intc/sifive_plic.h
> +++ b/include/hw/intc/sifive_plic.h
> @@ -33,7 +33,6 @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
> typedef enum PLICMode {
> PLICMode_U,
> PLICMode_S,
> -PLICMode_H,
> PLICMode_M
> } PLICMode;
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 1cf156cf85..3f6ffb1d70 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -42,7 +42,6 @@ static PLICMode char_to_mode(char c)
> switch (c) {
> case 'U': return PLICMode_U;
> case 'S': return PLICMode_S;
> -case 'H': return PLICMode_H;
> case 'M': return PLICMode_M;
> default:
> error_report("plic: invalid mode '%c'", c);
> --
> 2.34.1
>
>
Re: [PATCH 05/15] hw/riscv: spike: Remove misleading comments
On Fri, Dec 2, 2022 at 12:14 AM Bin Meng wrote: > > PLIC is not included in the 'spike' machine. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/spike.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 1e1d752c00..13946acf0d 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -8,7 +8,6 @@ > * > * 0) HTIF Console and Poweroff > * 1) CLINT (Timer and IPI) > - * 2) PLIC (Platform Level Interrupt Controller) > * > * This program is free software; you can redistribute it and/or modify it > * under the terms and conditions of the GNU General Public License, > -- > 2.34.1 > >
Re: [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order
On Fri, Dec 2, 2022 at 12:14 AM Bin Meng wrote: > > SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/riscv/Kconfig | 16 +--- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 1e4b58024f..4550b3b938 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -4,6 +4,8 @@ config RISCV_NUMA > config IBEX > bool > > +# RISC-V machines in alphabetical order > + > config MICROCHIP_PFSOC > bool > select CADENCE_SDHCI > @@ -22,13 +24,6 @@ config OPENTITAN > select SIFIVE_PLIC > select UNIMP > > -config SHAKTI_C > -bool > -select UNIMP > -select SHAKTI_UART > -select RISCV_ACLINT > -select SIFIVE_PLIC > - > config RISCV_VIRT > bool > imply PCI_DEVICES > @@ -50,6 +45,13 @@ config RISCV_VIRT > select FW_CFG_DMA > select PLATFORM_BUS > > +config SHAKTI_C > +bool > +select RISCV_ACLINT > +select SHAKTI_UART > +select SIFIVE_PLIC > +select UNIMP > + > config SIFIVE_E > bool > select RISCV_ACLINT > -- > 2.34.1 > >
Re: [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote:
>
> Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
> the IBEX PLIC model was replaced with the SiFive PLIC model in the
> 'opentitan' machine but we forgot the add the dependency there.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> hw/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 167dc4cca6..1e4b58024f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -19,6 +19,7 @@ config MICROCHIP_PFSOC
> config OPENTITAN
> bool
> select IBEX
> +select SIFIVE_PLIC
> select UNIMP
>
> config SHAKTI_C
> --
> 2.34.1
>
>
Re: [PATCH 02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote: > > hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt > controllers regardless of how MSI is implemented. msi_nonbroken is > initialized to true in both riscv_aplic_realize() and > riscv_imsic_realize(). > > Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/intc/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig > index 1d4573e803..21441d0a0c 100644 > --- a/hw/intc/Kconfig > +++ b/hw/intc/Kconfig > @@ -72,9 +72,11 @@ config RISCV_ACLINT > > config RISCV_APLIC > bool > +select MSI_NONBROKEN > > config RISCV_IMSIC > bool > +select MSI_NONBROKEN > > config SIFIVE_PLIC > bool > -- > 2.34.1 > >
Re: [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
On Fri, Dec 2, 2022 at 12:15 AM Bin Meng wrote: > > hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt > controllers regardless of how MSI is implemented. msi_nonbroken is > initialized to true in sifive_plic_realize(). > > Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from > RISC-V machines. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > hw/intc/Kconfig | 1 + > hw/riscv/Kconfig | 5 - > 2 files changed, 1 insertion(+), 5 deletions(-) > > diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig > index ecd2883ceb..1d4573e803 100644 > --- a/hw/intc/Kconfig > +++ b/hw/intc/Kconfig > @@ -78,6 +78,7 @@ config RISCV_IMSIC > > config SIFIVE_PLIC > bool > +select MSI_NONBROKEN > > config GOLDFISH_PIC > bool > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 79ff61c464..167dc4cca6 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -11,7 +11,6 @@ config MICROCHIP_PFSOC > select MCHP_PFSOC_IOSCB > select MCHP_PFSOC_MMUART > select MCHP_PFSOC_SYSREG > -select MSI_NONBROKEN > select RISCV_ACLINT > select SIFIVE_PDMA > select SIFIVE_PLIC > @@ -37,7 +36,6 @@ config RISCV_VIRT > imply TPM_TIS_SYSBUS > select RISCV_NUMA > select GOLDFISH_RTC > -select MSI_NONBROKEN > select PCI > select PCI_EXPRESS_GENERIC_BRIDGE > select PFLASH_CFI01 > @@ -53,7 +51,6 @@ config RISCV_VIRT > > config SIFIVE_E > bool > -select MSI_NONBROKEN > select RISCV_ACLINT > select SIFIVE_GPIO > select SIFIVE_PLIC > @@ -64,7 +61,6 @@ config SIFIVE_E > config SIFIVE_U > bool > select CADENCE > -select MSI_NONBROKEN > select RISCV_ACLINT > select SIFIVE_GPIO > select SIFIVE_PDMA > @@ -82,6 +78,5 @@ config SPIKE > bool > select RISCV_NUMA > select HTIF > -select MSI_NONBROKEN > select RISCV_ACLINT > select SIFIVE_PLIC > -- > 2.34.1 > >
Re: [PATCH] docs/acpi/bits: document BITS_DEBUG environment variable
On Sat, 2022-12-03 at 13:23 +, Ani Sinha wrote: > Debug specific actions can be enabled in bios bits acpi tests by > passing > BITS_DEBUG in the environment variable while running the test. > Document that. > > CC: qemu-triv...@nongnu.org > Signed-off-by: Ani Sinha > --- > docs/devel/acpi-bits.rst | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Wilfred Mallawa > > diff --git a/docs/devel/acpi-bits.rst b/docs/devel/acpi-bits.rst > index 4a94c7d83d..9eb4b9e666 100644 > --- a/docs/devel/acpi-bits.rst > +++ b/docs/devel/acpi-bits.rst > @@ -52,6 +52,9 @@ Under ``tests/avocado/`` as the root we have: > for their tests. In order to enable debugging, you can set > **V=1** > environment variable. This enables verbose mode for the test and > also dumps > the entire log from bios bits and more information in case > failure happens. > + You can also set **BITS_DEBUG=1** to turn on debug mode. It will > enable > + verbose logs and also retain the temporary work directory the > test used for > + you to inspect and run the specific commands manually. > > In order to run this test, please perform the following steps > from the QEMU > build directory:
Re: [PATCH 06/32] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
On 4/12/22 20:05, Bernhard Beschow wrote: Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-10-shen...@gmail.com> --- hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 13 +++-- hw/isa/piix4.c| 2 +- hw/usb/hcd-uhci.c | 16 hw/usb/hcd-uhci.h | 4 5 files changed, 22 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 04/32] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
On 4/12/22 20:05, Bernhard Beschow wrote: Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow --- configs/devices/mips-softmmu/common.mak | 2 -- hw/mips/Kconfig | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) Yeah, it is it that state due to the Super I/O stuff pulled by x86 :/ Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 4/6] hw/misc: Allwinner AXP-209 Emulation
Hi Strahinja,
On 4/12/22 00:19, Strahinja Jankovic wrote:
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.
Signed-off-by: Strahinja Jankovic
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig | 4 +
hw/misc/allwinner-axp-209.c | 263
hw/misc/meson.build | 1 +
4 files changed, 269 insertions(+)
create mode 100644 hw/misc/allwinner-axp-209.c
diff --git a/hw/misc/allwinner-axp-209.c b/hw/misc/allwinner-axp-209.c
new file mode 100644
index 00..229e3961b6
--- /dev/null
+++ b/hw/misc/allwinner-axp-209.c
@@ -0,0 +1,263 @@
+/*
+ * AXP-209 Emulation
+ *
+ * Written by Strahinja Jankovic
+ *
You missed the "Copyright (c) " line.
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
If you mind, please also include:
* SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/i2c/i2c.h"
+#include "migration/vmstate.h"
+
+#ifndef AXP_209_ERR_DEBUG
+#define AXP_209_ERR_DEBUG 0
+#endif
+
+#define TYPE_AXP_209 "allwinner.axp209"
+
+#define AXP_209(obj) \
+OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP_209)
+
+#define DB_PRINT(fmt, args...) do { \
+if (AXP_209_ERR_DEBUG) { \
+fprintf(stderr, "%s: " fmt, __func__, ## args); \
Please replace the DB_PRINT() calls by trace events which are more
powerful: when a tracing backend is present, the events are built
in and you can individually enable them at runtime.
+} \
+} while (0)
+#define AXP_209_CHIP_VERSION_ID (0x01)
+#define AXP_209_DC_DC2_OUT_V_CTRL_RESET (0x16)
+#define AXP_209_IRQ_BANK_1_CTRL_RESET (0xd8)
+/* Reset all counters and load ID register */
+static void axp_209_reset_enter(Object *obj, ResetType type)
+{
+AXP209I2CState *s = AXP_209(obj);
+
+memset(s->regs, 0, NR_REGS);
+s->ptr = 0;
+s->count = 0;
+s->regs[REG_CHIP_VERSION] = AXP_209_CHIP_VERSION_ID;
+s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP_209_DC_DC2_OUT_V_CTRL_RESET;
+s->regs[REG_IRQ_BANK_1_CTRL] = AXP_209_IRQ_BANK_1_CTRL_RESET;
+}
+/* Initialization */
+static void axp_209_init(Object *obj)
+{
+AXP209I2CState *s = AXP_209(obj);
+
+s->count = 0;
+s->ptr = 0;
+memset(s->regs, 0, NR_REGS);
+s->regs[REG_CHIP_VERSION] = AXP_209_CHIP_VERSION_ID;
+s->regs[REG_DC_DC2_OUT_V_CTRL] = 0x16;
+s->regs[REG_IRQ_BANK_1_CTRL] = 0xd8;
The device initialization flow is:
- init()
- realize()
- reset()
So these values are already set in axp_209_reset_enter().
Besides, you should use the definition you added instead of
magic values (AXP_209_DC_DC2_OUT_V_CTRL_RESET and
AXP_209_IRQ_BANK_1_CTRL_RESET).
+
+DB_PRINT("INIT AXP209\n");
+
+return;
+}
Otherwise LGTM!
Thanks,
Phil.
Re: [PULL for-7.2 0/5] hw/nvme fixes
On Sun, Dec 04, 2022 at 11:06:13AM -0500, Stefan Hajnoczi wrote: > On Thu, 1 Dec 2022 at 11:50, Klaus Jensen wrote: > > > > From: Klaus Jensen > > > > Hi, > > > > The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece: > > > > Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500) > > > > are available in the Git repository at: > > > > git://git.infradead.org/qemu-nvme.git tags/nvme-next-pull-request > > Hi Klaus, > Please send pull requests with an https:// URI in the future. Is this a new requirement? Our public git server doesn't support https.
Re: [PATCH 00/32] Consolidate PIIX south bridges
Sorry, the titles should have contained a "v3"... Am 4. Dezember 2022 19:05:21 UTC schrieb Bernhard Beschow : >This series consolidates the implementations of the PIIX3 and PIIX4 south > >bridges and is an extended version of [1]. The motivation is to share as much > >code as possible and to bring both device models to feature parity such that > >perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. >This > >could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this > >list before. > > > >The series is structured as follows: First, PIIX3 is changed to instantiate > >internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared > >for the merge with PIIX4 which includes some fixes, cleanups, and renamings. > >Third, the same is done for PIIX4. In step four the implementations are merged. > >Since some consolidations could be done easier with merged implementations, the > >consolidation continues in step five which concludes the series. > > > >One particular challenge in this series was that the PIC of PIIX3 used to be > >instantiated outside of the south bridge while some sub functions require a PIC > >with populated qemu_irqs. This has been solved by introducing a proxy PIC which > >furthermore allows PIIX3 to be agnostic towards the virtualization technology > >used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. > > > >Another challenge was dealing with optional devices where Peter already gave > >advice in [1] which this series implements. > > > >A challenge still remains with consolidating PCI interrupt handling. There are > >still board-specific piix3_pci_slot_get_pirq() and piix4_pci_slot_get_pirq() > >which are implemented in isa/piix.c. Any advice how to resolve these would be > >highly appreaciated. See [2] for details. > > > >Last but not least there might be some opportunity to consolidate VM state > >handling, probably by reusing the one from PIIX3. Since I'm not very familiar > >with the requirements I didn't touch it so far. > > > >Testing done: > >* make check > >* make check-avocado > >* Boot live CD: > > * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom > manjaro-kde-21.3.2-220704-linux515.iso` > > * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom > manjaro-kde-21.3.2-220704-linux515.iso` > >* 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda >debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` > > > >v3: > >- Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx >(Philippe) > >- Make proxy PIC generic (Philippe) > >- Track Malta's PIIX dependencies through KConfig > >- Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' >series [3] - Use OBJECT_DECLARE_SIMPLE_TYPE() for PIIXState (Mark in v1) Best regards, Bernhard > >- Also rebase onto latest master to resolve merge conflicts. This required >copying > > Philippe's series as first three patches - please ignore. > > > >v2: > >- Introduce TYPE_ defines for IDE and USB device models (Mark) > >- Omit unexporting of PIIXState (Mark) > >- Improve commit message of patch 5 to mention reset triggering through PCI > > configuration space (Mark) > >- Move reviewed patches w/o dependencies to the bottom of the series for early > > upstreaming > > > >[1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html > >[2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html > >[3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html > > > >Bernhard Beschow (29): > > hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig > > hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 > >south bridge > > hw/usb/hcd-uhci: Introduce TYPE_ defines for device models > > hw/i386/pc: Create RTC controllers in south bridges > > hw/i386/pc: No need for rtc_state to be an out-parameter > > hw/isa/piix3: Create USB controller in host device > > hw/isa/piix3: Create power management controller in host device > > hw/core: Introduce proxy-pic > > hw/isa/piix3: Create Proxy PIC in host device > > hw/isa/piix3: Create IDE controller in host device > > hw/isa/piix3: Wire up ACPI interrupt internally > > hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS > > hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 > > hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 > > hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" > > hw/isa/piix3: Rename typedef PIIX3State to PIIXState > > hw/isa/piix4: Make PIIX4's ACPI and USB functions optional > > hw/isa/piix4: Remove unused code > > hw/isa/piix4: Use Proxy PIC device > > hw/isa/piix4: Reuse struct PIIXState from PIIX3 > > hw/isa/piix4: Rename reset control operations to match PIIX3 > > hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" > > hw/isa/piix3: Merge hw/isa/piix4.c > > hw/isa/piix: Harmonize names of
[PATCH 03/32] hw/isa/piix4: Correct IRQRC[A:D] reset values
From: Philippe Mathieu-Daudé IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-4-phi...@linaro.org> --- hw/isa/piix4.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8fc1db6dc9..0d23e11a39 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -116,10 +116,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; -pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 -pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 -pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 -pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 +pci_conf[0x60] = 0x80; +pci_conf[0x61] = 0x80; +pci_conf[0x62] = 0x80; +pci_conf[0x63] = 0x80; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; -- 2.38.1
[PATCH 04/32] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow --- configs/devices/mips-softmmu/common.mak | 2 -- hw/mips/Kconfig | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index 416161f833..7813fd1b41 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -18,10 +18,8 @@ CONFIG_PCSPK=y CONFIG_PCKBD=y CONFIG_FDC=y CONFIG_ACPI=y -CONFIG_ACPI_PIIX4=y CONFIG_APM=y CONFIG_I8257=y -CONFIG_PIIX4=y CONFIG_IDE_ISA=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 725525358d..4e7042f03d 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,6 +1,7 @@ config MALTA bool select ISA_SUPERIO +select PIIX4 config MIPSSIM bool -- 2.38.1
[PATCH 02/32] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
From: Philippe Mathieu-Daudé
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included values specific to
the Malta board.
Set the Malta-specific IRQ routing values in the embedded
bootloader, so the next commit can remove the Malta specific
bits from the PIIX4 PCI-ISA bridge and make it generic
(matching the real hardware).
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221027204720.33611-3-phi...@linaro.org>
---
hw/mips/malta.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9bffa1b128..c3dcd43f37 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -803,6 +803,8 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
stw_p(p++, 0x8422); stw_p(p++, 0x9088);
/* sw t0, 0x88(t1) */
+/* TODO set PIIX IRQC[A:D] routing values! */
+
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
@@ -840,6 +842,9 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
static void write_bootloader(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
+const char pci_pins_cfg[PCI_NUM_PINS] = {
+10, 10, 11, 11 /* PIIX IRQRC[A:D] */
+};
uint32_t *p;
/* Small bootloader */
@@ -914,6 +919,20 @@ static void write_bootloader(uint8_t *base, uint64_t
run_addr,
#undef cpu_to_gt32
+/*
+ * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
+ * Load the PIIX IRQC[A:D] routing config address, then
+ * write routing configuration to the config data register.
+ */
+bl_gen_write_u32(, /* GT_PCI0_CFGADDR */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be0 + 0xcf8),
+ tswap32((1 << 31) /* ConfigEn */
+ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
+ | PIIX_PIRQCA));
+bl_gen_write_u32(, /* GT_PCI0_CFGDATA */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be0 + 0xcfc),
+ tswap32(ldl_be_p(pci_pins_cfg)));
+
bl_gen_jump_kernel(,
true, ENVP_VADDR - 64,
/*
--
2.38.1
[PATCH 19/32] hw/isa/piix3: Rename typedef PIIX3State to PIIXState
This commit marks the finalization of the PIIX3 preparations
to be merged with PIIX4. In particular, PIIXState is prepared
to be reused in piix4.c.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-25-shen...@gmail.com>
---
hw/isa/piix3.c| 50 +--
include/hw/southbridge/piix.h | 4 +--
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 7faa699a3d..ff349c99ad 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -38,7 +38,7 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{
qemu_set_irq(piix3->pic.in_irqs[pic_irq],
!!(piix3->pic_levels &
@@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
(pic_irq * PIIX_NUM_PIRQS;
}
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int
level)
+static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
uint64_t mask;
@@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3,
int pirq, int level)
piix3->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
@@ -77,7 +77,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq,
int level)
static void piix3_set_irq(void *opaque, int pirq, int level)
{
-PIIX3State *piix3 = opaque;
+PIIXState *piix3 = opaque;
piix3_set_irq_level(piix3, pirq, level);
}
@@ -94,7 +94,7 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int
pci_intx)
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
-PIIX3State *piix3 = opaque;
+PIIXState *piix3 = opaque;
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
@@ -109,7 +109,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void
*opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
+static void piix3_update_irq_levels(PIIXState *piix3)
{
PCIBus *bus = pci_get_bus(>dev);
int pirq;
@@ -125,7 +125,7 @@ static void piix3_write_config(PCIDevice *dev,
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
-PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
int pic_irq;
pci_bus_fire_intx_routing_notifier(pci_get_bus(>dev));
@@ -158,7 +158,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
static void piix_reset(DeviceState *dev)
{
-PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -199,7 +199,7 @@ static void piix_reset(DeviceState *dev)
static int piix3_post_load(void *opaque, int version_id)
{
-PIIX3State *piix3 = opaque;
+PIIXState *piix3 = opaque;
int pirq;
/*
@@ -222,7 +222,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix3_pre_save(void *opaque)
{
int i;
-PIIX3State *piix3 = opaque;
+PIIXState *piix3 = opaque;
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
piix3->pci_irq_levels_vmstate[i] =
@@ -234,7 +234,7 @@ static int piix3_pre_save(void *opaque)
static bool piix3_rcr_needed(void *opaque)
{
-PIIX3State *piix3 = opaque;
+PIIXState *piix3 = opaque;
return (piix3->rcr != 0);
}
@@ -245,7 +245,7 @@ static const VMStateDescription vmstate_piix3_rcr = {
.minimum_version_id = 1,
.needed = piix3_rcr_needed,
.fields = (VMStateField[]) {
-VMSTATE_UINT8(rcr, PIIX3State),
+VMSTATE_UINT8(rcr, PIIXState),
VMSTATE_END_OF_LIST()
}
};
@@ -257,8 +257,8 @@ static const VMStateDescription vmstate_piix3 = {
.post_load = piix3_post_load,
.pre_save = piix3_pre_save,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(dev, PIIX3State),
-VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+VMSTATE_PCI_DEVICE(dev, PIIXState),
+VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
PIIX_NUM_PIRQS, 3),
VMSTATE_END_OF_LIST()
},
@@ -271,7 +271,7 @@ static const VMStateDescription vmstate_piix3 = {
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{
-PIIX3State *d = opaque;
+PIIXState *d = opaque;
if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -282,7 +282,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t
val, unsigned len)
static
[PATCH 14/32] hw/isa/piix3: Wire up ACPI interrupt internally
Now that PIIX3 has the PIC integrated, the ACPI controller can be wired
up internally.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-18-shen...@gmail.com>
---
hw/i386/pc_piix.c | 1 -
hw/isa/piix3.c| 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 19fe07a13b..dd4e89acf9 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -313,7 +313,6 @@ static void pc_init1(MachineState *machine,
if (piix4_pm) {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
-qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 3504ad16ca..0341284199 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -354,6 +354,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
return;
}
+qdev_connect_gpio_out(DEVICE(>pm), 0,
+ qdev_get_gpio_in(DEVICE(>pic), 9));
}
}
--
2.38.1
[PATCH 27/32] hw/isa/piix: Harmonize names of reset control memory regions
There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-38-shen...@gmail.com> --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 75001ce528..035f64b928 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -387,7 +387,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) isa_bus_irqs(isa_bus, d->pic.in_irqs); memory_region_init_io(>rcr_mem, OBJECT(dev), _ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, >rcr_mem, 1); @@ -585,7 +585,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } memory_region_init_io(>rcr_mem, OBJECT(dev), _ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, >rcr_mem, 1); -- 2.38.1
[PATCH 26/32] hw/isa/piix3: Merge hw/isa/piix4.c
Now that the PIIX3 and PIIX4 device models are sufficiently consolidated,
their implementations can be merged into one file for further
consolidation.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-37-shen...@gmail.com>
---
MAINTAINERS| 6 +-
hw/i386/Kconfig| 2 +-
hw/isa/Kconfig | 12 +-
hw/isa/meson.build | 3 +-
hw/isa/{piix3.c => piix.c} | 184 ++
hw/isa/piix4.c | 311 -
hw/mips/Kconfig| 2 +-
7 files changed, 191 insertions(+), 329 deletions(-)
rename hw/isa/{piix3.c => piix.c} (73%)
delete mode 100644 hw/isa/piix4.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b33fc7e091..ca0444dd15 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1223,7 +1223,7 @@ Malta
M: Philippe Mathieu-Daudé
R: Aurelien Jarno
S: Odd Fixes
-F: hw/isa/piix4.c
+F: hw/isa/piix.c
F: hw/acpi/piix4.c
F: hw/mips/malta.c
F: hw/mips/gt64xxx_pci.c
@@ -1640,7 +1640,7 @@ F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
-F: hw/isa/piix3.c
+F: hw/isa/piix.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
@@ -2330,7 +2330,7 @@ PIIX4 South Bridge (i82371AB)
M: Hervé Poussineau
M: Philippe Mathieu-Daudé
S: Maintained
-F: hw/isa/piix4.c
+F: hw/isa/piix.c
F: include/hw/southbridge/piix.h
Firmware configuration (fw_cfg)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 39a35467ca..15442ddbdf 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -74,7 +74,7 @@ config I440FX
select ACPI_SMBUS
select I8259
select PCI_I440FX
-select PIIX3
+select PIIX
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 4dfa3310d9..0f3284220b 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -31,17 +31,7 @@ config PC87312
select FDC_ISA
select IDE_ISA
-config PIIX3
-bool
-select ACPI_PIIX4
-select I8257
-select IDE_PIIX
-select ISA_BUS
-select MC146818RTC
-select PROXY_PIC
-select USB_UHCI
-
-config PIIX4
+config PIIX
bool
# For historical reasons, SuperIO devices are created in the board
# for PIIX4.
diff --git a/hw/isa/meson.build b/hw/isa/meson.build
index 8bf678ca0a..314bbd0860 100644
--- a/hw/isa/meson.build
+++ b/hw/isa/meson.build
@@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true:
files('i82378.c'))
softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c'))
softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c'))
softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c'))
-softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c'))
-softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c'))
+softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c'))
softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c'))
softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c'))
diff --git a/hw/isa/piix3.c b/hw/isa/piix.c
similarity index 73%
rename from hw/isa/piix3.c
rename to hw/isa/piix.c
index ff349c99ad..75001ce528 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix.c
@@ -2,6 +2,7 @@
* QEMU PIIX PCI ISA Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
deal
@@ -27,6 +28,7 @@
#include "qapi/error.h"
#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
+#include "hw/timer/i8254.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ide/piix.h"
@@ -81,6 +83,27 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
piix3_set_irq_level(piix3, pirq, level);
}
+static void piix4_set_irq(void *opaque, int irq_num, int level)
+{
+int i, pic_irq, pic_level;
+PIIXState *s = opaque;
+PCIBus *bus = pci_get_bus(>dev);
+
+/* now we change the pic irq level according to the piix irq mappings */
+/* XXX: optimize */
+pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
+if (pic_irq < ISA_NUM_IRQS) {
+/* The pic level is the logical OR of all the PCI irqs mapped to it. */
+pic_level = 0;
+for (i = 0; i < PIIX_NUM_PIRQS; i++) {
+if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
+pic_level |= pci_bus_get_irq_level(bus, i);
+}
+}
+qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level);
+}
+}
+
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
@@ -92,6 +115,31 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int
pci_intx)
return (pci_intx + slot_addend) & 3;
}
+static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+{
+int
[PATCH 28/32] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
Resolves duplicate code.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-39-shen...@gmail.com>
---
hw/isa/piix.c | 65 +++
1 file changed, 9 insertions(+), 56 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 035f64b928..f37851c5f4 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -367,7 +367,8 @@ static const MemoryRegionOps rcr_ops = {
},
};
-static void pci_piix3_realize(PCIDevice *dev, Error **errp)
+static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
+ Error **errp)
{
PIIXState *d = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
@@ -407,8 +408,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
/* USB */
if (d->has_usb) {
-object_initialize_child(OBJECT(dev), "uhci", >uhci,
-TYPE_PIIX3_USB_UHCI);
+object_initialize_child(OBJECT(dev), "uhci", >uhci, uhci_type);
qdev_prop_set_int32(DEVICE(>uhci), "addr", dev->devfn + 2);
if (!qdev_realize(DEVICE(>uhci), BUS(pci_bus), errp)) {
return;
@@ -513,7 +513,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
-pci_piix3_realize(dev, errp);
+pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
if (*errp) {
return;
}
@@ -543,7 +543,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp)
PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
-pci_piix3_realize(dev, errp);
+pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
if (*errp) {
return;
}
@@ -574,71 +574,24 @@ static const TypeInfo piix3_xen_info = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
+ERRP_GUARD();
PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
-isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
- pci_address_space_io(dev), errp);
-if (!isa_bus) {
-return;
-}
-
-memory_region_init_io(>rcr_mem, OBJECT(dev), _ops, s,
- "piix-reset-control", 1);
-memory_region_add_subregion_overlap(pci_address_space_io(dev),
-PIIX_RCR_IOPORT, >rcr_mem, 1);
-
-/* initialize i8259 pic */
-if (!qdev_realize(DEVICE(>pic), NULL, errp)) {
+pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp);
+if (*errp) {
return;
}
-/* initialize ISA irqs */
-isa_bus_irqs(isa_bus, s->pic.in_irqs);
+isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0"));
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
-/* DMA */
-i8257_dma_init(isa_bus, 0);
-
/* RTC */
-qdev_prop_set_int32(DEVICE(>rtc), "base_year", 2000);
-if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
-return;
-}
s->rtc.irq = qdev_get_gpio_in(DEVICE(>pic), s->rtc.isairq);
-/* IDE */
-qdev_prop_set_int32(DEVICE(>ide), "addr", dev->devfn + 1);
-if (!qdev_realize(DEVICE(>ide), BUS(pci_bus), errp)) {
-return;
-}
-
-/* USB */
-if (s->has_usb) {
-object_initialize_child(OBJECT(dev), "uhci", >uhci,
-TYPE_PIIX4_USB_UHCI);
-qdev_prop_set_int32(DEVICE(>uhci), "addr", dev->devfn + 2);
-if (!qdev_realize(DEVICE(>uhci), BUS(pci_bus), errp)) {
-return;
-}
-}
-
-/* ACPI controller */
-if (s->has_acpi) {
-object_initialize_child(OBJECT(s), "pm", >pm, TYPE_PIIX4_PM);
-qdev_prop_set_int32(DEVICE(>pm), "addr", dev->devfn + 3);
-qdev_prop_set_uint32(DEVICE(>pm), "smb_io_base", s->smb_io_base);
-qdev_prop_set_bit(DEVICE(>pm), "smm-enabled", s->smm_enabled);
-if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
-return;
-}
-qdev_connect_gpio_out(DEVICE(>pm), 0,
- qdev_get_gpio_in(DEVICE(>pic), 9));
-}
-
pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s,
PIIX_NUM_PIRQS);
}
--
2.38.1
[PATCH 00/32] Consolidate PIIX south bridges
This series consolidates the implementations of the PIIX3 and PIIX4 south bridges and is an extended version of [1]. The motivation is to share as much code as possible and to bring both device models to feature parity such that perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The series is structured as follows: First, PIIX3 is changed to instantiate internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared for the merge with PIIX4 which includes some fixes, cleanups, and renamings. Third, the same is done for PIIX4. In step four the implementations are merged. Since some consolidations could be done easier with merged implementations, the consolidation continues in step five which concludes the series. One particular challenge in this series was that the PIC of PIIX3 used to be instantiated outside of the south bridge while some sub functions require a PIC with populated qemu_irqs. This has been solved by introducing a proxy PIC which furthermore allows PIIX3 to be agnostic towards the virtualization technology used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. Another challenge was dealing with optional devices where Peter already gave advice in [1] which this series implements. A challenge still remains with consolidating PCI interrupt handling. There are still board-specific piix3_pci_slot_get_pirq() and piix4_pci_slot_get_pirq() which are implemented in isa/piix.c. Any advice how to resolve these would be highly appreaciated. See [2] for details. Last but not least there might be some opportunity to consolidate VM state handling, probably by reusing the one from PIIX3. Since I'm not very familiar with the requirements I didn't touch it so far. Testing done: * make check * make check-avocado * Boot live CD: * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` v3: - Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx (Philippe) - Make proxy PIC generic (Philippe) - Track Malta's PIIX dependencies through KConfig - Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' series [3] - Also rebase onto latest master to resolve merge conflicts. This required copying Philippe's series as first three patches - please ignore. v2: - Introduce TYPE_ defines for IDE and USB device models (Mark) - Omit unexporting of PIIXState (Mark) - Improve commit message of patch 5 to mention reset triggering through PCI configuration space (Mark) - Move reviewed patches w/o dependencies to the bottom of the series for early upstreaming [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html [2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html [3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html Bernhard Beschow (29): hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/i386/pc: Create RTC controllers in south bridges hw/i386/pc: No need for rtc_state to be an out-parameter hw/isa/piix3: Create USB controller in host device hw/isa/piix3: Create power management controller in host device hw/core: Introduce proxy-pic hw/isa/piix3: Create Proxy PIC in host device hw/isa/piix3: Create IDE controller in host device hw/isa/piix3: Wire up ACPI interrupt internally hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" hw/isa/piix3: Rename typedef PIIX3State to PIIXState hw/isa/piix4: Make PIIX4's ACPI and USB functions optional hw/isa/piix4: Remove unused code hw/isa/piix4: Use Proxy PIC device hw/isa/piix4: Reuse struct PIIXState from PIIX3 hw/isa/piix4: Rename reset control operations to match PIIX3 hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" hw/isa/piix3: Merge hw/isa/piix4.c hw/isa/piix: Harmonize names of reset control memory regions hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Rename functions to be shared for interrupt triggering hw/isa/piix: Consolidate IRQ triggering hw/isa/piix: Share PIIX3 base class with PIIX4 hw/isa/piix: Drop the "3" from the PIIX base class Philippe Mathieu-Daudé (3): hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader hw/isa/piix4:
[PATCH 23/32] hw/isa/piix4: Reuse struct PIIXState from PIIX3
Now that PIIX4 also uses the "proxy-pic", both implementations
can share the same struct.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-34-shen...@gmail.com>
---
hw/isa/piix4.c | 51 +++---
1 file changed, 15 insertions(+), 36 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0c34e3717c..c12388ddac 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -42,32 +42,10 @@
#include "sysemu/runstate.h"
#include "qom/object.h"
-struct PIIX4State {
-PCIDevice dev;
-
-ProxyPICState pic;
-RTCState rtc;
-PCIIDEState ide;
-UHCIState uhci;
-PIIX4PMState pm;
-
-uint32_t smb_io_base;
-
-/* Reset Control Register */
-MemoryRegion rcr_mem;
-uint8_t rcr;
-
-bool has_acpi;
-bool has_usb;
-bool smm_enabled;
-};
-
-OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
-
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
-PIIX4State *s = opaque;
+PIIXState *s = opaque;
PCIBus *bus = pci_get_bus(>dev);
/* now we change the pic irq level according to the piix irq mappings */
@@ -112,7 +90,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
static void piix4_isa_reset(DeviceState *dev)
{
-PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; // master, memory and I/O
@@ -147,12 +125,13 @@ static void piix4_isa_reset(DeviceState *dev)
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
+d->pic_levels = 0; /* not used in PIIX4 */
d->rcr = 0;
}
static int piix4_post_load(void *opaque, int version_id)
{
-PIIX4State *s = opaque;
+PIIXState *s = opaque;
if (version_id == 2) {
s->rcr = 0;
@@ -167,8 +146,8 @@ static const VMStateDescription vmstate_piix4 = {
.minimum_version_id = 2,
.post_load = piix4_post_load,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(dev, PIIX4State),
-VMSTATE_UINT8_V(rcr, PIIX4State, 3),
+VMSTATE_PCI_DEVICE(dev, PIIXState),
+VMSTATE_UINT8_V(rcr, PIIXState, 3),
VMSTATE_END_OF_LIST()
}
};
@@ -176,7 +155,7 @@ static const VMStateDescription vmstate_piix4 = {
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
-PIIX4State *s = opaque;
+PIIXState *s = opaque;
if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -188,7 +167,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr,
uint64_t val,
static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
{
-PIIX4State *s = opaque;
+PIIXState *s = opaque;
return s->rcr;
}
@@ -205,7 +184,7 @@ static const MemoryRegionOps piix4_rcr_ops = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
-PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
@@ -275,7 +254,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
static void piix4_init(Object *obj)
{
-PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+PIIXState *s = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
@@ -283,10 +262,10 @@ static void piix4_init(Object *obj)
}
static Property piix4_props[] = {
-DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0),
-DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true),
-DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true),
-DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false),
+DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
+DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
+DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -314,7 +293,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
.parent= TYPE_PCI_DEVICE,
-.instance_size = sizeof(PIIX4State),
+.instance_size = sizeof(PIIXState),
.instance_init = piix4_init,
.class_init= piix4_class_init,
.interfaces = (InterfaceInfo[]) {
--
2.38.1
[PATCH 32/32] hw/isa/piix: Drop the "3" from the PIIX base class
Now that the base class is used for both PIIX3 and PIIX4, the "3"
became misleading.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-43-shen...@gmail.com>
---
hw/isa/piix.c | 8
include/hw/southbridge/piix.h | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 70fe1166c1..84b27b36ea 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -469,7 +469,7 @@ static void pci_piix_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo piix_pci_type_info = {
-.name = TYPE_PIIX3_PCI_DEVICE,
+.name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIXState),
.instance_init = pci_piix_init,
@@ -519,7 +519,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
-.parent= TYPE_PIIX3_PCI_DEVICE,
+.parent= TYPE_PIIX_PCI_DEVICE,
.instance_init = piix3_init,
.class_init= piix3_class_init,
};
@@ -559,7 +559,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void
*data)
static const TypeInfo piix3_xen_info = {
.name = TYPE_PIIX3_XEN_DEVICE,
-.parent= TYPE_PIIX3_PCI_DEVICE,
+.parent= TYPE_PIIX_PCI_DEVICE,
.instance_init = piix3_init,
.class_init= piix3_xen_class_init,
};
@@ -608,7 +608,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
-.parent= TYPE_PIIX3_PCI_DEVICE,
+.parent= TYPE_PIIX_PCI_DEVICE,
.instance_init = piix4_init,
.class_init= piix4_class_init,
};
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index a489f52d1b..65ad8569da 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -72,11 +72,9 @@ struct PIIXState {
bool has_usb;
bool smm_enabled;
};
-typedef struct PIIXState PIIXState;
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE,
- TYPE_PIIX3_PCI_DEVICE)
+#define TYPE_PIIX_PCI_DEVICE "pci-piix"
+OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
--
2.38.1
[PATCH 05/32] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge
The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Message-Id: <20221022150508.26830-3-shen...@gmail.com> --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0ad0ed1603..e26509a935 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -218,7 +218,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; -pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); +pci_dev = pci_new_multifunction(-1, true, type); +pci_realize_and_unref(pci_dev, pci_bus, _fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; -- 2.38.1
[PATCH 11/32] hw/core: Introduce proxy-pic
Having a proxy PIC allows for ISA PICs to be created and wired up in
southbridges. This is especially useful for PIIX3 for two reasons:
First, the southbridge doesn't need to care about the virtualization
technology used (KVM, TCG, Xen) due to in-IRQs (where devices get
attached) and out-IRQs (which will trigger the IRQs of the respective
virtzalization technology) are separated. Second, since the in-IRQs are
populated with fully initialized qemu_irq's, they can already be wired
up inside PIIX3.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-15-shen...@gmail.com>
---
MAINTAINERS | 2 ++
hw/core/Kconfig | 3 ++
hw/core/meson.build | 1 +
hw/core/proxy-pic.c | 70 +
include/hw/core/proxy-pic.h | 54
5 files changed, 130 insertions(+)
create mode 100644 hw/core/proxy-pic.c
create mode 100644 include/hw/core/proxy-pic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6966490c94..b33fc7e091 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1660,6 +1660,7 @@ S: Supported
F: hw/char/debugcon.c
F: hw/char/parallel*
F: hw/char/serial*
+F: hw/core/proxy-pic.c
F: hw/dma/i8257*
F: hw/i2c/pm_smbus.c
F: hw/input/pckbd.c
@@ -1676,6 +1677,7 @@ F: hw/watchdog/wdt_ib700.c
F: hw/watchdog/wdt_i6300esb.c
F: include/hw/display/vga.h
F: include/hw/char/parallel.h
+F: include/hw/core/proxy-pic.h
F: include/hw/dma/i8257.h
F: include/hw/i2c/pm_smbus.h
F: include/hw/input/i8042.h
diff --git a/hw/core/Kconfig b/hw/core/Kconfig
index 9397503656..a7224f4ca0 100644
--- a/hw/core/Kconfig
+++ b/hw/core/Kconfig
@@ -22,6 +22,9 @@ config OR_IRQ
config PLATFORM_BUS
bool
+config PROXY_PIC
+bool
+
config REGISTER
bool
diff --git a/hw/core/meson.build b/hw/core/meson.build
index 7a4d02b6c0..e86aef6ec3 100644
--- a/hw/core/meson.build
+++ b/hw/core/meson.build
@@ -30,6 +30,7 @@ softmmu_ss.add(when: ['CONFIG_GUEST_LOADER', fdt], if_true:
files('guest-loader.
softmmu_ss.add(when: 'CONFIG_OR_IRQ', if_true: files('or-irq.c'))
softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('platform-bus.c'))
softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
+softmmu_ss.add(when: 'CONFIG_PROXY_PIC', if_true: files('proxy-pic.c'))
softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
diff --git a/hw/core/proxy-pic.c b/hw/core/proxy-pic.c
new file mode 100644
index 00..3251727d19
--- /dev/null
+++ b/hw/core/proxy-pic.c
@@ -0,0 +1,70 @@
+/*
+ * Proxy interrupt controller device.
+ *
+ * Copyright (c) 2022 Bernhard Beschow
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/core/proxy-pic.h"
+
+static void proxy_pic_set_irq(void *opaque, int irq, int level)
+{
+ProxyPICState *s = opaque;
+
+qemu_set_irq(s->out_irqs[irq], level);
+}
+
+static void proxy_pic_realize(DeviceState *dev, Error **errp)
+{
+ProxyPICState *s = PROXY_PIC(dev);
+
+qdev_init_gpio_in(DEVICE(s), proxy_pic_set_irq, MAX_PROXY_PIC_LINES);
+qdev_init_gpio_out(DEVICE(s), s->out_irqs, MAX_PROXY_PIC_LINES);
+
+for (int i = 0; i < MAX_PROXY_PIC_LINES; ++i) {
+s->in_irqs[i] = qdev_get_gpio_in(DEVICE(s), i);
+}
+}
+
+static void proxy_pic_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+/* No state to reset or migrate */
+dc->realize = proxy_pic_realize;
+
+/* Reason: Needs to be wired up to work */
+dc->user_creatable = false;
+}
+
+static const TypeInfo proxy_pic_info = {
+.name = TYPE_PROXY_PIC,
+.parent= TYPE_DEVICE,
+.instance_size = sizeof(ProxyPICState),
+.class_init = proxy_pic_class_init,
+};
+
+static void split_irq_register_types(void)
+{
+
[PATCH 06/32] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-10-shen...@gmail.com>
---
hw/i386/pc_piix.c | 3 ++-
hw/i386/pc_q35.c | 13 +++--
hw/isa/piix4.c| 2 +-
hw/usb/hcd-uhci.c | 16
hw/usb/hcd-uhci.h | 4
5 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e26509a935..caa983d76e 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -50,6 +50,7 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
+#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -291,7 +292,7 @@ static void pc_init1(MachineState *machine,
#endif
if (pcmc->pci_enabled && machine_usb(machine)) {
-pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
+pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
}
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a496bd6e74..1da6d34339 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -48,6 +48,7 @@
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/usb.h"
+#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/numa.h"
@@ -65,15 +66,15 @@ struct ehci_companions {
};
static const struct ehci_companions ich9_1d[] = {
-{ .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
-{ .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
-{ .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
+{ .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
+{ .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
+{ .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
};
static const struct ehci_companions ich9_1a[] = {
-{ .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
-{ .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
-{ .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
+{ .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
+{ .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
+{ .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
};
static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0d23e11a39..aceb21ee3e 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -280,7 +280,7 @@ static void piix4_init(Object *obj)
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", >ide, TYPE_PIIX4_IDE);
-object_initialize_child(obj, "uhci", >uhci, "piix4-usb-uhci");
+object_initialize_child(obj, "uhci", >uhci, TYPE_PIIX4_USB_UHCI);
object_initialize_child(obj, "pm", >pm, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(>pm), "smb_io_base", 0x1100);
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index d1b5657d72..30ae0104bb 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void
*data)
static UHCIInfo uhci_info[] = {
{
-.name = "piix3-usb-uhci",
+.name = TYPE_PIIX3_USB_UHCI,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
.revision = 0x01,
.irq_pin = 3,
.unplug= true,
},{
-.name = "piix4-usb-uhci",
+.name = TYPE_PIIX4_USB_UHCI,
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
.revision = 0x01,
.irq_pin = 3,
.unplug= true,
},{
-.name = "ich9-usb-uhci1", /* 00:1d.0 */
+.name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
.revision = 0x03,
.irq_pin = 0,
.unplug= false,
},{
-.name = "ich9-usb-uhci2", /* 00:1d.1 */
+.name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
.revision = 0x03,
.irq_pin = 1,
.unplug= false,
},{
-.name = "ich9-usb-uhci3", /* 00:1d.2 */
+.name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
.revision = 0x03,
.irq_pin = 2,
.unplug= false,
},{
-.name = "ich9-usb-uhci4", /* 00:1a.0 */
+.name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */
.vendor_id = PCI_VENDOR_ID_INTEL,
.device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
.revision = 0x03,
.irq_pin = 0,
.unplug= false,
},{
-.name = "ich9-usb-uhci5", /* 00:1a.1 */
+.name =
[PATCH 29/32] hw/isa/piix: Rename functions to be shared for interrupt triggering
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-40-shen...@gmail.com>
---
hw/isa/piix.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index f37851c5f4..3d1659e5fd 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -40,47 +40,47 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
-static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
+static void piix_set_irq_pic(PIIXState *piix, int pic_irq)
{
-qemu_set_irq(piix3->pic.in_irqs[pic_irq],
- !!(piix3->pic_levels &
+qemu_set_irq(piix->pic.in_irqs[pic_irq],
+ !!(piix->pic_levels &
(((1ULL << PIIX_NUM_PIRQS) - 1) <<
(pic_irq * PIIX_NUM_PIRQS;
}
-static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
+static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int level)
{
int pic_irq;
uint64_t mask;
-pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+pic_irq = piix->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
-piix3->pic_levels &= ~mask;
-piix3->pic_levels |= mask * !!level;
+piix->pic_levels &= ~mask;
+piix->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
+static void piix_set_irq_level(PIIXState *piix, int pirq, int level)
{
int pic_irq;
-pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+pic_irq = piix->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
-piix3_set_irq_level_internal(piix3, pirq, level);
+piix_set_irq_level_internal(piix, pirq, level);
-piix3_set_irq_pic(piix3, pic_irq);
+piix_set_irq_pic(piix, pic_irq);
}
-static void piix3_set_irq(void *opaque, int pirq, int level)
+static void piix_set_irq(void *opaque, int pirq, int level)
{
-PIIXState *piix3 = opaque;
-piix3_set_irq_level(piix3, pirq, level);
+PIIXState *piix = opaque;
+piix_set_irq_level(piix, pirq, level);
}
static void piix4_set_irq(void *opaque, int irq_num, int level)
@@ -157,29 +157,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void
*opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIXState *piix3)
+static void piix_update_irq_levels(PIIXState *piix)
{
-PCIBus *bus = pci_get_bus(>dev);
+PCIBus *bus = pci_get_bus(>dev);
int pirq;
-piix3->pic_levels = 0;
+piix->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq));
}
}
-static void piix3_write_config(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
+static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val,
+ int len)
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
-PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
+PIIXState *piix = PIIX_PCI_DEVICE(dev);
int pic_irq;
-pci_bus_fire_intx_routing_notifier(pci_get_bus(>dev));
-piix3_update_irq_levels(piix3);
+pci_bus_fire_intx_routing_notifier(pci_get_bus(>dev));
+piix_update_irq_levels(piix);
for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
-piix3_set_irq_pic(piix3, pic_irq);
+piix_set_irq_pic(piix, pic_irq);
}
}
}
@@ -201,7 +201,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
}
}
-piix3_write_config(dev, address, val, len);
+piix_write_config(dev, address, val, len);
}
static void piix_reset(DeviceState *dev)
@@ -261,7 +261,7 @@ static int piix3_post_load(void *opaque, int version_id)
*/
piix3->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-piix3_set_irq_level_internal(piix3, pirq,
+piix_set_irq_level_internal(piix3, pirq,
pci_bus_get_irq_level(pci_get_bus(>dev), pirq));
}
return 0;
@@ -518,7 +518,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
-pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq,
+pci_bus_irqs(pci_bus, piix_set_irq, piix3_pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
@@ -527,7 +527,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-k->config_write = piix3_write_config;
+k->config_write = piix_write_config;
[PATCH 24/32] hw/isa/piix4: Rename reset control operations to match PIIX3
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-35-shen...@gmail.com>
---
hw/isa/piix4.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index c12388ddac..13ec2503d0 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -152,7 +152,7 @@ static const VMStateDescription vmstate_piix4 = {
}
};
-static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
PIIXState *s = opaque;
@@ -165,16 +165,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr,
uint64_t val,
s->rcr = val & 2; /* keep System Reset type only */
}
-static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len)
{
PIIXState *s = opaque;
return s->rcr;
}
-static const MemoryRegionOps piix4_rcr_ops = {
-.read = piix4_rcr_read,
-.write = piix4_rcr_write,
+static const MemoryRegionOps rcr_ops = {
+.read = rcr_read,
+.write = rcr_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
@@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
-memory_region_init_io(>rcr_mem, OBJECT(dev), _rcr_ops, s,
+memory_region_init_io(>rcr_mem, OBJECT(dev), _ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, >rcr_mem, 1);
--
2.38.1
[PATCH 10/32] hw/isa/piix3: Create power management controller in host device
The power management controller is an integral part of PIIX3 (function
3). So create it as part of the south bridge.
Note that the ACPI function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-14-shen...@gmail.com>
---
hw/i386/pc_piix.c | 23 +--
hw/isa/Kconfig| 1 +
hw/isa/piix3.c| 14 ++
include/hw/southbridge/piix.h | 6 ++
4 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 22c1c5404c..c96d989636 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -46,11 +46,11 @@
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "hw/sysbus.h"
+#include "hw/i2c/i2c.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/xen/xen-x86.h"
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
-#include "hw/acpi/piix4.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -85,6 +85,7 @@ static void pc_init1(MachineState *machine,
MemoryRegion *system_io = get_system_io();
PCIBus *pci_bus;
ISABus *isa_bus;
+Object *piix4_pm;
int piix3_devfn = -1;
qemu_irq smi_irq;
GSIState *gsi_state;
@@ -222,6 +223,13 @@ static void pc_init1(MachineState *machine,
pci_dev = pci_new_multifunction(-1, true, type);
object_property_set_bool(OBJECT(pci_dev), "has-usb",
machine_usb(machine), _abort);
+object_property_set_bool(OBJECT(pci_dev), "has-acpi",
+ x86_machine_is_acpi_enabled(x86ms),
+ _abort);
+qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
+object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
+ x86_machine_is_smm_enabled(x86ms),
+ _abort);
pci_realize_and_unref(pci_dev, pci_bus, _fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -229,8 +237,10 @@ static void pc_init1(MachineState *machine,
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
+piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
} else {
pci_bus = NULL;
+piix4_pm = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
_abort);
@@ -300,15 +310,8 @@ static void pc_init1(MachineState *machine,
}
#endif
-if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
-PCIDevice *piix4_pm;
-
+if (piix4_pm) {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
-piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM);
-qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100);
-qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled",
- x86_machine_is_smm_enabled(x86ms));
-pci_realize_and_unref(piix4_pm, pci_bus, _fatal);
qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
@@ -322,7 +325,7 @@ static void pc_init1(MachineState *machine,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
- OBJECT(piix4_pm), _abort);
+ piix4_pm, _abort);
}
if (machine->nvdimms_state->is_enabled) {
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 97b8ea7c06..6c154d88c7 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -33,6 +33,7 @@ config PC87312
config PIIX3
bool
+select ACPI_PIIX4
select I8257
select ISA_BUS
select MC146818RTC
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index af1c5b9859..cb2d9285ae 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -330,6 +330,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
return;
}
}
+
+/* Power Management */
+if (d->has_acpi) {
+object_initialize_child(OBJECT(d), "pm", >pm, TYPE_PIIX4_PM);
+qdev_prop_set_int32(DEVICE(>pm), "addr", dev->devfn + 3);
+qdev_prop_set_uint32(DEVICE(>pm), "smb_io_base", d->smb_io_base);
+qdev_prop_set_bit(DEVICE(>pm), "smm-enabled", d->smm_enabled);
+if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
+return;
+}
+}
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -364,7 +375,10 @@ static void pci_piix3_init(Object *obj)
}
static Property pci_piix3_props[] = {
+
[PATCH 07/32] hw/i386/pc: Create RTC controllers in south bridges
Just like in the real hardware (and in PIIX4), create the RTC
controllers in the south bridges.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-11-shen...@gmail.com>
---
hw/i386/pc.c | 12 +++-
hw/i386/pc_piix.c | 8
hw/i386/pc_q35.c | 1 +
hw/isa/Kconfig| 2 ++
hw/isa/lpc_ich9.c | 8
hw/isa/piix3.c| 15 +++
include/hw/i386/ich9.h| 2 ++
include/hw/southbridge/piix.h | 3 +++
8 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 546b703cb4..9379cf4374 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1299,7 +1299,17 @@ void pc_basic_device_init(struct PCMachineState *pcms,
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
}
-*rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
+
+if (rtc_irq) {
+qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq);
+} else {
+uint32_t irq = object_property_get_uint(OBJECT(*rtc_state),
+"irq",
+_fatal);
+isa_connect_gpio_out(*rtc_state, 0, irq);
+}
+object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state),
+ "date");
qemu_register_boot_set(pc_boot_set, *rtc_state);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index caa983d76e..7de2f1092b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -32,6 +32,7 @@
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
#include "hw/pci-host/i440fx.h"
+#include "hw/rtc/mc146818rtc.h"
#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
@@ -225,10 +226,17 @@ static void pc_init1(MachineState *machine,
piix3->pic = x86ms->gsi;
piix3_devfn = piix3->dev.devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
+ "rtc"));
} else {
pci_bus = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
_abort);
+
+rtc_state = isa_new(TYPE_MC146818_RTC);
+qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
+isa_realize_and_unref(rtc_state, isa_bus, _fatal);
+
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 1da6d34339..b5cd876dc2 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -239,6 +239,7 @@ static void pc_q35_init(MachineState *machine)
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
+rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 18b5c6bf3f..af5ec9cd61 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -35,6 +35,7 @@ config PIIX3
bool
select I8257
select ISA_BUS
+select MC146818RTC
config PIIX4
bool
@@ -79,3 +80,4 @@ config LPC_ICH9
select ISA_BUS
select ACPI_SMBUS
select ACPI_X86_ICH
+select MC146818RTC
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 6c44cc9767..eb230a1a23 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj)
static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
+
object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
>sci_gsi, OBJ_PROP_FLAG_READ);
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
@@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
isa_bus_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
+
+/* RTC */
+qdev_prop_set_int32(DEVICE(>rtc), "base_year", 2000);
+if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
+return;
+}
}
static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index eabad7ba58..c68e51ddad 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -28,6 +28,7 @@
#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "hw/xen/xen.h"
#include "sysemu/runstate.h"
@@ -312,6 +313,12 @@ static void
[PATCH 09/32] hw/isa/piix3: Create USB controller in host device
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-13-shen...@gmail.com>
---
hw/i386/pc_piix.c | 7 ++-
hw/isa/Kconfig| 1 +
hw/isa/piix3.c| 17 +
include/hw/southbridge/piix.h | 4
4 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b97bff5674..22c1c5404c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine,
pcms->bus = pci_bus;
pci_dev = pci_new_multifunction(-1, true, type);
+object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), _abort);
pci_realize_and_unref(pci_dev, pci_bus, _fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine,
}
#endif
-if (pcmc->pci_enabled && machine_usb(machine)) {
-pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
-}
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index af5ec9cd61..97b8ea7c06 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -36,6 +36,7 @@ config PIIX3
select I8257
select ISA_BUS
select MC146818RTC
+select USB_UHCI
config PIIX4
bool
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index c68e51ddad..af1c5b9859 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -299,6 +299,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
@@ -319,6 +320,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
return;
}
+
+/* USB */
+if (d->has_usb) {
+object_initialize_child(OBJECT(dev), "uhci", >uhci,
+TYPE_PIIX3_USB_UHCI);
+qdev_prop_set_int32(DEVICE(>uhci), "addr", dev->devfn + 2);
+if (!qdev_realize(DEVICE(>uhci), BUS(pci_bus), errp)) {
+return;
+}
+}
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -352,6 +363,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
}
+static Property pci_piix3_props[] = {
+DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -371,6 +387,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b1fa08dd2b..5367917182 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
RTCState rtc;
+UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+bool has_usb;
};
typedef struct PIIXState PIIX3State;
--
2.38.1
[PATCH 31/32] hw/isa/piix: Share PIIX3 base class with PIIX4
Having a common base class allows for substituting PIIX3 with PIIX4
and vice versa. Moreover, it makes PIIX4 implement the
acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-42-shen...@gmail.com>
---
hw/isa/piix.c | 53 +++
1 file changed, 24 insertions(+), 29 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index d05f1aa4ff..70fe1166c1 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -432,13 +432,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml
*scope)
}
}
-static void pci_piix3_init(Object *obj)
+static void pci_piix_init(Object *obj)
{
PIIXState *d = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
-object_initialize_child(obj, "ide", >ide, TYPE_PIIX3_IDE);
}
static Property pci_piix_props[] = {
@@ -449,7 +448,7 @@ static Property pci_piix_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
+static void pci_piix_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -457,11 +456,8 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
dc->reset = piix_reset;
dc->desc= "ISA bridge";
-dc->vmsd= _piix3;
dc->hotpluggable = false;
k->vendor_id= PCI_VENDOR_ID_INTEL;
-/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
-k->device_id= PCI_DEVICE_ID_INTEL_82371SB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;
/*
* Reason: part of PIIX3 southbridge, needs to be wired up by
@@ -472,13 +468,13 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
adevc->build_dev_aml = build_pci_isa_aml;
}
-static const TypeInfo piix3_pci_type_info = {
+static const TypeInfo piix_pci_type_info = {
.name = TYPE_PIIX3_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIXState),
-.instance_init = pci_piix3_init,
+.instance_init = pci_piix_init,
.abstract = true,
-.class_init = pci_piix3_class_init,
+.class_init = pci_piix_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ TYPE_ACPI_DEV_AML_IF },
@@ -502,17 +498,29 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
+static void piix3_init(Object *obj)
+{
+PIIXState *d = PIIX_PCI_DEVICE(obj);
+
+object_initialize_child(obj, "ide", >ide, TYPE_PIIX3_IDE);
+}
+
static void piix3_class_init(ObjectClass *klass, void *data)
{
+DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix_write_config;
k->realize = piix3_realize;
+/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+dc->vmsd = _piix3;
}
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
.parent= TYPE_PIIX3_PCI_DEVICE,
+.instance_init = piix3_init,
.class_init= piix3_class_init,
};
@@ -539,15 +547,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error
**errp)
static void piix3_xen_class_init(ObjectClass *klass, void *data)
{
+DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config_xen;
k->realize = piix3_xen_realize;
+/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+dc->vmsd = _piix3;
}
static const TypeInfo piix3_xen_info = {
.name = TYPE_PIIX3_XEN_DEVICE,
.parent= TYPE_PIIX3_PCI_DEVICE,
+.instance_init = piix3_init,
.class_init= piix3_xen_class_init,
};
@@ -579,8 +592,6 @@ static void piix4_init(Object *obj)
{
PIIXState *s = PIIX_PCI_DEVICE(obj);
-object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
-object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", >ide, TYPE_PIIX4_IDE);
}
@@ -591,36 +602,20 @@ static void piix4_class_init(ObjectClass *klass, void
*data)
k->config_write = piix_write_config;
k->realize = piix4_realize;
-k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
-k->class_id = PCI_CLASS_BRIDGE_ISA;
-dc->reset = piix_reset;
-dc->desc = "ISA bridge";
dc->vmsd = _piix4;
-/*
- * Reason: part of PIIX4 southbridge, needs to be wired up,
- * e.g. by mips_malta_init()
- */
-dc->user_creatable = false;
-dc->hotpluggable = false;
-device_class_set_props(dc, pci_piix_props);
}
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
-.parent=
[PATCH 16/32] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-22-shen...@gmail.com>
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 7ee706243a..a811a9bdab 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -392,7 +392,7 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "ide", >ide, TYPE_PIIX3_IDE);
}
-static Property pci_piix3_props[] = {
+static Property pci_piix_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true),
DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
@@ -419,7 +419,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
-device_class_set_props(dc, pci_piix3_props);
+device_class_set_props(dc, pci_piix_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
--
2.38.1
[PATCH 17/32] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-23-shen...@gmail.com>
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index a811a9bdab..e99622699a 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -156,7 +156,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
piix3_write_config(dev, address, val, len);
}
-static void piix3_reset(DeviceState *dev)
+static void piix_reset(DeviceState *dev)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
@@ -406,7 +406,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
-dc->reset = piix3_reset;
+dc->reset = piix_reset;
dc->desc= "ISA bridge";
dc->vmsd= _piix3;
dc->hotpluggable = false;
--
2.38.1
[PATCH 30/32] hw/isa/piix: Consolidate IRQ triggering
Speeds up PIIX4 which resolves an old TODO.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-41-shen...@gmail.com>
---
hw/isa/piix.c | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 3d1659e5fd..d05f1aa4ff 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int level)
piix_set_irq_level(piix, pirq, level);
}
-static void piix4_set_irq(void *opaque, int irq_num, int level)
-{
-int i, pic_irq, pic_level;
-PIIXState *s = opaque;
-PCIBus *bus = pci_get_bus(>dev);
-
-/* now we change the pic irq level according to the piix irq mappings */
-/* XXX: optimize */
-pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
-if (pic_irq < ISA_NUM_IRQS) {
-/* The pic level is the logical OR of all the PCI irqs mapped to it. */
-pic_level = 0;
-for (i = 0; i < PIIX_NUM_PIRQS; i++) {
-if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
-pic_level |= pci_bus_get_irq_level(bus, i);
-}
-}
-qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level);
-}
-}
-
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
@@ -275,7 +254,7 @@ static int piix4_post_load(void *opaque, int version_id)
s->rcr = 0;
}
-return 0;
+return piix3_post_load(opaque, version_id);
}
static int piix3_pre_save(void *opaque)
@@ -592,7 +571,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* RTC */
s->rtc.irq = qdev_get_gpio_in(DEVICE(>pic), s->rtc.isairq);
-pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s,
+pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s,
PIIX_NUM_PIRQS);
}
@@ -610,6 +589,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+k->config_write = piix_write_config;
k->realize = piix4_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
--
2.38.1
[PATCH 08/32] hw/i386/pc: No need for rtc_state to be an out-parameter
Now that the RTC is created as part of the southbridges it doesn't need
to be an out-parameter any longer.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Message-Id: <20221022150508.26830-12-shen...@gmail.com>
---
hw/i386/pc.c | 12 ++--
hw/i386/pc_piix.c| 2 +-
hw/i386/pc_q35.c | 2 +-
include/hw/i386/pc.h | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9379cf4374..beb5f4d313 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1246,7 +1246,7 @@ static void pc_superio_init(ISABus *isa_bus, bool
create_fdctrl,
void pc_basic_device_init(struct PCMachineState *pcms,
ISABus *isa_bus, qemu_irq *gsi,
- ISADevice **rtc_state,
+ ISADevice *rtc_state,
bool create_fdctrl,
uint32_t hpet_irqs)
{
@@ -1301,17 +1301,17 @@ void pc_basic_device_init(struct PCMachineState *pcms,
}
if (rtc_irq) {
-qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq);
+qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
} else {
-uint32_t irq = object_property_get_uint(OBJECT(*rtc_state),
+uint32_t irq = object_property_get_uint(OBJECT(rtc_state),
"irq",
_fatal);
-isa_connect_gpio_out(*rtc_state, 0, irq);
+isa_connect_gpio_out(rtc_state, 0, irq);
}
-object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state),
+object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
"date");
-qemu_register_boot_set(pc_boot_set, *rtc_state);
+qemu_register_boot_set(pc_boot_set, rtc_state);
if (!xen_enabled() &&
(x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 7de2f1092b..b97bff5674 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine,
}
/* init basic PC hardware */
-pc_basic_device_init(pcms, isa_bus, x86ms->gsi, _state, true,
+pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true,
0x4);
pc_nic_init(pcmc, isa_bus, pci_bus);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index b5cd876dc2..c88f4448d9 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -293,7 +293,7 @@ static void pc_q35_init(MachineState *machine)
}
/* init basic PC hardware */
-pc_basic_device_init(pcms, isa_bus, x86ms->gsi, _state, !mc->no_floppy,
+pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy,
0xff0104);
/* connect pm stuff to lpc */
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c95333514e..0cf3ccdf0d 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -169,7 +169,7 @@ uint64_t pc_pci_hole64_start(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(struct PCMachineState *pcms,
ISABus *isa_bus, qemu_irq *gsi,
- ISADevice **rtc_state,
+ ISADevice *rtc_state,
bool create_fdctrl,
uint32_t hpet_irqs);
void pc_cmos_init(PCMachineState *pcms,
--
2.38.1
[PATCH 13/32] hw/isa/piix3: Create IDE controller in host device
Now that PIIX3 contains the new isa-pic, it is possible to instantiate
PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to
the ISA bus in its realize method which requires the interrupt
controller to provide fully populated qemu_irqs. This is the case for
isa-pic even though the virtualization technology not known yet.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-17-shen...@gmail.com>
---
hw/i386/Kconfig | 1 -
hw/i386/pc_piix.c | 15 ++-
hw/isa/Kconfig| 1 +
hw/isa/piix3.c| 8
include/hw/southbridge/piix.h | 2 ++
5 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 79f5925dbe..39a35467ca 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -75,7 +75,6 @@ config I440FX
select I8259
select PCI_I440FX
select PIIX3
-select IDE_PIIX
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index f81e91220f..19fe07a13b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -41,7 +41,6 @@
#include "hw/usb.h"
#include "net/net.h"
#include "hw/ide/pci.h"
-#include "hw/ide/piix.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
@@ -86,7 +85,6 @@ static void pc_init1(MachineState *machine,
PCIBus *pci_bus;
ISABus *isa_bus;
Object *piix4_pm;
-int piix3_devfn = -1;
qemu_irq smi_irq;
GSIState *gsi_state;
BusState *idebus[MAX_IDE_BUS];
@@ -236,11 +234,14 @@ static void pc_init1(MachineState *machine,
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out(dev, i, x86ms->gsi[i]);
}
-piix3_devfn = pci_dev->devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
+dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
+pci_ide_create_devs(PCI_DEVICE(dev));
+idebus[0] = qdev_get_child_bus(dev, "ide.0");
+idebus[1] = qdev_get_child_bus(dev, "ide.1");
} else {
pci_bus = NULL;
piix4_pm = NULL;
@@ -254,6 +255,8 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
+idebus[0] = NULL;
+idebus[1] = NULL;
}
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
@@ -282,12 +285,6 @@ static void pc_init1(MachineState *machine,
pc_nic_init(pcmc, isa_bus, pci_bus);
if (pcmc->pci_enabled) {
-PCIDevice *dev;
-
-dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE);
-pci_ide_create_devs(dev);
-idebus[0] = qdev_get_child_bus(>qdev, "ide.0");
-idebus[1] = qdev_get_child_bus(>qdev, "ide.1");
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
}
#ifdef CONFIG_IDE_ISA
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index b4ad1fb66e..8bf6462798 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -35,6 +35,7 @@ config PIIX3
bool
select ACPI_PIIX4
select I8257
+select IDE_PIIX
select ISA_BUS
select MC146818RTC
select PROXY_PIC
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 199cbf1e14..3504ad16ca 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -29,6 +29,7 @@
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
#include "hw/xen/xen.h"
#include "sysemu/runstate.h"
@@ -328,6 +329,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
return;
}
+/* IDE */
+qdev_prop_set_int32(DEVICE(>ide), "addr", dev->devfn + 1);
+if (!qdev_realize(DEVICE(>ide), BUS(pci_bus), errp)) {
+return;
+}
+
/* USB */
if (d->has_usb) {
object_initialize_child(OBJECT(dev), "uhci", >uhci,
@@ -380,6 +387,7 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
+object_initialize_child(obj, "ide", >ide, TYPE_PIIX3_IDE);
}
static Property pci_piix3_props[] = {
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 7b1b4625a3..c4e6e9f827 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -16,6 +16,7 @@
#include "qom/object.h"
#include "hw/acpi/piix4.h"
#include "hw/core/proxy-pic.h"
+#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/usb/hcd-uhci.h"
@@ -56,6 +57,7 @@ struct PIIXState {
ProxyPICState pic;
RTCState rtc;
+PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
--
2.38.1
[PATCH 18/32] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"
The additional prefix aligns the function name with both other
piix3-internal functions as well as QEMU conventions. Furthermore, it
will help to distinguish the function from its PIIX4 counterpart once
merged.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-24-shen...@gmail.com>
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index e99622699a..7faa699a3d 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -85,7 +85,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
*/
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
@@ -448,7 +448,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
-pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
--
2.38.1
[PATCH 01/32] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition
From: Philippe Mathieu-Daudé
The PIIX4 PCI-ISA bridge function is always located at 10:0.
Since we want to re-use its address, add the PIIX4_PCI_DEVFN
definition.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221027204720.33611-2-phi...@linaro.org>
---
hw/mips/malta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index c0a2e0ab04..9bffa1b128 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -71,6 +71,8 @@
#define FLASH_SIZE 0x40
+#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
+
typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_lo; /* 0 - 0x900 */
@@ -1401,7 +1403,7 @@ void mips_malta_init(MachineState *machine)
empty_slot_init("GT64120", 0, 0x2000);
/* Southbridge */
-piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true,
+piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true,
TYPE_PIIX4_PCI_DEVICE);
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
--
2.38.1
[PATCH 12/32] hw/isa/piix3: Create Proxy PIC in host device
Use the newly introduced TYPE_PROXY_PIC which allows for wiring
up devices in the southbridge where the virtualization technology used
(KVM, TCG, Xen) is not yet known.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-16-shen...@gmail.com>
---
hw/i386/Kconfig | 1 +
hw/i386/pc_piix.c | 15 +--
hw/isa/Kconfig| 1 +
hw/isa/piix3.c| 10 +-
include/hw/southbridge/piix.h | 4 ++--
5 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index d22ac4a4b9..79f5925dbe 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -72,6 +72,7 @@ config I440FX
select PC_PCI
select PC_ACPI
select ACPI_SMBUS
+select I8259
select PCI_I440FX
select PIIX3
select IDE_PIIX
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c96d989636..f81e91220f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -207,10 +207,11 @@ static void pc_init1(MachineState *machine,
gsi_state = pc_gsi_create(>gsi, pcmc->pci_enabled);
if (pcmc->pci_enabled) {
-PIIX3State *piix3;
+DeviceState *dev;
PCIDevice *pci_dev;
const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE
: TYPE_PIIX3_DEVICE;
+int i;
pci_bus = i440fx_init(pci_type,
i440fx_host,
@@ -231,10 +232,12 @@ static void pc_init1(MachineState *machine,
x86_machine_is_smm_enabled(x86ms),
_abort);
pci_realize_and_unref(pci_dev, pci_bus, _fatal);
-piix3 = PIIX3_PCI_DEVICE(pci_dev);
-piix3->pic = x86ms->gsi;
-piix3_devfn = piix3->dev.devfn;
-isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic"));
+for (i = 0; i < ISA_NUM_IRQS; i++) {
+qdev_connect_gpio_out(dev, i, x86ms->gsi[i]);
+}
+piix3_devfn = pci_dev->devfn;
+isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
@@ -243,6 +246,7 @@ static void pc_init1(MachineState *machine,
piix4_pm = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
_abort);
+isa_bus_irqs(isa_bus, x86ms->gsi);
rtc_state = isa_new(TYPE_MC146818_RTC);
qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
@@ -251,7 +255,6 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
-isa_bus_irqs(isa_bus, x86ms->gsi);
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 6c154d88c7..b4ad1fb66e 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,7 @@ config PIIX3
select I8257
select ISA_BUS
select MC146818RTC
+select PROXY_PIC
select USB_UHCI
config PIIX4
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index cb2d9285ae..199cbf1e14 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -39,7 +39,7 @@
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
-qemu_set_irq(piix3->pic[pic_irq],
+qemu_set_irq(piix3->pic.in_irqs[pic_irq],
!!(piix3->pic_levels &
(((1ULL << PIIX_NUM_PIRQS) - 1) <<
(pic_irq * PIIX_NUM_PIRQS;
@@ -308,6 +308,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
return;
}
+/* PIC */
+if (!qdev_realize(DEVICE(>pic), NULL, errp)) {
+return;
+}
+
+isa_bus_irqs(isa_bus, d->pic.in_irqs);
+
memory_region_init_io(>rcr_mem, OBJECT(dev), _ops, d,
"piix3-reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
@@ -371,6 +378,7 @@ static void pci_piix3_init(Object *obj)
{
PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1c291cc954..7b1b4625a3 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/acpi/piix4.h"
+#include "hw/core/proxy-pic.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/usb/hcd-uhci.h"
@@ -50,11 +51,10 @@ struct PIIXState {
#endif
uint64_t pic_levels;
-qemu_irq *pic;
-
/* This member isn't used. Just for save/load
[PATCH 15/32] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-21-shen...@gmail.com>
---
hw/isa/piix3.c| 8
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 0341284199..7ee706243a 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3,
int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq,
int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque,
int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
-if (irq < PIIX_NUM_PIC_IRQS) {
+if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -130,7 +130,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(>dev));
piix3_update_irq_levels(piix3);
-for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index c4e6e9f827..39c31da9ad 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -32,7 +32,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL/* PIRQ[A-D] */
struct PIIXState {
@@ -44,10 +43,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
--
2.38.1
[PATCH 21/32] hw/isa/piix4: Remove unused code
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-32-shen...@gmail.com>
---
hw/isa/piix4.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 24d943c609..dbefcb3ff4 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -180,12 +180,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq,
int level)
qemu_set_irq(s->cpu_intr, level);
}
-static void piix4_set_i8259_irq(void *opaque, int irq, int level)
-{
-PIIX4State *s = opaque;
-qemu_set_irq(s->isa[irq], level);
-}
-
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -229,8 +223,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
-qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
-"isa", ISA_NUM_IRQS);
qdev_init_gpio_out_named(DEVICE(dev), >cpu_intr,
"intr", 1);
--
2.38.1
[PATCH 25/32] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_"
Prefixing with "piix4_" makes the method distinguishable from its
PIIX3 counterpart upon merging and also complies more with QEMU
conventions.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-36-shen...@gmail.com>
---
hw/isa/piix4.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 13ec2503d0..e01d6ae00c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -63,7 +63,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int
level)
}
}
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
int slot;
@@ -249,7 +249,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
qdev_get_gpio_in(DEVICE(>pic), 9));
}
-pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
+pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s,
+ PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
--
2.38.1
[PATCH 22/32] hw/isa/piix4: Use Proxy PIC device
Aligns the code with PIIX3 such that PIIXState can be used in PIIX4,
too.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-33-shen...@gmail.com>
---
hw/isa/Kconfig | 2 +-
hw/isa/piix4.c | 30 +++---
hw/mips/Kconfig | 1 +
hw/mips/malta.c | 11 +--
4 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 8bf6462798..4dfa3310d9 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -48,10 +48,10 @@ config PIIX4
select ACPI_PIIX4
select I8254
select I8257
-select I8259
select IDE_PIIX
select ISA_BUS
select MC146818RTC
+select PROXY_PIC
select USB_UHCI
config VT82C686
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index dbefcb3ff4..0c34e3717c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,7 +30,7 @@
#include "hw/pci/pci.h"
#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
-#include "hw/intc/i8259.h"
+#include "hw/core/proxy-pic.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/rtc/mc146818rtc.h"
@@ -44,9 +44,8 @@
struct PIIX4State {
PCIDevice dev;
-qemu_irq cpu_intr;
-qemu_irq *isa;
+ProxyPICState pic;
RTCState rtc;
PCIIDEState ide;
UHCIState uhci;
@@ -82,7 +81,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int
level)
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
-qemu_set_irq(s->isa[pic_irq], pic_level);
+qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level);
}
}
@@ -174,12 +173,6 @@ static const VMStateDescription vmstate_piix4 = {
}
};
-static void piix4_request_i8259_irq(void *opaque, int irq, int level)
-{
-PIIX4State *s = opaque;
-qemu_set_irq(s->cpu_intr, level);
-}
-
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -215,7 +208,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
-qemu_irq *i8259_out_irq;
isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -223,20 +215,18 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
-qdev_init_gpio_out_named(DEVICE(dev), >cpu_intr,
- "intr", 1);
-
memory_region_init_io(>rcr_mem, OBJECT(dev), _rcr_ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, >rcr_mem, 1);
/* initialize i8259 pic */
-i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
-s->isa = i8259_init(isa_bus, *i8259_out_irq);
+if (!qdev_realize(DEVICE(>pic), NULL, errp)) {
+return;
+}
/* initialize ISA irqs */
-isa_bus_irqs(isa_bus, s->isa);
+isa_bus_irqs(isa_bus, s->pic.in_irqs);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
@@ -249,7 +239,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
return;
}
-s->rtc.irq = isa_get_irq(ISA_DEVICE(>rtc), s->rtc.isairq);
+s->rtc.irq = qdev_get_gpio_in(DEVICE(>pic), s->rtc.isairq);
/* IDE */
qdev_prop_set_int32(DEVICE(>ide), "addr", dev->devfn + 1);
@@ -276,7 +266,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
return;
}
-qdev_connect_gpio_out(DEVICE(>pm), 0, s->isa[9]);
+qdev_connect_gpio_out(DEVICE(>pm), 0,
+ qdev_get_gpio_in(DEVICE(>pic), 9));
}
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
@@ -286,6 +277,7 @@ static void piix4_init(Object *obj)
{
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+object_initialize_child(obj, "pic", >pic, TYPE_PROXY_PIC);
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", >ide, TYPE_PIIX4_IDE);
}
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index 4e7042f03d..d156de812c 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -1,5 +1,6 @@
config MALTA
bool
+select I8259
select ISA_SUPERIO
select PIIX4
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 4d0251ee12..36bdc184f6 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -29,6 +29,7 @@
#include "qemu/guest-random.h"
#include "hw/clock.h"
#include "hw/southbridge/piix.h"
+#include "hw/intc/i8259.h"
#include "hw/isa/superio.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -1254,10 +1255,11 @@ void mips_malta_init(MachineState *machine)
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq cbus_irq, i8259_irq;
+qemu_irq *i8259;
I2CBus *smbus;
[PATCH 20/32] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional
This aligns PIIX4 with PIIX3.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-30-shen...@gmail.com>
---
hw/isa/piix4.c | 44
hw/mips/malta.c | 6 --
2 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index aceb21ee3e..24d943c609 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -51,9 +51,16 @@ struct PIIX4State {
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
+
+uint32_t smb_io_base;
+
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
+
+bool has_acpi;
+bool has_usb;
+bool smm_enabled;
};
OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
@@ -259,17 +266,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
}
/* USB */
-qdev_prop_set_int32(DEVICE(>uhci), "addr", dev->devfn + 2);
-if (!qdev_realize(DEVICE(>uhci), BUS(pci_bus), errp)) {
-return;
+if (s->has_usb) {
+object_initialize_child(OBJECT(dev), "uhci", >uhci,
+TYPE_PIIX4_USB_UHCI);
+qdev_prop_set_int32(DEVICE(>uhci), "addr", dev->devfn + 2);
+if (!qdev_realize(DEVICE(>uhci), BUS(pci_bus), errp)) {
+return;
+}
}
/* ACPI controller */
-qdev_prop_set_int32(DEVICE(>pm), "addr", dev->devfn + 3);
-if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
-return;
+if (s->has_acpi) {
+object_initialize_child(OBJECT(s), "pm", >pm, TYPE_PIIX4_PM);
+qdev_prop_set_int32(DEVICE(>pm), "addr", dev->devfn + 3);
+qdev_prop_set_uint32(DEVICE(>pm), "smb_io_base", s->smb_io_base);
+qdev_prop_set_bit(DEVICE(>pm), "smm-enabled", s->smm_enabled);
+if (!qdev_realize(DEVICE(>pm), BUS(pci_bus), errp)) {
+return;
+}
+qdev_connect_gpio_out(DEVICE(>pm), 0, s->isa[9]);
}
-qdev_connect_gpio_out(DEVICE(>pm), 0, s->isa[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
}
@@ -280,13 +296,16 @@ static void piix4_init(Object *obj)
object_initialize_child(obj, "rtc", >rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", >ide, TYPE_PIIX4_IDE);
-object_initialize_child(obj, "uhci", >uhci, TYPE_PIIX4_USB_UHCI);
-
-object_initialize_child(obj, "pm", >pm, TYPE_PIIX4_PM);
-qdev_prop_set_uint32(DEVICE(>pm), "smb_io_base", 0x1100);
-qdev_prop_set_bit(DEVICE(>pm), "smm-enabled", 0);
}
+static Property piix4_props[] = {
+DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0),
+DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true),
+DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true),
+DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void piix4_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -305,6 +324,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
*/
dc->user_creatable = false;
dc->hotpluggable = false;
+device_class_set_props(dc, piix4_props);
}
static const TypeInfo piix4_info = {
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index c3dcd43f37..4d0251ee12 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1422,8 +1422,10 @@ void mips_malta_init(MachineState *machine)
empty_slot_init("GT64120", 0, 0x2000);
/* Southbridge */
-piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true,
-TYPE_PIIX4_PCI_DEVICE);
+piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, true,
+ TYPE_PIIX4_PCI_DEVICE);
+qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
+pci_realize_and_unref(piix4, pci_bus, _fatal);
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
--
2.38.1
Re: [PATCH] configure: Add --enable-lto
On Sun, 4 Dec 2022 at 00:04, Richard Henderson wrote: > > Separately control b_lto without --enable-cfi. > Also add --disable-lto for completeness. Before this patch, CFI defaults to false and therefore LTO also defaults to false. After this patch, LTO defaults to true even if CFI is false. Intentional change ? Do we have figures for whether LTO produces an interesting performance improvement ? We should probably complain if the user tries '--enable-cfi --disable-lto' rather than silently doing something that presumably doesn't work. thanks -- PMM
Re: [PATCH for-8.0] hw/misc: Move some arm-related files from specific_ss into softmmu_ss
On Fri, 2 Dec 2022 at 12:25, Thomas Huth wrote:
>
> On 01/12/2022 12.55, Peter Maydell wrote:
> > On Wed, 30 Nov 2022 at 11:16, Thomas Huth wrote:
> >> #define QEMU_ARM_POWERCTL_RET_SUCCESS QEMU_PSCI_RET_SUCCESS
> >> #define QEMU_ARM_POWERCTL_INVALID_PARAM QEMU_PSCI_RET_INVALID_PARAMS
> >> #define QEMU_ARM_POWERCTL_ALREADY_ON QEMU_PSCI_RET_ALREADY_ON
> >
> > kvm-consts.h is where QEMU_PSCI_RET_SUCCESS etc are defined.
> > So while the #include isn't strictly needed for compilation to work
> > because arm-powerctl.h only creates the #define and doesn't use it,
> > it does mean that any source file that uses the QEMU_ARM_POWERCTL_*
> > now needs to include kvm-consts.h somehow itself. (Usually this is
> > going to happen implicitly via target/arm/cpu.h, I think.)
> >
> > I guess this is worth living with for the benefit of not
> > compiling things twice. It could probably be untangled a little
> > by e.g. moving the PSCI constants into their own header rather
> > than defining them in kvm-consts.h, but I'm not sure if it's
> > worth the effort right now.
>
> Hmm, do we really need these QEMU_ARM_POWERCTL* redefinitions?
> They seem hardly to be used outside of the arm-powerctl.[ch]
> files:
>
> $ grep -r QEMU_ARM_POWERCTL * | grep -v target/arm/arm-powerctl
> hw/misc/allwinner-cpucfg.c:if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
> target/arm/hvf/hvf.c:assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
> target/arm/psci.c:assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
>
> ... so maybe we could rather change those spots to use the QEMU_PSCI_*
> constants instead? ... or since they basically only check for success,
> we could maybe use "if (ret) ..." and "assert(!ret)" there?
I see you've found a neat way to avoid this problem, but for the
record, the reason the two sets of constant names are different
is because these are two separate levels of API. The PSCI values
are required to be those values by the PSCI specification. The
ARM_POWERCTL values are just part of a within-QEMU API that is
used both by our PSCI implementation and also by some non-PSCI
power-control devices, so conceptually it shouldn't use PSCI
constants at all. However we assume in our PSCI implementation
that we can just pass through an Arm powerctl return code as a
PSCI return code to the guest, and so we want at compile time to
know that in fact we picked the same numbers for each. In theory
you could separate them the two sets of constant definitions and
then compile-time-assert in the PSCI implementation code that they
have the same values, or you could really separate them out and
then have the PSCI implementation code (that's the two cases in
target/arm) do a runtime conversion between an ARM_POWERCTL return
value and the appropriate PSCI return value.
The current setup exists partly because we started with only
a PSCI implementation, and then abstracted out the "start/stop
a CPU" functionality into its own within-QEMU API so other
power-control devices could use it.
-- PMM
Re: [PULL for-7.2 0/5] hw/nvme fixes
On Thu, 1 Dec 2022 at 11:50, Klaus Jensen wrote: > > From: Klaus Jensen > > Hi, > > The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece: > > Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500) > > are available in the Git repository at: > > git://git.infradead.org/qemu-nvme.git tags/nvme-next-pull-request Hi Klaus, Please send pull requests with an https:// URI in the future. Stefan > > for you to fetch changes up to 83f56ac321ca2301f00e63b6acbde5c692916a1d: > > hw/nvme: remove copy bh scheduling (2022-12-01 08:45:03 +0100) > > > hw/nvme fixes > > * fixes for aio cancellation in commands that may issue several > aios > > > > Klaus Jensen (5): > hw/nvme: fix aio cancel in format > hw/nvme: fix aio cancel in flush > hw/nvme: fix aio cancel in zone reset > hw/nvme: fix aio cancel in dsm > hw/nvme: remove copy bh scheduling > > hw/nvme/ctrl.c | 182 ++--- > 1 file changed, 51 insertions(+), 131 deletions(-) > > -- > 2.38.1 > >
