Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
ping
On Tue, Jan 31, 2023 at 2:30 PM wlfightup wrote:
>
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS support in the downstream port to allow
> passthrough of individual functions of a device to different
> guests (in a nested virt.setting) with VFIO.
> Without this patch, all functions of a device, such as all VFs of
> an SR/IOV device, will end up in the same IOMMU group.
> A similar situation occurs on Windows with Hyper-V.
>
> Signed-off-by: wlfightup
> ---
> hw/pci-bridge/xio3130_downstream.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/pci-bridge/xio3130_downstream.c
> b/hw/pci-bridge/xio3130_downstream.c
> index 38a2361fa2..2017cf42a3 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -40,6 +40,8 @@
> #define XIO3130_SSVID_SSID 0
> #define XIO3130_EXP_OFFSET 0x90
> #define XIO3130_AER_OFFSET 0x100
> +#define XIO3130_ACS_OFFSET \
> +(XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
>
> static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
> uint32_t val, int len)
> @@ -111,6 +113,10 @@ static void xio3130_downstream_realize(PCIDevice *d,
> Error **errp)
> goto err;
> }
>
> +if (!s->disable_acs) {
> +pcie_acs_init(d, XIO3130_ACS_OFFSET);
> +}
> +
> return;
>
> err:
> @@ -137,6 +143,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
> static Property xio3130_downstream_props[] = {
> DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
> QEMU_PCIE_SLTCAP_PCP_BITNR, true),
> +DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
> DEFINE_PROP_END_OF_LIST()
> };
>
> --
> 2.24.3 (Apple Git-128)
>
Re: [PATCH v6 16/29] target/arm: Move cortex sysregs into cpu64.c
On 2/17/23 10:11, Fabiano Rosas wrote:
diff --git a/target/arm/meson.build b/target/arm/meson.build
index a5191b57e1..b0bc8a3cea 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
arm_ss = ss.source_set()
arm_ss.add(files(
'cpu.c',
+ 'cpu64.c',
'debug_helper.c',
'gdbstub.c',
'helper.c',
@@ -12,7 +13,6 @@ arm_ss.add(zlib)
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false:
files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
- 'cpu64.c',
'gdbstub64.c',
))
Not keen on this. I think better something like cortex-regs.c.
r~
Re: [PATCH v6 07/29] target/arm: Wrap TCG-only code in debug_helper.c
On 2/17/23 10:11, Fabiano Rosas wrote: The next few patches will move helpers under CONFIG_TCG. We'd prefer to keep the debug helpers and debug registers close together, so rearrange the file a bit to be able to wrap the helpers with a TCG ifdef. Signed-off-by: Fabiano Rosas --- target/arm/debug_helper.c | 476 +++--- 1 file changed, 239 insertions(+), 237 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v6 06/29] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
On 2/17/23 10:11, Fabiano Rosas wrote: This is in preparation for restricting compilation of some parts of debug_helper.c to TCG only. Signed-off-by: Fabiano Rosas --- Dropped r-bs because I added a few more ifs in debug_helper.c --- target/arm/cpu.c | 6 -- target/arm/debug_helper.c | 16 target/arm/machine.c | 7 +-- 3 files changed, 21 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v6 3/4] target/riscv: implement Zicbom extension
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+/*
+ * Section 2.5.2 of cmobase v1.0.1:
+ *
+ * "A cache-block management instruction is permitted to
+ * access the specified cache block whenever a load instruction
+ * or store instruction is permitted to access the corresponding
+ * physical addresses. If neither a load instruction nor store
+ * instruction is permitted to access the physical addresses,
+ * but an instruction fetch is permitted to access the physical
+ * addresses, whether a cache-block management instruction is
+ * permitted to access the cache block is UNSPECIFIED.
+ *
+ * This means we have to make a choice of whether checking
+ * MMU_INST_FETCH is worth it or not. We'll go the easier
+ * route and check MMU_DATA_LOAD and MMU_DATA_STORE only.
+ */
+ret = probe_access_range_flags(env, address, cbomlen,
+ MMU_DATA_LOAD,
+ mmu_idx, true, &phost, ra);
+
+if (ret == TLB_INVALID_MASK) {
+probe_access_range_flags(env, address, cbomlen,
+ MMU_DATA_STORE,
+ mmu_idx, true, &phost, ra);
+}
Not correct, at minimum for discarding the result of the second call. But I suggested a
different ordering of operations which avoid a third probe.
r~
Re: [PATCH v6 2/4] target/riscv: implement Zicboz extension
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+void helper_cbo_zero(CPURISCVState *env, target_ulong address)
+{
+RISCVCPU *cpu = env_archcpu(env);
+uintptr_t ra = GETPC();
+uint16_t cbozlen;
+void *mem;
+
+check_zicbo_envcfg(env, MENVCFG_CBZE, ra);
+
+/* Get the size of the cache block for zero instructions. */
+cbozlen = cpu->cfg.cboz_blocksize;
+
+/* Mask off low-bits to align-down to the cache-block. */
+address &= ~(cbozlen - 1);
+
+mem = tlb_vaddr_to_host(env, address, MMU_DATA_STORE,
+cpu_mmu_index(env, false));
+
+if (likely(mem)) {
+/* Zero the block */
+memset(mem, 0, cbozlen);
+}
+}
Not correct. This fails to zero the block at all under a number of conditions.
Please have a closer look at the feedback on v5.
r~
Re: Runnig solaris binary(32 bit) on linux(64 bit)
Thanks to everyone. Ok , so I need to run QEMU in Full System Emulation mode to run the Solaris binary. Is the *qemu-kvm* , the only package required to be installed ( on RHEL machine) to launch QEMU or there are some packages also. Also I would need the Solars OS image, right? Regards, Ginu On Fri, 17 Feb 2023 at 21:34, Warner Losh wrote: > > > On Thu, Feb 16, 2023 at 12:40 PM David Woodhouse > wrote: > >> On Thu, 2023-02-16 at 09:29 -1000, Richard Henderson wrote: >> > On 2/16/23 09:02, David Woodhouse wrote: >> > > It wouldn't be beyond the wit of man to extend qemu-user to support >> the >> > > similar personality variations for SCO/Solaris/etc. using that as a >> > > guide. >> > >> > Not beyond wit but perhaps beyond patience. >> > >> > It would certainly be possible to emulate the "easy middle" of one >> POSIX guest on a >> > different POSIX host. But the dusty corners are going to get in the >> way, where we >> > currently rely on guest and host having identical semantics, and pass >> the system call >> > through to the host. >> > >> > It's a big job. >> >> True, but the existing iBCS / linux-abi kernel patches should highlight >> a lot of those dusty corners. >> > > So one thing to understand, the iBCS is a separate ABI. This means that > you'd > have to rewrite everything from the syscall dispatch on down. Even if this > were > relevant, it would be a huge job. > > A lot would depend on how much of Solaris is used. Solaris is ELF, which > is good > (it would be even worse if it were SunOS 4, then it's a.out and a whole > lot of other > complication that's more of a bsd-user thing). However, as others have > pointed > out, linux-user assumes a linux kernel. While one can run linux-user on > FreeBSD > with its Linux ABI implementation, even that's quite limited in what it > can do (I > needed to do this for some kexec support I was adding to FreeBSD boot > loader > that ran as a Linux binary). I had to make tweaks to FreeBSD's emulation > to make it work, and that was for a binary that used only 10 system calls, > no > threads, no signals, nothing "messy" and apart from some extensions to > 64-bits, > nothing that wasn't in 7th Edition Unix. > > And there's also a number of special filesystems, IIRC, on Solaris that > are used > like linux's /sys and /proc filesystems, but with different details. And a > million other > details. Knowing the details isn't enough, assuming you could know them > from > cribbing from existing code. You have to actually go implement the details > and > that would be a very tedious job. Even if you kept it to a subset that > your program > uses... > > I started on a Venix emulator (ancient Unix V7 port to 8088/8086 micros I > cut my > teeth on), and even that was daunting. Now, with 3 years of bsd-user > hacking and > upstreaming under my belt, it would be easier, but there's a *HUGE* > learning curve > to understand the CPU, its exception model, how system calls are handled, > how > memory is mapped, etc. And the 'assume we're on linux' is definitely > leveraged > for memory mapping in the existing linux-user code if you were to copy it > all > as a starting point. > > When people say it's a big job, they are underselling it somewhat. It > would be > a big job for the maintainers of linux-user who have all the context and > know > where the gotchas are. For anybody else, learning everything you need to > know itself is a big job. > > Your best bet is qemu-sparc-system + Solaris install. > > Warner > > P.S. Sorry to go into partial rant mode, but 4 years ago when I started > helping > the folks working with bsd-user, I thought how hard could it be... now I > know... >
Re: [PATCH v1 2/2] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG
在 2023/2/18 0:54, Strahinja Jankovic 写道: Hi, I tried running Avocado tests for cubieboard with following command: ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run-t machine:cubieboard tests/avocado/boot_linux_console.py Without this patch all tests pass: RESULTS: PASS 3 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 53.15 s However, if I apply this patch, all tests fail. This is part of the log that captures the failure: axp20x-i2c 1-0034: AXP20x variant AXP209 found console: random: crng init done console: irq 43: nobody cared (try booting with the "irqpoll" option) console: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.10.16-sunxi #21.02.2 console: Hardware name: Allwinner sun4i/sun5i Families console: [] (unwind_backtrace) from [] (show_stack+0x11/0x14) console: [] (show_stack) from [] (dump_stack+0x77/0x84) console: [] (dump_stack) from [] (__report_bad_irq+0x37/0x94) console: [] (__report_bad_irq) from [] (note_interrupt+0xfb/0x1f4) console: [] (note_interrupt) from [] (handle_irq_event_percpu+0x4f/0x54) console: [] (handle_irq_event_percpu) from [] (handle_irq_event+0x39/0x50) console: [] (handle_irq_event) from [] (handle_fasteoi_irq+0x67/0xbc) console: [] (handle_fasteoi_irq) from [] (generic_handle_irq+0x29/0x34) console: [] (generic_handle_irq) from [] (__handle_domain_irq+0x43/0x84) console: [] (__handle_domain_irq) from [] (sun4i_handle_irq+0x3b/0x4c) console: [] (sun4i_handle_irq) from [] (__irq_svc+0x65/0x94) console: Exception stack(0xc1517950 to 0xc1517998) console: 7940: c1701ca0 6153 00e4 0001 console: 7960: c1701c40 0002 6153 c1517a1c c1701ca0 c0f03d00 fffede04 console: 7980: c15179a0 c075ebb7 c09785d4 0173 console: [] (__irq_svc) from [] (_raw_spin_unlock_irqrestore+0x1c/0x20) console: [] (_raw_spin_unlock_irqrestore) from [] (mv64xxx_i2c_xfer+0x5b/0x13c) console: [] (mv64xxx_i2c_xfer) from [] (__i2c_transfer+0x145/0x4c0) console: [] (__i2c_transfer) from [] (i2c_transfer+0x5b/0xbc) console: [] (i2c_transfer) from [] (regmap_i2c_read+0x49/0x68) console: [] (regmap_i2c_read) from [] (_regmap_raw_read+0x99/0x1d8) console: [] (_regmap_raw_read) from [] (_regmap_bus_read+0x29/0x40) console: [] (_regmap_bus_read) from [] (_regmap_read+0x3d/0xe8) console: [] (_regmap_read) from [] (_regmap_update_bits+0x75/0xb0) console: [] (_regmap_update_bits) from [] (regmap_update_bits_base+0x39/0x50) console: [] (regmap_update_bits_base) from [] (regmap_irq_update_bits+0x2f/0x34) console: [] (regmap_irq_update_bits) from [] (regmap_add_irq_chip_fwnode+0x56f/0x72c) console: [] (regmap_add_irq_chip_fwnode) from [] (regmap_add_irq_chip+0x2f/0x34) console: [] (regmap_add_irq_chip) from [] (axp20x_device_probe+0x3f/0x368) console: [] (axp20x_device_probe) from [] (i2c_device_probe+0x1d3/0x1e4) console: [] (i2c_device_probe) from [] (really_probe+0xb7/0x378) console: [] (really_probe) from [] (driver_probe_device+0xa9/0x16c) console: [] (driver_probe_device) from [] (bus_for_each_drv+0x4d/0x78) console: [] (bus_for_each_drv) from [] (__device_attach+0x8f/0xf0) console: [] (__device_attach) from [] (bus_probe_device+0x5b/0x60) console: [] (bus_probe_device) from [] (device_add+0x2e7/0x564) console: [] (device_add) from [] (i2c_new_client_device+0xdf/0x1bc) console: [] (i2c_new_client_device) from [] (of_i2c_register_device+0x71/0x90) console: [] (of_i2c_register_device) from [] (of_i2c_register_devices+0x59/0xc4) console: [] (of_i2c_register_devices) from [] (i2c_register_adapter+0x195/0x53c) console: [] (i2c_register_adapter) from [] (mv64xxx_i2c_probe+0x199/0x440) console: [] (mv64xxx_i2c_probe) from [] (platform_drv_probe+0x33/0x68) console: [] (platform_drv_probe) from [] (really_probe+0xb7/0x378) console: [] (really_probe) from [] (driver_probe_device+0xa9/0x16c) console: [] (driver_probe_device) from [] (device_driver_attach+0x3d/0x40) console: [] (device_driver_attach) from [] (__driver_attach+0x5d/0xe0) console: [] (__driver_attach) from [] (bus_for_each_dev+0x41/0x68) console: [] (bus_for_each_dev) from [] (bus_add_driver+0xe7/0x154) console: [] (bus_add_driver) from [] (driver_register+0x39/0xa0) console: [] (driver_register) from [] (do_one_initcall+0x39/0x1b0) console: [] (do_one_initcall) from [] (kernel_init_freeable+0x1c1/0x20c) console: [] (kernel_init_freeable) from [] (kernel_init+0xd/0xe0) console: [] (kernel_init) from [] (ret_from_fork+0x11/0x38) console: Exception stack(0xc1517fb0 to 0xc1517ff8) console: 7fa0: console: 7fc0: console: 7fe0: 0013 console: handlers: console: [<(ptrval)>] mv64xxx_i2c_intr console: Disabling IRQ #43 RESULTS: PASS 0 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 3 | CANCEL 0 JOB TIME : 94.23
Re: [PATCH v2] Fix exec migration on Windows (w32+w64).
ping. Is there anything I can do to help this get merged? Best regards, John Berberian, Jr.
Re: [PATCH 1/2] qemu/typedefs: Sort in case-insensitive alphabetical order (again)
Am 17. Februar 2023 14:18:31 UTC schrieb "Philippe Mathieu-Daudé"
:
>Following the recommendation added in commit a98c370c46
>("typedefs: (Re-)sort entries alphabetically"), and similarly
>to commit 64baadc272 ("Sort include/qemu/typedefs.h"), sort
>again the type definitions (in case-insensitive alphabetical
>order, using 'sort --ignore-case').
Since it can be done mechanically: Maybe add a checkpach check?
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
> include/qemu/typedefs.h | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
>diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
>index c7c8a85315..df4b55ac65 100644
>--- a/include/qemu/typedefs.h
>+++ b/include/qemu/typedefs.h
>@@ -49,6 +49,7 @@ typedef struct DeviceState DeviceState;
> typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot;
> typedef struct DisplayChangeListener DisplayChangeListener;
> typedef struct DriveInfo DriveInfo;
>+typedef struct DumpState DumpState;
> typedef struct Error Error;
> typedef struct EventNotifier EventNotifier;
> typedef struct FlatView FlatView;
>@@ -56,6 +57,7 @@ typedef struct FWCfgEntry FWCfgEntry;
> typedef struct FWCfgIoState FWCfgIoState;
> typedef struct FWCfgMemState FWCfgMemState;
> typedef struct FWCfgState FWCfgState;
>+typedef struct GraphicHwOps GraphicHwOps;
> typedef struct HostMemoryBackend HostMemoryBackend;
> typedef struct I2CBus I2CBus;
> typedef struct I2SCodec I2SCodec;
>@@ -90,10 +92,10 @@ typedef struct PCIDevice PCIDevice;
> typedef struct PCIEAERErr PCIEAERErr;
> typedef struct PCIEAERLog PCIEAERLog;
> typedef struct PCIEAERMsg PCIEAERMsg;
>-typedef struct PCIESriovPF PCIESriovPF;
>-typedef struct PCIESriovVF PCIESriovVF;
> typedef struct PCIEPort PCIEPort;
> typedef struct PCIESlot PCIESlot;
>+typedef struct PCIESriovPF PCIESriovPF;
>+typedef struct PCIESriovVF PCIESriovVF;
> typedef struct PCIExpressDevice PCIExpressDevice;
> typedef struct PCIExpressHost PCIExpressHost;
> typedef struct PCIHostDeviceAddress PCIHostDeviceAddress;
>@@ -106,6 +108,7 @@ typedef struct QBool QBool;
> typedef struct QDict QDict;
> typedef struct QEMUBH QEMUBH;
> typedef struct QemuConsole QemuConsole;
>+typedef struct QEMUCursor QEMUCursor;
> typedef struct QEMUFile QEMUFile;
> typedef struct QemuLockable QemuLockable;
> typedef struct QemuMutex QemuMutex;
>@@ -132,9 +135,6 @@ typedef struct VirtIODevice VirtIODevice;
> typedef struct Visitor Visitor;
> typedef struct VMChangeStateEntry VMChangeStateEntry;
> typedef struct VMStateDescription VMStateDescription;
>-typedef struct DumpState DumpState;
>-typedef struct GraphicHwOps GraphicHwOps;
>-typedef struct QEMUCursor QEMUCursor;
>
> /*
> * Pointer types
[RFC PATCH 2/2] selftests: restrictedmem: Add selftest for RMFD_HUGEPAGE
Tests that when RMFD_HUGEPAGE is specified, restrictedmem will be
backed by Transparent HugePages.
Signed-off-by: Ackerley Tng
---
.../restrictedmem_hugepage_test.c | 25 +++
1 file changed, 25 insertions(+)
diff --git
a/tools/testing/selftests/restrictedmem/restrictedmem_hugepage_test.c
b/tools/testing/selftests/restrictedmem/restrictedmem_hugepage_test.c
index 0d9cf2ced754..75283d68696f 100644
--- a/tools/testing/selftests/restrictedmem/restrictedmem_hugepage_test.c
+++ b/tools/testing/selftests/restrictedmem/restrictedmem_hugepage_test.c
@@ -180,6 +180,31 @@ TEST_F(reset_shmem_enabled,
restrictedmem_fstat_shmem_enabled_always)
close(mfd);
}
+TEST(restrictedmem_invalid_flags)
+{
+ int mfd = memfd_restricted(99, NULL);
+
+ ASSERT_EQ(-1, mfd);
+ ASSERT_EQ(EINVAL, errno);
+}
+
+TEST_F(reset_shmem_enabled, restrictedmem_rmfd_hugepage)
+{
+ int mfd = -1;
+ struct stat stat;
+
+ ASSERT_EQ(0, set_shmem_thp_policy("never"));
+
+ mfd = memfd_restricted(RMFD_HUGEPAGE, NULL);
+ ASSERT_NE(-1, mfd);
+
+ ASSERT_EQ(0, fstat(mfd, &stat));
+
+ ASSERT_EQ(stat.st_blksize, get_hpage_pmd_size());
+
+ close(mfd);
+}
+
TEST(restrictedmem_tmpfile_no_mount_path)
{
int mfd = memfd_restricted(RMFD_TMPFILE, NULL);
--
2.39.2.637.g21b0678d19-goog
[RFC PATCH 1/2] mm: restrictedmem: Add flag as THP allocation hint for memfd_restricted() syscall
Allow userspace to hint the kernel to use Transparent HugePages to
back restricted memory on a per-file basis.
Signed-off-by: Ackerley Tng
---
include/uapi/linux/restrictedmem.h | 1 +
mm/restrictedmem.c | 27 +--
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/include/uapi/linux/restrictedmem.h
b/include/uapi/linux/restrictedmem.h
index 9f108dd1ac4c..f671ccbb43bc 100644
--- a/include/uapi/linux/restrictedmem.h
+++ b/include/uapi/linux/restrictedmem.h
@@ -4,5 +4,6 @@
/* flags for memfd_restricted */
#define RMFD_TMPFILE 0x0001U
+#define RMFD_HUGEPAGE 0x0002U
#endif /* _UAPI_LINUX_RESTRICTEDMEM_H */
diff --git a/mm/restrictedmem.c b/mm/restrictedmem.c
index 97f3e2159e8b..87c829960b31 100644
--- a/mm/restrictedmem.c
+++ b/mm/restrictedmem.c
@@ -190,19 +190,25 @@ static struct file *restrictedmem_file_create(struct file
*memfd)
return file;
}
-static int restrictedmem_create(struct vfsmount *mount)
+static int restrictedmem_create(unsigned int flags, struct vfsmount *mount)
{
struct file *file, *restricted_file;
int fd, err;
+ unsigned long shmem_setup_flags = VM_NORESERVE;
fd = get_unused_fd_flags(0);
if (fd < 0)
return fd;
- if (mount)
- file = shmem_file_setup_with_mnt(mount, "memfd:restrictedmem",
0, VM_NORESERVE);
- else
- file = shmem_file_setup("memfd:restrictedmem", 0, VM_NORESERVE);
+ if (flags & RMFD_HUGEPAGE)
+ shmem_setup_flags |= VM_HUGEPAGE;
+
+ if (mount) {
+ file = shmem_file_setup_with_mnt(mount, "memfd:restrictedmem",
+0, shmem_setup_flags);
+ } else {
+ file = shmem_file_setup("memfd:restrictedmem", 0,
shmem_setup_flags);
+ }
if (IS_ERR(file)) {
err = PTR_ERR(file);
@@ -230,7 +236,8 @@ static bool is_shmem_mount(struct vfsmount *mnt)
return mnt->mnt_sb->s_magic == TMPFS_MAGIC;
}
-static int restrictedmem_create_from_path(const char __user *mount_path)
+static int restrictedmem_create_from_path(unsigned int flags,
+ const char __user *mount_path)
{
int ret;
struct path path;
@@ -250,7 +257,7 @@ static int restrictedmem_create_from_path(const char __user
*mount_path)
if (unlikely(ret))
goto out;
- ret = restrictedmem_create(path.mnt);
+ ret = restrictedmem_create(flags, path.mnt);
mnt_drop_write(path.mnt);
out:
@@ -261,16 +268,16 @@ static int restrictedmem_create_from_path(const char
__user *mount_path)
SYSCALL_DEFINE2(memfd_restricted, unsigned int, flags, const char __user *,
mount_path)
{
- if (flags & ~RMFD_TMPFILE)
+ if (flags & ~(RMFD_TMPFILE | RMFD_HUGEPAGE))
return -EINVAL;
if (flags == RMFD_TMPFILE) {
if (!mount_path)
return -EINVAL;
- return restrictedmem_create_from_path(mount_path);
+ return restrictedmem_create_from_path(flags, mount_path);
} else {
- return restrictedmem_create(NULL);
+ return restrictedmem_create(flags, NULL);
}
}
--
2.39.2.637.g21b0678d19-goog
[RFC PATCH 0/2] Add flag as THP allocation hint for memfd_restricted() syscall
Hello, This patchset builds upon the memfd_restricted() system call that has been discussed in the ‘KVM: mm: fd-based approach for supporting KVM’ patch series, at https://lore.kernel.org/lkml/20221202061347.1070246-1-chao.p.p...@linux.intel.com/T/#m7e944d7892afdd1d62a03a287bd488c56e377b0c The tree can be found at: https://github.com/googleprodkernel/linux-cc/tree/restrictedmem-rmfd-hugepage Following the RFC to provide mount for memfd_restricted() syscall at https://lore.kernel.org/lkml/cover.1676507663.git.ackerley...@google.com/T/#u, this patchset adds the RMFD_HUGEPAGE flag to the memfd_restricted() syscall, which will hint the kernel to use Transparent HugePages to back restrictedmem pages. This supplements the interface proposed earlier, which requires the creation of a tmpfs mount to be passed to memfd_restricted(), with a more direct per-file hint. Dependencies: + Sean’s iteration of the ‘KVM: mm: fd-based approach for supporting KVM’ patch series at https://github.com/sean-jc/linux/tree/x86/upm_base_support + Proposed fix for restrictedmem_getattr() as mentioned on the mailing list at https://lore.kernel.org/lkml/diqzzga0fv96@ackerleytng-cloudtop-sg.c.googlers.com/ + Hugh’s patch: https://lore.kernel.org/lkml/c140f56a-1aa3-f7ae-b7d1-93da7d5a3...@google.com/, which provides functionality in shmem that reads the VM_HUGEPAGE flag in key functions shmem_is_huge() and shmem_get_inode() Future work/TODOs: + man page for the memfd_restricted() syscall + Support for per file NUMA binding hints Ackerley Tng (2): mm: restrictedmem: Add flag as THP allocation hint for memfd_restricted() syscall selftests: restrictedmem: Add selftest for RMFD_HUGEPAGE include/uapi/linux/restrictedmem.h| 1 + mm/restrictedmem.c| 27 --- .../restrictedmem_hugepage_test.c | 25 + 3 files changed, 43 insertions(+), 10 deletions(-) -- 2.39.2.637.g21b0678d19-goog
Re: [PATCH v2 6/7] CI: Stop building docs on centos8
On Tue, Feb 14, 2023 at 12:26 PM Kevin Wolf wrote: > > Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben: > > In the case of Python the issue is not the interpreter per se, though > > there are a couple new feature in Python 3.7 that are quite nice (for > > example improved data classes[1] or context variables[2]). The main > > problem as far as I understood (and have seen in my experience) is > > linting tools. New versions fix bugs that caused false positives, but > > also become more strict at the same time. The newer versions at the > > same time are very quick at dropping support for old versions of > > Python; while older versions sometimes throw deprecation warnings on > > new versions of Python. This makes it very hard to support a single > > version of, say, mypy that works on all versions from RHEL8 and SLE15 > > to Fedora 38 and Ubuntu 23.04. > > Why do we have to support a single version of mypy? What is wrong with > running an old mypy version with old Python version, and a newer mypy > with newer Python versions? Well, the problem is, ... > > Sure, they will complain about different things, but it doesn't feel > that different from supporting multiple C compilers in various versions. ...well, it's this. The first dimension of the test matrix is the version of mypy itself. The second dimension of the test matrix is the version of Python mypy runs under. A given version of mypy can run under multiple versions of Python and may indeed have different behaviors under each. The third dimension of this test matrix is the version(s) of Python our code is targeting; for instance we configure mypy to understand that we require Python 3.6. Trying to cast the net wide on *all of these* gets tough; the very latest versions of mypy don't support 3.6 at all, so you'll have cases where the mypy that just so happens to come with your Fedora installation just won't work properly with our code anymore, which has to test under 3.6 appropriately. In general, the majority of python package upstreams I am aware of simply pin a python version and a mypy version and leave it at that. Compatibility concerns for most of the upstreams just do not really ever consider that you'd be running *and* testing against a large spread of versions. I've gone the extra mile and I run mypy and pylint under all versions of python from 3.6 to 3.11 to ensure that developer workstations can run the same linting tests and feel assured that if it passes locally, it will pass on the CI and vice-versa. Our matrix is generally quite a bit larger than most upstreams, so I am playing a lot of whack-a-mole to keep things functioning consistently across the versions. I will probably even add support for Python 3.12 alpha *soon* because it's already available in the Fedora repo, and it will be good to find any compatibility issues before that version is officially released. (I'll need to do this for the qemu.qmp package, which should have support for 3.12 on the day 3.12 releases and not sometime afterwards.) I know the "check-tox" test was annoying upstream as it sometimes turned yellow because a new pylint version was released, but that's how I stay ahead of breaking changes before they're on local workstations. We could avoid at least one of the reasons for dropping 3.6 support by saying "Tough cookies, you'll use precisely this version of mypy and precisely this python interpreter, or you'll get nothing" and that does relieve a huge amount of pressure as-is. But, as a courtesy, I do go out of my way -- where possible -- to ensure that developers can use whichever versions of tools their distro is providing them so that they don't have to mess around with that stuff. Unfortunately, that means when upstreams start dropping support for older things, it gets hairier and quite a bit more painful. I think 3.6 being the first version that offers full-throated type hint support has unique pain in this circumstance because a lot of the details did not get hammered out until 3.7 or later; in general the amount of workarounds I have had to apply because something type checks only in 3.7+ but not 3.6 is fairly high compared to the number of times I've found that a different version was the odd one out. I don't expect this to become a recurring desire where I start to whine about old Python versions before our support window would otherwise let me drop them; I think this is actually just a unique pain point of this one version if we keep static typing. That's the tooling issue, anyway. > > Kevin >
Re: [PATCH v4 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.
Note:
- Header content needs to be manually specified in a fashion that
matches the specification for what can be in the header for each
error type.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header":
[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Signed-off-by: Jonathan Cameron
---
v4:
- Improved QMP help text wth more detail (following request in review
of the Poison injection series)
---
hw/cxl/cxl-component-utils.c | 4 +-
hw/mem/cxl_type3.c | 281 +
hw/mem/cxl_type3_stubs.c | 10 ++
hw/mem/meson.build | 2 +
include/hw/cxl/cxl_component.h | 26 +++
include/hw/cxl/cxl_device.h| 11 ++
qapi/cxl.json | 118 ++
qapi/meson.build | 1 +
qapi/qapi-schema.json | 1 +
9 files changed, 453 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 737b4764b9..b665d4f565 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -142,16 +142,18 @@ static void ras_init_common(uint32_t *reg_state, uint32_t
*write_msk)
* be handled as RO.
*/
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
+stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
+stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
/* CXL switches and devices must set */
-stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00);
+stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
}
static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 6cdd988d1d..e32bbac966 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
+#include "qapi/qapi-commands-cxl.h"
#include "hw/mem/memory-device.h"
#include "hw/mem/pc-dimm.h"
#include "hw/pci/pci.h"
@@ -323,6 +324,66 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int
which)
ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
}
+static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
+{
+switch (qmp_err) {
+case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_DATA_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_ADDRESS_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_BE_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_BE_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_ECC:
+return CXL_RAS_UNC_ERR_CACHE_DATA_ECC;
+case CXL_UNCOR_ERROR_TYPE_MEM_DATA_PARITY:
+return CXL_RAS_UNC_ERR_MEM_DATA_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_ADDRESS_PARITY:
+return CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_BE_PARITY:
+return CXL_RAS_UNC_ERR_MEM_BE_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_DATA_ECC:
+return CXL_RAS_UNC_ERR_MEM_DATA_ECC;
+case CXL_UNCOR_ERROR_TYPE_REINIT_THRESHOLD:
+return CXL_RAS_UNC_ERR_REINIT_THRESHOLD;
+case CXL_UNCOR_ERROR_TYPE_RSVD_ENCODING:
+return CXL_RAS_UNC_ERR_RSVD_ENCODING;
+case CXL_UNCOR_ERROR_TYPE_POISON_RECEIVED:
+return CXL_RAS_UNC_ERR_POISON_RECEIVED;
+case CXL_UNCOR_ERROR_TYPE_RECEIVER_OVERFLOW:
+return CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW;
+case CXL_UNCOR_ERROR
Re: [PATCH v4 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks
On 2/17/23 10:29 AM, Jonathan Cameron wrote: As these are about to be modified, fix the endian handle for this set of registers rather than making it worse. Note that CXL is currently only supported in QEMU on x86 (arm64 patches out of tree) so we aren't going to yet hit an problems with big endian. However it is good to avoid making things worse for that support in the future. Signed-off-by: Jonathan Cameron Reviewed-by: Dave Jiang --- hw/cxl/cxl-component-utils.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 3edd303a33..737b4764b9 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) * Error status is RW1C but given bits are not yet set, it can * be handled as RO. */ -reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; +stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ -reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; -write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; -reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; -write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; -reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; -reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; -write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; +stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); +stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); +stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); +stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); +stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); +stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); +stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); /* CXL switches and devices must set */ -reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; +stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); } static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
[PATCH 3/2] hw/timer: Rename ptimer_state -> PTimer
Remove a pointless cast in ptimer_tick() and rename 'ptimer_state'
as 'PTimer' to follow the Structure naming convention.
See docs/devel/style.rst:
Variables are lower_case_with_underscores; easy to type and
read. Structured type names are in CamelCase; harder to type
but standing out. Enum type names and function type names
should also be in CamelCase. Scalar type names are
lower_case_with_underscores_ending_with_a_t, like the POSIX
uint64_t and family.
Mechanical change doing:
$ sed -i -e s/ptimer_state/PTimer/g \
$(git grep -l ptimer_state)
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/musicpal.c| 2 +-
hw/core/ptimer.c | 56
hw/dma/xilinx_axidma.c | 2 +-
hw/m68k/mcf5206.c| 2 +-
hw/m68k/mcf5208.c| 2 +-
hw/net/fsl_etsec/etsec.h | 2 +-
hw/net/lan9118.c | 2 +-
hw/rtc/exynos4210_rtc.c | 4 +-
hw/timer/altera_timer.c | 2 +-
hw/timer/arm_mptimer.c | 4 +-
hw/timer/arm_timer.c | 2 +-
hw/timer/etraxfs_timer.c | 8 ++--
hw/timer/exynos4210_mct.c| 8 ++--
hw/timer/exynos4210_pwm.c| 2 +-
hw/timer/grlib_gptimer.c | 2 +-
hw/timer/sh_timer.c | 2 +-
hw/timer/slavio_timer.c | 2 +-
hw/timer/xilinx_timer.c | 2 +-
include/hw/display/xlnx_dp.h | 2 +-
include/hw/dma/xlnx_csu_dma.h| 2 +-
include/hw/net/xlnx-zynqmp-can.h | 2 +-
include/hw/ptimer.h | 34 +++---
include/hw/timer/allwinner-a10-pit.h | 2 +-
include/hw/timer/arm_mptimer.h | 2 +-
include/hw/timer/armv7m_systick.h| 2 +-
include/hw/timer/cmsdk-apb-dualtimer.h | 2 +-
include/hw/timer/cmsdk-apb-timer.h | 2 +-
include/hw/timer/digic-timer.h | 2 +-
include/hw/timer/imx_epit.h | 4 +-
include/hw/timer/imx_gpt.h | 2 +-
include/hw/timer/mss-timer.h | 2 +-
include/hw/watchdog/cmsdk-apb-watchdog.h | 2 +-
include/hw/watchdog/wdt_imx2.h | 4 +-
include/qemu/typedefs.h | 2 +-
tests/unit/ptimer-test.c | 22 +-
35 files changed, 98 insertions(+), 98 deletions(-)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 89b66606c3..63e0bbda95 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -435,7 +435,7 @@ static const TypeInfo mv88w8618_pic_info = {
#define MP_BOARD_RESET_MAGIC0x1
typedef struct mv88w8618_timer_state {
-ptimer_state *ptimer;
+PTimer *ptimer;
uint32_t limit;
int freq;
qemu_irq irq;
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
index eb5ba1aff7..3ff49a0a04 100644
--- a/hw/core/ptimer.c
+++ b/hw/core/ptimer.c
@@ -19,7 +19,7 @@
#define DELTA_ADJUST 1
#define DELTA_NO_ADJUST -1
-struct ptimer_state
+struct PTimer
{
uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */
uint64_t limit;
@@ -43,12 +43,12 @@ struct ptimer_state
};
/* Use a bottom-half routine to avoid reentrancy issues. */
-static void ptimer_trigger(ptimer_state *s)
+static void ptimer_trigger(PTimer *s)
{
s->callback(s->callback_opaque);
}
-static void ptimer_reload(ptimer_state *s, int delta_adjust)
+static void ptimer_reload(PTimer *s, int delta_adjust)
{
uint32_t period_frac;
uint64_t period;
@@ -73,7 +73,7 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
/*
* Note that ptimer_trigger() might call the device callback function,
* which can then modify timer state, so we must not cache any fields
- * from ptimer_state until after we have called it.
+ * from PTimer state until after we have called it.
*/
delta = s->delta;
period = s->period;
@@ -154,7 +154,7 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
static void ptimer_tick(void *opaque)
{
-ptimer_state *s = (ptimer_state *)opaque;
+PTimer *s = opaque;
bool trigger = true;
/*
@@ -198,7 +198,7 @@ static void ptimer_tick(void *opaque)
ptimer_transaction_commit(s);
}
-uint64_t ptimer_get_count(ptimer_state *s)
+uint64_t ptimer_get_count(PTimer *s)
{
uint64_t counter;
@@ -294,7 +294,7 @@ uint64_t ptimer_get_count(ptimer_state *s)
return counter;
}
-void ptimer_set_count(ptimer_state *s, uint64_t count)
+void ptimer_set_count(PTimer *s, uint64_t count)
{
assert(s->in_transaction);
s->delta = count;
@@ -303,7 +303,7 @@ void ptimer_set_count(ptimer_state *s, uint64_t count)
}
}
-void ptimer_run(ptimer_state *s, int oneshot)
+void ptimer_run(PTimer *s, int oneshot)
{
bool was_disabled = !s->enabled;
@@ -323,7 +323,7 @@ void ptimer_run(ptimer_state
Re: [PATCH v4 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use.
On 2/17/23 10:29 AM, Jonathan Cameron wrote: This infrastructure will be reused for CXL RAS error injection in patches that follow. Signed-off-by: Jonathan Cameron Reviewed-by: Dave Jiang --- hw/pci/pci-internal.h | 1 - include/hw/pci/pcie_aer.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h index 2ea356bdf5..a7d6d8a732 100644 --- a/hw/pci/pci-internal.h +++ b/hw/pci/pci-internal.h @@ -20,6 +20,5 @@ void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); int pcie_aer_parse_error_string(const char *error_name, uint32_t *status, bool *correctable); -int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err); #endif diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h index 65e71d98fe..1234fdc4e2 100644 --- a/include/hw/pci/pcie_aer.h +++ b/include/hw/pci/pcie_aer.h @@ -100,4 +100,5 @@ void pcie_aer_root_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len, uint32_t root_cmd_prev); +int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err); #endif /* QEMU_PCIE_AER_H */
Re: [PATCH v4 5/8] hw/mem/cxl-type3: Add AER extended capability
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 217a5e639b..6cdd988d1d 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -250,6 +250,7 @@ static void ct3d_config_write(PCIDevice *pci_dev, uint32_t
addr, uint32_t val,
pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
pci_default_write_config(pci_dev, addr, val, size);
+pcie_aer_write_config(pci_dev, addr, val, size);
}
/*
@@ -452,8 +453,19 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
cxl_cstate->cdat.private = ct3d;
cxl_doe_cdat_init(cxl_cstate, errp);
+
+pcie_cap_deverr_init(pci_dev);
+/* Leave a bit of room for expansion */
+rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL);
+if (rc) {
+goto err_release_cdat;
+}
+
return;
+err_release_cdat:
+cxl_doe_cdat_release(cxl_cstate);
+g_free(regs->special_ops);
err_address_space_free:
address_space_destroy(&ct3d->hostmem_as);
return;
@@ -465,6 +477,7 @@ static void ct3_exit(PCIDevice *pci_dev)
CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
ComponentRegisters *regs = &cxl_cstate->crb;
+pcie_aer_exit(pci_dev);
cxl_doe_cdat_release(cxl_cstate);
g_free(regs->special_ops);
address_space_destroy(&ct3d->hostmem_as);
Re: [PATCH v4 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 00195257f7..7dfd20aa67 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -22,6 +22,7 @@
#include "qemu/range.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie_port.h"
+#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
@@ -29,6 +30,10 @@
#define CXL_ROOT_PORT_DID 0x7075
+#define CXL_RP_MSI_OFFSET 0x60
+#define CXL_RP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
+#define CXL_RP_MSI_NR_VECTOR2
+
/* Copied from the gen root port which we derive */
#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
@@ -47,6 +52,49 @@ typedef struct CXLRootPort {
#define TYPE_CXL_ROOT_PORT "cxl-rp"
DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT)
+/*
+ * If two MSI vector are allocated, Advanced Error Interrupt Message Number
+ * is 1. otherwise 0.
+ * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
+ */
+static uint8_t cxl_rp_aer_vector(const PCIDevice *d)
+{
+switch (msi_nr_vectors_allocated(d)) {
+case 1:
+return 0;
+case 2:
+return 1;
+case 4:
+case 8:
+case 16:
+case 32:
+default:
+break;
+}
+abort();
+return 0;
+}
+
+static int cxl_rp_interrupts_init(PCIDevice *d, Error **errp)
+{
+int rc;
+
+rc = msi_init(d, CXL_RP_MSI_OFFSET, CXL_RP_MSI_NR_VECTOR,
+ CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
+ CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
+ errp);
+if (rc < 0) {
+assert(rc == -ENOTSUP);
+}
+
+return rc;
+}
+
+static void cxl_rp_interrupts_uninit(PCIDevice *d)
+{
+msi_uninit(d);
+}
+
static void latch_registers(CXLRootPort *crp)
{
uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers;
@@ -183,6 +231,15 @@ static void cxl_rp_dvsec_write_config(PCIDevice *dev,
uint32_t addr,
}
}
+static void cxl_rp_aer_vector_update(PCIDevice *d)
+{
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
+
+if (rpc->aer_vector) {
+pcie_aer_root_set_vector(d, rpc->aer_vector(d));
+}
+}
+
static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
int len)
{
@@ -192,6 +249,7 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
pci_bridge_write_config(d, address, val, len);
+cxl_rp_aer_vector_update(d);
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
pcie_aer_write_config(d, address, val, len);
@@ -220,6 +278,9 @@ static void cxl_root_port_class_init(ObjectClass *oc, void
*data)
rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
+rpc->aer_vector = cxl_rp_aer_vector;
+rpc->interrupts_init = cxl_rp_interrupts_init;
+rpc->interrupts_uninit = cxl_rp_interrupts_uninit;
dc->hotpluggable = false;
}
Re: [PATCH v4 3/8] hw/pci-bridge/cxl_root_port: Wire up AER
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 6664783974..00195257f7 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -187,12 +187,15 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
int len)
{
uint16_t slt_ctl, slt_sta;
+uint32_t root_cmd =
+pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
pci_bridge_write_config(d, address, val, len);
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
pcie_aer_write_config(d, address, val, len);
+pcie_aer_root_write_config(d, address, val, len, root_cmd);
cxl_rp_dvsec_write_config(d, address, val, len);
}
Re: Lost partition tables on ide-hd + ahci drive
I think it's guest memory again. IMHO It's a part of a memory pool and not real IO data (unless this was pagefile data). The first 16 bytes look like POOL_HEADER structure. The first dump contained signature from FilterManager and the latest contains two structures from Ntfs. It's not clear to me what exact data after header structure, but in case of Ntfs it looks like doubly linked list element with Flink/Blink pointers: 60 a5 a6 d4 0c a8 ff ff, - is a 0xa80cd4a6a560, and 30 15 d9 e6 0c a8 ff ff = 0xa80ce6d91530. The first Ntfs, looks like a final element of something, while the second is a middle part of something else. That is why I think it is not real IO (i.e disk data sent by guest NTFS driver). IMHO. I can not tell anything about dma-reentracy issues, but yes, i would start to look at check_cmd() function call sequence. The most interesting is why Sector Count = 1. I thought about race with IDE reset where registers initialized with value SATA_SIGNATURE_DISK = 0x0101, but this means LBA=1 as well... Regards, Mike On Fri, Feb 17, 2023 at 4:40 PM Fiona Ebner wrote: > > Am 16.02.23 um 15:17 schrieb Mike Maslenkin: > > Does additional comparison make a sense here: check for LBA == 0 and > > then check MBR signature bytes. > > Additionally it’s easy to check buffer_is_zero() result or even print > > FIS contents under these conditions. > > Data looks like a part of guest memory of 64bit Windows. > > Just today we got a new dump [0], and it's very similar. Again only 512 > bytes and again guest memory? > > > febner@enia ~/Downloads % hexdump -C dump.raw > > 00 03 22 00 4e 74 46 73 da 4c a3 1c 3b f5 7d 19 > > |..".NtFs.L..;.}.| > > 0010 60 a5 a6 d4 0c a8 ff ff 30 15 d9 e6 0c a8 ff ff > > |`...0...| > > 0020 5c 00 53 00 6f 00 66 00 74 00 77 00 61 00 72 00 > > |\.S.o.f.t.w.a.r.| > > 0030 65 00 44 00 69 00 73 00 74 00 72 00 69 00 62 00 > > |e.D.i.s.t.r.i.b.| > > 0040 75 00 74 00 69 00 6f 00 6e 00 5c 00 44 00 6f 00 > > |u.t.i.o.n.\.D.o.| > > 0050 77 00 6e 00 6c 00 6f 00 61 00 64 00 5c 00 37 00 > > |w.n.l.o.a.d.\.7.| > > 0060 33 00 63 00 36 00 33 00 65 00 32 00 64 00 37 00 > > |3.c.6.3.e.2.d.7.| > > 0070 66 00 66 00 38 00 66 00 36 00 35 00 31 00 31 00 > > |f.f.8.f.6.5.1.1.| > > 0080 39 00 36 00 63 00 65 00 61 00 31 00 65 00 30 00 > > |9.6.c.e.a.1.e.0.| > > 0090 39 00 66 00 66 00 36 00 32 00 30 00 65 00 5c 00 > > |9.f.f.6.2.0.e.\.| > > 00a0 69 00 6e 00 73 00 74 00 5c 00 70 00 61 00 63 00 > > |i.n.s.t.\.p.a.c.| > > 00b0 6b 00 61 00 67 00 65 00 5f 00 39 00 31 00 37 00 > > |k.a.g.e._.9.1.7.| > > 00c0 31 00 5f 00 66 00 6f 00 72 00 5f 00 6b 00 62 00 > > |1._.f.o.r._.k.b.| > > 00d0 35 00 30 00 32 00 32 00 38 00 33 00 38 00 7e 00 > > |5.0.2.2.8.3.8.~.| > > 00e0 33 00 31 00 62 00 66 00 33 00 38 00 35 00 36 00 > > |3.1.b.f.3.8.5.6.| > > 00f0 61 00 64 00 33 00 36 00 34 00 65 00 33 00 35 00 > > |a.d.3.6.4.e.3.5.| > > 0100 7e 00 61 00 6d 00 64 00 36 00 34 00 7e 00 7e 00 > > |~.a.m.d.6.4.~.~.| > > 0110 31 00 30 00 2e 00 30 00 2e 00 31 00 2e 00 31 00 > > |1.0...0...1...1.| > > 0120 33 00 2e 00 63 00 61 00 74 00 1d 08 0d a8 ff ff > > |3...c.a.t...| > > 0130 13 03 0f 00 4e 74 46 73 ea 4d a3 1c 3b f5 7d 19 > > |NtFs.M..;.}.| > > 0140 90 05 4d 0f 0d a8 ff ff a0 0c 55 0d 0d a8 ff ff > > |..M...U.| > > 0150 43 52 4f 53 4f 46 54 2d 57 49 4e 44 4f 57 53 2d > > |CROSOFT-WINDOWS-| > > 0160 44 2e 2e 2d 57 49 4e 50 52 4f 56 49 44 45 52 53 > > |D..-WINPROVIDERS| > > 0170 2d 41 53 53 4f 43 5f 33 31 42 46 33 38 35 36 41 > > |-ASSOC_31BF3856A| > > 0180 0c 03 67 00 70 00 73 00 63 00 72 00 69 00 70 00 > > |..g.p.s.c.r.i.p.| > > 0190 74 00 2e 00 65 00 78 00 65 00 37 00 36 00 34 00 > > |t...e.x.e.7.6.4.| > > 01a0 37 00 62 00 33 00 36 00 30 00 30 00 63 00 64 00 > > |7.b.3.6.0.0.c.d.| > > 01b0 65 00 30 00 34 00 31 00 35 00 39 00 35 00 32 00 > > |e.0.4.1.5.9.5.2.| > > 01c0 31 00 2e 00 74 00 6d 00 70 00 47 00 50 00 53 00 > > |1...t.m.p.G.P.S.| > > 01d0 43 00 52 00 49 00 50 00 54 00 2e 00 45 00 58 00 > > |C.R.I.P.T...E.X.| > > 01e0 45 00 37 00 36 00 34 00 37 00 42 00 33 00 36 00 > > |E.7.6.4.7.B.3.6.| > > 01f0 30 00 30 00 43 00 44 00 45 00 30 00 34 00 31 00 > > |0.0.C.D.E.0.4.1.| > > 0200 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > || > > * > > 0010 > > [0]: > https://forum.proxmox.com/threads/not-a-bootable-disk-vm-ms-server-2016.122849/post-534473 >
Re: [PATCH v4 2/8] hw/pci/aer: Add missing routing for AER errors
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pcie_aer.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 909e027d99..103667c368 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -192,8 +192,16 @@ static void pcie_aer_update_uncor_status(PCIDevice *dev)
static bool
pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
{
+uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
+ PCI_EXP_DEVCTL);
if (!(pcie_aer_msg_is_uncor(msg) &&
- (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
+ (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
+!((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
+ (devctl & PCI_EXP_DEVCTL_NFERE)) &&
+!((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
+ (devctl & PCI_EXP_DEVCTL_CERE)) &&
+!((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
+ (devctl & PCI_EXP_DEVCTL_FERE))) {
return false;
}
Re: [PATCH v4 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_regs.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 9a19be44ae..909e027d99 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver,
uint16_t offset,
pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
PCI_ERR_UNC_SUPPORTED);
+pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
+ PCI_ERR_UNC_MASK_DEFAULT);
+pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
+ PCI_ERR_UNC_SUPPORTED);
pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
PCI_ERR_UNC_SEVERITY_DEFAULT);
diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
index 963dc2e170..6ec4785448 100644
--- a/include/hw/pci/pcie_regs.h
+++ b/include/hw/pci/pcie_regs.h
@@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth {
PCI_ERR_UNC_ATOP_EBLOCKED |\
PCI_ERR_UNC_TLP_PRF_BLOCKED)
+#define PCI_ERR_UNC_MASK_DEFAULT(PCI_ERR_UNC_INTN | \
+ PCI_ERR_UNC_TLP_PRF_BLOCKED)
+
#define PCI_ERR_UNC_SEVERITY_DEFAULT(PCI_ERR_UNC_DLP | \
PCI_ERR_UNC_SDN | \
PCI_ERR_UNC_FCP | \
Re: [PATCH 2/2] hw/timer: Reduce 'hw/ptimer.h' inclusion
On 17/2/23 19:52, Thomas Huth wrote: On 17/02/2023 15.18, Philippe Mathieu-Daudé wrote: "hw/ptimer.h" API is mostly used by timer / watchdog device models. Since the SoC / machines only access the ptimer via reference, they don't need its definition: the declartion is enough. On order to reduce the inclusion on the source files, forward-declare 'ptimer_state' in "qemu/typedefs.h". Use the typedef in few place instead of the structure. Signed-off-by: Philippe Mathieu-Daudé --- "30 files changed"... but since this is trivial, there is no point in splitting per subsystem IMO. --- ... diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index df4b55ac65..effcba4bca 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -104,6 +104,7 @@ typedef struct PICCommonState PICCommonState; typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; +typedef struct ptimer_state ptimer_state; Would it make sense to properly CamelCase the type while you're at it anyway? PeriodicTimer, PTimerState, PTimer? This API is documented as 'ptimer API' although, and renaming all the API methods doesn't seem to bring much, so maybe stick to PTimer. More generically for QOM objects, we can agree for no 'State' trailing for instance state, and 'Class' trailing for class one, similar to Object / ObjectClass. I.e: PeriodicTimer // instance PeriodicTimerClass // class Maybe 'Device' is too generic? Here the API uses 'qdev_' prefix, so QDev / QDevClass could work...
Re: [PATCH v2 0/7] Python: Drop support for Python 3.6
On Thu, Feb 16, 2023 at 5:58 AM Thomas Huth wrote: > > On 15/02/2023 20.05, Markus Armbruster wrote: > > The discussion under PATCH 6 makes me think there's a bit of confusion > > about the actual impact of dropping support for Python 3.6. Possibly > > because it's spelled out in the commit message of PATCH 7. Let me > > summarize it in one sentence: > > > > *** All supported host systems continue to work *** > > > > Evidence: CI remains green. > > The CI remains green since one of the patches disabled the building of the > docs on CentOS 8. That's not how I'd describe "continue to work", at least > not in the same extend as before. > > > On some supported host systems, different packages need to be installed. > > On CentOS 8, for instance, we need to install Python 3.8.13 or 3.9.16 > > instead of 3.6.8. Let me stress again: same repository, different > > package. No downsides I can see. > > > > The *one* exception is Sphinx on CentOS 8. CentOS 8 does not ship a > > version of Sphinx that works with Python 3.7 or newer. This series > > proposes to simply stop building the docs there, unless the user > > provides a suitable version of Sphinx (which is easy enough with pip). > > I think we've all understood that. The thing that you obviously did not > understood: This breaks our support statement. > I'm pretty sure that you could also build the whole QEMU suite successfully > on an ancient CentOS 7 or Ubuntu 18.04 system if you manually install a > newer version of GCC and some of the required libraries first. But that's > not how we understand our support statement. > > Sure, you can argue that you can use "pip install" to get a newer version of > Sphinx on RHEL 8 / CentOS 8 to continue building the docs there - but is > that really that much different from installing a newer version of GCC and > libraries on an ancient distro that we do not officially support anymore? > I'd say no. You also have to consider that not every build host has access > to the internet, maybe some companies only have an internal mirror of the > distro packages in their intranet (I remember some discussion about such a > case in the past) - so while you were perfectly fine to build the whole of > QEMU on a CentOS 8 there before this change, you could now not build parts > of QEMU anymore there due to the missing possibility to run "pip install" > without full internet connection. There are good points elsewhere in this thread and I am taking notes, but this critique caught my eye as something I was not specifically planning around, so I wanted to get an elaboration here if I may. Do we have a support statement for this? I find this critique somewhat surprising -- If we don't have internet, how did we get the other 20 to 30 dependencies needed to build QEMU? To what extent are we *required* to preserve a build that works without internet access? you generally need internet to run "dnf install", as you would to "pip install", so how does this distinction exclude one but not the other? If you mean to say: "The build cannot rely on using internet-connected pip to configure an environment just-in-time during a build because internet may not be present" -- I completely agree, as this is a necessity for e.g. RHEL packaging downstream. That requirement won't be violated by me. --js
[PATCH v3] configure: Add 'mkdir build' check
QEMU configure script goes into an infinite error printing loop when in read only directory due to 'build' dir never being created. Checking if 'mkdir dir' succeeds prevents this error. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/321 Signed-off-by: Dinah Baum --- Changes since v2: Updated error message Reverted changes to 'help' command configure | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 00415f0b48..784f9d18a5 100755 --- a/configure +++ b/configure @@ -31,7 +31,12 @@ then fi fi -mkdir build +if ! mkdir build || ! touch $MARKER +then +echo "ERROR: Could not create ./build directory. Check the permissions on +your source directory, or try doing an out-of-tree build." +exit 1 +fi touch $MARKER cat > GNUmakefile <<'EOF' -- 2.30.2
[PATCH v6 0/4] riscv: Add support for Zicbo[m,z,p] instructions
Hi,
This new version contains a change in patch 2 based on Richard's
feedback in v5 [1].
Changes from v5:
- patch 2:
- check if 'mem' is mapped into RAM with 'tlb_vaddr_to_host' before
zeroing it.
- v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html
Christoph Muellner (4):
accel/tcg: Add probe_access_range_flags interface
target/riscv: implement Zicboz extension
target/riscv: implement Zicbom extension
target/riscv: add Zicbop cbo.prefetch{i,r,m} placeholder
accel/tcg/cputlb.c | 19 +++
accel/tcg/user-exec.c | 15 +-
include/exec/exec-all.h | 24 +++
target/riscv/cpu.c | 7 +
target/riscv/cpu.h | 4 +
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 16 +-
target/riscv/insn_trans/trans_rvzicbo.c.inc | 57 +++
target/riscv/op_helper.c| 162
target/riscv/translate.c| 1 +
10 files changed, 306 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
--
2.39.2
[PATCH v6 4/4] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
From: Christoph Muellner
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3788f86528..1aebd37572 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -134,6 +134,7 @@ addi . 000 . 0010011 @i
slti . 010 . 0010011 @i
sltiu . 011 . 0010011 @i
xori . 100 . 0010011 @i
+# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
ori . 110 . 0010011 @i
andi . 111 . 0010011 @i
slli 0. ... 001 . 0010011 @sh
--
2.39.2
[PATCH v6 1/4] accel/tcg: Add probe_access_range_flags interface
From: Christoph Muellner
The existing probe_access* functions do not allow to specify the
access size and a non-faulting behavior at the same time.
This is resolved by adding a generalization of probe_access_flags()
that takes an additional size parameter.
The semantics is basically the same as probe_access_flags(),
but instead of assuming an access to any byte of the addressed
page, we can restrict to access to a specific area, like
probe_access() allows.
Signed-off-by: Christoph Muellner
---
accel/tcg/cputlb.c | 19 +++
accel/tcg/user-exec.c | 15 ---
include/exec/exec-all.h | 24
3 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 4812d83961..dd3bc7a356 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1606,6 +1606,25 @@ int probe_access_full(CPUArchState *env, target_ulong
addr,
return flags;
}
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t retaddr)
+{
+CPUTLBEntryFull *full;
+int flags = probe_access_internal(env, addr, size, access_type,
+ mmu_idx, nonfault, phost, &full,
+ retaddr);
+
+/* Handle clean RAM pages. */
+if (unlikely(flags & TLB_NOTDIRTY)) {
+notdirty_write(env_cpu(env), addr, 1, full, retaddr);
+flags &= ~TLB_NOTDIRTY;
+}
+
+return flags;
+}
+
int probe_access_flags(CPUArchState *env, target_ulong addr,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index ae67d84638..a73c840655 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -761,9 +761,10 @@ static int probe_access_internal(CPUArchState *env,
target_ulong addr,
cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra);
}
-int probe_access_flags(CPUArchState *env, target_ulong addr,
- MMUAccessType access_type, int mmu_idx,
- bool nonfault, void **phost, uintptr_t ra)
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t ra)
{
int flags;
@@ -772,6 +773,14 @@ int probe_access_flags(CPUArchState *env, target_ulong
addr,
return flags;
}
+int probe_access_flags(CPUArchState *env, target_ulong addr,
+ MMUAccessType access_type, int mmu_idx,
+ bool nonfault, void **phost, uintptr_t ra)
+{
+return probe_access_range_flags(env, addr, 0, access_type, mmu_idx,
+nonfault, phost, ra);
+}
+
void *probe_access(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t ra)
{
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 54585a9954..b75f15f247 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -442,6 +442,30 @@ static inline void *probe_read(CPUArchState *env,
target_ulong addr, int size,
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
}
+/**
+ * probe_access_range_flags:
+ * @env: CPUArchState
+ * @addr: guest virtual address to look up
+ * @size: size of the access
+ * @access_type: read, write or execute permission
+ * @mmu_idx: MMU index to use for lookup
+ * @nonfault: suppress the fault
+ * @phost: return value for host address
+ * @retaddr: return address for unwinding
+ *
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
+ * the access range, and storing the host address for RAM in @phost.
+ *
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
+ * Do handle clean pages, so exclude TLB_NOTDIRTY from the returned flags.
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
+ */
+int probe_access_range_flags(CPUArchState *env, target_ulong addr,
+ int size, MMUAccessType access_type,
+ int mmu_idx, bool nonfault, void **phost,
+ uintptr_t retaddr);
+
/**
* probe_access_flags:
* @env: CPUArchState
--
2.39.2
[PATCH v6 3/4] target/riscv: implement Zicbom extension
From: Christoph Muellner
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].
The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group as LQ and
cbo.zero due to overlapping patterns.
All these instructions can throw a Illegal Instruction/Virtual
Instruction exception, similar to the existing cbo.zero. The same
check_zicbo_envcfg() is used to handle these exceptions.
Aside from that, these instructions also need to handle page faults and
guest page faults. This is done in a new check_zicbom_access() helper.
As with Zicboz, the cache block size for Zicbom is also configurable.
Note that the spec determines that Zicbo[mp] and Zicboz can have
different cache sizes (Section 2.7 of [1]), so we also include a
'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They
are set to the same size, so unless users want to play around with the
settings both sizes will be the same.
[1]
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 2 +
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvzicbo.c.inc | 27 +
target/riscv/op_helper.c| 107
6 files changed, 146 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7dd37de7f9..4b779b1775 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -74,6 +74,7 @@ struct isa_ext_data {
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
+ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
@@ -1127,6 +1128,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
+DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6b4c714d3a..a0673b4604 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -447,6 +447,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+bool ext_icbom;
bool ext_icboz;
bool ext_zihintpause;
bool ext_smstateen;
@@ -495,6 +496,7 @@ struct RISCVCPUConfig {
char *vext_spec;
uint16_t vlen;
uint16_t elen;
+uint16_t cbom_blocksize;
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ce165821b8..37b54e0991 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -98,6 +98,8 @@ DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64)
/* Cache-block operations */
+DEF_HELPER_2(cbo_clean_flush, void, env, tl)
+DEF_HELPER_2(cbo_inval, void, env, tl)
DEF_HELPER_2(cbo_zero, void, env, tl)
/* Special functions */
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3985bc703f..3788f86528 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -181,6 +181,11 @@ sraw 010 . . 101 . 0111011 @r
ldu . 111 . 011 @i
{
[
+# *** RV32 Zicbom Standard Extension ***
+cbo_clean 000 1 . 010 0 000 @sfence_vm
+cbo_flush 000 00010 . 010 0 000 @sfence_vm
+cbo_inval 000 0 . 010 0 000 @sfence_vm
+
# *** RV32 Zicboz Standard Extension ***
cbo_zero 000 00100 . 010 0 000 @sfence_vm
]
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index feabc28342..7df9c30b58 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -16,12 +16,39 @@
* this program. If not, see
[PATCH v6 2/4] target/riscv: implement Zicboz extension
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Block Zero extension, Zicboz. It
uses the cbo.zero instruction that, as with all CBO instructions that
will be added later, needs to be implemented in an overlap group with
the LQ instruction due to overlapping patterns.
cbo.zero throws a Illegal Instruction/Virtual Instruction exception
depending on CSR state. This is also the case for the remaining cbo
instructions we're going to add next, so create a check_zicbo_envcfg()
that will be used by all Zicbo[mz] instructions.
[1]
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 4 ++
target/riscv/cpu.h | 2 +
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 10 +++-
target/riscv/insn_trans/trans_rvzicbo.c.inc | 30 +++
target/riscv/op_helper.c| 55 +
target/riscv/translate.c| 1 +
7 files changed, 104 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..7dd37de7f9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -74,6 +74,7 @@ struct isa_ext_data {
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
+ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0,
ext_zihintpause),
@@ -1126,6 +1127,9 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
+DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* Vendor-specific custom extensions */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..6b4c714d3a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -447,6 +447,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+bool ext_icboz;
bool ext_zihintpause;
bool ext_smstateen;
bool ext_sstc;
@@ -494,6 +495,7 @@ struct RISCVCPUConfig {
char *vext_spec;
uint16_t vlen;
uint16_t elen;
+uint16_t cboz_blocksize;
bool mmu;
bool pmp;
bool epmp;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0497370afd..ce165821b8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -97,6 +97,9 @@ DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64)
+/* Cache-block operations */
+DEF_HELPER_2(cbo_zero, void, env, tl)
+
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b7e7613ea2..3985bc703f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -179,7 +179,15 @@ sraw 010 . . 101 . 0111011 @r
# *** RV128I Base Instruction Set (in addition to RV64I) ***
ldu . 111 . 011 @i
-lq . 010 . 000 @i
+{
+ [
+# *** RV32 Zicboz Standard Extension ***
+cbo_zero 000 00100 . 010 0 000 @sfence_vm
+ ]
+
+ # *** RVI128 lq ***
+ lq . 010 . 000 @i
+}
sq . 100 . 0100011 @s
addid . 000 . 1011011 @i
sllid00 .. . 001 . 1011011 @sh6
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
new file mode 100644
index 00..feabc28342
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -0,0 +1,30 @@
+/*
+ * RISC-V translation routines for the RISC-V CBO Extension.
+ *
+ * Copyright (c) 2021 Philipp Tomsich, philipp.toms...@vrull.eu
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Soft
[PATCH v6 19/29] target/arm: Move 64-bit TCG CPUs into tcg/
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we still cannot move all of the TCG code
into the tcg directory because the qtests might reach the !kvm && !hvf
branch. Keep the cortex_a57_initfn() call to cover that scenario.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
hw/arm/virt.c | 6 +-
target/arm/cpu64.c | 633 +--
target/arm/internals.h | 4 +
target/arm/tcg/cpu64.c | 655 +
target/arm/tcg/meson.build | 1 +
5 files changed, 676 insertions(+), 623 deletions(-)
create mode 100644 target/arm/tcg/cpu64.c
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 75f28947de..20a18d0ba1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -206,14 +206,16 @@ static const int a15irqmap[] = {
static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
-ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a55"),
-ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
+#endif
+ARM_CPU_TYPE_NAME("cortex-a53"),
+ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
};
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index ab2818dc15..1c8f1ef17f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -24,6 +24,8 @@
#include "qemu/module.h"
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
+#include "sysemu/qtest.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "qapi/visitor.h"
@@ -92,86 +94,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
#ifdef TARGET_AARCH64
-static void aarch64_a35_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-
-cpu->dtb_compatible = "arm,cortex-a35";
-set_feature(&cpu->env, ARM_FEATURE_V8);
-set_feature(&cpu->env, ARM_FEATURE_NEON);
-set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-set_feature(&cpu->env, ARM_FEATURE_EL2);
-set_feature(&cpu->env, ARM_FEATURE_EL3);
-set_feature(&cpu->env, ARM_FEATURE_PMU);
-
-/* From B2.2 AArch64 identification registers. */
-cpu->midr = 0x411fd040;
-cpu->revidr = 0;
-cpu->ctr = 0x84448004;
-cpu->isar.id_pfr0 = 0x0131;
-cpu->isar.id_pfr1 = 0x00011011;
-cpu->isar.id_dfr0 = 0x03010066;
-cpu->id_afr0 = 0;
-cpu->isar.id_mmfr0 = 0x10201105;
-cpu->isar.id_mmfr1 = 0x4000;
-cpu->isar.id_mmfr2 = 0x0126;
-cpu->isar.id_mmfr3 = 0x02102211;
-cpu->isar.id_isar0 = 0x02101110;
-cpu->isar.id_isar1 = 0x13112111;
-cpu->isar.id_isar2 = 0x21232042;
-cpu->isar.id_isar3 = 0x01112131;
-cpu->isar.id_isar4 = 0x00011142;
-cpu->isar.id_isar5 = 0x00011121;
-cpu->isar.id_aa64pfr0 = 0x;
-cpu->isar.id_aa64pfr1 = 0;
-cpu->isar.id_aa64dfr0 = 0x10305106;
-cpu->isar.id_aa64dfr1 = 0;
-cpu->isar.id_aa64isar0 = 0x00011120;
-cpu->isar.id_aa64isar1 = 0;
-cpu->isar.id_aa64mmfr0 = 0x00101122;
-cpu->isar.id_aa64mmfr1 = 0;
-cpu->clidr = 0x0a200023;
-cpu->dcz_blocksize = 4;
-
-/* From B2.4 AArch64 Virtual Memory control registers */
-cpu->reset_sctlr = 0x00c50838;
-
-/* From B2.10 AArch64 performance monitor registers */
-cpu->isar.reset_pmcr_el0 = 0x410a3000;
-
-/* From B2.29 Cache ID registers */
-cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
-cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
-cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
-
-/* From B3.5 VGIC Type register */
-cpu->gic_num_lrs = 4;
-cpu->gic_vpribits = 5;
-cpu->gic_vprebits = 5;
-cpu->gic_pribits = 5;
-
-/* From C6.4 Debug ID Register */
-cpu->isar.dbgdidr = 0x3516d000;
-/* From C6.5 Debug Device ID Register */
-cpu->isar.dbgdevid = 0x00110f13;
-/* From C6.6 Debug Device ID Register 1 */
-cpu->isar.dbgdevid1 = 0x2;
-
-/* From Cortex-A35 SIMD and Floating-point Support r1p0 */
-/* From 3.2 AArch32 register summary */
-cpu->reset_fpsid = 0x41034043;
-
-/* From 2.2 AArch64 register summary */
-cpu->isar.mvfr0 = 0x10110222;
-cpu->isar.mvfr1 = 0x1211;
-cpu->isar.mvfr2 = 0x0043;
-
-/* These values are the same with A53/A57/A72. */
-define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
@@ -371,47 +293,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
cpu->sve_vq.map =
Re: [RFC PATCH] docs/about/build-platforms: Refine the distro support policy
Il ven 17 feb 2023, 19:47 Thomas Huth ha scritto: > On 17/02/2023 16.59, Daniel P. Berrangé wrote: > > On Fri, Feb 17, 2023 at 04:55:49PM +0100, Markus Armbruster wrote: > > > The cost/benefit tradeoff of dropping the platforms entirely > > is not obviously favourable when we don't have clear demand > > to bump the min versions of native packages, and the cost to > > users stuck on these platforms to build their own toolchain > > or libraries is very high. > > There's another urgent point which I completely forget to mention in my > patch description (not sure how I managed that, since it's bugging me > quite > badly in the past weeks): We're struggling heavily with CI minutes. The only viable solution for CI minutes is going to be private runners, it's not easy to cut 30% of the jobs. We're using less than half of our Azure sponsorship budget, and could also find other sources; either Azure Kubernetes or AWS Fargate are pretty cheap for running CI because unlike VM instances you pay for just the time that CI is running (at least with Azure you still have VMs but they scale out dynamically). The complicated part is setting up the kubernetes executor for gitlab-runner, but we'll find someone. :) Paolo If we > have to support multiple major releases for a long time in parallel, there > will always be the desire to have all major releases also tested in the CI > ... and honestly, we're really struggling quite badly there right now - as > you know, we've already run out of CI minutes in January in the main > project, and also in my forked repo I'm struggling each month. > Additionally, > it's of course additional effort to keep everything in the "green" state > the > more you have to support. > > We're currently "lucky" in a sense that we're only testing one version of > CentOS, Debian and Ubuntu right now, but there have been voices in the > past > weeks asking for more already (like we also did in the past already). I'd > really appreciate if we could have a clearer policy here to support less > at > the same time. It would help with the pressure on the CI and the effort > and > time it takes to maintain all that stuff. > > Thomas > >
[PATCH v6 24/29] target/avocado: Pass parameters to migration test
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep the current behavior of only running
migration tests when the qemu target matches the host architecture.
Signed-off-by: Fabiano Rosas
---
tests/avocado/migration.py | 83 +++---
1 file changed, 78 insertions(+), 5 deletions(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 4b25680c50..8b2ec0e3c4 100644
--- a/tests/avocado/migration.py
+++ b/tests/avocado/migration.py
@@ -11,6 +11,8 @@
import tempfile
+import os
+
from avocado_qemu import QemuSystemTest
from avocado import skipUnless
@@ -19,7 +21,7 @@
from avocado.utils.path import find_command
-class Migration(QemuSystemTest):
+class MigrationTest(QemuSystemTest):
"""
:avocado: tags=migration
"""
@@ -62,20 +64,91 @@ def _get_free_port(self):
self.cancel('Failed to find a free port')
return port
-
-def test_migration_with_tcp_localhost(self):
+def migration_with_tcp_localhost(self):
dest_uri = 'tcp:localhost:%u' % self._get_free_port()
self.do_migrate(dest_uri)
-def test_migration_with_unix(self):
+def migration_with_unix(self):
with tempfile.TemporaryDirectory(prefix='socket_') as socket_path:
dest_uri = 'unix:%s/qemu-test.sock' % socket_path
self.do_migrate(dest_uri)
@skipUnless(find_command('nc', default=False), "'nc' command not found")
-def test_migration_with_exec(self):
+def migration_with_exec(self):
"""The test works for both netcat-traditional and netcat-openbsd
packages."""
free_port = self._get_free_port()
dest_uri = 'exec:nc -l localhost %u' % free_port
src_uri = 'exec:nc localhost %u' % free_port
self.do_migrate(dest_uri, src_uri)
+
+
+@skipUnless('aarch64' in os.uname()[4], "host != target")
+class Aarch64(MigrationTest):
+"""
+:avocado: tags=arch:aarch64
+:avocado: tags=machine:virt
+:avocado: tags=cpu:max
+"""
+
+def test_migration_with_tcp_localhost(self):
+self.migration_with_tcp_localhost()
+
+def test_migration_with_unix(self):
+self.migration_with_unix()
+
+def test_migration_with_exec(self):
+self.migration_with_exec()
+
+
+@skipUnless('x86_64' in os.uname()[4], "host != target")
+class X86_64(MigrationTest):
+"""
+:avocado: tags=arch:x86_64
+:avocado: tags=machine:pc
+:avocado: tags=cpu:qemu64
+"""
+
+def test_migration_with_tcp_localhost(self):
+self.migration_with_tcp_localhost()
+
+def test_migration_with_unix(self):
+self.migration_with_unix()
+
+def test_migration_with_exec(self):
+self.migration_with_exec()
+
+
+@skipUnless('ppc64le' in os.uname()[4], "host != target")
+class PPC64(MigrationTest):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:pseries
+:avocado: tags=cpu:power9_v2.0
+"""
+
+def test_migration_with_tcp_localhost(self):
+self.migration_with_tcp_localhost()
+
+def test_migration_with_unix(self):
+self.migration_with_unix()
+
+def test_migration_with_exec(self):
+self.migration_with_exec()
+
+
+@skipUnless('s390x' in os.uname()[4], "host != target")
+class S390X(MigrationTest):
+"""
+:avocado: tags=arch:s390x
+:avocado: tags=machine:s390-ccw-virtio
+:avocado: tags=cpu:qemu
+"""
+
+def test_migration_with_tcp_localhost(self):
+self.migration_with_tcp_localhost()
+
+def test_migration_with_unix(self):
+self.migration_with_unix()
+
+def test_migration_with_exec(self):
+self.migration_with_exec()
--
2.35.3
[PATCH v6 14/29] target/arm: Don't access TCG code when debugging with KVM
When TCG is disabled this part of the code should not be reachable, so
wrap it with an ifdef for now.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/ptw.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2b125fff44..be0cc6bc15 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -254,6 +254,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate
*ptw,
ptw->out_host = NULL;
ptw->out_rw = false;
} else {
+#ifdef CONFIG_TCG
CPUTLBEntryFull *full;
int flags;
@@ -270,6 +271,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate
*ptw,
ptw->out_rw = full->prot & PAGE_WRITE;
pte_attrs = full->pte_attrs;
pte_secure = full->attrs.secure;
+#else
+g_assert_not_reached();
+#endif
}
if (regime_is_stage2(s2_mmu_idx)) {
--
2.35.3
[PATCH v6 12/29] target/arm: Move hflags code into the tcg directory
The hflags are used only for TCG code, so introduce a new file
hflags.c to keep that code.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c| 393 +---
target/arm/internals.h | 2 +
target/arm/tcg-stubs.c | 4 +
target/arm/tcg/hflags.c| 403 +
target/arm/tcg/meson.build | 1 +
5 files changed, 411 insertions(+), 392 deletions(-)
create mode 100644 target/arm/tcg/hflags.c
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2c4336bab6..4da3095c4c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6669,32 +6669,6 @@ int sme_exception_el(CPUARMState *env, int el)
return 0;
}
-/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
-static bool sme_fa64(CPUARMState *env, int el)
-{
-if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
-return false;
-}
-
-if (el <= 1 && !el_is_in_host(env, el)) {
-if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
-return false;
-}
-}
-if (el <= 2 && arm_is_el2_enabled(env)) {
-if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
-return false;
-}
-}
-if (arm_feature(env, ARM_FEATURE_EL3)) {
-if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
-return false;
-}
-}
-
-return true;
-}
-
/*
* Given that SVE is enabled, return the vector length for EL.
*/
@@ -11142,7 +6,7 @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx
mmu_idx)
}
}
-static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
{
if (regime_has_2_ranges(mmu_idx)) {
return extract64(tcr, 57, 2);
@@ -11853,371 +11827,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
return arm_mmu_idx_el(env, arm_current_el(env));
}
-static inline bool fgt_svc(CPUARMState *env, int el)
-{
-/*
- * Assuming fine-grained-traps are active, return true if we
- * should be trapping on SVC instructions. Only AArch64 can
- * trap on an SVC at EL1, but we don't need to special-case this
- * because if this is AArch32 EL1 then arm_fgt_active() is false.
- * We also know el is 0 or 1.
- */
-return el == 0 ?
-FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
-FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
-}
-
-static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx,
- CPUARMTBFlags flags)
-{
-DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
-DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
-
-if (arm_singlestep_active(env)) {
-DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
-}
-
-return flags;
-}
-
-static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx,
- CPUARMTBFlags flags)
-{
-bool sctlr_b = arm_sctlr_b(env);
-
-if (sctlr_b) {
-DP_TBFLAG_A32(flags, SCTLR__B, 1);
-}
-if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
-DP_TBFLAG_ANY(flags, BE_DATA, 1);
-}
-DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
-
-return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
-}
-
-static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
-ARMMMUIdx mmu_idx)
-{
-CPUARMTBFlags flags = {};
-uint32_t ccr = env->v7m.ccr[env->v7m.secure];
-
-/* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
-if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
-DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
-}
-
-if (arm_v7m_is_handler_mode(env)) {
-DP_TBFLAG_M32(flags, HANDLER, 1);
-}
-
-/*
- * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
- * is suppressing them because the requested execution priority
- * is less than 0.
- */
-if (arm_feature(env, ARM_FEATURE_V8) &&
-!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
- (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
-DP_TBFLAG_M32(flags, STACKCHECK, 1);
-}
-
-if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
-DP_TBFLAG_M32(flags, SECURE, 1);
-}
-
-return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
-}
-
-static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
-ARMMMUIdx mmu_idx)
-{
-CPUARMTBFlags flags = {};
-int el = arm_current_el(env);
-
-if (arm_sctlr(env, el) & SCTLR_A) {
-DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
-}
-
-if (arm_el_is_aa64(env, 1)) {
-DP_TBFLAG_A32(flags, VFPEN, 1);
-}
-
-if (el < 2 && env->cp15.hstr_el2 &&
[PATCH v6 17/29] tests/avocado: Skip tests that require a missing accelerator
If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.
We can now write tests without explicit calls to require_accelerator,
just the tag is enough.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
tests/avocado/avocado_qemu/__init__.py | 4
1 file changed, 4 insertions(+)
diff --git a/tests/avocado/avocado_qemu/__init__.py
b/tests/avocado/avocado_qemu/__init__.py
index 25a546842f..a313e88c07 100644
--- a/tests/avocado/avocado_qemu/__init__.py
+++ b/tests/avocado/avocado_qemu/__init__.py
@@ -274,6 +274,10 @@ def setUp(self):
super().setUp('qemu-system-')
+accel_required = self._get_unique_tag_val('accel')
+if accel_required:
+self.require_accelerator(accel_required)
+
self.machine = self.params.get('machine',
default=self._get_unique_tag_val('machine'))
--
2.35.3
[PATCH v6 21/29] target/arm: Use "max" as default cpu for the virt machine with KVM
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed-off-by: Fabiano Rosas
Acked-by: Richard Henderson
Reviewed-by: Thomas Huth
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index fbeeed115d..cc6b8ff85f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3015,7 +3015,11 @@ static void virt_machine_class_init(ObjectClass *oc,
void *data)
mc->minimum_page_bits = 12;
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#else
+mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
+#endif
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
assert(!mc->get_hotplug_handler);
--
2.35.3
[PATCH v6 26/29] arm/Kconfig: Always select SEMIHOSTING when TCG is present
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in default.mak anymore. So reflect the change in a Kconfig. Instead of using semihosting/Kconfig, use a target-specific file, so that the change doesn't affect other architectures which might implement semihosting in a way compatible with KVM. The selection from ARM_v7M needs to be removed to avoid a cycle during parsing. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- configs/devices/arm-softmmu/default.mak | 2 -- hw/arm/Kconfig | 1 - target/arm/Kconfig | 7 +++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak index 1b49a7830c..cb3e5aea65 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -40,6 +40,4 @@ CONFIG_MICROBIT=y CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y -CONFIG_SEMIHOSTING=y -CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2d157de9b8..ef518c1f1d 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -316,7 +316,6 @@ config ARM_V7M # currently v7M must be included in a TCG build due to translate.c default y if TCG && (ARM || AARCH64) select PTIMER -select ARM_COMPATIBLE_SEMIHOSTING config ALLWINNER_A10 bool diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 3f3394a22b..39f05b6420 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -4,3 +4,10 @@ config ARM config AARCH64 bool select ARM + +# This config exists just so we can make SEMIHOSTING default when TCG +# is selected without also changing it for other architectures. +config ARM_SEMIHOSTING +bool +default y if TCG && ARM +select ARM_COMPATIBLE_SEMIHOSTING -- 2.35.3
[PATCH v6 27/29] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
Move all the CONFIG_FOO=y from default.mak into "default y if TCG" statements in Kconfig. That way they won't be selected when CONFIG_TCG=n. I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to keep the two default.mak files not empty and keep aarch64-default.mak including arm-default.mak. That way we don't surprise anyone that's used to altering these files. With this change we can start building with --disable-tcg. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- configs/devices/aarch64-softmmu/default.mak | 4 -- configs/devices/arm-softmmu/default.mak | 37 -- hw/arm/Kconfig | 42 - 3 files changed, 41 insertions(+), 42 deletions(-) diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak index cf43ac8da1..70e05a197d 100644 --- a/configs/devices/aarch64-softmmu/default.mak +++ b/configs/devices/aarch64-softmmu/default.mak @@ -2,7 +2,3 @@ # We support all the 32 bit boards so need all their config include ../arm-softmmu/default.mak - -CONFIG_XLNX_ZYNQMP_ARM=y -CONFIG_XLNX_VERSAL=y -CONFIG_SBSA_REF=y diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak index cb3e5aea65..647fbce88d 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -4,40 +4,3 @@ # CONFIG_TEST_DEVICES=n CONFIG_ARM_VIRT=y -CONFIG_CUBIEBOARD=y -CONFIG_EXYNOS4=y -CONFIG_HIGHBANK=y -CONFIG_INTEGRATOR=y -CONFIG_FSL_IMX31=y -CONFIG_MUSICPAL=y -CONFIG_MUSCA=y -CONFIG_CHEETAH=y -CONFIG_SX1=y -CONFIG_NSERIES=y -CONFIG_STELLARIS=y -CONFIG_STM32VLDISCOVERY=y -CONFIG_REALVIEW=y -CONFIG_VERSATILE=y -CONFIG_VEXPRESS=y -CONFIG_ZYNQ=y -CONFIG_MAINSTONE=y -CONFIG_GUMSTIX=y -CONFIG_SPITZ=y -CONFIG_TOSA=y -CONFIG_Z2=y -CONFIG_NPCM7XX=y -CONFIG_COLLIE=y -CONFIG_ASPEED_SOC=y -CONFIG_NETDUINO2=y -CONFIG_NETDUINOPLUS2=y -CONFIG_OLIMEX_STM32_H405=y -CONFIG_MPS2=y -CONFIG_RASPI=y -CONFIG_DIGIC=y -CONFIG_SABRELITE=y -CONFIG_EMCRAFT_SF2=y -CONFIG_MICROBIT=y -CONFIG_FSL_IMX25=y -CONFIG_FSL_IMX7=y -CONFIG_FSL_IMX6UL=y -CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ef518c1f1d..a25046848a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -34,20 +34,24 @@ config ARM_VIRT config CHEETAH bool +default y if TCG && ARM select OMAP select TSC210X config CUBIEBOARD bool +default y if TCG && ARM select ALLWINNER_A10 config DIGIC bool +default y if TCG && ARM select PTIMER select PFLASH_CFI02 config EXYNOS4 bool +default y if TCG && ARM imply I2C_DEVICES select A9MPCORE select I2C @@ -60,6 +64,7 @@ config EXYNOS4 config HIGHBANK bool +default y if TCG && ARM select A9MPCORE select A15MPCORE select AHCI @@ -74,6 +79,7 @@ config HIGHBANK config INTEGRATOR bool +default y if TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -86,12 +92,14 @@ config INTEGRATOR config MAINSTONE bool +default y if TCG && ARM select PXA2XX select PFLASH_CFI01 select SMC91C111 config MUSCA bool +default y if TCG && ARM select ARMSSE select PL011 select PL031 @@ -103,6 +111,7 @@ config MARVELL_88W8618 config MUSICPAL bool +default y if TCG && ARM select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -113,18 +122,22 @@ config MUSICPAL config NETDUINO2 bool +default y if TCG && ARM select STM32F205_SOC config NETDUINOPLUS2 bool +default y if TCG && ARM select STM32F405_SOC config OLIMEX_STM32_H405 bool +default y if TCG && ARM select STM32F405_SOC config NSERIES bool +default y if TCG && ARM select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -157,12 +170,14 @@ config PXA2XX config GUMSTIX bool +default y if TCG && ARM select PFLASH_CFI01 select SMC91C111 select PXA2XX config TOSA bool +default y if TCG && ARM select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -170,6 +185,7 @@ config TOSA config SPITZ bool +default y if TCG && ARM select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -182,6 +198,7 @@ config SPITZ config Z2 bool +default y if TCG && ARM select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -189,6 +206,7 @@ config Z2 config REALVIEW bool +default y if TCG && ARM imply PCI_DEVICES imply PCI_TESTDEV imply I2C_DEVICES @@ -217,6 +235,7 @@ config REALVIEW config SBSA_REF bool +default y if TCG && AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 @@ -232,11 +251,13 @@ config SBSA_REF config SABRELITE bool +default y if TCG &&
[PATCH v6 23/29] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
These tests set -accel tcg, so restrict them to when TCG is present.
Signed-off-by: Fabiano Rosas
Acked-by: Richard Henderson
Reviewed-by: Thomas Huth
---
Removed unneeded hunk restricting dependencies
Use config_all instead of config_devices_all to check for TCG
---
tests/qtest/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 222e1892fb..29a4efb4c2 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -208,8 +208,8 @@ qtests_arm = \
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test
unconditional
qtests_aarch64 = \
(cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +
\
- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
['tpm-tis-device-test'] : []) +\
- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
['tpm-tis-device-swtpm-test'] : []) + \
+ (config_all.has_key('CONFIG_TCG') and
config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?\
+['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +
\
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test',
'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
['arm-cpu-features',
--
2.35.3
[PATCH v6 25/29] tests/avocado: add machine:none tag to version.py
This test currently fails when run on a host for which the QEMU target
has no default machine set:
ERROR| Output: qemu-system-aarch64: No machine specified, and there is
no default
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
---
tests/avocado/version.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/avocado/version.py b/tests/avocado/version.py
index ded7f039c1..dd775955eb 100644
--- a/tests/avocado/version.py
+++ b/tests/avocado/version.py
@@ -15,6 +15,7 @@
class Version(QemuSystemTest):
"""
:avocado: tags=quick
+:avocado: tags=machine:none
"""
def test_qmp_human_info_version(self):
self.vm.add_args('-nodefaults')
--
2.35.3
[PATCH v6 10/29] target/arm: Move psci.c into the tcg directory
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Tested-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 1 -
target/arm/tcg/meson.build | 4
target/arm/{ => tcg}/psci.c | 0
3 files changed, 4 insertions(+), 1 deletion(-)
rename target/arm/{ => tcg}/psci.c (100%)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 3e2f403005..a5191b57e1 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -22,7 +22,6 @@ arm_softmmu_ss.add(files(
'arm-powerctl.c',
'machine.c',
'monitor.c',
- 'psci.c',
'ptw.c',
))
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 1f27ba1272..fa8a9eab93 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -43,3 +43,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'sme_helper.c',
'sve_helper.c',
))
+
+arm_softmmu_ss.add(files(
+ 'psci.c',
+))
diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c
similarity index 100%
rename from target/arm/psci.c
rename to target/arm/tcg/psci.c
--
2.35.3
[PATCH v6 29/29] tests/qtest: Fix tests when no KVM or TCG are present
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Fix tests that crash or hang in the above scenario. Do not include any
test cases if TCG and KVM are missing.
Signed-off-by: Fabiano Rosas
---
This currently affects Arm, but will also affect x86 after the xenpvh
series gets merged. This patch fixes both scenarios.
---
tests/qtest/bios-tables-test.c | 4
tests/qtest/boot-serial-test.c | 10 ++
tests/qtest/migration-test.c | 5 +
tests/qtest/pxe-test.c | 6 ++
tests/qtest/vmgenid-test.c | 6 ++
5 files changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d29a4e47af..f6c2a010d2 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2114,6 +2114,10 @@ int main(int argc, char *argv[])
char *v_env = getenv("V");
int ret;
+if (!has_tcg && !has_kvm) {
+return 0;
+}
+
if (v_env) {
verbosity_level = atoi(v_env);
}
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index 3aef3a97a9..45490f5931 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -17,6 +17,9 @@
#include "libqtest.h"
#include "libqos/libqos-spapr.h"
+static bool has_tcg;
+static bool has_kvm;
+
static const uint8_t bios_avr[] = {
0x88, 0xe0, /* ldi r24, 0x08 */
0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
@@ -285,6 +288,13 @@ int main(int argc, char *argv[])
const char *arch = qtest_get_arch();
int i;
+has_tcg = qtest_has_accel("tcg");
+has_kvm = qtest_has_accel("kvm");
+
+if (!has_tcg && !has_kvm) {
+return 0;
+}
+
g_test_init(&argc, &argv, NULL);
for (i = 0; tests[i].arch != NULL; i++) {
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 109bc8e7b1..a6e3ca9f7d 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -2460,11 +2460,16 @@ static bool kvm_dirty_ring_supported(void)
int main(int argc, char **argv)
{
const bool has_kvm = qtest_has_accel("kvm");
+const bool has_tcg = qtest_has_accel("tcg");
const bool has_uffd = ufd_version_check();
const char *arch = qtest_get_arch();
g_autoptr(GError) err = NULL;
int ret;
+if (!has_tcg && !has_kvm) {
+return 0;
+}
+
g_test_init(&argc, &argv, NULL);
/*
diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
index 62b6eef464..05575f7687 100644
--- a/tests/qtest/pxe-test.c
+++ b/tests/qtest/pxe-test.c
@@ -130,6 +130,12 @@ int main(int argc, char *argv[])
{
int ret;
const char *arch = qtest_get_arch();
+bool has_tcg = qtest_has_accel("tcg");
+bool has_kvm = qtest_has_accel("kvm");
+
+if (!has_tcg && !has_kvm) {
+return 0;
+}
ret = boot_sector_init(disk);
if(ret)
diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c
index efba76e716..8045d3d706 100644
--- a/tests/qtest/vmgenid-test.c
+++ b/tests/qtest/vmgenid-test.c
@@ -164,6 +164,12 @@ static void vmgenid_query_monitor_test(void)
int main(int argc, char **argv)
{
int ret;
+bool has_tcg = qtest_has_accel("tcg");
+bool has_kvm = qtest_has_accel("kvm");
+
+if (!has_tcg && !has_kvm) {
+return 0;
+}
ret = boot_sector_init(disk);
if (ret) {
--
2.35.3
[PATCH v6 28/29] gitlab-ci: Check building KVM-only aarch64 target
From: Philippe Mathieu-Daudé Add a manual new job to cross-build the aarch64 target with only the KVM accelerator enabled (in particular, no TCG). Re-enable running the similar job on the project Aarch64 custom runner. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Fabiano Rosas Reviewed-by: Thomas Huth --- .gitlab-ci.d/crossbuilds.yml | 11 +++ .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml | 4 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 74d6259b90..80269a3656 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -212,3 +212,14 @@ cross-arm64-xen-only: IMAGE: debian-arm64-cross ACCEL: xen EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-kvm + +# Similar job is run by qemu-project's custom runner by default +cross-arm64-kvm-only: + extends: .cross_accel_build_job + needs: +job: arm64-debian-cross-container + variables: +QEMU_JOB_OPTIONAL: 1 +IMAGE: debian-arm64-cross +ACCEL: kvm +EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-xen --without-default-devices diff --git a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml index 8ba85be440..770e596242 100644 --- a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml +++ b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml @@ -115,11 +115,7 @@ ubuntu-22.04-aarch64-notcg: - aarch64 rules: - if: '$CI_PROJECT_NAMESPACE == "qemu-project" && $CI_COMMIT_BRANCH =~ /^staging/' - when: manual - allow_failure: true - if: "$AARCH64_RUNNER_AVAILABLE" - when: manual - allow_failure: true script: - mkdir build - cd build -- 2.35.3
[PATCH v6 22/29] tests/qtest: arm-cpu-features: Match tests to required accelerators
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
---
tests/qtest/arm-cpu-features.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4ff2014bea..1555b0bab8 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -21,7 +21,7 @@
#define SVE_MAX_VQ 16
#define MACHINE "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
" 'arguments': { 'type': 'full', "
#define QUERY_TAIL "}}"
@@ -613,31 +613,39 @@ int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
-qtest_add_data_func("/arm/query-cpu-model-expansion",
-NULL, test_query_cpu_model_expansion);
+if (qtest_has_accel("tcg")) {
+qtest_add_data_func("/arm/query-cpu-model-expansion",
+NULL, test_query_cpu_model_expansion);
+}
+
+if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+goto out;
+}
/*
* For now we only run KVM specific tests with AArch64 QEMU in
* order avoid attempting to run an AArch32 QEMU with KVM on
* AArch64 hosts. That won't work and isn't easy to detect.
*/
-if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+if (qtest_has_accel("kvm")) {
/*
* This tests target the 'host' CPU type, so register it only if
* KVM is available.
*/
qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
NULL, test_query_cpu_model_expansion_kvm);
+
+qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+NULL, sve_tests_sve_off_kvm);
}
-if (g_str_equal(qtest_get_arch(), "aarch64")) {
+if (qtest_has_accel("tcg")) {
qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
NULL, sve_tests_sve_max_vq_8);
qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
NULL, sve_tests_sve_off);
-qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
-NULL, sve_tests_sve_off_kvm);
}
+out:
return g_test_run();
}
--
2.35.3
[PATCH v6 09/29] target/arm: move helpers to tcg/
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 15 ++-
target/arm/tcg-stubs.c | 23 +++
target/arm/{ => tcg}/crypto_helper.c | 0
target/arm/{ => tcg}/helper-a64.c| 0
target/arm/{ => tcg}/iwmmxt_helper.c | 0
target/arm/{ => tcg}/m_helper.c | 0
target/arm/tcg/meson.build | 13 +
target/arm/{ => tcg}/mte_helper.c| 0
target/arm/{ => tcg}/mve_helper.c| 0
target/arm/{ => tcg}/neon_helper.c | 0
target/arm/{ => tcg}/op_helper.c | 0
target/arm/{ => tcg}/pauth_helper.c | 0
target/arm/{ => tcg}/sme_helper.c| 0
target/arm/{ => tcg}/sve_helper.c| 0
target/arm/{ => tcg}/tlb_helper.c| 0
target/arm/{ => tcg}/vec_helper.c| 0
target/arm/{ => tcg}/vec_internal.h | 0
17 files changed, 38 insertions(+), 13 deletions(-)
create mode 100644 target/arm/tcg-stubs.c
rename target/arm/{ => tcg}/crypto_helper.c (100%)
rename target/arm/{ => tcg}/helper-a64.c (100%)
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
rename target/arm/{ => tcg}/m_helper.c (100%)
rename target/arm/{ => tcg}/mte_helper.c (100%)
rename target/arm/{ => tcg}/mve_helper.c (100%)
rename target/arm/{ => tcg}/neon_helper.c (100%)
rename target/arm/{ => tcg}/op_helper.c (100%)
rename target/arm/{ => tcg}/pauth_helper.c (100%)
rename target/arm/{ => tcg}/sme_helper.c (100%)
rename target/arm/{ => tcg}/sve_helper.c (100%)
rename target/arm/{ => tcg}/tlb_helper.c (100%)
rename target/arm/{ => tcg}/vec_helper.c (100%)
rename target/arm/{ => tcg}/vec_internal.h (100%)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index b2904b676b..3e2f403005 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,17 +1,9 @@
arm_ss = ss.source_set()
arm_ss.add(files(
'cpu.c',
- 'crypto_helper.c',
'debug_helper.c',
'gdbstub.c',
'helper.c',
- 'iwmmxt_helper.c',
- 'm_helper.c',
- 'mve_helper.c',
- 'neon_helper.c',
- 'op_helper.c',
- 'tlb_helper.c',
- 'vec_helper.c',
'vfp_helper.c',
'cpu_tcg.c',
))
@@ -22,11 +14,6 @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c',
'kvm64.c'), if_false: fil
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'cpu64.c',
'gdbstub64.c',
- 'helper-a64.c',
- 'mte_helper.c',
- 'pauth_helper.c',
- 'sve_helper.c',
- 'sme_helper.c',
))
arm_softmmu_ss = ss.source_set()
@@ -43,6 +30,8 @@ subdir('hvf')
if 'CONFIG_TCG' in config_all
subdir('tcg')
+else
+arm_ss.add(files('tcg-stubs.c'))
endif
target_arch += {'arm': arm_ss}
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
new file mode 100644
index 00..1a7ddb3664
--- /dev/null
+++ b/target/arm/tcg-stubs.c
@@ -0,0 +1,23 @@
+/*
+ * QEMU ARM stubs for some TCG helper functions
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+g_assert_not_reached();
+}
+
+void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
+uint32_t target_el, uintptr_t ra)
+{
+g_assert_not_reached();
+}
diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c
similarity index 100%
rename from target/arm/crypto_helper.c
rename to target/arm/tcg/crypto_helper.c
diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c
similarity index 100%
rename from target/arm/helper-a64.c
rename to target/arm/tcg/helper-a64.c
diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c
similarity index 100%
rename from target/arm/iwmmxt_helper.c
rename to target/arm/tcg/iwmmxt_helper.c
diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c
similarity index 100%
rename from target/arm/m_helper.c
rename to target/arm/tcg/m_helper.c
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 044561bd4d..1f27ba1272 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -23,10 +23,23 @@ arm_ss.add(files(
'translate-mve.c',
'translate-neon.c',
'translate-vfp.c',
+ 'crypto_helper.c',
+ 'iwmmxt_helper.c',
+ 'm_helper.c',
+ 'mve_helper.c',
+ 'neon_helper.c',
+ 'op_helper.c',
+ 'tlb_helper.c',
+ 'vec_helper.c',
))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'translate-a64.c',
'translate-sve.c',
'translate-sme.c',
+ 'helper-a64.c',
+ 'mte_helper.c',
+ 'pauth_helper.c',
+ 'sme_helper.c',
+ 'sve_helper.c',
))
diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c
similarity index 100%
rename from target/arm/mte_helper.c
rename to target/arm/tcg/mte_helper.c
diff --git a/target/arm/mve_helper.c b
[PATCH v6 11/29] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
hw/arm/boot.c | 6 +-
hw/intc/armv7m_nvic.c | 20 +---
target/arm/arm-powerctl.c | 7 +--
target/arm/cpu.c | 3 ++-
target/arm/helper.c | 18 +-
target/arm/machine.c | 5 -
6 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3d7d11f782..1e021c4a34 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -15,6 +15,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/linux-boot-if.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "hw/boards.h"
@@ -827,7 +828,10 @@ static void do_cpu_reset(void *opaque)
info->secondary_cpu_reset_hook(cpu, info);
}
}
-arm_rebuild_hflags(env);
+
+if (tcg_enabled()) {
+arm_rebuild_hflags(env);
+}
}
}
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1f7763964c..74ac8f610c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -18,6 +18,7 @@
#include "hw/intc/armv7m_nvic.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "sysemu/tcg.h"
#include "sysemu/runstate.h"
#include "target/arm/cpu.h"
#include "exec/exec-all.h"
@@ -2466,8 +2467,10 @@ static MemTxResult nvic_sysreg_write(void *opaque,
hwaddr addr,
/* This is UNPREDICTABLE; treat as RAZ/WI */
exit_ok:
-/* Ensure any changes made are reflected in the cached hflags. */
-arm_rebuild_hflags(&s->cpu->env);
+if (tcg_enabled()) {
+/* Ensure any changes made are reflected in the cached hflags. */
+arm_rebuild_hflags(&s->cpu->env);
+}
return MEMTX_OK;
}
@@ -2648,11 +2651,14 @@ static void armv7m_nvic_reset(DeviceState *dev)
}
}
-/*
- * We updated state that affects the CPU's MMUidx and thus its hflags;
- * and we can't guarantee that we run before the CPU reset function.
- */
-arm_rebuild_hflags(&s->cpu->env);
+if (tcg_enabled()) {
+/*
+ * We updated state that affects the CPU's MMUidx and thus its
+ * hflags; and we can't guarantee that we run before the CPU
+ * reset function.
+ */
+arm_rebuild_hflags(&s->cpu->env);
+}
}
static void nvic_systick_trigger(void *opaque, int n, int level)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index b75f813b40..326a03153d 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -15,6 +15,7 @@
#include "arm-powerctl.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
+#include "sysemu/tcg.h"
#ifndef DEBUG_ARM_POWERCTL
#define DEBUG_ARM_POWERCTL 0
@@ -127,8 +128,10 @@ static void arm_set_cpu_on_async_work(CPUState
*target_cpu_state,
target_cpu->env.regs[0] = info->context_id;
}
-/* CP15 update requires rebuilding hflags */
-arm_rebuild_hflags(&target_cpu->env);
+if (tcg_enabled()) {
+/* CP15 update requires rebuilding hflags */
+arm_rebuild_hflags(&target_cpu->env);
+}
/* Start the new CPU at the requested address */
cpu_set_pc(target_cpu_state, info->entry);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d7ceb626f0..ce1a425e10 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -539,8 +539,9 @@ static void arm_cpu_reset_hold(Object *obj)
if (tcg_enabled()) {
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+
+arm_rebuild_hflags(env);
}
-arm_rebuild_hflags(env);
}
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bd704396e0..2c4336bab6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5173,7 +5173,7 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu));
-if (ri->type & ARM_CP_SUPPRESS_TB_END) {
+if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
/*
* Normally we would always end the TB on an SCTLR write; see the
* comment in ARMCPRegInfo sctlr initialization below for why Xscale
@@ -6841,7 +6841,9 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,
uint64_t mask)
memset(env->zarray, 0, sizeof(env->zarray));
}
-arm_rebuild_hflags(env);
+if (tcg_enabled()) {
+arm_rebuild_hflags(env);
+}
}
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -9878,7 +9880,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
}
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
-if (rebuild_hflags) {
+if (tcg_enabled() && rebuild_hfla
[PATCH v6 15/29] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
This struct has no dependencies on TCG code and it is being used in
target/arm/ptw.c to simplify the passing around of page table walk
results. Those routines can be reached by KVM code via the gdbstub
breakpoint code, so take the structure out of CONFIG_TCG to make it
visible when building with --disable-tcg.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
include/exec/cpu-defs.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 21309cf567..d5a4f30717 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -135,6 +135,10 @@ typedef struct CPUTLBEntry {
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
+
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+
+#if !defined(CONFIG_USER_ONLY)
/*
* The full TLB entry, which is not accessed by generated TCG code,
* so the layout is not as critical as that of CPUTLBEntry. This is
@@ -176,7 +180,9 @@ typedef struct CPUTLBEntryFull {
TARGET_PAGE_ENTRY_EXTRA
#endif
} CPUTLBEntryFull;
+#endif /* !CONFIG_USER_ONLY */
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/*
* Data elements that are per MMU mode, minus the bits accessed by
* the TCG fast path.
--
2.35.3
[PATCH v6 05/29] target/arm: Move cpregs code out of cpu.h
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.
Code moved verbatim.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm/cpregs.h | 98 +
target/arm/cpu.h| 91 -
2 files changed, 98 insertions(+), 91 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index efcf9181b9..1ee64e99de 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -120,6 +120,104 @@ enum {
ARM_CP_SME = 1 << 19,
};
+/*
+ * Interface for defining coprocessor registers.
+ * Registers are defined in tables of arm_cp_reginfo structs
+ * which are passed to define_arm_cp_regs().
+ */
+
+/*
+ * When looking up a coprocessor register we look for it
+ * via an integer which encodes all of:
+ * coprocessor number
+ * Crn, Crm, opc1, opc2 fields
+ * 32 or 64 bit register (ie is it accessed via MRC/MCR
+ *or via MRRC/MCRR?)
+ * non-secure/secure bank (AArch32 only)
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
+ * (In this case crn and opc2 should be zero.)
+ * For AArch64, there is no 32/64 bit size distinction;
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
+ * to be easy to convert to and from the KVM encodings, and also
+ * so that the hashtable can contain both AArch32 and AArch64
+ * registers (to allow for interprocessing where we might run
+ * 32 bit code on a 64 bit core).
+ */
+/*
+ * This bit is private to our hashtable cpreg; in KVM register
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
+ * in the upper bits of the 64 bit ID.
+ */
+#define CP_REG_AA64_SHIFT 28
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
+
+/*
+ * To enable banking of coprocessor registers depending on ns-bit we
+ * add a bit to distinguish between secure and non-secure cpregs in the
+ * hashtable.
+ */
+#define CP_REG_NS_SHIFT 29
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
+((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
+ ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
+(CP_REG_AA64_MASK | \
+ ((cp) << CP_REG_ARM_COPROC_SHIFT) |\
+ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+/*
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
+ * version used as a key for the coprocessor register hashtable
+ */
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
+{
+uint32_t cpregid = kvmid;
+if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
+cpregid |= CP_REG_AA64_MASK;
+} else {
+if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
+cpregid |= (1 << 15);
+}
+
+/*
+ * KVM is always non-secure so add the NS flag on AArch32 register
+ * entries.
+ */
+ cpregid |= 1 << CP_REG_NS_SHIFT;
+}
+return cpregid;
+}
+
+/*
+ * Convert a truncated 32 bit hashtable key into the full
+ * 64 bit KVM register ID.
+ */
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+{
+uint64_t kvmid;
+
+if (cpregid & CP_REG_AA64_MASK) {
+kvmid = cpregid & ~CP_REG_AA64_MASK;
+kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
+} else {
+kvmid = cpregid & ~(1 << 15);
+if (cpregid & (1 << 15)) {
+kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
+} else {
+kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
+}
+}
+return kvmid;
+}
+
/*
* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7bc97fece9..9d4573c53c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2680,97 +2680,6 @@ static inline bool armv7m_nvic_neg_prio_requested(void
*opaque, bool secure)
}
#endif
-/* Interface for defining coprocessor registers.
- * Registers are defined in tables of arm_cp_reginfo structs
- * which are passed to define_arm_cp_regs().
- */
-
-/* When looking up a coprocessor register we look for it
- * via an integer which encodes all of:
- * coprocessor number
- * Crn, Crm, opc1, opc2 fields
- * 32 or 64 bit register (ie is it accessed via MRC/MCR
- *or via MRRC/MCRR?)
- * non-secure/secure bank (AArch32 only)
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
- * (In this case crn and opc2 should
[PATCH v6 01/29] target/arm: rename handle_semihosting to tcg_handle_semihosting
From: Claudio Fontana
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c62ed05c12..190be1a64d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11006,7 +11006,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* trapped to the hypervisor in KVM.
*/
#ifdef CONFIG_TCG
-static void handle_semihosting(CPUState *cs)
+static void tcg_handle_semihosting(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -11068,7 +11068,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
*/
#ifdef CONFIG_TCG
if (cs->exception_index == EXCP_SEMIHOST) {
-handle_semihosting(cs);
+tcg_handle_semihosting(cs);
return;
}
#endif
--
2.35.3
[PATCH v6 00/29] target/arm: Allow CONFIG_TCG=n builds
Addressed Peter's comments and dropped the cpregs change which is not
related to fixing the --disable-tcg build. This unblocks the xenpvh
series and I can tackle the regs split without holding up the build
work.
changes:
- debug regs: I left debug_helper.c out of the movement to tcg/ along
with the other files that still are somewhat coupled to tcg. We
don't need to do this right now, but I propose that after the cpregs
split we define something like:
target/arm/
cpregs.c - generic code and uncategorized registers
debug_regs.c - debug registers
pmu_regs.c - PMU registers
gtimer_regs.c - Generic Timer registers
*_regs.c -
tcg/helper.c - generic helpers
tcg/debug_helper.c - TCG helpers
tcg/*_helper.c -
- cortex regs: these were _not_ related to the 32-bit cpus in
cpu_tcg.c, they were related to 64-bit cpus in cpu64.c and only used
to borrow some registers for the 32-bit "max" cpu. I moved them into
cpu64.c.
- avocado migration test: rewrote it in a more generic fashion and
stopped using defaults for the major (by some definition of major)
architectures (let me know if I missed any).
- new avocado patch that fixes version.py for aarch64. This was lost
in the ml.
- new patch to fix the tests that break due to Xen pulling in
non-native QEMU targets
Thanks!
v5 resend:
https://lore.kernel.org/r/20230213202927.28992-1-faro...@suse.de
v5:
https://lore.kernel.org/r/20230120184825.31626-1-faro...@suse.de
This series makes the necessary changes to allow the use of
--disable-tcg for arm.
- Used "max" as the default CPU for KVM-only builds. This allows me to
drop all the clunky qtest changes and it keeps disabling TCG
separate from changing cpu defaults.
I'm neutral towards removing the defaults for arm. We can do that in a
separate series. It would be nice to make the TCG default equal to the
non-TCG one. Otherwise we're bound to get reports that "this command
line used to work" if users switch from: 'CONFIG_TCG=n -accel kvm' to
'CONFIG_TCG=y -accel kvm' (the latter would try to use the cortex-a15
as default).
- Move the ifdef around valid_cpus into the patches that move the
respective cpus. Patches 1 & 2.
v5 was based on "target/arm: CONFIG_TCG=n part 1":
https://lore.kernel.org/r/20230118193518.26433-1-faro...@suse.de
v4:
https://lore.kernel.org/r/20230119135424.5417-1-faro...@suse.de
v3:
https://lore.kernel.org/r/20230113140419.4013-1-faro...@suse.de
v2:
https://lore.kernel.org/r/20230109224232.11661-1-faro...@suse.de
v1:
https://lore.kernel.org/r/20230104215835.24692-1-faro...@suse.de
Claudio Fontana (6):
target/arm: rename handle_semihosting to tcg_handle_semihosting
target/arm: wrap psci call with tcg_enabled
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
target/arm: move helpers to tcg/
target/arm: Move psci.c into the tcg directory
target/arm: move cpu_tcg to tcg/cpu32.c
Fabiano Rosas (22):
target/arm: Move PC alignment check
target/arm: Move cpregs code out of cpu.h
target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
target/arm: Wrap TCG-only code in debug_helper.c
target/arm: move translate modules to tcg/
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
target/arm: Move hflags code into the tcg directory
target/arm: Move regime_using_lpae_format into internal.h
target/arm: Don't access TCG code when debugging with KVM
cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
target/arm: Move cortex sysregs into cpu64.c
tests/avocado: Skip tests that require a missing accelerator
tests/avocado: Tag TCG tests with accel:tcg
target/arm: Move 64-bit TCG CPUs into tcg/
target/arm: Use "max" as default cpu for the virt machine with KVM
tests/qtest: arm-cpu-features: Match tests to required accelerators
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
target/avocado: Pass parameters to migration test
tests/avocado: add machine:none tag to version.py
arm/Kconfig: Always select SEMIHOSTING when TCG is present
arm/Kconfig: Do not build TCG-only boards on a KVM-only build
tests/qtest: Fix tests when no KVM or TCG are present
Philippe Mathieu-Daudé (1):
gitlab-ci: Check building KVM-only aarch64 target
.gitlab-ci.d/crossbuilds.yml | 11 +
.../custom-runners/ubuntu-22.04-aarch64.yml | 4 -
MAINTAINERS | 1 +
configs/devices/aarch64-softmmu/default.mak | 4 -
configs/devices/arm-softmmu/default.mak | 39 -
hw/arm/Kconfig| 43 +-
hw/arm/boot.c | 6 +-
hw/arm/virt.c | 10 +-
hw/intc/armv7m_nvic.c | 20 +-
include/exec/cpu-defs.h | 6 +
target/arm/Kconfig| 7 +
target/arm/arm-powerctl.c | 7 +-
target/arm/cpregs.h | 104 +++
target/ar
[PATCH v6 20/29] target/arm: move cpu_tcg to tcg/cpu32.c
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
hw/arm/virt.c | 2 +-
target/arm/meson.build| 1 -
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++--
target/arm/tcg/cpu64.c| 2 +-
target/arm/tcg/meson.build| 1 +
tests/qtest/arm-cpu-features.c| 12 +---
6 files changed, 15 insertions(+), 16 deletions(-)
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 20a18d0ba1..fbeeed115d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -204,9 +204,9 @@ static const int a15irqmap[] = {
};
static const char *valid_cpus[] = {
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
diff --git a/target/arm/meson.build b/target/arm/meson.build
index b0bc8a3cea..f03d242ba8 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -6,7 +6,6 @@ arm_ss.add(files(
'gdbstub.c',
'helper.c',
'vfp_helper.c',
- 'cpu_tcg.c',
))
arm_ss.add(zlib)
diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c
similarity index 99%
rename from target/arm/cpu_tcg.c
rename to target/arm/tcg/cpu32.c
index 64d5a785c1..caa5252ad9 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/tcg/cpu32.c
@@ -1,5 +1,5 @@
/*
- * QEMU ARM TCG CPUs.
+ * QEMU ARM TCG-only CPUs.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@@ -10,9 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
@@ -93,7 +91,7 @@ void aa32_max_features(ARMCPU *cpu)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if !defined(CONFIG_USER_ONLY)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -117,7 +115,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
}
return ret;
}
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -1013,7 +1011,6 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x0078;
}
-#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
@@ -1034,7 +1031,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.debug_check_breakpoint = arm_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
-#endif /* CONFIG_TCG */
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
@@ -1042,10 +1038,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void
*data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifdef CONFIG_TCG
cc->tcg_ops = &arm_v7m_tcg_ops;
-#endif /* CONFIG_TCG */
-
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 89d54ec0f6..d0feb3eb52 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -457,7 +457,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
/*
* -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
* this only needs to handle 64 bits.
*/
void aarch64_max_tcg_initfn(Object *obj)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 128f782816..4d99f6dacb 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -18,6 +18,7 @@ gen = [
arm_ss.add(gen)
arm_ss.add(files(
+ 'cpu32.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 8691802950..4ff2014bea 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void
*data)
QDict *resp;
char *error;
-assert_error(qts, "cortex-a15",
-"We cannot guarantee the CPU type 'cortex-a15' works "
-"with KVM on this host", NULL);
+if (qtest_has_accel("tcg")) {
+assert_error(qts, "cortex-a15",
+ "We cannot guarantee the CPU type 'cortex-a15' works "
+ "with KVM on this host", NULL);
+} else {
+assert_er
[PATCH v6 16/29] target/arm: Move cortex sysregs into cpu64.c
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into cpu64.c along with the cortex cpus
definition.
This code defines registers for 64-bit cpus but it is shared by the 32
bit "max" CPU, so use an ifdef instead of meson to keep the rest of
the file 64-bit only.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.h| 6
target/arm/cpu64.c | 63 ++
target/arm/cpu_tcg.c | 59 ---
target/arm/internals.h | 6
target/arm/meson.build | 2 +-
5 files changed, 70 insertions(+), 66 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1ee64e99de..b04d344a9f 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1071,4 +1071,10 @@ static inline bool arm_cpreg_in_idspace(const
ARMCPRegInfo *ri)
ri->crn, ri->crm);
}
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..ab2818dc15 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -29,6 +29,68 @@
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
#include "internals.h"
+#include "cpregs.h"
+
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ARMCPU *cpu = env_archcpu(env);
+
+/* Number of cores is in [25:24]; otherwise we RAZ */
+return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+{ .name = "L2CTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "L2ECTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "CPUACTLR",
+ .cp = 15, .opc1 = 0, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "CPUECTLR",
+ .cp = 15, .opc1 = 1, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "CPUMERRSR",
+ .cp = 15, .opc1 = 2, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = "L2MERRSR",
+ .cp = 15, .opc1 = 3, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_AARCH64
static void aarch64_a35_initfn(Object *obj)
{
@@ -1425,3 +1487,4 @@ static void aarch64_cpu_register_types(void)
}
type_init(aarch64_cpu_register_types)
+#endif /* TARGET_AARCH64 */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ccde5080eb..64d5a785c1 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -90,65 +90,6 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_dfr0 = t;
}
-#ifndef CONFIG_USER_ONLY
-static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-ARMCPU *cpu = env_archcpu(env);
-
-/* Number of cores is in [25:24]; otherwise we RAZ */
-return (cpu->core_count - 1) << 24;
-}
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = P
[PATCH v6 07/29] target/arm: Wrap TCG-only code in debug_helper.c
The next few patches will move helpers under CONFIG_TCG. We'd prefer
to keep the debug helpers and debug registers close together, so
rearrange the file a bit to be able to wrap the helpers with a TCG
ifdef.
Signed-off-by: Fabiano Rosas
---
target/arm/debug_helper.c | 476 +++---
1 file changed, 239 insertions(+), 237 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 3325eb9d7d..dfc8b2a1a5 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -12,8 +12,9 @@
#include "cpregs.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "sysemu/tcg.h"
-
+#ifdef CONFIG_TCG
/* Return the Exception Level targeted by debug exceptions. */
static int arm_debug_target_el(CPUARMState *env)
{
@@ -536,6 +537,243 @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t
syndrome)
raise_exception_debug(env, EXCP_UDEF, syndrome);
}
+void hw_watchpoint_update(ARMCPU *cpu, int n)
+{
+CPUARMState *env = &cpu->env;
+vaddr len = 0;
+vaddr wvr = env->cp15.dbgwvr[n];
+uint64_t wcr = env->cp15.dbgwcr[n];
+int mask;
+int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
+
+if (env->cpu_watchpoint[n]) {
+cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
+env->cpu_watchpoint[n] = NULL;
+}
+
+if (!FIELD_EX64(wcr, DBGWCR, E)) {
+/* E bit clear : watchpoint disabled */
+return;
+}
+
+switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
+case 0:
+/* LSC 00 is reserved and must behave as if the wp is disabled */
+return;
+case 1:
+flags |= BP_MEM_READ;
+break;
+case 2:
+flags |= BP_MEM_WRITE;
+break;
+case 3:
+flags |= BP_MEM_ACCESS;
+break;
+}
+
+/*
+ * Attempts to use both MASK and BAS fields simultaneously are
+ * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
+ * thus generating a watchpoint for every byte in the masked region.
+ */
+mask = FIELD_EX64(wcr, DBGWCR, MASK);
+if (mask == 1 || mask == 2) {
+/*
+ * Reserved values of MASK; we must act as if the mask value was
+ * some non-reserved value, or as if the watchpoint were disabled.
+ * We choose the latter.
+ */
+return;
+} else if (mask) {
+/* Watchpoint covers an aligned area up to 2GB in size */
+len = 1ULL << mask;
+/*
+ * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
+ * whether the watchpoint fires when the unmasked bits match; we opt
+ * to generate the exceptions.
+ */
+wvr &= ~(len - 1);
+} else {
+/* Watchpoint covers bytes defined by the byte address select bits */
+int bas = FIELD_EX64(wcr, DBGWCR, BAS);
+int basstart;
+
+if (extract64(wvr, 2, 1)) {
+/*
+ * Deprecated case of an only 4-aligned address. BAS[7:4] are
+ * ignored, and BAS[3:0] define which bytes to watch.
+ */
+bas &= 0xf;
+}
+
+if (bas == 0) {
+/* This must act as if the watchpoint is disabled */
+return;
+}
+
+/*
+ * The BAS bits are supposed to be programmed to indicate a contiguous
+ * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
+ * we fire for each byte in the word/doubleword addressed by the WVR.
+ * We choose to ignore any non-zero bits after the first range of 1s.
+ */
+basstart = ctz32(bas);
+len = cto32(bas >> basstart);
+wvr += basstart;
+}
+
+cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
+ &env->cpu_watchpoint[n]);
+}
+
+void hw_watchpoint_update_all(ARMCPU *cpu)
+{
+int i;
+CPUARMState *env = &cpu->env;
+
+/*
+ * Completely clear out existing QEMU watchpoints and our array, to
+ * avoid possible stale entries following migration load.
+ */
+cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
+memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
+
+for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
+hw_watchpoint_update(cpu, i);
+}
+}
+
+void hw_breakpoint_update(ARMCPU *cpu, int n)
+{
+CPUARMState *env = &cpu->env;
+uint64_t bvr = env->cp15.dbgbvr[n];
+uint64_t bcr = env->cp15.dbgbcr[n];
+vaddr addr;
+int bt;
+int flags = BP_CPU;
+
+if (env->cpu_breakpoint[n]) {
+cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
+env->cpu_breakpoint[n] = NULL;
+}
+
+if (!extract64(bcr, 0, 1)) {
+/* E bit clear : watchpoint disabled */
+return;
+}
+
+bt = extract64(bcr, 20, 4);
+
+switch (bt) {
+case 4: /* unlinked address mismatch (reserved if AArch64) */
+case 5: /* linked address mismatch (reserved if AArch64) */
+qemu_log_mask(L
[PATCH v6 08/29] target/arm: move translate modules to tcg/
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
target/arm/meson.build | 30 ---
target/arm/{ => tcg}/a32-uncond.decode | 0
target/arm/{ => tcg}/a32.decode | 0
target/arm/{ => tcg}/m-nocp.decode | 0
target/arm/tcg/meson.build | 32 +
target/arm/{ => tcg}/mve.decode | 0
target/arm/{ => tcg}/neon-dp.decode | 0
target/arm/{ => tcg}/neon-ls.decode | 0
target/arm/{ => tcg}/neon-shared.decode | 0
target/arm/{ => tcg}/sme-fa64.decode| 0
target/arm/{ => tcg}/sme.decode | 0
target/arm/{ => tcg}/sve.decode | 0
target/arm/{ => tcg}/t16.decode | 0
target/arm/{ => tcg}/t32.decode | 0
target/arm/{ => tcg}/translate-a64.c| 0
target/arm/{ => tcg}/translate-a64.h| 0
target/arm/{ => tcg}/translate-m-nocp.c | 0
target/arm/{ => tcg}/translate-mve.c| 0
target/arm/{ => tcg}/translate-neon.c | 0
target/arm/{ => tcg}/translate-sme.c| 0
target/arm/{ => tcg}/translate-sve.c| 0
target/arm/{ => tcg}/translate-vfp.c| 0
target/arm/{ => tcg}/translate.c| 0
target/arm/{ => tcg}/translate.h| 0
target/arm/{ => tcg}/vfp-uncond.decode | 0
target/arm/{ => tcg}/vfp.decode | 0
27 files changed, 37 insertions(+), 26 deletions(-)
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
rename target/arm/{ => tcg}/a32.decode (100%)
rename target/arm/{ => tcg}/m-nocp.decode (100%)
create mode 100644 target/arm/tcg/meson.build
rename target/arm/{ => tcg}/mve.decode (100%)
rename target/arm/{ => tcg}/neon-dp.decode (100%)
rename target/arm/{ => tcg}/neon-ls.decode (100%)
rename target/arm/{ => tcg}/neon-shared.decode (100%)
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
rename target/arm/{ => tcg}/sme.decode (100%)
rename target/arm/{ => tcg}/sve.decode (100%)
rename target/arm/{ => tcg}/t16.decode (100%)
rename target/arm/{ => tcg}/t32.decode (100%)
rename target/arm/{ => tcg}/translate-a64.c (100%)
rename target/arm/{ => tcg}/translate-a64.h (100%)
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
rename target/arm/{ => tcg}/translate-mve.c (100%)
rename target/arm/{ => tcg}/translate-neon.c (100%)
rename target/arm/{ => tcg}/translate-sme.c (100%)
rename target/arm/{ => tcg}/translate-sve.c (100%)
rename target/arm/{ => tcg}/translate-vfp.c (100%)
rename target/arm/{ => tcg}/translate.c (100%)
rename target/arm/{ => tcg}/translate.h (100%)
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
rename target/arm/{ => tcg}/vfp.decode (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd54c1f140..426f0922ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -161,6 +161,7 @@ M: Peter Maydell
L: qemu-...@nongnu.org
S: Maintained
F: target/arm/
+F: target/arm/tcg/
F: tests/tcg/arm/
F: tests/tcg/aarch64/
F: tests/qtest/arm-cpu-features.c
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 87e911b27f..b2904b676b 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,22 +1,4 @@
-gen = [
- decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
- decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
- decodetree.process('sme-fa64.decode', extra_args:
'--static-decode=disas_sme_fa64'),
- decodetree.process('neon-shared.decode', extra_args:
'--decode=disas_neon_shared'),
- decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
- decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
- decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
- decodetree.process('vfp-uncond.decode', extra_args:
'--decode=disas_vfp_uncond'),
- decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
- decodetree.process('mve.decode', extra_args: '--decode=disas_mve'),
- decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
- decodetree.process('a32-uncond.decode', extra_args:
'--static-decode=disas_a32_uncond'),
- decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
- decodetree.process('t16.decode', extra_args: ['-w', '16',
'--static-decode=disas_t16']),
-]
-
arm_ss = ss.source_set()
-arm_ss.add(gen)
arm_ss.add(files(
'cpu.c',
'crypto_helper.c',
@@ -29,11 +11,6 @@ arm_ss.add(files(
'neon_helper.c',
'op_helper.c',
'tlb_helper.c',
- 'translate.c',
- 'translate-m-nocp.c',
- 'translate-mve.c',
- 'translate-neon.c',
- 'translate-vfp.c',
'vec_helper.c',
'vfp_helper.c',
'cpu_tcg.c',
@@ -50,9 +27,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'pauth_helper.c',
'sve_helper.c',
'sme_helpe
[PATCH v6 18/29] tests/avocado: Tag TCG tests with accel:tcg
This allows the test to be skipped when TCG is not present in the QEMU binary. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé --- tests/avocado/boot_linux_console.py | 1 + tests/avocado/reverse_debugging.py | 8 2 files changed, 9 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index be60f8cda9..574609bf43 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -997,6 +997,7 @@ def test_arm_orangepi_uboot_netbsd9(self): def test_aarch64_raspi3_atf(self): """ +:avocado: tags=accel:tcg :avocado: tags=arch:aarch64 :avocado: tags=machine:raspi3b :avocado: tags=cpu:cortex-a53 diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py index d2921e70c3..680c314cfc 100644 --- a/tests/avocado/reverse_debugging.py +++ b/tests/avocado/reverse_debugging.py @@ -173,6 +173,10 @@ def reverse_debugging(self, shift=7, args=None): vm.shutdown() class ReverseDebugging_X86_64(ReverseDebugging): +""" +:avocado: tags=accel:tcg +""" + REG_PC = 0x10 REG_CS = 0x12 def get_pc(self, g): @@ -190,6 +194,10 @@ def test_x86_64_pc(self): self.reverse_debugging() class ReverseDebugging_AArch64(ReverseDebugging): +""" +:avocado: tags=accel:tcg +""" + REG_PC = 32 # unidentified gitlab timeout problem -- 2.35.3
[PATCH v6 13/29] target/arm: Move regime_using_lpae_format into internal.h
This function is needed by common code (ptw.c), so move it along with
the other regime_* functions in internal.h. When we enable the build
without TCG, the tlb_helper.c file will not be present.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 21 ++---
target/arm/tcg/tlb_helper.c | 18 --
2 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 22a0451157..6ebe59959e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -614,9 +614,6 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env,
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
-/* Return true if the translation regime is using LPAE format page tables */
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
-
/*
* Return true if the stage 1 translation regime is using LPAE
* format page tables
@@ -781,6 +778,24 @@ static inline uint64_t regime_tcr(CPUARMState *env,
ARMMMUIdx mmu_idx)
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
+/* Return true if the translation regime is using LPAE format page tables */
+static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx
mmu_idx)
+{
+int el = regime_el(env, mmu_idx);
+if (el == 2 || arm_el_is_aa64(env, el)) {
+return true;
+}
+if (arm_feature(env, ARM_FEATURE_PMSA) &&
+arm_feature(env, ARM_FEATURE_V8)) {
+return true;
+}
+if (arm_feature(env, ARM_FEATURE_LPAE)
+&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
+return true;
+}
+return false;
+}
+
/**
* arm_num_brps: Return number of implemented breakpoints.
* Note that the ID register BRPS field is "number of bps - 1",
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 60abcbebe6..31eb77f7df 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -12,24 +12,6 @@
#include "exec/helper-proto.h"
-/* Return true if the translation regime is using LPAE format page tables */
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
-int el = regime_el(env, mmu_idx);
-if (el == 2 || arm_el_is_aa64(env, el)) {
-return true;
-}
-if (arm_feature(env, ARM_FEATURE_PMSA) &&
-arm_feature(env, ARM_FEATURE_V8)) {
-return true;
-}
-if (arm_feature(env, ARM_FEATURE_LPAE)
-&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
-return true;
-}
-return false;
-}
-
/*
* Returns true if the stage 1 translation regime is using LPAE format page
* tables. Used when raising alignment exceptions, whose FSR changes depending
--
2.35.3
[PATCH v6 06/29] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
This is in preparation for restricting compilation of some parts of
debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas
---
Dropped r-bs because I added a few more ifs in debug_helper.c
---
target/arm/cpu.c | 6 --
target/arm/debug_helper.c | 16
target/arm/machine.c | 7 +--
3 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5f63316dbf..d7ceb626f0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -536,8 +536,10 @@ static void arm_cpu_reset_hold(Object *obj)
}
#endif
-hw_breakpoint_update_all(cpu);
-hw_watchpoint_update_all(cpu);
+if (tcg_enabled()) {
+hw_breakpoint_update_all(cpu);
+hw_watchpoint_update_all(cpu);
+}
arm_rebuild_hflags(env);
}
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 3c671c88c1..3325eb9d7d 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -939,7 +939,9 @@ static void dbgwvr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
value &= ~3ULL;
raw_write(env, ri, value);
-hw_watchpoint_update(cpu, i);
+if (tcg_enabled()) {
+hw_watchpoint_update(cpu, i);
+}
}
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -949,7 +951,9 @@ static void dbgwcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
int i = ri->crm;
raw_write(env, ri, value);
-hw_watchpoint_update(cpu, i);
+if (tcg_enabled()) {
+hw_watchpoint_update(cpu, i);
+}
}
void hw_breakpoint_update(ARMCPU *cpu, int n)
@@ -1062,7 +1066,9 @@ static void dbgbvr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
int i = ri->crm;
raw_write(env, ri, value);
-hw_breakpoint_update(cpu, i);
+if (tcg_enabled()) {
+hw_breakpoint_update(cpu, i);
+}
}
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1079,7 +1085,9 @@ static void dbgbcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
value = deposit64(value, 8, 1, extract64(value, 7, 1));
raw_write(env, ri, value);
-hw_breakpoint_update(cpu, i);
+if (tcg_enabled()) {
+hw_breakpoint_update(cpu, i);
+}
}
void define_debug_regs(ARMCPU *cpu)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index b4c3850570..fd6323f6d8 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "internals.h"
#include "migration/cpu.h"
@@ -848,8 +849,10 @@ static int cpu_post_load(void *opaque, int version_id)
return -1;
}
-hw_breakpoint_update_all(cpu);
-hw_watchpoint_update_all(cpu);
+if (tcg_enabled()) {
+hw_breakpoint_update_all(cpu);
+hw_watchpoint_update_all(cpu);
+}
/*
* TCG gen_update_fp_context() relies on the invariant that
--
2.35.3
[PATCH v6 03/29] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1fc860e039..bd704396e0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10819,11 +10819,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
unsigned int cur_el = arm_current_el(env);
int rt;
-/*
- * Note that new_el can never be 0. If cur_el is 0, then
- * el0_a64 is is_a64(), else el0_a64 is ignored.
- */
-aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+if (tcg_enabled()) {
+/*
+ * Note that new_el can never be 0. If cur_el is 0, then
+ * el0_a64 is is_a64(), else el0_a64 is ignored.
+ */
+aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+}
if (cur_el < new_el) {
/*
--
2.35.3
[PATCH v6 04/29] target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
target/arm/machine.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 5f26152652..b4c3850570 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -839,6 +839,15 @@ static int cpu_post_load(void *opaque, int version_id)
}
}
+/*
+ * Misaligned thumb pc is architecturally impossible. Fail the
+ * incoming migration. For TCG it would trigger the assert in
+ * thumb_tr_translate_insn().
+ */
+if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+return -1;
+}
+
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
@@ -856,15 +865,6 @@ static int cpu_post_load(void *opaque, int version_id)
}
}
-/*
- * Misaligned thumb pc is architecturally impossible.
- * We have an assert in thumb_tr_translate_insn to verify this.
- * Fail an incoming migrate to avoid this assert.
- */
-if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-return -1;
-}
-
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
--
2.35.3
[PATCH v6 02/29] target/arm: wrap psci call with tcg_enabled
From: Claudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
Tested-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 190be1a64d..1fc860e039 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -22,6 +22,7 @@
#include "hw/irq.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "qapi/qapi-commands-machine-target.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
@@ -11055,7 +11056,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception.syndrome);
}
-if (arm_is_psci_call(cpu, cs->exception_index)) {
+if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
arm_handle_psci_call(cpu);
qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
return;
--
2.35.3
Re: [PATCH] hw/ide/ahci: trace ncq write command as write instead of read
On Fri, Feb 17, 2023 at 7:27 AM Philippe Mathieu-Daudé
wrote:
>
> On 17/2/23 11:31, Fiona Ebner wrote:
> > Fixes: e4baa9f00b ("AHCI: Replace DPRINTF with trace-events")
>
> Oops
Seconding the whoops.
>
> > Signed-off-by: Fiona Ebner
> > ---
> >
> > Or should it be sorted alphabetically below execute_ncq_command_unsup?
>
> No, there is no convention...
>
> > I felt read and write belong close together and this reflects the
> > positions in the code.
>
> probably for this reason.
>
> Reviewed-by: Philippe Mathieu-Daudé
>
> Thanks!
>
Reviewed-by: John Snow
Re: [RFC PATCH] docs/about/deprecated: Deprecate 32-bit host systems
On 17/02/2023 17.38, Paolo Bonzini wrote: On 2/17/23 11:47, Daniel P. Berrangé wrote: On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote: I feel the discussion petered out without a conclusion. I don't think letting the status quo win by inertia is a good outcome here. Which 32-bit hosts are still useful, and why? Which 32-bit hosts does Linux still provide KVM support for. All except ARM: MIPS, x86, PPC and RISC-V. I would like to remove x86, but encountered some objections. So if I got that right: https://lore.kernel.org/all/b8fa9561295bb6af2b7fcaa8125c6a3b89b305c7.ca...@redhat.com/ ... the objection is mainly that some kernel developers want to keep the code around for easier testing of nested 32-bit guests L1 hypervisors. If that's the only use case that is still around for the 32-bit KVM x86 kernel code, I guess it should also be fine to use older versions of QEMU in those L1 hypervisor guests (assuming you have to use an older 32-bit Linux distro for this anyway). So unless I got that wrong, there is really nobody around anymore who needs an *upstream* QEMU for running 32-bit x86 KVM hosts, is there? Please correct me if I'm wrong, but I think we can really deprecated at least qemu-system-i386 and qemu-system-arm now, can't we? Thanks, Thomas
Re: [PATCH 2/2] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron via wrote:
> On Tue, 31 Jan 2023 16:38:47 +
> Jonathan Cameron via wrote:
>
> > From: Gregory Price
> >
> > This commit enables each CXL Type-3 device to contain one volatile
> > memory region and one persistent region.
> >
> > Two new properties have been added to cxl-type3 device initialization:
> > [volatile-memdev] and [persistent-memdev]
> >
> > The existing [memdev] property has been deprecated and will default the
> > memory region to a persistent memory region (although a user may assign
> > the region to a ram or file backed region). It cannot be used in
> > combination with the new [persistent-memdev] property.
> >
> > Partitioning volatile memory from persistent memory is not yet supported.
> >
> > Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped
> > at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
> >
> > Signed-off-by: Gregory Price
> > Signed-off-by: Jonathan Cameron
> >
> Hi Gregory,
>
> I've added support for multiple HDM decoders and hence can now
> test both volatile and non volatile on same device.
> It very nearly all works. With one exception which is I couldn't
> poke the first byte of the non volatile region.
>
> I think we have an off by one in a single check.
>
> Interestingly it makes no difference when creating an FS on top
> (which was my standard test) so I only noticed when poking memory
> addresses directly to sanity check the HDM decoder setup.
>
> I'll roll a v2 if no one shouts out that I'm wrong.
>
> Note that adding multiple HDM decoders massively increases
> the number of test cases over what we had before to poke all the
> corners so I may well be missing stuff. Hopefully can send an RFC
> of that support out next week.
>
> Jonathan
>
Very cool! Thanks for pushing this over the finishing line.
All my testing so far has been really smooth since getting the TCG issue
worked out.
> > -MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
> > - unsigned size, MemTxAttrs attrs)
[...]
> > +if (vmr) {
> > +if (*dpa_offset <= int128_get64(vmr->size)) {
>
> Off by one I think. <
>
Yes that makes sense, should be <. Derp derp.
Though I think this may alludes to more off-by-one issues? This says
if (dpa_offset < vmr->size)
but dpa_offset should be (hpa - memory_region_base),
The HPA is used by memory access routing for the whole system to determine
what device it should access.
If that corner case is being hit, doesn't it imply the higher level code
is also susceptible to this, and is routing accesses to the wrong device?
~Gregory
Re: CXL 2.0 memory pooling emulation
On Fri, Feb 17, 2023 at 11:14:18AM +, Jonathan Cameron wrote: > On Thu, 16 Feb 2023 15:52:31 -0500 > Gregory Price wrote: > > > > > I agree, it's certainly "not pretty". > > > > I'd go so far as to call the baby ugly :]. Like i said: "The Hackiest way" > > > > My understanding from looking around at some road shows is that some > > of these early multi-headed devices are basically just SLD's with multiple > > heads. Most of these devices had to be developed well before DCD's and > > therefore the FM-API were placed in the spec, and we haven't seen or > > heard of any of these early devices having any form of switch yet. > > > > I don't see how this type of device is feasible unless it's either > > statically > > provisioned (change firmware settings from bios on reboot) or implements > > custom firmware commands to implement some form of exclusivity controls over > > memory regions. > > > > The former makes it not really a useful pooling device, so I'm sorta > > guessing > > we'll see most of these early devices implement custom commands. > > > > I'm just not sure these early MHD's are going to have any real form of > > FM-API, but it would still be nice to emulate them. > > > Makes sense. I'd be fine with adding any necessary hooks to allow that > in the QEMU emulation, but probably not upstreaming the custom stuff. > > Jonathan > I'll have to give it some thought. The "custom stuff" is mostly init code, mailbox commands, and the fields those mailbox commands twiddle. I guess we could create a wrapper-device that hooks raw commands? Is that what raw commands are intended for? Notably the kernel has to be compiled with raw command support, which is disabled by default, but that's fine. Dunno, spitballing, but i'm a couple days away from a first pass at a MHD, though I'll need to spend quite a bit of time cleaning it up before i can push an RFC. ~Gregory
Re: [RFC PATCH] docs/about/deprecated: Deprecate 32-bit host systems
On 17/02/2023 18.43, Philippe Mathieu-Daudé wrote:
(Cc'ing Huacai & Jiaxun).
On 17/2/23 17:38, Paolo Bonzini wrote:
On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't think letting the status quo win by inertia is a good outcome
here.
Which 32-bit hosts are still useful, and why?
Which 32-bit hosts does Linux still provide KVM support for.
All except ARM: MIPS, x86, PPC and RISC-V.
I would like to remove x86, but encountered some objections.
MIPS, nobody is really using it I think.
32-bit was added in 2014, commit 222e7d11e7 ("target-mips: Enable KVM
support in build system"). I'm not aware of anybody using it (even
testing it). I don't have hardware to test it (neither time).
Could you maybe suggest a kernel patch to remove it, to see what happens?
... if nobody objects to the removal of the 32-bit MIPS KVM kernel support
and the patch gets merged, that would help us in the long run, I think.
Thanks,
Thomas
Re: [PATCH 2/2] hw/timer: Reduce 'hw/ptimer.h' inclusion
On 17/02/2023 15.18, Philippe Mathieu-Daudé wrote: "hw/ptimer.h" API is mostly used by timer / watchdog device models. Since the SoC / machines only access the ptimer via reference, they don't need its definition: the declartion is enough. On order to reduce the inclusion on the source files, forward-declare 'ptimer_state' in "qemu/typedefs.h". Use the typedef in few place instead of the structure. Signed-off-by: Philippe Mathieu-Daudé --- "30 files changed"... but since this is trivial, there is no point in splitting per subsystem IMO. --- ... diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index df4b55ac65..effcba4bca 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -104,6 +104,7 @@ typedef struct PICCommonState PICCommonState; typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; +typedef struct ptimer_state ptimer_state; Would it make sense to properly CamelCase the type while you're at it anyway? Thomas
Re: [RFC PATCH] docs/about/build-platforms: Refine the distro support policy
On 17/02/2023 16.59, Daniel P. Berrangé wrote: On Fri, Feb 17, 2023 at 04:55:49PM +0100, Markus Armbruster wrote: The cost/benefit tradeoff of dropping the platforms entirely is not obviously favourable when we don't have clear demand to bump the min versions of native packages, and the cost to users stuck on these platforms to build their own toolchain or libraries is very high. There's another urgent point which I completely forget to mention in my patch description (not sure how I managed that, since it's bugging me quite badly in the past weeks): We're struggling heavily with CI minutes. If we have to support multiple major releases for a long time in parallel, there will always be the desire to have all major releases also tested in the CI ... and honestly, we're really struggling quite badly there right now - as you know, we've already run out of CI minutes in January in the main project, and also in my forked repo I'm struggling each month. Additionally, it's of course additional effort to keep everything in the "green" state the more you have to support. We're currently "lucky" in a sense that we're only testing one version of CentOS, Debian and Ubuntu right now, but there have been voices in the past weeks asking for more already (like we also did in the past already). I'd really appreciate if we could have a clearer policy here to support less at the same time. It would help with the pressure on the CI and the effort and time it takes to maintain all that stuff. Thomas
Re: [RFC PATCH] docs/about/build-platforms: Refine the distro support policy
On 17/02/2023 16.06, Daniel P. Berrangé wrote: On Fri, Feb 17, 2023 at 02:26:31PM +0100, Thomas Huth wrote: ... I'm also not so comfortable dropping the only version of SLES that we explicitly target, when we don't know when their new major release will arrive. Let's hope that the next major version will show up at least five years after the previous one ... but what if it takes many more years? Do we want to support very old long term distros for "almost forever"? Also, should we maybe at least limit the time to 5 years? Otherwise, if openSUSE 16 gets released 5 years after v15, we have to support v15 for 7 years in total due to the "two more years" rule... If we allow compilers, libraries to be bumped, then someone stuck on RHEL-8 has a significant task to build their own toolchain/libraries in order to work with QEMU still. If we only allow python modules to be bumped, the solution is just a pip install / virtualenv away. Honestly, being a Python ignorant, I'm more comfortable with "./configure && make && make install" instead of messing up my system with pip like I did in the past ... but I guess it's ok if it is properly done automatically under the hood with a venv ... I'll get used to it ;-) Thomas
Re: [RFC PATCH] docs/about/deprecated: Deprecate 32-bit host systems
On 2/17/23 06:06, Reinoud Zandijk wrote: On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote: I feel the discussion petered out without a conclusion. I don't think letting the status quo win by inertia is a good outcome here. Which 32-bit hosts are still useful, and why? NetBSD runs on a bunch of 32 bit-only hosts (sparc32, ppc32, armv7, vax, mips32 etc.) that all run Qemu fine. They are all actively maintained and released as part of the main releases. Are you sure about that? TCG doesn't support sparc32 or vax. I suppose you could be using TCI, but I can't even imagine how slow that would be on vax. r~
[PATCH 6/6] hw/cxl: Add clear poison mailbox command support.
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 77 +
hw/mem/cxl_type3.c | 36 +
include/hw/cxl/cxl_device.h | 1 +
3 files changed, 114 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 7d3f7bcd3a..f56c76b205 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -65,6 +65,7 @@ enum {
MEDIA_AND_POISON = 0x43,
#define GET_POISON_LIST0x0
#define INJECT_POISON 0x1
+#define CLEAR_POISON 0x2
};
struct cxl_cmd;
@@ -474,6 +475,80 @@ static CXLRetCode cmd_media_inject_poison(struct cxl_cmd
*cmd,
return CXL_MBOX_SUCCESS;
}
+static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+CXLPoisonList *poison_list = &ct3d->poison_list;
+CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
+struct clear_poison_pl {
+uint64_t dpa;
+uint8_t data[64];
+};
+CXLPoison *ent;
+
+struct clear_poison_pl *in = (void *)cmd->payload;
+
+if (in->dpa + 64 > cxl_dstate->mem_size) {
+return CXL_MBOX_INVALID_PA;
+}
+
+QLIST_FOREACH(ent, poison_list, node) {
+/*
+ * Test for contained in entry. Simpler than general case
+ * as clearing 64 bytes and entries 64 byte aligned
+ */
+if ((in->dpa < ent->start) || (in->dpa >= ent->start + ent->length)) {
+continue;
+}
+/* Do accounting early as we know one will go away */
+ct3d->poison_list_cnt--;
+if (in->dpa > ent->start) {
+CXLPoison *frag;
+if (ct3d->poison_list_cnt == CXL_POISON_LIST_LIMIT) {
+cxl_set_poison_list_overflowed(ct3d);
+break;
+}
+frag = g_new0(CXLPoison, 1);
+
+frag->start = ent->start;
+frag->length = in->dpa - ent->start;
+frag->type = ent->type;
+
+QLIST_INSERT_HEAD(poison_list, frag, node);
+ct3d->poison_list_cnt++;
+}
+if (in->dpa + 64 < ent->start + ent->length) {
+CXLPoison *frag;
+
+if (ct3d->poison_list_cnt == CXL_POISON_LIST_LIMIT) {
+cxl_set_poison_list_overflowed(ct3d);
+break;
+}
+
+frag = g_new0(CXLPoison, 1);
+
+frag->start = in->dpa + 64;
+frag->length = ent->start + ent->length - frag->start;
+frag->type = ent->type;
+QLIST_INSERT_HEAD(poison_list, frag, node);
+ct3d->poison_list_cnt++;
+}
+/* Any fragments have been added, free original entry */
+QLIST_REMOVE(ent, node);
+g_free(ent);
+break;
+}
+/* Clearing a region with no poison is not an error so always do so */
+if (cvc->set_cacheline)
+if (!cvc->set_cacheline(ct3d, in->dpa, in->data)) {
+return CXL_MBOX_INTERNAL_ERROR;
+}
+
+return CXL_MBOX_SUCCESS;
+}
+
#define IMMEDIATE_CONFIG_CHANGE (1 << 1)
#define IMMEDIATE_DATA_CHANGE (1 << 2)
#define IMMEDIATE_POLICY_CHANGE (1 << 3)
@@ -505,6 +580,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
cmd_media_get_poison_list, 16, 0 },
[MEDIA_AND_POISON][INJECT_POISON] = { "MEDIA_AND_POISON_INJECT_POISON",
cmd_media_inject_poison, 8, 0 },
+[MEDIA_AND_POISON][CLEAR_POISON] = { "MEDIA_AND_POISON_CLEAR_POISON",
+cmd_media_clear_poison, 72, 0 },
};
void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3585f78b4e..8adc725edc 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -925,6 +925,41 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf,
uint64_t size,
*/
}
+static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t
*data)
+{
+MemoryRegion *vmr = NULL, *pmr = NULL;
+AddressSpace *as;
+
+if (ct3d->hostvmem) {
+vmr = host_memory_backend_get_memory(ct3d->hostvmem);
+}
+if (ct3d->hostpmem) {
+pmr = host_memory_backend_get_memory(ct3d->hostpmem);
+}
+
+if (!vmr && !pmr) {
+return false;
+}
+
+if (dpa_offset + 64 > int128_get64(ct3d->cxl_dstate.mem_size)) {
+return false;
+}
+
+if (vmr) {
+if (dpa_offset <= int128_get64(vmr->size)) {
+as = &ct3d->hostvmem_as;
+} else {
+as = &ct3d->hostpmem_as;
+dpa_offset -= vmr->size;
+}
+} else {
+as = &ct3d->hostpmem_as;
+}
+
+address_space_write(as, dpa_offset, MEMTXATTRS_UNSPECIFIED, &data, 64
[PATCH 5/6] hw/cxl: Add poison injection via the mailbox.
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 40 ++
1 file changed, 40 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index cf3cfb10a1..7d3f7bcd3a 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -64,6 +64,7 @@ enum {
#define SET_LSA 0x3
MEDIA_AND_POISON = 0x43,
#define GET_POISON_LIST0x0
+#define INJECT_POISON 0x1
};
struct cxl_cmd;
@@ -436,6 +437,43 @@ static CXLRetCode cmd_media_get_poison_list(struct cxl_cmd
*cmd,
return CXL_MBOX_SUCCESS;
}
+static CXLRetCode cmd_media_inject_poison(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+CXLPoisonList *poison_list = &ct3d->poison_list;
+CXLPoison *ent;
+struct inject_poison_pl {
+uint64_t dpa;
+};
+struct inject_poison_pl *in = (void *)cmd->payload;
+CXLPoison *p;
+
+QLIST_FOREACH(ent, poison_list, node) {
+if (ent->start == in->dpa && ent->length == 64) {
+return CXL_MBOX_SUCCESS;
+}
+}
+
+if (ct3d->poison_list_cnt == CXL_POISON_LIST_LIMIT) {
+return CXL_MBOX_INJECT_POISON_LIMIT;
+}
+p = g_new0(CXLPoison, 1);
+
+p->length = 64;
+p->start = in->dpa;
+p->type = CXL_POISON_TYPE_INJECTED;
+
+/*
+ * Possible todo: Merge with existing entry if next to it and if same type
+ */
+QLIST_INSERT_HEAD(poison_list, p, node);
+ct3d->poison_list_cnt++;
+
+return CXL_MBOX_SUCCESS;
+}
+
#define IMMEDIATE_CONFIG_CHANGE (1 << 1)
#define IMMEDIATE_DATA_CHANGE (1 << 2)
#define IMMEDIATE_POLICY_CHANGE (1 << 3)
@@ -465,6 +503,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
[MEDIA_AND_POISON][GET_POISON_LIST] = { "MEDIA_AND_POISON_GET_POISON_LIST",
cmd_media_get_poison_list, 16, 0 },
+[MEDIA_AND_POISON][INJECT_POISON] = { "MEDIA_AND_POISON_INJECT_POISON",
+cmd_media_inject_poison, 8, 0 },
};
void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
--
2.37.2
Re: [PATCH v1 2/4] linux-user: fix sockaddr_in6 endianness
On 17/2/23 17:35, Mathis Marion wrote: From: Mathis Marion Fields sin6_flowinfo and sin6_scope_id use the host byte order, so there is a conversion to be made when host and target endianness differ. Signed-off-by: Mathis Marion --- linux-user/syscall.c | 6 ++ 1 file changed, 6 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
[PATCH 4/6] hw/cxl: QMP based poison injection support
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
https://lore.kernel.org/linux-cxl/cover.1665606782.git.alison.schofi...@intel.com/
To inject poison using qmp (telnet to the qmp port)
{ "execute": "qmp_capabilities" }
{ "execute": "cxl-inject-poison",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"start": 2048,
"length": 256
}
}
Adjusted to select a device on your machine.
Note that the poison list supported is kept short enough to avoid the
complexity of state machine that is needed to handle the MORE flag.
Signed-off-by: Jonathan Cameron
---
v3:
Improve QMP documentation.
v2:
Moved to QMP to allow for single command.
Update reference in coverletter
Added specific setting of type for this approach to injection.
Drop the unnecessary ct3d class get_poison_list callback.
Block overlapping regions from being injected
Handle list overflow
Use Ira's utility function to get the timestamps
---
hw/cxl/cxl-mailbox-utils.c | 82 +
hw/mem/cxl_type3.c | 56 +
hw/mem/cxl_type3_stubs.c| 3 ++
hw/mem/meson.build | 2 +
include/hw/cxl/cxl_device.h | 20 +
qapi/cxl.json | 16
6 files changed, 179 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 580366ed2f..cf3cfb10a1 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -62,6 +62,8 @@ enum {
#define GET_PARTITION_INFO 0x0
#define GET_LSA 0x2
#define SET_LSA 0x3
+MEDIA_AND_POISON = 0x43,
+#define GET_POISON_LIST0x0
};
struct cxl_cmd;
@@ -267,6 +269,8 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd
*cmd,
id->persistent_capacity = cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER;
id->volatile_capacity = cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER;
id->lsa_size = cvc->get_lsa_size(ct3d);
+id->poison_list_max_mer[1] = 0x1; /* 256 poison records */
+id->inject_poison_limit = 0; /* No limit - so limited by main poison
record limit */
*len = sizeof(*id);
return CXL_MBOX_SUCCESS;
@@ -356,6 +360,82 @@ static CXLRetCode cmd_ccls_set_lsa(struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+/*
+ * This is very inefficient, but good enough for now!
+ * Also the payload will always fit, so no need to handle the MORE flag and
+ * make this stateful. We may want to allow longer poison lists to aid
+ * testing that kernel functionality.
+ */
+static CXLRetCode cmd_media_get_poison_list(struct cxl_cmd *cmd,
+CXLDeviceState *cxl_dstate,
+uint16_t *len)
+{
+struct get_poison_list_pl {
+uint64_t pa;
+uint64_t length;
+} QEMU_PACKED;
+
+struct get_poison_list_out_pl {
+uint8_t flags;
+uint8_t rsvd1;
+uint64_t overflow_timestamp;
+uint16_t count;
+uint8_t rsvd2[0x14];
+struct {
+uint64_t addr;
+uint32_t length;
+uint32_t resv;
+} QEMU_PACKED records[];
+} QEMU_PACKED;
+
+struct get_poison_list_pl *in = (void *)cmd->payload;
+struct get_poison_list_out_pl *out = (void *)cmd->payload;
+CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+uint16_t record_count = 0, i = 0;
+uint64_t query_start = in->pa;
+uint64_t query_length = in->length;
+CXLPoisonList *poison_list = &ct3d->poison_list;
+CXLPoison *ent;
+uint16_t out_pl_len;
+
+QLIST_FOREACH(ent, poison_list, node) {
+/* Check for no overlap */
+if (ent->start >= query_start + query_length ||
+ent->start + ent->length <= query_start) {
+continue;
+}
+record_count++;
+}
+out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]);
+assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE);
+
+memset(out, 0, out_pl_len);
+QLIST_FOREACH(ent, poison_list, node) {
+uint64_t start, stop;
+
+/* Check for no overlap */
+if (ent->start >= query_start + query_length ||
+ent->start + ent->length <= query_start) {
+continue;
+}
+
+/* Deal with overlap */
+start = MAX(ent->start & 0xffc0, query_start);
+stop = MIN((ent->start & 0xffc0) + ent->length,
+ query_start + query_length);
+out->records[i].addr = start | (ent->type & 0x3);
+out->records[i].length = (stop - start) / 64;
+i++;
+}
+if (ct3d->poison_list_overflowed) {
+out->flags = (1 << 1);
+out->overfl
[PATCH 3/6] hw/cxl: Introduce cxl_device_get_timestamp() utility function
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 15 +++
hw/cxl/cxl-mailbox-utils.c | 11 +--
include/hw/cxl/cxl_device.h | 2 ++
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index 4c5e88aaf5..86e1cea8ce 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -269,3 +269,18 @@ void cxl_device_register_init_common(CXLDeviceState
*cxl_dstate)
cxl_initialize_mailbox(cxl_dstate);
}
+
+uint64_t cxl_device_get_timestamp(CXLDeviceState *cxl_dstate)
+{
+uint64_t time, delta;
+uint64_t final_time = 0;
+
+if (cxl_dstate->timestamp.set) {
+/* Find the delta from the last time the host set the time. */
+time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+delta = time - cxl_dstate->timestamp.last_set;
+final_time = cxl_dstate->timestamp.host_set + delta;
+}
+
+return final_time;
+}
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 67aca3fd6c..580366ed2f 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -135,17 +135,8 @@ static CXLRetCode cmd_timestamp_get(struct cxl_cmd *cmd,
CXLDeviceState *cxl_dstate,
uint16_t *len)
{
-uint64_t time, delta;
-uint64_t final_time = 0;
-
-if (cxl_dstate->timestamp.set) {
-/* First find the delta from the last time the host set the time. */
-time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
-delta = time - cxl_dstate->timestamp.last_set;
-final_time = cxl_dstate->timestamp.host_set + delta;
-}
+uint64_t final_time = cxl_device_get_timestamp(cxl_dstate);
-/* Then adjust the actual time */
stq_le_p(cmd->payload, final_time);
*len = 8;
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index b737c3699f..44fea2d649 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -315,4 +315,6 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr,
uint64_t *data,
MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
unsigned size, MemTxAttrs attrs);
+uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds);
+
#endif
--
2.37.2
[PATCH 2/6] hw/cxl: rename mailbox return code type from ret_code to CXLRetCode
This enum typedef used to be local to one file, so having a generic
name wasn't a big problem even if it wasn't compliant with QEMU naming
conventions. Now it is in cxl_device.h to support use outside of
cxl-mailbox-utils.c rename it.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 62 ++---
include/hw/cxl/cxl_device.h | 2 +-
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index d9bd5daa0d..67aca3fd6c 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -23,7 +23,7 @@
* FOO= 0x7f,
* #define BAR 0
* 2. Implement the handler
- *static ret_code cmd_foo_bar(struct cxl_cmd *cmd,
+ *static CXLRetCode cmd_foo_bar(struct cxl_cmd *cmd,
* CXLDeviceState *cxl_dstate, uint16_t *len)
* 3. Add the command to the cxl_cmd_set[][]
*[FOO][BAR] = { "FOO_BAR", cmd_foo_bar, x, y },
@@ -65,7 +65,7 @@ enum {
};
struct cxl_cmd;
-typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
+typedef CXLRetCode (*opcode_handler)(struct cxl_cmd *cmd,
CXLDeviceState *cxl_dstate, uint16_t *len);
struct cxl_cmd {
const char *name;
@@ -77,16 +77,16 @@ struct cxl_cmd {
#define DEFINE_MAILBOX_HANDLER_ZEROED(name, size) \
uint16_t __zero##name = size; \
-static ret_code cmd_##name(struct cxl_cmd *cmd, \
- CXLDeviceState *cxl_dstate, uint16_t *len) \
+static CXLRetCode cmd_##name(struct cxl_cmd *cmd, \
+ CXLDeviceState *cxl_dstate, uint16_t *len) \
{ \
*len = __zero##name; \
memset(cmd->payload, 0, *len);\
return CXL_MBOX_SUCCESS; \
}
#define DEFINE_MAILBOX_HANDLER_NOP(name) \
-static ret_code cmd_##name(struct cxl_cmd *cmd, \
- CXLDeviceState *cxl_dstate, uint16_t *len) \
+static CXLRetCode cmd_##name(struct cxl_cmd *cmd, \
+ CXLDeviceState *cxl_dstate, uint16_t *len) \
{ \
return CXL_MBOX_SUCCESS; \
}
@@ -97,9 +97,9 @@ DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
/* 8.2.9.2.1 */
-static ret_code cmd_firmware_update_get_info(struct cxl_cmd *cmd,
- CXLDeviceState *cxl_dstate,
- uint16_t *len)
+static CXLRetCode cmd_firmware_update_get_info(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
{
struct {
uint8_t slots_supported;
@@ -131,9 +131,9 @@ static ret_code cmd_firmware_update_get_info(struct cxl_cmd
*cmd,
}
/* 8.2.9.3.1 */
-static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
- CXLDeviceState *cxl_dstate,
- uint16_t *len)
+static CXLRetCode cmd_timestamp_get(struct cxl_cmd *cmd,
+CXLDeviceState *cxl_dstate,
+uint16_t *len)
{
uint64_t time, delta;
uint64_t final_time = 0;
@@ -153,7 +153,7 @@ static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
}
/* 8.2.9.3.2 */
-static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
+static CXLRetCode cmd_timestamp_set(struct cxl_cmd *cmd,
CXLDeviceState *cxl_dstate,
uint16_t *len)
{
@@ -173,9 +173,9 @@ static const QemuUUID cel_uuid = {
};
/* 8.2.9.4.1 */
-static ret_code cmd_logs_get_supported(struct cxl_cmd *cmd,
- CXLDeviceState *cxl_dstate,
- uint16_t *len)
+static CXLRetCode cmd_logs_get_supported(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
{
struct {
uint16_t entries;
@@ -196,9 +196,9 @@ static ret_code cmd_logs_get_supported(struct cxl_cmd *cmd,
}
/* 8.2.9.4.2 */
-static ret_code cmd_logs_get_log(struct cxl_cmd *cmd,
- CXLDeviceState *cxl_dstate,
- uint16_t *len)
+static CXLRetCode cmd_logs_get_log(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
[PATCH 1/6] hw/cxl: Move enum ret_code definition to cxl_device.h
Needs tidy up and rename to something more generic now it is
in a header.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 28
include/hw/cxl/cxl_device.h | 28
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index cc9c8b7380..d9bd5daa0d 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -64,34 +64,6 @@ enum {
#define SET_LSA 0x3
};
-/* 8.2.8.4.5.1 Command Return Codes */
-typedef enum {
-CXL_MBOX_SUCCESS = 0x0,
-CXL_MBOX_BG_STARTED = 0x1,
-CXL_MBOX_INVALID_INPUT = 0x2,
-CXL_MBOX_UNSUPPORTED = 0x3,
-CXL_MBOX_INTERNAL_ERROR = 0x4,
-CXL_MBOX_RETRY_REQUIRED = 0x5,
-CXL_MBOX_BUSY = 0x6,
-CXL_MBOX_MEDIA_DISABLED = 0x7,
-CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
-CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
-CXL_MBOX_FW_AUTH_FAILED = 0xa,
-CXL_MBOX_FW_INVALID_SLOT = 0xb,
-CXL_MBOX_FW_ROLLEDBACK = 0xc,
-CXL_MBOX_FW_REST_REQD = 0xd,
-CXL_MBOX_INVALID_HANDLE = 0xe,
-CXL_MBOX_INVALID_PA = 0xf,
-CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
-CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
-CXL_MBOX_ABORTED = 0x12,
-CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
-CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
-CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
-CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
-CXL_MBOX_MAX = 0x17
-} ret_code;
-
struct cxl_cmd;
typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,
CXLDeviceState *cxl_dstate, uint16_t *len);
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index edb9791bab..d01c6b29c5 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -82,6 +82,34 @@
(CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \
CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
+/* 8.2.8.4.5.1 Command Return Codes */
+typedef enum {
+CXL_MBOX_SUCCESS = 0x0,
+CXL_MBOX_BG_STARTED = 0x1,
+CXL_MBOX_INVALID_INPUT = 0x2,
+CXL_MBOX_UNSUPPORTED = 0x3,
+CXL_MBOX_INTERNAL_ERROR = 0x4,
+CXL_MBOX_RETRY_REQUIRED = 0x5,
+CXL_MBOX_BUSY = 0x6,
+CXL_MBOX_MEDIA_DISABLED = 0x7,
+CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
+CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
+CXL_MBOX_FW_AUTH_FAILED = 0xa,
+CXL_MBOX_FW_INVALID_SLOT = 0xb,
+CXL_MBOX_FW_ROLLEDBACK = 0xc,
+CXL_MBOX_FW_REST_REQD = 0xd,
+CXL_MBOX_INVALID_HANDLE = 0xe,
+CXL_MBOX_INVALID_PA = 0xf,
+CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
+CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
+CXL_MBOX_ABORTED = 0x12,
+CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
+CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
+CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
+CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
+CXL_MBOX_MAX = 0x17
+} ret_code;
+
typedef struct cxl_device_state {
MemoryRegion device_registers;
--
2.37.2
[PATCH 0/6] hw/cxl: Poison get, inject, clear
Note Alison has stated the kernel series will be post 6.3 material so this one isn't quite as urgent as the patches it is based on. However I think this series in a good state (plus I have lots more queued behind it) hence promoting it from RFC. Changes since RFC v2: Thanks to Markus for review. - Improve documentation for QMP interface - Add better description of baseline series - Include precursor refactors around ret_code / CXLRetCode as this is now the first series in suggeste merge order to rely on those. - Include Ira's cxl_device_get_timestamp() function as it was better than the equivalent in the RFC. Based on following series (in order) 1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream 2. [PATCH v4 0/8] hw/cxl: RAS error emulation and injection 3. [PATCH 0/2] hw/cxl: Passthrough HDM decoder emulation 4. [PATCH v2 0/2] hw/mem: CXL Type-3 Volatile Memory Support Based on: Message-Id: 20230206172816.8201-1-jonathan.came...@huawei.com Based-on: Message-id: 20230217172924.25239-1-jonathan.came...@huawei.com Based-on: Message-id: 20230125152703.9928-1-jonathan.came...@huawei.com Based-on: Message-id: 20230217175657.26632-1-jonathan.came...@huawei.com The series supports: 1) Injection of variable length poison regions via QMP (to fake real memory corruption and ensure we deal with odd overflow corner cases such as clearing the middle of a large region making the list overflow as we go from one long entry to two smaller entries. 2) Read of poison list via the CXL mailbox. 3) Injection via the poison injection mailbox command (limited to 64 byte entries) 4) Clearing of poison injected via either method. The implementation is meant to be a valid combination of impdef choices based on what the spec allowed. There are a number of places where it could be made more sophisticated that we might consider in future: * Fusing adjacent poison entries if the types match. * Separate injection list and main poison list, to test out limits on injected poison list being smaller than the main list. * Poison list overflow event (needs event log support in general) * Connecting up to the poison list error record generation (rather complex and not needed for currently kernel handling testing). As the kernel code is currently fairly simple, it is likely that the above does not yet matter but who knows what will turn up in future! Kernel patches: [PATCH v6 0/6] CXL Poison List Retrieval & Tracing Message-id: cover.1675983077.git.alison.schofi...@intel.com [PATCH v2 0/6] cxl: CXL Inject & Clear Poison cover.1674101475.git.alison.schofi...@intel.com Ira Weiny (1): hw/cxl: Introduce cxl_device_get_timestamp() utility function Jonathan Cameron (5): hw/cxl: Move enum ret_code definition to cxl_device.h hw/cxl: rename mailbox return code type from ret_code to CXLRetCode hw/cxl: QMP based poison injection support hw/cxl: Add poison injection via the mailbox. hw/cxl: Add clear poison mailbox command support. hw/cxl/cxl-device-utils.c | 15 ++ hw/cxl/cxl-mailbox-utils.c | 300 +++- hw/mem/cxl_type3.c | 92 +++ hw/mem/cxl_type3_stubs.c| 3 + hw/mem/meson.build | 2 + include/hw/cxl/cxl_device.h | 51 ++ qapi/cxl.json | 16 ++ 7 files changed, 410 insertions(+), 69 deletions(-) -- 2.37.2
Re: [PATCH v2 5/5] hw/nvme: flexible data placement emulation
On Fri, Feb 17, 2023 at 01:07:43PM +0100, Jesper Devantier wrote:
> +static void nvme_do_write_fdp(NvmeCtrl *n, NvmeRequest *req, uint64_t slba,
> + uint32_t nlb)
> +{
> +NvmeNamespace *ns = req->ns;
> +NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
> +uint64_t data_size = nvme_l2b(ns, nlb);
> +uint32_t dw12 = le32_to_cpu(req->cmd.cdw12);
> +uint8_t dtype = (dw12 >> 20) & 0xf;
> +uint16_t pid = le16_to_cpu(rw->dspec);
> +uint16_t ph, rg, ruhid;
> +NvmeReclaimUnit *ru;
> +
> +if (dtype != NVME_DIRECTIVE_DATA_PLACEMENT
> +|| !nvme_parse_pid(ns, pid, &ph, &rg)) {
Style nit, the "||" ought to go in the previous line.
> +ph = 0;
> +rg = 0;
> +}
> +
> +ruhid = ns->fdp.phs[ph];
> +ru = &ns->endgrp->fdp.ruhs[ruhid].rus[rg];
> +
> +nvme_fdp_stat_inc(&ns->endgrp->fdp.hbmw, data_size);
> +nvme_fdp_stat_inc(&ns->endgrp->fdp.mbmw, data_size);
> +
> +//trace_pci_nvme_fdp_ruh_write(ruh->rgid, ruh->ruhid, ruh->nlb_ruamw,
> nlb);
> +
> +while (nlb) {
> +if (nlb < ru->ruamw) {
> +ru->ruamw -= nlb;
> +break;
> +}
> +
> +nlb -= ru->ruamw;
> +//trace_pci_nvme_fdp_ruh_change(ruh->rgid, ruh->ruhid);
Please use the trace points if you find them useful, otherwise just delete
them instead of committing commented out code.
Beyond that, looks good! For the series:
Reviewed-by: Keith Busch
Re: [PATCH 2/2] hw/timer: Reduce 'hw/ptimer.h' inclusion
On 2/17/23 04:18, Philippe Mathieu-Daudé wrote: "hw/ptimer.h" API is mostly used by timer / watchdog device models. Since the SoC / machines only access the ptimer via reference, they don't need its definition: the declartion is enough. On order to reduce the inclusion on the source files, forward-declare 'ptimer_state' in "qemu/typedefs.h". Use the typedef in few place instead of the structure. Signed-off-by: Philippe Mathieu-Daudé --- "30 files changed"... but since this is trivial, there is no point in splitting per subsystem IMO. --- Reviewed-by: Richard Henderson r~
[PATCH v2 2/2] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
From: Gregory Price This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region. Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev] The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property. Partitioning volatile memory from persistent memory is not yet supported. Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info. Signed-off-by: Gregory Price Reviewed-by: Davidlohr Bueso Reviewed-by: Fan Ni Tested-by: Fan Ni Signed-off-by: Jonathan Cameron --- v2: - Fixed an off by one in address space selection. - Gather tags. --- docs/system/devices/cxl.rst| 49 -- hw/cxl/cxl-mailbox-utils.c | 26 +-- hw/mem/cxl_type3.c | 300 + include/hw/cxl/cxl_device.h| 11 +- tests/qtest/bios-tables-test.c | 8 +- tests/qtest/cxl-test.c | 76 +++-- 6 files changed, 359 insertions(+), 111 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..89a41cff73 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -300,7 +300,7 @@ Example topology involving a switch:: Example command lines - -A very simple setup with just one directly attached CXL Type 3 device:: +A very simple setup with just one directly attached CXL Type 3 Persistent Memory device:: qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ ... @@ -308,7 +308,28 @@ A very simple setup with just one directly attached CXL Type 3 device:: -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ - -device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ + -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G + +A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: + + qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + ... + -object memory-backend-ram,id=vmem0,share=on,size=256M \ + -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ + -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ + -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0 \ + -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G + +The same volatile setup may optionally include an LSA region:: + + qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + ... + -object memory-backend-ram,id=vmem0,share=on,size=256M \ + -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \ + -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ + -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ + -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,lsa=cxl-lsa0,id=cxl-vmem0 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G A setup suitable for 4 way interleave. Only one fixed window provided, to enable 2 way @@ -328,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ - -device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ - -device cxl-type3,bus=root_port14,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ - -device cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ - -device cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: @@ -354,15 +375,23 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-rp,port=1,bus=cxl.1,id=root_p
Re: [PATCH 1/2] qemu/typedefs: Sort in case-insensitive alphabetical order (again)
On 2/17/23 04:18, Philippe Mathieu-Daudé wrote:
Following the recommendation added in commit a98c370c46
("typedefs: (Re-)sort entries alphabetically"), and similarly
to commit 64baadc272 ("Sort include/qemu/typedefs.h"), sort
again the type definitions (in case-insensitive alphabetical
order, using 'sort --ignore-case').
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/typedefs.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
[PATCH v2 1/2] tests/qtest/cxl-test: whitespace, line ending cleanup
From: Gregory Price Defines are starting to exceed line length limits, align them for cleanliness before making modifications. Signed-off-by: Gregory Price Signed-off-by: Jonathan Cameron --- tests/qtest/cxl-test.c | 84 +++--- 1 file changed, 46 insertions(+), 38 deletions(-) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 61f25a72b6..eda2e6 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -8,50 +8,58 @@ #include "qemu/osdep.h" #include "libqtest-single.h" -#define QEMU_PXB_CMD "-machine q35,cxl=on " \ - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G " +#define QEMU_PXB_CMD \ +"-machine q35,cxl=on " \ +"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ +"-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G " -#define QEMU_2PXB_CMD "-machine q35,cxl=on "\ - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ - "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " +#define QEMU_2PXB_CMD \ +"-machine q35,cxl=on " \ +"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ +"-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ +"-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " -#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " +#define QEMU_RP \ +"-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " /* Dual ports on first pxb */ -#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " +#define QEMU_2RP \ +"-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ +"-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " /* Dual ports on each of the pxb instances */ -#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \ - "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \ - "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 " - -#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " - -#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "\ - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ - "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "\ - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " - -#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ - "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "\ - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \ - "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M "\ - "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \ - "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M "\ - "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \ - "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 " +#define QEMU_4RP \ +"-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ +"-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \ +"-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \ +"-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 " + +#define QEMU_T3D \ +"-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ +"-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ +"-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " + +#define QEMU_2T3D \ +"-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ +"-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ +"-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ +"-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \ +"-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \ +"-devic
[PATCH v2 0/2] hw/mem: CXL Type-3 Volatile Memory Support
v2: - Fix an off by one in address space matching when both volatile and persistent memory is in present (meant 1st byte of persistent memory not readale) - Picked up tags (thanks to all who tested!) Based on following series (in order) 1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream 2. [PATCH v4 0/8] hw/cxl: RAS error emulation and injection 3. [PATCH 0/2] hw/cxl: Passthrough HDM decoder emulation Based on: Message-Id: 20230206172816.8201-1-jonathan.came...@huawei.com Based-on: Message-id: 20230217172924.25239-1-jonathan.came...@huawei.com Based-on: Message-id: 20230125152703.9928-1-jonathan.came...@huawei.com Kernel code is queued up in kernel.org cxl/pending. Now we have some kernel code to test this against (and it looks good) I'd like to propose this series for upstream following 3 other series already proposed for inclusion: Original cover letter with minor updates. This patches provides 2 features to the CXL Type-3 Device: 1) Volatile Memory Region Support 2) Multi-Region support (1 Volatile, 1 Persistent) Summary of Changes per-commit: 1) Whitespace updates to docs and tests 2) Refactor CDAT DSMAS Initialization for multi-region initialization Multi-Region and Volatile Memory support for CXL Type-3 Devices Test and Documentation updates The final patch in this series makes 6 major changes to the type-3 device in order to implement multi-region and volatile region support 1) The HostMemoryBackend [hostmem] has been replaced by two [hostvmem] and [hostpmem] to store volatile and persistent memory respectively 2) The single AddressSpace has been replaced by two AddressSpaces [hostvmem_as] and [hostpmem_as] to map respective memdevs. 3) Each memory region size and total region are stored separately 4) The CDAT and DVSEC memory map entries have been updated: a) if vmem is present, vmem is mapped at DPA(0) b) if pmem is present i) and vmem is present, pmem is mapped at DPA(vmem->size) ii) else, pmem is mapped at DPA(0) c) partitioning of pmem is not supported in this patch set but has been discussed and this design should suffice. 5) Read/Write functions have been updated to access AddressSpaces according to the mapping described in #4. Access to the persistent address space is calculated by (dpa-vmem_len) 6) cxl-mailbox has been updated to report the respective size of volatile and persistent memory region Gregory Price (2): tests/qtest/cxl-test: whitespace, line ending cleanup hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) docs/system/devices/cxl.rst| 49 -- hw/cxl/cxl-mailbox-utils.c | 26 +-- hw/mem/cxl_type3.c | 300 + include/hw/cxl/cxl_device.h| 11 +- tests/qtest/bios-tables-test.c | 8 +- tests/qtest/cxl-test.c | 146 +++- 6 files changed, 398 insertions(+), 142 deletions(-) -- 2.37.2
[PULL 1/9] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
From: Daniel Henrique Barboza
Next patch will move all calls to riscv_load_initrd() to
riscv_load_kernel(). Machines that want to load initrd will be able to
do via an extra flag to riscv_load_kernel().
This change will expose a sign-extend behavior that is happening in
load_elf_ram_sym() when running 32 bit guests [1]. This is currently
obscured by the fact that riscv_load_initrd() is using the return of
riscv_load_kernel(), defined as target_ulong, and this return type will
crop the higher 32 bits that would be padded with 1s by the sign
extension when running in 32 bit targets. The changes to be done will
force riscv_load_initrd() to use an uint64_t instead, exposing it to the
padding when dealing with 32 bit CPUs.
There is a discussion about whether load_elf_ram_sym() should or should
not sign extend the value returned by 'lowaddr'. What we can do is to
prevent the behavior change that the next patch will end up doing.
riscv_load_initrd() wasn't dealing with 64 bit kernel entries when
running 32 bit CPUs, and we want to keep it that way.
One way of doing it is to use target_ulong in 'kernel_entry' in
riscv_load_kernel() and rely on the fact that this var will not be sign
extended for 32 bit targets. Another way is to explictly clear the
higher 32 bits when running 32 bit CPUs for all possibilities of
kernel_entry.
We opted for the later. This will allow us to be clear about the design
choices made in the function, while also allowing us to add a small
comment about what load_elf_ram_sym() is doing. With this change, the
consolation patch can do its job without worrying about unintended
behavioral changes.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-Id: <20230206140022.2748401-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c| 20 +---
hw/riscv/microchip_pfsoc.c | 3 ++-
hw/riscv/opentitan.c | 3 ++-
hw/riscv/sifive_e.c| 3 ++-
hw/riscv/sifive_u.c| 3 ++-
hw/riscv/spike.c | 3 ++-
hw/riscv/virt.c| 3 ++-
include/hw/riscv/boot.h| 1 +
8 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index c7e0e50bd8..df6b4a1fba 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -174,6 +174,7 @@ target_ulong riscv_load_firmware(const char
*firmware_filename,
}
target_ulong riscv_load_kernel(MachineState *machine,
+ RISCVHartArrayState *harts,
target_ulong kernel_start_addr,
symbol_fn_t sym_cb)
{
@@ -192,21 +193,34 @@ target_ulong riscv_load_kernel(MachineState *machine,
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
NULL, &kernel_load_base, NULL, NULL, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
-return kernel_load_base;
+kernel_entry = kernel_load_base;
+goto out;
}
if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
NULL, NULL, NULL) > 0) {
-return kernel_entry;
+goto out;
}
if (load_image_targphys_as(kernel_filename, kernel_start_addr,
current_machine->ram_size, NULL) > 0) {
-return kernel_start_addr;
+kernel_entry = kernel_start_addr;
+goto out;
}
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
+
+out:
+/*
+ * For 32 bit CPUs 'kernel_entry' can be sign-extended by
+ * load_elf_ram_sym().
+ */
+if (riscv_is_32bit(harts)) {
+kernel_entry = extract64(kernel_entry, 0, 32);
+}
+
+return kernel_entry;
}
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 2b91e49561..712625d2a4 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState
*machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
-kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
+kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
+ kernel_start_addr, NULL);
if (machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 353f030d80..7fe4fb5628 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
-riscv_load_kernel(machine, memm
[PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf
From: LIU Zhiwei
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Frank Chang
Message-ID: <20230213094550.29621-1-zhiwei_...@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 00de879787..3073c54871 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
-static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
@@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
-static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
--
2.39.0
[PULL 0/9] Fourth RISC-V PR for QEMU 8.0
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6: tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09 11:23:53 +) are available in the Git repository at: https://github.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230217 for you to fetch changes up to e8c0697d79ef05aa5aefb1121dfede5986b4: target/riscv: Fix vslide1up.vf and vslide1down.vf (2023-02-16 08:10:40 -0800) Fourth RISC-V PR for QEMU 8.0 * A triplet of cleanups to the kernel/initrd loader that avoids duplication between the various boards. * OpenSBI has been updated to version 1.2. * Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as reviewers. Thanks for the help! * A fix for PMP matching to avoid incorrectly appling the default permissions on PMP permission violations. * A cleanup to avoid an unnecessary avoid env_archcpu() in cpu_get_tb_cpu_state(). * Fixes for the vector slide instructions to avoid truncating 64-bit values (such as doubles) on 32-bit targets. Alistair is going to be out for a bit, so I'm going to pick up the pull requests for a bit until he's back online. It's been a while so apologies in advance if anything has gone off the rails, the only thing I know of is that I moved to a Yubikey a while ago so there's likely some new subkeys involved in the signing here. This is all passing my standard tests (make check along with a handful of Linux boots), both on its own and when merge into master from this morning. There has been some flakiness in both of those for a while now, but it doesn't appear to be anything new here (and I think might just be flaky infrastructure on my end). Alistair Francis (1): MAINTAINERS: Add some RISC-V reviewers Bin Meng (1): roms/opensbi: Upgrade from v1.1 to v1.2 Daniel Henrique Barboza (4): hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Frank Chang (1): target/riscv: Remove privileged spec version restriction for RVV Himanshu Chauhan (1): target/riscv: Smepmp: Skip applying default rules when address matches LIU Zhiwei (1): target/riscv: Fix vslide1up.vf and vslide1down.vf MAINTAINERS| 3 + hw/riscv/boot.c| 97 - hw/riscv/microchip_pfsoc.c | 12 +-- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_e.c| 4 +- hw/riscv/sifive_u.c| 12 +-- hw/riscv/spike.c | 14 +--- hw/riscv/virt.c| 12 +-- include/hw/riscv/boot.h| 3 +- pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 117704 -> 123072 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 115344 -> 121800 bytes roms/opensbi | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 21 ++ target/riscv/pmp.c | 9 ++- target/riscv/vector_helper.c | 4 +- 17 files changed, 99 insertions(+), 102 deletions(-)
[PULL 5/9] target/riscv: Remove privileged spec version restriction for RVV
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.
This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.
Signed-off-by: Frank Chang
Reviewed-by: Bin Meng
Reviewed-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-Id: <20230208063209.27279-1-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 21 +++--
2 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..93b52b826c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -73,7 +73,7 @@ struct isa_ext_data {
*/
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
-ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
+ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0,
ext_zihintpause),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fa17d7770c..1b0a0c1693 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm},
[CSR_FCSR] = { "fcsr", fs, read_fcsr,write_fcsr },
/* Vector CSRs */
-[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VL] = { "vl", vs, read_vl,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VTYPE]= { "vtype",vs, read_vtype,
- .min_priv_ver = PRIV_VERSION_1_12_0},
-[CSR_VLENB]= { "vlenb",vs, read_vlenb,
- .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
+[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat },
+[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm },
+[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr },
+[CSR_VL] = { "vl", vs, read_vl},
+[CSR_VTYPE]= { "vtype",vs, read_vtype },
+[CSR_VLENB]= { "vlenb",vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE]= { "cycle",ctr,read_hpmcounter },
[CSR_INSTRET] = { "instret", ctr,read_hpmcounter },
--
2.39.0
[PULL 8/9] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
From: Daniel Henrique Barboza We have a RISCVCPU *cpu pointer available at the start of the function. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Weiwei Li Message-ID: <20230210123836.506286-1-dbarb...@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ad8d82662c..3a9472a2ff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -60,7 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, * which is not supported by GVEC. So we set vl_eq_vlmax flag to true * only when maxsz >= 8 bytes. */ -uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); +uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); uint32_t maxsz = vlmax << sew; bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && -- 2.39.0
[PULL 2/9] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
From: Daniel Henrique Barboza
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. To not change the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.
Cc: Palmer Dabbelt
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230206140022.2748401-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c| 11 +++
hw/riscv/microchip_pfsoc.c | 11 +--
hw/riscv/opentitan.c | 3 ++-
hw/riscv/sifive_e.c| 3 ++-
hw/riscv/sifive_u.c| 11 +--
hw/riscv/spike.c | 11 +--
hw/riscv/virt.c| 11 +--
include/hw/riscv/boot.h| 1 +
8 files changed, 20 insertions(+), 42 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index df6b4a1fba..4954bb9d4b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -176,10 +176,12 @@ target_ulong riscv_load_firmware(const char
*firmware_filename,
target_ulong riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts,
target_ulong kernel_start_addr,
+ bool load_initrd,
symbol_fn_t sym_cb)
{
const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry;
+void *fdt = machine->fdt;
g_assert(kernel_filename != NULL);
@@ -220,6 +222,15 @@ out:
kernel_entry = extract64(kernel_entry, 0, 32);
}
+if (load_initrd && machine->initrd_filename) {
+riscv_load_initrd(machine, kernel_entry);
+}
+
+if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
+qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+machine->kernel_cmdline);
+}
+
return kernel_entry;
}
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 712625d2a4..e81bbd12df 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -630,16 +630,7 @@ static void microchip_icicle_kit_machine_init(MachineState
*machine)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
- kernel_start_addr, NULL);
-
-if (machine->initrd_filename) {
-riscv_load_initrd(machine, kernel_entry);
-}
-
-if (machine->kernel_cmdline && *machine->kernel_cmdline) {
-qemu_fdt_setprop_string(machine->fdt, "/chosen",
-"bootargs", machine->kernel_cmdline);
-}
+ kernel_start_addr, true, NULL);
/* Compute the fdt load address in dram */
fdt_load_addr =
riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 7fe4fb5628..b06944d382 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -102,7 +102,8 @@ static void opentitan_board_init(MachineState *machine)
if (machine->kernel_filename) {
riscv_load_kernel(machine, &s->soc.cpus,
- memmap[IBEX_DEV_RAM].base, NULL);
+ memmap[IBEX_DEV_RAM].base,
+ false, NULL);
}
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1a7d381514..04939b60c3 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -115,7 +115,8 @@ static void sifive_e_machine_init(MachineState *machine)
if (machine->kernel_filename) {
riscv_load_kernel(machine, &s->soc.cpus,
- memmap[SIFIVE_E_DEV_DTIM].base, NULL);
+ memmap[SIFIVE_E_DEV_DTIM].base,
+ false, NULL);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 71be442a50..ad3bb35b34 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -599,16 +599,7 @@ static void sifive_u_machine_init(MachineState *machine)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
- kernel_start_addr, NULL);
-
-if (machine->initrd_filename) {
-riscv_load_initrd(machine, kernel_entry);
-}
-
-if (machine->kernel_cmdline && *machine->kernel_cmdline) {
-qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
-machine->kernel_cmdline);
-}
[PULL 6/9] MAINTAINERS: Add some RISC-V reviewers
From: Alistair Francis This patch adds some active RISC-V members as reviewers to the MAINTAINERS file. Signed-off-by: Alistair Francis Acked-by: LIU Zhiwei Acked-by: Weiwei Li Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Message-Id: <20230209003308.738237-1-alistair.fran...@opensource.wdc.com> Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 96e25f62ac..847bc7f131 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -287,6 +287,9 @@ RISC-V TCG CPUs M: Palmer Dabbelt M: Alistair Francis M: Bin Meng +R: Weiwei Li +R: Daniel Henrique Barboza +R: Liu Zhiwei L: qemu-ri...@nongnu.org S: Supported F: target/riscv/ -- 2.39.0
[PULL 3/9] hw/riscv/boot.c: make riscv_load_initrd() static
From: Daniel Henrique Barboza
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20230206140022.2748401-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 80 -
include/hw/riscv/boot.h | 1 -
2 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 4954bb9d4b..52bf8e67de 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char
*firmware_filename,
exit(1);
}
+static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+{
+const char *filename = machine->initrd_filename;
+uint64_t mem_size = machine->ram_size;
+void *fdt = machine->fdt;
+hwaddr start, end;
+ssize_t size;
+
+g_assert(filename != NULL);
+
+/*
+ * We want to put the initrd far enough into RAM that when the
+ * kernel is uncompressed it will not clobber the initrd. However
+ * on boards without much RAM we must ensure that we still leave
+ * enough room for a decent sized initrd, and on boards with large
+ * amounts of RAM we must avoid the initrd being so far up in RAM
+ * that it is outside lowmem and inaccessible to the kernel.
+ * So for boards with less than 256MB of RAM we put the initrd
+ * halfway into RAM, and for boards with 256MB of RAM or more we put
+ * the initrd at 128MB.
+ */
+start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+
+size = load_ramdisk(filename, start, mem_size - start);
+if (size == -1) {
+size = load_image_targphys(filename, start, mem_size - start);
+if (size == -1) {
+error_report("could not load ramdisk '%s'", filename);
+exit(1);
+}
+}
+
+/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+if (fdt) {
+end = start + size;
+qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+}
+}
+
target_ulong riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts,
target_ulong kernel_start_addr,
@@ -234,46 +274,6 @@ out:
return kernel_entry;
}
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-{
-const char *filename = machine->initrd_filename;
-uint64_t mem_size = machine->ram_size;
-void *fdt = machine->fdt;
-hwaddr start, end;
-ssize_t size;
-
-g_assert(filename != NULL);
-
-/*
- * We want to put the initrd far enough into RAM that when the
- * kernel is uncompressed it will not clobber the initrd. However
- * on boards without much RAM we must ensure that we still leave
- * enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
- */
-start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
-
-size = load_ramdisk(filename, start, mem_size - start);
-if (size == -1) {
-size = load_image_targphys(filename, start, mem_size - start);
-if (size == -1) {
-error_report("could not load ramdisk '%s'", filename);
-exit(1);
-}
-}
-
-/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-if (fdt) {
-end = start + size;
-qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-}
-}
-
/*
* This function makes an assumption that the DRAM interval
* 'dram_base' + 'dram_size' is contiguous.
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index ea1de8b020..a2e4ae9cb0 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
bool load_initrd,
symbol_fn_t sym_cb);
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
MachineState *ms);
void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
--
2.39.0
[PULL 7/9] target/riscv: Smepmp: Skip applying default rules when address matches
From: Himanshu Chauhan
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch skips applying default rules when matching address range
is found. It returns the index of the match PMP entry.
Fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb)
Signed-off-by: Himanshu Chauhan
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-Id: <20230209055206.229392-1-hchau...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d1126a6066..4bc4113531 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -441,9 +441,12 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
}
}
-if ((privs & *allowed_privs) == privs) {
-ret = i;
-}
+/*
+ * If matching address range was found, the protection bits
+ * defined with PMP must be used. We shouldn't fallback on
+ * finding default privileges.
+ */
+ret = i;
break;
}
}
--
2.39.0
Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
On 2/17/23 13:10, Ivan Klokov wrote:
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Ivan Klokov
---
Reviewed-by: Daniel Henrique Barboza
v2:
- added fixes line
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..544558 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
Re: [RFC PATCH] docs/about/deprecated: Deprecate 32-bit host systems
(Cc'ing Huacai & Jiaxun).
On 17/2/23 17:38, Paolo Bonzini wrote:
On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
I feel the discussion petered out without a conclusion.
I don't think letting the status quo win by inertia is a good outcome
here.
Which 32-bit hosts are still useful, and why?
Which 32-bit hosts does Linux still provide KVM support for.
All except ARM: MIPS, x86, PPC and RISC-V.
I would like to remove x86, but encountered some objections.
MIPS, nobody is really using it I think.
32-bit was added in 2014, commit 222e7d11e7 ("target-mips: Enable KVM
support in build system"). I'm not aware of anybody using it (even
testing it). I don't have hardware to test it (neither time).
We are still cross-compiling it although.
64-bit support was added recently (see commit aa2953fd16 "configure:
Add KVM target support for MIPS64") and is used (see commit fbc5884ce2
"meson.build: Re-enable KVM support for MIPS" from 2020), however I
tend to see it more as hobbyist use than production one. Besides it
is listed as 'Odd Fixes' in MAINTAINERS (still 2020, commit 134f7f7da1
"MAINTAINERS: Reactivate MIPS KVM CPUs").
So that leaves PPC and RISC-V.
If any, is there an EOL date for Linux 32-bit KVM support ?
No, and I don't think there's going to be one.
Paolo
Re: [PATCH v3 06/11] bsd-user: Helper routines h2g_old_sysctl
On 2/16/23 13:33, Warner Losh wrote:
h2g_old_sysctl does the byte swapping in the data to return it to the
target for the 'well known' types. For most of the types, either the
data is returned verbatim (strings, byte size, opaque we don't know
about) or it's returned with byte swapping (for all the integer
types). However, for ABI32 targets, LONG and ULONG are different sizes,
and need to be carefully converted (along with help from the caller).
Co-Authored-by: Sean Bruno
Signed-off-by: Sean Bruno
Co-Authored-by: Juergen Lock
Signed-off-by: Juergen Lock
Co-Authored-by: Raphael Kubo da Costa
Signed-off-by: Raphael Kubo da Costa
Co-Authored-by: Stacey Son
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 100 --
1 file changed, 96 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
+}
+else {
+#ifdef TARGET_ABI32
} else {
r~
Re: [PATCH v3 04/11] bsd-user: various helper routines for sysctl
On 2/16/23 13:33, Warner Losh wrote: cap_memory - Caps the memory to just below MAXINT scale_to_guest_pages - Account for difference in host / guest page size h2g_long_sat - converts a int64_t to a int32_t, saturating at max / min values h2g_ulong_sat - converts a uint64_t to a uint32_t, saturating at max value Signed-off-by: Warner Losh --- bsd-user/freebsd/os-sys.c | 86 +++ 1 file changed, 86 insertions(+) Reviewed-by: Richard Henderson r~
[PATCH v4 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.
Note:
- Header content needs to be manually specified in a fashion that
matches the specification for what can be in the header for each
error type.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header":
[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Signed-off-by: Jonathan Cameron
---
v4:
- Improved QMP help text wth more detail (following request in review
of the Poison injection series)
---
hw/cxl/cxl-component-utils.c | 4 +-
hw/mem/cxl_type3.c | 281 +
hw/mem/cxl_type3_stubs.c | 10 ++
hw/mem/meson.build | 2 +
include/hw/cxl/cxl_component.h | 26 +++
include/hw/cxl/cxl_device.h| 11 ++
qapi/cxl.json | 118 ++
qapi/meson.build | 1 +
qapi/qapi-schema.json | 1 +
9 files changed, 453 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 737b4764b9..b665d4f565 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -142,16 +142,18 @@ static void ras_init_common(uint32_t *reg_state, uint32_t
*write_msk)
* be handled as RO.
*/
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
+stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
+stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
/* CXL switches and devices must set */
-stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00);
+stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
}
static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 6cdd988d1d..e32bbac966 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
+#include "qapi/qapi-commands-cxl.h"
#include "hw/mem/memory-device.h"
#include "hw/mem/pc-dimm.h"
#include "hw/pci/pci.h"
@@ -323,6 +324,66 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int
which)
ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
}
+static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
+{
+switch (qmp_err) {
+case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_DATA_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_ADDRESS_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_BE_PARITY:
+return CXL_RAS_UNC_ERR_CACHE_BE_PARITY;
+case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_ECC:
+return CXL_RAS_UNC_ERR_CACHE_DATA_ECC;
+case CXL_UNCOR_ERROR_TYPE_MEM_DATA_PARITY:
+return CXL_RAS_UNC_ERR_MEM_DATA_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_ADDRESS_PARITY:
+return CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_BE_PARITY:
+return CXL_RAS_UNC_ERR_MEM_BE_PARITY;
+case CXL_UNCOR_ERROR_TYPE_MEM_DATA_ECC:
+return CXL_RAS_UNC_ERR_MEM_DATA_ECC;
+case CXL_UNCOR_ERROR_TYPE_REINIT_THRESHOLD:
+return CXL_RAS_UNC_ERR_REINIT_THRESHOLD;
+case CXL_UNCOR_ERROR_TYPE_RSVD_ENCODING:
+return CXL_RAS_UNC_ERR_RSVD_ENCODING;
+case CXL_UNCOR_ERROR_TYPE_POISON_RECEIVED:
+return CXL_RAS_UNC_ERR_POISON_RECEIVED;
+case CXL_UNCOR_ERROR_TYPE_RECEIVER_OVERFLOW:
+return CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW;
+case CXL_UNCOR_ERROR_TYPE_INTERNAL:
+return CXL_RAS_UNC_ERR_INTERNAL;
+case CXL_UNCOR_ERROR_TYPE_CXL_IDE_TX:
+r
