Re: [Qemu-devel] [PATCH 07/29] ds1338: use QEMU_IS_ALIGNED macro
I'm not sure this makes sense - we're dealing with time here.
--
Alastair D'Silva mob: 0423 762 819
skype: alastair_dsilva msn: alast...@d-silva.org
blog: http://alastair.d-silva.orgTwitter: @EvilDeece
> -Original Message-
> From: Philippe Mathieu-Daudé [mailto:philippe.mathieu.da...@gmail.com]
> On Behalf Of Philippe Mathieu-Daudé
> Sent: Tuesday, 18 July 2017 4:10 PM
> To: qemu-triv...@nongnu.org; Peter Maydell <peter.mayd...@linaro.org>;
> Alastair D'Silva <alast...@d-silva.org>; Corey Minyard
> <cminy...@mvista.com>
> Cc: Philippe Mathieu-Daudé <f4...@amsat.org>; qemu-devel@nongnu.org;
> Eric Blake <ebl...@redhat.com>
> Subject: [PATCH 07/29] ds1338: use QEMU_IS_ALIGNED macro
>
> Applied using the Coccinelle semantic patch
> scripts/coccinelle/use_osdep.cocci
>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
> hw/timer/ds1338.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c index
> 3849b74a68..a77fe14514 100644
> --- a/hw/timer/ds1338.c
> +++ b/hw/timer/ds1338.c
> @@ -65,7 +65,7 @@ static void capture_current_time(DS1338State *s)
> s->nvram[1] = to_bcd(now.tm_min);
> if (s->nvram[2] & HOURS_12) {
> int tmp = now.tm_hour;
> -if (tmp % 12 == 0) {
> +if (QEMU_IS_ALIGNED(tmp, 12)) {
> tmp += 12;
> }
> if (tmp <= 12) {
> @@ -154,7 +154,7 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data)
> if (data & HOURS_PM) {
> tmp += 12;
> }
> -if (tmp % 12 == 0) {
> +if (QEMU_IS_ALIGNED(tmp, 12)) {
> tmp -= 12;
> }
> now.tm_hour = tmp;
> --
> 2.13.2
>
>
> ---
> This email has been checked for viruses by AVG.
> http://www.avg.com
[Qemu-devel] [PATCH v5 7/7] arm: Add an RX8900 RTC to the ASpeed board
From: Alastair D'Silva <alast...@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
hw/arm/aspeed.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 40c1383..ef63fd0 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -26,6 +26,12 @@ static struct arm_boot_info aspeed_board_binfo = {
.nb_cpus = 1,
};
+typedef struct AspeedI2CDevice {
+const char *type;
+uint8_t address;
+int bus;
+} AspeedI2CDevice;
+
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
@@ -37,6 +43,7 @@ typedef struct AspeedBoardConfig {
const char *fmc_model;
const char *spi_model;
uint32_t num_cs;
+const AspeedI2CDevice *i2c_devices;
} AspeedBoardConfig;
enum {
@@ -80,6 +87,11 @@ enum {
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
+
+static const AspeedI2CDevice ast2500_i2c_devices[] = {
+{"rx8900", 0x32, 11}
+};
+
static const AspeedBoardConfig aspeed_boards[] = {
[PALMETTO_BMC] = {
.soc_name = "ast2400-a1",
@@ -94,6 +106,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
.fmc_model = "n25q256a",
.spi_model = "mx25l25635e",
.num_cs= 1,
+.i2c_devices = ast2500_i2c_devices,
},
[ROMULUS_BMC] = {
.soc_name = "ast2500-a1",
@@ -104,6 +117,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
},
};
+
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Error **errp)
{
@@ -130,6 +144,19 @@ static void aspeed_board_init_flashes(AspeedSMCState *s,
const char *flashtype,
}
}
+static void aspeed_i2c_init(AspeedBoardState *bmc,
+const AspeedBoardConfig *cfg)
+{
+AspeedSoCState *soc = >soc;
+const AspeedI2CDevice *dev;
+
+for (dev = cfg->i2c_devices; dev != NULL && dev->type != NULL; dev++) {
+I2CBus *i2c_bus = aspeed_i2c_get_bus((DeviceState *)>i2c,
+ dev->bus);
+(void)i2c_create_slave(i2c_bus, dev->type, dev->address);
+}
+}
+
static void aspeed_board_init(MachineState *machine,
const AspeedBoardConfig *cfg)
{
@@ -174,6 +201,8 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+aspeed_i2c_init(bmc, cfg);
+
arm_load_kernel(ARM_CPU(first_cpu), _board_binfo);
}
--
2.9.3
[Qemu-devel] [PATCH v5 6/7] tests: Test all implemented RX8900 functionality
From: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
tests/Makefile.include | 2 +
tests/rx8900-test.c| 880 +
2 files changed, 882 insertions(+)
create mode 100644 tests/rx8900-test.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 4841d58..04815be 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -301,6 +301,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/rx8900-test$(EXESUF)
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
@@ -639,6 +640,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y)
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
new file mode 100644
index 000..0c9e568
--- /dev/null
+++ b/tests/rx8900-test.c
@@ -0,0 +1,880 @@
+/*
+ * QTest testcase for the Epson RX8900SA/CE RTC
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/rx8900_regs.h"
+#include "libqtest.h"
+#include "libqos/i2c.h"
+#include "qemu/timer.h"
+
+#define IMX25_I2C_0_BASE 0x43F8
+#define RX8900_TEST_ID "rx8900-test"
+#define RX8900_ADDR 0x32
+#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
+#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
+#define RX8900_FOUT "rx8900-fout"
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+return (x & 0x0f) + (x >> 4) * 10;
+}
+
+static inline uint8_t bin2bcd(uint8_t x)
+{
+return (x / 10 << 4) | (x % 10);
+}
+
+static void qmp_rx8900_set_temperature(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'temperature', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+static void qmp_rx8900_set_voltage(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'voltage', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+/**
+ * Read an RX8900 register
+ * @param reg the address of the register
+ * @return the value of the register
+ */
+static uint8_t read_register(RX8900Addresses reg)
+{
+uint8_t val;
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, , 1);
+
+return val;
+}
+
+/**
+ * Write to an RX8900 register
+ * @param reg the address of the register
+ * @param val the value to write
+ */
+static uint8_t write_register(RX8900Addresses reg, uint8_t val)
+{
+uint8_t buf[2];
+
+buf[0] = reg;
+buf[1] = val;
+
+i2c_send(i2c, addr, buf, 2);
+
+return val;
+}
+
+/**
+ * Set bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void set_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value |= mask;
+write_register(reg, value);
+}
+
+/**
+ * Clear bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value &= ~mask;
+write_register(reg, value);
+}
+
+/**
+ * Read a number of sequential RX8900 registers
+ * @param reg the address of the first register
+ * @param buf (out) an output buffer to stash the register values
+ * @param count the number of registers to read
+ */
+static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count)
+{
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, buf, count);
+}
+
+/**
+ * Write to a sequential number of RX8900 registers
+ * @param reg the address of the first reg
[Qemu-devel] [PATCH v5 3/7] qtest: Support setting named GPIOs
From: Alastair D'Silva <alast...@d-silva.org>
Some devices change their behaviour based on the state of their input GPIO
lines.
This patch allows testing of the variable behaviour by providing facilities
for the test to set the state of these GPIO lines.
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
qtest.c | 42 ++
tests/libqtest.c | 7 +++
tests/libqtest.h | 29 +
3 files changed, 78 insertions(+)
diff --git a/qtest.c b/qtest.c
index ad7e215..a947892 100644
--- a/qtest.c
+++ b/qtest.c
@@ -165,6 +165,11 @@ static bool qtest_opened;
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -344,6 +349,43 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+} else if (strcmp(words[0], "irq_set") == 0) {
+DeviceState *dev;
+NamedGPIOList *ngl;
+int level;
+qemu_irq irq = NULL;
+int irq_num;
+
+g_assert(words[1]); /* device */
+g_assert(words[2]); /* gpio list */
+g_assert(words[3]); /* gpio line in list */
+g_assert(words[4]); /* level */
+dev = DEVICE(object_resolve_path(words[1], NULL));
+if (!dev) {
+qtest_send_prefix(chr);
+qtest_send(chr, "FAIL Unknown device\n");
+return;
+}
+
+irq_num = atoi(words[3]);
+level = atoi(words[4]);
+
+QLIST_FOREACH(ngl, >gpios, node) {
+if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) {
+irq = ngl->in[irq_num];
+}
+}
+
+if (irq == NULL) {
+qtest_send_prefix(chr);
+qtest_send(chr, "FAIL Unknown IRQ\n");
+return;
+}
+
+qemu_set_irq(irq, level);
+
+qtest_send_prefix(chr);
+qtest_send(chr, "OK\n");
} else if (strcmp(words[0], "outb") == 0 ||
strcmp(words[0], "outw") == 0 ||
strcmp(words[0], "outl") == 0) {
diff --git a/tests/libqtest.c b/tests/libqtest.c
index a433c3b..a7cdd3b 100644
--- a/tests/libqtest.c
+++ b/tests/libqtest.c
@@ -988,3 +988,10 @@ bool qtest_big_endian(QTestState *s)
{
return s->big_endian;
}
+
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+bool level)
+{
+qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level);
+qtest_rsp(s, 0);
+}
diff --git a/tests/libqtest.h b/tests/libqtest.h
index 99b14b1..3063bc9 100644
--- a/tests/libqtest.h
+++ b/tests/libqtest.h
@@ -190,6 +190,20 @@ void qtest_irq_attach(QTestState *s, const char *name, int
irq,
void *opaque);
/**
+ * qtest_irq_set:
+ * Set an interrupt level
+ * @s: #QTestState instance to operate on.
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the IRQ
+ * @n: the GPIO within the list
+ * @level: the IRQ level
+ *
+ * Set an interrupt to a nominated level
+ */
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+bool level);
+
+/**
* qtest_outb:
* @s: #QTestState instance to operate on.
* @addr: I/O port to write to.
@@ -656,6 +670,21 @@ static inline void irq_attach(const char *name, int irq,
}
/**
+ * qtest_irq_set
+ * Set an interrupt level
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the line to seh
+ * @n: the line to set within the list
+ * @level: the IRQ level
+ */
+static inline void irq_set(const char *id, const char *gpiolist, int n,
+bool level)
+{
+qtest_irq_set(global_qtest, id, gpiolist, n, level);
+}
+
+
+/**
* outb:
* @addr: I/O port to write to.
* @value: Value being written.
--
2.9.3
[Qemu-devel] [PATCH v5 5/7] hw/timer: Add Epson RX8900 RTC support
From: Alastair D'Silva <alast...@d-silva.org>
This patch adds support for the Epson RX8900 I2C RTC.
The following chip features are implemented:
- RTC (wallclock based, ptimer 10x oversampling to pick up
wallclock transitions)
- Time update interrupt (per second/minute, wallclock based)
- Alarms (wallclock based)
- Temperature (set via a property)
- Countdown timer (emulated clock via ptimer)
- FOUT via GPIO (emulated clock via ptimer)
The following chip features are unimplemented:
- Low voltage detection
- i2c timeout
The implementation exports the following named GPIOs:
rx8900-interrupt-out
rx8900-fout-enable
rx8900-fout
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 914
hw/timer/rx8900_regs.h | 141 +++
hw/timer/trace-events | 31 ++
5 files changed, 1089 insertions(+)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 000..146603e
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,914 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ * Chris Smart <ch...@distroguy.com>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE=en
+ *
+ * Not implemented:
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "trace.h"
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+typedef struct RX8900State {
+I2CSlave parent_obj;
+
+ptimer_state *sec_timer; /* triggered once per second */
+ptimer_state *fout_timer;
+ptimer_state *countdown_timer;
+bool fout_state;
+int64_t offset;
+#define INVALID_WEEKDAY 0xff
+uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+uint8_t wday_offset;
+uint8_t nvram[RX8900_NVRAM_SIZE];
+int32_t nvram_offset; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+bool addr_byte;
+uint8_t last_interrupt_seconds; /* The last time the second timer ticked */
+/* the last minute the timer update interrupt was triggered (if enabled) */
+uint8_t last_update_interrupt_minutes;
+double supply_voltage;
+qemu_irq interrupt_pin;
+qemu_irq fout_pin;
+struct tm now;
+bool time_altered; /* True if this transaction altered the time */
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+.name = "rx8900",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+VMSTATE_PTIMER(sec_timer, RX8900State),
+VMSTATE_PTIMER(fout_timer, RX8900State),
+VMSTATE_PTIMER(countdown_timer, RX8900State),
+VMSTATE_BOOL(fout_state, RX8900State),
+VMSTATE_INT64(offset, RX8900State),
+VMSTATE_UINT8(weekday, RX8900State),
+VMSTATE_UINT8(wday_offset, RX8900State),
+VMSTATE_UINT8_ARRAY(
[Qemu-devel] [PATCH v5 1/7] arm: Uniquely name imx25 I2C buses.
From: Alastair D'Silva <alast...@d-silva.org> The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely: i2c-bus.0 i2c-bus.1 i2c-bus.2 Signed-off-by: Alastair D'Silva <alast...@d-silva.org> --- hw/arm/imx25_pdk.c | 2 +- hw/i2c/imx_i2c.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 025b608..44e741f 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -139,7 +139,7 @@ static void imx25_pdk_init(MachineState *machine) * of simple qtest. See "make check" for details. */ i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(>soc.i2c[0]), - "i2c"), + "i2c-bus.0"), "ds1338", 0x68); } } diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index 37e5a62..6c81b98 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -310,7 +310,7 @@ static void imx_i2c_realize(DeviceState *dev, Error **errp) IMX_I2C_MEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq); -s->bus = i2c_init_bus(DEVICE(dev), "i2c"); +s->bus = i2c_init_bus(DEVICE(dev), NULL); } static void imx_i2c_class_init(ObjectClass *klass, void *data) -- 2.9.3
[Qemu-devel] [PATCH v5 2/7] qtest: Support named interrupts
From: Alastair D'Silva <alast...@d-silva.org>
The QTest framework cannot check the state of named interrupts. This patch
adds support for them.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/core/irq.c| 18 +++--
include/hw/irq.h | 13 +++---
qtest.c | 57 +
tests/libqtest.c | 78 +---
tests/libqtest.h | 30 ++
5 files changed, 159 insertions(+), 37 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..75f915b 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -134,15 +134,17 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
return qemu_allocate_irqs(proxy_irq_handler, target, n);
}
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
+qemu_irq qemu_irq_dup(qemu_irq in)
{
-int i;
-qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
-for (i = 0; i < n; i++) {
-*old_irqs[i] = *gpio_in[i];
-gpio_in[i]->handler = handler;
-gpio_in[i]->opaque = _irqs[i];
-}
+qemu_irq out = qemu_allocate_irq(in->handler, in->opaque, in->n);
+return out;
+}
+
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque)
+{
+gpio_in->handler = handler;
+gpio_in->opaque = opaque;
}
static const TypeInfo irq_type_info = {
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..2583fd1 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -58,8 +58,15 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
*/
qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-/* For internal use in qtest. Similar to qemu_irq_split, but operating
- on an existing vector of qemu_irq. */
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
+/**
+ * Duplicate an IRQ
+ * @param in the IRQ to deplicate
+ * @return a copy of the IRQ
+ */
+qemu_irq qemu_irq_dup(qemu_irq in);
+
+/* For internal use in qtest. */
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque);
#endif
diff --git a/qtest.c b/qtest.c
index 46b99ae..ad7e215 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,6 +159,8 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED raise NAME NUM
+ * IRQ_NAMED lower NAME NUM
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
@@ -243,17 +244,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend
*chr,
va_end(ap);
}
+typedef struct qtest_irq {
+qemu_irq old_irq;
+char *name;
+bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
-qemu_irq old_irq = *(qemu_irq *)opaque;
-qemu_set_irq(old_irq, level);
+qtest_irq *data = (qtest_irq *)opaque;
+level = !!level;
+
+qemu_set_irq(data->old_irq, level);
-if (irq_levels[n] != level) {
+if (level != data->last_level) {
CharBackend *chr = _chr;
-irq_levels[n] = level;
qtest_send_prefix(chr);
-qtest_sendf(chr, "IRQ %s %d\n",
-level ? "raise" : "lower", n);
+
+if (data->name) {
+qtest_sendf(chr, "IRQ_NAMED %s %s %d\n",
+level ? "raise" : "lower", data->name, n);
+} else {
+qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+}
+
+data->last_level = level;
}
}
@@ -303,23 +318,26 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
}
QLIST_FOREACH(ngl, >gpios, node) {
-/* We don't support intercept of named GPIOs yet */
-if (ngl->name) {
-continue;
-}
if (words[0][14] == 'o') {
int i;
for (i = 0; i < ngl->num_out; ++i) {
-qemu_irq *disconnected = g_new0(qemu_irq, 1);
-qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
- disconnected, i);
+qtest_irq *data = g_new0(qtest_irq, 1);
+data->name = ngl->name;
+qemu_irq icpt = qemu_allocate_irq(qtest_irq_hand
[Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board
From: Alastair D'Silva <alast...@d-silva.org> This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. Support for named interrupts has been implemented in qtest to facilitate testing. Changelog: v5: - Use time functions for time manipulation (note: check-patch incorrectly reports an error on timercmp()) - Refactor weekday validation - Defer time offset calculation until the I2C transaction is complete as partial updates can result in incorrect offsets - Cosmetic changes as requested by Adrew Jeffery v4: - Split overloaded patches - Fix spelling of Celsius - Remove degrees sign from messages - Don't force float precision - Reformat named interrupt qtest protocol for consistency - Minor formatting changes - Don't connect the RX8900 INT line to NVIC:22, it should be connected to GPIOJ10 on the ASPEED SOC v3: - Add range checks for time components - Shorten trace messages - Use qemu generated i2c bus names - Address style comments from Alexey for rx8900 driver - Fix long lines in qtest harness - Remove trailing whitespace in hw/arm/pxa - Remove stray headers from rx8900 driver - Support low voltage detection in rx8900 driver v2: - Avoid using error_report - Fix TIE behaviour - Move temperature init out of reset, it should not change on a soft reset - Fix IRQ in test failures - Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. - Refactor to use the existing qemu trace infrastructure - Move the RX8900 definition into the aspeed machine init - It it possible for check_update_interrupt_seconds in the rx8900 test to return 6, depending on the alignment with the wall clock. - Support low voltage detection Alastair D'Silva (7): arm: Uniquely name imx25 I2C buses. qtest: Support named interrupts qtest: Support setting named GPIOs qtest: Fix whitespace hw/timer: Add Epson RX8900 RTC support tests: Test all implemented RX8900 functionality arm: Add an RX8900 RTC to the ASpeed board default-configs/arm-softmmu.mak | 1 + hw/arm/aspeed.c | 29 ++ hw/arm/imx25_pdk.c | 2 +- hw/core/irq.c | 18 +- hw/i2c/imx_i2c.c| 2 +- hw/timer/Makefile.objs | 2 + hw/timer/rx8900.c | 914 hw/timer/rx8900_regs.h | 141 +++ hw/timer/trace-events | 31 ++ include/hw/irq.h| 13 +- qtest.c | 103 +++-- tests/Makefile.include | 2 + tests/libqtest.c| 85 +++- tests/libqtest.h| 59 +++ tests/rx8900-test.c | 880 ++ 15 files changed, 2241 insertions(+), 41 deletions(-) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c -- 2.9.3
[Qemu-devel] [PATCH v5 4/7] qtest: Fix whitespace
From: Alastair D'Silva <alast...@d-silva.org>
Fix 2 cases of incorrect indentation
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
qtest.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qtest.c b/qtest.c
index a947892..143077e 100644
--- a/qtest.c
+++ b/qtest.c
@@ -309,7 +309,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+return;
}
if (irq_intercept_dev) {
@@ -319,7 +319,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+return;
}
QLIST_FOREACH(ngl, >gpios, node) {
--
2.9.3
Re: [Qemu-devel] [PATCH v4 7/8] tests: Test all implemented RX8900 functionality
On Wed, 2017-01-04 at 16:44 +1030, Andrew Jeffery wrote:
> Hi Alastair,
>
> Again, small comments below.
>
> On Thu, 2016-12-15 at 16:48 +1100, Alastair D'Silva wrote:
> > > From: Alastair D'Silva <alast...@d-silva.org>
> > > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> >
> > ---
> > tests/Makefile.include | 2 +
> > tests/rx8900-test.c| 882
> > +
> > 2 files changed, 884 insertions(+)
> > create mode 100644 tests/rx8900-test.c
> >
> > diff --git a/tests/Makefile.include b/tests/Makefile.include
> > index e98d3b6..e52e355 100644
> > --- a/tests/Makefile.include
> > +++ b/tests/Makefile.include
> > @@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-
> > test$(EXESUF)
> >
> > check-qtest-arm-y = tests/tmp105-test$(EXESUF)
> > check-qtest-arm-y += tests/ds1338-test$(EXESUF)
> > +check-qtest-arm-y += tests/rx8900-test$(EXESUF)
> > check-qtest-arm-y += tests/m25p80-test$(EXESUF)
> > gcov-files-arm-y += hw/misc/tmp105.c
> > check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
> > @@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-
> > tables-test.o \
> > tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o
> > $(libqos-obj-y)
> > tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-
> > y)
> > tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-
> > y)
> > +tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-
> > y)
> > tests/m25p80-test$(EXESUF): tests/m25p80-test.o
> > tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
> > tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
> > diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
> > new file mode 100644
> > index 000..1769659
> > --- /dev/null
> > +++ b/tests/rx8900-test.c
> > @@ -0,0 +1,882 @@
> > +/*
> > + * QTest testcase for the Epson RX8900SA/CE RTC
> > + *
> > + * Copyright (c) 2016 IBM Corporation
> > + * Authors:
> > > + * Alastair D'Silva <alast...@d-silva.org>
> >
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/timer/rx8900_regs.h"
> > +#include "libqtest.h"
> > +#include "libqos/i2c.h"
> > +#include "qemu/timer.h"
> > +
> > +#define IMX25_I2C_0_BASE 0x43F8
> > +#define RX8900_TEST_ID "rx8900-test"
> > +#define RX8900_ADDR 0x32
> > +#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
> > +#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
> > +#define RX8900_FOUT "rx8900-fout"
> > +
> > +static I2CAdapter *i2c;
> > +static uint8_t addr;
> > +
> > +static inline uint8_t bcd2bin(uint8_t x)
> > +{
> > +return (x & 0x0f) + (x >> 4) * 10;
> > +}
> > +
> > +static inline uint8_t bin2bcd(uint8_t x)
> > +{
> > +return (x / 10 << 4) | (x % 10);
> > +}
> > +
> > +static void qmp_rx8900_set_temperature(const char *id, double
> > value)
> > +{
> > +QDict *response;
> > +
> > +response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path':
> > %s, "
> > + "'property': 'temperature', 'value': %f } }",
> > id, value);
> > +g_assert(qdict_haskey(response, "return"));
> > +QDECREF(response);
> > +}
> > +
> > +static void qmp_rx8900_set_voltage(const char *id, double value)
> > +{
> > +QDict *response;
> > +
> > +response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path':
> > %s, "
> > + "'property': 'voltage', 'value': %f } }", id,
> > value);
> > +g_assert(qdict_haskey(response, "return"));
> > +QDECREF(response);
> > +}
> > +
> > +/**
> > + * Read an RX8900 register
> > + * @param reg the address of the register
> > + * @return the value of the register
> > + */
> > +static uint8_t read_register(RX8900Addresses reg)
> > +{
> > +uint8_t val;
> > +uint8_t reg_address = (uint8_t)reg;
> > +
> > +i2c_send(i2c, addr, _address, 1);
> > +i2c_recv(i2c, addr, , 1);
> > +
> > +return val;
> > +}
> > +
> >
Re: [Qemu-devel] [PATCH v4 6/8] hw/timer: Add Epson RX8900 RTC support
On Wed, 2017-01-04 at 15:29 +1030, Andrew Jeffery wrote:
> Hi Alastair,
>
> I have some mostly minor comments below.
Ok, I'm removing Chris from the CC list since he's left the team.
>
> On Thu, 2016-12-15 at 16:48 +1100, Alastair D'Silva wrote:
> > > From: Alastair D'Silva <alast...@d-silva.org>
> >
> > This patch adds support for the Epson RX8900 I2C RTC.
> >
> > The following chip features are implemented:
> > - RTC (wallclock based, ptimer 10x oversampling to pick up
> > wallclock transitions)
> > - Time update interrupt (per second/minute, wallclock based)
> > - Alarms (wallclock based)
> > - Temperature (set via a property)
> > - Countdown timer (emulated clock via ptimer)
> > - FOUT via GPIO (emulated clock via ptimer)
> >
> > The following chip features are unimplemented:
> > - Low voltage detection
> > - i2c timeout
> >
> > The implementation exports the following named GPIOs:
> > rx8900-interrupt-out
> > rx8900-fout-enable
> > rx8900-fout
> >
> > > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > > Signed-off-by: Chris Smart <ch...@distroguy.com>
> >
> > ---
> > default-configs/arm-softmmu.mak | 1 +
> > hw/timer/Makefile.objs | 2 +
> > hw/timer/rx8900.c | 912
> >
> > hw/timer/rx8900_regs.h | 141 +++
> > hw/timer/trace-events | 31 ++
> > 5 files changed, 1087 insertions(+)
> > create mode 100644 hw/timer/rx8900.c
> > create mode 100644 hw/timer/rx8900_regs.h
> >
> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-
> > softmmu.mak
> > index 6de3e16..adb600e 100644
> > --- a/default-configs/arm-softmmu.mak
> > +++ b/default-configs/arm-softmmu.mak
> > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
> > CONFIG_ALLWINNER_EMAC=y
> > CONFIG_IMX_FEC=y
> > CONFIG_DS1338=y
> > +CONFIG_RX8900=y
> > CONFIG_PFLASH_CFI01=y
> > CONFIG_PFLASH_CFI02=y
> > CONFIG_MICRODRIVE=y
> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> > index 7ba8c23..fa028ac 100644
> > --- a/hw/timer/Makefile.objs
> > +++ b/hw/timer/Makefile.objs
> > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
> > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
> > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
> > common-obj-$(CONFIG_DS1338) += ds1338.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> > common-obj-$(CONFIG_HPET) += hpet.o
> > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
> > common-obj-$(CONFIG_M48T59) += m48t59.o
> > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> > common-obj-$(CONFIG_IMX) += imx_gpt.o
> > common-obj-$(CONFIG_LM32) += lm32_timer.o
> > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> >
> > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
> > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
> > new file mode 100644
> > index 000..cb1a2c8
> > --- /dev/null
> > +++ b/hw/timer/rx8900.c
> > @@ -0,0 +1,912 @@
> > +/*
> > + * Epson RX8900SA/CE Realtime Clock Module
> > + *
> > + * Copyright (c) 2016 IBM Corporation
> > + * Authors:
> > > + * Alastair D'Silva <alast...@d-silva.org>
> > > + * Chris Smart <ch...@distroguy.com>
> >
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Datasheet available at:
> > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE
> > =en
> > + *
> > + * Not implemented:
> > + * Implement i2c timeout
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu-common.h"
> > +#include "hw/i2c/i2c.h"
> > +#include "hw/timer/rx8900_regs.h"
> > +#include "hw/ptimer.h"
> > +#include "qemu/main-loop.h"
> > +#include "qemu/bcd.h"
> > +#include "qemu/log.h"
> > +#include "qapi/error.h"
> > +#include "qapi/visitor.h"
> > +#include "trace.h"
> > +
> > +#define TYPE_RX8900 "rx8900"
> > +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
> > +
> > +typedef struct RX8900State {
> > +I2CSlave parent_obj;
> > +
> > +ptim
Re: [Qemu-devel] [PATCH v1 0/2] Add Atmel I2C TPM AT97SC3204T emulated device
On Fri, 2016-12-16 at 17:35 +, Peter Maydell wrote:
> (added a couple of people to cc who might have an opinion on the i2c
> protocol questions below)
I'm certainly no expert, but I'll try :)
> On 29 November 2016 at 19:30, Fabio Urquiza <f...@cesar.org.br>
> wrote:
> >
> > One of the problems we had to address is regarding the behavior of
> > the
> > ATMEL I2C TPM AT97SC3204T Linux driver. After the driver sends a
> > request
> > to the TPM, it keeps polling the device with I2C read request. The
> > real
> > AT97SC3204T hardware ignore those requests while the response is
> > not ready
> > simply by not ACKing the I2C read on its address. When the response
> > is
> > ready it will ACK the request and proceed writing the response in
> > the wire.
> >
> > The QEMU I2C API does not provide a way to not ACK I2C requests
> > when the
> > device is not ready to transmit. In fact, if the device has been
> > configured
> > in the virtual machine, QEMU will automatically ACK every request
> > without
> > asking for the device permission for it. Therefore we created a
> > flag in
> > the I2CSlave struct that tells the I2C subsystem that the device is
> > busy
> > and not ready to ACK a I2C transfer. We understand that it could
> > not be
> > the best solution to the problem, but it appears to be the solution
> > that
> > have the least impact in the code overall. Suggestions on a
> > different
> > approach would be welcome.
>
> I2C slaves definitely ought to be able to NAK I2C requests. This
> is possible for sends, ie data sent from the master to the slave
> (the slave just returns non-zero from its I2CSlaveClass::send
> function).
> In i2c protocol terms, this corresponds to the slave generating a NAK
> (by not taking SDA low) after the master has sent a byte of data.
> The bitbang_i2c code used by versatile was buggy in handling NAKs
> for sends until commit 9706e0162d24.
>
I agree that they should be able to NAK, it seems that this may be the
first device that actually needs that functionality (or at least, has
implemented it).
The change looks about as minimal as one could make it, so I'm mostly
happy with it.
I think we may need to add the busy field to hw/i2c/core.c:
VMStateDescription vmstate_i2c_slave, if this state should be
persisted.
Also, it looks like the busy element is only ever used in a boolean
context, so a boolean type may be more appropriate.
> For recv I'm less sure how it ought to work, so if you can explain
> in terms of the i2c protocol what slave h/w behaviour we're trying
> to emulate that would help. At what points in the protocol can
> the slave return a NAK?
>
> Our current API seems to envisage that the slave can return a
> negative value from I2CSlaveClass::recv instead of a data byte,
> but I'm not sure what this means in the i2c protocol.
Negative values are propagated upwards, where they are treated as
errors, eg, in hw/i2c/aspeed_i2c.c:aspeed_i2c_bus_handle_cmd():
int ret = i2c_recv(bus->bus);
if (ret < 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
ret = 0xff;
}
The call to i2c_recv is too late to issue the NAK, I believe they occur
during the start_transfer() call.
> If I understand your patch correctly, this is adding support
> for the slave refusing to ACK when the master sends out the
> slave address and r/w bit. I think that makes sense, but rather
> than having a state flag in the I2CSlave struct, we should
> change the prototype of the I2CSlaveClass event method so that
> it can return a value indicating ack or nak.
>
Hmm, this could end up being quite an invasive change, but ultimately
more elegant. I'm not sure which way the community prefers.
> thanks
> -- PMM
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
[Qemu-devel] [PATCH v4 4/8] qtest: Fix whitespace
From: Alastair D'Silva <alast...@d-silva.org>
Fix 2 cases of incorrect indentation
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
qtest.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qtest.c b/qtest.c
index a947892..143077e 100644
--- a/qtest.c
+++ b/qtest.c
@@ -309,7 +309,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+return;
}
if (irq_intercept_dev) {
@@ -319,7 +319,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+return;
}
QLIST_FOREACH(ngl, >gpios, node) {
--
2.9.3
[Qemu-devel] [PATCH v4 6/8] hw/timer: Add Epson RX8900 RTC support
From: Alastair D'Silva <alast...@d-silva.org>
This patch adds support for the Epson RX8900 I2C RTC.
The following chip features are implemented:
- RTC (wallclock based, ptimer 10x oversampling to pick up
wallclock transitions)
- Time update interrupt (per second/minute, wallclock based)
- Alarms (wallclock based)
- Temperature (set via a property)
- Countdown timer (emulated clock via ptimer)
- FOUT via GPIO (emulated clock via ptimer)
The following chip features are unimplemented:
- Low voltage detection
- i2c timeout
The implementation exports the following named GPIOs:
rx8900-interrupt-out
rx8900-fout-enable
rx8900-fout
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 912
hw/timer/rx8900_regs.h | 141 +++
hw/timer/trace-events | 31 ++
5 files changed, 1087 insertions(+)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 000..cb1a2c8
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,912 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ * Chris Smart <ch...@distroguy.com>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE=en
+ *
+ * Not implemented:
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "trace.h"
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+typedef struct RX8900State {
+I2CSlave parent_obj;
+
+ptimer_state *sec_timer; /* triggered once per second */
+ptimer_state *fout_timer;
+ptimer_state *countdown_timer;
+bool fout_state;
+int64_t offset;
+uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+uint8_t wday_offset;
+uint8_t nvram[RX8900_NVRAM_SIZE];
+int32_t nvram_offset; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+bool addr_byte;
+uint8_t last_interrupt_seconds; /* The last time the second timer ticked */
+/* the last minute the timer update interrupt was triggered (if enabled) */
+uint8_t last_update_interrupt_minutes;
+double supply_voltage;
+qemu_irq interrupt_pin;
+qemu_irq fout_pin;
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+.name = "rx8900",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+VMSTATE_PTIMER(sec_timer, RX8900State),
+VMSTATE_PTIMER(fout_timer, RX8900State),
+VMSTATE_PTIMER(countdown_timer, RX8900State),
+VMSTATE_BOOL(fout_state, RX8900State),
+VMSTATE_INT64(offset, RX8900State),
+VMSTATE_UINT8(weekday, RX8900State),
+VMSTATE_UINT8(wday_offset, RX8900State),
+VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE),
+VMSTATE_INT32(nvram_offset, RX8900State),
+VMSTATE_BOOL(addr_byte, RX8900State
[Qemu-devel] [PATCH v4 8/8] arm: Add an RX8900 RTC to the ASpeed board
From: Alastair D'Silva <alast...@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
hw/arm/aspeed.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 40c1383..ef63fd0 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -26,6 +26,12 @@ static struct arm_boot_info aspeed_board_binfo = {
.nb_cpus = 1,
};
+typedef struct AspeedI2CDevice {
+const char *type;
+uint8_t address;
+int bus;
+} AspeedI2CDevice;
+
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
@@ -37,6 +43,7 @@ typedef struct AspeedBoardConfig {
const char *fmc_model;
const char *spi_model;
uint32_t num_cs;
+const AspeedI2CDevice *i2c_devices;
} AspeedBoardConfig;
enum {
@@ -80,6 +87,11 @@ enum {
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
+
+static const AspeedI2CDevice ast2500_i2c_devices[] = {
+{"rx8900", 0x32, 11}
+};
+
static const AspeedBoardConfig aspeed_boards[] = {
[PALMETTO_BMC] = {
.soc_name = "ast2400-a1",
@@ -94,6 +106,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
.fmc_model = "n25q256a",
.spi_model = "mx25l25635e",
.num_cs= 1,
+.i2c_devices = ast2500_i2c_devices,
},
[ROMULUS_BMC] = {
.soc_name = "ast2500-a1",
@@ -104,6 +117,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
},
};
+
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Error **errp)
{
@@ -130,6 +144,19 @@ static void aspeed_board_init_flashes(AspeedSMCState *s,
const char *flashtype,
}
}
+static void aspeed_i2c_init(AspeedBoardState *bmc,
+const AspeedBoardConfig *cfg)
+{
+AspeedSoCState *soc = >soc;
+const AspeedI2CDevice *dev;
+
+for (dev = cfg->i2c_devices; dev != NULL && dev->type != NULL; dev++) {
+I2CBus *i2c_bus = aspeed_i2c_get_bus((DeviceState *)>i2c,
+ dev->bus);
+(void)i2c_create_slave(i2c_bus, dev->type, dev->address);
+}
+}
+
static void aspeed_board_init(MachineState *machine,
const AspeedBoardConfig *cfg)
{
@@ -174,6 +201,8 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+aspeed_i2c_init(bmc, cfg);
+
arm_load_kernel(ARM_CPU(first_cpu), _board_binfo);
}
--
2.9.3
[Qemu-devel] [PATCH v4 5/8] hw/i2c: Tidy up NULL check for i2c slave init callbacks
From: Alastair D'Silva <alast...@d-silva.org>
Remove unnecessary syntax
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/i2c/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index ae3ca94..e40781e 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState *dev)
if (sc->init) {
return sc->init(s);
-} else {
-return 0;
}
+
+return 0;
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
--
2.9.3
[Qemu-devel] [PATCH v4 7/8] tests: Test all implemented RX8900 functionality
From: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
tests/Makefile.include | 2 +
tests/rx8900-test.c| 882 +
2 files changed, 884 insertions(+)
create mode 100644 tests/rx8900-test.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index e98d3b6..e52e355 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/rx8900-test$(EXESUF)
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
@@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y)
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
new file mode 100644
index 000..1769659
--- /dev/null
+++ b/tests/rx8900-test.c
@@ -0,0 +1,882 @@
+/*
+ * QTest testcase for the Epson RX8900SA/CE RTC
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/rx8900_regs.h"
+#include "libqtest.h"
+#include "libqos/i2c.h"
+#include "qemu/timer.h"
+
+#define IMX25_I2C_0_BASE 0x43F8
+#define RX8900_TEST_ID "rx8900-test"
+#define RX8900_ADDR 0x32
+#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
+#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
+#define RX8900_FOUT "rx8900-fout"
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+return (x & 0x0f) + (x >> 4) * 10;
+}
+
+static inline uint8_t bin2bcd(uint8_t x)
+{
+return (x / 10 << 4) | (x % 10);
+}
+
+static void qmp_rx8900_set_temperature(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'temperature', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+static void qmp_rx8900_set_voltage(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'voltage', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+/**
+ * Read an RX8900 register
+ * @param reg the address of the register
+ * @return the value of the register
+ */
+static uint8_t read_register(RX8900Addresses reg)
+{
+uint8_t val;
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, , 1);
+
+return val;
+}
+
+/**
+ * Write to an RX8900 register
+ * @param reg the address of the register
+ * @param val the value to write
+ */
+static uint8_t write_register(RX8900Addresses reg, uint8_t val)
+{
+uint8_t buf[2];
+
+buf[0] = reg;
+buf[1] = val;
+
+i2c_send(i2c, addr, buf, 2);
+
+return val;
+}
+
+/**
+ * Set bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void set_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value |= mask;
+write_register(reg, value);
+}
+
+/**
+ * Clear bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value &= ~mask;
+write_register(reg, value);
+}
+
+/**
+ * Read a number of sequential RX8900 registers
+ * @param reg the address of the first register
+ * @param buf (out) an output buffer to stash the register values
+ * @param count the number of registers to read
+ */
+static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count)
+{
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, buf, count);
+}
+
+/**
+ * Write to a sequential number of RX8900 registers
+ * @param reg the address of the first reg
[Qemu-devel] [PATCH v4 2/8] qtest: Support named interrupts
From: Alastair D'Silva <alast...@d-silva.org>
The QTest framework cannot check the state of named interrupts. This patch
adds support for them.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/core/irq.c| 18 +++--
include/hw/irq.h | 13 +++---
qtest.c | 57 +
tests/libqtest.c | 78 +---
tests/libqtest.h | 30 ++
5 files changed, 159 insertions(+), 37 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..75f915b 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -134,15 +134,17 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
return qemu_allocate_irqs(proxy_irq_handler, target, n);
}
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
+qemu_irq qemu_irq_dup(qemu_irq in)
{
-int i;
-qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
-for (i = 0; i < n; i++) {
-*old_irqs[i] = *gpio_in[i];
-gpio_in[i]->handler = handler;
-gpio_in[i]->opaque = _irqs[i];
-}
+qemu_irq out = qemu_allocate_irq(in->handler, in->opaque, in->n);
+return out;
+}
+
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque)
+{
+gpio_in->handler = handler;
+gpio_in->opaque = opaque;
}
static const TypeInfo irq_type_info = {
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..2583fd1 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -58,8 +58,15 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
*/
qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-/* For internal use in qtest. Similar to qemu_irq_split, but operating
- on an existing vector of qemu_irq. */
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
+/**
+ * Duplicate an IRQ
+ * @param in the IRQ to deplicate
+ * @return a copy of the IRQ
+ */
+qemu_irq qemu_irq_dup(qemu_irq in);
+
+/* For internal use in qtest. */
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque);
#endif
diff --git a/qtest.c b/qtest.c
index 46b99ae..ad7e215 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,6 +159,8 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED raise NAME NUM
+ * IRQ_NAMED lower NAME NUM
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
@@ -243,17 +244,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend
*chr,
va_end(ap);
}
+typedef struct qtest_irq {
+qemu_irq old_irq;
+char *name;
+bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
-qemu_irq old_irq = *(qemu_irq *)opaque;
-qemu_set_irq(old_irq, level);
+qtest_irq *data = (qtest_irq *)opaque;
+level = !!level;
+
+qemu_set_irq(data->old_irq, level);
-if (irq_levels[n] != level) {
+if (level != data->last_level) {
CharBackend *chr = _chr;
-irq_levels[n] = level;
qtest_send_prefix(chr);
-qtest_sendf(chr, "IRQ %s %d\n",
-level ? "raise" : "lower", n);
+
+if (data->name) {
+qtest_sendf(chr, "IRQ_NAMED %s %s %d\n",
+level ? "raise" : "lower", data->name, n);
+} else {
+qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+}
+
+data->last_level = level;
}
}
@@ -303,23 +318,26 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
}
QLIST_FOREACH(ngl, >gpios, node) {
-/* We don't support intercept of named GPIOs yet */
-if (ngl->name) {
-continue;
-}
if (words[0][14] == 'o') {
int i;
for (i = 0; i < ngl->num_out; ++i) {
-qemu_irq *disconnected = g_new0(qemu_irq, 1);
-qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
- disconnected, i);
+qtest_irq *data = g_new0(qtest_irq, 1);
+data->name = ngl->name;
+qemu_irq icpt = qemu_allocate_irq(qtest_irq_hand
[Qemu-devel] [PATCH v4 1/8] arm: Uniquely name imx25 I2C buses.
From: Alastair D'Silva <alast...@d-silva.org> The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely: i2c-bus.0 i2c-bus.1 i2c-bus.2 Signed-off-by: Alastair D'Silva <alast...@d-silva.org> --- hw/arm/imx25_pdk.c | 2 +- hw/i2c/imx_i2c.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 025b608..44e741f 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -139,7 +139,7 @@ static void imx25_pdk_init(MachineState *machine) * of simple qtest. See "make check" for details. */ i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(>soc.i2c[0]), - "i2c"), + "i2c-bus.0"), "ds1338", 0x68); } } diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index 37e5a62..6c81b98 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -310,7 +310,7 @@ static void imx_i2c_realize(DeviceState *dev, Error **errp) IMX_I2C_MEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq); -s->bus = i2c_init_bus(DEVICE(dev), "i2c"); +s->bus = i2c_init_bus(DEVICE(dev), NULL); } static void imx_i2c_class_init(ObjectClass *klass, void *data) -- 2.9.3
[Qemu-devel] [PATCH v4 0/8] Add support for the Epson RX8900 RTC to the aspeed board
From: Alastair D'Silva <alast...@d-silva.org> This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. Support for named interrupts has been implemented in qtest to facilitate testing. Changelog: v4: - Split overloaded patches - Fix spelling of Celsius - Remove degrees sign from messages - Don't force float precision - Reformat named interrupt qtest protocol for consistency - Minor formatting changes - Don't connect the RX8900 INT line to NVIC:22, it should be connected to GPIOJ10 on the ASPEED SOC v3: - Add range checks for time components - Shorten trace messages - Use qemu generated i2c bus names - Address style comments from Alexey for rx8900 driver - Fix long lines in qtest harness - Remove trailing whitespace in hw/arm/pxa - Remove stray headers from rx8900 driver - Support low voltage detection in rx8900 driver v2: - Avoid using error_report - Fix TIE behaviour - Move temperature init out of reset, it should not change on a soft reset - Fix IRQ in test failures - Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. - Refactor to use the existing qemu trace infrastructure - Move the RX8900 definition into the aspeed machine init - It it possible for check_update_interrupt_seconds in the rx8900 test to return 6, depending on the alignment with the wall clock. - Support low voltage detection Alastair D'Silva (8): arm: Uniquely name imx25 I2C buses. qtest: Support named interrupts qtest: Support setting named GPIOs qtest: Fix whitespace hw/i2c: Tidy up NULL check for i2c slave init callbacks hw/timer: Add Epson RX8900 RTC support tests: Test all implemented RX8900 functionality arm: Add an RX8900 RTC to the ASpeed board default-configs/arm-softmmu.mak | 1 + hw/arm/aspeed.c | 29 ++ hw/arm/imx25_pdk.c | 2 +- hw/core/irq.c | 18 +- hw/i2c/core.c | 4 +- hw/i2c/imx_i2c.c| 2 +- hw/timer/Makefile.objs | 2 + hw/timer/rx8900.c | 912 hw/timer/rx8900_regs.h | 141 +++ hw/timer/trace-events | 31 ++ include/hw/irq.h| 13 +- qtest.c | 103 +++-- tests/Makefile.include | 2 + tests/libqtest.c| 85 +++- tests/libqtest.h| 59 +++ tests/rx8900-test.c | 882 ++ 16 files changed, 2243 insertions(+), 43 deletions(-) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c -- 2.9.3
[Qemu-devel] [PATCH v4 3/8] qtest: Support setting named GPIOs
From: Alastair D'Silva <alast...@d-silva.org>
Some devices change their behaviour based on the state of their input GPIO
lines.
This patch allows testing of the variable behaviour by providing facilities
for the test to set the state of these GPIO lines.
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
qtest.c | 42 ++
tests/libqtest.c | 7 +++
tests/libqtest.h | 29 +
3 files changed, 78 insertions(+)
diff --git a/qtest.c b/qtest.c
index ad7e215..a947892 100644
--- a/qtest.c
+++ b/qtest.c
@@ -165,6 +165,11 @@ static bool qtest_opened;
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -344,6 +349,43 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+} else if (strcmp(words[0], "irq_set") == 0) {
+DeviceState *dev;
+NamedGPIOList *ngl;
+int level;
+qemu_irq irq = NULL;
+int irq_num;
+
+g_assert(words[1]); /* device */
+g_assert(words[2]); /* gpio list */
+g_assert(words[3]); /* gpio line in list */
+g_assert(words[4]); /* level */
+dev = DEVICE(object_resolve_path(words[1], NULL));
+if (!dev) {
+qtest_send_prefix(chr);
+qtest_send(chr, "FAIL Unknown device\n");
+return;
+}
+
+irq_num = atoi(words[3]);
+level = atoi(words[4]);
+
+QLIST_FOREACH(ngl, >gpios, node) {
+if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) {
+irq = ngl->in[irq_num];
+}
+}
+
+if (irq == NULL) {
+qtest_send_prefix(chr);
+qtest_send(chr, "FAIL Unknown IRQ\n");
+return;
+}
+
+qemu_set_irq(irq, level);
+
+qtest_send_prefix(chr);
+qtest_send(chr, "OK\n");
} else if (strcmp(words[0], "outb") == 0 ||
strcmp(words[0], "outw") == 0 ||
strcmp(words[0], "outl") == 0) {
diff --git a/tests/libqtest.c b/tests/libqtest.c
index a433c3b..a7cdd3b 100644
--- a/tests/libqtest.c
+++ b/tests/libqtest.c
@@ -988,3 +988,10 @@ bool qtest_big_endian(QTestState *s)
{
return s->big_endian;
}
+
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+bool level)
+{
+qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level);
+qtest_rsp(s, 0);
+}
diff --git a/tests/libqtest.h b/tests/libqtest.h
index 99b14b1..3063bc9 100644
--- a/tests/libqtest.h
+++ b/tests/libqtest.h
@@ -190,6 +190,20 @@ void qtest_irq_attach(QTestState *s, const char *name, int
irq,
void *opaque);
/**
+ * qtest_irq_set:
+ * Set an interrupt level
+ * @s: #QTestState instance to operate on.
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the IRQ
+ * @n: the GPIO within the list
+ * @level: the IRQ level
+ *
+ * Set an interrupt to a nominated level
+ */
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+bool level);
+
+/**
* qtest_outb:
* @s: #QTestState instance to operate on.
* @addr: I/O port to write to.
@@ -656,6 +670,21 @@ static inline void irq_attach(const char *name, int irq,
}
/**
+ * qtest_irq_set
+ * Set an interrupt level
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the line to seh
+ * @n: the line to set within the list
+ * @level: the IRQ level
+ */
+static inline void irq_set(const char *id, const char *gpiolist, int n,
+bool level)
+{
+qtest_irq_set(global_qtest, id, gpiolist, n, level);
+}
+
+
+/**
* outb:
* @addr: I/O port to write to.
* @value: Value being written.
--
2.9.3
Re: [Qemu-devel] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support
On Wed, 2016-12-14 at 18:02 +, Peter Maydell wrote:
> On 2 December 2016 at 05:46, Alastair D'Silva <alast...@au1.ibm.com>
> wrote:
> > From: Alastair D'Silva <alast...@d-silva.org>
> >
> > This patch adds support for the Epson RX8900 I2C RTC.
> >
> > The following chip features are implemented:
> > - RTC (wallclock based, ptimer 10x oversampling to pick up
> > wallclock transitions)
> > - Time update interrupt (per second/minute, wallclock based)
> > - Alarms (wallclock based)
> > - Temperature (set via a property)
> > - Countdown timer (emulated clock via ptimer)
> > - FOUT via GPIO (emulated clock via ptimer)
> >
> > The following chip features are unimplemented:
> > - Low voltage detection
> > - i2c timeout
> >
> > The implementation exports the following named GPIOs:
> > rx8900-interrupt-out
> > rx8900-fout-enable
> > rx8900-fout
> >
> > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > Signed-off-by: Chris Smart <ch...@distroguy.com>
> > ---
> > default-configs/arm-softmmu.mak | 1 +
> > hw/i2c/core.c | 4 +-
> > hw/timer/Makefile.objs | 2 +
> > hw/timer/rx8900.c | 912
> >
> > hw/timer/rx8900_regs.h | 141 +++
> > hw/timer/trace-events | 31 ++
> > 6 files changed, 1089 insertions(+), 2 deletions(-)
> > create mode 100644 hw/timer/rx8900.c
> > create mode 100644 hw/timer/rx8900_regs.h
> >
> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-
> > softmmu.mak
> > index 6de3e16..adb600e 100644
> > --- a/default-configs/arm-softmmu.mak
> > +++ b/default-configs/arm-softmmu.mak
> > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
> > CONFIG_ALLWINNER_EMAC=y
> > CONFIG_IMX_FEC=y
> > CONFIG_DS1338=y
> > +CONFIG_RX8900=y
> > CONFIG_PFLASH_CFI01=y
> > CONFIG_PFLASH_CFI02=y
> > CONFIG_MICRODRIVE=y
> > diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> > index ae3ca94..e40781e 100644
> > --- a/hw/i2c/core.c
> > +++ b/hw/i2c/core.c
> > @@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState
> > *dev)
> >
> > if (sc->init) {
> > return sc->init(s);
> > -} else {
> > -return 0;
> > }
> > +
> > +return 0;
> > }
> >
>
> This change shouldn't be in this patch.
Ok
>
> > DeviceState *i2c_create_slave(I2CBus *bus, const char *name,
> > uint8_t addr)
> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> > index 7ba8c23..fa028ac 100644
> > --- a/hw/timer/Makefile.objs
> > +++ b/hw/timer/Makefile.objs
> > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
> > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
> > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
> > common-obj-$(CONFIG_DS1338) += ds1338.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> > common-obj-$(CONFIG_HPET) += hpet.o
> > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
> > common-obj-$(CONFIG_M48T59) += m48t59.o
> > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> > common-obj-$(CONFIG_IMX) += imx_gpt.o
> > common-obj-$(CONFIG_LM32) += lm32_timer.o
> > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> >
> > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
> > +/**
> > + * Get the device temperature in Celcius as a property
>
> It's spelt "Celsius" -- please fix through the whole file.
>
Whoops, thanks for that :)
> > + * @param obj the device
> > + * @param v
> > + * @param name the property name
> > + * @param opaque
> > + * @param errp an error object to populate on failure
> > + */
> > +static void rx8900_get_temperature(Object *obj, Visitor *v, const
> > char *name,
> > + void *opaque, Error **errp)
> > +{
> > +RX8900State *s = RX8900(obj);
> > +double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) /
> > 3.218f;
>
> Why use 'double' for the variable when you're doing all your
> arithmetic at 'float' precision because of those 'f' suffixes?
> Unless there's a good reason I'd suggest dropping the 'f's and
> just doing all the arithmetic at double precision.
Ok
> > +static void rx8900_set_temperature(Object *obj, Visitor *v, const
> > char *name,
> > +
Re: [Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts
On Wed, 2016-12-14 at 18:29 +, Peter Maydell wrote:
> On 2 December 2016 at 05:46, Alastair D'Silva <alast...@au1.ibm.com>
> wrote:
> > From: Alastair D'Silva <alast...@d-silva.org>
> >
> > The QTest framework cannot work with named interrupts. This patch
> > adds support for them, as well as the ability to manipulate them
> > from within a test.
> >
> > Read actions are via callbacks, which allows for pulsed interrupts
> > to be read (the polled method used for the unnamed interrupts
> > cannot read pulsed interrupts as the value is reverted before the
> > test sees the changes).
> >
> > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > --- a/qtest.c
> > +++ b/qtest.c
> > @@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
> > static FILE *qtest_log_fp;
> > static CharBackend qtest_chr;
> > static GString *inbuf;
> > -static int irq_levels[MAX_IRQ];
> > static qemu_timeval start_time;
> > static bool qtest_opened;
> >
> > @@ -160,10 +159,16 @@ static bool qtest_opened;
> > *
> > * IRQ raise NUM
> > * IRQ lower NUM
> > + * IRQ_NAMED NAME NUM LEVEL
>
> I think we should be consistent about the protocol here:
> unnamed IRQs get 'raise' and 'lower' messages, so we should
> do the same for named IRQs.
>
Ok
> > *
> > * where NUM is an IRQ number. For the PC, interrupts can be
> > intercepted
> > * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out
> > with
> > * NUM=0 even though it is remapped to GSI 2).
> > + *
> > + * > irq_set NAME NUM LEVEL
> > + * < OK
> > + *
> > + * Set the named input IRQ to the level (0/1)
>
> I think adding support for raising and lowering device IRQs
> should be a separate patch, as it's a different feature.
> (I'm also not sure we should need it -- devices will be
> wired into the system, and qtest is testing the whole
> system from the point of view of the CPU. The CPU can't
> arbitrarily reach in and assert a device's outgoing
> interrupt line, so I'm not sure the tests should be able
> to do it either.)
>
Unfortunately, from what I can see, the concepts of GPIO lines & IRQs
are a bit mixed up in Qemu. The use case I have is that an input line
to the chip (not an output) needs to be asserted during the test to
change it's behaviour.
> (Everything else below here is trivial fixes.)
>
> > */
> >
> > static int hex2nib(char ch)
> > @@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3)
> > qtest_sendf(CharBackend *chr,
> > va_end(ap);
> > }
> >
> > +typedef struct qtest_irq {
> > +qemu_irq old_irq;
> > +char *name;
> > +bool last_level;
> > +} qtest_irq;
> > +
> > static void qtest_irq_handler(void *opaque, int n, int level)
> > {
> > -qemu_irq old_irq = *(qemu_irq *)opaque;
> > -qemu_set_irq(old_irq, level);
> > +qtest_irq *data = (qtest_irq *)opaque;
> > +level = !!level;
> > +
> > +qemu_set_irq(data->old_irq, level);
> >
> > -if (irq_levels[n] != level) {
> > +if (level != data->last_level) {
> > CharBackend *chr = _chr;
> > -irq_levels[n] = level;
> > qtest_send_prefix(chr);
> > -qtest_sendf(chr, "IRQ %s %d\n",
> > -level ? "raise" : "lower", n);
> > +
> > +if (data->name) {
> > +qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
> > +data->name, n, level);
> > +} else {
> > +qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" :
> > "lower", n);
> > +}
> > +
> > +data->last_level = level;
> > }
> > }
> >
> > @@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend
> > *chr, gchar **words)
> > if (!dev) {
> > qtest_send_prefix(chr);
> > qtest_send(chr, "FAIL Unknown device\n");
> > - return;
> > +return;
> > }
> >
> > if (irq_intercept_dev) {
> > @@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend
> > *chr, gchar **words)
> > } else {
> > qtest_send(chr, "OK\n");
> > }
> > - return;
> > +return;
> > }
>
> Fixing whitespace issues is generally best done in a separate patch.
>
[Qemu-devel] [PATCH v3 6/7] tests: Test all implemented RX8900 functionality
From: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
tests/Makefile.include | 2 +
tests/rx8900-test.c| 882 +
2 files changed, 884 insertions(+)
create mode 100644 tests/rx8900-test.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index e98d3b6..e52e355 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/rx8900-test$(EXESUF)
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
@@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y)
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
new file mode 100644
index 000..1769659
--- /dev/null
+++ b/tests/rx8900-test.c
@@ -0,0 +1,882 @@
+/*
+ * QTest testcase for the Epson RX8900SA/CE RTC
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/rx8900_regs.h"
+#include "libqtest.h"
+#include "libqos/i2c.h"
+#include "qemu/timer.h"
+
+#define IMX25_I2C_0_BASE 0x43F8
+#define RX8900_TEST_ID "rx8900-test"
+#define RX8900_ADDR 0x32
+#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
+#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
+#define RX8900_FOUT "rx8900-fout"
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+return (x & 0x0f) + (x >> 4) * 10;
+}
+
+static inline uint8_t bin2bcd(uint8_t x)
+{
+return (x / 10 << 4) | (x % 10);
+}
+
+static void qmp_rx8900_set_temperature(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'temperature', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+static void qmp_rx8900_set_voltage(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'voltage', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+/**
+ * Read an RX8900 register
+ * @param reg the address of the register
+ * @return the value of the register
+ */
+static uint8_t read_register(RX8900Addresses reg)
+{
+uint8_t val;
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, , 1);
+
+return val;
+}
+
+/**
+ * Write to an RX8900 register
+ * @param reg the address of the register
+ * @param val the value to write
+ */
+static uint8_t write_register(RX8900Addresses reg, uint8_t val)
+{
+uint8_t buf[2];
+
+buf[0] = reg;
+buf[1] = val;
+
+i2c_send(i2c, addr, buf, 2);
+
+return val;
+}
+
+/**
+ * Set bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void set_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value |= mask;
+write_register(reg, value);
+}
+
+/**
+ * Clear bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value &= ~mask;
+write_register(reg, value);
+}
+
+/**
+ * Read a number of sequential RX8900 registers
+ * @param reg the address of the first register
+ * @param buf (out) an output buffer to stash the register values
+ * @param count the number of registers to read
+ */
+static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count)
+{
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, buf, count);
+}
+
+/**
+ * Write to a sequential number of RX8900 registers
+ * @param reg the address of the first reg
[Qemu-devel] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support
From: Alastair D'Silva <alast...@d-silva.org>
This patch adds support for the Epson RX8900 I2C RTC.
The following chip features are implemented:
- RTC (wallclock based, ptimer 10x oversampling to pick up
wallclock transitions)
- Time update interrupt (per second/minute, wallclock based)
- Alarms (wallclock based)
- Temperature (set via a property)
- Countdown timer (emulated clock via ptimer)
- FOUT via GPIO (emulated clock via ptimer)
The following chip features are unimplemented:
- Low voltage detection
- i2c timeout
The implementation exports the following named GPIOs:
rx8900-interrupt-out
rx8900-fout-enable
rx8900-fout
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/i2c/core.c | 4 +-
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 912
hw/timer/rx8900_regs.h | 141 +++
hw/timer/trace-events | 31 ++
6 files changed, 1089 insertions(+), 2 deletions(-)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index ae3ca94..e40781e 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState *dev)
if (sc->init) {
return sc->init(s);
-} else {
-return 0;
}
+
+return 0;
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 000..6a113e4
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,912 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ * Chris Smart <ch...@distroguy.com>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE=en
+ *
+ * Not implemented:
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "trace.h"
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+typedef struct RX8900State {
+I2CSlave parent_obj;
+
+ptimer_state *sec_timer; /* triggered once per second */
+ptimer_state *fout_timer;
+ptimer_state *countdown_timer;
+bool fout_state;
+int64_t offset;
+uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+uint8_t wday_offset;
+uint8_t nvram[RX8900_NVRAM_SIZE];
+int32_t nvram_offset; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+bool addr_byte;
+uint8_t last_interrupt_seconds; /* The last time the second timer ticked */
+/* the last minute the timer update interrupt was triggered (if enabled) */
+uint8_t last_update_interrupt_minutes;
+double supply_voltage;
+qemu_irq interrupt_pin;
+qemu_irq fout_pin;
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+.name = "rx8900",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+VMSTATE_PTIMER(sec_timer, RX8900State),
+VMSTATE_PTIMER(fout_
[Qemu-devel] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks
From: Alastair D'Silva <alast...@d-silva.org>
Add a NULL check for i2c slave init callbacks, so that we no longer need to
implement empty init functions.
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/pxa2xx.c | 7 ---
hw/arm/tosa.c | 7 ---
hw/arm/z2.c | 7 ---
hw/i2c/core.c | 6 +-
hw/timer/ds1338.c | 6 --
5 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 8aa0f8a..bdcf6bc 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -1449,17 +1449,10 @@ static const VMStateDescription vmstate_pxa2xx_i2c = {
}
};
-static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = pxa2xx_i2c_slave_init;
k->event = pxa2xx_i2c_event;
k->recv = pxa2xx_i2c_rx;
k->send = pxa2xx_i2c_tx;
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 1ee12f4..39d9dbb 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -202,12 +202,6 @@ static int tosa_dac_recv(I2CSlave *s)
return -1;
}
-static int tosa_dac_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static void tosa_tg_init(PXA2xxState *cpu)
{
I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
@@ -275,7 +269,6 @@ static void tosa_dac_class_init(ObjectClass *klass, void
*data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = tosa_dac_init;
k->event = tosa_dac_event;
k->recv = tosa_dac_recv;
k->send = tosa_dac_send;
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 68a92f3..b3a6bbd 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -263,12 +263,6 @@ static int aer915_recv(I2CSlave *slave)
return retval;
}
-static int aer915_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static VMStateDescription vmstate_aer915_state = {
.name = "aer915",
.version_id = 1,
@@ -285,7 +279,6 @@ static void aer915_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = aer915_init;
k->event = aer915_event;
k->recv = aer915_recv;
k->send = aer915_send;
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index abd4c4c..ae3ca94 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -260,7 +260,11 @@ static int i2c_slave_qdev_init(DeviceState *dev)
I2CSlave *s = I2C_SLAVE(dev);
I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
-return sc->init(s);
+if (sc->init) {
+return sc->init(s);
+} else {
+return 0;
+}
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c
index 0112949..f5d04dd 100644
--- a/hw/timer/ds1338.c
+++ b/hw/timer/ds1338.c
@@ -198,11 +198,6 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data)
return 0;
}
-static int ds1338_init(I2CSlave *i2c)
-{
-return 0;
-}
-
static void ds1338_reset(DeviceState *dev)
{
DS1338State *s = DS1338(dev);
@@ -220,7 +215,6 @@ static void ds1338_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = ds1338_init;
k->event = ds1338_event;
k->recv = ds1338_recv;
k->send = ds1338_send;
--
2.9.3
[Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts
From: Alastair D'Silva <alast...@d-silva.org>
The QTest framework cannot work with named interrupts. This patch
adds support for them, as well as the ability to manipulate them
from within a test.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/core/irq.c| 18 +-
include/hw/irq.h | 13 +--
qtest.c | 102 ++-
tests/libqtest.c | 88 ---
tests/libqtest.h | 59
5 files changed, 241 insertions(+), 39 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..75f915b 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -134,15 +134,17 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
return qemu_allocate_irqs(proxy_irq_handler, target, n);
}
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
+qemu_irq qemu_irq_dup(qemu_irq in)
{
-int i;
-qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
-for (i = 0; i < n; i++) {
-*old_irqs[i] = *gpio_in[i];
-gpio_in[i]->handler = handler;
-gpio_in[i]->opaque = _irqs[i];
-}
+qemu_irq out = qemu_allocate_irq(in->handler, in->opaque, in->n);
+return out;
+}
+
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque)
+{
+gpio_in->handler = handler;
+gpio_in->opaque = opaque;
}
static const TypeInfo irq_type_info = {
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..2583fd1 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -58,8 +58,15 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
*/
qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-/* For internal use in qtest. Similar to qemu_irq_split, but operating
- on an existing vector of qemu_irq. */
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
+/**
+ * Duplicate an IRQ
+ * @param in the IRQ to deplicate
+ * @return a copy of the IRQ
+ */
+qemu_irq qemu_irq_dup(qemu_irq in);
+
+/* For internal use in qtest. */
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+void *opaque);
#endif
diff --git a/qtest.c b/qtest.c
index 46b99ae..2e09634 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,10 +159,16 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED NAME NUM LEVEL
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend
*chr,
va_end(ap);
}
+typedef struct qtest_irq {
+qemu_irq old_irq;
+char *name;
+bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
-qemu_irq old_irq = *(qemu_irq *)opaque;
-qemu_set_irq(old_irq, level);
+qtest_irq *data = (qtest_irq *)opaque;
+level = !!level;
+
+qemu_set_irq(data->old_irq, level);
-if (irq_levels[n] != level) {
+if (level != data->last_level) {
CharBackend *chr = _chr;
-irq_levels[n] = level;
qtest_send_prefix(chr);
-qtest_sendf(chr, "IRQ %s %d\n",
-level ? "raise" : "lower", n);
+
+if (data->name) {
+qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
+data->name, n, level);
+} else {
+qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+}
+
+data->last_level = level;
}
}
@@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+return;
}
if (irq_intercept_dev) {
@@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+return;
}
QLIST_FOREACH(ngl, >gpios, node) {
-/* We don't support interc
[Qemu-devel] [PATCH v3 7/7] arm: Add an RX8900 RTC to the ASpeed board
From: Alastair D'Silva <alast...@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
hw/arm/aspeed.c | 58 +++--
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c7206fd..7445242 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -26,6 +26,20 @@ static struct arm_boot_info aspeed_board_binfo = {
.nb_cpus = 1,
};
+typedef struct IRQConfig {
+const char *name;
+int irq;
+int nvic_irq;
+} IRQConfig;
+
+typedef struct AspeedI2CDevice {
+const char *type;
+uint8_t address;
+int bus;
+/* device_inputs not yet implemented */
+const IRQConfig *device_outputs;
+} AspeedI2CDevice;
+
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
@@ -34,6 +48,7 @@ typedef struct AspeedBoardState {
typedef struct AspeedBoardConfig {
const char *soc_name;
uint32_t hw_strap1;
+const AspeedI2CDevice *i2c_devices;
} AspeedBoardConfig;
enum {
@@ -64,9 +79,25 @@ enum {
SCU_HW_STRAP_MAC0_RGMII) & \
~SCU_HW_STRAP_2ND_BOOT_WDT)
+static const IRQConfig rx8900_out[] = {
+{"rx8900-interrupt-out", 0, 22},
+{NULL}
+};
+
+static const AspeedI2CDevice ast2500_i2c_devices[] = {
+{"rx8900", 0x32, 11, rx8900_out},
+{NULL}
+};
+
static const AspeedBoardConfig aspeed_boards[] = {
-[PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },
-[AST2500_EVB] = { "ast2500-a1", AST2500_EVB_HW_STRAP1 },
+[PALMETTO_BMC] = {
+"ast2400-a0", PALMETTO_BMC_HW_STRAP1,
+NULL
+},
+[AST2500_EVB] = {
+"ast2500-a1", AST2500_EVB_HW_STRAP1,
+ast2500_i2c_devices
+},
};
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
@@ -95,6 +126,27 @@ static void aspeed_board_init_flashes(AspeedSMCState *s,
const char *flashtype,
}
}
+static void aspeed_i2c_init(AspeedBoardState *bmc,
+const AspeedBoardConfig *cfg)
+{
+AspeedSoCState *soc = >soc;
+const AspeedI2CDevice *dev;
+const IRQConfig *out;
+
+for (dev = cfg->i2c_devices; dev != NULL && dev->type != NULL; dev++) {
+I2CBus *i2c_bus = aspeed_i2c_get_bus((DeviceState *)>i2c,
+ dev->bus);
+DeviceState *i2c_slave = i2c_create_slave(i2c_bus, dev->type,
+ dev->address);
+
+for (out = dev->device_outputs; out != NULL && out->name != NULL;
+out++) {
+qdev_connect_gpio_out_named(i2c_slave, out->name, out->irq,
+qdev_get_gpio_in(DEVICE(>vic), out->nvic_irq));
+}
+}
+}
+
static void aspeed_board_init(MachineState *machine,
const AspeedBoardConfig *cfg)
{
@@ -137,6 +189,8 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+aspeed_i2c_init(bmc, cfg);
+
arm_load_kernel(ARM_CPU(first_cpu), _board_binfo);
}
--
2.9.3
[Qemu-devel] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board
From: Alastair D'Silva <alast...@d-silva.org> This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. A NULL check have been added to eliminate empty i2cslave init functions. Support for named interrupts has been implemented in qtest to facilitate testing. Changelog: v3: - Add a table to Aspeed for i2c devices - Add range checks for time components - Shorten trace messages - Use qemu generated i2c bus names - Address style comments from Alexey for rx8900 driver - Fix long lines in qtest harness - Remove trailing whitespace in hw/arm/pxa - Remove stray headers from rx8900 driver - Support low voltage detection in rx8900 driver v2: - Avoid using error_report - Fix TIE behaviour - Move temperature init out of reset, it should not change on a soft reset - Fix IRQ in test failures - Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. - Refactor to use the existing qemu trace infrastructure - Move the RX8900 definition into the aspeed machine init - It it possible for check_update_interrupt_seconds in the rx8900 test to return 6, depending on the alignment with the wall clock. - Support low voltage detection Alastair D'Silva (7): arm: Uniquely name imx25 I2C buses. hw/arm: remove trailing whitespace hw/i2c: Add a NULL check for i2c slave init callbacks qtest: Support named interrupts hw/timer: Add Epson RX8900 RTC support tests: Test all implemented RX8900 functionality arm: Add an RX8900 RTC to the ASpeed board default-configs/arm-softmmu.mak | 1 + hw/arm/aspeed.c | 58 ++- hw/arm/imx25_pdk.c | 4 +- hw/arm/pxa2xx.c | 9 +- hw/arm/tosa.c | 7 - hw/arm/z2.c | 7 - hw/core/irq.c | 18 +- hw/i2c/core.c | 6 +- hw/i2c/imx_i2c.c| 2 +- hw/timer/Makefile.objs | 2 + hw/timer/ds1338.c | 6 - hw/timer/rx8900.c | 912 hw/timer/rx8900_regs.h | 141 +++ hw/timer/trace-events | 31 ++ include/hw/irq.h| 13 +- qtest.c | 102 +++-- tests/Makefile.include | 2 + tests/libqtest.c| 88 +++- tests/libqtest.h| 59 +++ tests/rx8900-test.c | 882 ++ 20 files changed, 2276 insertions(+), 74 deletions(-) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c -- 2.9.3
[Qemu-devel] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses.
From: Alastair D'Silva <alast...@d-silva.org> The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely: i2c-bus.0 i2c-bus.1 i2c-bus.2 Signed-off-by: Alastair D'Silva <alast...@d-silva.org> --- hw/arm/imx25_pdk.c | 4 +--- hw/i2c/imx_i2c.c | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 025b608..c6f04d3 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState *machine) * We add it here (only on qtest usage) to be able to do a bit * of simple qtest. See "make check" for details. */ -i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(>soc.i2c[0]), - "i2c"), - "ds1338", 0x68); +i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68); } } diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index 37e5a62..6c81b98 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -310,7 +310,7 @@ static void imx_i2c_realize(DeviceState *dev, Error **errp) IMX_I2C_MEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq); -s->bus = i2c_init_bus(DEVICE(dev), "i2c"); +s->bus = i2c_init_bus(DEVICE(dev), NULL); } static void imx_i2c_class_init(ObjectClass *klass, void *data) -- 2.9.3
[Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace
From: Alastair D'Silva <alast...@d-silva.org>
Remove trailing whitespace in hw/arm/pxa2xx.c
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 21ea1d6..8aa0f8a 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2070,7 +2070,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
if (!revision)
revision = "pxa270";
-
+
s->cpu = cpu_arm_init(revision);
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
--
2.9.3
Re: [Qemu-devel] [PATCH v2 4/6] hw/timer: Add Epson RX8900 RTC support
On Fri, 2016-12-02 at 15:07 +1100, Alexey Kardashevskiy wrote:
> On 02/12/16 14:30, Alastair D'Silva wrote:
> > On Fri, 2016-12-02 at 13:48 +1100, Alexey Kardashevskiy wrote:
> > > On 02/12/16 11:19, Alastair D'Silva wrote:
> > > > On Thu, 2016-12-01 at 16:53 +1100, Alexey Kardashevskiy wrote:
> > > >
> > > > > On 30/11/16 16:36, Alastair D'Silva wrote:
> > > > > > From: Alastair D'Silva <alast...@d-silva.org>
> > > > > >
> > > > > > This patch adds support for the Epson RX8900 I2C RTC.
> > > > > >
> > > > > > The following chip features are implemented:
> > > > > > - RTC (wallclock based, ptimer 10x oversampling to pick up
> > > > > > wallclock transitions)
> > > > > > - Time update interrupt (per second/minute, wallclock
> > > > > > based)
> > > > > > - Alarms (wallclock based)
> > > > > > - Temperature (set via a property)
> > > > > > - Countdown timer (emulated clock via ptimer)
> > > > > > - FOUT via GPIO (emulated clock via ptimer)
> > > > > >
> > > > > > The following chip features are unimplemented:
> > > > > > - Low voltage detection
> > > > > > - i2c timeout
> > > > > >
> > > > > > The implementation exports the following named GPIOs:
> > > > > > rx8900-interrupt-out
> > > > > > rx8900-fout-enable
> > > > > > rx8900-fout
> > > > > >
> > > > > > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > > > > > Signed-off-by: Chris Smart <ch...@distroguy.com>
> > > > > > ---
> > > > > > default-configs/arm-softmmu.mak | 1 +
> > > > > > hw/timer/Makefile.objs | 2 +
> > > > > > hw/timer/rx8900.c | 890
> > > > > >
> > > > > > hw/timer/rx8900_regs.h | 139 +++
> > > > > > hw/timer/trace-events | 31 ++
> > > > > > 5 files changed, 1063 insertions(+)
> > > > > > create mode 100644 hw/timer/rx8900.c
> > > > > > create mode 100644 hw/timer/rx8900_regs.h
> > > > > >
> > > > > >
> > > > > > +#define TYPE_RX8900 "rx8900"
> > > > > > +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj),
> > > > > > TYPE_RX8900)
> > > > > > +
> > > > > > +typedef struct RX8900State {
> > > > > > +I2CSlave parent_obj;
> > > > > > +
> > > > > > +ptimer_state *sec_timer; /* triggered once per second
> > > > > > */
> > > > > > +ptimer_state *fout_timer;
> > > > > > +ptimer_state *countdown_timer;
> > > > > > +bool fout;
> > > > >
> > > > > Is this "FOE" on the chip?
> > > > >
> > > >
> > > > No, it tracks the state of the fout waveform. I'll rename it to
> > > > fout_state.
> > >
> > > Since it is bool, fout_enabled makes more sense.
> > >
> >
> > No it does't, it's not an enabled control, but the phase of the
> > waveform.
>
> I do not mind that "enabled" may be bad name but you are not helping
> :)
>
> A "phase" can be false or true? What does "true" phase of a waveform
> mean?
>
> I cannot find neither "phase" nor "waveform" words in the spec.
>
FOUT outputs a 1, 1024 or 32768Hz square wave. We need to track the
current state of the wave so we know what the next state should be.
> > > > > > +
> > > > > > +static void capture_current_time(RX8900State *s)
> > > > > > +{
> > > > > > +/* Capture the current time into the secondary
> > > > > > registers
> > > > > > + * which will be actually read by the data transfer
> > > > > > operation.
> > > > > > + */
> > > > > > +struct tm now;
> > > > > > +qemu_get_timedate(, s->offset);
> > > > > > +s->nvram[SECONDS] = to_bcd(now.tm_sec);
> > > > > > +s->nvram[MINUTES] = to_bcd(now.tm_min);
> > > > > &g
Re: [Qemu-devel] [PATCH v2 4/6] hw/timer: Add Epson RX8900 RTC support
On Fri, 2016-12-02 at 13:48 +1100, Alexey Kardashevskiy wrote: > On 02/12/16 11:19, Alastair D'Silva wrote: > > On Thu, 2016-12-01 at 16:53 +1100, Alexey Kardashevskiy wrote: > > > > > On 30/11/16 16:36, Alastair D'Silva wrote: > > > > From: Alastair D'Silva <alast...@d-silva.org> > > > > > > > > This patch adds support for the Epson RX8900 I2C RTC. > > > > > > > > The following chip features are implemented: > > > > - RTC (wallclock based, ptimer 10x oversampling to pick up > > > > wallclock transitions) > > > > - Time update interrupt (per second/minute, wallclock based) > > > > - Alarms (wallclock based) > > > > - Temperature (set via a property) > > > > - Countdown timer (emulated clock via ptimer) > > > > - FOUT via GPIO (emulated clock via ptimer) > > > > > > > > The following chip features are unimplemented: > > > > - Low voltage detection > > > > - i2c timeout > > > > > > > > The implementation exports the following named GPIOs: > > > > rx8900-interrupt-out > > > > rx8900-fout-enable > > > > rx8900-fout > > > > > > > > Signed-off-by: Alastair D'Silva <alast...@d-silva.org> > > > > Signed-off-by: Chris Smart <ch...@distroguy.com> > > > > --- > > > > default-configs/arm-softmmu.mak | 1 + > > > > hw/timer/Makefile.objs | 2 + > > > > hw/timer/rx8900.c | 890 > > > > > > > > hw/timer/rx8900_regs.h | 139 +++ > > > > hw/timer/trace-events | 31 ++ > > > > 5 files changed, 1063 insertions(+) > > > > create mode 100644 hw/timer/rx8900.c > > > > create mode 100644 hw/timer/rx8900_regs.h > > > > > > > > diff --git a/default-configs/arm-softmmu.mak b/default- > > > > configs/arm- > > > > softmmu.mak > > > > index 6de3e16..adb600e 100644 > > > > --- a/default-configs/arm-softmmu.mak > > > > +++ b/default-configs/arm-softmmu.mak > > > > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y > > > > CONFIG_ALLWINNER_EMAC=y > > > > CONFIG_IMX_FEC=y > > > > CONFIG_DS1338=y > > > > +CONFIG_RX8900=y > > > > CONFIG_PFLASH_CFI01=y > > > > CONFIG_PFLASH_CFI02=y > > > > CONFIG_MICRODRIVE=y > > > > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > > > > index 7ba8c23..fa028ac 100644 > > > > --- a/hw/timer/Makefile.objs > > > > +++ b/hw/timer/Makefile.objs > > > > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += > > > > arm_mptimer.o > > > > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o > > > > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o > > > > common-obj-$(CONFIG_DS1338) += ds1338.o > > > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > > > common-obj-$(CONFIG_HPET) += hpet.o > > > > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o > > > > common-obj-$(CONFIG_M48T59) += m48t59.o > > > > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o > > > > common-obj-$(CONFIG_IMX) += imx_gpt.o > > > > common-obj-$(CONFIG_LM32) += lm32_timer.o > > > > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o > > > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > > > > > > > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o > > > > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o > > > > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c > > > > new file mode 100644 > > > > index 000..e634819 > > > > --- /dev/null > > > > +++ b/hw/timer/rx8900.c > > > > @@ -0,0 +1,890 @@ > > > > +/* > > > > + * Epson RX8900SA/CE Realtime Clock Module > > > > + * > > > > + * Copyright (c) 2016 IBM Corporation > > > > + * Authors: > > > > + * Alastair D'Silva <alast...@d-silva.org> > > > > + * Chris Smart <ch...@distroguy.com> > > > > + * > > > > + * This code is licensed under the GPL version 2 or > > > > later. See > > > > + * the COPYING file in the top-level directory. > > > > + * > > > > + * Datasheet available at: > > > > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX89 > >
Re: [Qemu-devel] [PATCH v2 4/6] hw/timer: Add Epson RX8900 RTC support
On Thu, 2016-12-01 at 16:53 +1100, Alexey Kardashevskiy wrote:
> On 30/11/16 16:36, Alastair D'Silva wrote:
> > From: Alastair D'Silva <alast...@d-silva.org>
> >
> > This patch adds support for the Epson RX8900 I2C RTC.
> >
> > The following chip features are implemented:
> > - RTC (wallclock based, ptimer 10x oversampling to pick up
> > wallclock transitions)
> > - Time update interrupt (per second/minute, wallclock based)
> > - Alarms (wallclock based)
> > - Temperature (set via a property)
> > - Countdown timer (emulated clock via ptimer)
> > - FOUT via GPIO (emulated clock via ptimer)
> >
> > The following chip features are unimplemented:
> > - Low voltage detection
> > - i2c timeout
> >
> > The implementation exports the following named GPIOs:
> > rx8900-interrupt-out
> > rx8900-fout-enable
> > rx8900-fout
> >
> > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > Signed-off-by: Chris Smart <ch...@distroguy.com>
> > ---
> > default-configs/arm-softmmu.mak | 1 +
> > hw/timer/Makefile.objs | 2 +
> > hw/timer/rx8900.c | 890
> >
> > hw/timer/rx8900_regs.h | 139 +++
> > hw/timer/trace-events | 31 ++
> > 5 files changed, 1063 insertions(+)
> > create mode 100644 hw/timer/rx8900.c
> > create mode 100644 hw/timer/rx8900_regs.h
> >
> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-
> > softmmu.mak
> > index 6de3e16..adb600e 100644
> > --- a/default-configs/arm-softmmu.mak
> > +++ b/default-configs/arm-softmmu.mak
> > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
> > CONFIG_ALLWINNER_EMAC=y
> > CONFIG_IMX_FEC=y
> > CONFIG_DS1338=y
> > +CONFIG_RX8900=y
> > CONFIG_PFLASH_CFI01=y
> > CONFIG_PFLASH_CFI02=y
> > CONFIG_MICRODRIVE=y
> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> > index 7ba8c23..fa028ac 100644
> > --- a/hw/timer/Makefile.objs
> > +++ b/hw/timer/Makefile.objs
> > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
> > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
> > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
> > common-obj-$(CONFIG_DS1338) += ds1338.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> > common-obj-$(CONFIG_HPET) += hpet.o
> > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
> > common-obj-$(CONFIG_M48T59) += m48t59.o
> > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> > common-obj-$(CONFIG_IMX) += imx_gpt.o
> > common-obj-$(CONFIG_LM32) += lm32_timer.o
> > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> >
> > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
> > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
> > new file mode 100644
> > index 000..e634819
> > --- /dev/null
> > +++ b/hw/timer/rx8900.c
> > @@ -0,0 +1,890 @@
> > +/*
> > + * Epson RX8900SA/CE Realtime Clock Module
> > + *
> > + * Copyright (c) 2016 IBM Corporation
> > + * Authors:
> > + * Alastair D'Silva <alast...@d-silva.org>
> > + * Chris Smart <ch...@distroguy.com>
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Datasheet available at:
> > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE
> > =en
> > + *
> > + * Not implemented:
> > + * Implement i2c timeout
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu-common.h"
> > +#include "hw/i2c/i2c.h"
> > +#include "hw/timer/rx8900_regs.h"
> > +#include "hw/ptimer.h"
> > +#include "qemu/main-loop.h"
> > +#include "qemu/bcd.h"
> > +#include "qemu/log.h"
> > +#include "qapi/error.h"
> > +#include "qapi/visitor.h"
> > +#include "trace.h"
> > +
> > + #include
> > +
> > + #include
>
> Not needed empty lines and spaces before "#include".
>
Ok, these were leftovers and don't belong there anyway.
>
> > +
> > +#define TYPE_RX8900 "rx8900"
> > +#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
> > +
> > +typedef struct RX8900State {
> > +I2CSlave parent_obj;
> > +
> > +pt
Re: [Qemu-devel] [PATCH v2 1/6] arm: Uniquely name imx25 I2C buses.
On Thu, 2016-12-01 at 13:31 +0100, Cédric Le Goater wrote:
> On 12/01/2016 01:42 AM, Alastair D'Silva wrote:
> > On Wed, 2016-11-30 at 09:18 +0100, Cédric Le Goater wrote:
> > > On 11/30/2016 06:36 AM, Alastair D'Silva wrote:
> > > > diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
> > > > index 37e5a62..7be10fb 100644
> > > > --- a/hw/i2c/imx_i2c.c
> > > > +++ b/hw/i2c/imx_i2c.c
> > > > @@ -305,12 +305,16 @@ static const VMStateDescription
> > > > imx_i2c_vmstate = {
> > > > static void imx_i2c_realize(DeviceState *dev, Error **errp)
> > > > {
> > > > IMXI2CState *s = IMX_I2C(dev);
> > > > +static int bus_count;
> > >
> > > hmm, the static is ugly :/
> > >
> > > Isn't there other ways to achieve this naming ?
> > >
> > > Thanks,
> > >
> > > C.
> > >
> >
> > I'm not seeing an obvious way around it. The busses are realized
> > independently (so I can't implement what we do with the aspeed i2c
> > busses), and it is named before fsl-imx25:fsl_imx25_realize() can
> > apply
> > specific properties to the bus.
> >
> > If you have any suggestions, I'm all ears.
>
> What about that ?
>
> @@ -310,7 +310,7 @@ static void imx_i2c_realize(DeviceState
> IMX_I2C_MEM_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem);
> sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq);
> -s->bus = i2c_init_bus(DEVICE(dev), "i2c");
> +s->bus = i2c_init_bus(DEVICE(dev), NULL);
>}
>
> static void imx_i2c_class_init(ObjectClass *klass, void *data)
>
> Which should name automatically the I2C objects :
>
> (qemu) info qom-tree
> /machine (imx25-pdk-machine)
> /peripheral (container)
> /soc (fsl,imx25)
> /peripheral-anon (container)
> /unattached (container)
> /device[0] (arm926-arm-cpu)
> /unnamed-gpio-in[1] (irq)
> /unnamed-gpio-in[3] (irq)
> /unnamed-gpio-in[2] (irq)
> /unnamed-gpio-in[0] (irq)
>
> /device[15] (imx.i2c)
> /imx.i2c[0] (qemu:memory-region)
> /i2c-bus.0 (i2c-bus)
> /device[17] (imx.i2c)
> /imx.i2c[0] (qemu:memory-region)
> /i2c-bus.2 (i2c-bus)
> /device[16] (imx.i2c)
> /imx.i2c[0] (qemu:memory-region)
> /i2c-bus.1 (i2c-bus)
>
>
>
> Cheers,
>
> C.
Oh, great, that looks like a much better solution, thanks :)
--
Alastair D'Silva mob: 0423 762 819
skype:
alastair_dsilva
Twitter: @EvilDeece
blog: http://alastair.d-silva.org
Re: [Qemu-devel] [PATCH v2 1/6] arm: Uniquely name imx25 I2C buses.
On Wed, 2016-11-30 at 09:18 +0100, Cédric Le Goater wrote:
> On 11/30/2016 06:36 AM, Alastair D'Silva wrote:
> > From: Alastair D'Silva <alast...@d-silva.org>
> >
> > The imx25 chip provides 3 i2c buses, but they have all been named
> > "i2c", which makes it difficult to predict which bus a device will
> > be connected to when specified on the command line.
> >
> > This patch addresses the issue by naming the buses uniquely:
> > i2c.0 i2c.1 i2c.2
> >
> > Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
> > ---
> > hw/arm/imx25_pdk.c | 4 +---
> > hw/i2c/imx_i2c.c | 6 +-
> > 2 files changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
> > index 025b608..c6f04d3 100644
> > --- a/hw/arm/imx25_pdk.c
> > +++ b/hw/arm/imx25_pdk.c
> > @@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState
> > *machine)
> > * We add it here (only on qtest usage) to be able to do a
> > bit
> > * of simple qtest. See "make check" for details.
> > */
> > -i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(
> > >soc.i2c[0]),
> > - "i2c"),
> > - "ds1338", 0x68);
> > +i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68);
> > }
> > }
> >
> > diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
> > index 37e5a62..7be10fb 100644
> > --- a/hw/i2c/imx_i2c.c
> > +++ b/hw/i2c/imx_i2c.c
> > @@ -305,12 +305,16 @@ static const VMStateDescription
> > imx_i2c_vmstate = {
> > static void imx_i2c_realize(DeviceState *dev, Error **errp)
> > {
> > IMXI2CState *s = IMX_I2C(dev);
> > +static int bus_count;
>
> hmm, the static is ugly :/
>
> Isn't there other ways to achieve this naming ?
>
> Thanks,
>
> C.
>
I'm not seeing an obvious way around it. The busses are realized
independently (so I can't implement what we do with the aspeed i2c
busses), and it is named before fsl-imx25:fsl_imx25_realize() can apply
specific properties to the bus.
If you have any suggestions, I'm all ears.
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
Re: [Qemu-devel] [PATCH v2 0/6] Add support for the Epson RX8900 RTC to the aspeed board
On Wed, 2016-11-30 at 16:36 +1100, Alastair D'Silva wrote: > > This patch series adds support for the Epson RX8900 RTC to the > Aspeed board. > > The tests use the existing imx25 infrastructure, and some minor > changes have been made to uniquely identify the I2C buses. > > A NULL check have been added to eliminate empty i2cslave init > functions. > > Support for named interrupts has been implemented in qtest to > facilitate testing. Sorry, I missed a changelog... Changelog: v2: - Avoid using error_report - Fix TIE behaviour - Move temperature init out of reset, it should not change on a soft reset - Fix IRQ in test failures - Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. - Refactor to use the existing qemu trace infrastructure - Move the RX8900 definition into the aspeed machine init - It it possible for check_update_interrupt_seconds in the rx8900 test to return 6, depending on the alignment with the wall clock. - Support low voltage detection
[Qemu-devel] [PATCH v2 4/6] hw/timer: Add Epson RX8900 RTC support
From: Alastair D'Silva <alast...@d-silva.org>
This patch adds support for the Epson RX8900 I2C RTC.
The following chip features are implemented:
- RTC (wallclock based, ptimer 10x oversampling to pick up
wallclock transitions)
- Time update interrupt (per second/minute, wallclock based)
- Alarms (wallclock based)
- Temperature (set via a property)
- Countdown timer (emulated clock via ptimer)
- FOUT via GPIO (emulated clock via ptimer)
The following chip features are unimplemented:
- Low voltage detection
- i2c timeout
The implementation exports the following named GPIOs:
rx8900-interrupt-out
rx8900-fout-enable
rx8900-fout
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Chris Smart <ch...@distroguy.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 890
hw/timer/rx8900_regs.h | 139 +++
hw/timer/trace-events | 31 ++
5 files changed, 1063 insertions(+)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 000..e634819
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,890 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ * Chris Smart <ch...@distroguy.com>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE=en
+ *
+ * Not implemented:
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "trace.h"
+
+ #include
+
+ #include
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+typedef struct RX8900State {
+I2CSlave parent_obj;
+
+ptimer_state *sec_timer; /* triggered once per second */
+ptimer_state *fout_timer;
+ptimer_state *countdown_timer;
+bool fout;
+int64_t offset;
+uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+uint8_t wday_offset;
+uint8_t nvram[RX8900_NVRAM_SIZE];
+int32_t ptr; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+bool addr_byte;
+uint8_t last_interrupt_seconds;
+uint8_t last_update_interrupt_minutes;
+double supply_voltage;
+qemu_irq interrupt_pin;
+qemu_irq fout_pin;
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+.name = "rx8900",
+.version_id = 2,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+VMSTATE_PTIMER(sec_timer, RX8900State),
+VMSTATE_PTIMER(fout_timer, RX8900State),
+VMSTATE_PTIMER(countdown_timer, RX8900State),
+VMSTATE_BOOL(fout, RX8900State),
+VMSTATE_INT64(offset, RX8900State),
+VMSTATE_UINT8_V(weekday, RX8900State, 2),
+VMSTATE_UINT8_V(wday_offset, RX8900State, 2),
+VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE),
+VMSTATE_INT32(ptr, RX8900State),
+VMSTATE_BOOL(addr_byte, RX8900State),
+VMSTATE_UINT8_V(last_interrupt_seconds, RX8900State, 2),
+VMSTATE_UINT8_V(last_update_interrupt_minute
[Qemu-devel] [PATCH v2 1/6] arm: Uniquely name imx25 I2C buses.
From: Alastair D'Silva <alast...@d-silva.org>
The imx25 chip provides 3 i2c buses, but they have all been named
"i2c", which makes it difficult to predict which bus a device will
be connected to when specified on the command line.
This patch addresses the issue by naming the buses uniquely:
i2c.0 i2c.1 i2c.2
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/imx25_pdk.c | 4 +---
hw/i2c/imx_i2c.c | 6 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 025b608..c6f04d3 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState *machine)
* We add it here (only on qtest usage) to be able to do a bit
* of simple qtest. See "make check" for details.
*/
-i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(>soc.i2c[0]),
- "i2c"),
- "ds1338", 0x68);
+i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68);
}
}
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index 37e5a62..7be10fb 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -305,12 +305,16 @@ static const VMStateDescription imx_i2c_vmstate = {
static void imx_i2c_realize(DeviceState *dev, Error **errp)
{
IMXI2CState *s = IMX_I2C(dev);
+static int bus_count;
+char name[16];
+
+snprintf(name, sizeof(name), "i2c.%d", bus_count++);
memory_region_init_io(>iomem, OBJECT(s), _i2c_ops, s, TYPE_IMX_I2C,
IMX_I2C_MEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq);
-s->bus = i2c_init_bus(DEVICE(dev), "i2c");
+s->bus = i2c_init_bus(DEVICE(dev), name);
}
static void imx_i2c_class_init(ObjectClass *klass, void *data)
--
2.9.3
[Qemu-devel] [PATCH v2 3/6] qtest: Support named interrupts
From: Alastair D'Silva <alast...@d-silva.org>
The QTest framework cannot work with named interrupts. This patch
adds support for them, as well as the ability to manipulate them
from within a test.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/core/irq.c| 17 +-
include/hw/irq.h | 12 +--
qtest.c | 102 ++-
tests/libqtest.c | 87 ---
tests/libqtest.h | 59
5 files changed, 238 insertions(+), 39 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..6b0e694 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -134,15 +134,16 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
return qemu_allocate_irqs(proxy_irq_handler, target, n);
}
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
+qemu_irq qemu_irq_dup(qemu_irq in)
{
-int i;
-qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
-for (i = 0; i < n; i++) {
-*old_irqs[i] = *gpio_in[i];
-gpio_in[i]->handler = handler;
-gpio_in[i]->opaque = _irqs[i];
-}
+qemu_irq out = qemu_allocate_irq(in->handler, in->opaque, in->n);
+return out;
+}
+
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler, void
*opaque)
+{
+gpio_in->handler = handler;
+gpio_in->opaque = opaque;
}
static const TypeInfo irq_type_info = {
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..86d1d1e 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -58,8 +58,14 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
*/
qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-/* For internal use in qtest. Similar to qemu_irq_split, but operating
- on an existing vector of qemu_irq. */
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
+/**
+ * Duplicate an IRQ
+ * @param in the IRQ to deplicate
+ * @return a copy of the IRQ
+ */
+qemu_irq qemu_irq_dup(qemu_irq in);
+
+/* For internal use in qtest. */
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler, void
*opaque);
#endif
diff --git a/qtest.c b/qtest.c
index 46b99ae..2e09634 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,10 +159,16 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED NAME NUM LEVEL
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend
*chr,
va_end(ap);
}
+typedef struct qtest_irq {
+qemu_irq old_irq;
+char *name;
+bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
-qemu_irq old_irq = *(qemu_irq *)opaque;
-qemu_set_irq(old_irq, level);
+qtest_irq *data = (qtest_irq *)opaque;
+level = !!level;
+
+qemu_set_irq(data->old_irq, level);
-if (irq_levels[n] != level) {
+if (level != data->last_level) {
CharBackend *chr = _chr;
-irq_levels[n] = level;
qtest_send_prefix(chr);
-qtest_sendf(chr, "IRQ %s %d\n",
-level ? "raise" : "lower", n);
+
+if (data->name) {
+qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
+data->name, n, level);
+} else {
+qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+}
+
+data->last_level = level;
}
}
@@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+return;
}
if (irq_intercept_dev) {
@@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+return;
}
QLIST_FOREACH(ngl, >gpios, node) {
-/* We don't support intercept of named GPIOs yet */
[Qemu-devel] [PATCH v2 5/6] tests: Test all implemented RX8900 functionality
From: Alastair D'Silva <alast...@d-silva.org>
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
tests/Makefile.include | 2 +
tests/rx8900-test.c| 881 +
2 files changed, 883 insertions(+)
create mode 100644 tests/rx8900-test.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index e98d3b6..e52e355 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/rx8900-test$(EXESUF)
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
@@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y)
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
new file mode 100644
index 000..f822a41
--- /dev/null
+++ b/tests/rx8900-test.c
@@ -0,0 +1,881 @@
+/*
+ * QTest testcase for the Epson RX8900SA/CE RTC
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/rx8900_regs.h"
+#include "libqtest.h"
+#include "libqos/i2c.h"
+#include "qemu/timer.h"
+
+#define IMX25_I2C_0_BASE 0x43F8
+#define RX8900_TEST_ID "rx8900-test"
+#define RX8900_ADDR 0x32
+#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
+#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
+#define RX8900_FOUT "rx8900-fout"
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+return (x & 0x0f) + (x >> 4) * 10;
+}
+
+static inline uint8_t bin2bcd(uint8_t x)
+{
+return (x / 10 << 4) | (x % 10);
+}
+
+static void qmp_rx8900_set_temperature(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'temperature', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+static void qmp_rx8900_set_voltage(const char *id, double value)
+{
+QDict *response;
+
+response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'supply voltage', 'value': %f } }", id, value);
+g_assert(qdict_haskey(response, "return"));
+QDECREF(response);
+}
+
+/**
+ * Read an RX8900 register
+ * @param reg the address of the register
+ * @return the value of the register
+ */
+static uint8_t read_register(RX8900Addresses reg)
+{
+uint8_t val;
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, , 1);
+
+return val;
+}
+
+/**
+ * Write to an RX8900 register
+ * @param reg the address of the register
+ * @param val the value to write
+ */
+static uint8_t write_register(RX8900Addresses reg, uint8_t val)
+{
+uint8_t buf[2];
+
+buf[0] = reg;
+buf[1] = val;
+
+i2c_send(i2c, addr, buf, 2);
+
+return val;
+}
+
+/**
+ * Set bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void set_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value |= mask;
+write_register(reg, value);
+}
+
+/**
+ * Clear bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+uint8_t value = read_register(reg);
+value &= ~mask;
+write_register(reg, value);
+}
+
+/**
+ * Read a number of sequential RX8900 registers
+ * @param reg the address of the first register
+ * @param buf (out) an output buffer to stash the register values
+ * @param count the number of registers to read
+ */
+static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count)
+{
+uint8_t reg_address = (uint8_t)reg;
+
+i2c_send(i2c, addr, _address, 1);
+i2c_recv(i2c, addr, buf, count);
+}
+
+/**
+ * Write to a sequential number of RX8900 registers
+ * @param reg the address of the first reg
[Qemu-devel] [PATCH v2 6/6] arm: Add an RX8900 RTC to the ASpeed board
From: Alastair D'Silva <alast...@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/aspeed.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c7206fd..8de95f2 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -166,7 +166,19 @@ static const TypeInfo palmetto_bmc_type = {
static void ast2500_evb_init(MachineState *machine)
{
+AspeedSoCState *soc;
+I2CBus *i2c12;
+DeviceState *rx8900;
+
aspeed_board_init(machine, _boards[AST2500_EVB]);
+
+soc = ASPEED_SOC(object_resolve_path_component(OBJECT(machine), "soc"));
+
+i2c12 = aspeed_i2c_get_bus((DeviceState *)>i2c, 11);
+rx8900 = i2c_create_slave(i2c12, "rx8900", 0x32);
+
+qdev_connect_gpio_out_named(rx8900, "rx8900-interrupt-out", 0,
+qdev_get_gpio_in(DEVICE(>vic), 22));
}
static void ast2500_evb_class_init(ObjectClass *oc, void *data)
--
2.9.3
[Qemu-devel] [PATCH v2 2/6] hw/i2c: Add a NULL check for i2c slave init callbacks
From: Alastair D'Silva <alast...@d-silva.org>
Add a NULL check for i2c slave init callbacks, so that we no longer
need to implement empty init functions.
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/pxa2xx.c | 9 +
hw/arm/tosa.c | 7 ---
hw/arm/z2.c | 7 ---
hw/i2c/core.c | 6 +-
hw/timer/ds1338.c | 6 --
5 files changed, 6 insertions(+), 29 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 21ea1d6..bdcf6bc 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -1449,17 +1449,10 @@ static const VMStateDescription vmstate_pxa2xx_i2c = {
}
};
-static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = pxa2xx_i2c_slave_init;
k->event = pxa2xx_i2c_event;
k->recv = pxa2xx_i2c_rx;
k->send = pxa2xx_i2c_tx;
@@ -2070,7 +2063,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
if (!revision)
revision = "pxa270";
-
+
s->cpu = cpu_arm_init(revision);
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 1ee12f4..39d9dbb 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -202,12 +202,6 @@ static int tosa_dac_recv(I2CSlave *s)
return -1;
}
-static int tosa_dac_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static void tosa_tg_init(PXA2xxState *cpu)
{
I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
@@ -275,7 +269,6 @@ static void tosa_dac_class_init(ObjectClass *klass, void
*data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = tosa_dac_init;
k->event = tosa_dac_event;
k->recv = tosa_dac_recv;
k->send = tosa_dac_send;
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 68a92f3..b3a6bbd 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -263,12 +263,6 @@ static int aer915_recv(I2CSlave *slave)
return retval;
}
-static int aer915_init(I2CSlave *i2c)
-{
-/* Nothing to do. */
-return 0;
-}
-
static VMStateDescription vmstate_aer915_state = {
.name = "aer915",
.version_id = 1,
@@ -285,7 +279,6 @@ static void aer915_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = aer915_init;
k->event = aer915_event;
k->recv = aer915_recv;
k->send = aer915_send;
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index abd4c4c..ae3ca94 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -260,7 +260,11 @@ static int i2c_slave_qdev_init(DeviceState *dev)
I2CSlave *s = I2C_SLAVE(dev);
I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
-return sc->init(s);
+if (sc->init) {
+return sc->init(s);
+} else {
+return 0;
+}
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c
index 0112949..f5d04dd 100644
--- a/hw/timer/ds1338.c
+++ b/hw/timer/ds1338.c
@@ -198,11 +198,6 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data)
return 0;
}
-static int ds1338_init(I2CSlave *i2c)
-{
-return 0;
-}
-
static void ds1338_reset(DeviceState *dev)
{
DS1338State *s = DS1338(dev);
@@ -220,7 +215,6 @@ static void ds1338_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-k->init = ds1338_init;
k->event = ds1338_event;
k->recv = ds1338_recv;
k->send = ds1338_send;
--
2.9.3
[Qemu-devel] [PATCH v2 0/6] Add support for the Epson RX8900 RTC to the aspeed board
From: Alastair D'Silva <alast...@d-silva.org> This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. A NULL check have been added to eliminate empty i2cslave init functions. Support for named interrupts has been implemented in qtest to facilitate testing. Alastair D'Silva (6): arm: Uniquely name imx25 I2C buses. hw/i2c: Add a NULL check for i2c slave init callbacks qtest: Support named interrupts hw/timer: Add Epson RX8900 RTC support tests: Test all implemented RX8900 functionality arm: Add an RX8900 RTC to the ASpeed board default-configs/arm-softmmu.mak | 1 + hw/arm/aspeed.c | 12 + hw/arm/imx25_pdk.c | 4 +- hw/arm/pxa2xx.c | 9 +- hw/arm/tosa.c | 7 - hw/arm/z2.c | 7 - hw/core/irq.c | 17 +- hw/i2c/core.c | 6 +- hw/i2c/imx_i2c.c| 6 +- hw/timer/Makefile.objs | 2 + hw/timer/ds1338.c | 6 - hw/timer/rx8900.c | 890 hw/timer/rx8900_regs.h | 139 +++ hw/timer/trace-events | 31 ++ include/hw/irq.h| 12 +- qtest.c | 102 +++-- tests/Makefile.include | 2 + tests/libqtest.c| 87 +++- tests/libqtest.h| 59 +++ tests/rx8900-test.c | 881 +++ 20 files changed, 2208 insertions(+), 72 deletions(-) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c -- 2.9.3
Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board
On Tue, 2016-11-22 at 17:56 +0100, Cédric Le Goater wrote: > On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > From: Alastair D'Silva <alast...@d-silva.org> > > > > Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 > > If this is a board device, we should include it under a machine > routine. > > Is that for the palmetto ? The ast2500 does not have a RTC. > > Thanks, > > C. Ok -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819
Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts
On Tue, 2016-11-22 at 23:39 +0100, Paolo Bonzini wrote:
> On 22/11/2016 23:31, Alastair D'Silva wrote:
> >
> > >
> > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > +if (irq == NULL) {
> > > > > > > > +qtest_send_prefix(chr);
> > > > > > > > +qtest_send(chr, "FAIL Unknown IRQ\n");
> > > > > > > > +return;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +qemu_set_irq(irq, level);
> > > >
> > > > This seems wrong. The IRQ should not be modifiable by the
> > > > test.
> > > >
> > > > Paolo
> > > >
> > Thanks Paolo, could you please advise as to why that is?
Could you answer this please? I would like to understand why.
> > The situation I am addressing is that I device under test that
> > changes
> > behaviour when a GPIO line is raised. Is there another way I should
> > be
> > raising that line from within qtest?
>
> What causes the GPIO line to be raised in the normal emulated case?
>
>
It would be wired to a GPIO line from the host microcontroller, under
software control.
In this test case, the device is connected to a "borrowed" board via
the command line:
snprintf(args, sizeof(args), "-display none -machine imx25-pdk "
"-device rx8900,bus=i2c.0,address=0x%x,id=%s",
RX8900_ADDR, RX8900_TEST_ID);
I couldn't see a way to wire in the the GPIO to the host via the
command line, but even if there was, manipulating it would require
manipulating the host CPU, which would broaden the scope of the test.
At the moment, the test has no dependency on/interaction with the host
CPU, it's just using it to provide an I2C bus.
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
Re: [Qemu-devel] [PATCH 2/4] qtest: Support named interrupts
On Tue, 2016-11-22 at 18:24 +0100, Paolo Bonzini wrote:
>
> On 22/11/2016 18:22, Cédric Le Goater wrote:
> >
> > >
> > > +
> > > +g_assert(words[1]); /* device */
> > > +g_assert(words[2]); /* gpio list */
> > > +g_assert(words[3]); /* gpio line in list */
> > > +g_assert(words[4]); /* level */
> > > +dev = DEVICE(object_resolve_path(words[1], NULL));
> > > +if (!dev) {
> > > +qtest_send_prefix(chr);
> > > +qtest_send(chr, "FAIL Unknown device\n");
> > > +return;
> > > +}
> > > +
> > > +irq_num = atoi(words[3]);
> > > +level = atoi(words[4]);
> > > +
> > > +QLIST_FOREACH(ngl, >gpios, node) {
> > > +if (strcmp(words[2], ngl->name) == 0 && ngl->num_in
> > > > irq_num) {
> > > +irq = ngl->in[irq_num];
> > > +}
> > > +}
> > > +
> > > +if (irq == NULL) {
> > > +qtest_send_prefix(chr);
> > > +qtest_send(chr, "FAIL Unknown IRQ\n");
> > > +return;
> > > +}
> > > +
> > > +qemu_set_irq(irq, level);
>
> This seems wrong. The IRQ should not be modifiable by the test.
>
> Paolo
>
Thanks Paolo, could you please advise as to why that is?
The situation I am addressing is that I device under test that changes
behaviour when a GPIO line is raised. Is there another way I should be
raising that line from within qtest?
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
Re: [Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support
On Thu, 2016-11-17 at 09:29 +0100, Cédric Le Goater wrote: On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > From: Alastair D'Silva <alast...@d-silva.org> > > > > This patch adds support for the Epson RX8900 RTC chip. > > It would be nice to have a short list of the features this > chip has and also the main point of the design. I see you > are using a BH. > Ok > > > > > Signed-off-by: Alastair D'Silva <alast...@d-silva.org> > > --- > > default-configs/arm-softmmu.mak | 1 + > > hw/timer/Makefile.objs | 2 + > > hw/timer/rx8900.c | 891 > > > > hw/timer/rx8900_regs.h | 125 ++ > > tests/Makefile.include | 2 + > > tests/rx8900-test.c | 800 > > > > Nice test ! But Why aren't you using the aspeed machine in > qtest ? > > The reason I am asking is because the I2C controller model > is a little too simplistic in the way it handles the irq > status and we would need a test for it. > The aspeed machine is missing a bunch of I2C infrastructure (imx_i2c_create & friends) required to access it from the test harness, and I don't have the knowledge required to implement it. I am working on the premise that the RX8900 is an independent device, and so can be tested independently of the aspeed model. > > Also I would put the test case in another patch, after the > model and after patch 2 also which introduces named > interrupts for qtest. > Ok > > > > > 6 files changed, 1821 insertions(+) > > create mode 100644 hw/timer/rx8900.c > > create mode 100644 hw/timer/rx8900_regs.h > > create mode 100644 tests/rx8900-test.c > > > > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm- > > softmmu.mak > > index 6de3e16..adb600e 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y > > CONFIG_ALLWINNER_EMAC=y > > CONFIG_IMX_FEC=y > > CONFIG_DS1338=y > > +CONFIG_RX8900=y > > CONFIG_PFLASH_CFI01=y > > CONFIG_PFLASH_CFI02=y > > CONFIG_MICRODRIVE=y > > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs > > index 7ba8c23..fa028ac 100644 > > --- a/hw/timer/Makefile.objs > > +++ b/hw/timer/Makefile.objs > > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o > > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o > > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o > > common-obj-$(CONFIG_DS1338) += ds1338.o > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > common-obj-$(CONFIG_HPET) += hpet.o > > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o > > common-obj-$(CONFIG_M48T59) += m48t59.o > > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o > > common-obj-$(CONFIG_IMX) += imx_gpt.o > > common-obj-$(CONFIG_LM32) += lm32_timer.o > > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o > > +common-obj-$(CONFIG_RX8900) += rx8900.o > > > > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o > > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o > > diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c > > new file mode 100644 > > index 000..208a31b > > --- /dev/null > > +++ b/hw/timer/rx8900.c > > @@ -0,0 +1,891 @@ > > +/* > > + * Epson RX8900SA/CE Realtime Clock Module > > + * > > + * Copyright (c) 2016 IBM Corporation > > + * Authors: > > + * Alastair D'Silva <alast...@d-silva.org> > > + * > > + * This code is licensed under the GPL version 2 or later. See > > + * the COPYING file in the top-level directory. > > + * > > + * Datasheet available at: > > + * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE > > =en > > + * > > + * Not implemented: > > + * Implement Timer Counters > > + * Implement i2c timeout > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu-common.h" > > +#include "hw/i2c/i2c.h" > > +#include "hw/timer/rx8900_regs.h" > > +#include "hw/ptimer.h" > > +#include "qemu/main-loop.h" > > +#include "qemu/bcd.h" > > +#include "qemu/error-report.h" > > +#include "qemu/log.h" > > +#include "qapi/error.h" > > +#include "qapi/visitor.h" > > + > > + #include > > + > > + #include > > + > > +#define TYPE_RX8900 "rx8900" > > +#define RX89
[Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board
From: Alastair D'Silva <alast...@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/aspeed.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c7206fd..554ae20 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -100,6 +100,8 @@ static void aspeed_board_init(MachineState *machine,
{
AspeedBoardState *bmc;
AspeedSoCClass *sc;
+I2CBus *i2c12;
+DeviceState *rx8900;
bmc = g_new0(AspeedBoardState, 1);
object_initialize(>soc, (sizeof(bmc->soc)), cfg->soc_name);
@@ -137,6 +139,12 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+i2c12 = aspeed_i2c_get_bus((DeviceState *)>soc.i2c, 11);
+rx8900 = i2c_create_slave(i2c12, "rx8900", 0x32);
+
+qdev_connect_gpio_out_named(rx8900, "rx8900-interrupt-out", 0,
+qdev_get_gpio_in(DEVICE(>soc.vic), 22));
+
arm_load_kernel(ARM_CPU(first_cpu), _board_binfo);
}
--
2.7.4
[Qemu-devel] [PATCH 2/4] qtest: Support named interrupts
From: Alastair D'Silva <alast...@d-silva.org>
The QTest framework cannot work with named interrupts. This patch
adds support for them, as well as the ability to manipulate them
from within a test.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
qtest.c | 98 ++--
tests/libqtest.c | 87 ++---
tests/libqtest.h | 59 ++
3 files changed, 216 insertions(+), 28 deletions(-)
diff --git a/qtest.c b/qtest.c
index 46b99ae..a56503b 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,10 +159,16 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED NAME NUM LEVEL
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend
*chr,
va_end(ap);
}
+typedef struct qtest_irq {
+qemu_irq old_irq;
+char *name;
+bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
-qemu_irq old_irq = *(qemu_irq *)opaque;
-qemu_set_irq(old_irq, level);
+qtest_irq *data = (qtest_irq *)opaque;
+level = !!level;
+
+qemu_set_irq(data->old_irq, level);
-if (irq_levels[n] != level) {
+if (level != data->last_level) {
CharBackend *chr = _chr;
-irq_levels[n] = level;
qtest_send_prefix(chr);
-qtest_sendf(chr, "IRQ %s %d\n",
-level ? "raise" : "lower", n);
+
+if (data->name) {
+qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
+data->name, n, level);
+} else {
+qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+}
+
+data->last_level = level;
}
}
@@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+return;
}
if (irq_intercept_dev) {
@@ -299,33 +318,69 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+return;
}
QLIST_FOREACH(ngl, >gpios, node) {
-/* We don't support intercept of named GPIOs yet */
-if (ngl->name) {
-continue;
-}
if (words[0][14] == 'o') {
int i;
for (i = 0; i < ngl->num_out; ++i) {
-qemu_irq *disconnected = g_new0(qemu_irq, 1);
-qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
- disconnected, i);
+qtest_irq *data = g_new0(qtest_irq, 1);
+data->name = ngl->name;
+qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, data,
+i);
-*disconnected = qdev_intercept_gpio_out(dev, icpt,
+data->old_irq = qdev_intercept_gpio_out(dev, icpt,
ngl->name, i);
}
} else {
-qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
- ngl->num_in);
+qtest_irq *data = g_new0(qtest_irq, 1);
+data->old_irq = *ngl->in;
+data->name = ngl->name;
+qemu_irq_intercept_in(ngl->in, qtest_irq_handler, ngl->num_in);
}
}
irq_intercept_dev = dev;
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+} else if (strcmp(words[0], "irq_set") == 0) {
+DeviceState *dev;
+NamedGPIOList *ngl;
+int level;
+qemu_irq irq = NULL;
+int irq_num;
+
+g_assert(words[1]); /* device */
+g_assert(words[2]); /* gpio list */
+
[Qemu-devel] [PATCH 3/4] hw/timer: Add Epson RX8900 RTC support
From: Alastair D'Silva <alast...@d-silva.org>
This patch adds support for the Epson RX8900 RTC chip.
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 891
hw/timer/rx8900_regs.h | 125 ++
tests/Makefile.include | 2 +
tests/rx8900-test.c | 800
6 files changed, 1821 insertions(+)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
create mode 100644 tests/rx8900-test.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 000..208a31b
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,891 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alast...@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE=en
+ *
+ * Not implemented:
+ * Implement Timer Counters
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+ #include
+
+ #include
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+static bool log;
+
+typedef struct RX8900State {
+I2CSlave parent_obj;
+
+ptimer_state *sec_timer; /* triggered once per second */
+ptimer_state *fout_timer;
+ptimer_state *countdown_timer;
+bool fout;
+int64_t offset;
+uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+uint8_t wday_offset;
+uint8_t nvram[RX8900_NVRAM_SIZE];
+int32_t ptr; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+bool addr_byte;
+uint8_t last_interrupt_seconds;
+uint8_t last_update_interrupt_minutes;
+qemu_irq interrupt_pin;
+qemu_irq fout_pin;
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+.name = "rx8900",
+.version_id = 2,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+VMSTATE_PTIMER(sec_timer, RX8900State),
+VMSTATE_PTIMER(fout_timer, RX8900State),
+VMSTATE_PTIMER(countdown_timer, RX8900State),
+VMSTATE_BOOL(fout, RX8900State),
+VMSTATE_INT64(offset, RX8900State),
+VMSTATE_UINT8_V(weekday, RX8900State, 2),
+VMSTATE_UINT8_V(wday_offset, RX8900State, 2),
+VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE),
+VMSTATE_INT32(ptr, RX8900State),
+VMSTATE_BOOL(addr_byte, RX8900State),
+VMSTATE_UINT8_V(last_interrupt_seconds, RX8900State, 2),
+VMSTATE_UINT8_V(last_update_interrupt_minutes, RX8900State, 2),
+VMSTATE_END_OF_LIST()
+}
+};
+
+static void rx8900_reset(DeviceState *dev);
+static void disable_countdown_timer(RX8900State *s);
+static void enable_countdown_timer(RX8900State *s);
+static void disable_timer(RX8900State *s);
+static void enable_timer(RX8900State *s);
+
+#ifdef RX8900_TRACE
+#define RX8900_TRACE_BUF_SIZE 256
+/**
+ * Emit a trace message
+ * @param file the source filename
+ * @param line the line number the message was emitted from
+ * @param dev
[Qemu-devel] [PATCH 1/4] arm: Uniquely name imx25 I2C buses.
From: Alastair D'Silva <alast...@d-silva.org>
The imx25 chip provides 3 i2c buses, but they have all been named
"i2c", which makes it difficult to predict which bus a device will
be connected to when specified on the command line.
This patch addresses the issue by naming the buses uniquely:
i2c.0 i2c.1 i2c.2
Signed-off-by: Alastair D'Silva <alast...@d-silva.org>
---
hw/arm/imx25_pdk.c | 2 +-
hw/i2c/imx_i2c.c | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 025b608..1f7512c 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -139,7 +139,7 @@ static void imx25_pdk_init(MachineState *machine)
* of simple qtest. See "make check" for details.
*/
i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(>soc.i2c[0]),
- "i2c"),
+ "i2c.0"),
"ds1338", 0x68);
}
}
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index 37e5a62..7be10fb 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -305,12 +305,16 @@ static const VMStateDescription imx_i2c_vmstate = {
static void imx_i2c_realize(DeviceState *dev, Error **errp)
{
IMXI2CState *s = IMX_I2C(dev);
+static int bus_count;
+char name[16];
+
+snprintf(name, sizeof(name), "i2c.%d", bus_count++);
memory_region_init_io(>iomem, OBJECT(s), _i2c_ops, s, TYPE_IMX_I2C,
IMX_I2C_MEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), >iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), >irq);
-s->bus = i2c_init_bus(DEVICE(dev), "i2c");
+s->bus = i2c_init_bus(DEVICE(dev), name);
}
static void imx_i2c_class_init(ObjectClass *klass, void *data)
--
2.7.4
[Qemu-devel] [PATCH 0/4] Add support for the Epson RX8900 RTC to the aspeed board
From: Alastair D'Silva <alast...@d-silva.org> This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. Support for named interrupts has been implemented in qtest to facilitate testing. Alastair D'Silva (4): arm: Uniquely name imx25 I2C buses. qtest: Support named interrupts hw/timer: Add Epson RX8900 RTC support arm: Add an RX8900 RTC to the ASpeed board default-configs/arm-softmmu.mak | 1 + hw/arm/aspeed.c | 8 + hw/arm/imx25_pdk.c | 2 +- hw/i2c/imx_i2c.c| 6 +- hw/timer/Makefile.objs | 2 + hw/timer/rx8900.c | 891 hw/timer/rx8900_regs.h | 125 ++ qtest.c | 98 +++-- tests/Makefile.include | 2 + tests/libqtest.c| 87 +++- tests/libqtest.h| 59 +++ tests/rx8900-test.c | 800 12 files changed, 2051 insertions(+), 30 deletions(-) create mode 100644 hw/timer/rx8900.c create mode 100644 hw/timer/rx8900_regs.h create mode 100644 tests/rx8900-test.c -- 2.7.4
