[Qemu-devel] [PULL 0/2] OpenRISC patch queue for 2.3
Hi Anthony, This is my OpenRISC patch queue for 2.3, it have been well tested, please pull. Thanks to Christian and Sebastian, they made the LD/ST updated. Regards, Jia The following changes since commit 16017c48547960539fcadb1f91d252124f442482: softfloat: Clarify license status (2015-01-29 16:45:45 +) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to bcf7d6e965d5323cae32f18c5e6c8af173c40d41: target-openrisc: Add l.lwa/l.swa support (2015-02-03 09:55:41 +0800) Christian Svensson (1): target-openrisc: Add l.lwa/l.swa support Sebastian Macke (1): target-openrisc: Separate of load/store instructions target-openrisc/cpu.h | 3 + target-openrisc/interrupt.c | 3 + target-openrisc/translate.c | 188 ++-- 3 files changed, 153 insertions(+), 41 deletions(-)
[Qemu-devel] [PULL 2/2] target-openrisc: Add l.lwa/l.swa support
From: Christian Svensson b...@cmd.nu
This patch adds support for atomic locks and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock implementation of musl
Signed-off-by: Christian Svensson b...@cmd.nu
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviwed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.h | 3 ++
target-openrisc/interrupt.c | 3 ++
target-openrisc/translate.c | 74 -
3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 69b96c6..abdba75 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -302,6 +302,9 @@ typedef struct CPUOpenRISCState {
in solt so far. */
uint32_t btaken; /* the SR_F bit */
+target_ulong lock_addr; /* Atomicity lock address. */
+target_ulong lock_value; /* Atomicity lock value. */
+
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index e480cfd..68d554c 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -54,6 +54,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env-tlb-cpu_openrisc_map_address_data = cpu_openrisc_get_phys_nommu;
env-tlb-cpu_openrisc_map_address_code = cpu_openrisc_get_phys_nommu;
+/* invalidate lock */
+env-cpu_lock_addr = -1;
+
if (cs-exception_index 0 cs-exception_index EXCP_NR) {
env-pc = (cs-exception_index 8);
} else {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 77b1c35..6401b4b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -55,6 +55,8 @@ typedef struct DisasContext {
static TCGv_ptr cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
+static TCGv cpu_lock_addr;
+static TCGv cpu_lock_value;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
@@ -82,6 +84,12 @@ void openrisc_translate_init(void)
env_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, flags),
flags);
+cpu_lock_addr = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUOpenRISCState, lock_addr),
+ lock_addr);
+cpu_lock_value = tcg_global_mem_new(TCG_AREG0,
+offsetof(CPUOpenRISCState, lock_value),
+lock_value);
cpu_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, pc), pc);
cpu_npc = tcg_global_mem_new(TCG_AREG0,
@@ -254,17 +262,67 @@ static void gen_jump(DisasContext *dc, uint32_t imm,
uint32_t reg, uint32_t op0)
gen_sync_flags(dc);
}
+/* According to the OpenRISC specification we should poison our atomic lock
+ * if any other store is detected to the same address. For the sake of speed
+ * and because we're single-threaded we guarantee that atomic stores
+ * fail only if an atomic load or another atomic store
+ * is executed.
+ *
+ * To prevent the potential case of an ordinary store, we save
+ * the *value* of the address at the lock time. */
+
+static void gen_atomic_load(TCGv tD, TCGv t0, DisasContext *dc)
+{
+tcg_gen_qemu_ld_tl(tD, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_mov_i32(cpu_lock_addr, t0);
+tcg_gen_mov_i32(cpu_lock_value, tD);
+}
+
+static void gen_atomic_store(TCGv tB, TCGv t0, DisasContext *dc)
+{
+int store_fail;
+int store_done;
+
+store_fail = gen_new_label();
+store_done = gen_new_label();
+
+/* check address */
+tcg_gen_brcond_i32(TCG_COND_NE, t0, cpu_lock_addr, store_fail);
+
+/* check value */
+TCGv val = tcg_temp_new();
+tcg_gen_qemu_ld_tl(val, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_brcond_i32(TCG_COND_NE, val, cpu_lock_value, store_fail);
+tcg_temp_free(val);
+
+/* success of atomic access */
+tcg_gen_qemu_st_tl(tB, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
+tcg_gen_br(store_done);
+
+gen_set_label(store_fail);
+tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
+
+gen_set_label(store_done);
+/* the atomic store invalidates the lock address. */
+tcg_gen_movi_i32(cpu_lock_addr, -1);
+}
+
static void gen_loadstore(DisasContext *dc, uint32 op0,
uint32_t ra, uint32_t rb, uint32_t rd,
uint32_t offset)
{
TCGv t0 = cpu_R[ra];
if (offset != 0) {
-t0 = tcg_temp_new();
+t0 = tcg_temp_local_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(offset, 16));
}
switch (op0) {
+case 0x1b:/* l.lwa */
+gen_atomic_load(cpu_R[rd], t0, dc);
+break;
+
case 0x21
[Qemu-devel] [PULL 1/2] target-openrisc: Separate of load/store instructions
From: Sebastian Macke sebast...@macke.de
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks for a zero offset and optimizes it.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviwed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 116
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b90181d..77b1c35 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -254,6 +254,63 @@ static void gen_jump(DisasContext *dc, uint32_t imm,
uint32_t reg, uint32_t op0)
gen_sync_flags(dc);
}
+static void gen_loadstore(DisasContext *dc, uint32 op0,
+ uint32_t ra, uint32_t rb, uint32_t rd,
+ uint32_t offset)
+{
+TCGv t0 = cpu_R[ra];
+if (offset != 0) {
+t0 = tcg_temp_new();
+tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(offset, 16));
+}
+
+switch (op0) {
+case 0x21:/* l.lwz */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_TEUL);
+break;
+
+case 0x22:/* l.lws */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_TESL);
+break;
+
+case 0x23:/* l.lbz */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_UB);
+break;
+
+case 0x24:/* l.lbs */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_SB);
+break;
+
+case 0x25:/* l.lhz */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_TEUW);
+break;
+
+case 0x26:/* l.lhs */
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, MO_TESW);
+break;
+
+case 0x35:/* l.sw */
+tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc-mem_idx, MO_TEUL);
+break;
+
+case 0x36:/* l.sb */
+tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc-mem_idx, MO_UB);
+break;
+
+case 0x37:/* l.sh */
+tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc-mem_idx, MO_TEUW);
+break;
+
+default:
+break;
+}
+
+if (offset != 0) {
+tcg_temp_free(t0);
+}
+
+}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
@@ -710,7 +767,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
-TCGMemOp mop;
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
@@ -843,48 +899,37 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS(l.ld r%d, r%d, %d\n, rd, ra, I16);
-check_ob64s(dc);
-mop = MO_TEQ;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
#endif*/
case 0x21:/* l.lwz */
LOG_DIS(l.lwz r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_TEUL;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
+break;
case 0x22:/* l.lws */
LOG_DIS(l.lws r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_TESL;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
+break;
case 0x23:/* l.lbz */
LOG_DIS(l.lbz r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_UB;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
+break;
case 0x24:/* l.lbs */
LOG_DIS(l.lbs r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_SB;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
+break;
case 0x25:/* l.lhz */
LOG_DIS(l.lhz r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_TEUW;
-goto do_load;
+gen_loadstore(dc, op0, ra, rb, rd, I16);
+break;
case 0x26:/* l.lhs */
LOG_DIS(l.lhs r%d, r%d, %d\n, rd, ra, I16);
-mop = MO_TESW;
-goto do_load;
-
-do_load:
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, mop);
-tcg_temp_free(t0);
-}
+gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x27:/* l.addi */
@@ -1021,33 +1066,22 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS(l.sd %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-check_ob64s(dc);
-mop = MO_TEQ;
-goto do_store;
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
#endif*/
case 0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-mop = MO_TEUL;
-goto do_store;
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
+break;
case 0x36:/* l.sb */
LOG_DIS(l.sb %d, r%d, r%d, %d\n, I5, ra, rb, I11
Re: [Qemu-devel] [PATCH 2/2] target-openrisc: Add l.lwa/l.swa support
On Mon, Jan 26, 2015 at 6:18 PM, Sebastian Macke sebast...@macke.de wrote:
Hi Jia,
On 1/26/2015 10:50 AM, Jia Liu wrote:
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke sebast...@macke.de
wrote:
From: Christian Svensson b...@cmd.nu
This patch adds support for atomic locks
and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock implementation of musl
Signed-off-by: Christian Svensson b...@cmd.nu
Signed-off-by: Sebastian Macke sebast...@macke.de
---
target-openrisc/cpu.h | 3 ++
target-openrisc/interrupt.c | 3 ++
target-openrisc/translate.c | 77
++---
3 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 69b96c6..abdba75 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -302,6 +302,9 @@ typedef struct CPUOpenRISCState {
in solt so far. */
uint32_t btaken; /* the SR_F bit */
+target_ulong lock_addr; /* Atomicity lock address. */
+target_ulong lock_value; /* Atomicity lock value. */
+
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index e480cfd..68d554c 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -54,6 +54,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env-tlb-cpu_openrisc_map_address_data =
cpu_openrisc_get_phys_nommu;
env-tlb-cpu_openrisc_map_address_code =
cpu_openrisc_get_phys_nommu;
+/* invalidate lock */
+env-cpu_lock_addr = -1;
+
if (cs-exception_index 0 cs-exception_index EXCP_NR) {
env-pc = (cs-exception_index 8);
} else {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 543aa67..6401b4b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -55,6 +55,8 @@ typedef struct DisasContext {
static TCGv_ptr cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
+static TCGv cpu_lock_addr;
+static TCGv cpu_lock_value;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
@@ -82,6 +84,12 @@ void openrisc_translate_init(void)
env_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState,
flags),
flags);
+cpu_lock_addr = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUOpenRISCState,
lock_addr),
+ lock_addr);
+cpu_lock_value = tcg_global_mem_new(TCG_AREG0,
+offsetof(CPUOpenRISCState,
lock_value),
+lock_value);
cpu_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, pc), pc);
cpu_npc = tcg_global_mem_new(TCG_AREG0,
@@ -254,17 +262,67 @@ static void gen_jump(DisasContext *dc, uint32_t
imm, uint32_t reg, uint32_t op0)
gen_sync_flags(dc);
}
+/* According to the OpenRISC specification we should poison our atomic
lock
+ * if any other store is detected to the same address. For the sake of
speed
+ * and because we're single-threaded we guarantee that atomic stores
+ * fail only if an atomic load or another atomic store
+ * is executed.
+ *
+ * To prevent the potential case of an ordinary store, we save
+ * the *value* of the address at the lock time. */
+
+static void gen_atomic_load(TCGv tD, TCGv t0, DisasContext *dc)
+{
+tcg_gen_qemu_ld_tl(tD, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_mov_i32(cpu_lock_addr, t0);
+tcg_gen_mov_i32(cpu_lock_value, tD);
+}
+
+static void gen_atomic_store(TCGv tB, TCGv t0, DisasContext *dc)
+{
+int store_fail;
+int store_done;
+
+store_fail = gen_new_label();
+store_done = gen_new_label();
+
+/* check address */
+tcg_gen_brcond_i32(TCG_COND_NE, t0, cpu_lock_addr, store_fail);
+
+/* check value */
+TCGv val = tcg_temp_new();
+tcg_gen_qemu_ld_tl(val, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_brcond_i32(TCG_COND_NE, val, cpu_lock_value, store_fail);
+tcg_temp_free(val);
+
+/* success of atomic access */
+tcg_gen_qemu_st_tl(tB, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
+tcg_gen_br(store_done);
+
+gen_set_label(store_fail);
+tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
+
+gen_set_label(store_done);
+/* the atomic store invalidates the lock address. */
+tcg_gen_movi_i32(cpu_lock_addr, -1);
+}
+
static void gen_loadstore(DisasContext *dc, uint32 op0,
uint32_t ra, uint32_t rb, uint32_t rd,
uint32_t offset)
{
TCGv t0 = cpu_R
Re: [Qemu-devel] [PATCH 2/2] target-openrisc: Add l.lwa/l.swa support
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke sebast...@macke.de wrote:
From: Christian Svensson b...@cmd.nu
This patch adds support for atomic locks
and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock implementation of musl
Signed-off-by: Christian Svensson b...@cmd.nu
Signed-off-by: Sebastian Macke sebast...@macke.de
---
target-openrisc/cpu.h | 3 ++
target-openrisc/interrupt.c | 3 ++
target-openrisc/translate.c | 77
++---
3 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 69b96c6..abdba75 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -302,6 +302,9 @@ typedef struct CPUOpenRISCState {
in solt so far. */
uint32_t btaken; /* the SR_F bit */
+target_ulong lock_addr; /* Atomicity lock address. */
+target_ulong lock_value; /* Atomicity lock value. */
+
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index e480cfd..68d554c 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -54,6 +54,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env-tlb-cpu_openrisc_map_address_data = cpu_openrisc_get_phys_nommu;
env-tlb-cpu_openrisc_map_address_code = cpu_openrisc_get_phys_nommu;
+/* invalidate lock */
+env-cpu_lock_addr = -1;
+
if (cs-exception_index 0 cs-exception_index EXCP_NR) {
env-pc = (cs-exception_index 8);
} else {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 543aa67..6401b4b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -55,6 +55,8 @@ typedef struct DisasContext {
static TCGv_ptr cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
+static TCGv cpu_lock_addr;
+static TCGv cpu_lock_value;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
@@ -82,6 +84,12 @@ void openrisc_translate_init(void)
env_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, flags),
flags);
+cpu_lock_addr = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUOpenRISCState, lock_addr),
+ lock_addr);
+cpu_lock_value = tcg_global_mem_new(TCG_AREG0,
+offsetof(CPUOpenRISCState,
lock_value),
+lock_value);
cpu_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, pc), pc);
cpu_npc = tcg_global_mem_new(TCG_AREG0,
@@ -254,17 +262,67 @@ static void gen_jump(DisasContext *dc, uint32_t imm,
uint32_t reg, uint32_t op0)
gen_sync_flags(dc);
}
+/* According to the OpenRISC specification we should poison our atomic lock
+ * if any other store is detected to the same address. For the sake of speed
+ * and because we're single-threaded we guarantee that atomic stores
+ * fail only if an atomic load or another atomic store
+ * is executed.
+ *
+ * To prevent the potential case of an ordinary store, we save
+ * the *value* of the address at the lock time. */
+
+static void gen_atomic_load(TCGv tD, TCGv t0, DisasContext *dc)
+{
+tcg_gen_qemu_ld_tl(tD, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_mov_i32(cpu_lock_addr, t0);
+tcg_gen_mov_i32(cpu_lock_value, tD);
+}
+
+static void gen_atomic_store(TCGv tB, TCGv t0, DisasContext *dc)
+{
+int store_fail;
+int store_done;
+
+store_fail = gen_new_label();
+store_done = gen_new_label();
+
+/* check address */
+tcg_gen_brcond_i32(TCG_COND_NE, t0, cpu_lock_addr, store_fail);
+
+/* check value */
+TCGv val = tcg_temp_new();
+tcg_gen_qemu_ld_tl(val, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_brcond_i32(TCG_COND_NE, val, cpu_lock_value, store_fail);
+tcg_temp_free(val);
+
+/* success of atomic access */
+tcg_gen_qemu_st_tl(tB, t0, dc-mem_idx, MO_TEUL);
+tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
+tcg_gen_br(store_done);
+
+gen_set_label(store_fail);
+tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
+
+gen_set_label(store_done);
+/* the atomic store invalidates the lock address. */
+tcg_gen_movi_i32(cpu_lock_addr, -1);
+}
+
static void gen_loadstore(DisasContext *dc, uint32 op0,
uint32_t ra, uint32_t rb, uint32_t rd,
uint32_t offset)
{
TCGv t0 = cpu_R[ra];
if (offset != 0) {
-t0 = tcg_temp_new();
+t0 = tcg_temp_local_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(offset, 16));
Re: [Qemu-devel] [PATCH 1/2] target-openrisc: Separate of load/store instructions
0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-mop = MO_TEUL;
-goto do_store;
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
+break;
case 0x36:/* l.sb */
LOG_DIS(l.sb %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-mop = MO_UB;
-goto do_store;
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
+break;
case 0x37:/* l.sh */
LOG_DIS(l.sh %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-mop = MO_TEUW;
-goto do_store;
-
-do_store:
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc-mem_idx, mop);
-tcg_temp_free(t0);
-}
+gen_loadstore(dc, op0, ra, rb, rd, tmp);
break;
default:
Thank you, it is good to separate the related instructions.
Reviwed-by: Jia Liu pro...@gmail.com
--
2.2.2
Regards,
Jia
Re: [Qemu-devel] [PATCH v2] target-openrisc: bugfix for dec_sys to decode instructions correctly
Hi David, On Wed, Jan 7, 2015 at 1:06 AM, David Morrison dmorri...@invlim.com wrote: Fixed the decoding of system instructions (starting with 0x2) in dec_sys() in translate.c. In particular, the l.trap instruction is now correctly decoded, which enables for singlestepping and breakpoints to be set in GDB. Signed-off-by: David R. Morrison dmorri...@invlim.com --- target-openrisc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Changes since previous version: * Added 'signed-off-by' line; sorry to forget this before! diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 407bd97..d36278f 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1320,7 +1320,7 @@ static void dec_sys(DisasContext *dc, uint32_t insn) #ifdef OPENRISC_DISAS uint32_t K16; #endif -op0 = extract32(insn, 16, 8); +op0 = extract32(insn, 16, 10); Thank you for pointing this. Acked-by: Jia Liu pro...@gmail.com #ifdef OPENRISC_DISAS K16 = extract32(insn, 0, 16); #endif -- 2.2.1 Regards, Jia
Re: [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support
Hi Valentin,
On Sun, Oct 5, 2014 at 7:03 PM, Valentin Manea valentin.ma...@gmail.com wrote:
Create new OpenRISC machine(asim) with default IDE support. It will
incude more peripherals in order to run a fully fledged Linux computer.
Signed-off-by: Valentin Manea valentin.ma...@gmail.com
---
default-configs/or32-softmmu.mak | 3 +
hw/openrisc/Makefile.objs| 1 +
hw/openrisc/openrisc_asim.c | 202
+++
3 files changed, 206 insertions(+)
create mode 100644 hw/openrisc/openrisc_asim.c
diff --git a/default-configs/or32-softmmu.mak
b/default-configs/or32-softmmu.mak
index cce4746..c3ff078 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -2,3 +2,6 @@
CONFIG_SERIAL=y
CONFIG_OPENCORES_ETH=y
+CONFIG_IDE_CORE=y
+CONFIG_IDE_QDEV=y
+CONFIG_IDE_MMIO=y
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index 61246b1..f266f5d 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1,2 +1,3 @@
obj-y = pic_cpu.o cputimer.o
obj-y += openrisc_sim.o
+obj-y += openrisc_asim.o
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
new file mode 100644
index 000..80aa5ed
--- /dev/null
+++ b/hw/openrisc/openrisc_asim.c
@@ -0,0 +1,202 @@
+/*
+ * OpenRISC simulator with more peripherals
+ *
+ * Copyright (c) 2011-2014 Jia Liu pro...@gmail.com
+ * Feng Gao gf91...@gmail.com
+ * Valentin Manea valentin.ma...@gmail.com
+ *
+ * This OpenRISC machine supports more hardware - same configuration as the
+ * jor1k(http://s-macke.github.io/jor1k). Currently the default Linux branch
+ * does not have all the support for this machine so the jor1k Linux kernel
is
+ * needed for more advanced usecases: X support, compiling etc. You can
download
+ * a precompiled image here http://mrs.ro/dl/or1k/vmlinux or compile it using
+ * the instructions at https://github.com/s-macke/jor1k/wiki
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
http://www.gnu.org/licenses/.
+ */
+
+#include hw/hw.h
+#include hw/boards.h
+#include elf.h
+#include hw/char/serial.h
+#include net/net.h
+#include hw/loader.h
+#include hw/ide.h
+#include exec/address-spaces.h
+#include sysemu/sysemu.h
+#include hw/sysbus.h
+#include sysemu/blockdev.h
+#include sysemu/qtest.h
+
+#define KERNEL_LOAD_ADDR 0x100
+
+enum {
+OR_UART0,
+OR_IDE,
+OR_OPENETH
+};
+
+static hwaddr mem_map[] = {
+[OR_UART0] = 0x9000,
+[OR_IDE] = 0x9e00,
+[OR_OPENETH] = 0x9200,
+};
+
+
+static void main_cpu_reset(void *opaque)
+{
+OpenRISCCPU *cpu = opaque;
+
+cpu_reset(CPU(cpu));
+}
+
+static void openrisc_sim_ide_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ qemu_irq irq)
+{
+DeviceState *dev;
+SysBusDevice *busdev;
+DriveInfo *dinfo;
+
+
+dinfo = drive_get(IF_IDE, 0, 0);
+if (!dinfo) {
+return;
+}
+dev = qdev_create(NULL, mmio-ide);
+busdev = SYS_BUS_DEVICE(dev);
+sysbus_connect_irq(busdev, 0, irq);
+qdev_prop_set_uint32(dev, shift, 2);
+qdev_init_nofail(dev);
+memory_region_add_subregion(address_space, base,
+sysbus_mmio_get_region(busdev, 0));
+memory_region_add_subregion(address_space, descriptors,
+sysbus_mmio_get_region(busdev, 1));
+mmio_ide_init_drives(dev, dinfo, NULL);
+}
+
+static void openrisc_sim_net_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ qemu_irq irq, NICInfo *nd)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+dev = qdev_create(NULL, open_eth);
+qdev_set_nic_properties(dev, nd);
+qdev_init_nofail(dev);
+
+s = SYS_BUS_DEVICE(dev);
+sysbus_connect_irq(s, 0, irq);
+memory_region_add_subregion(address_space, base,
+sysbus_mmio_get_region(s, 0));
+memory_region_add_subregion(address_space, descriptors,
+sysbus_mmio_get_region(s, 1
Re: [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support
(void *opaque, int version_id)
+{
+OCFBState *s = opaque;
+/* Make sure we redraw, and at the right size */
+ocfb_invalidate_display(s);
+return 0;
+}
+
+static const GraphicHwOps ocfb_gfx_ops = {
+.invalidate = ocfb_invalidate_display,
+.gfx_update = ocfb_update_display,
+};
+
+static int ocfb_initfn(SysBusDevice *sbd)
+{
+DeviceState *dev = DEVICE(sbd);
+OCFBState *s = OCFB(dev);
+
+memory_region_init_io(s-iomem, OBJECT(s), ocfb_ops, s, ocfb,
0x1000);
+sysbus_init_mmio(sbd, s-iomem);
+sysbus_init_irq(sbd, s-irq);
+
+s-con = graphic_console_init(dev, 0, ocfb_gfx_ops, s);
+
+return 0;
+}
+
+static void ocfb_init(Object *obj)
+{
+OCFBState *s = OCFB(obj);
+
+s-fb = 0;
+s-cols = 0;
+s-rows = 0;
+s-bpp = 0;
+}
+
+static void ocfb_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+k-init = ocfb_initfn;
+set_bit(DEVICE_CATEGORY_DISPLAY, dc-categories);
+dc-vmsd = vmstate_ocfb;
+}
+
+static const TypeInfo ocfb_info = {
+.name = TYPE_OCFB,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(OCFBState),
+.instance_init = ocfb_init,
+.class_init= ocfb_class_init,
+};
+
+static void ocfb_register_types(void)
+{
+type_register_static(ocfb_info);
+}
+
+type_init(ocfb_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 80aa5ed..7752d22 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -44,13 +44,15 @@
enum {
OR_UART0,
OR_IDE,
-OR_OPENETH
+OR_OPENETH,
+OR_FRAMEBUFFER
};
static hwaddr mem_map[] = {
[OR_UART0] = 0x9000,
[OR_IDE] = 0x9e00,
[OR_OPENETH] = 0x9200,
+[OR_FRAMEBUFFER] = 0x9100
};
@@ -183,6 +185,10 @@ static void openrisc_sim_init(MachineState *machine)
openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
mem_map[OR_IDE] + 0x100, cpu-env.irq[15]);
+/* OpenCores FrameBuffer device */
+sysbus_create_simple(ocfb, mem_map[OR_FRAMEBUFFER], cpu-env.irq[8]);
+
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
Re: [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard device support
);
+
+qemu_add_kbd_event_handler(ockb_keycode, s);
+
+return 0;
+}
+
+
+static const VMStateDescription vmstate_ockb_regs = {
+.name = ockb,
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_UINT8_ARRAY(data, OCKBState, 16),
+VMSTATE_UINT32(rptr, OCKBState),
+VMSTATE_UINT32(wptr, OCKBState),
+VMSTATE_UINT32(count, OCKBState),
+VMSTATE_END_OF_LIST(),
+},
+};
+
+static void ockb_init(Object *obj)
+{
+OCKBState *s = OCKB(obj);
+
+memset(s-data, 0, sizeof(s-data));
+s-rptr = 0;
+s-wptr = 0;
+s-count = 0;
+}
+
+static void ockb_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+k-init = ockb_initfn;
+dc-desc = OpenCores Keyboard controller;
+dc-vmsd = vmstate_ockb_regs;
+}
+
+static const TypeInfo ockb_info = {
+.name = TYPE_OCKB,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(OCKBState),
+.instance_init = ockb_init,
+.class_init= ockb_class_init,
+};
+
+static void ockb_register_types(void)
+{
+type_register_static(ockb_info);
+}
+
+type_init(ockb_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 7752d22..05b59e8 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -45,14 +45,16 @@ enum {
OR_UART0,
OR_IDE,
OR_OPENETH,
-OR_FRAMEBUFFER
+OR_FRAMEBUFFER,
+OR_KEYBOARD,
};
static hwaddr mem_map[] = {
[OR_UART0] = 0x9000,
[OR_IDE] = 0x9e00,
[OR_OPENETH] = 0x9200,
-[OR_FRAMEBUFFER] = 0x9100
+[OR_FRAMEBUFFER] = 0x9100,
+[OR_KEYBOARD] = 0x9400,
};
@@ -188,7 +190,8 @@ static void openrisc_sim_init(MachineState *machine)
/* OpenCores FrameBuffer device */
sysbus_create_simple(ocfb, mem_map[OR_FRAMEBUFFER], cpu-env.irq[8]);
-
+/* OpenCores keyboard */
+sysbus_create_simple(ockb, mem_map[OR_KEYBOARD], cpu-env.irq[5]);
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
Re: [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device
(lpc32xx_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 05b59e8..2199a63 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -47,6 +47,7 @@ enum {
OR_OPENETH,
OR_FRAMEBUFFER,
OR_KEYBOARD,
+OR_TOUCHSCREEN,
};
static hwaddr mem_map[] = {
@@ -55,6 +56,7 @@ static hwaddr mem_map[] = {
[OR_OPENETH] = 0x9200,
[OR_FRAMEBUFFER] = 0x9100,
[OR_KEYBOARD] = 0x9400,
+[OR_TOUCHSCREEN] = 0x9300,
};
@@ -193,6 +195,9 @@ static void openrisc_sim_init(MachineState *machine)
/* OpenCores keyboard */
sysbus_create_simple(ockb, mem_map[OR_KEYBOARD], cpu-env.irq[5]);
+/* LPC32XX Touch Screen */
+sysbus_create_simple(lpc32xx, mem_map[OR_TOUCHSCREEN],
cpu-env.irq[9]);
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
Acked-by: Jia Liu pro...@gmail.com
Regards,
Jia
Re: [Qemu-devel] [PATCH 16/23] target-openrisc: Use cpu_exec_interrupt qom hook
Hi Richard,
Thank you!
Tested-by: Jia Liu pro...@gmail.com
On Sat, Sep 13, 2014 at 9:45 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
cpu-exec.c | 18 --
target-openrisc/cpu.c | 1 +
target-openrisc/cpu.h | 1 +
target-openrisc/interrupt.c | 20
4 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 075abf9..81441e7 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -528,24 +528,6 @@ int cpu_exec(CPUArchState *env)
cc-do_interrupt(cpu);
next_tb = 0;
}
-
-#elif defined(TARGET_OPENRISC)
-{
-int idx = -1;
-if ((interrupt_request CPU_INTERRUPT_HARD)
- (env-sr SR_IEE)) {
-idx = EXCP_INT;
-}
-if ((interrupt_request CPU_INTERRUPT_TIMER)
- (env-sr SR_TEE)) {
-idx = EXCP_TICK;
-}
-if (idx = 0) {
-cpu-exception_index = idx;
-cc-do_interrupt(cpu);
-next_tb = 0;
-}
-}
#endif
/* The target hook has 3 exit conditions:
False when the interrupt isn't processed,
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 08e724c..39bedc1 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -165,6 +165,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void
*data)
cc-class_by_name = openrisc_cpu_class_by_name;
cc-has_work = openrisc_cpu_has_work;
cc-do_interrupt = openrisc_cpu_do_interrupt;
+cc-cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc-dump_state = openrisc_cpu_dump_state;
cc-set_pc = openrisc_cpu_set_pc;
cc-gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 4512f45..69b96c6 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -348,6 +348,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s);
void openrisc_cpu_do_interrupt(CPUState *cpu);
+bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 3de567e..e480cfd 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -63,3 +63,23 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
cs-exception_index = -1;
}
+
+bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+CPUOpenRISCState *env = cpu-env;
+int idx = -1;
+
+if ((interrupt_request CPU_INTERRUPT_HARD) (env-sr SR_IEE)) {
+idx = EXCP_INT;
+}
+if ((interrupt_request CPU_INTERRUPT_TIMER) (env-sr SR_TEE)) {
+idx = EXCP_TICK;
+}
+if (idx = 0) {
+cs-exception_index = idx;
+openrisc_cpu_do_interrupt(cs);
+return true;
+}
+return false;
+}
--
1.9.3
Regards,
Jia
Re: [Qemu-devel] [PATCH v2 3/4] target-openrisc: Add OpenCores keyboard device support
Hi Valentin,
On Sat, Aug 23, 2014 at 1:05 AM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores keyboard device to the default OpenRisc
machine.
The OpenCores keyboard device is a simple open source keyboard device
created by the OpenCores project(http://opencores.org/). By default it
just forwards Linux like keycodes.
Signed-off-by: Valentin Manea valentin.ma...@gmail.com
---
hw/openrisc/Makefile.objs | 4 +-
hw/openrisc/ockbd.c| 165
+
hw/openrisc/openrisc_sim.c | 3 +
3 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 hw/openrisc/ockbd.c
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index 1922a22..b907a40 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1,3 +1,3 @@
obj-y = pic_cpu.o cputimer.o
-obj-y += openrisc_sim.o
-obj-y += ocfb.o
+obj-y += openrisc_sim.o
+obj-y += ockbd.o ocfb.o
I think here should be look like this, or it will make a *.rej and
make patch failed.
obj-y = pic_cpu.o cputimer.o
obj-y += openrisc_sim.o
-obj-y += ocfb.o
+obj-y += ockbd.o ocfb.o
diff --git a/hw/openrisc/ockbd.c b/hw/openrisc/ockbd.c
new file mode 100644
index 000..64a6505
--- /dev/null
+++ b/hw/openrisc/ockbd.c
@@ -0,0 +1,165 @@
+/*
+ * OpenCores Keyboard device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the
rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include ui/console.h
+
+#define TYPE_OCKB ockb
+#define OCKB(obj) OBJECT_CHECK(OCKBState, (obj), TYPE_OCKB)
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...)\
+do { printf(ockb: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct OCKBState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+qemu_irq irq;
+uint8_t data[16];
+uint32_t rptr, wptr, count;
+} OCKBState;
+
+
+static void ockb_keycode(void *opaque, int keycode)
+{
+OCKBState *s = (OCKBState *) opaque;
+/* The keycodes the driver expects are exactly the
+ same as we receive them */
+if (s-count sizeof(s-data)) {
+s-data[s-wptr] = keycode;
+if (++s-wptr == sizeof(s-data)) {
+s-wptr = 0;
+}
+s-count++;
+}
+qemu_irq_raise(s-irq);
+}
+
+static uint64_t ockb_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+OCKBState *s = (OCKBState *) opaque;
+int keycode;
+
+
+if (offset = 0x4) {
+return 0;
+}
+
+DPRINTF(read offset %u\n, (uint32_t)offset);
+if (s-count == 0) {
+qemu_irq_lower(s-irq);
+return 0;
+}
+
+keycode = s-data[s-rptr];
+if (++s-rptr == sizeof(s-data)) {
+s-rptr = 0;
+}
+s-count--;
+
+return keycode;
+}
+
+static void ockb_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+/* Don't actually expect any write but don't fail */
+DPRINTF(read offset %u\n, (uint32_t)offset);
+}
+
+static const MemoryRegionOps ockb_ops = {
+.read = ockb_read,
+.write = ockb_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int ockb_initfn(SysBusDevice *sbd)
+{
+DeviceState *dev = DEVICE(sbd);
+OCKBState *s = OCKB(dev);
+
+memory_region_init_io(s-iomem, OBJECT(s), ockb_ops, s, ockb, 0x100);
+sysbus_init_mmio(sbd, s-iomem);
+sysbus_init_irq(sbd, s-irq);
+
+qemu_add_kbd_event_handler(ockb_keycode, s);
+
+return 0;
+}
+
+
+static const VMStateDescription vmstate_ockb_regs = {
+.name = ockb,
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+
Re: [Qemu-devel] [PATCH v2 4/4] target-openrisc: Add LPC32XX touchscreen device
Hi Valentin,
On Sat, Aug 23, 2014 at 1:06 AM, Valentin Manea
valentin.ma...@gmail.com wrote:
The LPC32XX is a simple MMIO touch screen device with a Linux device
driver. The device is suitable for small machines which require mouse
input but have no suitable bus(SPI, I2C).
Add the LPC32XX device to the default OpenRisc machine.
Signed-off-by: Valentin Manea valentin.ma...@gmail.com
---
default-configs/or32-softmmu.mak | 1 +
hw/input/Makefile.objs | 1 +
hw/input/lpc32xx.c | 274
+++
hw/openrisc/openrisc_sim.c | 3 +
4 files changed, 279 insertions(+)
create mode 100644 hw/input/lpc32xx.c
diff --git a/default-configs/or32-softmmu.mak
b/default-configs/or32-softmmu.mak
index 0e17a43..6e42d7e 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -6,3 +6,4 @@ CONFIG_IDE_CORE=y
CONFIG_IDE_QDEV=y
CONFIG_IDE_MMIO=y
CONFIG_FRAMEBUFFER=y
+CONFIG_LPC32XX=y
diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
index e8c80b9..7b9b055 100644
--- a/hw/input/Makefile.objs
+++ b/hw/input/Makefile.objs
@@ -11,3 +11,4 @@ common-obj-$(CONFIG_VMMOUSE) += vmmouse.o
obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o
obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o
obj-$(CONFIG_TSC210X) += tsc210x.o
+obj-$(CONFIG_LPC32XX) += lpc32xx.o
diff --git a/hw/input/lpc32xx.c b/hw/input/lpc32xx.c
new file mode 100644
index 000..fbf68bc
--- /dev/null
+++ b/hw/input/lpc32xx.c
@@ -0,0 +1,274 @@
+/*
+ * OpenCores framebuffer device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the
rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/devices.h
+#include ui/console.h
+#include ui/input.h
+#include qemu/timer.h
+
+/*
+ * Touchscreen controller register offsets
+ */
+#define LPC32XX_TSC_STAT0x00
+#define LPC32XX_TSC_SEL 0x04
+#define LPC32XX_TSC_CON 0x08
+#define LPC32XX_TSC_FIFO0x0C
+#define LPC32XX_TSC_DTR 0x10
+#define LPC32XX_TSC_RTR 0x14
+#define LPC32XX_TSC_UTR 0x18
+#define LPC32XX_TSC_TTR 0x1C
+#define LPC32XX_TSC_DXP 0x20
+#define LPC32XX_TSC_MIN_X 0x24
+#define LPC32XX_TSC_MAX_X 0x28
+#define LPC32XX_TSC_MIN_Y 0x2C
+#define LPC32XX_TSC_MAX_Y 0x30
+#define LPC32XX_TSC_AUX_UTR 0x34
+#define LPC32XX_TSC_AUX_MIN 0x38
+#define LPC32XX_TSC_AUX_MAX 0x3C
+
+#define LPC32XX_TSC_STAT_FIFO_OVRRN (1 8)
+#define LPC32XX_TSC_STAT_FIFO_EMPTY (1 7)
+#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 31)
+
+#define LPC32XX_TSC_ADCCON_POWER_UP (1 2)
+#define LPC32XX_TSC_ADCCON_AUTO_EN (1 0)
+
+#define LPC32XX_TSC_FIFO_TS_P_LEVEL(1 31)
+
+#define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x03FF
+#define LPC32XX_TSC_FIFO_X_VAL(x)(((LPC32XX_TSC_ADCDAT_VALUE_MASK - x)
\
+ LPC32XX_TSC_ADCDAT_VALUE_MASK) 16)
+#define LPC32XX_TSC_FIFO_Y_VAL(y)((LPC32XX_TSC_ADCDAT_VALUE_MASK - y) \
+ LPC32XX_TSC_ADCDAT_VALUE_MASK)
+
+
+#define LPC32XX_TSC_MIN_XY_VAL 0x0
+#define LPC32XX_TSC_MAX_XY_VAL 0x3FF
+
+
+#define TYPE_LPC32XX lpc32xx
+#define LPC32XX(obj) OBJECT_CHECK(LPC32XXState, (obj), TYPE_LPC32XX)
+
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...)\
+do { printf(lpc32xx: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+
+typedef struct LPC32XXState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+qemu_irq irq;
+uint32_t control;
+uint32_t status;
+bool pressed;
+uint32_t move_count;
+
Re: [Qemu-devel] [PATCH 2/4] target-openrisc: Add OpenCores FB device support
Hi Valentin,
On Fri, Aug 22, 2014 at 9:10 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores Framebuffer device and enable it by
default in the OpenRISC machine.
The OpenCores display device is a simple open source framebuffer device
created http://opencores.org/project,vgafb
Signed-off-by: Valentin Manea valentin.ma...@gmail.com
---
default-configs/or32-softmmu.mak | 1 +
hw/openrisc/Makefile.objs| 1 +
hw/openrisc/ocfb.c | 325
+++
hw/openrisc/openrisc_sim.c | 3 +
4 files changed, 330 insertions(+)
create mode 100644 hw/openrisc/ocfb.c
diff --git a/default-configs/or32-softmmu.mak
b/default-configs/or32-softmmu.mak
index c3ff078..0e17a43 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -5,3 +5,4 @@ CONFIG_OPENCORES_ETH=y
CONFIG_IDE_CORE=y
CONFIG_IDE_QDEV=y
CONFIG_IDE_MMIO=y
+CONFIG_FRAMEBUFFER=y
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index 61246b1..1922a22 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1,2 +1,3 @@
obj-y = pic_cpu.o cputimer.o
obj-y += openrisc_sim.o
+obj-y += ocfb.o
diff --git a/hw/openrisc/ocfb.c b/hw/openrisc/ocfb.c
new file mode 100644
index 000..226d1e3
--- /dev/null
+++ b/hw/openrisc/ocfb.c
@@ -0,0 +1,325 @@
+/*
+ * OpenCores framebuffer device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k
http://s-macke.github.io/jor1k/
Is here a line wrapped?
I think it should looks like:
+ * Based on work by Sebastian Macke for jor1k
+ * http://s-macke.github.io/jor1k/
rather than
+ http://s-macke.github.io/jor1k/
+ * Based on Arm PrimeCell PL110 Color LCD Controller by Paul Brook
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a copy
+ * of this software and associated documentation files (the
Software), to deal
+ * in the Software without restriction, including without limitation
the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include hw/sysbus.h
+#include hw/display/framebuffer.h
+#include ui/console.h
+
+/* VGA defines */
+#define VGA_CTRL 0x000
+#define VGA_STAT 0x004
+#define VGA_HTIM 0x008
+#define VGA_VTIM 0x00c
+#define VGA_HVLEN 0x010
+#define VGA_VBARA 0x014
+#define VGA_PALETTE0x800
+
+#define VGA_CTRL_VEN 0x0001 /* Video Enable */
+#define VGA_CTRL_HIE 0x0002 /* HSync Interrupt Enable */
+#define VGA_CTRL_PC0x0800 /* 8-bit Pseudo Color Enable*/
+#define VGA_CTRL_CD8 0x /* Color Depth 8 */
+#define VGA_CTRL_CD16 0x0200 /* Color Depth 16 */
+#define VGA_CTRL_CD24 0x0400 /* Color Depth 24 */
+#define VGA_CTRL_CD32 0x0600 /* Color Depth 32 */
+#define VGA_CTRL_CD0x0E00 /* Color Depth Mask */
+#define VGA_CTRL_VBL1 0x /* Burst Length 1 */
+#define VGA_CTRL_VBL2 0x0080 /* Burst Length 2 */
+#define VGA_CTRL_VBL4 0x0100 /* Burst Length 4 */
+#define VGA_CTRL_VBL8 0x0180 /* Burst Length 8 */
+
+#define PALETTE_SIZE 256
+
+#define TYPE_OCFB ocfb
+#define OCFB(obj) OBJECT_CHECK(OCFBState, (obj), TYPE_OCFB)
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...)\
+do { printf(ocfb: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct OCFBState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+QemuConsole *con;
+/* RAM fragment containing framebuffer */
+MemoryRegionSection mem_section;
+uint32_t cr;
+uint8_t *fb;
+uint32_t fb_size;
+uint32_t fb_phys;
+uint32_t cols;
+uint32_t rows;
+uint32_t bpp;
+uint32_t invalidate;
+qemu_irq irq;
+} OCFBState;
+
+static int vmstate_ocfb_post_load(void *opaque, int version_id);
+
+static const VMStateDescription vmstate_ocfb = {
+.name = ocfb,
+.version_id = 2,
+.minimum_version_id = 1,
+.post_load = vmstate_ocfb_post_load,
+.fields = (VMStateField[]) {
+VMSTATE_UINT32(cr,
Re: [Qemu-devel] [PATCH 3/4] target-openrisc: Add OpenCores keyboard device support
Hi Valentin,
On Fri, Aug 22, 2014 at 9:11 PM, Valentin Manea
valentin.ma...@gmail.com wrote:
Add support for the OpenCores keyboard device to the default OpenRisc
machine.
The OpenCores keyboard device is a simple open source keyboard device
created by the OpenCores project(http://opencores.org/). By default it
just forwards Linux like keycodes.
Signed-off-by: Valentin Manea valentin.ma...@gmail.com
---
hw/openrisc/Makefile.objs | 4 +-
hw/openrisc/ockbd.c| 165
+
hw/openrisc/openrisc_sim.c | 3 +
3 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 hw/openrisc/ockbd.c
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index 1922a22..b907a40 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1,3 +1,3 @@
obj-y = pic_cpu.o cputimer.o
-obj-y += openrisc_sim.o
-obj-y += ocfb.o
+obj-y += openrisc_sim.o
+obj-y += ockbd.o ocfb.o
diff --git a/hw/openrisc/ockbd.c b/hw/openrisc/ockbd.c
new file mode 100644
index 000..64a6505
--- /dev/null
+++ b/hw/openrisc/ockbd.c
@@ -0,0 +1,165 @@
+/*
+ * OpenCores Keyboard device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k
http://s-macke.github.io/jor1k/
Same as 2/4, I think it should looks like:
+ * Based on work by Sebastian Macke for jor1k
+ * http://s-macke.github.io/jor1k/
rather than
+ * Based on work by Sebastian Macke for jor1k
+ http://s-macke.github.io/jor1k/
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a copy
+ * of this software and associated documentation files (the
Software), to deal
+ * in the Software without restriction, including without limitation
the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include ui/console.h
+
+#define TYPE_OCKB ockb
+#define OCKB(obj) OBJECT_CHECK(OCKBState, (obj), TYPE_OCKB)
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...)\
+do { printf(ockb: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct OCKBState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+qemu_irq irq;
+uint8_t data[16];
+uint32_t rptr, wptr, count;
+} OCKBState;
+
+
+static void ockb_keycode(void *opaque, int keycode)
+{
+OCKBState *s = (OCKBState *) opaque;
+/* The keycodes the driver expects are exactly the
+ same as we receive them */
+if (s-count sizeof(s-data)) {
+s-data[s-wptr] = keycode;
+if (++s-wptr == sizeof(s-data)) {
+s-wptr = 0;
+}
+s-count++;
+}
+qemu_irq_raise(s-irq);
+}
+
+static uint64_t ockb_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+OCKBState *s = (OCKBState *) opaque;
+int keycode;
+
+
+if (offset = 0x4) {
+return 0;
+}
+
+DPRINTF(read offset %u\n, (uint32_t)offset);
+if (s-count == 0) {
+qemu_irq_lower(s-irq);
+return 0;
+}
+
+keycode = s-data[s-rptr];
+if (++s-rptr == sizeof(s-data)) {
+s-rptr = 0;
+}
+s-count--;
+
+return keycode;
+}
+
+static void ockb_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+/* Don't actually expect any write but don't fail */
+DPRINTF(read offset %u\n, (uint32_t)offset);
+}
+
+static const MemoryRegionOps ockb_ops = {
+.read = ockb_read,
+.write = ockb_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int ockb_initfn(SysBusDevice *sbd)
+{
+DeviceState *dev = DEVICE(sbd);
+OCKBState *s = OCKB(dev);
+
+memory_region_init_io(s-iomem, OBJECT(s), ockb_ops, s, ockb,
0x100);
+sysbus_init_mmio(sbd, s-iomem);
+sysbus_init_irq(sbd, s-irq);
+
+qemu_add_kbd_event_handler(ockb_keycode, s);
+
+return 0;
+}
+
+
+static const VMStateDescription vmstate_ockb_regs = {
+.name = ockb,
+.version_id = 1,
+.minimum_version_id = 1,
+
Re: [Qemu-devel] [PATCH 4/4] target-openrisc: Add LPC32XX touchscreen device
Hi Valentin, On Fri, Aug 22, 2014 at 9:12 PM, Valentin Manea valentin.ma...@gmail.com wrote: The LPC32XX is a simple MMIO touch screen device with a Linux device driver. The device is suitable for small machines which require mouse input but have no suitable bus(SPI, I2C). Add the LPC32XX device to the default OpenRisc machine. Signed-off-by: Valentin Manea valentin.ma...@gmail.com --- default-configs/or32-softmmu.mak | 1 + hw/input/Makefile.objs | 1 + hw/input/lpc32xx.c | 274 +++ hw/openrisc/openrisc_sim.c | 3 + 4 files changed, 279 insertions(+) create mode 100644 hw/input/lpc32xx.c diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak index 0e17a43..6e42d7e 100644 --- a/default-configs/or32-softmmu.mak +++ b/default-configs/or32-softmmu.mak @@ -6,3 +6,4 @@ CONFIG_IDE_CORE=y CONFIG_IDE_QDEV=y CONFIG_IDE_MMIO=y CONFIG_FRAMEBUFFER=y +CONFIG_LPC32XX=y diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs index e8c80b9..7b9b055 100644 --- a/hw/input/Makefile.objs +++ b/hw/input/Makefile.objs @@ -11,3 +11,4 @@ common-obj-$(CONFIG_VMMOUSE) += vmmouse.o obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o obj-$(CONFIG_TSC210X) += tsc210x.o +obj-$(CONFIG_LPC32XX) += lpc32xx.o diff --git a/hw/input/lpc32xx.c b/hw/input/lpc32xx.c new file mode 100644 index 000..fbf68bc --- /dev/null +++ b/hw/input/lpc32xx.c @@ -0,0 +1,274 @@ +/* + * OpenCores framebuffer device + * + * Copyright (c) 2014 Valentin Manea + * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/ Same as 2/4 and 3/4, I think it should looks like: + * Based on work by Sebastian Macke for jor1k + * http://s-macke.github.io/jor1k/ rather than + * Based on work by Sebastian Macke for jor1k + http://s-macke.github.io/jor1k/ + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the Software), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include hw/hw.h +#include hw/sysbus.h +#include hw/devices.h +#include ui/console.h +#include ui/input.h +#include qemu/timer.h + +/* + * Touchscreen controller register offsets + */ +#define LPC32XX_TSC_STAT0x00 +#define LPC32XX_TSC_SEL 0x04 +#define LPC32XX_TSC_CON 0x08 +#define LPC32XX_TSC_FIFO0x0C +#define LPC32XX_TSC_DTR 0x10 +#define LPC32XX_TSC_RTR 0x14 +#define LPC32XX_TSC_UTR 0x18 +#define LPC32XX_TSC_TTR 0x1C +#define LPC32XX_TSC_DXP 0x20 +#define LPC32XX_TSC_MIN_X 0x24 +#define LPC32XX_TSC_MAX_X 0x28 +#define LPC32XX_TSC_MIN_Y 0x2C +#define LPC32XX_TSC_MAX_Y 0x30 +#define LPC32XX_TSC_AUX_UTR 0x34 +#define LPC32XX_TSC_AUX_MIN 0x38 +#define LPC32XX_TSC_AUX_MAX 0x3C + +#define LPC32XX_TSC_STAT_FIFO_OVRRN (1 8) +#define LPC32XX_TSC_STAT_FIFO_EMPTY (1 7) +#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 31) + +#define LPC32XX_TSC_ADCCON_POWER_UP (1 2) +#define LPC32XX_TSC_ADCCON_AUTO_EN (1 0) + +#define LPC32XX_TSC_FIFO_TS_P_LEVEL(1 31) + +#define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x03FF +#define LPC32XX_TSC_FIFO_X_VAL(x)(((LPC32XX_TSC_ADCDAT_VALUE_MASK - x) \ Macros with complex values should be enclosed in parenthesis, and 80 columns. + LPC32XX_TSC_ADCDAT_VALUE_MASK) 16) +#define LPC32XX_TSC_FIFO_Y_VAL(y)((LPC32XX_TSC_ADCDAT_VALUE_MASK - y) \ Macros with complex values should be enclosed in parenthesis, and 80 columns. + LPC32XX_TSC_ADCDAT_VALUE_MASK) + + +#define LPC32XX_TSC_MIN_XY_VAL 0x0 +#define LPC32XX_TSC_MAX_XY_VAL 0x3FF + + +#define TYPE_LPC32XX lpc32xx +#define LPC32XX(obj) OBJECT_CHECK(LPC32XXState, (obj), TYPE_LPC32XX) + + +#ifdef
Re: [Qemu-devel] [PATCH 0/4] target-openrisc: Some openrisc improvements
Hi Valentin, On Fri, Aug 22, 2014 at 10:01 PM, Valentin Manea valentin.ma...@gmail.com wrote: Hi, I would like to share this series of patches to improve the openrisc machine. Mostly my goal is to have the same features as the web based machine and be able to boot qemu with exactly the same images. Some feedback would be appreciated. Thank you very much! May you please upload the test linux image to somewhere, and tell us your test steps? Make me can test your change. Regards, Valentin Regards, Jia
Re: [Qemu-devel] [PATCH] linux-user: Handle arches with llseek instead of _llseek
Hi James, On Wed, Mar 26, 2014 at 5:51 AM, James Hogan james.ho...@imgtec.com wrote: Recently merged kernel ports (such as OpenRISC and Meta) have an llseek system call instead of _llseek. This is handled for the host architecture by defining __NR__llseek as __NR_llseek, but not for the target architecture. Thank you, James. I don't have a Linux test environment for I'm a OS X user, may you please make a test, please? Handle it in the same way for these architectures, defining TARGET_NR__llseek as TARGET_NR_llseek. Signed-off-by: James Hogan james.ho...@imgtec.com Cc: Riku Voipio riku.voi...@iki.fi Cc: Jia Liu pro...@gmail.com --- linux-user/syscall.c | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 2eac6d5..8dbe39b 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -198,6 +198,11 @@ static type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5, \ #define __NR__llseek __NR_lseek #endif +/* Newer kernel ports have llseek() instead of _llseek() */ +#if defined(TARGET_NR_llseek) !defined(TARGET_NR__llseek) +#define TARGET_NR__llseek TARGET_NR_llseek +#endif + #ifdef __NR_gettid _syscall0(int, gettid) #else -- 1.8.3.2 Regards, Jia
[Qemu-devel] [PULL] OpenRISC patch queue for 1.8
Hi Anthony, This is my OpenRISC patch queue for 1.8, it have been well tested, please pull. Thanks to Richard Henderson, he made the LD/ST updated. Regards, Jia The following changes since commit a4550442b947d2c2b346bd2efc8fe3da16425f4d: petalogix-ml605: Create the CPU with object_new() (2014-02-11 22:57:57 +1000) are available in the git repository at: git://github.com/J-Liu/qemu.git or32-ld-st for you to fetch changes up to 5631e69c269c6b832837715a3bd4d685120a2713: target-openrisc: Use new qemu_ld/st opcodes (2014-02-12 08:47:57 +0800) Richard Henderson (1): target-openrisc: Use new qemu_ld/st opcodes target-openrisc/translate.c | 99 +++-- 1 file changed, 32 insertions(+), 67 deletions(-)
[Qemu-devel] [PULL] target-openrisc: Use new qemu_ld/st opcodes
From: Richard Henderson r...@twiddle.net
Signed-off-by: Richard Henderson r...@twiddle.net
Acked-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 99 +++--
1 file changed, 32 insertions(+), 67 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b381477..776cb6e 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -707,6 +707,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
+TCGMemOp mop;
+
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
@@ -838,72 +840,46 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS(l.ld r%d, r%d, %d\n, rd, ra, I16);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld64(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_load;
#endif*/
case 0x21:/* l.lwz */
LOG_DIS(l.lwz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_load;
case 0x22:/* l.lws */
LOG_DIS(l.lws r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TESL;
+goto do_load;
case 0x23:/* l.lbz */
LOG_DIS(l.lbz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_load;
case 0x24:/* l.lbs */
LOG_DIS(l.lbs r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_SB;
+goto do_load;
case 0x25:/* l.lhz */
LOG_DIS(l.lhz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUW;
+goto do_load;
case 0x26:/* l.lhs */
LOG_DIS(l.lhs r%d, r%d, %d\n, rd, ra, I16);
+mop = MO_TESW;
+goto do_load;
+
+do_load:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc-mem_idx);
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, mop);
tcg_temp_free(t0);
}
break;
@@ -1042,42 +1018,31 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS(l.sd %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st64(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_store;
#endif*/
case 0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st32(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_store;
case 0x36:/* l.sb */
LOG_DIS(l.sb %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st8(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_store;
case 0x37:/* l.sh */
LOG_DIS(l.sh %d, r%d, r%d, %d\n, I5, ra, rb, I11);
+mop = MO_TEUW;
+goto
Re: [Qemu-devel] [PATCH] target-openrisc: Use new qemu_ld/st opcodes
Hi Anthony,
Michael said he had applied the typo patch, then I waited it for days
and didn't find it in master,
so I resend the same patch in my pull request queue.
It is my fault, sorry Michael.
And, Anthony, please applied this one, please.
On Sat, Dec 14, 2013 at 4:45 PM, Jia Liu pro...@gmail.com wrote:
Hi Richard,
On Thu, Dec 12, 2013 at 12:42 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-openrisc/translate.c | 99
+++--
1 file changed, 32 insertions(+), 67 deletions(-)
Untested, since there's no openrisc images at http://wiki.qemu.org/Testing,
but it's certainly a simple enough change.
r~
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..72d0b9c 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -707,6 +707,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
+TCGMemOp mop;
+
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
@@ -838,72 +840,46 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS(l.ld r%d, r%d, %d\n, rd, ra, I16);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld64(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_load;
#endif*/
case 0x21:/* l.lwz */
LOG_DIS(l.lwz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_load;
case 0x22:/* l.lws */
LOG_DIS(l.lws r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TESL;
+goto do_load;
case 0x23:/* l.lbz */
LOG_DIS(l.lbz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_load;
case 0x24:/* l.lbs */
LOG_DIS(l.lbs r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_SB;
+goto do_load;
case 0x25:/* l.lhz */
LOG_DIS(l.lhz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUW;
+goto do_load;
case 0x26:/* l.lhs */
LOG_DIS(l.lhs r%d, r%d, %d\n, rd, ra, I16);
+mop = MO_TESW;
+goto do_load;
+
+do_load:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc-mem_idx);
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, mop);
tcg_temp_free(t0);
}
break;
@@ -1042,42 +1018,31 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS(l.sd %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st64(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_store;
#endif*/
case 0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st32(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0
Re: [Qemu-devel] [PULL 0/2] OpenRISC patch queue for 1.8
ping~~ On Sat, Dec 21, 2013 at 9:47 AM, Jia Liu pro...@gmail.com wrote: Hi Anthony, This is my OpenRISC patch queue for 1.8, it have been well tested, please pull. Thanks to Richard Henderson, he made the LD/ST updated. Thanks to Stefan Weil, he fixed a typo. Regards, Jia The following changes since commit f8251db121c3f051b22a7536b97d160c30bcccd4: Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into staging (2013-12-19 17:03:17 -0800) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 31ab4c235b7f7342f727fd835e732623753e1ffb: target-openrisc: Use new qemu_ld/st opcodes (2013-12-21 09:38:18 +0800) Richard Henderson (1): target-openrisc: Use new qemu_ld/st opcodes Stefan Weil (1): openrisc: Fix spelling in comment (transaltion - translation) target-openrisc/translate.c | 101 +++- 1 file changed, 33 insertions(+), 68 deletions(-)
[Qemu-devel] [PULL 1/2] openrisc: Fix spelling in comment (transaltion - translation)
From: Stefan Weil s...@weilnetz.de
Fix typo in comment (transaltion - translation).
And I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil s...@weilnetz.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..b381477 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -112,7 +112,7 @@ void openrisc_translate_init(void)
}
}
-/* Writeback SR_F transaltion-space to execution-space. */
+/* Writeback SR_F translation space to execution space. */
static inline void wb_SR_F(void)
{
int label;
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 0/2] OpenRISC patch queue for 1.8
Hi Anthony, This is my OpenRISC patch queue for 1.8, it have been well tested, please pull. Thanks to Richard Henderson, he made the LD/ST updated. Thanks to Stefan Weil, he fixed a typo. Regards, Jia The following changes since commit f8251db121c3f051b22a7536b97d160c30bcccd4: Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into staging (2013-12-19 17:03:17 -0800) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 31ab4c235b7f7342f727fd835e732623753e1ffb: target-openrisc: Use new qemu_ld/st opcodes (2013-12-21 09:38:18 +0800) Richard Henderson (1): target-openrisc: Use new qemu_ld/st opcodes Stefan Weil (1): openrisc: Fix spelling in comment (transaltion - translation) target-openrisc/translate.c | 101 +++- 1 file changed, 33 insertions(+), 68 deletions(-)
[Qemu-devel] [PULL 2/2] target-openrisc: Use new qemu_ld/st opcodes
From: Richard Henderson r...@twiddle.net
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
Acked-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 99 +++--
1 file changed, 32 insertions(+), 67 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b381477..776cb6e 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -707,6 +707,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
+TCGMemOp mop;
+
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
@@ -838,72 +840,46 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS(l.ld r%d, r%d, %d\n, rd, ra, I16);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld64(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_load;
#endif*/
case 0x21:/* l.lwz */
LOG_DIS(l.lwz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_load;
case 0x22:/* l.lws */
LOG_DIS(l.lws r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TESL;
+goto do_load;
case 0x23:/* l.lbz */
LOG_DIS(l.lbz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_load;
case 0x24:/* l.lbs */
LOG_DIS(l.lbs r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_SB;
+goto do_load;
case 0x25:/* l.lhz */
LOG_DIS(l.lhz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUW;
+goto do_load;
case 0x26:/* l.lhs */
LOG_DIS(l.lhs r%d, r%d, %d\n, rd, ra, I16);
+mop = MO_TESW;
+goto do_load;
+
+do_load:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc-mem_idx);
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, mop);
tcg_temp_free(t0);
}
break;
@@ -1042,42 +1018,31 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS(l.sd %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st64(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_store;
#endif*/
case 0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st32(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_store;
case 0x36:/* l.sb */
LOG_DIS(l.sb %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st8(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_store;
case 0x37:/* l.sh */
LOG_DIS(l.sh %d, r%d, r%d, %d\n, I5, ra, rb, I11
Re: [Qemu-devel] [PATCH] target-openrisc: Use new qemu_ld/st opcodes
Hi Richard,
On Thu, Dec 12, 2013 at 12:42 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-openrisc/translate.c | 99
+++--
1 file changed, 32 insertions(+), 67 deletions(-)
Untested, since there's no openrisc images at http://wiki.qemu.org/Testing,
but it's certainly a simple enough change.
r~
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..72d0b9c 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -707,6 +707,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
+TCGMemOp mop;
+
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
@@ -838,72 +840,46 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS(l.ld r%d, r%d, %d\n, rd, ra, I16);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld64(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_load;
#endif*/
case 0x21:/* l.lwz */
LOG_DIS(l.lwz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_load;
case 0x22:/* l.lws */
LOG_DIS(l.lws r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TESL;
+goto do_load;
case 0x23:/* l.lbz */
LOG_DIS(l.lbz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_UB;
+goto do_load;
case 0x24:/* l.lbs */
LOG_DIS(l.lbs r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_SB;
+goto do_load;
case 0x25:/* l.lhz */
LOG_DIS(l.lhz r%d, r%d, %d\n, rd, ra, I16);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUW;
+goto do_load;
case 0x26:/* l.lhs */
LOG_DIS(l.lhs r%d, r%d, %d\n, rd, ra, I16);
+mop = MO_TESW;
+goto do_load;
+
+do_load:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
-tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc-mem_idx);
+tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc-mem_idx, mop);
tcg_temp_free(t0);
}
break;
@@ -1042,42 +1018,31 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS(l.sd %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-check_ob64s(dc);
-TCGv_i64 t0 = tcg_temp_new_i64();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st64(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free_i64(t0);
-}
-break;
+check_ob64s(dc);
+mop = MO_TEQ;
+goto do_store;
#endif*/
case 0x35:/* l.sw */
LOG_DIS(l.sw %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st32(cpu_R[rb], t0, dc-mem_idx);
-tcg_temp_free(t0);
-}
-break;
+mop = MO_TEUL;
+goto do_store;
case 0x36:/* l.sb */
LOG_DIS(l.sb %d, r%d, r%d, %d\n, I5, ra, rb, I11);
-{
-TCGv t0 = tcg_temp_new();
-tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
-tcg_gen_qemu_st8
Re: [Qemu-devel] [PATCH] openrisc: Fix spelling in comment (transaltion - translation)
Hi Stefan,
On Sat, Dec 7, 2013 at 4:24 PM, Stefan Weil s...@weilnetz.de wrote:
I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
target-openrisc/translate.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..b381477 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -112,7 +112,7 @@ void openrisc_translate_init(void)
}
}
-/* Writeback SR_F transaltion-space to execution-space. */
+/* Writeback SR_F translation space to execution space. */
Thank you very much!
Reviewed-by: Jia Liu pro...@gmail.com
static inline void wb_SR_F(void)
{
int label;
--
1.7.10.4
Regards,
Jia
[Qemu-devel] [PULL 5/7] openrisc-timer: Reduce overhead, Separate clock update functions
From: Sebastian Macke sebast...@macke.de
The clock value is only evaluated when really necessary reducing
the overhead of the timer handling.
This also solves a problem in the way the Linux kernel
handles the timer and the expected accuracy.
The old version could lead to inaccurate timings.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/cputimer.c | 29 +++--
target-openrisc/cpu.h| 1 +
target-openrisc/sys_helper.c | 38 ++
3 files changed, 38 insertions(+), 30 deletions(-)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 988ca20..9c54945 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -30,19 +30,28 @@ static int is_counting;
void cpu_openrisc_count_update(OpenRISCCPU *cpu)
{
-uint64_t now, next;
-uint32_t wait;
+uint64_t now;
-now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (!is_counting) {
-timer_del(cpu-env.timer);
-last_clk = now;
return;
}
-
+now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
cpu-env.ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ,
get_ticks_per_sec());
last_clk = now;
+}
+
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
+{
+uint32_t wait;
+uint64_t now, next;
+
+if (!is_counting) {
+return;
+}
+
+cpu_openrisc_count_update(cpu);
+now = last_clk;
if ((cpu-env.ttmr TTMR_TP) = (cpu-env.ttcr TTMR_TP)) {
wait = TTMR_TP - (cpu-env.ttcr TTMR_TP) + 1;
@@ -50,7 +59,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
} else {
wait = (cpu-env.ttmr TTMR_TP) - (cpu-env.ttcr TTMR_TP);
}
-
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
timer_mod(cpu-env.timer, next);
}
@@ -63,8 +71,9 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu)
void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
{
-is_counting = 0;
+timer_del(cpu-env.timer);
cpu_openrisc_count_update(cpu);
+is_counting = 0;
}
static void openrisc_timer_cb(void *opaque)
@@ -84,15 +93,15 @@ static void openrisc_timer_cb(void *opaque)
break;
case TIMER_INTR:
cpu-env.ttcr = 0;
-cpu_openrisc_count_start(cpu);
break;
case TIMER_SHOT:
cpu_openrisc_count_stop(cpu);
break;
case TIMER_CONT:
-cpu_openrisc_count_start(cpu);
break;
}
+
+cpu_openrisc_timer_update(cpu);
}
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 8fd0bc0..0f9efdf 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -373,6 +373,7 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index cccbc0e..f116588 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -127,33 +127,31 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
break;
case TO_SPR(10, 0): /* TTMR */
{
+if ((env-ttmr TTMR_M) ^ (rb TTMR_M)) {
+switch (rb TTMR_M) {
+case TIMER_NONE:
+cpu_openrisc_count_stop(cpu);
+break;
+case TIMER_INTR:
+case TIMER_SHOT:
+case TIMER_CONT:
+cpu_openrisc_count_start(cpu);
+break;
+default:
+break;
+}
+}
+
int ip = env-ttmr TTMR_IP;
if (rb TTMR_IP) {/* Keep IP bit. */
-env-ttmr = (rb ~TTMR_IP) + ip;
+env-ttmr = (rb ~TTMR_IP) | ip;
} else {/* Clear IP bit. */
env-ttmr = rb ~TTMR_IP;
cs-interrupt_request = ~CPU_INTERRUPT_TIMER;
}
-cpu_openrisc_count_update(cpu);
-
-switch (env-ttmr TTMR_M) {
-case TIMER_NONE:
-cpu_openrisc_count_stop(cpu);
-break;
-case TIMER_INTR:
-cpu_openrisc_count_start(cpu);
-break;
-case TIMER_SHOT:
-cpu_openrisc_count_start(cpu);
-break;
-case TIMER_CONT:
-cpu_openrisc_count_start(cpu);
-break;
-default:
-break;
-}
+cpu_openrisc_timer_update(cpu);
}
break;
@@ -162,7 +160,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
if (env-ttmr
[Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler
From: Sebastian Macke sebast...@macke.de
This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.
Tested by checking crashing programs which otherwise work in or1ksim.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/interrupt.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 16ef4b3..2153e7e 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = cpu-env;
#ifndef CONFIG_USER_ONLY
-if (env-flags D_FLAG) { /* Delay Slot insn */
+
+env-epcr = env-pc;
+if (env-flags D_FLAG) {
env-flags = ~D_FLAG;
env-sr |= SR_DSX;
-if (env-exception_index == EXCP_TICK||
-env-exception_index == EXCP_INT ||
-env-exception_index == EXCP_SYSCALL ||
-env-exception_index == EXCP_FPE) {
-env-epcr = env-jmp_pc;
-} else {
-env-epcr = env-pc - 4;
-}
-} else {
-if (env-exception_index == EXCP_TICK||
-env-exception_index == EXCP_INT ||
-env-exception_index == EXCP_SYSCALL ||
-env-exception_index == EXCP_FPE) {
-env-epcr = env-npc;
-} else {
-env-epcr = env-pc;
-}
+env-epcr -= 4;
+}
+if (env-exception_index == EXCP_SYSCALL) {
+env-epcr += 4;
}
/* For machine-state changed between user-mode and supervisor mode,
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 7/7] target-openrisc: Correct carry flag check of l.addc and l.addic test cases
From: Sebastian Macke sebast...@macke.de
The test cases did not correctly test for the carry flag.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
tests/tcg/openrisc/test_addc.c | 8 +---
tests/tcg/openrisc/test_addic.c | 10 ++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/openrisc/test_addc.c b/tests/tcg/openrisc/test_addc.c
index 05d18f8..a8f756a 100644
--- a/tests/tcg/openrisc/test_addc.c
+++ b/tests/tcg/openrisc/test_addc.c
@@ -7,9 +7,10 @@ int main(void)
b = 0x01;
c = 0x;
-result = 1;
+result = 0;
__asm
-(l.addc %0, %1, %2\n\t
+(l.add r1, r1, r0\n\t /* clear carry */
+ l.addc %0, %1, %2\n\t
: =r(a)
: r(b), r(c)
);
@@ -22,7 +23,8 @@ int main(void)
c = 0x;
result = 0x8001;
__asm
-(l.addc %0, %1, %2\n\t
+(l.add r1, r1, r0\n\t /* clear carry */
+ l.addc %0, %1, %2\n\t
l.movhi %2, 0x7fff\n\t
l.ori%2, %2, 0x\n\t
l.addc %0, %1, %2\n\t
diff --git a/tests/tcg/openrisc/test_addic.c b/tests/tcg/openrisc/test_addic.c
index 4ba7432..857aaa1 100644
--- a/tests/tcg/openrisc/test_addic.c
+++ b/tests/tcg/openrisc/test_addic.c
@@ -6,9 +6,10 @@ int main(void)
int result;
a = 1;
-result = 0x1;
+result = 0x0;
__asm
-(l.addic %0, %0, 0x\n\t
+(l.add r1, r1, r0\n\t /* clear carry */
+ l.addic %0, %0, 0x\n\t
: +r(a)
);
if (a != result) {
@@ -16,10 +17,11 @@ int main(void)
return -1;
}
-a = 0x1;
+a = -1;
result = 0x201;
__asm
-(l.addic %0, %0, 0x\n\t
+(l.add r1, r1, r0\n\t /* clear carry */
+ l.addic %0, %0, 0x1\n\t
l.ori %0, r0, 0x100\n\t
l.addic %0, %0, 0x100\n\t
: +r(a)
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 3/7] target-openrisc: Remove executable flag for every page
From: Sebastian Macke sebast...@macke.de
Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 22d7cbe..dd487bd 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -32,7 +32,7 @@ int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
int *prot, target_ulong address, int rw)
{
*physical = address;
-*prot = PAGE_READ | PAGE_WRITE;
+*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
@@ -187,7 +187,7 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
if (ret == TLBRET_MATCH) {
tlb_set_page(env, address TARGET_PAGE_MASK,
- physical TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
} else if (ret 0) {
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 6/7] target-openrisc: Correct memory bounds checking for the tlb buffers
From: Sebastian Macke sebast...@macke.de
The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/sys_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index f116588..be06c45 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -81,7 +81,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 64): /* ESR */
env-esr = rb;
break;
-case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb 1)) {
tlb_flush_page(env, env-tlb-dtlb[0][idx].mr TARGET_PAGE_MASK);
@@ -89,7 +89,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
env-tlb-dtlb[0][idx].mr = rb;
break;
-case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env-tlb-dtlb[0][idx].tr = rb;
break;
@@ -100,7 +100,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
-case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
+case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb 1)) {
tlb_flush_page(env, env-tlb-itlb[0][idx].mr TARGET_PAGE_MASK);
@@ -108,7 +108,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
env-tlb-itlb[0][idx].mr = rb;
break;
-case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env-tlb-itlb[0][idx].tr = rb;
break;
@@ -212,11 +212,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
case TO_SPR(0, 64): /* ESR */
return env-esr;
-case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env-tlb-dtlb[0][idx].mr;
-case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
return env-tlb-dtlb[0][idx].tr;
@@ -228,11 +228,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
-case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
+case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
return env-tlb-itlb[0][idx].mr;
-case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
return env-tlb-itlb[0][idx].tr;
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7
Hi Anthony, Hi Blue, This is my OpenRISC patch queue for 1.7, it have been well tested, please pull. Thanks to Sebastian Macke, it made move optimization and fix some bugs. The following changes since commit 394cfa39ba24dd838ace1308ae24961243947fb8: Merge remote-tracking branch 'quintela/migration.next' into staging (2013-11-19 13:03:06 -0800) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 14a650ec25ca93a626397783d6c6e840ec2502c6: target-openrisc: Correct carry flag check of l.addc and l.addic test cases (2013-11-20 21:47:46 +0800) Sebastian Macke (7): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 - target-openrisc/cpu.h | 1 + target-openrisc/interrupt.c | 25 +++ target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c| 54 +++ target-openrisc/translate.c | 95 +++-- tests/tcg/openrisc/test_addc.c | 8 ++-- tests/tcg/openrisc/test_addic.c | 10 +++-- 8 files changed, 119 insertions(+), 107 deletions(-)
[Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction
From: Sebastian Macke sebast...@macke.de
The OpenRISC architecture does not have its own move register
instruction. Instead it uses either l.addi rd, r0, x or
l.ori rd, rs, 0 or l.or rd, rx, r0
The l.ori instruction is automatically optimized but not the l.addi instruction.
This patch optimizes for this special case.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 50 -
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8908a2e..8276ce7 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -904,29 +904,33 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
case 0x27:/* l.addi */
LOG_DIS(l.addi r%d, r%d, %d\n, rd, ra, I16);
{
-int lab = gen_new_label();
-TCGv_i64 ta = tcg_temp_new_i64();
-TCGv_i64 td = tcg_temp_local_new_i64();
-TCGv_i32 res = tcg_temp_local_new_i32();
-TCGv_i32 sr_ove = tcg_temp_local_new_i32();
-tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
-tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
-tcg_gen_trunc_i64_i32(res, td);
-tcg_gen_shri_i64(td, td, 32);
-tcg_gen_andi_i64(td, td, 0x3);
-/* Jump to lab when no overflow. */
-tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
-tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
-tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
-tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
-tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
-gen_exception(dc, EXCP_RANGE);
-gen_set_label(lab);
-tcg_gen_mov_i32(cpu_R[rd], res);
-tcg_temp_free_i64(ta);
-tcg_temp_free_i64(td);
-tcg_temp_free_i32(res);
-tcg_temp_free_i32(sr_ove);
+if (I16 == 0) {
+tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
+} else {
+int lab = gen_new_label();
+TCGv_i64 ta = tcg_temp_new_i64();
+TCGv_i64 td = tcg_temp_local_new_i64();
+TCGv_i32 res = tcg_temp_local_new_i32();
+TCGv_i32 sr_ove = tcg_temp_local_new_i32();
+tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
+tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
+tcg_gen_trunc_i64_i32(res, td);
+tcg_gen_shri_i64(td, td, 32);
+tcg_gen_andi_i64(td, td, 0x3);
+/* Jump to lab when no overflow. */
+tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
+tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
+tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
+tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
+tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
+gen_exception(dc, EXCP_RANGE);
+gen_set_label(lab);
+tcg_gen_mov_i32(cpu_R[rd], res);
+tcg_temp_free_i64(ta);
+tcg_temp_free_i64(td);
+tcg_temp_free_i32(res);
+tcg_temp_free_i32(sr_ove);
+}
}
break;
--
1.8.3.4 (Apple Git-47)
[Qemu-devel] [PULL 2/7] target-openrisc: Remove unnecessary code generated by jump instructions
From: Sebastian Macke sebast...@macke.de
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/translate.c | 45 ++---
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8276ce7..91c60eb 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -209,42 +209,49 @@ static void gen_goto_tb(DisasContext *dc, int n,
target_ulong dest)
static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t
op0)
{
target_ulong tmp_pc;
-int lab = gen_new_label();
-TCGv sr_f = tcg_temp_new();
/* N26, 26bits imm */
tmp_pc = sign_extend((imm2), 26) + dc-pc;
-tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
-if (op0 == 0x00) {/* l.j */
+switch (op0) {
+case 0x00: /* l.j */
tcg_gen_movi_tl(jmp_pc, tmp_pc);
-} else if (op0 == 0x01) {/* l.jal */
+break;
+case 0x01: /* l.jal */
tcg_gen_movi_tl(cpu_R[9], (dc-pc + 8));
tcg_gen_movi_tl(jmp_pc, tmp_pc);
-} else if (op0 == 0x03) {/* l.bnf */
-tcg_gen_movi_tl(jmp_pc, dc-pc+8);
-tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
-tcg_gen_movi_tl(jmp_pc, tmp_pc);
-gen_set_label(lab);
-} else if (op0 == 0x04) {/* l.bf */
-tcg_gen_movi_tl(jmp_pc, dc-pc+8);
-tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
-tcg_gen_movi_tl(jmp_pc, tmp_pc);
-gen_set_label(lab);
-} else if (op0 == 0x11) {/* l.jr */
+break;
+case 0x03: /* l.bnf */
+case 0x04: /* l.bf */
+{
+int lab = gen_new_label();
+TCGv sr_f = tcg_temp_new();
+tcg_gen_movi_tl(jmp_pc, dc-pc+8);
+tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
+tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
+sr_f, SR_F, lab);
+tcg_gen_movi_tl(jmp_pc, tmp_pc);
+gen_set_label(lab);
+tcg_temp_free(sr_f);
+}
+break;
+case 0x11: /* l.jr */
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
-} else if (op0 == 0x12) {/* l.jalr */
+break;
+case 0x12: /* l.jalr */
tcg_gen_movi_tl(cpu_R[9], (dc-pc + 8));
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
-} else {
+break;
+default:
gen_illegal_exception(dc);
+break;
}
-tcg_temp_free(sr_f);
dc-delayed_branch = 2;
dc-tb_flags |= D_FLAG;
gen_sync_flags(dc);
}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
--
1.8.3.4 (Apple Git-47)
Re: [Qemu-devel] [PATCH 00/13] target-openrisc: More optimizations and corrections
Hi Sebastian, On Wed, Oct 30, 2013 at 5:22 AM, Sebastian Macke sebast...@macke.de wrote: On 29/10/2013 2:15 PM, Max Filippov wrote: On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote: Hi, This is the second part of the patches to make the openrisc target faster and more reliable. Hi Sebastian, this series doesn't apply cleanly to the current qemu git head, what tree is it based on? It is based on the current master tree but depends on the patches I send on the 21st October. They got accepted by the maintainer but are not in the master tree right now. Your previous patch set separate SR is a little different from Arch spec, you said it will speed up some instructions, I think maybe it is a good reason and acceptable. But this one, going a little more too far, maybe you should consider on the comment from Max, Peter and Richard. More people comment your patch, make your code more better :) Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
Hi Sebastian, On Mon, Oct 28, 2013 at 9:56 AM, Sebastian Macke sebast...@macke.de wrote: On 25/10/2013 5:21 PM, Jia Liu wrote: On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote: On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Then, I'll make one pull request when you finish all you jobs, please let me know when you finish your last work, is it OK? Ok, do you want me to send then all patches including the old ones together in one patchset? At the moment this are 19 patches. Your call. Keep in mind that the new patches will change much more. And maybe there will be discussions of some decisions I made. But I promise also a speed increase of a factor of 7-10 :) When you summit a patch, I'll be always there :) Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote: On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Then, I'll make one pull request when you finish all you jobs, please let me know when you finish your last work, is it OK? Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] qemu-system-or32 is not working on OS X, ask for help.
Hi Peter, On Thu, Oct 17, 2013 at 5:15 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 17 October 2013 04:17, Jia Liu pro...@gmail.com wrote: On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu pro...@gmail.com wrote: I'm not sure about why qemu-system-or32 is not working on OS X, is it a AREG0 problem? May you please give me some suggestion, I want to test it on OS X, not Ubuntu any longer. The things that meant we had to use gcc for its put variable in a fixed native register functionality have gone away, so OSX+clang should work OK. I test the ARM targets from time to time and they work. GCC on OS X is OK, it looks like a Clang and GCC different, any suggestion, please? You'll need to debug the problem, that's all. Watch out that OSX gdb is broken in an odd way that means you can't really debug qemu under it (it breaks sigwait()). In general I think OSX is a poor target for trying to develop and debug qemu under, not least because of that gdb issue. But it should in principle work if you're not trying to run under the debugger. Thanks, I'll try lldb. -- PMM Regards, Jia
Re: [Qemu-devel] qemu-system-or32 is not working on OS X, ask for help.
Hi all, On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu pro...@gmail.com wrote: Hi all, I'm not sure about why qemu-system-or32 is not working on OS X, is it a AREG0 problem? May you please give me some suggestion, I want to test it on OS X, not Ubuntu any longer. GCC on OS X is OK, it looks like a Clang and GCC different, any suggestion, please? Thank you. Regards, Jia Regards, Jia
Re: [Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
Hi Anthony, Hi Peter, On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote: Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. As this is a pull request, the patches in it need your Signed-off-by, not just Reviewed-by. Need I resend this pull request? thanks -- PMM Regards, Jia
[Qemu-devel] qemu-system-or32 is not working on OS X, ask for help.
Hi all, I'm not sure about why qemu-system-or32 is not working on OS X, is it a AREG0 problem? May you please give me some suggestion, I want to test it on OS X, not Ubuntu any longer. Thank you. Regards, Jia
[Qemu-devel] [PULL 1/2] target-openrisc: Correct handling of page faults.
From: Sebastian Macke sebast...@macke.de
The result of (rw 0) is always zero and therefore a logic false.
The whole comparison will therefore never be executed, it is a obvious bug,
we should use !(rw 1) here.
Signed-off-by: Sebastian Macke sebast...@macke.de
Reviewed-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 57f5616..323a173 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
}
}
-if ((rw 0) ((right PAGE_READ) == 0)) {
+if (!(rw 1) ((right PAGE_READ) == 0)) {
return TLBRET_BADADDR;
}
if ((rw 1) ((right PAGE_WRITE) == 0)) {
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. This patch set correct two problems. The first one corrects one obvious bug concerning the handling of page faults while reading from a page. The second part removes a non-conforming behavior for the first page of the memory. Sebastian have tested this patch with the newest Linux kernel and compared the output with or1ksim. The following changes since commit a684f3cf9b9b9c3cb82be87aafc463de8974610c: Merge remote-tracking branch 'kraxel/seabios-1.7.3.2' into staging (2013-09-30 17:15:27 -0500) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 6ef8263ead779e1eecfaf1e0388f4c3941ea7ec3: target-openrisc: Removes a non-conforming behavior for the first page of the memory (2013-10-03 16:24:44 +0800) Sebastian Macke (2): target-openrisc: Correct handling of page faults. target-openrisc: Removes a non-conforming behavior for the first page of the memory target-openrisc/mmu.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-)
[Qemu-devel] [PULL 2/2] target-openrisc: Removes a non-conforming behavior for the first page of the memory
From: Sebastian Macke sebast...@macke.de
Where *software* leaves 0x - 0x2000 unmapped, the hardware should
still allow for this area to be mapped.
Signed-off-by: Sebastian Macke sebast...@macke.de
Signed-off-by: Stefan Kristiansson stefan.kristians...@saunalahti.fi
Reviewed-by: Jia Liu pro...@gmail.com
---
target-openrisc/mmu.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 323a173..22d7cbe 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
{
int ret = TLBRET_MATCH;
-/* [0x--0x2000]: unmapped */
-if (address 0x2000 (cpu-env.sr SR_SM)) {
-*physical = address;
-*prot = PAGE_READ | PAGE_WRITE;
-return ret;
-}
-
if (rw == 2) {/* ITLB */
*physical = 0;
ret = cpu-env.tlb-cpu_openrisc_map_address_code(cpu, physical,
--
1.7.12.4 (Apple Git-37)
Re: [Qemu-devel] [PULL 0/2] Correction of the TLB handling of the OpenRISC target
Hi Peter, On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 3 October 2013 17:41, Jia Liu pro...@gmail.com wrote: Hi Anthony, This is my OpenRISC patch queue. It originally come from Sebastian Macke, split by me, and I used some comment come from Stefan Kristiansson. Please pull. As this is a pull request, the patches in it need your Signed-off-by, not just Reviewed-by. Thank you for mention. thanks -- PMM Regards, Jia
Re: [Qemu-devel] [OpenRISC] [PATCH] Correction of the TLB handling of the OpenRISC target
On Wed, Oct 2, 2013 at 2:15 PM, Stefan Kristiansson
stefan.kristians...@saunalahti.fi wrote:
On Wed, Oct 2, 2013 at 8:33 AM, Jia Liu pro...@gmail.com wrote:
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke sebast...@macke.de
wrote:
Hi,
this patch corrects two problems for the OpenRISC Target in QEMU. The
first
one corrects one obvious bug
concerning the handling of page faults while reading from a page.
@@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
}
}
-if ((rw 0) ((right PAGE_READ) == 0)) {
+if (!(rw 1) ((right PAGE_READ) == 0)) {
return TLBRET_BADADDR;
}
if ((rw 1) ((right PAGE_WRITE) == 0)) {
They are just two type of one code...
No, (rw 0) always evaluates to 0.
The second
part removes a non-conforming behavior for the first page of the memory.
@@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU
*cpu,
{
int ret = TLBRET_MATCH;
-/* [0x--0x2000]: unmapped */
-if (address 0x2000 (cpu-env.sr SR_SM)) {
-*physical = address;
-*prot = PAGE_READ | PAGE_WRITE;
-return ret;
-}
-
May you please explain more about why the first page is non-conforming?
The Arch manual told me 0x--0x2000 is unmapped.
It shows an example where *software* leaves 0x - 0x2000 unmapped,
the hardware should still allow for this area to be mapped.
OK, thank you. I will send a PULL Request soon.
Reviewed-by: Jia Liu pro...@gmail.com
Stefan
Regards,
Jia
Re: [Qemu-devel] [OpenRISC] [PATCH] Correction of the TLB handling of the OpenRISC target
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke sebast...@macke.de wrote:
Hi,
this patch corrects two problems for the OpenRISC Target in QEMU. The first
one corrects one obvious bug
concerning the handling of page faults while reading from a page.
@@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
}
}
-if ((rw 0) ((right PAGE_READ) == 0)) {
+if (!(rw 1) ((right PAGE_READ) == 0)) {
return TLBRET_BADADDR;
}
if ((rw 1) ((right PAGE_WRITE) == 0)) {
They are just two type of one code...
The second
part removes a non-conforming behavior for the first page of the memory.
@@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
{
int ret = TLBRET_MATCH;
-/* [0x--0x2000]: unmapped */
-if (address 0x2000 (cpu-env.sr SR_SM)) {
-*physical = address;
-*prot = PAGE_READ | PAGE_WRITE;
-return ret;
-}
-
May you please explain more about why the first page is non-conforming?
The Arch manual told me 0x--0x2000 is unmapped.
I have tested this patch with the newest Linux kernel and compared the
output with or1ksim.
May you please upload a newest Linux kernel to somewhere?
Sebastian
___
OpenRISC mailing list
openr...@lists.openrisc.net
http://lists.openrisc.net/listinfo/openrisc
Regards,
Jia
Re: [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook
= superh_cpu_class_by_name;
+cc-has_work = superh_cpu_has_work;
cc-do_interrupt = superh_cpu_do_interrupt;
cc-dump_state = superh_cpu_dump_state;
cc-set_pc = superh_cpu_set_pc;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 276d295..2eafc2d 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -352,11 +352,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State
*env, target_ulong *pc,
| (env-movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
-return cpu-interrupt_request CPU_INTERRUPT_HARD;
-}
-
#include exec/exec-all.h
#endif /* _CPU_SH4_H */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 47ce60d..ede2c80 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -739,6 +739,15 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
TranslationBlock *tb)
cpu-env.npc = tb-cs_base;
}
+static bool sparc_cpu_has_work(CPUState *cs)
+{
+SPARCCPU *cpu = SPARC_CPU(cs);
+CPUSPARCState *env = cpu-env;
+
+return (cs-interrupt_request CPU_INTERRUPT_HARD)
+ cpu_interrupts_enabled(env);
+}
+
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
@@ -782,6 +791,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void
*data)
scc-parent_reset = cc-reset;
cc-reset = sparc_cpu_reset;
+cc-has_work = sparc_cpu_has_work;
cc-do_interrupt = sparc_cpu_do_interrupt;
cc-dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) !defined(CONFIG_USER_ONLY)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 41194ec..adf6557 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -747,15 +747,6 @@ static inline bool tb_am_enabled(int tb_flags)
#endif
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
-SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
-CPUSPARCState *env1 = sparc_cpu-env;
-
-return (cpu-interrupt_request CPU_INTERRUPT_HARD)
- cpu_interrupts_enabled(env1);
-}
-
#include exec/exec-all.h
#endif
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 3f78208..1cfe50a 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
cpu-env.regs[31] = value;
}
+static bool uc32_cpu_has_work(CPUState *cs)
+{
+return cs-interrupt_request
+(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
static inline void set_feature(CPUUniCore32State *env, int feature)
{
env-features |= feature;
@@ -138,6 +144,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void
*data)
dc-realize = uc32_cpu_realizefn;
cc-class_by_name = uc32_cpu_class_by_name;
+cc-has_work = uc32_cpu_has_work;
cc-do_interrupt = uc32_cpu_do_interrupt;
cc-dump_state = uc32_cpu_dump_state;
cc-set_pc = uc32_cpu_set_pc;
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 967511e..1db7419 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -160,10 +160,4 @@ static inline void
cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc
void uc32_translate_init(void);
void switch_mode(CPUUniCore32State *, int);
-static inline bool cpu_has_work(CPUState *cpu)
-{
-return cpu-interrupt_request
-(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
#endif /* QEMU_UNICORE32_CPU_H */
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index c19d17a..46573c6 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
cpu-env.pc = value;
}
+static bool xtensa_cpu_has_work(CPUState *cs)
+{
+XtensaCPU *cpu = XTENSA_CPU(cs);
+
+return cpu-env.pending_irq_level;
+}
+
/* CPUClass::reset() */
static void xtensa_cpu_reset(CPUState *s)
{
@@ -132,6 +139,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
*data)
cc-reset = xtensa_cpu_reset;
cc-class_by_name = xtensa_cpu_class_by_name;
+cc-has_work = xtensa_cpu_has_work;
cc-do_interrupt = xtensa_cpu_do_interrupt;
cc-dump_state = xtensa_cpu_dump_state;
cc-set_pc = xtensa_cpu_set_pc;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 95103e9..de27c8c 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -519,11 +519,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env, target_ulong *pc,
#include exec/cpu-all.h
#include exec/exec-all.h
-static inline int cpu_has_work(CPUState *cpu)
-{
-CPUXtensaState *env = XTENSA_CPU(cpu)-env;
-
-return env-pending_irq_level;
-}
-
#endif
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() into a CPUClass hook
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -137,10 +137,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address, int
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index(CPUUniCore32State *env)
-{
-return (env-uncached_asr ASR_M) == ASR_MODE_USER ? 1 : 0;
-}
#include exec/cpu-all.h
#include cpu-qom.h
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 46573c6..f99feaa 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
cpu-env.pc = value;
}
+static int xtensa_cpu_mmu_index(const CPUState *cs)
+{
+XtensaCPU *cpu = XTENSA_CPU(cs);
+
+return xtensa_get_cring(cpu-env);
+}
+
static bool xtensa_cpu_has_work(CPUState *cs)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
@@ -142,6 +149,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
*data)
cc-has_work = xtensa_cpu_has_work;
cc-do_interrupt = xtensa_cpu_do_interrupt;
cc-dump_state = xtensa_cpu_dump_state;
+cc-mmu_index = xtensa_cpu_mmu_index;
cc-set_pc = xtensa_cpu_set_pc;
cc-gdb_read_register = xtensa_cpu_gdb_read_register;
cc-gdb_write_register = xtensa_cpu_gdb_write_register;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index de27c8c..4fdaf20 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -472,11 +472,6 @@ static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState *env,
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3
-static inline int cpu_mmu_index(CPUXtensaState *env)
-{
-return xtensa_get_cring(env);
-}
-
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON
= cpu_model;
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index e07a4df..ab9d2cc 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -157,7 +157,6 @@ MoxieCPU *cpu_moxie_init(const char *cpu_model)
return NULL;
}
cpu = MOXIE_CPU(object_new(object_class_get_name(oc)));
-cpu-env.cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index b233969..b7104e3 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -241,7 +241,6 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
return NULL;
}
cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
-cpu-env.cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0934a45..db5e526 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8267,7 +8267,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char
*name)
PowerPCCPU *cpu_ppc_init(const char *cpu_model)
{
PowerPCCPU *cpu;
-CPUPPCState *env;
ObjectClass *oc;
Error *err = NULL;
@@ -8277,8 +8276,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
}
cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
-env = cpu-env;
-env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, err);
if (err != NULL) {
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index c9d3d55..e1ed6c0 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -73,11 +73,8 @@ void s390x_cpu_timer(void *opaque)
S390CPU *cpu_s390x_init(const char *cpu_model)
{
S390CPU *cpu;
-CPUS390XState *env;
cpu = S390_CPU(object_new(TYPE_S390_CPU));
-env = cpu-env;
-env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 7f98f80..1f1b8fd 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -172,7 +172,6 @@ static ObjectClass *superh_cpu_class_by_name(const char
*cpu_model)
SuperHCPU *cpu_sh4_init(const char *cpu_model)
{
SuperHCPU *cpu;
-CPUSH4State *env;
ObjectClass *oc;
oc = superh_cpu_class_by_name(cpu_model);
@@ -180,8 +179,6 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
return NULL;
}
cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
-env = cpu-env;
-env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index c8d8c55..9443713 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -84,7 +84,6 @@ static int cpu_sparc_register(CPUSPARCState *env, const
char *cpu_model)
env-def-features |= CPU_FEATURE_FLOAT128;
}
#endif
-env-cpu_model_str = cpu_model;
env-version = def-iu_version;
env-fsr = def-fpu_version;
env-nwindows = def-nwindows;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 4e90cf3..eece271 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -37,7 +37,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
}
cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
env = cpu-env;
-env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field from CPU_COMMON to CPUState
) {
if (ctx.pc == bp-pc) {
/* We have hit a breakpoint - make sure PC is up-to-date
*/
tcg_gen_movi_i32(cpu_pc, ctx.pc);
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 9443713..6c1ff68 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s)
scc-parent_reset(s);
-memset(env, 0, offsetof(CPUSPARCState, breakpoints));
+memset(env, 0, offsetof(CPUSPARCState, version));
tlb_flush(env, 1);
env-cwp = 0;
#ifndef TARGET_SPARC64
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index cfa1e0d..69c6154 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -421,6 +421,7 @@ struct CPUSPARCState {
CPU_COMMON
+/* Fields from here on are preserved across CPU reset. */
target_ulong version;
uint32_t nwindows;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 73f8b9c..bc52c85 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5254,8 +5254,8 @@ static inline void
gen_intermediate_code_internal(SPARCCPU *cpu,
max_insns = CF_COUNT_MASK;
gen_tb_start();
do {
-if (unlikely(!QTAILQ_EMPTY(env-breakpoints))) {
-QTAILQ_FOREACH(bp, env-breakpoints, entry) {
+if (unlikely(!QTAILQ_EMPTY(cs-breakpoints))) {
+QTAILQ_FOREACH(bp, cs-breakpoints, entry) {
if (bp-pc == dc-pc) {
if (dc-pc != pc_start)
save_state(dc);
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 1246895..b4bee99 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1925,8 +1925,8 @@ static inline void
gen_intermediate_code_internal(UniCore32CPU *cpu,
gen_tb_start();
do {
-if (unlikely(!QTAILQ_EMPTY(env-breakpoints))) {
-QTAILQ_FOREACH(bp, env-breakpoints, entry) {
+if (unlikely(!QTAILQ_EMPTY(cs-breakpoints))) {
+QTAILQ_FOREACH(bp, cs-breakpoints, entry) {
if (bp-pc == dc-pc) {
gen_set_pc_im(dc-pc);
gen_exception(EXCP_DEBUG);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 24343bd..55d4448 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2871,10 +2871,11 @@ invalid_opcode:
static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
{
+CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUBreakpoint *bp;
-if (unlikely(!QTAILQ_EMPTY(env-breakpoints))) {
-QTAILQ_FOREACH(bp, env-breakpoints, entry) {
+if (unlikely(!QTAILQ_EMPTY(cs-breakpoints))) {
+QTAILQ_FOREACH(bp, cs-breakpoints, entry) {
if (bp-pc == dc-pc) {
tcg_gen_movi_i32(cpu_pc, dc-pc);
gen_exception(dc, EXCP_DEBUG);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() argument to CPUState
);
+cpu_loop_exit(CPU(s390_env_get_cpu(env)));
break;
case SIGP_STOP:
qemu_system_shutdown_request();
-cpu_loop_exit(env);
+cpu_loop_exit(CPU(s390_env_get_cpu(env)));
break;
#endif
default:
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 6e527cf..271401f 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
}
@@ -77,7 +77,7 @@ static inline void QEMU_NORETURN
raise_exception(CPUSH4State *env, int index,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
void helper_raise_illegal_instruction(CPUSH4State *env)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index a393ef0..fb5f6ec 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -27,7 +27,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt)
CPUState *cs = CPU(sparc_env_get_cpu(env));
cs-exception_index = tt;
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
void helper_debug(CPUSPARCState *env)
@@ -35,7 +35,7 @@ void helper_debug(CPUSPARCState *env)
CPUState *cs = CPU(sparc_env_get_cpu(env));
cs-exception_index = EXCP_DEBUG;
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
#ifdef TARGET_SPARC64
@@ -239,6 +239,6 @@ void helper_power_down(CPUSPARCState *env)
cs-exception_index = EXCP_HLT;
env-pc = env-npc;
env-npc = env-pc + 4;
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
#endif
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 973fcb6..65ce724 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2443,7 +2443,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 3efc6a8..c2bf834 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t
excp)
CPUState *cs = CPU(uc32_env_get_cpu(env));
cs-exception_index = excp;
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
static target_ulong asr_read(CPUUniCore32State *env)
@@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cc1d5e2..17d7f35 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -104,7 +104,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
if (excp == EXCP_DEBUG) {
env-exception_taken = 0;
}
-cpu_loop_exit(env);
+cpu_loop_exit(cs);
}
void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t
cause)
@@ -390,7 +390,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc,
uint32_t intlevel)
(intlevel PS_INTLEVEL_SHIFT);
check_interrupts(env);
if (env-pending_irq_level) {
-cpu_loop_exit(env);
+cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
return;
}
diff --git a/user-exec.c b/user-exec.c
index dbb9c8d..e149c97 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -40,12 +40,12 @@
static void exception_action(CPUArchState *env1)
{
-#if defined(TARGET_I386)
CPUState *cpu = ENV_GET_CPU(env1);
+#if defined(TARGET_I386)
raise_exception_err(env1, cpu-exception_index, env1-error_code);
#else
-cpu_loop_exit(env1);
+cpu_loop_exit(cpu);
#endif
}
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument to CPUState
= s390_env_get_cpu(env);
int ret;
-ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
+S390CPU *cpu = S390_CPU(cs);
+CPUS390XState *env = cpu-env;
+
if (likely(retaddr)) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 03633f0..6e527cf 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -38,15 +38,17 @@
#define SHIFT 3
#include exec/softmmu_template.h
-void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
-SuperHCPU *cpu = sh_env_get_cpu(env);
int ret;
-ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
+SuperHCPU *cpu = SUPERH_CPU(cs);
+CPUSH4State *env = cpu-env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index af7c289..973fcb6 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2430,14 +2430,16 @@ static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState *env,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int
mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
-SPARCCPU *cpu = sparc_env_get_cpu(env);
int ret;
-ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+SPARCCPU *cpu = SPARC_CPU(cs);
+CPUSPARCState *env = cpu-env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index cd2cbef..3efc6a8 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env,
uint32_t x, uint32_t i)
#define SHIFT 3
#include exec/softmmu_template.h
-void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
-UniCore32CPU *cpu = uc32_env_get_cpu(env);
int ret;
-ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+UniCore32CPU *cpu = UNICORE32_CPU(cs);
+CPUUniCore32State *env = cpu-env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 2e006e4..cc1d5e2 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -59,9 +59,11 @@ static void do_unaligned_access(CPUXtensaState *env,
}
}
-void tlb_fill(CPUXtensaState *env,
-target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
+void tlb_fill(CPUState *cs,
+ target_ulong vaddr, int is_write, int mmu_idx, uintptr_t
retaddr)
{
+XtensaCPU *cpu = XTENSA_CPU(cs);
+CPUXtensaState *env = cpu-env;
uint32_t paddr;
uint32_t page_size;
unsigned access;
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() argument to CPUState
) {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(ENV_GET_CPU(env), retaddr);
}
helper_raise_exception(env, TT_UNALIGNED);
}
@@ -2437,11 +2437,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
-SPARCCPU *cpu = SPARC_CPU(cs);
-CPUSPARCState *env = cpu-env;
-
if (retaddr) {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index c2bf834..4c6950d 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write,
ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
-UniCore32CPU *cpu = UNICORE32_CPU(cs);
-CPUUniCore32State *env = cpu-env;
-
if (retaddr) {
/* now we have a real cpu fault */
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 17d7f35..24f7579 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -53,7 +53,7 @@ static void do_unaligned_access(CPUXtensaState *env,
{
if (xtensa_option_enabled(env-config,
XTENSA_OPTION_UNALIGNED_EXCEPTION)
!xtensa_option_enabled(env-config, XTENSA_OPTION_HW_ALIGNMENT))
{
-cpu_restore_state(env, retaddr);
+cpu_restore_state(ENV_GET_CPU(env), retaddr);
HELPER(exception_cause_vaddr)(env,
env-pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
}
@@ -79,7 +79,7 @@ void tlb_fill(CPUState *cs,
paddr TARGET_PAGE_MASK,
access, mmu_idx, page_size);
} else {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env-pc, ret, vaddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index ef34936..5673420 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -249,8 +249,9 @@ static int cpu_restore_state_from_tb(TranslationBlock
*tb, CPUArchState *env,
return 0;
}
-bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr)
+bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
{
+CPUArchState *env = cpu-env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(retaddr);
diff --git a/user-exec.c b/user-exec.c
index e149c97..75c6d54 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
unsigned long address,
return 1; /* the MMU fault was handled without causing real CPU
fault */
}
/* now we have a real cpu fault */
-cpu_restore_state(env, pc);
+cpu_restore_state(cpu, pc);
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState
Table Pointer Register */
@@ -901,7 +901,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
uint64_t val, int asi,
if (oldreg != env-mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
}
break;
case 3: /* Synchronous Fault Status Register with Clear */
@@ -1657,6 +1657,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
+SPARCCPU *cpu = sparc_env_get_cpu(env);
+
#ifdef DEBUG_ASI
dump_asi(write, addr, asi, size, val);
#endif
@@ -1865,7 +1867,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
addr, target_ulong val,
#ifdef DEBUG_MMU
dump_mmu(stdout, fprintf, env);
#endif
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
}
return;
}
@@ -1954,13 +1956,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
addr, target_ulong val,
env-dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
break;
case 2: /* Secondary context */
env-dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
break;
case 5: /* TSB access */
DPRINTF_MMU(dmmu TSB write: 0x%016 PRIx64 - 0x%016
@@ -2389,7 +2391,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr
addr,
/* flush neverland mappings created during no-fault mode,
so the sequential MMU faults report proper fault types */
if (env-mmuregs[0] MMU_NF) {
-tlb_flush(env, 1);
+tlb_flush(cs, 1);
}
}
#else
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index a353dab..3f3de4c 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUSPARCState *env = opaque;
+SPARCCPU *cpu = sparc_env_get_cpu(env);
int i;
uint32_t tmp;
@@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be64s(f, env-ssr);
cpu_get_timer(f, env-hstick);
#endif
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
return 0;
}
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index dcf3b16..a317217 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -141,7 +141,7 @@ static void uc32_cpu_initfn(Object *obj)
env-regs[31] = 0x0300;
#endif
-tlb_flush(env, 1);
+tlb_flush(cs, 1);
if (tcg_enabled() !inited) {
inited = true;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f91ed93..8de6a33 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -57,6 +57,8 @@ uint32_t HELPER(clz)(uint32_t x)
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)
{
+UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
/*
* movc pp.nn, rn, #imm9
* rn: UCOP_REG_D
@@ -125,7 +127,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val,
uint32_t creg,
case 6:
if ((cop = 6) (cop = 2)) {
/* invalid all tlb */
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
return;
}
break;
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 5771841..70937b6 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -479,10 +479,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env,
uint32_t pc, uint32_t vaddr)
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
+XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
v = (v 0xff00) | 0x1;
if (v != env-sregs[RASID]) {
env-sregs[RASID] = v;
-tlb_flush(env, 1);
+tlb_flush(CPU(cpu), 1);
}
}
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState
,
DPRINTF_MMU(mmu flush level %d\n, mmulev);
switch (mmulev) {
case 0: /* flush page */
-tlb_flush_page(env, addr 0xf000);
+tlb_flush_page(CPU(cpu), addr 0xf000);
break;
case 1: /* flush segment (256k) */
case 2: /* flush region (16M) */
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 5952ed8..5771841 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -679,7 +679,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v,
uint32_t dtlb)
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, wi);
if (entry-variable entry-asid) {
-tlb_flush_page(env, entry-vaddr);
+tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry-vaddr);
entry-asid = 0;
}
}
@@ -724,21 +724,24 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
+XtensaCPU *cpu = xtensa_env_get_cpu(env);
+CPUState *cs;
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env-config, XTENSA_OPTION_MMU)) {
if (entry-variable) {
+cs = CPU(cpu);
if (entry-asid) {
-tlb_flush_page(env, entry-vaddr);
+tlb_flush_page(cs, entry-vaddr);
}
xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
-tlb_flush_page(env, entry-vaddr);
+tlb_flush_page(cs, entry-vaddr);
} else {
qemu_log(%s %d, %d, %d trying to set immutable entry\n,
__func__, dtlb, wi, ei);
}
} else {
-tlb_flush_page(env, entry-vaddr);
+tlb_flush_page(CPU(cpu), entry-vaddr);
if (xtensa_option_enabled(env-config,
XTENSA_OPTION_REGION_TRANSLATION)) {
entry-paddr = pte REGION_PAGE_MASK;
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [RFC qom-cpu 33/41] cputlb: Change tlb_set_page() argument to CPUState
a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 164b34b..5952ed8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -74,10 +74,10 @@ void tlb_fill(CPUState *cs,
vaddr, is_write, mmu_idx, paddr, ret);
if (ret == 0) {
-tlb_set_page(env,
-vaddr TARGET_PAGE_MASK,
-paddr TARGET_PAGE_MASK,
-access, mmu_idx, page_size);
+tlb_set_page(cs,
+ vaddr TARGET_PAGE_MASK,
+ paddr TARGET_PAGE_MASK,
+ access, mmu_idx, page_size);
} else {
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env-pc, ret, vaddr);
target-openrisc: Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Re: [Qemu-devel] [PULL 0/3] OpenRISC patch queue for 1.7
Hi Peter, On Fri, Aug 23, 2013 at 10:09 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 21 August 2013 03:06, Jia Liu pro...@gmail.com wrote: This is my OpenRISC patch queue for 1.7, it have been well tested, please pull. Jia Liu (3): hw/openrisc: Avoid using uninitialised variable 'entry' hw/openrisc: Fix masking in openrisc_pic_cpu_handler() hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() Hi -- a couple of minor notes for next time you put together a pull: (1) your process for putting the git tree together has lost the authorship -- these patches weren't written by you, but the commits in your git repo (and thus now in master) have you as the Author. (If you use 'git am' or Anthony's 'patches apply' script it will get this right.) Thank you for reminding me, I'll use git am next time. (2) You should put your own Signed-off-by: line in each patchset, as an indication that the patches have come through your tree. thanks -- PMM Regards, Jia
Re: [Qemu-devel] [PATCH] hw/openrisc/openrisc_sim: Avoid using uninitialised variable 'entry'
Hi Peter,
On Tue, Aug 20, 2013 at 9:00 PM, Peter Maydell peter.mayd...@linaro.org wrote:
Ping for qemu-trivial now 1.7 is open.
Thank you, I'll send a PULL very soon.
thanks
-- PMM
On 5 August 2013 19:24, Peter Maydell peter.mayd...@linaro.org wrote:
clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used
uninitialized whenever '' condition is false
[-Werror,-Wsometimes-uninitialized]
if (kernel_filename !qtest_enabled()) {
^~~
hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
cpu-env.pc = entry;
^
Fix this by not attempting to change the CPU's starting PC unless
we actually loaded a kernel.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/openrisc/openrisc_sim.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index a08f27c..4595fa9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -86,9 +86,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
kernel_filename);
exit(1);
}
-}
-cpu-env.pc = entry;
+cpu-env.pc = entry;
+}
}
static void openrisc_sim_init(QEMUMachineInitArgs *args)
--
1.7.9.5
Regards,
Jia
[Qemu-devel] [PULL 2/3] hw/openrisc: Fix masking in openrisc_pic_cpu_handler()
Consider the masking of PICSR and PICMR:
((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i)))
To correctly mask bits, we should use the bitwise AND rather than
the logical AND . Also, the loop is not necessary for masking.
Simply use (cpu-env.picsr cpu-env.picmr).
Signed-off-by: Xi Wang xi.w...@gmail.com
Acked-by: Jia Liu pro...@gmail.com
---
hw/openrisc/pic_cpu.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index ca0b7c1..3fcee02 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq,
int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
-int i;
uint32_t irq_bit = 1 irq;
if (irq 31 || irq 0) {
@@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq,
int level)
cpu-env.picsr = ~irq_bit;
}
-for (i = 0; i 32; i++) {
-if ((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i))) {
-cpu_interrupt(cs, CPU_INTERRUPT_HARD);
-} else {
-cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
-cpu-env.picsr = ~(1 i);
-}
+if (cpu-env.picsr cpu-env.picmr) {
+cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+cpu-env.picsr = 0;
}
}
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 0/3] OpenRISC patch queue for 1.7
Hi Anthony, This is my OpenRISC patch queue for 1.7, it have been well tested, please pull. Thanks to Peter Maydell and Xi Wang, it fix OpenRISC sim broad and pic: * Avoid using uninitialised variable 'entry' * Fix masking in openrisc_pic_cpu_handler() * Avoid undefined shift in openrisc_pic_cpu_handler() The following changes since commit ecfe10c9a6f9bc77d0e4b7eb5d0f5d61e8fbaed8: Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130820' into staging (2013-08-20 11:23:52 -0500) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 7717f248eebdcfe6de400404d0cf65dcb3633308: hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() (2013-08-21 09:31:42 +0800) Jia Liu (3): hw/openrisc: Avoid using uninitialised variable 'entry' hw/openrisc: Fix masking in openrisc_pic_cpu_handler() hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() hw/openrisc/openrisc_sim.c | 3 +-- hw/openrisc/pic_cpu.c | 17 - 2 files changed, 9 insertions(+), 11 deletions(-)
[Qemu-devel] [PULL 3/3] hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler()
In C99 signed shift (1 31) is undefined behavior, since the result
exceeds INT_MAX. Use 1U instead and move the shift after the check.
Signed-off-by: Xi Wang xi.w...@gmail.com
Acked-by: Jia Liu pro...@gmail.com
---
hw/openrisc/pic_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index 3fcee02..2af1d60 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq,
int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
-uint32_t irq_bit = 1 irq;
+uint32_t irq_bit;
if (irq 31 || irq 0) {
return;
}
+irq_bit = 1U irq;
+
if (level) {
cpu-env.picsr |= irq_bit;
} else {
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 1/3] hw/openrisc: Avoid using uninitialised variable 'entry'
clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used uninitialized
whenever '' condition is false [-Werror,-Wsometimes-uninitialized]
if (kernel_filename !qtest_enabled()) {
^~~
hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
cpu-env.pc = entry;
^
Fix this by not attempting to change the CPU's starting PC unless
we actually loaded a kernel.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index a08f27c..28fa41d 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -86,9 +86,8 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
kernel_filename);
exit(1);
}
+cpu-env.pc = entry;
}
-
-cpu-env.pc = entry;
}
static void openrisc_sim_init(QEMUMachineInitArgs *args)
--
1.7.12.4 (Apple Git-37)
Re: [Qemu-devel] [PATCH v2 1/2] hw/openrisc: fix masking in openrisc_pic_cpu_handler()
Hi Xi,
You should use git format-patch with -s and --cover-letter next time,
and manually edit cover letter for a brief description of your patch set.
More info. at http://qemu-project.org/Contribute/SubmitAPatch .
On Wed, Aug 14, 2013 at 1:55 PM, Xi Wang xi.w...@gmail.com wrote:
Consider the masking of PICSR and PICMR:
((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i)))
To correctly mask bits, we should use the bitwise AND rather than
the logical AND . Also, the loop is not necessary for masking.
Simply use (cpu-env.picsr cpu-env.picmr).
Cc: Jia Liu pro...@gmail.com
Cc: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Xi Wang xi.w...@gmail.com
---
hw/openrisc/pic_cpu.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index ca0b7c1..3fcee02 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq,
int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
-int i;
uint32_t irq_bit = 1 irq;
if (irq 31 || irq 0) {
@@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int
irq, int level)
cpu-env.picsr = ~irq_bit;
}
-for (i = 0; i 32; i++) {
-if ((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i))) {
-cpu_interrupt(cs, CPU_INTERRUPT_HARD);
-} else {
-cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
-cpu-env.picsr = ~(1 i);
-}
+if (cpu-env.picsr cpu-env.picmr) {
+cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+cpu-env.picsr = 0;
}
}
Thank you very much for fixing this bug.
Acked-by: Jia Liu pro...@gmail.com
--
1.8.1.2
Regards,
Jia.
Re: [Qemu-devel] [PATCH v2 2/2] hw/openrisc: avoid undefined shift in openrisc_pic_cpu_handler()
Hi Xi,
On Wed, Aug 14, 2013 at 1:55 PM, Xi Wang xi.w...@gmail.com wrote:
In C99 signed shift (1 31) is undefined behavior, since the result
exceeds INT_MAX. Use 1U instead and move the shift after the check.
Cc: Jia Liu pro...@gmail.com
Cc: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Xi Wang xi.w...@gmail.com
---
hw/openrisc/pic_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index 3fcee02..2af1d60 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int
irq, int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
-uint32_t irq_bit = 1 irq;
+uint32_t irq_bit;
if (irq 31 || irq 0) {
return;
}
+irq_bit = 1U irq;
+
Thanks for making the code better.
Acked-by: Jia Liu pro...@gmail.com
if (level) {
cpu-env.picsr |= irq_bit;
} else {
--
1.8.1.2
Regards,
Jia
Re: [Qemu-devel] [PATCH 0/2] Disassembly with external objdump
Hi Richard, On Sat, Aug 10, 2013 at 3:19 AM, Richard Henderson r...@twiddle.net wrote: We have one host platform (aarch64), and three target platforms (openrisc, unicore32, xtensa) with no built-in disassembly support, thanks largely to gplv3 silliness. Thank you for doing this for or32. Here's a first-cut at handling these cases with an external tool. The qemu-produced dump file contains just a hex dump of bytes, and a perl script is provided to pass those bytes through objdump. I've lightly tested this with aarch64 host running on Foundation. Feedback appreciated. r~ Richard Henderson (2): disas: Implement fallback to dump object code as hex disas: Add disas-objdump.pl disas.c | 46 +++-- scripts/disas-objdump.pl | 87 2 files changed, 123 insertions(+), 10 deletions(-) create mode 100755 scripts/disas-objdump.pl -- 1.8.3.1 Regards, Jia
Re: [Qemu-devel] [PATCH] hw/openrisc/openrisc_sim: Avoid using uninitialised variable 'entry'
Hi Peter,
On Tue, Aug 6, 2013 at 2:24 AM, Peter Maydell peter.mayd...@linaro.org wrote:
clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used
uninitialized whenever '' condition is false
[-Werror,-Wsometimes-uninitialized]
if (kernel_filename !qtest_enabled()) {
^~~
hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
cpu-env.pc = entry;
^
Fix this by not attempting to change the CPU's starting PC unless
we actually loaded a kernel.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/openrisc/openrisc_sim.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index a08f27c..4595fa9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -86,9 +86,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
kernel_filename);
exit(1);
}
-}
-cpu-env.pc = entry;
+cpu-env.pc = entry;
+}
}
static void openrisc_sim_init(QEMUMachineInitArgs *args)
Thank you for using clang test it.
Reviewed-by: Jia Liu pro...@gmail.com
--
1.7.9.5
Regards,
Jia
Re: [Qemu-devel] [PATCH qom-cpu for-1.6] cpu: Partially revert cpu: Change qemu_init_vcpu() argument to CPUState
+++ b/target-m68k/cpu.c
@@ -143,12 +143,14 @@ static const M68kCPUInfo m68k_cpus[] = {
static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
{
+CPUState *cs = CPU(dev);
M68kCPU *cpu = M68K_CPU(dev);
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
m68k_cpu_init_gdb(cpu);
-cpu_reset(CPU(cpu));
+cpu_reset(cs);
+qemu_init_vcpu(cs);
mcc-parent_realize(dev, errp);
}
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index c75d1bd..0ef9aa4 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -90,10 +90,11 @@ static void mb_cpu_reset(CPUState *s)
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
-MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
+CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+cpu_reset(cs);
+qemu_init_vcpu(cs);
mcc-parent_realize(dev, errp);
}
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index f81f9e9..9dd47e8 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -62,10 +62,11 @@ static void mips_cpu_reset(CPUState *s)
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
-MIPSCPU *cpu = MIPS_CPU(dev);
+CPUState *cs = CPU(dev);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+cpu_reset(cs);
+qemu_init_vcpu(cs);
mcc-parent_realize(dev, errp);
}
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 6550be5..d97a091 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -45,10 +45,11 @@ static void moxie_cpu_reset(CPUState *s)
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
{
-MoxieCPU *cpu = MOXIE_CPU(dev);
+CPUState *cs = CPU(dev);
MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+qemu_init_vcpu(cs);
+cpu_reset(cs);
mcc-parent_realize(dev, errp);
}
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index aa269fb..075f00a 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -66,10 +66,11 @@ static inline void set_feature(OpenRISCCPU *cpu, int
feature)
static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
{
-OpenRISCCPU *cpu = OPENRISC_CPU(dev);
+CPUState *cs = CPU(dev);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+qemu_init_vcpu(cs);
+cpu_reset(cs);
occ-parent_realize(dev, errp);
}
target-openrisc Tested-by: Jia Liu pro...@gmail.com
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8215946..3c81798 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7861,6 +7861,8 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error
**errp)
34, power-spe.xml, 0);
}
+qemu_init_vcpu(cs);
+
pcc-parent_realize(dev, errp);
#if defined(PPC_DUMP_CPU)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 1d16da3..9b82495 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -101,10 +101,11 @@ static void s390_cpu_machine_reset_cb(void *opaque)
static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
{
-S390CPU *cpu = S390_CPU(dev);
+CPUState *cs = CPU(dev);
S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+qemu_init_vcpu(cs);
+cpu_reset(cs);
scc-parent_realize(dev, errp);
}
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index bda3c51..34b2b57 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -240,10 +240,11 @@ static const TypeInfo sh7785_type_info = {
static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
{
-SuperHCPU *cpu = SUPERH_CPU(dev);
+CPUState *cs = CPU(dev);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
-cpu_reset(CPU(cpu));
+cpu_reset(cs);
+qemu_init_vcpu(cs);
scc-parent_realize(dev, errp);
}
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index c7b4a90..47ce60d 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -743,6 +743,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error
**errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
+qemu_init_vcpu(CPU(dev));
+
scc-parent_realize(dev, errp);
}
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 46813e5..3f78208 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -92,6 +92,8 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error
**errp)
{
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
+qemu_init_vcpu(CPU(dev));
+
ucc-parent_realize(dev, errp);
}
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index e966aa0..c19d17a 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -90,6 +90,8 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error
Re: [Qemu-devel] [PATCH] target-or32: fix masking in openrisc_pic_cpu_handler()
Hi Xi,
On Tue, Jan 22, 2013 at 11:57 PM, Xi Wang xi.w...@gmail.com wrote:
A correct mask should be `x (1 i)', rather than `x (1 i)'.
Also, in C99 signed shift (1 31) is undefined behavior, since the
result exceeds INT_MAX; use 1U instead.
Signed-off-by: Xi Wang xi.w...@gmail.com
---
hw/openrisc_pic.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
index aaeb9a9..4f6d5a0 100644
--- a/hw/openrisc_pic.c
+++ b/hw/openrisc_pic.c
@@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int
irq, int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
int i;
-uint32_t irq_bit = 1 irq;
+uint32_t irq_bit;
if (irq 31 || irq 0) {
return;
}
+irq_bit = 1U irq;
+
Thanks, this part is OK.
if (level) {
cpu-env.picsr |= irq_bit;
} else {
@@ -39,11 +41,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int
irq, int level)
}
for (i = 0; i 32; i++) {
-if ((cpu-env.picsr (1 i)) (cpu-env.picmr (1 i))) {
+if ((cpu-env.picsr (1U i)) (cpu-env.picmr (1U i))) {
cpu_interrupt(cpu-env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cpu-env, CPU_INTERRUPT_HARD);
-cpu-env.picsr = ~(1 i);
+cpu-env.picsr = ~(1U i);
May you please test it? Your change here make qemu-system-or32 can not
boot Linux.
You can download pre-compiled Linux form here:
https://docs.google.com/file/d/0BxeTrz3x0CBLbTNmU0lrV1Y0V0U/edit?usp=sharing
or build one yourself.
}
}
}
--
1.7.10.4
At last, openrisc_pic.c is renamed into pic_cpu.c, please update your patch.
Regards,
Jia.
Re: [Qemu-devel] [PATCH qom-cpu for-1.6] cpu: Fix VMSTATE_CPU() semantics
On Mon, Jul 29, 2013 at 10:20 AM, Andreas Färber afaer...@suse.de wrote:
Commit 1a1562f5ea3da17d45d3829e35b5f49da9ec2db5 prepared a VMSTATE_CPU()
macro for device-style VMStateDescription registration, but missed to
adapt cpu_exec_init(), so that the cpu_common VMStateDescription was
still registered for AlphaCPU (fe31e7374299c0c6172ce618b29bf2fecbd881c7)
and OpenRISCCPU (da69721460e652072b6a3dd52b7693da21ffe237). Fix this.
Cc: Richard Henderson r...@twiddle.net
Cc: Jia Liu pro...@gmail.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index c4f2894..3ca9381 100644
--- a/exec.c
+++ b/exec.c
@@ -402,11 +402,14 @@ void cpu_exec_init(CPUArchState *env)
#if defined(CONFIG_USER_ONLY)
cpu_list_unlock();
#endif
-vmstate_register(NULL, cpu_index, vmstate_cpu_common, cpu);
+if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+vmstate_register(NULL, cpu_index, vmstate_cpu_common, cpu);
+}
#if defined(CPU_SAVE_VERSION) !defined(CONFIG_USER_ONLY)
register_savevm(NULL, cpu, cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
assert(cc-vmsd == NULL);
+assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
#endif
if (cc-vmsd != NULL) {
vmstate_register(NULL, cpu_index, cc-vmsd, cpu);
Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Regards,
Jia
Re: [Qemu-devel] [RFC for-next 2/2] cpu: Move VMSTATE_CPU() into TYPE_CPU VMStateDescription
On Mon, Jul 29, 2013 at 10:03 AM, Andreas Färber afaer...@suse.de wrote:
Assign DeviceClass::vmsd for common CPUState and drop VMSTATE_CPU() from
AlphaCPU and OpenRISCCPU.
Since we have two types of CPUs, those that register their state through
CPUClass::vmsd or CPU_SAVE_VERSION and those that register it through
DeviceClass::vmsd, we must keep device code from registering VMState
when only the base CPU class has DeviceClass::vmsd set.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/core/qdev.c| 5 +
include/qom/cpu.h | 4
qom/cpu.c | 10 ++
stubs/vmstate.c | 1 +
target-alpha/machine.c| 1 -
target-openrisc/machine.c | 1 -
6 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 0430fba..6035f64 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -685,6 +685,11 @@ static void device_register_vmstate(DeviceState *dev,
Error **errp)
oc = object_get_class(OBJECT(dev));
do {
dc = DEVICE_CLASS(oc);
+if (oc == object_class_by_name(cpu)
+fields == 0 subsections == 0) {
+/* Old-style CPU with common state as separate VMSD */
+break;
+}
if (dc-vmsd != NULL) {
if (vmsd == NULL) {
vmsd = dc-vmsd;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 0d6e95c..e0ad8b6 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -507,11 +507,7 @@ void qemu_init_vcpu(CPUState *cpu);
*/
void cpu_single_step(CPUState *cpu, int enabled);
-#ifdef CONFIG_SOFTMMU
extern const struct VMStateDescription vmstate_cpu_common;
-#else
-#define vmstate_cpu_common vmstate_dummy
-#endif
#define VMSTATE_CPU() { \
.name = parent_obj, \
diff --git a/qom/cpu.c b/qom/cpu.c
index dbc9fb6..a3e47cb 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -24,6 +24,7 @@
#include qemu/notify.h
#include qemu/log.h
#include sysemu/sysemu.h
+#include migration/vmstate.h
typedef struct CPUExistsArgs {
int64_t id;
@@ -250,6 +251,14 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu-cpu_index;
}
+static const VMStateDescription vmstate_cpu_device = {
+.name = CPU,
+.fields = (VMStateField[]) {
+VMSTATE_CPU(),
+VMSTATE_END_OF_LIST()
+},
+};
+
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -268,6 +277,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k-gdb_write_register = cpu_common_gdb_write_register;
dc-realize = cpu_common_realizefn;
dc-no_user = 1;
+dc-vmsd = vmstate_cpu_device;
}
static const TypeInfo cpu_type_info = {
diff --git a/stubs/vmstate.c b/stubs/vmstate.c
index 778bc3f..22e2bd4 100644
--- a/stubs/vmstate.c
+++ b/stubs/vmstate.c
@@ -2,6 +2,7 @@
#include migration/vmstate.h
const VMStateDescription vmstate_dummy = {};
+const VMStateDescription vmstate_cpu_common = {};
int vmstate_register_with_alias_id(DeviceState *dev,
int instance_id,
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 889f2fc..e3e75fb 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -77,7 +77,6 @@ static const VMStateDescription vmstate_env = {
};
static VMStateField vmstate_cpu_fields[] = {
-VMSTATE_CPU(),
VMSTATE_STRUCT(env, AlphaCPU, 1, vmstate_env, CPUAlphaState),
VMSTATE_END_OF_LIST()
};
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 6f864fe..372b261 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -45,7 +45,6 @@ const VMStateDescription vmstate_openrisc_cpu = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
-VMSTATE_CPU(),
VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
VMSTATE_END_OF_LIST()
}
Tested-by: Jia Liu pro...@gmail.com
--
1.8.1.4
Regards,
Jia
[Qemu-devel] [PULL 0/3] OpenRISC patch queue
Hi Anthony, This is my OpenRISC patch queue, and myfirst time to send a pull requests, please pull. It fix OpenRISC CPU and sim broad: * Free typename in openrisc_cpu_class_by_name * Use stderr output in openrisc_sim.c * fixed a indent typo. The following changes since commit 3464700f6aecb3e2aa9098839d90672d6b3fa974: tests: Add test-bitops.c with some sextract tests (2013-07-22 15:41:49 -0500) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 9b146e9a28bbd9567f5ac6a8e2bcb543aa3b9392: target-openrisc: Free typename in openrisc_cpu_class_by_name (2013-07-23 18:32:30 +0800) Jia Liu (3): hw/openrisc: Indent typo hw/openrisc: Use stderr output instead of qemu_log target-openrisc: Free typename in openrisc_cpu_class_by_name hw/openrisc/openrisc_sim.c | 6 +++--- target-openrisc/cpu.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-)
[Qemu-devel] [PULL 1/3] hw/openrisc: Indent typo
Indent typo. Signed-off-by: Jia Liu pro...@gmail.com Reviewed-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Andreas Färber afaer...@suse.de --- hw/openrisc/openrisc_sim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 924438b..250f5b5 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args) ram_addr_t ram_size = args-ram_size; const char *cpu_model = args-cpu_model; const char *kernel_filename = args-kernel_filename; - OpenRISCCPU *cpu = NULL; +OpenRISCCPU *cpu = NULL; MemoryRegion *ram; int n; -- 1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 3/3] target-openrisc: Free typename in openrisc_cpu_class_by_name
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PULL 2/3] hw/openrisc: Use stderr output instead of qemu_log
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Andreas Färber afaer...@suse.de
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 250f5b5..a08f27c 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -82,7 +82,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
}
if (kernel_size 0) {
-qemu_log(QEMU: couldn't load the kernel '%s'\n,
+fprintf(stderr, QEMU: couldn't load the kernel '%s'\n,
kernel_filename);
exit(1);
}
@@ -107,7 +107,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
for (n = 0; n smp_cpus; n++) {
cpu = cpu_openrisc_init(cpu_model);
if (cpu == NULL) {
-qemu_log(Unable to find CPU definition!\n);
+fprintf(stderr, Unable to find CPU definition!\n);
exit(1);
}
qemu_register_reset(main_cpu_reset, cpu);
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v3 0/4] target-openrisc hw/openrisc: Some OpenRISC fix.
Fix OpenRISC CPU and sim broad, we should free typename and check cpu models by name in cpu.c, and we should use stderr output in openrisc_sim.c. Updates from V3: * Replace a typo fix using a stderr fix. Updates from V2: * Combine typo patchset and typename free. * Add cpu_model by name fix, make any and or1200 works both OK. Jia Liu (4): hw/openrisc: Indent typo hw/openrisc: Use stderr output instead of qemu_log target-openrisc: Free typename target-openrisc: Fix cpu_model by name hw/openrisc/openrisc_sim.c | 6 +++--- target-openrisc/cpu.c | 17 + 2 files changed, 16 insertions(+), 7 deletions(-) -- 1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v3 1/4] hw/openrisc: Indent typo
Indent typo. Signed-off-by: Jia Liu pro...@gmail.com --- hw/openrisc/openrisc_sim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 924438b..250f5b5 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args) ram_addr_t ram_size = args-ram_size; const char *cpu_model = args-cpu_model; const char *kernel_filename = args-kernel_filename; - OpenRISCCPU *cpu = NULL; +OpenRISCCPU *cpu = NULL; MemoryRegion *ram; int n; -- 1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v3 3/4] target-openrisc: Free typename
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v3 4/4] target-openrisc: Fix cpu_model by name
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e348df0..6637166 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -100,11 +100,19 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
-if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
- object_class_is_abstract(oc))) {
-return NULL;
+
+if (oc != NULL object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) != NULL
+ !object_class_is_abstract(oc)) {
+return oc;
}
-return oc;
+
+oc = object_class_by_name(cpu_model);
+if (oc != NULL object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) != NULL
+ !object_class_is_abstract(oc)) {
+return oc;
+}
+
+return NULL;
}
static void or1200_initfn(Object *obj)
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v3 2/4] hw/openrisc: Use stderr output instead of qemu_log
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 250f5b5..a08f27c 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -82,7 +82,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
}
if (kernel_size 0) {
-qemu_log(QEMU: couldn't load the kernel '%s'\n,
+fprintf(stderr, QEMU: couldn't load the kernel '%s'\n,
kernel_filename);
exit(1);
}
@@ -107,7 +107,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
for (n = 0; n smp_cpus; n++) {
cpu = cpu_openrisc_init(cpu_model);
if (cpu == NULL) {
-qemu_log(Unable to find CPU definition!\n);
+fprintf(stderr, Unable to find CPU definition!\n);
exit(1);
}
qemu_register_reset(main_cpu_reset, cpu);
--
1.7.12.4 (Apple Git-37)
Re: [Qemu-devel] [PATCH v3 3/4] target-openrisc: Free typename
Hi Andreas,
On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu pro...@gmail.com wrote:
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Sorry I didn't know I need add Signed-off-by: Andreas Färber your@mail here.
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
--
1.7.12.4 (Apple Git-37)
Regards,
Jia.
Re: [Qemu-devel] [PATCH v3 4/4] target-openrisc: Fix cpu_model by name
Hi Andreas and Peter,
On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 July 2013 09:56, Jia Liu pro...@gmail.com wrote:
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e348df0..6637166 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -100,11 +100,19 @@ static ObjectClass *openrisc_cpu_class_by_name(const
char *cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
-if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
- object_class_is_abstract(oc))) {
-return NULL;
+
+if (oc != NULL object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) !=
NULL
+ !object_class_is_abstract(oc)) {
+return oc;
}
-return oc;
+
+oc = object_class_by_name(cpu_model);
+if (oc != NULL object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) !=
NULL
+ !object_class_is_abstract(oc)) {
+return oc;
+}
+
+return NULL;
}
This looks a bit odd. The commit message suggests it's an
attempt to fix the bug that was fixed by commit 071b3364e --
is it really needed? Andreas?
commit 071b3364e fix the typename only, but this one make -cpu any
-cpu or1200 -cpu any-or32-cpu -cpu or1200-or32-cpu working fine.
thanks
-- PMM
Regards,
Jia
Re: [Qemu-devel] [PATCH v3 3/4] target-openrisc: Free typename
On Mon, Jul 22, 2013 at 5:41 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 22 July 2013 10:37, Jia Liu pro...@gmail.com wrote: Hi Andreas, On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu pro...@gmail.com wrote: We should free typename here. Signed-off-by: Jia Liu pro...@gmail.com Sorry I didn't know I need add Signed-off-by: Andreas Färber your@mail here. Not Signed-off-by, Reviewed-by. The distinction is important. Thanks Peter, I got. thanks -- PMM Regards, Jia
Re: [Qemu-devel] [PATCH v3 4/4] target-openrisc: Fix cpu_model by name
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 22 July 2013 10:42, Jia Liu pro...@gmail.com wrote: Hi Andreas and Peter, On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org wrote: This looks a bit odd. The commit message suggests it's an attempt to fix the bug that was fixed by commit 071b3364e -- is it really needed? Andreas? commit 071b3364e fix the typename only, but this one make -cpu any -cpu or1200 -cpu any-or32-cpu -cpu or1200-or32-cpu working fine. The last two of these would be wrong: -cpu should only accept CPU names, ie any or or1200. So, I need make only -cpu any and -cpu or1200 accepted, thanks. -- PMM Regards, Jia
Re: [Qemu-devel] [PATCH v3 4/4] target-openrisc: Fix cpu_model by name
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 22 July 2013 10:42, Jia Liu pro...@gmail.com wrote: Hi Andreas and Peter, On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell peter.mayd...@linaro.org wrote: This looks a bit odd. The commit message suggests it's an attempt to fix the bug that was fixed by commit 071b3364e -- is it really needed? Andreas? Yes! you are right, it is not needed. It was my mistake, I didn't understand Andreas. Thanks! It seems I need resend a v4 with Reviewed-by AndreasPeter. commit 071b3364e fix the typename only, but this one make -cpu any -cpu or1200 -cpu any-or32-cpu -cpu or1200-or32-cpu working fine. The last two of these would be wrong: -cpu should only accept CPU names, ie any or or1200. -- PMM Regards, Jia.
[Qemu-devel] [PATCH v4 2/3] hw/openrisc: Use stderr output instead of qemu_log
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 250f5b5..a08f27c 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -82,7 +82,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
}
if (kernel_size 0) {
-qemu_log(QEMU: couldn't load the kernel '%s'\n,
+fprintf(stderr, QEMU: couldn't load the kernel '%s'\n,
kernel_filename);
exit(1);
}
@@ -107,7 +107,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
for (n = 0; n smp_cpus; n++) {
cpu = cpu_openrisc_init(cpu_model);
if (cpu == NULL) {
-qemu_log(Unable to find CPU definition!\n);
+fprintf(stderr, Unable to find CPU definition!\n);
exit(1);
}
qemu_register_reset(main_cpu_reset, cpu);
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v4 3/3] target-openrisc: Free typename in openrisc_cpu_class_by_name
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH v4 1/3] hw/openrisc: Indent typo
Indent typo. Signed-off-by: Jia Liu pro...@gmail.com Reviewed-by: Peter Maydell peter.mayd...@linaro.org --- hw/openrisc/openrisc_sim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 924438b..250f5b5 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args) ram_addr_t ram_size = args-ram_size; const char *cpu_model = args-cpu_model; const char *kernel_filename = args-kernel_filename; - OpenRISCCPU *cpu = NULL; +OpenRISCCPU *cpu = NULL; MemoryRegion *ram; int n; -- 1.7.12.4 (Apple Git-37)
Re: [Qemu-devel] [PATCH] linux-user: Fix target_stat and target_stat64 for OpenRISC
Hi Peter, On Fri, Jul 19, 2013 at 5:27 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 19 July 2013 01:25, Jia Liu pro...@gmail.com wrote: Hi Peter, On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell peter.mayd...@linaro.org wrote: Ping? Thank you, it looks good to me, please push it. The usual way to say this is to add your reviewed-by or acked-by tag (depending on how thoroughly you checked it)... Got it. Reviewed-by: Jia Liu pro...@gmail.com thanks -- PMM Regards, Jia
Re: [Qemu-devel] [PATCH] linux-user: Fix target_stat and target_stat64 for OpenRISC
Hi Peter,
On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell peter.mayd...@linaro.org wrote:
Ping?
Thank you, it looks good to me, please push it.
thanks
-- PMM
On 6 July 2013 21:44, Peter Maydell peter.mayd...@linaro.org wrote:
OpenRISC uses the asm-generic versions of target_stat and
target_stat64, but it was incorrectly using the x86/ARM/etc version
due to a misplaced defined(TARGET_OPENRISC). The previously unused
OpenRISC section of the ifdef ladder also defined an incorrect
target_stat and omitted the target_stat64 definition. Fix
target_stat, provide target_stat64, and add a comment noting that
these are the asm-generic versions for the benefit of future ports.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
This fixes basic problems like ls -l output is nonsense and shell
thinks programs aren't executable and won't run them.
linux-user/syscall_defs.h | 49
++---
1 file changed, 37 insertions(+), 12 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 92c01a9..cb6341f 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -1138,8 +1138,7 @@ struct target_winsize {
#endif
#if (defined(TARGET_I386) defined(TARGET_ABI32)) || defined(TARGET_ARM) \
-|| defined(TARGET_CRIS) || defined(TARGET_UNICORE32) \
-|| defined(TARGET_OPENRISC)
+|| defined(TARGET_CRIS) || defined(TARGET_UNICORE32)
struct target_stat {
unsigned short st_dev;
unsigned short __pad1;
@@ -1837,29 +1836,55 @@ struct target_stat {
abi_ulong __unused[3];
};
#elif defined(TARGET_OPENRISC)
+
+/* These are the asm-generic versions of the stat and stat64 structures */
+
struct target_stat {
abi_ulong st_dev;
abi_ulong st_ino;
-abi_ulong st_nlink;
-
unsigned int st_mode;
+unsigned int st_nlink;
unsigned int st_uid;
unsigned int st_gid;
-unsigned int __pad0;
abi_ulong st_rdev;
+abi_ulong __pad1;
abi_long st_size;
-abi_long st_blksize;
-abi_long st_blocks;/* Number 512-byte blocks allocated. */
-
-abi_ulong target_st_atime;
+int st_blksize;
+int __pad2;
+abi_long st_blocks;
+abi_long target_st_atime;
abi_ulong target_st_atime_nsec;
-abi_ulong target_st_mtime;
+abi_long target_st_mtime;
abi_ulong target_st_mtime_nsec;
-abi_ulong target_st_ctime;
+abi_long target_st_ctime;
abi_ulong target_st_ctime_nsec;
+unsigned int __unused4;
+unsigned int __unused5;
+};
-abi_long __unused[3];
+struct target_stat64 {
+uint64_t st_dev;
+uint64_t st_ino;
+unsigned int st_mode;
+unsigned int st_nlink;
+unsigned int st_uid;
+unsigned int st_gid;
+uint64_t st_rdev;
+uint64_t __pad1;
+int64_t st_size;
+int st_blksize;
+int __pad2;
+int64_t st_blocks;
+int target_st_atime;
+unsigned int target_st_atime_nsec;
+int target_st_mtime;
+unsigned int target_st_mtime_nsec;
+int target_st_ctime;
+unsigned int target_st_ctime_nsec;
+unsigned int __unused4;
+unsigned int __unused5;
};
+
#else
#error unsupported CPU
#endif
--
1.7.9.5
Regards,
Jia
Re: [Qemu-devel] [PATCH 3/4] target-openrisc: Free typename
Hi Andreas,
On Tue, Jul 16, 2013 at 10:19 PM, Andreas Färber afaer...@suse.de wrote:
Am 16.07.2013 04:00, schrieb Jia Liu:
We should free typename here.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
Reviewed-by: Andreas Färber afaer...@suse.de
Thank you, Andreas.
May you want to review the other three? :) I've tested them all.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Regards,
Jia.
[Qemu-devel] [PATCH] hw/openrisc: typo in openrisc_sim
2 indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..f0dabb9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -83,7 +83,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
if (kernel_size 0) {
qemu_log(QEMU: couldn't load the kernel '%s'\n,
-kernel_filename);
+ kernel_filename);
exit(1);
}
}
@@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
ram_addr_t ram_size = args-ram_size;
const char *cpu_model = args-cpu_model;
const char *kernel_filename = args-kernel_filename;
- OpenRISCCPU *cpu = NULL;
+OpenRISCCPU *cpu = NULL;
MemoryRegion *ram;
int n;
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH 1/2] target-openrisc: Free typename in cpu_class_by_name
Add a g_free into openrisc_cpu_class_by_name to free typename.
Signed-off-by: Jia Liu pro...@gmail.com
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char
*cpu_model)
typename = g_strdup_printf(%s- TYPE_OPENRISC_CPU, cpu_model);
oc = object_class_by_name(typename);
+g_free(typename);
if (oc != NULL (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
return NULL;
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH 2/2] hw/openrisc: Use stderr output instead of qemu_log
Here should be stderr output instead of qemu_log.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..26bff75 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -107,7 +107,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
for (n = 0; n smp_cpus; n++) {
cpu = cpu_openrisc_init(cpu_model);
if (cpu == NULL) {
-qemu_log(Unable to find CPU definition!\n);
+fprintf(stderr, Unable to find CPU definition!\n);
exit(1);
}
qemu_register_reset(main_cpu_reset, cpu);
--
1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH 0/2] target-openrisc hw/openrisc: Two OpenRISC fix.
Fix OpenRISC CPU and sim broad, in cpu.c we should free typename, and in openrisc_sim.c we should use stderr output. Jia Liu (2): target-openrisc: free typename in cpu_class_by_name hw/openrisc: Use stderr output instead of qemu_log hw/openrisc/openrisc_sim.c | 2 +- target-openrisc/cpu.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- 1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH V2 0/4] target-openrisc hw/openrisc: Some OpenRISC fix.
Fix OpenRISC CPU and sim broad, we should free typename and check cpu models by name in cpu.c, and we should use stderr output in openrisc_sim.c. Jia Liu (4): hw/openrisc: Indent typo hw/openrisc: Use stderr output instead of qemu_log target-openrisc: Free typename target-openrisc: Fix cpu_model by name hw/openrisc/openrisc_sim.c | 8 target-openrisc/cpu.c | 17 + 2 files changed, 17 insertions(+), 8 deletions(-) -- 1.7.12.4 (Apple Git-37)
[Qemu-devel] [PATCH V2 1/4] hw/openrisc: Indent typo
Indent typo.
Signed-off-by: Jia Liu pro...@gmail.com
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..f0dabb9 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -83,7 +83,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
if (kernel_size 0) {
qemu_log(QEMU: couldn't load the kernel '%s'\n,
-kernel_filename);
+ kernel_filename);
exit(1);
}
}
@@ -96,7 +96,7 @@ static void openrisc_sim_init(QEMUMachineInitArgs *args)
ram_addr_t ram_size = args-ram_size;
const char *cpu_model = args-cpu_model;
const char *kernel_filename = args-kernel_filename;
- OpenRISCCPU *cpu = NULL;
+OpenRISCCPU *cpu = NULL;
MemoryRegion *ram;
int n;
--
1.7.12.4 (Apple Git-37)
