[PATCH RESEND 11/11] target/ppc: Implement slbiag
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 649b2a9c58..2e7c61e117 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,6 +695,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fb53bce0c8..e4aa336bbf 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
_rb rb
@X_rb .. . . rb:5 .. ._rb
+_rs_l rs l:bool
+@X_rs_l .. rs:5 l:1 . .. . _rs_l
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -822,6 +825,7 @@ SLBIE 01 - - . 0110110010 -
@X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBIAG 01 . . - 1101010010 - @X_rs_l
SLBMTE 01 . - . 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = >slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
[PATCH RESEND 05/11] target/ppc: Move slbia to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 5 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8f9dde6d3f..c2440a8854 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -694,7 +694,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env,
tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d3517d412c..1349c5e8a7 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_ih ih:uint8_t
+@X_ih .. .. ih:3 . . .. . _ih
+
_rb rb
@X_rb .. . . rb:5 .. ._rb
@@ -818,6 +821,8 @@ VMODUQ 000100 . . . 1101011@VX
SLBIE 01 - - . 0110110010 - @X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
+SLBIA 01 --... - - 010010 - @X_ih
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a842fbd6f6..dd2c7e588f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
}
#ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
{
PowerPCCPU *cpu = env_archcpu(env);
int starting_entry;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ad19a68f5c..5d2416143f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5450,22 +5450,6 @@ static void gen_tlbsync(DisasContext *ctx)
}
#if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-uint32_t ih = (ctx->opcode >> 21) & 0x7;
-TCGv_i32 t0 = tcg_const_i32(ih);
-
-CHK_SV(ctx);
-
-gen_helper_slbia(cpu_env, t0);
-tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6885,7 +6869,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b9bb950f7d..cbb8b81f13 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -49,6 +49,20 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
return true;
}
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 10/11] target/ppc: Move slbsync to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a28d31e123..fb53bce0c8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -830,6 +830,8 @@ SLBMFEE 01 . - . 1110010011 -
@X_tb
SLBFEE 01 . - . 010011 1 @X_tb
+SLBSYNC 01 - - - 0101010010 -
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 150318d70e..a918575fa9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5388,20 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-#if defined(TARGET_PPC64)
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif /* defined(TARGET_PPC64) */
-
/*** External control ***/
/* Optional: */
@@ -6803,9 +6789,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
* different ISA versions
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x0001, PPC_EXTERN),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 260bce35ac..c90cad10b4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -139,6 +139,20 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
return true;
}
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_check_tlb_flush(ctx, true);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 09/11] target/ppc: Move slbfee to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 26 ---
target/ppc/translate/storage-ctrl-impl.c.inc | 34
5 files changed, 38 insertions(+), 28 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 848665a4f4..649b2a9c58 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -693,7 +693,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0797a19896..a28d31e123 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -828,6 +828,8 @@ SLBMTE 01 . - . 0110010010 -
@X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
SLBMFEE 01 . - . 1110010011 - @X_tb
+SLBFEE 01 . - . 010011 1 @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 5d73d64436..7ec7a67a78 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -331,7 +331,7 @@ target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong
rb)
return rt;
}
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eadf4ca1b7..150318d70e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,31 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
-TCGLabel *l1, *l2;
-
-if (unlikely(ctx->pr)) {
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-return;
-}
-gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-l1 = gen_new_label();
-l2 = gen_new_label();
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
-gen_set_label(l2);
-#endif
-}
#endif /* defined(TARGET_PPC64) */
/*** Lookaside buffer management ***/
@@ -6821,7 +6796,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
/*
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b169bd6317..260bce35ac 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -105,6 +105,40 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE
*a)
return true;
}
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+TCGLabel *l1, *l2;
+
+if (unlikely(ctx->pr)) {
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+return true;
+}
+gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+l1 = gen_new_label();
+l2 = gen_new_label();
+tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+tcg_gen_br(l2);
+gen_set_label(l1);
+tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+gen_set_label(l2);
+#else
+qemu_build_not_reached();
+#endif
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 06/11] target/ppc: Move slbmte to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c2440a8854..ad88073ae0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -690,7 +690,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
-DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1349c5e8a7..e255f9241b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -823,6 +823,8 @@ SLBIEG 01 . - . 0111010010 -
@X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBMTE 01 . - . 0110010010 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index dd2c7e588f..1922960608 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -309,7 +309,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong
rb,
return 0;
}
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = env_archcpu(env);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5d2416143f..d421fe267c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,19 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbmte */
-static void gen_slbmte(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbmfee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -6857,7 +6844,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index cbb8b81f13..4c2dd758b5 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 07/11] target/ppc: Move slbmfev to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 12
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ad88073ae0..1d23de7358 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -692,7 +692,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e255f9241b..9354014ca5 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -825,6 +825,8 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
+SLBMFEV 01 . - . 1101010011 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1922960608..7854b91043 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -343,7 +343,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env,
target_ulong rb)
return rt;
}
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d421fe267c..6b44c6312b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5363,17 +5363,6 @@ static void gen_slbmfee(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6845,7 +6834,6 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06,
0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 4c2dd758b5..a037fc2b95 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -77,6 +77,20 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
return true;
}
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 08/11] target/ppc: Move slbmfee to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 1d23de7358..848665a4f4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -691,7 +691,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
-DEF_HELPER_2(load_slb_esid, tl, env, tl)
+DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9354014ca5..0797a19896 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -826,6 +826,7 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
+SLBMFEE 01 . - . 1110010011 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7854b91043..5d73d64436 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -319,7 +319,7 @@ void helper_SLBMTE(CPUPPCState *env, target_ulong rb,
target_ulong rs)
}
}
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6b44c6312b..eadf4ca1b7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,18 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfee(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6833,7 +6821,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index a037fc2b95..b169bd6317 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -91,6 +91,20 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
return true;
}
+static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 02/11] target/ppc: add macros to check privilege level
From: Matheus Ferst
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Reviewed-by: Leandro Lupori
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 21 +
target/ppc/translate/fixedpoint-impl.c.inc | 7 ++-
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 920bb543cf..275cffb2a7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,6 +6575,27 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+do {\
+if (unlikely((CTX)->pr)) { \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+
+#define REQUIRE_HV(CTX) \
+do {\
+if (unlikely((CTX)->pr || !(CTX)->hv)) \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..77d449c3cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool
store, bool prefixed)
REQUIRE_INSNS_FLAGS(ctx, 64BX);
if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
-if (ctx->pr) {
-/* lq and stq were privileged prior to V. 2.07 */
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-return true;
-}
+/* lq and stq were privileged prior to V. 2.07 */
+REQUIRE_SV(ctx);
if (ctx->le_mode) {
gen_align_no_le(ctx);
--
2.25.1
[PATCH RESEND 04/11] target/ppc: Move slbieg to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index b51b3d9f07..8f9dde6d3f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -696,7 +696,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d282cf00c1..d3517d412c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -816,6 +816,7 @@ VMODUQ 000100 . . . 1101011@VX
## SLB Management Instructions
SLBIE 01 - - . 0110110010 - @X_rb
+SLBIEG 01 . - . 0111010010 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03f71a82ec..a842fbd6f6 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -202,7 +202,7 @@ void helper_SLBIE(CPUPPCState *env, target_ulong addr)
__helper_slbie(env, addr, false);
}
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, true);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 14881e637f..ad19a68f5c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6898,7 +6886,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 41fc5ade8b..b9bb950f7d 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -35,6 +35,20 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
return true;
}
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 03/11] target/ppc: Move slbie to decodetree
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 7 +++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5e663a0a50..b51b3d9f07 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,7 +695,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2b985249b8..d282cf00c1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_rb rb
+@X_rb .. . . rb:5 .. ._rb
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -810,6 +813,10 @@ VMODUD 000100 . . . 11011001011@VX
VMODSQ 000100 . . . 1111011@VX
VMODUQ 000100 . . . 1101011@VX
+## SLB Management Instructions
+
+SLBIE 01 - - . 0110110010 - @X_rb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..03f71a82ec 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -197,7 +197,7 @@ static void __helper_slbie(CPUPPCState *env, target_ulong
addr,
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, false);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 275cffb2a7..14881e637f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbieg */
static void gen_slbieg(DisasContext *ctx)
{
@@ -6910,7 +6898,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index f9e4a807f2..41fc5ade8b 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -21,6 +21,20 @@
* Store Control Instructions
*/
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 00/11] target/ppc: Implement slbiag move slb* to decodetree
Resent after rebasing and fixing conflicts with master. Add Leandro Lupori as reviewer. Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br> Implement the following PowerISA v3.0 instuction: slbiag: SLB Invalidate All Global X-form Move the following PowerISA v3.0 instuction to decodetree: slbie: SLB Invalidate Entry X-form slbieg: SLB Invalidate Entry Global X-form slbia: SLB Invalidate All X-form slbmte: SLB Move To Entry X-form slbmfev: SLB Move From Entry VSID X-form slbmfee: SLB Move From Entry ESID X-form slbfee: SLB Find Entry ESID slbsync: SLB Synchronize Lucas Coutinho (9): target/ppc: Move slbie to decodetree target/ppc: Move slbieg to decodetree target/ppc: Move slbia to decodetree target/ppc: Move slbmte to decodetree target/ppc: Move slbmfev to decodetree target/ppc: Move slbmfee to decodetree target/ppc: Move slbfee to decodetree target/ppc: Move slbsync to decodetree target/ppc: Implement slbiag Matheus Ferst (2): target/ppc: receive DisasContext explicitly in GEN_PRIV target/ppc: add macros to check privilege level target/ppc/helper.h | 15 +- target/ppc/insn32.decode | 26 ++ target/ppc/mmu-hash64.c | 41 +- target/ppc/translate.c | 417 +++ target/ppc/translate/fixedpoint-impl.c.inc | 7 +- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/storage-ctrl-impl.c.inc | 146 +++ 7 files changed, 377 insertions(+), 279 deletions(-) -- 2.25.1
[PATCH RESEND 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV
From: Matheus Ferst
GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.
Reviewed-by: Leandro Lupori
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 299 +++--
target/ppc/translate/fp-impl.c.inc | 4 +-
2 files changed, 154 insertions(+), 149 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4fcb311c2d..920bb543cf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
const char *oname;
} opcode_t;
+static void gen_priv_opc(DisasContext *ctx)
+{
+gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
/* Helpers for priv. check */
-#define GEN_PRIV\
-do {\
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX) \
+do { \
+gen_priv_opc(CTX); return; \
} while (0)
#if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
#else
-#define CHK_HV \
-do {\
-if (unlikely(ctx->pr || !ctx->hv)) {\
-GEN_PRIV; \
-} \
+#define CHK_HV(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv)) {\
+GEN_PRIV(CTX); \
+} \
} while (0)
-#define CHK_SV \
+#define CHK_SV(CTX) \
do { \
if (unlikely(ctx->pr)) { \
-GEN_PRIV;\
+GEN_PRIV(CTX); \
}\
} while (0)
-#define CHK_HVRM\
-do {\
-if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
-GEN_PRIV; \
-} \
+#define CHK_HVRM(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+GEN_PRIV(CTX); \
+} \
} while (0)
#endif
-#define CHK_NONE
+#define CHK_NONE(CTX)
/*/
/* PowerPC instructions table*/
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA; \
-chk; \
+chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
-CHK_SV; \
+CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA;
[PATCH RESEND 11/11] target/ppc: Implement slbiag
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 649b2a9c58..2e7c61e117 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,6 +695,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fb53bce0c8..e4aa336bbf 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
_rb rb
@X_rb .. . . rb:5 .. ._rb
+_rs_l rs l:bool
+@X_rs_l .. rs:5 l:1 . .. . _rs_l
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -822,6 +825,7 @@ SLBIE 01 - - . 0110110010 -
@X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBIAG 01 . . - 1101010010 - @X_rs_l
SLBMTE 01 . - . 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = >slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
[PATCH RESEND 05/11] target/ppc: Move slbia to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 5 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8f9dde6d3f..c2440a8854 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -694,7 +694,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env,
tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d3517d412c..1349c5e8a7 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_ih ih:uint8_t
+@X_ih .. .. ih:3 . . .. . _ih
+
_rb rb
@X_rb .. . . rb:5 .. ._rb
@@ -818,6 +821,8 @@ VMODUQ 000100 . . . 1101011@VX
SLBIE 01 - - . 0110110010 - @X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
+SLBIA 01 --... - - 010010 - @X_ih
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a842fbd6f6..dd2c7e588f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
}
#ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
{
PowerPCCPU *cpu = env_archcpu(env);
int starting_entry;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ad19a68f5c..5d2416143f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5450,22 +5450,6 @@ static void gen_tlbsync(DisasContext *ctx)
}
#if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-uint32_t ih = (ctx->opcode >> 21) & 0x7;
-TCGv_i32 t0 = tcg_const_i32(ih);
-
-CHK_SV(ctx);
-
-gen_helper_slbia(cpu_env, t0);
-tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6885,7 +6869,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b9bb950f7d..cbb8b81f13 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -49,6 +49,20 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
return true;
}
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 09/11] target/ppc: Move slbfee to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 26 ---
target/ppc/translate/storage-ctrl-impl.c.inc | 34
5 files changed, 38 insertions(+), 28 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 848665a4f4..649b2a9c58 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -693,7 +693,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0797a19896..a28d31e123 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -828,6 +828,8 @@ SLBMTE 01 . - . 0110010010 -
@X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
SLBMFEE 01 . - . 1110010011 - @X_tb
+SLBFEE 01 . - . 010011 1 @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 5d73d64436..7ec7a67a78 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -331,7 +331,7 @@ target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong
rb)
return rt;
}
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eadf4ca1b7..150318d70e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,31 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
-TCGLabel *l1, *l2;
-
-if (unlikely(ctx->pr)) {
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-return;
-}
-gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-l1 = gen_new_label();
-l2 = gen_new_label();
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
-gen_set_label(l2);
-#endif
-}
#endif /* defined(TARGET_PPC64) */
/*** Lookaside buffer management ***/
@@ -6821,7 +6796,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
/*
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b169bd6317..260bce35ac 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -105,6 +105,40 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE
*a)
return true;
}
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+TCGLabel *l1, *l2;
+
+if (unlikely(ctx->pr)) {
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+return true;
+}
+gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+l1 = gen_new_label();
+l2 = gen_new_label();
+tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+tcg_gen_br(l2);
+gen_set_label(l1);
+tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+gen_set_label(l2);
+#else
+qemu_build_not_reached();
+#endif
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 00/11] target/ppc: Implement slbiag move slb* to decodetree
Resent after rebasing and fixing conflicts with master. Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br> Implement the following PowerISA v3.0 instuction: slbiag: SLB Invalidate All Global X-form Move the following PowerISA v3.0 instuction to decodetree: slbie: SLB Invalidate Entry X-form slbieg: SLB Invalidate Entry Global X-form slbia: SLB Invalidate All X-form slbmte: SLB Move To Entry X-form slbmfev: SLB Move From Entry VSID X-form slbmfee: SLB Move From Entry ESID X-form slbfee: SLB Find Entry ESID slbsync: SLB Synchronize Lucas Coutinho (9): target/ppc: Move slbie to decodetree target/ppc: Move slbieg to decodetree target/ppc: Move slbia to decodetree target/ppc: Move slbmte to decodetree target/ppc: Move slbmfev to decodetree target/ppc: Move slbmfee to decodetree target/ppc: Move slbfee to decodetree target/ppc: Move slbsync to decodetree target/ppc: Implement slbiag Matheus Ferst (2): target/ppc: receive DisasContext explicitly in GEN_PRIV target/ppc: add macros to check privilege level target/ppc/helper.h | 15 +- target/ppc/insn32.decode | 26 ++ target/ppc/mmu-hash64.c | 41 +- target/ppc/translate.c | 417 +++ target/ppc/translate/fixedpoint-impl.c.inc | 7 +- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/storage-ctrl-impl.c.inc | 146 +++ 7 files changed, 377 insertions(+), 279 deletions(-) -- 2.25.1
[PATCH RESEND 10/11] target/ppc: Move slbsync to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a28d31e123..fb53bce0c8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -830,6 +830,8 @@ SLBMFEE 01 . - . 1110010011 -
@X_tb
SLBFEE 01 . - . 010011 1 @X_tb
+SLBSYNC 01 - - - 0101010010 -
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 150318d70e..a918575fa9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5388,20 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-#if defined(TARGET_PPC64)
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif /* defined(TARGET_PPC64) */
-
/*** External control ***/
/* Optional: */
@@ -6803,9 +6789,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
* different ISA versions
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x0001, PPC_EXTERN),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 260bce35ac..c90cad10b4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -139,6 +139,20 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
return true;
}
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_check_tlb_flush(ctx, true);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 03/11] target/ppc: Move slbie to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 7 +++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5e663a0a50..b51b3d9f07 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,7 +695,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2b985249b8..d282cf00c1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_rb rb
+@X_rb .. . . rb:5 .. ._rb
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -810,6 +813,10 @@ VMODUD 000100 . . . 11011001011@VX
VMODSQ 000100 . . . 1111011@VX
VMODUQ 000100 . . . 1101011@VX
+## SLB Management Instructions
+
+SLBIE 01 - - . 0110110010 - @X_rb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..03f71a82ec 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -197,7 +197,7 @@ static void __helper_slbie(CPUPPCState *env, target_ulong
addr,
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, false);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 275cffb2a7..14881e637f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbieg */
static void gen_slbieg(DisasContext *ctx)
{
@@ -6910,7 +6898,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index f9e4a807f2..41fc5ade8b 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -21,6 +21,20 @@
* Store Control Instructions
*/
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 06/11] target/ppc: Move slbmte to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c2440a8854..ad88073ae0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -690,7 +690,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
-DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1349c5e8a7..e255f9241b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -823,6 +823,8 @@ SLBIEG 01 . - . 0111010010 -
@X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBMTE 01 . - . 0110010010 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index dd2c7e588f..1922960608 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -309,7 +309,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong
rb,
return 0;
}
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = env_archcpu(env);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5d2416143f..d421fe267c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,19 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbmte */
-static void gen_slbmte(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbmfee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -6857,7 +6844,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index cbb8b81f13..4c2dd758b5 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 07/11] target/ppc: Move slbmfev to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 12
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ad88073ae0..1d23de7358 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -692,7 +692,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e255f9241b..9354014ca5 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -825,6 +825,8 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
+SLBMFEV 01 . - . 1101010011 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1922960608..7854b91043 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -343,7 +343,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env,
target_ulong rb)
return rt;
}
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d421fe267c..6b44c6312b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5363,17 +5363,6 @@ static void gen_slbmfee(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6845,7 +6834,6 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06,
0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 4c2dd758b5..a037fc2b95 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -77,6 +77,20 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
return true;
}
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 08/11] target/ppc: Move slbmfee to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 1d23de7358..848665a4f4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -691,7 +691,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
-DEF_HELPER_2(load_slb_esid, tl, env, tl)
+DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9354014ca5..0797a19896 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -826,6 +826,7 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
+SLBMFEE 01 . - . 1110010011 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7854b91043..5d73d64436 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -319,7 +319,7 @@ void helper_SLBMTE(CPUPPCState *env, target_ulong rb,
target_ulong rs)
}
}
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6b44c6312b..eadf4ca1b7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,18 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfee(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6833,7 +6821,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index a037fc2b95..b169bd6317 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -91,6 +91,20 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
return true;
}
+static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 02/11] target/ppc: add macros to check privilege level
From: Matheus Ferst
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 21 +
target/ppc/translate/fixedpoint-impl.c.inc | 7 ++-
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 920bb543cf..275cffb2a7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,6 +6575,27 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+do {\
+if (unlikely((CTX)->pr)) { \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+
+#define REQUIRE_HV(CTX) \
+do {\
+if (unlikely((CTX)->pr || !(CTX)->hv)) \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..77d449c3cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool
store, bool prefixed)
REQUIRE_INSNS_FLAGS(ctx, 64BX);
if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
-if (ctx->pr) {
-/* lq and stq were privileged prior to V. 2.07 */
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-return true;
-}
+/* lq and stq were privileged prior to V. 2.07 */
+REQUIRE_SV(ctx);
if (ctx->le_mode) {
gen_align_no_le(ctx);
--
2.25.1
[PATCH RESEND 04/11] target/ppc: Move slbieg to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index b51b3d9f07..8f9dde6d3f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -696,7 +696,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d282cf00c1..d3517d412c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -816,6 +816,7 @@ VMODUQ 000100 . . . 1101011@VX
## SLB Management Instructions
SLBIE 01 - - . 0110110010 - @X_rb
+SLBIEG 01 . - . 0111010010 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03f71a82ec..a842fbd6f6 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -202,7 +202,7 @@ void helper_SLBIE(CPUPPCState *env, target_ulong addr)
__helper_slbie(env, addr, false);
}
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, true);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 14881e637f..ad19a68f5c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6898,7 +6886,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 41fc5ade8b..b9bb950f7d 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -35,6 +35,20 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
return true;
}
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH RESEND 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV
From: Matheus Ferst
GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 299 +++--
target/ppc/translate/fp-impl.c.inc | 4 +-
2 files changed, 154 insertions(+), 149 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4fcb311c2d..920bb543cf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
const char *oname;
} opcode_t;
+static void gen_priv_opc(DisasContext *ctx)
+{
+gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
/* Helpers for priv. check */
-#define GEN_PRIV\
-do {\
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX) \
+do { \
+gen_priv_opc(CTX); return; \
} while (0)
#if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
#else
-#define CHK_HV \
-do {\
-if (unlikely(ctx->pr || !ctx->hv)) {\
-GEN_PRIV; \
-} \
+#define CHK_HV(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv)) {\
+GEN_PRIV(CTX); \
+} \
} while (0)
-#define CHK_SV \
+#define CHK_SV(CTX) \
do { \
if (unlikely(ctx->pr)) { \
-GEN_PRIV;\
+GEN_PRIV(CTX); \
}\
} while (0)
-#define CHK_HVRM\
-do {\
-if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
-GEN_PRIV; \
-} \
+#define CHK_HVRM(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+GEN_PRIV(CTX); \
+} \
} while (0)
#endif
-#define CHK_NONE
+#define CHK_NONE(CTX)
/*/
/* PowerPC instructions table*/
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA; \
-chk; \
+chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
-CHK_SV; \
+CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA;
[PATCH 10/11] target/ppc: Move slbsync to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 34f0e3cbeb..f7ebca578b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -807,6 +807,8 @@ SLBMFEE 01 . - . 1110010011 -
@X_tb
SLBFEE 01 . - . 010011 1 @X_tb
+SLBSYNC 01 - - - 0101010010 -
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 62f3c19e6a..b005c15f98 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5388,20 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-#if defined(TARGET_PPC64)
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif /* defined(TARGET_PPC64) */
-
/*** External control ***/
/* Optional: */
@@ -6803,9 +6789,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
* different ISA versions
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x0001, PPC_EXTERN),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 260bce35ac..c90cad10b4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -139,6 +139,20 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
return true;
}
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_check_tlb_flush(ctx, true);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 08/11] target/ppc: Move slbmfee to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index dee6dfe6f4..271dd585e0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -683,7 +683,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
-DEF_HELPER_2(load_slb_esid, tl, env, tl)
+DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c0239335a1..22614ee915 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -803,6 +803,7 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
+SLBMFEE 01 . - . 1110010011 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7854b91043..5d73d64436 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -319,7 +319,7 @@ void helper_SLBMTE(CPUPPCState *env, target_ulong rb,
target_ulong rs)
}
}
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f0fc375b0c..dc87316ce7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,18 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfee(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6833,7 +6821,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index a037fc2b95..b169bd6317 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -91,6 +91,20 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
return true;
}
+static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 05/11] target/ppc: Move slbia to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 5 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 86cd12f399..4fbabda2f6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -686,7 +686,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env,
tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b900fd8f17..c378b34b58 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_ih ih:uint8_t
+@X_ih .. .. ih:3 . . .. . _ih
+
_rb rb
@X_rb .. . . rb:5 .. ._rb
@@ -795,6 +798,8 @@ XVF64GERNN 111011 ... -- 0 . 1010 ..-
@XX3_at xa=%xx_xa_pair
SLBIE 01 - - . 0110110010 - @X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
+SLBIA 01 --... - - 010010 - @X_ih
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a842fbd6f6..dd2c7e588f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
}
#ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
{
PowerPCCPU *cpu = env_archcpu(env);
int starting_entry;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6e47b81bf7..cf83890f82 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5450,22 +5450,6 @@ static void gen_tlbsync(DisasContext *ctx)
}
#if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-uint32_t ih = (ctx->opcode >> 21) & 0x7;
-TCGv_i32 t0 = tcg_const_i32(ih);
-
-CHK_SV(ctx);
-
-gen_helper_slbia(cpu_env, t0);
-tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6885,7 +6869,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b9bb950f7d..cbb8b81f13 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -49,6 +49,20 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
return true;
}
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 04/11] target/ppc: Move slbieg to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 793f307ab0..86cd12f399 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -688,7 +688,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index af13625832..b900fd8f17 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -793,6 +793,7 @@ XVF64GERNN 111011 ... -- 0 . 1010 ..-
@XX3_at xa=%xx_xa_pair
## SLB Management Instructions
SLBIE 01 - - . 0110110010 - @X_rb
+SLBIEG 01 . - . 0111010010 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03f71a82ec..a842fbd6f6 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -202,7 +202,7 @@ void helper_SLBIE(CPUPPCState *env, target_ulong addr)
__helper_slbie(env, addr, false);
}
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, true);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b0bb67b676..6e47b81bf7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6898,7 +6886,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 41fc5ade8b..b9bb950f7d 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -35,6 +35,20 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
return true;
}
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 03/11] target/ppc: Move slbie to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 7 +++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0b2bc8020b..793f307ab0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -687,7 +687,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 44ac5f0785..af13625832 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
_imm8 xt imm:uint8_t
@X_imm8 .. . .. imm:8 .. . _imm8
xt=%x_xt
+_rb rb
+@X_rb .. . . rb:5 .. ._rb
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -787,6 +790,10 @@ XVF64GERPN 111011 ... -- 0 . 10111010 ..-
@XX3_at xa=%xx_xa_pair
XVF64GERNP 111011 ... -- 0 . 0010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERNN 111011 ... -- 0 . 1010 ..- @XX3_at xa=%xx_xa_pair
+## SLB Management Instructions
+
+SLBIE 01 - - . 0110110010 - @X_rb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..03f71a82ec 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -197,7 +197,7 @@ static void __helper_slbie(CPUPPCState *env, target_ulong
addr,
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, false);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 508ef6660d..b0bb67b676 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbieg */
static void gen_slbieg(DisasContext *ctx)
{
@@ -6910,7 +6898,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01,
PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index f9e4a807f2..41fc5ade8b 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -21,6 +21,20 @@
* Store Control Instructions
*/
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree
Implement the following PowerISA v3.0 instuction: slbiag: SLB Invalidate All Global X-form Move the following PowerISA v3.0 instuction to decodetree: slbie: SLB Invalidate Entry X-form slbieg: SLB Invalidate Entry Global X-form slbia: SLB Invalidate All X-form slbmte: SLB Move To Entry X-form slbmfev: SLB Move From Entry VSID X-form slbmfee: SLB Move From Entry ESID X-form slbfee: SLB Find Entry ESID slbsync: SLB Synchronize Based-on: <20220614163018.39819-1-leandro.lup...@eldorado.org.br> Lucas Coutinho (9): target/ppc: Move slbie to decodetree target/ppc: Move slbieg to decodetree target/ppc: Move slbia to decodetree target/ppc: Move slbmte to decodetree target/ppc: Move slbmfev to decodetree target/ppc: Move slbmfee to decodetree target/ppc: Move slbfee to decodetree target/ppc: Move slbsync to decodetree target/ppc: Implement slbiag Matheus Ferst (2): target/ppc: receive DisasContext explicitly in GEN_PRIV target/ppc: add macros to check privilege level target/ppc/helper.h | 15 +- target/ppc/insn32.decode | 26 ++ target/ppc/mmu-hash64.c | 41 +- target/ppc/translate.c | 417 +++ target/ppc/translate/fixedpoint-impl.c.inc | 7 +- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/storage-ctrl-impl.c.inc | 146 +++ 7 files changed, 377 insertions(+), 279 deletions(-) -- 2.25.1
[PATCH 07/11] target/ppc: Move slbmfev to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 12
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index acfb360e59..dee6dfe6f4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -684,7 +684,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 00d033559f..c0239335a1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -802,6 +802,8 @@ SLBIA 01 --... - - 010010 -
@X_ih
SLBMTE 01 . - . 0110010010 - @X_tb
+SLBMFEV 01 . - . 1101010011 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1922960608..7854b91043 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -343,7 +343,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env,
target_ulong rb)
return rt;
}
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index efd00c7f77..f0fc375b0c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5363,17 +5363,6 @@ static void gen_slbmfee(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6845,7 +6834,6 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06,
0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 4c2dd758b5..a037fc2b95 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -77,6 +77,20 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
return true;
}
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 02/11] target/ppc: add macros to check privilege level
From: Matheus Ferst
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 21 +
target/ppc/translate/fixedpoint-impl.c.inc | 7 ++-
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 920bb543cf..508ef6660d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,6 +6575,27 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+do {\
+if (unlikely((CTX)->pr)) { \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+
+#define REQUIRE_HV(CTX) \
+do {\
+if (unlikely((CTX)->pr || !(CTX)->hv)) \
+gen_priv_opc(CTX); \
+return true;\
+} \
+} while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..77d449c3cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool
store, bool prefixed)
REQUIRE_INSNS_FLAGS(ctx, 64BX);
if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
-if (ctx->pr) {
-/* lq and stq were privileged prior to V. 2.07 */
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-return true;
-}
+/* lq and stq were privileged prior to V. 2.07 */
+REQUIRE_SV(ctx);
if (ctx->le_mode) {
gen_align_no_le(ctx);
--
2.25.1
[PATCH 11/11] target/ppc: Implement slbiag
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index de7bf9f175..4287f41880 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -687,6 +687,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f7ebca578b..b36a093828 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
_rb rb
@X_rb .. . . rb:5 .. ._rb
+_rs_l rs l:bool
+@X_rs_l .. rs:5 l:1 . .. . _rs_l
+
_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . _uim5
xt=%x_xt
@@ -799,6 +802,7 @@ SLBIE 01 - - . 0110110010 -
@X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBIAG 01 . . - 1101010010 - @X_rs_l
SLBMTE 01 . - . 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = >slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
[PATCH 06/11] target/ppc: Move slbmte to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4fbabda2f6..acfb360e59 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -682,7 +682,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
-DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c378b34b58..00d033559f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -800,6 +800,8 @@ SLBIEG 01 . - . 0111010010 -
@X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBMTE 01 . - . 0110010010 - @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index dd2c7e588f..1922960608 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -309,7 +309,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong
rb,
return 0;
}
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = env_archcpu(env);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cf83890f82..efd00c7f77 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,19 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbmte */
-static void gen_slbmte(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbmfee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -6857,7 +6844,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index cbb8b81f13..4c2dd758b5 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV
From: Matheus Ferst
GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 299 +++--
target/ppc/translate/fp-impl.c.inc | 4 +-
2 files changed, 154 insertions(+), 149 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4fcb311c2d..920bb543cf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
const char *oname;
} opcode_t;
+static void gen_priv_opc(DisasContext *ctx)
+{
+gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
/* Helpers for priv. check */
-#define GEN_PRIV\
-do {\
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX) \
+do { \
+gen_priv_opc(CTX); return; \
} while (0)
#if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
#else
-#define CHK_HV \
-do {\
-if (unlikely(ctx->pr || !ctx->hv)) {\
-GEN_PRIV; \
-} \
+#define CHK_HV(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv)) {\
+GEN_PRIV(CTX); \
+} \
} while (0)
-#define CHK_SV \
+#define CHK_SV(CTX) \
do { \
if (unlikely(ctx->pr)) { \
-GEN_PRIV;\
+GEN_PRIV(CTX); \
}\
} while (0)
-#define CHK_HVRM\
-do {\
-if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
-GEN_PRIV; \
-} \
+#define CHK_HVRM(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+GEN_PRIV(CTX); \
+} \
} while (0)
#endif
-#define CHK_NONE
+#define CHK_NONE(CTX)
/*/
/* PowerPC instructions table*/
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA; \
-chk; \
+chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
-CHK_SV; \
+CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
static void glue(gen_, name##x)(DisasContext *ctx)\
{ \
TCGv EA;
[PATCH 09/11] target/ppc: Move slbfee to decodetree
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 26 ---
target/ppc/translate/storage-ctrl-impl.c.inc | 34
5 files changed, 38 insertions(+), 28 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 271dd585e0..de7bf9f175 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -685,7 +685,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 22614ee915..34f0e3cbeb 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -805,6 +805,8 @@ SLBMTE 01 . - . 0110010010 -
@X_tb
SLBMFEV 01 . - . 1101010011 - @X_tb
SLBMFEE 01 . - . 1110010011 - @X_tb
+SLBFEE 01 . - . 010011 1 @X_tb
+
## TLB Management Instructions
_tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 5d73d64436..7ec7a67a78 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -331,7 +331,7 @@ target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong
rb)
return rt;
}
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index dc87316ce7..62f3c19e6a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,31 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
-TCGLabel *l1, *l2;
-
-if (unlikely(ctx->pr)) {
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-return;
-}
-gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-l1 = gen_new_label();
-l2 = gen_new_label();
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
-gen_set_label(l2);
-#endif
-}
#endif /* defined(TARGET_PPC64) */
/*** Lookaside buffer management ***/
@@ -6821,7 +6796,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14,
0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F,
PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
/*
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b169bd6317..260bce35ac 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -105,6 +105,40 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE
*a)
return true;
}
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+TCGLabel *l1, *l2;
+
+if (unlikely(ctx->pr)) {
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+return true;
+}
+gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+l1 = gen_new_label();
+l2 = gen_new_label();
+tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+tcg_gen_br(l2);
+gen_set_label(l1);
+tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+gen_set_label(l2);
+#else
+qemu_build_not_reached();
+#endif
+#endif
+return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
[PATCH] target/ppc: Replicate Double->Single-Precision result
Power ISA v3.1 formalizes the previously undefined result in
words 1 and 3 to be a copy of the result in words 0 and 2.
This affects: xvcvsxdsp, xvcvuxdsp, xvcvdpsp.
And the previously undefined result in word 1 to be a copy of
the result in word 0.
This affects: xscvdpsp.
Signed-off-by: Lucas Coutinho
---
This patch is a follow-up of:
https://lists.gnu.org/archive/html/qemu-ppc/2022-03/msg00354.html
which have the same behavior of the instructions altered
---
target/ppc/fpu_helper.c | 48 +
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index e76d2ae83a..e9cf5f7a78 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2691,11 +2691,35 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb) \
do_float_check_status(env, GETPC()); \
}
-VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
-VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
+#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfprf) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ppc_vsr_t t = { };\
+int i;\
+ \
+for (i = 0; i < nels; i++) { \
+t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), >fp_status); \
+if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
+>fp_status))) { \
+float_invalid_op_vxsnan(env, GETPC());\
+t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i));\
+} \
+if (sfprf) { \
+helper_compute_fprf_##ttp(env, t.VsrW(2 * i));\
+} \
+t.VsrW(2 * i + 1) = t.VsrW(2 * i);\
+} \
+ \
+*xt = t; \
+do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
+VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
+
/*
* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
* op- instruction mnemonic
@@ -3011,11 +3035,27 @@ VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64,
VsrD(i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
+#define VSX_CVT_INT_TO_FP2(op, stp, ttp)\
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\
+{ \
+ppc_vsr_t t = { }; \
+int i; \
+\
+for (i = 0; i < 2; i++) { \
+t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), >fp_status); \
+t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+} \
+\
+*xt = t;\
+do_float_check_status(env, GETPC());\
+}
+
+VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
+VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
+
/*
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
* op- instruction mnemonic
--
2.25.1
