Re: A question regarding TARGET_ALIGNED_ONLY flag

[Michael Rolnik]

Thank you Richard.

On Sun, May 19, 2024 at 6:26 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 5/19/24 16:23, Michael Rolnik wrote:
> > Hi all,
> >
> > Previously there was *TARGET_ALIGNED_ONLY* option that caused all memory
> accessed to be
> > aligned, now it seems to be removed.
> > Is there a way to achieve memory access alignment with QEMU v9.0.0 when
> I am building a
> > custom target?
>
> Explicitly add MO_ALIGN to the MemOp argument of
> tcg_gen_qemu_{ld,st}_{i32,i64,i128}.
>
>
> r~
>
>

-- 
Best Regards,
Michael Rolnik

A question regarding TARGET_ALIGNED_ONLY flag

[Michael Rolnik]

Hi all,

Previously there was *TARGET_ALIGNED_ONLY* option that caused all memory
accessed to be aligned, now it seems to be removed.
Is there a way to achieve memory access alignment with QEMU v9.0.0 when I
am building a custom target?


-- 
Best Regards,
Michael Rolnik

Re: [PATCH 1/9] target/avr: Use tcg_gen_extract_tl

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Tue, Oct 24, 2023 at 2:32 AM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 10/23/23 09:09, Philippe Mathieu-Daudé wrote:
> > Inspired-by: Richard Henderson 
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> >   target/avr/translate.c | 18 ++
> >   1 file changed, 6 insertions(+), 12 deletions(-)
>
> Reviewed-by: Richard Henderson 
>
> r~
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH] Fix handling of AVR interrupts above 33.

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Wed, Jun 14, 2023 at 3:22 PM Philippe Mathieu-Daudé 
wrote:

> On 14/6/23 16:07, Lucas Dietrich wrote:
> > This commit addresses a bug in the AVR interrupt handling code.
> > The modification involves replacing the usage of the ctz32 function
> > with ctz64 to ensure proper handling of interrupts above 33 in the AVR
> > target.
> >
> > Previously, timers 3, 4, and 5 interrupts were not functioning correctly
> > because most of their interrupt vectors are numbered above 33.
> >
> > Signed-off-by: Lucas Dietrich 
> > ---
> >   target/avr/helper.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
>
> Thanks for insisting with the patch posting process :)
>
> Reviewed-by: Philippe Mathieu-Daudé 
>
>

-- 
Best Regards,
Michael Rolnik

Re: QEMU AVR Patch - Correct handling of AVR interrupts

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Jun 9, 2023 at 12:04 AM Adecy  wrote:

>
>
> -- Forwarded message -
> De : Adecy 
> Date: jeu. 1 juin 2023 à 21:34
> Subject: QEMU AVR Patch - Correct handling of AVR interrupts
> To: 
>
>
> Hello,
>
> I would like to submit the attached patch.
>
> Best regards
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH qemu] hw: add ATmega16u4 and ATmega32u4 MCUs

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Sun, May 14, 2023 at 12:54 AM ~rmsyn  wrote:

> From: rmsyn 
>
> Adds support for ATmega16u4 and ATmega32u4 MCU definitions.
>
> Defines interrupts, memory layout, and machine types for generic
> ATmega16u4 and ATmega32u4 MCUs.
>
> Signed-off-by: rmsyn 
> ---
>  hw/avr/arduino.c |  36 ++
>  hw/avr/atmega.c  | 122 +++
>  hw/avr/atmega.h  |   2 +
>  3 files changed, 160 insertions(+)
>
> diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c
> index 48ef478346..be04e412e6 100644
> --- a/hw/avr/arduino.c
> +++ b/hw/avr/arduino.c
> @@ -129,6 +129,34 @@ static void arduino_mega2560_class_init(ObjectClass
> *oc, void *data)
>  amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
>  };
>
> +static void arduino_mega16u4_class_init(ObjectClass *oc, void *data)
> +{
> +MachineClass *mc = MACHINE_CLASS(oc);
> +ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
> +
> +/*
> + *
> https://ww1.microchip.com/downloads/en/devicedoc/atmel-7766-8-bit-avr-atmega16u4-32u4_datasheet.pdf
> + */
> +mc->desc= "Arduino Mega 16u4 (ATmega16u4)";
> +mc->alias   = "mega16u4";
> +amc->mcu_type   = TYPE_ATMEGA16U4_MCU;
> +amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
> +};
> +
> +static void arduino_mega32u4_class_init(ObjectClass *oc, void *data)
> +{
> +MachineClass *mc = MACHINE_CLASS(oc);
> +ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
> +
> +/*
> + *
> https://ww1.microchip.com/downloads/en/devicedoc/atmel-7766-8-bit-avr-atmega16u4-32u4_datasheet.pdf
> + */
> +mc->desc= "Arduino Mega 32u4 (ATmega32u4)";
> +mc->alias   = "mega32u4";
> +amc->mcu_type   = TYPE_ATMEGA32U4_MCU;
> +amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
> +};
> +
>  static const TypeInfo arduino_machine_types[] = {
>  {
>  .name  = MACHINE_TYPE_NAME("arduino-duemilanove"),
> @@ -146,6 +174,14 @@ static const TypeInfo arduino_machine_types[] = {
>  .name  = MACHINE_TYPE_NAME("arduino-mega-2560-v3"),
>  .parent= TYPE_ARDUINO_MACHINE,
>  .class_init= arduino_mega2560_class_init,
> +}, {
> +.name  = MACHINE_TYPE_NAME("arduino-mega-16u4"),
> +.parent= TYPE_ARDUINO_MACHINE,
> +.class_init= arduino_mega16u4_class_init,
> +}, {
> +.name  = MACHINE_TYPE_NAME("arduino-mega-32u4"),
> +.parent= TYPE_ARDUINO_MACHINE,
> +.class_init= arduino_mega32u4_class_init,
>  }, {
>  .name   = TYPE_ARDUINO_MACHINE,
>  .parent = TYPE_MACHINE,
> diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> index a34803e642..292ad9a447 100644
> --- a/hw/avr/atmega.c
> +++ b/hw/avr/atmega.c
> @@ -27,6 +27,17 @@ enum AtmegaPeripheral {
>  GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
>  USART0, USART1, USART2, USART3,
>  TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
> +RESET,
> +INT0, INT1, INT2, INT3, INT4, INT5, INT6,
> +PCINT0,
> +USB_GEN, USB_EP,
> +WDT,
> +SPI,
> +ANALOG_COMP,
> +ADC,
> +EE_READY,
> +TWI,
> +SPM_READY,
>  PERIFMAX
>  };
>
> @@ -98,6 +109,30 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
>  [GPIOC] = {  0x26 },
>  [GPIOB] = {  0x23 },
>  [GPIOA] = {  0x20 },
> +}, dev16u4_32u4[PERIFMAX] = {
> +[POWER1]= {  0x65 },
> +[POWER0]= {  0x64 },
> +[TIMER4]= {  0x4c, POWER1, 4, 0x72, 0x39, true },
> +[SPM_READY] = {  0x4a },
> +[TWI]   = {  0x48 },
> +[TIMER3]= {  0x3e, POWER1, 3, 0x71, 0x38, true },
> +[EE_READY]  = {  0x3c },
> +[ADC]   = {  0x3a },
> +[ANALOG_COMP]   = {  0x38 },
> +[USART1]= {  0x32, POWER1, 0 },
> +[SPI]   = {  0x30 },
> +[TIMER0]= {  0x2a, POWER0, 5, 0x6e, 0x35, true },
> +[TIMER1]= {  0x20, POWER0, 3, 0x6f, 0x36, true },
> +[WDT]   = {  0x18 },
> +[USB_GEN]   = {  0x14 },
> +[USB_EP]= {  0x16 },
> +[PCINT0]= {  0x12 },
> +[INT6]  = {  0x0e },
> +[INT3]  = {  0x08 },
> +[INT2]  = {  0x06 },
> +[INT1]  = {  0x04 },
> +[INT0]  = {  0x02 },
> +[RESET] = {  0x00 },
>  };
>
>  enum AtmegaIrq {
> @@ -117,6 +152,17 @@ enum AtmegaIrq {
> 

Re: [PATCH 3/4] target/avr: fix avr features processing

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Sat, Nov 19, 2022 at 7:56 AM Pavel Dovgalyuk 
wrote:

> Bit vector for features has 64 bits. This patch fixes bit shifts in
> avr_feature and set_avr_feature functions to be 64-bit too.
>
> Signed-off-by: Pavel Dovgalyuk 
> ---
>  target/avr/cpu.h |4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> index cfdc0ecb70..8295e50fa0 100644
> --- a/target/avr/cpu.h
> +++ b/target/avr/cpu.h
> @@ -166,12 +166,12 @@ vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu,
> vaddr addr);
>
>  static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
>  {
> -return (env->features & (1U << feature)) != 0;
> +return (env->features & (1ULL << feature)) != 0;
>  }
>
>  static inline void set_avr_feature(CPUAVRState *env, int feature)
>  {
> -env->features |= (1U << feature);
> +    env->features |= (1ULL << feature);
>  }
>
>  #define cpu_list avr_cpu_list
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 1/8] hw/avr: Add limited support for avr gpio registers

[Michael Rolnik]

Hi all,

Is there any kind of web UI where I can review it?
I don't find this patch in https://patchew.org/  (there is only 2 year old
version (https://patchew.org/search?q=project%3AQEMU+%22hw%2Favr%22))

Thank you,
Michael Rolnik

On Mon, Sep 12, 2022 at 2:21 PM Heecheol Yang 
wrote:

> Add some of these features for AVR GPIO:
>
>   - GPIO I/O : PORTx registers
>   - Data Direction : DDRx registers
>   - DDRx toggling : PINx registers
>
> Following things are not supported yet:
>   - MCUR registers
>
> Signed-off-by: Heecheol Yang 
> Reviewed-by: Michael Rolnik 
> Message-Id: <
> dm6pr16mb247368dbd3447abecdd795d7e6...@dm6pr16mb2473.namprd16.prod.outlook.com
> >
> [PMD: Use AVR_GPIO_COUNT]
> Signed-off-by: Philippe Mathieu-Daudé 
> Message-Id: <20210313165445.2113938-4-f4...@amsat.org>
> ---
>  hw/avr/Kconfig |   1 +
>  hw/avr/atmega.c|   7 +-
>  hw/avr/atmega.h|   2 +
>  hw/gpio/Kconfig|   3 +
>  hw/gpio/avr_gpio.c | 138 +
>  hw/gpio/meson.build|   1 +
>  include/hw/gpio/avr_gpio.h |  53 ++
>  7 files changed, 203 insertions(+), 2 deletions(-)
>  create mode 100644 hw/gpio/avr_gpio.c
>  create mode 100644 include/hw/gpio/avr_gpio.h
>
> diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
> index d31298c3cc..16a57ced11 100644
> --- a/hw/avr/Kconfig
> +++ b/hw/avr/Kconfig
> @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
>  select AVR_TIMER16
>  select AVR_USART
>  select AVR_POWER
> +select AVR_GPIO
>
>  config ARDUINO
>  select AVR_ATMEGA_MCU
> diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> index a34803e642..f5fb3a5225 100644
> --- a/hw/avr/atmega.c
> +++ b/hw/avr/atmega.c
> @@ -282,8 +282,11 @@ static void atmega_realize(DeviceState *dev, Error
> **errp)
>  continue;
>  }
>  devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
> -create_unimplemented_device(devname,
> -OFFSET_DATA + mc->dev[idx].addr, 3);
> +object_initialize_child(OBJECT(dev), devname, >gpio[i],
> +TYPE_AVR_GPIO);
> +sysbus_realize(SYS_BUS_DEVICE(>gpio[i]), _abort);
> +sysbus_mmio_map(SYS_BUS_DEVICE(>gpio[i]), 0,
> +OFFSET_DATA + mc->dev[idx].addr);
>  g_free(devname);
>  }
>
> diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
> index a99ee15c7e..e2289d5744 100644
> --- a/hw/avr/atmega.h
> +++ b/hw/avr/atmega.h
> @@ -13,6 +13,7 @@
>
>  #include "hw/char/avr_usart.h"
>  #include "hw/timer/avr_timer16.h"
> +#include "hw/gpio/avr_gpio.h"
>  #include "hw/misc/avr_power.h"
>  #include "target/avr/cpu.h"
>  #include "qom/object.h"
> @@ -44,6 +45,7 @@ struct AtmegaMcuState {
>  DeviceState *io;
>  AVRMaskState pwr[POWER_MAX];
>  AVRUsartState usart[USART_MAX];
> +AVRGPIOState gpio[GPIO_MAX];
>  AVRTimer16State timer[TIMER_MAX];
>  uint64_t xtal_freq_hz;
>  };
> diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
> index f0e7405f6e..fde7019b2b 100644
> --- a/hw/gpio/Kconfig
> +++ b/hw/gpio/Kconfig
> @@ -13,3 +13,6 @@ config GPIO_PWR
>
>  config SIFIVE_GPIO
>  bool
> +
> +config AVR_GPIO
> +bool
> diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
> new file mode 100644
> index 00..cdb574ef0d
> --- /dev/null
> +++ b/hw/gpio/avr_gpio.c
> @@ -0,0 +1,138 @@
> +/*
> + * AVR processors GPIO registers emulation.
> + *
> + * Copyright (C) 2020 Heecheol Yang 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/sysbus.h"
> +#include "hw/irq.h"
> +#include "hw/gpio/avr_gpio.h"
> +#include "hw/qdev-properties.h"
&

Re: Question about pending patch for AVR_GPIO.

[Michael Rolnik]

Hi Heecheol Yang.

I suggest rebasing your patch to the master.

Regards,
Michael Rolnik

On Sun, Sep 11, 2022 at 7:47 PM Hee-cheol Yang 
wrote:

> Hello.
>
> First of all, I am very sorry for my late response for following
> patchworks for AVR gpio.:
>
>- https://patchew.org/QEMU/20210313165445.2113938-1-f4...@amsat.org/
>
>
>
> I couldn’t check works for several years because of my personal reasons.
>
>
>
> If I or anyone want to continue these works, can I ask what should I do
> now to continue works?
>
> Should I continue additional works from the original source commit or
> after merging our patches into recent master branch?
>
>
>
> I apologize my fault again.
>
> Thanks a lot.
>
>
>
> Best regards
>
> Heecheol Yang.
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH 0/3] target/avr: Fix skips vs interrupts

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> Fixes https://gitlab.com/qemu-project/qemu/-/issues/1118
>
> r~
>
> Richard Henderson (3):
>   target/avr: Call avr_cpu_do_interrupt directly
>   target/avr: Only execute one interrupt at a time
>   target/avr: Disable interrupts when env->skip set
>
>  target/avr/helper.c| 23 ++-
>  target/avr/translate.c | 26 ++
>  2 files changed, 36 insertions(+), 13 deletions(-)
>
> --
> 2.34.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 3/3] target/avr: Disable interrupts when env->skip set

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> This bit is not saved across interrupts, so we must
> delay delivering the interrupt until the skip has
> been processed.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1118
> Signed-off-by: Richard Henderson 
> ---
>  target/avr/helper.c|  9 +
>  target/avr/translate.c | 26 ++
>  2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index 34f1cbffb2..156dde4e92 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -31,6 +31,15 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  AVRCPU *cpu = AVR_CPU(cs);
>  CPUAVRState *env = >env;
>
> +/*
> + * We cannot separate a skip from the next instruction,
> + * as the skip would not be preserved across the interrupt.
> + * Separating the two insn normally only happens at page boundaries.
> + */
> +if (env->skip) {
> +return false;
> +}
> +
>  if (interrupt_request & CPU_INTERRUPT_RESET) {
>  if (cpu_interrupts_enabled(env)) {
>  cs->exception_index = EXCP_RESET;
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index dc9c3d6bcc..026753c963 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -2971,8 +2971,18 @@ static void avr_tr_translate_insn(DisasContextBase
> *dcbase, CPUState *cs)
>  if (skip_label) {
>  canonicalize_skip(ctx);
>  gen_set_label(skip_label);
> -if (ctx->base.is_jmp == DISAS_NORETURN) {
> +
> +switch (ctx->base.is_jmp) {
> +case DISAS_NORETURN:
>  ctx->base.is_jmp = DISAS_CHAIN;
> +break;
> +case DISAS_NEXT:
> +if (ctx->base.tb->flags & TB_FLAGS_SKIP) {
> +ctx->base.is_jmp = DISAS_TOO_MANY;
> +}
> +break;
> +default:
> +break;
>  }
>  }
>
> @@ -2989,6 +2999,11 @@ static void avr_tr_tb_stop(DisasContextBase
> *dcbase, CPUState *cs)
>  {
>  DisasContext *ctx = container_of(dcbase, DisasContext, base);
>  bool nonconst_skip = canonicalize_skip(ctx);
> +/*
> + * Because we disable interrupts while env->skip is set,
> + * we must return to the main loop to re-evaluate afterward.
> + */
> +bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP;
>
>  switch (ctx->base.is_jmp) {
>  case DISAS_NORETURN:
> @@ -2997,7 +3012,7 @@ static void avr_tr_tb_stop(DisasContextBase *dcbase,
> CPUState *cs)
>  case DISAS_NEXT:
>  case DISAS_TOO_MANY:
>  case DISAS_CHAIN:
> -if (!nonconst_skip) {
> +if (!nonconst_skip && !force_exit) {
>  /* Note gen_goto_tb checks singlestep.  */
>  gen_goto_tb(ctx, 1, ctx->npc);
>  break;
> @@ -3005,8 +3020,11 @@ static void avr_tr_tb_stop(DisasContextBase
> *dcbase, CPUState *cs)
>  tcg_gen_movi_tl(cpu_pc, ctx->npc);
>  /* fall through */
>  case DISAS_LOOKUP:
> -tcg_gen_lookup_and_goto_ptr();
> -break;
> +if (!force_exit) {
> +tcg_gen_lookup_and_goto_ptr();
> +break;
> +}
> +/* fall through */
>  case DISAS_EXIT:
>  tcg_gen_exit_tb(NULL, 0);
>  break;
> --
> 2.34.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 1/3] target/avr: Call avr_cpu_do_interrupt directly

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> There is no need to go through cc->tcg_ops when
> we know what value that must have.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/avr/helper.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index 82284f8997..9614ccf3e4 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -29,14 +29,13 @@
>  bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  {
>  bool ret = false;
> -CPUClass *cc = CPU_GET_CLASS(cs);
>  AVRCPU *cpu = AVR_CPU(cs);
>  CPUAVRState *env = >env;
>
>  if (interrupt_request & CPU_INTERRUPT_RESET) {
>  if (cpu_interrupts_enabled(env)) {
>  cs->exception_index = EXCP_RESET;
> -cc->tcg_ops->do_interrupt(cs);
> +avr_cpu_do_interrupt(cs);
>
>  cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
>
> @@ -47,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
>  int index = ctz32(env->intsrc);
>  cs->exception_index = EXCP_INT(index);
> -cc->tcg_ops->do_interrupt(cs);
> +avr_cpu_do_interrupt(cs);
>
>  env->intsrc &= env->intsrc - 1; /* clear the interrupt */
>  if (!env->intsrc) {
> --
> 2.34.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 2/3] target/avr: Only execute one interrupt at a time

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> We cannot deliver two interrupts simultaneously;
> the first interrupt handler must execute first.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/avr/helper.c | 9 +++--
>  1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index 9614ccf3e4..34f1cbffb2 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -28,7 +28,6 @@
>
>  bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  {
> -bool ret = false;
>  AVRCPU *cpu = AVR_CPU(cs);
>  CPUAVRState *env = >env;
>
> @@ -38,8 +37,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  avr_cpu_do_interrupt(cs);
>
>  cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
> -
> -ret = true;
> +return true;
>  }
>  }
>  if (interrupt_request & CPU_INTERRUPT_HARD) {
> @@ -52,11 +50,10 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  if (!env->intsrc) {
>  cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
>  }
> -
> -ret = true;
> +return true;
>  }
>  }
> -return ret;
> +return false;
>  }
>
>  void avr_cpu_do_interrupt(CPUState *cs)
> --
> 2.34.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH] hw/avr: Realize AVRCPU qdev object using qdev_realize()

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Mon, Dec 6, 2021 at 12:41 AM Philippe Mathieu-Daudé 
wrote:

> TYPE_AVR_CPU inherits TYPE_CPU, which itself inherits TYPE_DEVICE.
> TYPE_DEVICE instances are realized using qdev_realize(), we don't
> need to access QOM internal values.
>
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/avr/atmega.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> index 0608e2d475e..a34803e6427 100644
> --- a/hw/avr/atmega.c
> +++ b/hw/avr/atmega.c
> @@ -233,7 +233,7 @@ static void atmega_realize(DeviceState *dev, Error
> **errp)
>
>  /* CPU */
>  object_initialize_child(OBJECT(dev), "cpu", >cpu, mc->cpu_type);
> -object_property_set_bool(OBJECT(>cpu), "realized", true,
> _abort);
> +qdev_realize(DEVICE(>cpu), NULL, _abort);
>  cpudev = DEVICE(>cpu);
>
>  /* SRAM */
> --
> 2.33.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH] target/avr: Optimize various functions using extract opcode

[Michael Rolnik]

hi Philippe

how was it tested?

On Wed, Oct 27, 2021 at 7:42 AM Philippe Mathieu-Daudé 
wrote:

> Hi Richard,
>
> On 10/3/21 17:24, Richard Henderson wrote:
> > On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote:
> >> When running the scripts/coccinelle/tcg_gen_extract.cocci
> >> Coccinelle semantic patch on target/avr/, we get:
> >>
> >>[DBG] candidate at target/avr/translate.c:228
> >>[DBG] candidate at target/avr/translate.c:266
> >>[DBG] candidate at target/avr/translate.c:885
> >>[DBG] candidate at target/avr/translate.c:924
> >>[DBG] candidate at target/avr/translate.c:962
> >>
> >> Manually inspect and replace combinations of (shri, andi)
> >> opcodes by the extract opcode.
> >>
> >> Signed-off-by: Philippe Mathieu-Daudé
> >> ---
> >>   target/avr/translate.c | 16 +---
> >>   1 file changed, 5 insertions(+), 11 deletions(-)
> >
> > Reviewed-by: Richard Henderson 
>
> Do you mind taking this patch via tcg-next?
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH v6 19/40] target/avr: Restrict has_work() handler to sysemu

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Fri, Sep 24, 2021 at 12:40 PM Philippe Mathieu-Daudé 
wrote:

> Restrict has_work() to sysemu.
>
> Reviewed-by: Richard Henderson 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/avr/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index 5d70e34dd54..6d51f91ca2c 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -195,6 +195,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
>  static const struct TCGCPUOps avr_tcg_ops = {
>  .initialize = avr_cpu_tcg_init,
>  .synchronize_from_tb = avr_cpu_synchronize_from_tb,
> +.has_work = avr_cpu_has_work,
>  .cpu_exec_interrupt = avr_cpu_exec_interrupt,
>  .tlb_fill = avr_cpu_tlb_fill,
>  .do_interrupt = avr_cpu_do_interrupt,
> @@ -211,7 +212,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void
> *data)
>
>  cc->class_by_name = avr_cpu_class_by_name;
>
> -cc->has_work = avr_cpu_has_work;
>  cc->dump_state = avr_cpu_dump_state;
>  cc->set_pc = avr_cpu_set_pc;
>  cc->memory_rw_debug = avr_cpu_memory_rw_debug;
> --
> 2.31.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH for-6.2 03/23] target/avr: Drop checks for singlestep_enabled

[Michael Rolnik]

Reviewed-by: Michael Rolnik 
Tested-by: Michael Rolnik 

On Wed, Jul 21, 2021 at 9:00 PM Philippe Mathieu-Daudé 
wrote:

> +Michael/Alex/Pavel
>
> On 7/21/21 8:41 AM, Richard Henderson wrote:
> > GDB single-stepping is now handled generically.
> >
> > Signed-off-by: Richard Henderson 
> > ---
> >  target/avr/translate.c | 19 ---
> >  1 file changed, 4 insertions(+), 15 deletions(-)
> >
> > diff --git a/target/avr/translate.c b/target/avr/translate.c
> > index e08b83..0403470dd8 100644
> > --- a/target/avr/translate.c
> > +++ b/target/avr/translate.c
> > @@ -1089,11 +1089,7 @@ static void gen_goto_tb(DisasContext *ctx, int n,
> target_ulong dest)
> >  tcg_gen_exit_tb(tb, n);
> >  } else {
> >  tcg_gen_movi_i32(cpu_pc, dest);
> > -if (ctx->base.singlestep_enabled) {
> > -gen_helper_debug(cpu_env);
> > -} else {
> > -tcg_gen_lookup_and_goto_ptr();
> > -}
> > +tcg_gen_lookup_and_goto_ptr();
> >  }
> >  ctx->base.is_jmp = DISAS_NORETURN;
> >  }
> > @@ -3011,17 +3007,10 @@ static void avr_tr_tb_stop(DisasContextBase
> *dcbase, CPUState *cs)
> >  tcg_gen_movi_tl(cpu_pc, ctx->npc);
> >  /* fall through */
> >  case DISAS_LOOKUP:
> > -if (!ctx->base.singlestep_enabled) {
> > -tcg_gen_lookup_and_goto_ptr();
> > -break;
> > -}
> > -/* fall through */
> > +tcg_gen_lookup_and_goto_ptr();
> > +break;
> >  case DISAS_EXIT:
> > -if (ctx->base.singlestep_enabled) {
> > -gen_helper_debug(cpu_env);
> > -} else {
> > -tcg_gen_exit_tb(NULL, 0);
> > -}
> > +tcg_gen_exit_tb(NULL, 0);
> >  break;
> >  default:
> >  g_assert_not_reached();
> >
>
> Reviewed-by: Philippe Mathieu-Daudé 
>
> Not related to this patch, but looking at the last
> gen_helper_debug() use:
>
> /*
>  *  The BREAK instruction is used by the On-chip Debug system, and is
>  *  normally not used in the application software. When the BREAK
> instruction is
>  *  executed, the AVR CPU is set in the Stopped Mode. This gives the
> On-chip
>  *  Debugger access to internal resources.  If any Lock bits are set, or
> either
>  *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the
> BREAK
>  *  instruction as a NOP and will not enter the Stopped mode.  This
> instruction
>  *  is not available in all devices. Refer to the device specific
> instruction
>  *  set summary.
>  */
> static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
> {
> if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
> return true;
> }
>
> #ifdef BREAKPOINT_ON_BREAK
> tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
> gen_helper_debug(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> #else
> /* NOP */
> #endif
>
> return true;
> }
>
> Shouldn't we have a generic 'bool gdbstub_is_attached()' in
> "exec/gdbstub.h", then use it in replay_gdb_attached() and
> trans_BREAK() instead of this BREAKPOINT_ON_BREAK build-time
> definitions?
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH] target/avr: Fix compiler errors (-Werror=enum-conversion)

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Tue, Jul 6, 2021 at 9:09 PM Stefan Weil  wrote:

> ../target/avr/translate.c: In function ‘gen_jmp_ez’:
> ../target/avr/translate.c:1012:22: error: implicit conversion from ‘enum
> ’ to ‘DisasJumpType’ [-Werror=enum-conversion]
>  1012 | ctx->base.is_jmp = DISAS_LOOKUP;
>   |  ^
>
> Signed-off-by: Stefan Weil 
> ---
>
> -Werror=enum-conversion is not enabled by -Wall, but by -Weverything
> with clang for example.
>
> As other targets use similar define statements, I think that's a simple
> fix.
>
> Regards,
> Stefan
>
>
>  target/avr/translate.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index c06ce45bc7..fcc839ac36 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -70,11 +70,9 @@ static const char reg_names[NUMBER_OF_CPU_REGISTERS][8]
> = {
>  };
>  #define REG(x) (cpu_r[x])
>
> -enum {
> -DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main
> loop.  */
> -DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition
> exit.  */
> -DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.
> */
> -};
> +#define DISAS_EXIT   DISAS_TARGET_0  /* We want return to the cpu main
> loop.  */
> +#define DISAS_LOOKUP DISAS_TARGET_1  /* We have a variable condition
> exit.  */
> +#define DISAS_CHAIN  DISAS_TARGET_2  /* We have a single condition exit.
> */
>
>  typedef struct DisasContext DisasContext;
>
> --
> 2.30.2
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v2 3/3] target/avr: Convert to TranslatorOps

[Michael Rolnik]

The whole series.

On Mon, Jun 21, 2021 at 11:33 AM Philippe Mathieu-Daudé 
wrote:

> Hi Michael,
>
> On 6/21/21 7:38 AM, Michael Rolnik wrote:
> > Reviewed-by: Michael Rolnik mailto:mrol...@gmail.com
> >>
> > Tested-by: Michael Rolnik mailto:mrol...@gmail.com>>
>
> Are your tags valid for the latest patch or the whole series?
>
> > On Mon, Jun 21, 2021 at 12:50 AM Richard Henderson
> > mailto:richard.hender...@linaro.org>>
> wrote:
> >
> > Signed-off-by: Richard Henderson  > <mailto:richard.hender...@linaro.org>>
> > ---
> >  target/avr/translate.c | 234
> ++-------
> >  1 file changed, 128 insertions(+), 106 deletions(-)
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 07/26] target/avr: Mark some helpers noreturn

[Michael Rolnik]

Reviewed-by: Michael Rolnik 


On Mon, Jun 21, 2021 at 4:34 AM Richard Henderson <
richard.hender...@linaro.org> wrote:

> All of these helpers end with cpu_loop_exit.
>
> Cc: Michael Rolnik 
> Signed-off-by: Richard Henderson 
> ---
>  target/avr/helper.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/avr/helper.h b/target/avr/helper.h
> index 8e1ae7fda0..4d02e648fa 100644
> --- a/target/avr/helper.h
> +++ b/target/avr/helper.h
> @@ -19,10 +19,10 @@
>   */
>
>  DEF_HELPER_1(wdr, void, env)
> -DEF_HELPER_1(debug, void, env)
> -DEF_HELPER_1(break, void, env)
> -DEF_HELPER_1(sleep, void, env)
> -DEF_HELPER_1(unsupported, void, env)
> +DEF_HELPER_1(debug, noreturn, env)
> +DEF_HELPER_1(break, noreturn, env)
> +DEF_HELPER_1(sleep, noreturn, env)
> +DEF_HELPER_1(unsupported, noreturn, env)
>  DEF_HELPER_3(outb, void, env, i32, i32)
>  DEF_HELPER_2(inb, tl, env, i32)
>  DEF_HELPER_3(fullwr, void, env, i32, i32)
> --
> 2.25.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v2 3/3] target/avr: Convert to TranslatorOps

[Michael Rolnik]

Reviewed-by: Michael Rolnik 
Tested-by: Michael Rolnik 

On Mon, Jun 21, 2021 at 12:50 AM Richard Henderson <
richard.hender...@linaro.org> wrote:

> Signed-off-by: Richard Henderson 
> ---
>  target/avr/translate.c | 234 ++---
>  1 file changed, 128 insertions(+), 106 deletions(-)
>
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index 66e9882422..c06ce45bc7 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -2897,113 +2897,131 @@ static bool canonicalize_skip(DisasContext *ctx)
>  return true;
>  }
>
> -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int
> max_insns)
> +static void gen_breakpoint(DisasContext *ctx)
>  {
> +canonicalize_skip(ctx);
> +tcg_gen_movi_tl(cpu_pc, ctx->npc);
> +gen_helper_debug(cpu_env);
> +ctx->base.is_jmp = DISAS_NORETURN;
> +}
> +
> +static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> *cs)
> +{
> +DisasContext *ctx = container_of(dcbase, DisasContext, base);
>  CPUAVRState *env = cs->env_ptr;
> -DisasContext ctx1 = {
> -.base.tb = tb,
> -.base.is_jmp = DISAS_NEXT,
> -.base.pc_first = tb->pc,
> -.base.pc_next = tb->pc,
> -.base.singlestep_enabled = cs->singlestep_enabled,
> -.cs = cs,
> -.env = env,
> -.memidx = 0,
> -.skip_cond = TCG_COND_NEVER,
> -};
> -DisasContext *ctx = 
> -target_ulong pc_start = tb->pc / 2;
> -int num_insns = 0;
> +uint32_t tb_flags = ctx->base.tb->flags;
>
> -if (tb->flags & TB_FLAGS_FULL_ACCESS) {
> -/*
> - * This flag is set by ST/LD instruction we will regenerate it
> ONLY
> - * with mem/cpu memory access instead of mem access
> - */
> -max_insns = 1;
> -}
> -if (ctx->base.singlestep_enabled) {
> -max_insns = 1;
> -}
> +ctx->cs = cs;
> +ctx->env = env;
> +ctx->npc = ctx->base.pc_first / 2;
>
> -gen_tb_start(tb);
> -
> -ctx->npc = pc_start;
> -if (tb->flags & TB_FLAGS_SKIP) {
> +ctx->skip_cond = TCG_COND_NEVER;
> +if (tb_flags & TB_FLAGS_SKIP) {
>  ctx->skip_cond = TCG_COND_ALWAYS;
>  ctx->skip_var0 = cpu_skip;
>  }
>
> -do {
> -TCGLabel *skip_label = NULL;
> -
> -/* translate current instruction */
> -tcg_gen_insn_start(ctx->npc);
> -num_insns++;
> -
> +if (tb_flags & TB_FLAGS_FULL_ACCESS) {
>  /*
> - * this is due to some strange GDB behavior
> - * let's assume main has address 0x100
> - * b main   - sets breakpoint at address 0x0100 (code)
> - * b *0x100 - sets breakpoint at address 0x00800100 (data)
> + * This flag is set by ST/LD instruction we will regenerate it
> ONLY
> + * with mem/cpu memory access instead of mem access
>   */
> -if (unlikely(!ctx->base.singlestep_enabled &&
> -(cpu_breakpoint_test(cs, OFFSET_CODE + ctx->npc * 2, BP_ANY)
> ||
> - cpu_breakpoint_test(cs, OFFSET_DATA + ctx->npc * 2,
> BP_ANY {
> -canonicalize_skip(ctx);
> -tcg_gen_movi_tl(cpu_pc, ctx->npc);
> -gen_helper_debug(cpu_env);
> -goto done_generating;
> -}
> +ctx->base.max_insns = 1;
> +}
> +}
>
> -/* Conditionally skip the next instruction, if indicated.  */
> -if (ctx->skip_cond != TCG_COND_NEVER) {
> -skip_label = gen_new_label();
> -if (ctx->skip_var0 == cpu_skip) {
> -/*
> - * Copy cpu_skip so that we may zero it before the branch.
> - * This ensures that cpu_skip is non-zero after the label
> - * if and only if the skipped insn itself sets a skip.
> - */
> -ctx->free_skip_var0 = true;
> -ctx->skip_var0 = tcg_temp_new();
> -tcg_gen_mov_tl(ctx->skip_var0, cpu_skip);
> -tcg_gen_movi_tl(cpu_skip, 0);
> -}
> -if (ctx->skip_var1 == NULL) {
> -tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0,
> -   0, skip_label);
> -} else {
> -tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0,
> -  ctx->skip_var1, skip_label);
> -ctx->skip_var1 = NULL;
> -}
> -if (ctx-

Re: [PATCH 3/3] target/avr: Convert to TranslatorOps

[Michael Rolnik]

}
> +
> +static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> +{
> +DisasContext *ctx = container_of(dcbase, DisasContext, base);
>  bool nonconst_skip = canonicalize_skip(ctx);
>
>  switch (ctx->base.is_jmp) {
> @@ -3036,24 +3058,28 @@ void gen_intermediate_code(CPUState *cs,
> TranslationBlock *tb, int max_insns)
>  default:
>  g_assert_not_reached();
>  }
> +}
>
> -done_generating:
> -gen_tb_end(tb, num_insns);
> +static void avr_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
> +{
> +qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
> +log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
> +}
>
> -    tb->size = (ctx->npc - pc_start) * 2;
> -tb->icount = num_insns;
> +static const TranslatorOps avr_tr_ops = {
> +.init_disas_context = avr_tr_init_disas_context,
> +.tb_start   = avr_tr_tb_start,
> +.insn_start = avr_tr_insn_start,
> +.breakpoint_check   = avr_tr_breakpoint_check,
> +.translate_insn = avr_tr_translate_insn,
> +.tb_stop= avr_tr_tb_stop,
> +.disas_log  = avr_tr_disas_log,
> +};
>
> -#ifdef DEBUG_DISAS
> -if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
> -&& qemu_log_in_addr_range(tb->pc)) {
> -FILE *fd;
> -fd = qemu_log_lock();
> -qemu_log("IN: %s\n", lookup_symbol(tb->pc));
> -log_target_disas(cs, tb->pc, tb->size);
> -qemu_log("\n");
> -qemu_log_unlock(fd);
> -}
> -#endif
> +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int
> max_insns)
> +{
> +DisasContext dc;
> +translator_loop(_tr_ops, , cs, tb, max_insns);
>  }
>
>  void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
> --
> 2.25.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [RFC v3 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

ping

On Sun, May 16, 2021 at 1:10 AM Michael Rolnik  wrote:

> 1.  Initial implementation of AVR WDT
> There are two issues with this implementation so I need your help here
> a. when I configure the WDT to fire an interrupt every 15ms it
> actually happens every 6 instructions
> b. when I specify --icount shift=0 qemu stucks
>
> changes since v1
> 1.  correct RW or RW1C behavior is implemented
> 2.  icount functionality is fixed
> 3.  I still observe something strange, it takes AVR 150 instructions to
> simulate 15ms
>
> changes since v2
> 1.  use REG8 & FIELD macros to define registers
> 2.  fixing ICOUNT behavior
>
> *** BLURB HERE ***
>
> Michael Rolnik (1):
>   Implement AVR watchdog timer
>
>  MAINTAINERS   |   2 +
>  hw/avr/Kconfig|   1 +
>  hw/avr/atmega.c   |  15 +-
>  hw/avr/atmega.h   |   2 +
>  hw/watchdog/Kconfig   |   3 +
>  hw/watchdog/avr_wdt.c | 279 ++
>  hw/watchdog/meson.build   |   2 +
>  hw/watchdog/trace-events  |   5 +
>  include/hw/watchdog/avr_wdt.h |  47 ++
>  target/avr/cpu.c  |   3 +
>  target/avr/cpu.h  |   1 +
>  target/avr/helper.c   |   7 +-
>  target/avr/translate.c|  58 ++-
>  13 files changed, 419 insertions(+), 6 deletions(-)
>  create mode 100644 hw/watchdog/avr_wdt.c
>  create mode 100644 include/hw/watchdog/avr_wdt.h
>
> --
> 2.25.1
>
>

-- 
Best Regards,
Michael Rolnik

[RFC v3 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 MAINTAINERS   |   2 +
 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 +-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 279 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 ++
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 target/avr/translate.c|  58 ++-
 13 files changed, 419 insertions(+), 6 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 78561a223f..e53bccfa9a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1036,6 +1036,8 @@ F: include/hw/timer/avr_timer16.h
 F: hw/timer/avr_timer16.c
 F: include/hw/misc/avr_power.h
 F: hw/misc/avr_power.c
+F: include/hw/watchdog/avr_wdt.h
+F: hw/watchdog/avr_wdt.c
 
 Arduino
 M: Philippe Mathieu-Daudé 
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
index d31298c3cc..9939e4902f 100644
--- a/hw/avr/Kconfig
+++ b/hw/avr/Kconfig
@@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
 select AVR_TIMER16
 select AVR_USART
 select AVR_POWER
+select AVR_WDT
 
 config ARDUINO
 select AVR_ATMEGA_MCU
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 80b8a41cb5..0932f781ff 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -27,6 +27,7 @@ enum AtmegaPeripheral {
 GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
 USART0, USART1, USART2, USART3,
 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
+WDT,
 PERIFMAX
 };
 
@@ -74,6 +75,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOD] = {  0x29 },
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
+[WDT]   = {  0x60 },
 }, dev1280_2560[PERIFMAX] = {
 [USART3]= { 0x130, POWER1, 2 },
 [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
@@ -98,6 +100,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
 [GPIOA] = {  0x20 },
+[WDT]   = {  0x60 },
 };
 
 enum AtmegaIrq {
@@ -117,6 +120,7 @@ enum AtmegaIrq {
 TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
 TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
 TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
+WATCHDOG_TIMER_IRQ,
 IRQ_COUNT
 };
 
@@ -132,6 +136,7 @@ enum AtmegaIrq {
 #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
 
 static const uint8_t irq168_328[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 7,
 [TIMER2_COMPA_IRQ]  = 8,
 [TIMER2_COMPB_IRQ]  = 9,
 [TIMER2_OVF_IRQ]= 10,
@@ -146,6 +151,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
 [USART0_DRE_IRQ]= 20,
 [USART0_TXC_IRQ]= 21,
 }, irq1280_2560[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 13,
 [TIMER2_COMPA_IRQ]  = 14,
 [TIMER2_COMPB_IRQ]  = 15,
 [TIMER2_OVF_IRQ]= 16,
@@ -343,10 +349,17 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 g_free(devname);
 }
 
+/* Watchdog Timer */
+object_initialize_child(OBJECT(dev), "wdt", >wdt, TYPE_AVR_WDT);
+sysbus_realize(SYS_BUS_DEVICE(>wdt), _abort);
+sysbus_mmio_map(SYS_BUS_DEVICE(>wdt), 0,
+OFFSET_DATA + mc->dev[WDT].addr);
+qdev_connect_gpio_out_named(cpudev, "wdr", 0,
+qdev_get_gpio_in_named(DEVICE(>wdt), "wdr", 0));
+
 create_unimplemented_device("avr-twi",  OFFSET_DATA + 0x0b8, 6);
 create_unimplemented_device("avr-adc",  OFFSET_DATA + 0x078, 8);
 create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2);
-create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1);
 create_unimplemented_device("avr-spi",  OFFSET_DATA + 0x04c, 3);
 create_unimplemented_device("avr-eeprom",   OFFSET_DATA + 0x03f, 3);
 }
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..60bbd44bdd 100644
--- a/hw/avr/atmega.h
+++ b/hw/avr/atmega.h
@@ -13,6 +13,7 @@
 
 #include "hw/char/avr_usart.h"
 #include "hw/timer/avr_timer16.h"
+#include "hw/watchdog/avr_wdt.h"
 #include "hw/misc/avr_power.h"
 #include "target/avr/cpu.h"
 #include "qom/object.h"
@@ -45,6 +46,7 @@ struct AtmegaMcuState {
 AVRMaskState pwr[POWER_MAX];
 AVRUsartState usart[USART_MAX];
 AVRTimer16State timer[TIMER_MAX];
+AVRWatchdogState wdt;
 uint64_t xtal_freq_hz;
 };
 
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
index 66e1d029e3..e0f89d2fe0 100644
--- a/hw/watchdog/Kconfig
+++ b/hw/watchdog/Kconfig
@@ -20,3 +20,6 @@ config WDT_IMX2
 
 config WDT_SBSA
 bool
+
+

[RFC v3 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

1.  Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually 
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks

changes since v1
1.  correct RW or RW1C behavior is implemented
2.  icount functionality is fixed
3.  I still observe something strange, it takes AVR 150 instructions to 
simulate 15ms

changes since v2
1.  use REG8 & FIELD macros to define registers
2.  fixing ICOUNT behavior

*** BLURB HERE ***

Michael Rolnik (1):
  Implement AVR watchdog timer

 MAINTAINERS   |   2 +
 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 +-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 279 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 ++
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 target/avr/translate.c|  58 ++-
 13 files changed, 419 insertions(+), 6 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

-- 
2.25.1

Re: [RFC 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Ok, thanks.

Sent from my cell phone, please ignore typos

On Thu, May 13, 2021, 3:27 PM Pavel Dovgalyuk 
wrote:

> On 06.05.2021 00:18, Michael Rolnik wrote:
> > Signed-off-by: Michael Rolnik 
> > ---
> >   MAINTAINERS   |   2 +
> >   hw/avr/Kconfig|   1 +
> >   hw/avr/atmega.c   |  15 +-
> >   hw/avr/atmega.h   |   2 +
> >   hw/watchdog/Kconfig   |   3 +
> >   hw/watchdog/avr_wdt.c | 274 ++
> >   hw/watchdog/meson.build   |   2 +
> >   hw/watchdog/trace-events  |   5 +
> >   include/hw/watchdog/avr_wdt.h |  47 ++
> >   target/avr/cpu.c  |   3 +
> >   target/avr/cpu.h  |   1 +
> >   target/avr/helper.c   |   7 +-
> >   target/avr/translate.c|  38 -
> >   13 files changed, 391 insertions(+), 9 deletions(-)
> >   create mode 100644 hw/watchdog/avr_wdt.c
> >   create mode 100644 include/hw/watchdog/avr_wdt.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 4c05ff8bba..e1fce736d2 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1052,6 +1052,8 @@ F: include/hw/timer/avr_timer16.h
> >   F: hw/timer/avr_timer16.c
> >   F: include/hw/misc/avr_power.h
> >   F: hw/misc/avr_power.c
> > +F: include/hw/watchdog/avr_wdt.h
> > +F: hw/watchdog/avr_wdt.c
> >
> >   Arduino
> >   M: Philippe Mathieu-Daudé 
> > diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
> > index d31298c3cc..9939e4902f 100644
> > --- a/hw/avr/Kconfig
> > +++ b/hw/avr/Kconfig
> > @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
> >   select AVR_TIMER16
> >   select AVR_USART
> >   select AVR_POWER
> > +select AVR_WDT
> >
> >   config ARDUINO
> >   select AVR_ATMEGA_MCU
> > diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> > index 44c6afebbb..31ceb1c21c 100644
> > --- a/hw/avr/atmega.c
> > +++ b/hw/avr/atmega.c
> > @@ -28,6 +28,7 @@ enum AtmegaPeripheral {
> >   GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
> >   USART0, USART1, USART2, USART3,
> >   TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
> > +WDT,
> >   PERIFMAX
> >   };
> >
> > @@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
> >   [GPIOD] = {  0x29 },
> >   [GPIOC] = {  0x26 },
> >   [GPIOB] = {  0x23 },
> > +[WDT]   = {  0x60 },
> >   }, dev1280_2560[PERIFMAX] = {
> >   [USART3]= { 0x130, POWER1, 2 },
> >   [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
> > @@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
> >   [GPIOC] = {  0x26 },
> >   [GPIOB] = {  0x23 },
> >   [GPIOA] = {  0x20 },
> > +[WDT]   = {  0x60 },
> >   };
> >
> >   enum AtmegaIrq {
> > @@ -118,6 +121,7 @@ enum AtmegaIrq {
> >   TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
> >   TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
> >   TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
> > +WATCHDOG_TIMER_IRQ,
> >   IRQ_COUNT
> >   };
> >
> > @@ -133,6 +137,7 @@ enum AtmegaIrq {
> >   #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
> >
> >   static const uint8_t irq168_328[IRQ_COUNT] = {
> > +[WATCHDOG_TIMER_IRQ]= 7,
> >   [TIMER2_COMPA_IRQ]  = 8,
> >   [TIMER2_COMPB_IRQ]  = 9,
> >   [TIMER2_OVF_IRQ]= 10,
> > @@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
> >   [USART0_DRE_IRQ]= 20,
> >   [USART0_TXC_IRQ]= 21,
> >   }, irq1280_2560[IRQ_COUNT] = {
> > +[WATCHDOG_TIMER_IRQ]= 13,
> >   [TIMER2_COMPA_IRQ]  = 14,
> >   [TIMER2_COMPB_IRQ]  = 15,
> >   [TIMER2_OVF_IRQ]= 16,
> > @@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, Error
> **errp)
> >   g_free(devname);
> >   }
> >
> > +/* Watchdog Timer */
> > +object_initialize_child(OBJECT(dev), "wdt", >wdt, TYPE_AVR_WDT);
> > +sysbus_realize(SYS_BUS_DEVICE(>wdt), _abort);
> > +sysbus_mmio_map(SYS_BUS_DEVICE(>wdt), 0,
> > +OFFSET_DATA + mc->dev[WDT].addr);
> > +qdev_connect_gpio_out_named(cpudev, "wdr", 0,
> > +qdev_get_gpio_in_named(DEVICE(>wdt), "wdr", 0));
> > +
> >   create_unimplemented_device(&quo

[RFC v1 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

1.  Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually 
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks

changes since v1
1.  correct RW or RW1C behavior is implemented
2.  icount functionality is fixed
3.  I still observe something strange, it takes AVR 150 instructions to 
simulate 15ms


*** BLURB HERE ***

Michael Rolnik (1):
  Implement AVR watchdog timer

 MAINTAINERS   |   2 +
 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 +-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 274 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 ++
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 target/avr/translate.c|  38 -
 13 files changed, 391 insertions(+), 9 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

-- 
2.25.1

[RFC 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 MAINTAINERS   |   2 +
 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 +-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 274 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 ++
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 target/avr/translate.c|  38 -
 13 files changed, 391 insertions(+), 9 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 4c05ff8bba..e1fce736d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1052,6 +1052,8 @@ F: include/hw/timer/avr_timer16.h
 F: hw/timer/avr_timer16.c
 F: include/hw/misc/avr_power.h
 F: hw/misc/avr_power.c
+F: include/hw/watchdog/avr_wdt.h
+F: hw/watchdog/avr_wdt.c
 
 Arduino
 M: Philippe Mathieu-Daudé 
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
index d31298c3cc..9939e4902f 100644
--- a/hw/avr/Kconfig
+++ b/hw/avr/Kconfig
@@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
 select AVR_TIMER16
 select AVR_USART
 select AVR_POWER
+select AVR_WDT
 
 config ARDUINO
 select AVR_ATMEGA_MCU
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 44c6afebbb..31ceb1c21c 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -28,6 +28,7 @@ enum AtmegaPeripheral {
 GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
 USART0, USART1, USART2, USART3,
 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
+WDT,
 PERIFMAX
 };
 
@@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOD] = {  0x29 },
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
+[WDT]   = {  0x60 },
 }, dev1280_2560[PERIFMAX] = {
 [USART3]= { 0x130, POWER1, 2 },
 [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
@@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
 [GPIOA] = {  0x20 },
+[WDT]   = {  0x60 },
 };
 
 enum AtmegaIrq {
@@ -118,6 +121,7 @@ enum AtmegaIrq {
 TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
 TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
 TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
+WATCHDOG_TIMER_IRQ,
 IRQ_COUNT
 };
 
@@ -133,6 +137,7 @@ enum AtmegaIrq {
 #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
 
 static const uint8_t irq168_328[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 7,
 [TIMER2_COMPA_IRQ]  = 8,
 [TIMER2_COMPB_IRQ]  = 9,
 [TIMER2_OVF_IRQ]= 10,
@@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
 [USART0_DRE_IRQ]= 20,
 [USART0_TXC_IRQ]= 21,
 }, irq1280_2560[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 13,
 [TIMER2_COMPA_IRQ]  = 14,
 [TIMER2_COMPB_IRQ]  = 15,
 [TIMER2_OVF_IRQ]= 16,
@@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 g_free(devname);
 }
 
+/* Watchdog Timer */
+object_initialize_child(OBJECT(dev), "wdt", >wdt, TYPE_AVR_WDT);
+sysbus_realize(SYS_BUS_DEVICE(>wdt), _abort);
+sysbus_mmio_map(SYS_BUS_DEVICE(>wdt), 0,
+OFFSET_DATA + mc->dev[WDT].addr);
+qdev_connect_gpio_out_named(cpudev, "wdr", 0,
+qdev_get_gpio_in_named(DEVICE(>wdt), "wdr", 0));
+
 create_unimplemented_device("avr-twi",  OFFSET_DATA + 0x0b8, 6);
 create_unimplemented_device("avr-adc",  OFFSET_DATA + 0x078, 8);
 create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2);
-create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1);
 create_unimplemented_device("avr-spi",  OFFSET_DATA + 0x04c, 3);
 create_unimplemented_device("avr-eeprom",   OFFSET_DATA + 0x03f, 3);
 }
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..60bbd44bdd 100644
--- a/hw/avr/atmega.h
+++ b/hw/avr/atmega.h
@@ -13,6 +13,7 @@
 
 #include "hw/char/avr_usart.h"
 #include "hw/timer/avr_timer16.h"
+#include "hw/watchdog/avr_wdt.h"
 #include "hw/misc/avr_power.h"
 #include "target/avr/cpu.h"
 #include "qom/object.h"
@@ -45,6 +46,7 @@ struct AtmegaMcuState {
 AVRMaskState pwr[POWER_MAX];
 AVRUsartState usart[USART_MAX];
 AVRTimer16State timer[TIMER_MAX];
+AVRWatchdogState wdt;
 uint64_t xtal_freq_hz;
 };
 
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
index 66e1d029e3..e0f89d2fe0 100644
--- a/hw/watchdog/Kconfig
+++ b/hw/watchdog/Kconfig
@@ -20,3 +20,6 @@ config WDT_IMX2
 
 config WDT_SBSA
 bool
+
+

Re: [RFC 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Hi all,

I was about to make icount work. but, there is something I still don't
understand. I have this code

timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wdt_interrupt, s);

and then

void avr_wdt_interrupt(/* some arguments */) {
#define MS2NS(n)((n) * 100ull)
timer_mod_ns(timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + MS2NS(15));
}

when running with --icount shift=0, *avr_wdt_interrupt* is called about
every 1K instructions, however it should have been called 15M instructions
as shift=0 makes every instruction to be executed in 1 virtual ns.

What am I doing wrong?

Thank you,
Michael Rolnik


On Mon, May 3, 2021 at 4:36 PM Michael Rolnik  wrote:

> Hi Fred.
>
> 1. thanks
> 2. It seems I have forgotten to set those flags.
> 3. 15ms is easy to test 8s will take 533 times longer, so in my case 3200
> instructions which is totally incorrect. I don't understand why as
> I program the timer in virtual nanoseconds and not host time.
> 4. I hope Richard could help with icount.
>
> best regards,
> Michael Rolnik
>
> On Mon, May 3, 2021 at 4:15 PM Fred Konrad  wrote:
>
>>
>>
>> Le 5/2/21 à 10:10 PM, Michael Rolnik a écrit :
>> > Signed-off-by: Michael Rolnik 
>> > ---
>> >   hw/avr/Kconfig|   1 +
>> >   hw/avr/atmega.c   |  15 ++-
>> >   hw/avr/atmega.h   |   2 +
>> >   hw/watchdog/Kconfig   |   3 +
>> >   hw/watchdog/avr_wdt.c | 190 ++
>> >   hw/watchdog/meson.build   |   2 +
>> >   hw/watchdog/trace-events  |   5 +
>> >   include/hw/watchdog/avr_wdt.h |  47 +
>> >   target/avr/cpu.c  |   3 +
>> >   target/avr/cpu.h  |   1 +
>> >   target/avr/helper.c   |   7 +-
>> >   11 files changed, 271 insertions(+), 5 deletions(-)
>> >   create mode 100644 hw/watchdog/avr_wdt.c
>> >   create mode 100644 include/hw/watchdog/avr_wdt.h
>> >
>> > diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
>> > index d31298c3cc..9939e4902f 100644
>> > --- a/hw/avr/Kconfig
>> > +++ b/hw/avr/Kconfig
>> > @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
>> >   select AVR_TIMER16
>> >   select AVR_USART
>> >   select AVR_POWER
>> > +select AVR_WDT
>> >
>> >   config ARDUINO
>> >   select AVR_ATMEGA_MCU
>> > diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
>> > index 44c6afebbb..31ceb1c21c 100644
>> > --- a/hw/avr/atmega.c
>> > +++ b/hw/avr/atmega.c
>> > @@ -28,6 +28,7 @@ enum AtmegaPeripheral {
>> >   GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
>> >   USART0, USART1, USART2, USART3,
>> >   TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
>> > +WDT,
>> >   PERIFMAX
>> >   };
>> >
>> > @@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
>> >   [GPIOD] = {  0x29 },
>> >   [GPIOC] = {  0x26 },
>> >   [GPIOB] = {  0x23 },
>> > +[WDT]   = {  0x60 },
>> >   }, dev1280_2560[PERIFMAX] = {
>> >   [USART3]= { 0x130, POWER1, 2 },
>> >   [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
>> > @@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
>> >   [GPIOC] = {  0x26 },
>> >   [GPIOB] = {  0x23 },
>> >   [GPIOA] = {  0x20 },
>> > +[WDT]   = {  0x60 },
>> >   };
>> >
>> >   enum AtmegaIrq {
>> > @@ -118,6 +121,7 @@ enum AtmegaIrq {
>> >   TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
>> >   TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
>> >   TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
>> > +WATCHDOG_TIMER_IRQ,
>> >   IRQ_COUNT
>> >   };
>> >
>> > @@ -133,6 +137,7 @@ enum AtmegaIrq {
>> >   #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
>> >
>> >   static const uint8_t irq168_328[IRQ_COUNT] = {
>> > +[WATCHDOG_TIMER_IRQ]= 7,
>> >   [TIMER2_COMPA_IRQ]  = 8,
>> >   [TIMER2_COMPB_IRQ]  = 9,
>> >   [TIMER2_OVF_IRQ]= 10,
>> > @@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
>> >   [USART0_DRE_IRQ]= 20,
>> >   [USART0_TXC_IRQ]= 21,
>> >   }, irq1280_2560[IRQ_COUNT] = {
>> > +[WATCHDOG_TIMER_IRQ]= 13,
>> >   [TIMER2_COMPA_IRQ]  = 14,
>> > 

Re: [RFC 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Hi Fred.

1. thanks
2. It seems I have forgotten to set those flags.
3. 15ms is easy to test 8s will take 533 times longer, so in my case 3200
instructions which is totally incorrect. I don't understand why as
I program the timer in virtual nanoseconds and not host time.
4. I hope Richard could help with icount.

best regards,
Michael Rolnik

On Mon, May 3, 2021 at 4:15 PM Fred Konrad  wrote:

>
>
> Le 5/2/21 à 10:10 PM, Michael Rolnik a écrit :
> > Signed-off-by: Michael Rolnik 
> > ---
> >   hw/avr/Kconfig|   1 +
> >   hw/avr/atmega.c   |  15 ++-
> >   hw/avr/atmega.h   |   2 +
> >   hw/watchdog/Kconfig   |   3 +
> >   hw/watchdog/avr_wdt.c | 190 ++
> >   hw/watchdog/meson.build   |   2 +
> >   hw/watchdog/trace-events  |   5 +
> >   include/hw/watchdog/avr_wdt.h |  47 +
> >   target/avr/cpu.c  |   3 +
> >   target/avr/cpu.h  |   1 +
> >   target/avr/helper.c   |   7 +-
> >   11 files changed, 271 insertions(+), 5 deletions(-)
> >   create mode 100644 hw/watchdog/avr_wdt.c
> >   create mode 100644 include/hw/watchdog/avr_wdt.h
> >
> > diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
> > index d31298c3cc..9939e4902f 100644
> > --- a/hw/avr/Kconfig
> > +++ b/hw/avr/Kconfig
> > @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
> >   select AVR_TIMER16
> >   select AVR_USART
> >   select AVR_POWER
> > +select AVR_WDT
> >
> >   config ARDUINO
> >   select AVR_ATMEGA_MCU
> > diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> > index 44c6afebbb..31ceb1c21c 100644
> > --- a/hw/avr/atmega.c
> > +++ b/hw/avr/atmega.c
> > @@ -28,6 +28,7 @@ enum AtmegaPeripheral {
> >   GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
> >   USART0, USART1, USART2, USART3,
> >   TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
> > +WDT,
> >   PERIFMAX
> >   };
> >
> > @@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
> >   [GPIOD] = {  0x29 },
> >   [GPIOC] = {  0x26 },
> >   [GPIOB] = {  0x23 },
> > +[WDT]   = {  0x60 },
> >   }, dev1280_2560[PERIFMAX] = {
> >   [USART3]= { 0x130, POWER1, 2 },
> >   [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
> > @@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
> >   [GPIOC] = {  0x26 },
> >   [GPIOB] = {  0x23 },
> >   [GPIOA] = {  0x20 },
> > +[WDT]   = {  0x60 },
> >   };
> >
> >   enum AtmegaIrq {
> > @@ -118,6 +121,7 @@ enum AtmegaIrq {
> >   TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
> >   TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
> >   TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
> > +WATCHDOG_TIMER_IRQ,
> >   IRQ_COUNT
> >   };
> >
> > @@ -133,6 +137,7 @@ enum AtmegaIrq {
> >   #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
> >
> >   static const uint8_t irq168_328[IRQ_COUNT] = {
> > +[WATCHDOG_TIMER_IRQ]= 7,
> >   [TIMER2_COMPA_IRQ]  = 8,
> >   [TIMER2_COMPB_IRQ]  = 9,
> >   [TIMER2_OVF_IRQ]= 10,
> > @@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
> >   [USART0_DRE_IRQ]= 20,
> >   [USART0_TXC_IRQ]= 21,
> >   }, irq1280_2560[IRQ_COUNT] = {
> > +[WATCHDOG_TIMER_IRQ]= 13,
> >   [TIMER2_COMPA_IRQ]  = 14,
> >   [TIMER2_COMPB_IRQ]  = 15,
> >   [TIMER2_OVF_IRQ]= 16,
> > @@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, Error
> **errp)
> >   g_free(devname);
> >   }
> >
> > +/* Watchdog Timer */
> > +object_initialize_child(OBJECT(dev), "wdt", >wdt, TYPE_AVR_WDT);
> > +sysbus_realize(SYS_BUS_DEVICE(>wdt), _abort);
> > +sysbus_mmio_map(SYS_BUS_DEVICE(>wdt), 0,
> > +OFFSET_DATA + mc->dev[WDT].addr);
> > +qdev_connect_gpio_out_named(cpudev, "wdr", 0,
> > +qdev_get_gpio_in_named(DEVICE(>wdt), "wdr", 0));
> > +
> >   create_unimplemented_device("avr-twi",  OFFSET_DATA +
> 0x0b8, 6);
> >   create_unimplemented_device("avr-adc",  OFFSET_DATA +
> 0x078, 8);
> >   create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA +
> 0x074, 2);
> > -cre

[RFC 1/1] Implement AVR watchdog timer

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 ++-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 190 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 +
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 11 files changed, 271 insertions(+), 5 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
index d31298c3cc..9939e4902f 100644
--- a/hw/avr/Kconfig
+++ b/hw/avr/Kconfig
@@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
 select AVR_TIMER16
 select AVR_USART
 select AVR_POWER
+select AVR_WDT
 
 config ARDUINO
 select AVR_ATMEGA_MCU
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 44c6afebbb..31ceb1c21c 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -28,6 +28,7 @@ enum AtmegaPeripheral {
 GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
 USART0, USART1, USART2, USART3,
 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
+WDT,
 PERIFMAX
 };
 
@@ -75,6 +76,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOD] = {  0x29 },
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
+[WDT]   = {  0x60 },
 }, dev1280_2560[PERIFMAX] = {
 [USART3]= { 0x130, POWER1, 2 },
 [TIMER5]= { 0x120, POWER1, 5, 0x73, 0x3a, true },
@@ -99,6 +101,7 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
 [GPIOC] = {  0x26 },
 [GPIOB] = {  0x23 },
 [GPIOA] = {  0x20 },
+[WDT]   = {  0x60 },
 };
 
 enum AtmegaIrq {
@@ -118,6 +121,7 @@ enum AtmegaIrq {
 TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
 TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
 TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
+WATCHDOG_TIMER_IRQ,
 IRQ_COUNT
 };
 
@@ -133,6 +137,7 @@ enum AtmegaIrq {
 #define TIMER_OVF_IRQ(n)(n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
 
 static const uint8_t irq168_328[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 7,
 [TIMER2_COMPA_IRQ]  = 8,
 [TIMER2_COMPB_IRQ]  = 9,
 [TIMER2_OVF_IRQ]= 10,
@@ -147,6 +152,7 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
 [USART0_DRE_IRQ]= 20,
 [USART0_TXC_IRQ]= 21,
 }, irq1280_2560[IRQ_COUNT] = {
+[WATCHDOG_TIMER_IRQ]= 13,
 [TIMER2_COMPA_IRQ]  = 14,
 [TIMER2_COMPB_IRQ]  = 15,
 [TIMER2_OVF_IRQ]= 16,
@@ -344,10 +350,17 @@ static void atmega_realize(DeviceState *dev, Error **errp)
 g_free(devname);
 }
 
+/* Watchdog Timer */
+object_initialize_child(OBJECT(dev), "wdt", >wdt, TYPE_AVR_WDT);
+sysbus_realize(SYS_BUS_DEVICE(>wdt), _abort);
+sysbus_mmio_map(SYS_BUS_DEVICE(>wdt), 0,
+OFFSET_DATA + mc->dev[WDT].addr);
+qdev_connect_gpio_out_named(cpudev, "wdr", 0,
+qdev_get_gpio_in_named(DEVICE(>wdt), "wdr", 0));
+
 create_unimplemented_device("avr-twi",  OFFSET_DATA + 0x0b8, 6);
 create_unimplemented_device("avr-adc",  OFFSET_DATA + 0x078, 8);
 create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2);
-create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1);
 create_unimplemented_device("avr-spi",  OFFSET_DATA + 0x04c, 3);
 create_unimplemented_device("avr-eeprom",   OFFSET_DATA + 0x03f, 3);
 }
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..60bbd44bdd 100644
--- a/hw/avr/atmega.h
+++ b/hw/avr/atmega.h
@@ -13,6 +13,7 @@
 
 #include "hw/char/avr_usart.h"
 #include "hw/timer/avr_timer16.h"
+#include "hw/watchdog/avr_wdt.h"
 #include "hw/misc/avr_power.h"
 #include "target/avr/cpu.h"
 #include "qom/object.h"
@@ -45,6 +46,7 @@ struct AtmegaMcuState {
 AVRMaskState pwr[POWER_MAX];
 AVRUsartState usart[USART_MAX];
 AVRTimer16State timer[TIMER_MAX];
+AVRWatchdogState wdt;
 uint64_t xtal_freq_hz;
 };
 
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
index 66e1d029e3..e0f89d2fe0 100644
--- a/hw/watchdog/Kconfig
+++ b/hw/watchdog/Kconfig
@@ -20,3 +20,6 @@ config WDT_IMX2
 
 config WDT_SBSA
 bool
+
+config AVR_WDT
+bool
diff --git a/hw/watchdog/avr_wdt.c b/hw/watchdog/avr_wdt.c
new file mode 100644
index 00..4ce1029a64
--- /dev/null
+++ b/hw/watchdog/avr_wdt.c
@@ -0,0 +1,190 @@
+/*
+ * AVR watchdog
+ *
+ * Copyright (c) 2018 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as pub

[RFC 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

1.  Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually 
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks

Michael Rolnik (1):
  Implement AVR watchdog timer

 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 ++-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 188 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 +
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 11 files changed, 269 insertions(+), 5 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

-- 
2.25.1

[RFC 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

1.  Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually 
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks

Michael Rolnik (1):
  Implement AVR watchdog timer

 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 ++-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 190 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 +
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 11 files changed, 271 insertions(+), 5 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

-- 
2.25.1

[RFC 0/1] Implement AVR WDT (watchdog timer)

[Michael Rolnik]

1.  Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually 
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks

Michael Rolnik (1):
  Implement AVR watchdog timer

 hw/avr/Kconfig|   1 +
 hw/avr/atmega.c   |  15 ++-
 hw/avr/atmega.h   |   2 +
 hw/watchdog/Kconfig   |   3 +
 hw/watchdog/avr_wdt.c | 188 ++
 hw/watchdog/meson.build   |   2 +
 hw/watchdog/trace-events  |   5 +
 include/hw/watchdog/avr_wdt.h |  47 +
 target/avr/cpu.c  |   3 +
 target/avr/cpu.h  |   1 +
 target/avr/helper.c   |   7 +-
 11 files changed, 269 insertions(+), 5 deletions(-)
 create mode 100644 hw/watchdog/avr_wdt.c
 create mode 100644 include/hw/watchdog/avr_wdt.h

-- 
2.25.1

Re: [RFC] AVR watchdog

[Michael Rolnik]

Hi Fred.

How can I reproduce it?
Thank you.
Michael Rolnik

Sent from my cell phone, please ignore typos

On Wed, Apr 28, 2021, 5:17 PM Fred Konrad  wrote:

> Hi,
>
> I fall on a segfault while running the wdr instruction on AVR:
>
> (gdb) bt
>   #0  0xadd0b23a in gdb_get_cpu_pid (cpu=0xaf5a4af0) at
> ../gdbstub.c:718
>   #1  0xadd0b2dd in gdb_get_cpu_process (cpu=0xaf5a4af0) at
> ../gdbstub.c:743
>   #2  0xadd0e477 in gdb_set_stop_cpu (cpu=0xaf5a4af0) at
> ../gdbstub.c:2742
>   #3  0xadc99b96 in cpu_handle_guest_debug
> (cpu=0xaf5a4af0) at
> ../softmmu/cpus.c:306
>   #4  0xadcc66ab in rr_cpu_thread_fn (arg=0xaf5a4af0) at
> ../accel/tcg/tcg-accel-ops-rr.c:224
>   #5  0xadefaf12 in qemu_thread_start (args=0xaf5d9870) at
> ../util/qemu-thread-posix.c:521
>   #6  0x7f692d940ea5 in start_thread () from /lib64/libpthread.so.0
>   #7  0x7f692d6699fd in clone () from /lib64/libc.so.6
>
> Wondering if there are some plan/on-going work to implement this watchdog?
>
> ---
>
> Also meanwhile I though about a workaround like that:
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index 35e1019594..7944ed21f4 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -24,6 +24,7 @@
>   #include "exec/exec-all.h"
>   #include "exec/address-spaces.h"
>   #include "exec/helper-proto.h"
> +#include "sysemu/runstate.h"
>
>   bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>   {
> @@ -191,7 +192,7 @@ void helper_wdr(CPUAVRState *env)
>   CPUState *cs = env_cpu(env);
>
>   /* WD is not implemented yet, placeholder */
> -cs->exception_index = EXCP_DEBUG;
> +qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
>   cpu_loop_exit(cs);
>   }
>
> In the case the guest wants to reset the board through the watchdog, would
> that
> make sense to swap to that?
>
> Best Regards,
> Fred
>

Re: [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits

[Michael Rolnik]

Please review.

On Tue, Mar 23, 2021 at 10:28 PM Michael Rolnik  wrote:

> If I set TARGET_PAGE_BITS to 12 this *assert assert(v_l2_levels >= 0);*
> will fail (page_table_config_init function) because
> TARGET_PHYS_ADDR_SPACE_BITS is 24 bits, because AVR has 24 is the longest
> pointer AVR has. I can set TARGET_PHYS_ADDR_SPACE_BITS to 32 and
> TARGET_PAGE_BITS to 12 and everything will work fine.
> What do you think?
>
> btw, wrote the original comment, you David referred to, when I did not
> know that QEMU could map several regions to the same page, which is not
> true. That's why I could change 8 to 10.
>
> On Tue, Mar 23, 2021 at 10:11 PM Michael Rolnik  wrote:
>
>> how long?
>>
>> On Tue, Mar 23, 2021 at 2:46 PM Dr. David Alan Gilbert <
>> dgilb...@redhat.com> wrote:
>>
>>> * Michael Rolnik (mrol...@gmail.com) wrote:
>>> > Signed-off-by: Michael Rolnik 
>>> > ---
>>> >  target/avr/cpu-param.h | 8 +---
>>> >  target/avr/helper.c| 2 --
>>> >  2 files changed, 1 insertion(+), 9 deletions(-)
>>> >
>>> > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
>>> > index 7ef4e7c679..9765a9d0db 100644
>>> > --- a/target/avr/cpu-param.h
>>> > +++ b/target/avr/cpu-param.h
>>> > @@ -22,13 +22,7 @@
>>> >  #define AVR_CPU_PARAM_H
>>> >
>>> >  #define TARGET_LONG_BITS 32
>>> > -/*
>>> > - * TARGET_PAGE_BITS cannot be more than 8 bits because
>>> > - * 1.  all IO registers occupy [0x .. 0x00ff] address range, and
>>> they
>>> > - * should be implemented as a device and not memory
>>> > - * 2.  SRAM starts at the address 0x0100
>>>
>>> I don't know AVR; but that seems to say why you can't make it any larger
>>> - how do you solve that?
>>>
>>> Dave
>>>
>>> > -#define TARGET_PAGE_BITS 8
>>> > +#define TARGET_PAGE_BITS 10
>>> >  #define TARGET_PHYS_ADDR_SPACE_BITS 24
>>> >  #define TARGET_VIRT_ADDR_SPACE_BITS 24
>>> >  #define NB_MMU_MODES 2
>>> > diff --git a/target/avr/helper.c b/target/avr/helper.c
>>> > index 35e1019594..da658afed3 100644
>>> > --- a/target/avr/helper.c
>>> > +++ b/target/avr/helper.c
>>> > @@ -111,8 +111,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address,
>>> int size,
>>> >  MemTxAttrs attrs = {};
>>> >  uint32_t paddr;
>>> >
>>> > -address &= TARGET_PAGE_MASK;
>>> > -
>>> >  if (mmu_idx == MMU_CODE_IDX) {
>>> >  /* access to code in flash */
>>> >  paddr = OFFSET_CODE + address;
>>> > --
>>> > 2.25.1
>>> >
>>> --
>>> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>>>
>>>
>>
>> --
>> Best Regards,
>> Michael Rolnik
>>
>
>
> --
> Best Regards,
> Michael Rolnik
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits

[Michael Rolnik]

If I set TARGET_PAGE_BITS to 12 this *assert assert(v_l2_levels >= 0);*
will fail (page_table_config_init function) because
TARGET_PHYS_ADDR_SPACE_BITS is 24 bits, because AVR has 24 is the longest
pointer AVR has. I can set TARGET_PHYS_ADDR_SPACE_BITS to 32 and
TARGET_PAGE_BITS to 12 and everything will work fine.
What do you think?

btw, wrote the original comment, you David referred to, when I did not know
that QEMU could map several regions to the same page, which is not true.
That's why I could change 8 to 10.

On Tue, Mar 23, 2021 at 10:11 PM Michael Rolnik  wrote:

> how long?
>
> On Tue, Mar 23, 2021 at 2:46 PM Dr. David Alan Gilbert <
> dgilb...@redhat.com> wrote:
>
>> * Michael Rolnik (mrol...@gmail.com) wrote:
>> > Signed-off-by: Michael Rolnik 
>> > ---
>> >  target/avr/cpu-param.h | 8 +---
>> >  target/avr/helper.c| 2 --
>> >  2 files changed, 1 insertion(+), 9 deletions(-)
>> >
>> > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
>> > index 7ef4e7c679..9765a9d0db 100644
>> > --- a/target/avr/cpu-param.h
>> > +++ b/target/avr/cpu-param.h
>> > @@ -22,13 +22,7 @@
>> >  #define AVR_CPU_PARAM_H
>> >
>> >  #define TARGET_LONG_BITS 32
>> > -/*
>> > - * TARGET_PAGE_BITS cannot be more than 8 bits because
>> > - * 1.  all IO registers occupy [0x .. 0x00ff] address range, and
>> they
>> > - * should be implemented as a device and not memory
>> > - * 2.  SRAM starts at the address 0x0100
>>
>> I don't know AVR; but that seems to say why you can't make it any larger
>> - how do you solve that?
>>
>> Dave
>>
>> > -#define TARGET_PAGE_BITS 8
>> > +#define TARGET_PAGE_BITS 10
>> >  #define TARGET_PHYS_ADDR_SPACE_BITS 24
>> >  #define TARGET_VIRT_ADDR_SPACE_BITS 24
>> >  #define NB_MMU_MODES 2
>> > diff --git a/target/avr/helper.c b/target/avr/helper.c
>> > index 35e1019594..da658afed3 100644
>> > --- a/target/avr/helper.c
>> > +++ b/target/avr/helper.c
>> > @@ -111,8 +111,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address,
>> int size,
>> >  MemTxAttrs attrs = {};
>> >  uint32_t paddr;
>> >
>> > -address &= TARGET_PAGE_MASK;
>> > -
>> >  if (mmu_idx == MMU_CODE_IDX) {
>> >  /* access to code in flash */
>> >  paddr = OFFSET_CODE + address;
>> > --
>> > 2.25.1
>> >
>> --
>> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits

[Michael Rolnik]

how long?

On Tue, Mar 23, 2021 at 2:46 PM Dr. David Alan Gilbert 
wrote:

> * Michael Rolnik (mrol...@gmail.com) wrote:
> > Signed-off-by: Michael Rolnik 
> > ---
> >  target/avr/cpu-param.h | 8 +---
> >  target/avr/helper.c| 2 --
> >  2 files changed, 1 insertion(+), 9 deletions(-)
> >
> > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
> > index 7ef4e7c679..9765a9d0db 100644
> > --- a/target/avr/cpu-param.h
> > +++ b/target/avr/cpu-param.h
> > @@ -22,13 +22,7 @@
> >  #define AVR_CPU_PARAM_H
> >
> >  #define TARGET_LONG_BITS 32
> > -/*
> > - * TARGET_PAGE_BITS cannot be more than 8 bits because
> > - * 1.  all IO registers occupy [0x .. 0x00ff] address range, and
> they
> > - * should be implemented as a device and not memory
> > - * 2.  SRAM starts at the address 0x0100
>
> I don't know AVR; but that seems to say why you can't make it any larger
> - how do you solve that?
>
> Dave
>
> > -#define TARGET_PAGE_BITS 8
> > +#define TARGET_PAGE_BITS 10
> >  #define TARGET_PHYS_ADDR_SPACE_BITS 24
> >  #define TARGET_VIRT_ADDR_SPACE_BITS 24
> >  #define NB_MMU_MODES 2
> > diff --git a/target/avr/helper.c b/target/avr/helper.c
> > index 35e1019594..da658afed3 100644
> > --- a/target/avr/helper.c
> > +++ b/target/avr/helper.c
> > @@ -111,8 +111,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> >  MemTxAttrs attrs = {};
> >  uint32_t paddr;
> >
> > -address &= TARGET_PAGE_MASK;
> > -
> >  if (mmu_idx == MMU_CODE_IDX) {
> >  /* access to code in flash */
> >  paddr = OFFSET_CODE + address;
> > --
> > 2.25.1
> >
> --
> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>
>

-- 
Best Regards,
Michael Rolnik

[PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 target/avr/cpu-param.h | 8 +---
 target/avr/helper.c| 2 --
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 7ef4e7c679..9765a9d0db 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -22,13 +22,7 @@
 #define AVR_CPU_PARAM_H
 
 #define TARGET_LONG_BITS 32
-/*
- * TARGET_PAGE_BITS cannot be more than 8 bits because
- * 1.  all IO registers occupy [0x .. 0x00ff] address range, and they
- * should be implemented as a device and not memory
- * 2.  SRAM starts at the address 0x0100
- */
-#define TARGET_PAGE_BITS 8
+#define TARGET_PAGE_BITS 10
 #define TARGET_PHYS_ADDR_SPACE_BITS 24
 #define TARGET_VIRT_ADDR_SPACE_BITS 24
 #define NB_MMU_MODES 2
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 35e1019594..da658afed3 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -111,8 +111,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 MemTxAttrs attrs = {};
 uint32_t paddr;
 
-address &= TARGET_PAGE_MASK;
-
 if (mmu_idx == MMU_CODE_IDX) {
 /* access to code in flash */
 paddr = OFFSET_CODE + address;
-- 
2.25.1

[PATCH 0/1] Set AVR TARGET_PAGE_BITS to be 10 instead of 8

[Michael Rolnik]

The previous value of TARGET_PAGE_BITS (8) is a bug. Make it 10
I tested it using the following commands
1. ninja test
2. make check-qtest-avr
3. avocado --show=app run -t arch:avr tests/acceptance/

Michael Rolnik (1):
  Set TARGET_PAGE_BITS to be 10 instead of 8 bits

 target/avr/cpu-param.h | 8 +---
 target/avr/helper.c| 2 --
 2 files changed, 1 insertion(+), 9 deletions(-)

-- 
2.25.1

Re: of AVR target page size

[Michael Rolnik]

how do I test my fix? Is there a procedure?

Thanks,
Michael Rolnik

On Thu, Mar 18, 2021 at 12:45 PM Dr. David Alan Gilbert 
wrote:

> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Thu, 18 Mar 2021 at 10:25, Dr. David Alan Gilbert
> >  wrote:
> > > Oh yes, just:
> > >
> > > diff --git a/migration/ram.c b/migration/ram.c
> > > index 52537f14ac..a7269955b5 100644
> > > --- a/migration/ram.c
> > > +++ b/migration/ram.c
> > > @@ -81,6 +81,8 @@
> > >  /* 0x80 is reserved in migration.h start with 0x100 next */
> > >  #define RAM_SAVE_FLAG_COMPRESS_PAGE0x100
> > >
> > > +#define RAM_SAVE_FLAG__MAX RAM_SAVE_FLAG_COMPRESS_PAGE
> > > +
> > >  static inline bool is_zero_range(uint8_t *p, uint64_t size)
> > >  {
> > >  return buffer_is_zero(p, size);
> > > @@ -4090,5 +4092,6 @@ static SaveVMHandlers savevm_ram_handlers = {
> > >  void ram_mig_init(void)
> > >  {
> > >  qemu_mutex_init();
> > > +QEMU_BUILD_BUG_ON(RAM_SAVE_FLAG__MAX >= (1 <<
> TARGET_PAGE_BITS_MIN));
> > >  register_savevm_live("ram", 0, 4, _ram_handlers,
> _state);
> > >  }
> > >
> > >
> > > works; lets keep that in mind somewhere after Michael fixes AVR.
> >
> > You don't have a great deal of headroom even after getting AVR
> > to change, by the way -- TARGET_PAGE_BITS_MIN for Arm is 10.
> > So you might want to think about ways to eg reclaim usage of
> > that "obsolete, not used" RAM_SAVE_FLAG_FULL bit.
>
> Yep, I've been warning anyone who adds one for ages
>
> > Also, what does the
> >  /* 0x80 is reserved in migration.h start with 0x100 next */
> > comment refer to? migration.h has no instances of "RAM_SAVE"
> > or 0x80 or 1 << 7...
>
> It looks like it got moved to qemu-file.h a few years ago
> as RAM_SAVE_FLAG_HOOK.
>
> Dave
>
> > thanks
> > -- PMM
> >
> --
> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>
>

-- 
Best Regards,
Michael Rolnik

Re: of AVR target page size

[Michael Rolnik]

ok. I will try to fix it.

Regards,
Michael Rolnik

On Thu, Mar 18, 2021 at 11:55 AM Dr. David Alan Gilbert 
wrote:

> * Michael Rolnik (mrol...@gmail.com) wrote:
> > Hi Dave.
> >
> > What is the smallest supported page size?
>
> Currently 512 I think; in migration/ram.c we have:
>
> #define RAM_SAVE_FLAG_FULL 0x01 /* Obsolete, not used anymore */
> #define RAM_SAVE_FLAG_ZERO 0x02
> #define RAM_SAVE_FLAG_MEM_SIZE 0x04
> #define RAM_SAVE_FLAG_PAGE 0x08
> #define RAM_SAVE_FLAG_EOS  0x10
> #define RAM_SAVE_FLAG_CONTINUE 0x20
> #define RAM_SAVE_FLAG_XBZRLE   0x40
> /* 0x80 is reserved in migration.h start with 0x100 next */
> #define RAM_SAVE_FLAG_COMPRESS_PAGE0x100
>
> so we're already using the 0x100 (256) flag.
>
> I spotted this yesterday because a patch tried to use the 0x200 flag.
>
> Dave
> >
> > On Wed, Mar 17, 2021 at 10:14 PM Dr. David Alan Gilbert <
> dgilb...@redhat.com>
> > wrote:
> >
> > > Hi Michael,
> > >   I noticed your AVR code defines:
> > >
> > >   #define TARGET_PAGE_BITS 8
> > >
> > > and has an explanation of why.
> > >
> > > Note however that's not going to work with the current live
> > > migration/snapshotting code, since you're a couple of bits smaller
> > > than the smallest page size we had so far, and for many years
> > > the RAM migration code has stolen the bottom few bits of the address
> > > as a flag field, and has already used 0x100 up; see migration/ram.c
> > > RAM_SAVE_FLAG_*- and it's actually tricky to change it, because if
> > > you change it then it'll break migration compatibility with existing
> > > qemu's.
> > >
> > > Hmm.
> > >
> > > Dave
> > >
> > > --
> > > Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
> > >
> > >
> >
> > --
> > Best Regards,
> > Michael Rolnik
> --
> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>
>

-- 
Best Regards,
Michael Rolnik

Re: of AVR target page size

[Michael Rolnik]

I guess we can add some bits TARGET_PAGE_BITS, this will make us to push
some portion of SRAM into the CPU.

Michael Rolnik

On Thu, Mar 18, 2021 at 12:33 AM Peter Maydell 
wrote:

> On Wed, 17 Mar 2021 at 20:17, Dr. David Alan Gilbert
>  wrote:
> >
> > Hi Michael,
> >   I noticed your AVR code defines:
> >
> >   #define TARGET_PAGE_BITS 8
> >
> > and has an explanation of why.
> >
> > Note however that's not going to work with the current live
> > migration/snapshotting code, since you're a couple of bits smaller
> > than the smallest page size we had so far, and for many years
> > the RAM migration code has stolen the bottom few bits of the address
> > as a flag field, and has already used 0x100 up; see migration/ram.c
> > RAM_SAVE_FLAG_*- and it's actually tricky to change it, because if
> > you change it then it'll break migration compatibility with existing
> > qemu's.
>
> If you want to use low bits as flags for other stuff, you
> should have a compile time assert that you have the number
> of bits you expect, or otherwise force a compile error.
> Otherwise you'll end up with unpleasant surprises like this one...
>
> I think that for the cpu-all.h uses of low bits we would
> end up with a compile error for excessively small TARGET_PAGE_BITS
> because we define the bits like this:
> #define TLB_DISCARD_WRITE   (1 << (TARGET_PAGE_BITS_MIN - 6))
> and I expect the compiler will complain if the RHS of the '<<'
> is a negative constant. But I don't know if that's deliberate
> or a happy accident :-)
>
> thanks
> -- PMM
>


-- 
Best Regards,
Michael Rolnik

Re: of AVR target page size

[Michael Rolnik]

Hi Dave.

What is the smallest supported page size?


On Wed, Mar 17, 2021 at 10:14 PM Dr. David Alan Gilbert 
wrote:

> Hi Michael,
>   I noticed your AVR code defines:
>
>   #define TARGET_PAGE_BITS 8
>
> and has an explanation of why.
>
> Note however that's not going to work with the current live
> migration/snapshotting code, since you're a couple of bits smaller
> than the smallest page size we had so far, and for many years
> the RAM migration code has stolen the bottom few bits of the address
> as a flag field, and has already used 0x100 up; see migration/ram.c
> RAM_SAVE_FLAG_*- and it's actually tricky to change it, because if
> you change it then it'll break migration compatibility with existing
> qemu's.
>
> Hmm.
>
> Dave
>
> --
> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 00/11] AVR patch queue for QEMU 6.0

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Sat, Mar 13, 2021 at 6:54 PM Philippe Mathieu-Daudé 
wrote:

> Hi,
>
> This series contains all the AVR patches I could find on the list.
>
> Niteesh, I fixed minor issues. Do you mind reviewing on top?
>
> Pull request planned for Monday if no problem arises.
>
> Thanks,
>
> Phil.
>
> G S Niteesh Babu (2):
>   hw/gpio/avr_gpio: Add tracing for reads and writes
>   hw/avr/arduino: Add D13 LED
>
> Heecheol Yang (1):
>   hw/avr: Add limited support for avr gpio registers
>
> Ivanov Arkasha (1):
>   target/avr: Fix interrupt execution
>
> Lichang Zhao (1):
>   target/avr: Fix some comment spelling errors
>
> Philippe Mathieu-Daudé (6):
>   hw/misc/led: Add yellow LED
>   hw/avr/arduino: List board schematic links
>   hw/gpio/avr_gpio: Add migration VMstate
>   hw/gpio/avr_gpio: Add 'id' field in AVRGPIOState
>   hw/gpio/avr_gpio: Simplify avr_gpio_write_port using extract32()
>   hw/avr/arduino: Replace magic number by gpio_port_index() call
>
>  hw/avr/atmega.h|   2 +
>  include/hw/gpio/avr_gpio.h |  54 
>  include/hw/misc/led.h  |   1 +
>  hw/avr/arduino.c   |  44 +-
>  hw/avr/atmega.c|   8 +-
>  hw/gpio/avr_gpio.c | 173 +
>  hw/misc/led.c  |   1 +
>  target/avr/helper.c|  10 ++-
>  hw/avr/Kconfig |   2 +
>  hw/gpio/Kconfig|   3 +
>  hw/gpio/meson.build|   1 +
>  hw/gpio/trace-events   |   5 ++
>  12 files changed, 294 insertions(+), 10 deletions(-)
>  create mode 100644 include/hw/gpio/avr_gpio.h
>  create mode 100644 hw/gpio/avr_gpio.c
>
> --
> 2.26.2
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 0/3] AVR GPIO Emulation and Arduino D13 LED

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Thu, Mar 11, 2021 at 3:55 PM G S Niteesh Babu 
wrote:

> Hello,
>
> The following series of the patches add a basic AVR GPIO emulation
> to QEMU. The AVR GPIO emulation patch was originally written by
> Heecheol Yang and was posted on the mailing list around 5 months ago.
> I am re-publishing the patch with some bug fixes along with my own
> patch, Adding the D13 onboard LED.
>
> G S Niteesh Babu (2):
>   hw/gpio/avr_gpio.c: add tracing for read and writes
>   avr/arduino: Add D13 LED
>
> Heecheol Yang (1):
>   hw/avr: Add limited support for avr gpio registers
>
>  hw/avr/Kconfig |   2 +
>  hw/avr/arduino.c   |  15 
>  hw/avr/atmega.c|   7 +-
>  hw/avr/atmega.h|   2 +
>  hw/gpio/Kconfig|   3 +
>  hw/gpio/avr_gpio.c | 148 +
>  hw/gpio/meson.build|   1 +
>  hw/gpio/trace-events   |   6 ++
>  include/hw/gpio/avr_gpio.h |  53 +
>  9 files changed, 235 insertions(+), 2 deletions(-)
>  create mode 100644 hw/gpio/avr_gpio.c
>  create mode 100644 include/hw/gpio/avr_gpio.h
>
> --
> 2.17.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v5] hw/avr: Add limited support for avr gpio registers

[Michael Rolnik]

Reviewed-by: Michael Rolnik 


On Sat, Oct 10, 2020 at 5:34 PM Heecheol Yang 
wrote:

> Add some of these features for AVR GPIO:
>
>   - GPIO I/O : PORTx registers
>   - Data Direction : DDRx registers
>   - DDRx toggling : PINx registers
>
> Following things are not supported yet:
>   - MCUR registers
>
> Signed-off-by: Heecheol Yang 
> ---
>  hw/avr/Kconfig |   1 +
>  hw/avr/atmega.c|   7 +-
>  hw/avr/atmega.h|   2 +
>  hw/gpio/Kconfig|   3 +
>  hw/gpio/avr_gpio.c | 136 +
>  hw/gpio/meson.build|   2 +
>  include/hw/gpio/avr_gpio.h |  53 +++
>  7 files changed, 202 insertions(+), 2 deletions(-)
>  create mode 100644 hw/gpio/avr_gpio.c
>  create mode 100644 include/hw/gpio/avr_gpio.h
>
> diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
> index d31298c3cc..16a57ced11 100644
> --- a/hw/avr/Kconfig
> +++ b/hw/avr/Kconfig
> @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
>  select AVR_TIMER16
>  select AVR_USART
>  select AVR_POWER
> +select AVR_GPIO
>
>  config ARDUINO
>  select AVR_ATMEGA_MCU
> diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
> index 44c6afebbb..ad942028fd 100644
> --- a/hw/avr/atmega.c
> +++ b/hw/avr/atmega.c
> @@ -283,8 +283,11 @@ static void atmega_realize(DeviceState *dev, Error
> **errp)
>  continue;
>  }
>  devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
> -create_unimplemented_device(devname,
> -OFFSET_DATA + mc->dev[idx].addr, 3);
> +object_initialize_child(OBJECT(dev), devname, >gpio[i],
> +TYPE_AVR_GPIO);
> +sysbus_realize(SYS_BUS_DEVICE(>gpio[i]), _abort);
> +sysbus_mmio_map(SYS_BUS_DEVICE(>gpio[i]), 0,
> +OFFSET_DATA + mc->dev[idx].addr);
>  g_free(devname);
>  }
>
> diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
> index a99ee15c7e..e2289d5744 100644
> --- a/hw/avr/atmega.h
> +++ b/hw/avr/atmega.h
> @@ -13,6 +13,7 @@
>
>  #include "hw/char/avr_usart.h"
>  #include "hw/timer/avr_timer16.h"
> +#include "hw/gpio/avr_gpio.h"
>  #include "hw/misc/avr_power.h"
>  #include "target/avr/cpu.h"
>  #include "qom/object.h"
> @@ -44,6 +45,7 @@ struct AtmegaMcuState {
>  DeviceState *io;
>  AVRMaskState pwr[POWER_MAX];
>  AVRUsartState usart[USART_MAX];
> +AVRGPIOState gpio[GPIO_MAX];
>  AVRTimer16State timer[TIMER_MAX];
>  uint64_t xtal_freq_hz;
>  };
> diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
> index b6fdaa2586..1752d0ce56 100644
> --- a/hw/gpio/Kconfig
> +++ b/hw/gpio/Kconfig
> @@ -10,3 +10,6 @@ config GPIO_KEY
>
>  config SIFIVE_GPIO
>  bool
> +
> +config AVR_GPIO
> +bool
> diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
> new file mode 100644
> index 00..29e799670d
> --- /dev/null
> +++ b/hw/gpio/avr_gpio.c
> @@ -0,0 +1,136 @@
> +/*
> + * AVR processors GPIO registers emulation.
> + *
> + * Copyright (C) 2020 Heecheol Yang 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/sysbus.h"
> +#include "hw/irq.h"
> +#include "hw/gpio/avr_gpio.h"
> +#include "hw/qdev-properties.h"
> +
> +static void avr_gpio_reset(DeviceState *dev)
> +{
> +AVRGPIOState *gpio = AVR_GPIO(dev);
> +gpio->reg.pin = 0u;
> +gpio->reg.ddr = 0u;
> +gpio->reg.port = 0u;
> +}
> +
> +static void avr_gpio_write_port(AVRGPIOState *s, uint64_t value)
> +{
> +uint8_t pin;
> +uint8_t cur_port_val = s->reg.port;
> +uint8_t cur_ddr_val = s->reg.ddr;
> +
> +for (pin = 0u; pin < 8u ; pin++) {
> +uint8_t cur_p

Re: [RFC PATCH] contrib/gitdm: Add more individual contributors

[Michael Rolnik]

Acked-by: Michael Rolnik >

On Mon, Oct 12, 2020 at 8:56 AM sundeep subbaraya 
wrote:

> Acked-by: Subbaraya Sundeep 
>
> Thanks,
> Sundeep
>
> On Sun, Oct 4, 2020 at 11:55 PM Philippe Mathieu-Daudé 
> wrote:
> >
> > These individual contributors have a number of contributions,
> > add them to the 'individual' group map.
> >
> > Cc: Ahmed Karaman 
> > Cc: Aleksandar Markovic 
> > Cc: Alistair Francis 
> > Cc: Artyom Tarasenko 
> > Cc: David Carlier 
> > Cc: Finn Thain 
> > Cc: Guenter Roeck 
> > Cc: Helge Deller 
> > Cc: Hervé Poussineau 
> > Cc: James Hogan 
> > Cc: Jean-Christophe Dubois 
> > Cc: Kővágó Zoltán 
> > Cc: Laurent Vivier 
> > Cc: Michael Rolnik 
> > Cc: Niek Linnenbank 
> > Cc: Paul Burton 
> > Cc: Paul Zimmerman 
> > Cc: Stefan Weil 
> > Cc: Subbaraya Sundeep 
> > Cc: Sven Schnelle 
> > Cc: Thomas Huth 
> > Cc: Volker Rümelin 
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> > To the developers Cc'ed: If you agree with your entry, please
> > reply with a Reviewed-by/Acked-by tag. If you disagree or doesn't
> > care, please either reply with Nack-by or ignore this patch.
> > I'll repost in 2 weeks as formal patch (not RFC) with only the
> > entries acked by their author.
> > ---
> >  contrib/gitdm/group-map-individuals | 22 ++
> >  contrib/gitdm/group-map-redhat  |  1 -
> >  2 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/contrib/gitdm/group-map-individuals
> b/contrib/gitdm/group-map-individuals
> > index cf8a2ce367..b478fd4576 100644
> > --- a/contrib/gitdm/group-map-individuals
> > +++ b/contrib/gitdm/group-map-individuals
> > @@ -16,3 +16,25 @@ aurel...@aurel32.net
> >  bala...@eik.bme.hu
> >  e.emanuelegiuse...@gmail.com
> >  andrew.smir...@gmail.com
> > +s...@weilnetz.de
> > +h...@tuxfamily.org
> > +laur...@vivier.eu
> > +atar4q...@gmail.com
> > +hpous...@reactos.org
> > +del...@gmx.de
> > +alist...@alistair23.me
> > +fth...@telegraphics.com.au
> > +sv...@stackframe.org
> > +aleksandar.qemu.de...@gmail.com
> > +jho...@kernel.org
> > +paulbur...@kernel.org
> > +vr_q...@t-online.de
> > +nieklinnenb...@gmail.com
> > +devne...@gmail.com
> > +j...@tribudubois.net
> > +dirty.ice...@gmail.com
> > +mrol...@gmail.com
> > +pauld...@gmail.com
> > +li...@roeck-us.net
> > +sundeep.l...@gmail.com
> > +ahmedkhaledkara...@gmail.com
> > diff --git a/contrib/gitdm/group-map-redhat
> b/contrib/gitdm/group-map-redhat
> > index d15db2d35e..4a8ca84b36 100644
> > --- a/contrib/gitdm/group-map-redhat
> > +++ b/contrib/gitdm/group-map-redhat
> > @@ -3,6 +3,5 @@
> >  #
> >
> >  da...@gibson.dropbear.id.au
> > -laur...@vivier.eu
> >  p...@fedoraproject.org
> >  arm...@pond.sub.org
> > --
> > 2.26.2
> >
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH v2] hw/avr: Add limited support for avr gpio registers

[Michael Rolnik]

;
> +case GPIO_DDR:
> +return s->ddr_val;
>
Why do you need `break` after `return` ?

> +break;
> +case GPIO_PORT:
> +return s->port_val;
> +default:
> +g_assert_not_reached();
> +break;
> +}
> +return 0;
> +}
> +
> +static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value,
> +unsigned int size)
> +{
> +AVRGPIOState *s = (AVRGPIOState *)opaque;
> +switch (offset) {
> +case GPIO_PIN:
> +/* Not implemented yet */
> +break;
> +case GPIO_DDR:
> +s->ddr_val = value & 0xF;
> +break;
> +case GPIO_PORT:
> +s->port_val = value & 0xF;
> +break;
> +default:
> +g_assert_not_reached();
> +break;
> +}
> +}
> +
> +static const MemoryRegionOps avr_gpio_ops = {
> +.read = avr_gpio_read,
> +.write = avr_gpio_write,
> +.endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void avr_gpio_init(Object *obj)
> +{
> +AVRGPIOState *s = AVR_GPIO(obj);
> +memory_region_init_io(>mmio, obj, _gpio_ops, s, TYPE_AVR_GPIO,
> 3);
> +sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
> +}
> +static void avr_gpio_realize(DeviceState *dev, Error **errp)
> +{
> +avr_gpio_reset(dev);
> +}
> +
> +
> +static void avr_gpio_class_init(ObjectClass *klass, void *data)
> +{
> +DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +dc->reset = avr_gpio_reset;
> +dc->realize = avr_gpio_realize;
> +}
> +
> +static const TypeInfo avr_gpio_info = {
> +.name  = TYPE_AVR_GPIO,
> +.parent= TYPE_SYS_BUS_DEVICE,
> +.instance_size = sizeof(AVRGPIOState),
> +.instance_init = avr_gpio_init,
> +.class_init= avr_gpio_class_init,
> +};
> +
> +static void avr_gpio_register_types(void)
> +{
> +type_register_static(_gpio_info);
> +}
> +
> +type_init(avr_gpio_register_types)
> diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
> index 86cae9a0f3..258bd5dcfc 100644
> --- a/hw/gpio/meson.build
> +++ b/hw/gpio/meson.build
> @@ -11,3 +11,5 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true:
> files('omap_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true:
> files('sifive_gpio.c'))
> +
> +softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c'))
> diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h
> new file mode 100644
> index 00..84d783f8fc
> --- /dev/null
> +++ b/include/hw/gpio/avr_gpio.h
> @@ -0,0 +1,46 @@
> +/*
> + * AVR processors GPIO registers definition.
> + *
> + * Copyright (C) 2020 Heecheol Yang 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef AVR_GPIO_H
> +#define AVR_GPIO_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +/* Offsets of registers. */
> +#define GPIO_PIN   0x00
> +#define GPIO_DDR   0x01
> +#define GPIO_PORT  0x02
> +
> +#define TYPE_AVR_GPIO "avr-gpio"
> +OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO)
> +
> +struct AVRGPIOState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +
> +uint8_t ddr_val;
> +uint8_t port_val;
> +
> +};
> +
> +#endif /* AVR_GPIO_H */
> --
> 2.17.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH 0/5] hw/avr: Start using the Clock API

[Michael Rolnik]

Tested-by: Michael Rolnik 

On Fri, Aug 14, 2020 at 7:39 PM Philippe Mathieu-Daudé 
wrote:

> In this series we slowly start to use the recently added
> Clock API in the AVR ATmega MCU.
>
> As the Clock Control Unit is not yet modelled, we simply
> connect the XTAL sink to the UART and Timer sources.
>
> Philippe Mathieu-Daudé (5):
>   hw/avr/atmega: Introduce the I/O clock
>   hw/timer/avr_timer16: Use the Clock API
>   hw/char/avr_usart: Restrict register definitions to source
>   hw/char/avr_usart: Use the Clock API
>   hw/char/avr_usart: Trace baudrate changes
>
>  hw/avr/atmega.h|  2 ++
>  include/hw/char/avr_usart.h| 32 ++-
>  include/hw/timer/avr_timer16.h |  3 ++-
>  hw/avr/atmega.c|  8 --
>  hw/char/avr_usart.c| 46 ++
>  hw/timer/avr_timer16.c | 12 +++--
>  hw/char/trace-events   |  3 +++
>  7 files changed, 65 insertions(+), 41 deletions(-)
>
> --
> 2.21.3
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH] docs/system/target-avr: Improve the AVR docs and add to MAINTAINERS

[Michael Rolnik]

Reviewed-by: Michael Rolnik 

On Thu, Aug 13, 2020 at 7:50 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 8/12/20 8:53 AM, Thomas Huth wrote:
> > The examples look nicer when using "::" code blocks.
> > Also mention that "-d in_asm" only outputs instructions that have not
> > been translated by the JIT layer yet.
> > And while we're at it, also add the AVR doc file to the MAINTAINERS file.
> >
> > Signed-off-by: Thomas Huth 
> > ---
> >  MAINTAINERS|  1 +
> >  docs/system/target-avr.rst | 47 +++---
> >  2 files changed, 30 insertions(+), 18 deletions(-)
>
> Reviewed-by: Richard Henderson 
>
> r~
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH v1 04/21] target/avr: add BQL to do_interrupt and cpu_exec_interrupt

[Michael Rolnik]

Hi Robert.

I am sorry but how can I apply it? following this what I get

error: patch failed: accel/tcg/cpu-exec.c:558
error: accel/tcg/cpu-exec.c: patch does not apply
error: patch failed: target/arm/helper.c:9808
error: target/arm/helper.c: patch does not apply
error: patch failed: target/ppc/excp_helper.c:1056
error: target/ppc/excp_helper.c: patch does not apply
error: patch failed: target/sh4/helper.c:62
error: target/sh4/helper.c: patch does not apply
error: patch failed: target/unicore32/softmmu.c:118
error: target/unicore32/softmmu.c: patch does not apply



On Wed, Aug 5, 2020 at 9:17 PM Robert Foley  wrote:

> This is part of a series of changes to remove the implied BQL
> from the common code of cpu_handle_interrupt and
> cpu_handle_exception.  As part of removing the implied BQL
> from the common code, we are pushing the BQL holding
> down into the per-arch implementation functions of
> do_interrupt and cpu_exec_interrupt.
>
> The purpose of this set of changes is to set the groundwork
> so that an arch could move towards removing
> the BQL from the cpu_handle_interrupt/exception paths.
>
> This approach was suggested by Paolo Bonzini.
> For reference, here are two key posts in the discussion, explaining
> the reasoning/benefits of this approach.
> https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html
> https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html
>
> Signed-off-by: Robert Foley 
> ---
>  target/avr/helper.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index d96d14372b..f0d625c195 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -30,6 +30,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  CPUClass *cc = CPU_GET_CLASS(cs);
>  AVRCPU *cpu = AVR_CPU(cs);
>  CPUAVRState *env = >env;
> +qemu_mutex_lock_iothread();
>
>  if (interrupt_request & CPU_INTERRUPT_RESET) {
>  if (cpu_interrupts_enabled(env)) {
> @@ -53,6 +54,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>  ret = true;
>  }
>  }
> +qemu_mutex_unlock_iothread();
>  return ret;
>  }
>
> @@ -61,10 +63,15 @@ void avr_cpu_do_interrupt(CPUState *cs)
>  AVRCPU *cpu = AVR_CPU(cs);
>  CPUAVRState *env = >env;
>
> -uint32_t ret = env->pc_w;
> +uint32_t ret;
>  int vector = 0;
>  int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
>  int base = 0;
> +bool bql = !qemu_mutex_iothread_locked();
> +if (bql) {
> +qemu_mutex_lock_iothread();
> +}
> +ret = env->pc_w;
>
>  if (cs->exception_index == EXCP_RESET) {
>  vector = 0;
> @@ -87,6 +94,9 @@ void avr_cpu_do_interrupt(CPUState *cs)
>  env->sregI = 0; /* clear Global Interrupt Flag */
>
>  cs->exception_index = -1;
> +if (bql) {
> +qemu_mutex_unlock_iothread();
> +}
>  }
>
>  int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
> --
> 2.17.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH-for-5.1 0/4] misc: Document qemu_find_file and fix memory leak in avr_load_firmware

[Michael Rolnik]

Tested-by: Michael Rolnik 

I mean I got the patch, built and then ran *make check-qtest-avr* and *make
check-acceptance*

On Mon, Jul 20, 2020 at 4:24 PM Michael Rolnik  wrote:

> Reviewed-by: Michael Rolnik 
>
>
> On Tue, Jul 14, 2020 at 7:42 PM Philippe Mathieu-Daudé 
> wrote:
>
>> Fix the memory leak reported by Coverity (CID 1430449).
>>
>> Philippe Mathieu-Daudé (4):
>>   qemu/osdep: Document os_find_datadir() return value
>>   qemu/osdep: Reword qemu_get_exec_dir() documentation
>>   qemu-common: Document qemu_find_file()
>>   hw/avr/boot: Fix memory leak in avr_load_firmware()
>>
>>  include/qemu-common.h | 14 ++
>>  include/qemu/osdep.h  |  5 -
>>  hw/avr/boot.c |  2 +-
>>  os-posix.c|  3 +++
>>  os-win32.c|  7 ++-
>>  5 files changed, 28 insertions(+), 3 deletions(-)
>>
>> --
>> 2.21.3
>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH-for-5.1 0/4] misc: Document qemu_find_file and fix memory leak in avr_load_firmware

[Michael Rolnik]

Reviewed-by: Michael Rolnik 


On Tue, Jul 14, 2020 at 7:42 PM Philippe Mathieu-Daudé 
wrote:

> Fix the memory leak reported by Coverity (CID 1430449).
>
> Philippe Mathieu-Daudé (4):
>   qemu/osdep: Document os_find_datadir() return value
>   qemu/osdep: Reword qemu_get_exec_dir() documentation
>   qemu-common: Document qemu_find_file()
>   hw/avr/boot: Fix memory leak in avr_load_firmware()
>
>  include/qemu-common.h | 14 ++
>  include/qemu/osdep.h  |  5 -
>  hw/avr/boot.c |  2 +-
>  os-posix.c|  3 +++
>  os-win32.c|  7 ++-
>  5 files changed, 28 insertions(+), 3 deletions(-)
>
> --
> 2.21.3
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

hi all.

are there any news / updates about AVR support?

On Mon, Mar 23, 2020 at 10:14 PM Michael Rolnik  wrote:

> thanks Philippe.
>
> On Mon, Mar 23, 2020 at 9:20 PM Philippe Mathieu-Daudé 
> wrote:
>
>> On 3/23/20 7:03 PM, Richard Henderson wrote:
>> > On 3/23/20 10:03 AM, Michael Rolnik wrote:
>> >> Hi Philippe.
>> >>
>> >> It's been a while. let me think about it and get back to you. what is
>> your
>> >> concern ?
>>
>> We are using this series with Joaquin for a Google Summit of Code
>> project, so we are noticing some bugs and fixing them.
>> As it has not been merged, we work in a fork.
>> Since it was posted on the list, I prefer to ask on the list than
>> directly to you.
>>
>> >
>> > It shouldn't be there.  See commit 1f5c00cfdb81.
>>
>> Ah it has been moved to cpu_common_reset, thanks :)
>> I suppose it is because this port is based on some quite old work.
>>
>> >
>> >>  > +memset(env->r, 0, sizeof(env->r));
>> >>  > +
>> >>  > +tlb_flush(cs);
>> >>
>> >>  Why are you calling tlb_flush() here?
>> >
>> >
>> > r~
>> >
>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>


-- 
Best Regards,
Michael Rolnik

Re: [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

thanks Philippe.

On Mon, Mar 23, 2020 at 9:20 PM Philippe Mathieu-Daudé 
wrote:

> On 3/23/20 7:03 PM, Richard Henderson wrote:
> > On 3/23/20 10:03 AM, Michael Rolnik wrote:
> >> Hi Philippe.
> >>
> >> It's been a while. let me think about it and get back to you. what is
> your
> >> concern ?
>
> We are using this series with Joaquin for a Google Summit of Code
> project, so we are noticing some bugs and fixing them.
> As it has not been merged, we work in a fork.
> Since it was posted on the list, I prefer to ask on the list than
> directly to you.
>
> >
> > It shouldn't be there.  See commit 1f5c00cfdb81.
>
> Ah it has been moved to cpu_common_reset, thanks :)
> I suppose it is because this port is based on some quite old work.
>
> >
> >>  > +memset(env->r, 0, sizeof(env->r));
> >>  > +
> >>  > +tlb_flush(cs);
> >>
> >>  Why are you calling tlb_flush() here?
> >
> >
> > r~
> >
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

Hi Philippe.

It's been a while. let me think about it and get back to you. what is your
concern ?

Regards,
Michael Rolnik

On Mon, Mar 23, 2020 at 5:55 PM Philippe Mathieu-Daudé 
wrote:

> Hi Michael,
>
> On 1/18/20 8:13 PM, Michael Rolnik wrote:
> > This includes:
> > - CPU data structures
> > - object model classes and functions
> > - migration functions
> > - GDB hooks
> >
> > Co-developed-by: Michael Rolnik 
> > Co-developed-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Signed-off-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Acked-by: Igor Mammedov 
> > Tested-by: Philippe Mathieu-Daudé 
> > ---
> >   target/avr/cpu-param.h |  37 ++
> >   target/avr/cpu-qom.h   |  54 +++
> >   target/avr/cpu.h   | 258 +
> >   target/avr/cpu.c   | 826 +
> >   target/avr/gdbstub.c   |  84 +
> >   target/avr/machine.c   | 121 ++
> >   gdb-xml/avr-cpu.xml|  49 +++
> >   7 files changed, 1429 insertions(+)
> >   create mode 100644 target/avr/cpu-param.h
> >   create mode 100644 target/avr/cpu-qom.h
> >   create mode 100644 target/avr/cpu.h
> >   create mode 100644 target/avr/cpu.c
> >   create mode 100644 target/avr/gdbstub.c
> >   create mode 100644 target/avr/machine.c
> >   create mode 100644 gdb-xml/avr-cpu.xml
> >
> [...]> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> > new file mode 100644
> > index 00..c74c5106fe
> > --- /dev/null
> > +++ b/target/avr/cpu.c
> > @@ -0,0 +1,826 @@
> > +/*
> > + * QEMU AVR CPU
> > + *
> > + * Copyright (c) 2019 Michael Rolnik
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see
> > + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "qemu/qemu-print.h"
> > +#include "exec/exec-all.h"
> > +#include "cpu.h"
> > +#include "disas/dis-asm.h"
> > +
> > +static void avr_cpu_set_pc(CPUState *cs, vaddr value)
> > +{
> > +AVRCPU *cpu = AVR_CPU(cs);
> > +
> > +cpu->env.pc_w = value / 2; /* internally PC points to words */
> > +}
> > +
> > +static bool avr_cpu_has_work(CPUState *cs)
> > +{
> > +AVRCPU *cpu = AVR_CPU(cs);
> > +CPUAVRState *env = >env;
> > +
> > +return (cs->interrupt_request & (CPU_INTERRUPT_HARD |
> CPU_INTERRUPT_RESET))
> > +&& cpu_interrupts_enabled(env);
> > +}
> > +
> > +static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock
> *tb)
> > +{
> > +AVRCPU *cpu = AVR_CPU(cs);
> > +CPUAVRState *env = >env;
> > +
> > +env->pc_w = tb->pc / 2; /* internally PC points to words */
> > +}
> > +
> > +static void avr_cpu_reset(CPUState *cs)
> > +{
> > +AVRCPU *cpu = AVR_CPU(cs);
> > +AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
> > +CPUAVRState *env = >env;
> > +
> > +mcc->parent_reset(cs);
> > +
> > +env->pc_w = 0;
> > +env->sregI = 1;
> > +env->sregC = 0;
> > +env->sregZ = 0;
> > +env->sregN = 0;
> > +env->sregV = 0;
> > +env->sregS = 0;
> > +env->sregH = 0;
> > +env->sregT = 0;
> > +
> > +env->rampD = 0;
> > +env->rampX = 0;
> > +env->rampY = 0;
> > +env->rampZ = 0;
> > +env->eind = 0;
> > +env->sp = 0;
> > +
> > +env->skip = 0;
> > +
> > +memset(env->r, 0, sizeof(env->r));
> > +
> > +tlb_flush(cs);
>
> Why are you calling tlb_flush() here?
>
> > +}
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

[Michael Rolnik]

Hi all.

are there any action items for me?

Regards,
Michael Rolnik

On Thu, Feb 27, 2020 at 10:38 AM Michael Rolnik  wrote:

> Hi all.
>
> I don't see how the fact that some MCUs have an instruction and some don't
> within same AVR family.
> Think about gnu binutils (not GCC) these utils have no idea about MCUs all
> they are aware of AVR CPU only.
> However, I don't mind removing -cpu flag.
>
> Regards,
> Michael Ronik
>
> On Fri, Feb 21, 2020 at 5:31 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>> On Fri, Feb 21, 2020 at 12:04 PM Michael Rolnik 
>> wrote:
>> >
>> > Hi all.
>> >
>> > How is it going?
>> >
>> > Regards,
>> > Michael.
>> >
>>
>> Michael,
>>
>> I think we are very close to merging.
>>
>> There is absolutely no need to support ALL AVR mcus or AVR core types
>> in the first version that will be merged.
>>
>> But this issue (recently discovered during Jaoquin's review) about the
>> fact that an avr core type doesn't determine in a complete way the
>> instruction set of a particular MCU is thorny.
>>
>> Should we switch from "-cpu " to "-cpu " (but keep
>> the current avr core type organization for internal purpose)? Or
>> something else?
>>
>> This is a high-level AVR suppot design issue. Let's think about it
>> without a rush.
>>
>> The problem is that once one organization/meaning of that switch is
>> upstreamed, it is very difficult to switch to other. There is a
>> procedural rule that deprecation process lasts at least 8 months, plus
>> there may be some technical obstacles and difficulties.
>>
>> In short, "-cpu " is not enough to emulate accurately a
>> givem program.
>>
>> Regards,
>> Aleksandar
>>
>> > On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik 
>> wrote:
>> >>
>> >> Hi all.
>> >>
>> >> When I decided to implement AVR 8 bit CPU support for QEMU I found
>> this document which listed all AVR instructions.
>> >> After that I learned that there are several CPU flavours, I looked
>> into this GCC file to figure out what are they as I could not find any
>> official document explaining it.
>> >> Then I downloaded several datasheets and created a list of
>> instructions by CPU type (attached).It turned out that there are some
>> variations
>> >> e.g.
>> >> - AVTTINY - some have LDS, some don't
>> >> - AVR1, AVR25 - some have short SP, some don't
>> >> - AVRXMEGA2, AVRXMEGA4, AVRXMEGA5, AVRXMEGA6, AVRXMEGA7 - some have
>> RMW, some don't
>> >> - AVRXMEGA3 - some have RCALL, some don't
>> >>
>> >> I decided to leave CPU flavour definition as suggested by GCC
>> gcc/config/avr/avr-devices.c file and when a specific MCU is created it
>> will set / reset CPU features relevant to it.
>> >>
>> >> I hope this helps.
>> >>
>> >> Best Regards,
>> >> Michael Rolnik
>> >>
>> >>
>> >>
>> >>
>> >>
>> >>
>> >>
>> >> On Sat, Feb 8, 2020 at 9:35 AM Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>> >>>
>> >>>
>> >>>
>> >>> On Sunday, February 2, 2020, Joaquin de Andres <
>> m...@xcancerberox.com.ar> wrote:
>> >>>>
>> >>>> On 1/31/20 1:02 AM, Aleksandar Markovic wrote:
>> >>>>>
>> >>>>> From: Michael Rolnik 
>> >>>>>
>> >>>>> AVR core types are:
>> >>>>>
>> >>>>>- avr1
>> >>>>>- avr2
>> >>>>>- avr25
>> >>>>>- avr3
>> >>>>>- avr31
>> >>>>>- avr35
>> >>>>>- avr4
>> >>>>>- avr5
>> >>>>>- avr51
>> >>>>>- avr6
>> >>>>>- avrtiny
>> >>>>>- xmega2
>> >>>>>- xmega3
>> >>>>>- xmega4
>> >>>>>- xmega5
>> >>>>>- xmega6
>> >>>>>- xmega7
>> >>>>>
>> >>>>> Each core type covers multiple AVR MCUs, mentioned in the comments
>> >>>>> before definition of particular AVR core type (part of 

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

[Michael Rolnik]

Hi all.

I don't see how the fact that some MCUs have an instruction and some don't
within same AVR family.
Think about gnu binutils (not GCC) these utils have no idea about MCUs all
they are aware of AVR CPU only.
However, I don't mind removing -cpu flag.

Regards,
Michael Ronik

On Fri, Feb 21, 2020 at 5:31 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:

> On Fri, Feb 21, 2020 at 12:04 PM Michael Rolnik  wrote:
> >
> > Hi all.
> >
> > How is it going?
> >
> > Regards,
> > Michael.
> >
>
> Michael,
>
> I think we are very close to merging.
>
> There is absolutely no need to support ALL AVR mcus or AVR core types
> in the first version that will be merged.
>
> But this issue (recently discovered during Jaoquin's review) about the
> fact that an avr core type doesn't determine in a complete way the
> instruction set of a particular MCU is thorny.
>
> Should we switch from "-cpu " to "-cpu " (but keep
> the current avr core type organization for internal purpose)? Or
> something else?
>
> This is a high-level AVR suppot design issue. Let's think about it
> without a rush.
>
> The problem is that once one organization/meaning of that switch is
> upstreamed, it is very difficult to switch to other. There is a
> procedural rule that deprecation process lasts at least 8 months, plus
> there may be some technical obstacles and difficulties.
>
> In short, "-cpu " is not enough to emulate accurately a
> givem program.
>
> Regards,
> Aleksandar
>
> > On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik 
> wrote:
> >>
> >> Hi all.
> >>
> >> When I decided to implement AVR 8 bit CPU support for QEMU I found this
> document which listed all AVR instructions.
> >> After that I learned that there are several CPU flavours, I looked into
> this GCC file to figure out what are they as I could not find any official
> document explaining it.
> >> Then I downloaded several datasheets and created a list of instructions
> by CPU type (attached).It turned out that there are some variations
> >> e.g.
> >> - AVTTINY - some have LDS, some don't
> >> - AVR1, AVR25 - some have short SP, some don't
> >> - AVRXMEGA2, AVRXMEGA4, AVRXMEGA5, AVRXMEGA6, AVRXMEGA7 - some have
> RMW, some don't
> >> - AVRXMEGA3 - some have RCALL, some don't
> >>
> >> I decided to leave CPU flavour definition as suggested by GCC
> gcc/config/avr/avr-devices.c file and when a specific MCU is created it
> will set / reset CPU features relevant to it.
> >>
> >> I hope this helps.
> >>
> >> Best Regards,
> >> Michael Rolnik
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >> On Sat, Feb 8, 2020 at 9:35 AM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
> >>>
> >>>
> >>>
> >>> On Sunday, February 2, 2020, Joaquin de Andres 
> wrote:
> >>>>
> >>>> On 1/31/20 1:02 AM, Aleksandar Markovic wrote:
> >>>>>
> >>>>> From: Michael Rolnik 
> >>>>>
> >>>>> AVR core types are:
> >>>>>
> >>>>>- avr1
> >>>>>- avr2
> >>>>>- avr25
> >>>>>    - avr3
> >>>>>- avr31
> >>>>>- avr35
> >>>>>- avr4
> >>>>>- avr5
> >>>>>- avr51
> >>>>>- avr6
> >>>>>- avrtiny
> >>>>>- xmega2
> >>>>>- xmega3
> >>>>>- xmega4
> >>>>>- xmega5
> >>>>>- xmega6
> >>>>>- xmega7
> >>>>>
> >>>>> Each core type covers multiple AVR MCUs, mentioned in the comments
> >>>>> before definition of particular AVR core type (part of this patch).
> >>>>>
> >>>>> AVR core type defines shared features that are valid for all AVR
> >>>>> MCUs belonging in that type.
> >>>>>
> >>>>> [AM: Split a larger AVR introduction patch into logical units]
> >>>>> Suggested-by: Aleksandar Markovic 
> >>>>>
> >>>>> Co-developed-by: Michael Rolnik 
> >>>>> Co-developed-by: Sarah Harris 
> >>>>> Signed-off-by: Michael Rolnik 
> >>>>> Signed-off-by: Sarah Harris 
> >>>>> S

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

[Michael Rolnik]

Hi all.

How is it going?

Regards,
Michael.

On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik  wrote:

> Hi all.
>
> When I decided to implement AVR 8 bit CPU support for QEMU I found this
> document
> <http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf>
>  which
> listed all AVR instructions.
> After that I learned that there are several CPU flavours, I looked into
> this GCC file
> <https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c> 
> to
> figure out what are they as I could not find any official document
> explaining it.
> Then I downloaded several datasheets and created a list of instructions by
> CPU type (attached).It turned out that there are some variations
> e.g.
> - AVTTINY - some have LDS, some don't
> - AVR1, AVR25 - some have short SP, some don't
> - AVRXMEGA2, AVRXMEGA4, AVRXMEGA5, AVRXMEGA6, AVRXMEGA7 - some have RMW,
> some don't
> - AVRXMEGA3 - some have RCALL, some don't
>
> I decided to leave CPU flavour definition as suggested by GCC
> gcc/config/avr/avr-devices.c
> <https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c>
> file and when a specific MCU is created it will set / reset CPU features
> relevant to it.
>
> I hope this helps.
>
> Best Regards,
> Michael Rolnik
>
>
>
>
>
>
>
> On Sat, Feb 8, 2020 at 9:35 AM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Sunday, February 2, 2020, Joaquin de Andres 
>> wrote:
>>
>>> On 1/31/20 1:02 AM, Aleksandar Markovic wrote:
>>>
>>>> From: Michael Rolnik 
>>>>
>>>> AVR core types are:
>>>>
>>>>- avr1
>>>>- avr2
>>>>- avr25
>>>>- avr3
>>>>- avr31
>>>>- avr35
>>>>- avr4
>>>>- avr5
>>>>- avr51
>>>>- avr6
>>>>- avrtiny
>>>>- xmega2
>>>>- xmega3
>>>>- xmega4
>>>>- xmega5
>>>>- xmega6
>>>>- xmega7
>>>>
>>>> Each core type covers multiple AVR MCUs, mentioned in the comments
>>>> before definition of particular AVR core type (part of this patch).
>>>>
>>>> AVR core type defines shared features that are valid for all AVR
>>>> MCUs belonging in that type.
>>>>
>>>> [AM: Split a larger AVR introduction patch into logical units]
>>>> Suggested-by: Aleksandar Markovic 
>>>>
>>>> Co-developed-by: Michael Rolnik 
>>>> Co-developed-by: Sarah Harris 
>>>> Signed-off-by: Michael Rolnik 
>>>> Signed-off-by: Sarah Harris 
>>>> Signed-off-by: Michael Rolnik 
>>>> Acked-by: Igor Mammedov 
>>>> Tested-by: Philippe Mathieu-Daudé 
>>>> Signed-off-by: Richard Henderson 
>>>> Signed-off-by: Aleksandar Markovic 
>>>> ---
>>>>   target/avr/cpu.c | 601
>>>> +++
>>>>   1 file changed, 601 insertions(+)
>>>>
>>>> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
>>>> index f41a887..e0ae055 100644
>>>> --- a/target/avr/cpu.c
>>>> +++ b/target/avr/cpu.c
>>>> @@ -215,3 +215,604 @@ static void avr_cpu_class_init(ObjectClass *oc,
>>>> void *data)
>>>>   cc->gdb_num_core_regs = 35;
>>>>   cc->gdb_core_xml_file = "avr-cpu.xml";
>>>>   }
>>>> +
>>>> +/*
>>>> + * Setting features of AVR core type avr1
>>>> + * --
>>>> + *
>>>> + * This type of AVR core is present in the following AVR MCUs:
>>>> + *
>>>> + * at90s1200, attiny11, attiny12, attiny15, attiny28
>>>> + */
>>>> +static void avr_avr1_initfn(Object *obj)
>>>> +{
>>>> +AVRCPU *cpu = AVR_CPU(obj);
>>>> +CPUAVRState *env = >env;
>>>> +
>>>> +set_avr_feature(env, AVR_FEATURE_LPM);
>>>> +set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
>>>> +set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
>>>> +}
>>>> +
>>>> +/*
>>>> + * Setting features of AVR core type avr2
>>>> + * --
>>>> + *
>>>> + * This type of AVR core is present in the following AVR MCUs:
>>>> + *
>&

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

[Michael Rolnik]

Hi all.

When I decided to implement AVR 8 bit CPU support for QEMU I found this
document
<http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf>
which
listed all AVR instructions.
After that I learned that there are several CPU flavours, I looked into
this GCC file
<https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c> to
figure out what are they as I could not find any official document
explaining it.
Then I downloaded several datasheets and created a list of instructions by
CPU type (attached).It turned out that there are some variations
e.g.
- AVTTINY - some have LDS, some don't
- AVR1, AVR25 - some have short SP, some don't
- AVRXMEGA2, AVRXMEGA4, AVRXMEGA5, AVRXMEGA6, AVRXMEGA7 - some have RMW,
some don't
- AVRXMEGA3 - some have RCALL, some don't

I decided to leave CPU flavour definition as suggested by GCC
gcc/config/avr/avr-devices.c
<https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c>
file and when a specific MCU is created it will set / reset CPU features
relevant to it.

I hope this helps.

Best Regards,
Michael Rolnik







On Sat, Feb 8, 2020 at 9:35 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:

>
>
> On Sunday, February 2, 2020, Joaquin de Andres 
> wrote:
>
>> On 1/31/20 1:02 AM, Aleksandar Markovic wrote:
>>
>>> From: Michael Rolnik 
>>>
>>> AVR core types are:
>>>
>>>- avr1
>>>- avr2
>>>- avr25
>>>- avr3
>>>- avr31
>>>- avr35
>>>- avr4
>>>- avr5
>>>- avr51
>>>- avr6
>>>- avrtiny
>>>- xmega2
>>>- xmega3
>>>- xmega4
>>>- xmega5
>>>- xmega6
>>>- xmega7
>>>
>>> Each core type covers multiple AVR MCUs, mentioned in the comments
>>> before definition of particular AVR core type (part of this patch).
>>>
>>> AVR core type defines shared features that are valid for all AVR
>>> MCUs belonging in that type.
>>>
>>> [AM: Split a larger AVR introduction patch into logical units]
>>> Suggested-by: Aleksandar Markovic 
>>>
>>> Co-developed-by: Michael Rolnik 
>>> Co-developed-by: Sarah Harris 
>>> Signed-off-by: Michael Rolnik 
>>> Signed-off-by: Sarah Harris 
>>> Signed-off-by: Michael Rolnik 
>>> Acked-by: Igor Mammedov 
>>> Tested-by: Philippe Mathieu-Daudé 
>>> Signed-off-by: Richard Henderson 
>>> Signed-off-by: Aleksandar Markovic 
>>> ---
>>>   target/avr/cpu.c | 601
>>> +++
>>>   1 file changed, 601 insertions(+)
>>>
>>> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
>>> index f41a887..e0ae055 100644
>>> --- a/target/avr/cpu.c
>>> +++ b/target/avr/cpu.c
>>> @@ -215,3 +215,604 @@ static void avr_cpu_class_init(ObjectClass *oc,
>>> void *data)
>>>   cc->gdb_num_core_regs = 35;
>>>   cc->gdb_core_xml_file = "avr-cpu.xml";
>>>   }
>>> +
>>> +/*
>>> + * Setting features of AVR core type avr1
>>> + * --
>>> + *
>>> + * This type of AVR core is present in the following AVR MCUs:
>>> + *
>>> + * at90s1200, attiny11, attiny12, attiny15, attiny28
>>> + */
>>> +static void avr_avr1_initfn(Object *obj)
>>> +{
>>> +AVRCPU *cpu = AVR_CPU(obj);
>>> +CPUAVRState *env = >env;
>>> +
>>> +set_avr_feature(env, AVR_FEATURE_LPM);
>>> +set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
>>> +set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
>>> +}
>>> +
>>> +/*
>>> + * Setting features of AVR core type avr2
>>> + * --
>>> + *
>>> + * This type of AVR core is present in the following AVR MCUs:
>>> + *
>>> + * at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26,
>>> at90s4414,
>>> + * at90s4433, at90s4434, at90s8515, at90c8534, at90s8535
>>> + */
>>> +static void avr_avr2_initfn(Object *obj)
>>> +{
>>> +AVRCPU *cpu = AVR_CPU(obj);
>>> +CPUAVRState *env = >env;
>>> +
>>> +set_avr_feature(env, AVR_FEATURE_LPM);
>>> +set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
>>> +set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
>>> +set_avr_feature(env, AVR_FEATURE_SRAM);
>>> +set_avr_f

Re: [PATCH rc5 01/32] target/avr: Add basic parameters of the new platform

[Michael Rolnik]

Tested-by: Michael Rolnik 

On Fri, Feb 7, 2020 at 3:58 AM Aleksandar Markovic <
aleksandar.marko...@rt-rk.com> wrote:

> From: Michael Rolnik 
>
> This includes definitions of various basic parameters needed
> for integration of a new platform into QEMU.
>
> [AM: Split a larger AVR introduction patch into logical units]
> Suggested-by: Aleksandar Markovic 
> Co-developed-by: Michael Rolnik 
> Co-developed-by: Sarah Harris 
> Signed-off-by: Michael Rolnik 
> Signed-off-by: Sarah Harris 
> Signed-off-by: Richard Henderson 
> Signed-off-by: Aleksandar Markovic 
> Acked-by: Igor Mammedov 
> Tested-by: Philippe Mathieu-Daudé 
> ---
>  target/avr/cpu-param.h | 37 
>  target/avr/cpu.h   | 66
> ++
>  MAINTAINERS|  7 ++
>  3 files changed, 110 insertions(+)
>  create mode 100644 target/avr/cpu-param.h
>  create mode 100644 target/avr/cpu.h
>
> diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
> new file mode 100644
> index 000..0c29ce4
> --- /dev/null
> +++ b/target/avr/cpu-param.h
> @@ -0,0 +1,37 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#ifndef AVR_CPU_PARAM_H
> +#define AVR_CPU_PARAM_H
> +
> +#define TARGET_LONG_BITS 32
> +/*
> + * TARGET_PAGE_BITS cannot be more than 8 bits because
> + * 1.  all IO registers occupy [0x .. 0x00ff] address range, and they
> + * should be implemented as a device and not memory
> + * 2.  SRAM starts at the address 0x0100
> + */
> +#define TARGET_PAGE_BITS 8
> +#define TARGET_PHYS_ADDR_SPACE_BITS 24
> +#define TARGET_VIRT_ADDR_SPACE_BITS 24
> +#define NB_MMU_MODES 2
> +
> +
> +#endif
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> new file mode 100644
> index 000..ecdeafb
> --- /dev/null
> +++ b/target/avr/cpu.h
> @@ -0,0 +1,66 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#ifndef QEMU_AVR_CPU_H
> +#define QEMU_AVR_CPU_H
> +
> +#include "exec/cpu-defs.h"
> +
> +#define TCG_GUEST_DEFAULT_MO 0
> +
> +/*
> + * AVR has two memory spaces, data & code.
> + * e.g. both have 0 address
> + * ST/LD instructions access data space
> + * LPM/SPM and instruction fetching access code memory space
> + */
> +#define MMU_CODE_IDX 0
> +#define MMU_DATA_IDX 1
> +
> +#define EXCP_RESET 1
> +#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
> +
> +/* Number of CPU registers */
> +#define NUMBER_OF_CPU_REGISTERS 32
> +/* Number of IO registers accessible by ld/st/in/out */
> +#define NUMBER_OF_IO_REGISTERS 64
> +
> +/*
> + * Offsets of AVR memory regions in host memory space.
> + *
> + * This is needed because the AVR has separate code and data address
> + * spaces that both have start from zero but have to go somewhere in
> + * host memory.
> + *
> + * It's also useful to know where some things are, like the IO registers.
> + */
> +/* Flash program memory */
> +#define OFFSET_CODE 0x
> +/* CPU registers, IO registers, and SRAM */
> +#define OFFSET_DATA 0x0080
> +/* CPU registers specifically, these are mapped at the start of data */
>

Re: [PATCH rc4 00/29] target/avr merger

[Michael Rolnik]

Looks good. Thanks

On Fri, Jan 31, 2020 at 3:24 AM Philippe Mathieu-Daudé 
wrote:

> On 1/31/20 1:12 AM, Aleksandar Markovic wrote:
> > Michael, Philippe,
> >
> > Can you guys do a quick checkup of this rc4? rc4, rc3,and rc2 should
> > be functionally 100% equivalent.
>
> Tested OK.
>
> git-backport-diff with rc2:
>
> Key:
> [] : patches are identical
> [] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/31:[down] 'target/avr: Add basic parameters for new AVR platform'
> 002/31:[down] 'target/avr: Introduce AVR CPU class object'
> 003/31:[down] 'target/avr: Add migration support'
> 004/31:[down] 'target/avr: Add GDB support'
> 005/31:[down] 'target/avr: Introduce enumeration AVRFeature'
> 006/31:[down] 'target/avr: Add defintions of AVR core types'
> 007/31:[0148] [FC] 'target/avr: Add instruction helpers'
> 008/31:[down] 'target/avr: Add instruction translation - Register
> definitions'
> 009/31:[] [--] 'target/avr: Add instruction translation - Arithmetic
> and Logic Instructions'
> 010/31:[] [--] 'target/avr: Add instruction translation - Branch
> Instructions'
> 011/31:[] [--] 'target/avr: Add instruction translation - Data
> Transfer Instructions'
> 012/31:[] [--] 'target/avr: Add instruction translation - Bit and
> Bit-test Instructions'
> 013/31:[] [--] 'target/avr: Add instruction translation - MCU
> Control Instructions'
> 014/31:[] [--] 'target/avr: Add instruction translation - CPU main
> translation function'
> 015/31:[] [--] 'target/avr: Add instruction disassembly function'
> 016/31:[down] 'hw/char: Add limited support for AVR USART peripheral'
> 017/31:[down] 'hw/timer: Add limited support for AVR 16-bit timer
> peripheral'
> 018/31:[down] 'hw/misc: Add limited support for AVR power device'
> 019/31:[0012] [FC] 'target/avr: Add section about AVR into QEMU
> documentation'
> 020/31:[0002] [FC] 'target/avr: Register AVR support with the rest of QEMU'
> 021/31:[] [--] 'target/avr: Add machine none test'
> 022/31:[0014] [FC] 'target/avr: Update MAINTAINERS file'
> 023/31:[0002] [FC] 'hw/avr: Add helper to load raw/ELF firmware binaries'
> 024/31:[0026] [FC] 'hw/avr: Add some ATmega microcontrollers'
> 025/31:[0009] [FC] 'hw/avr: Add some Arduino boards'
> 026/31:[] [--] 'target/avr: Update build system'
> 027/31:[] [--] 'tests/boot-serial-test: Test some Arduino boards
> (AVR based)'
> 028/31:[] [--] 'tests/acceptance: Test the Arduino MEGA2560 board'
> 029/31:[] [--] '.travis.yml: Run the AVR acceptance tests'
> 030/31:[down] '!fixup "hw/misc: Add limited support for AVR power device"'
> 031/31:[down] '!fixup "hw/timer: Add limited support for AVR 16-bit
> timer peripheral"'
>
> One thing that annoys me is we ignored the review comments from Joaquin,
> but I think it might now be easier to address them as new patches, once
> this series is merged.
>
> I made 2 comments (definitions in incorrect patch, and definition
> misplaced in elf.h), and sent 2 patches converting the PRINTF() to
> trace-events. Thanks for preparing the rc4, hopefully we are done!
>
> >
> > Thank you,
> > Aleksandar
> >
> > On Fri, Jan 31, 2020 at 1:06 AM Aleksandar Markovic
> >  wrote:
> >>
> >> From: Aleksandar Markovic 
> >>
> >> This is the AVR port from Michael, release (merge) candidate 4.
> >>
> >> The series can be found also in this repository:
> >>
> >> https://github.com/AMarkovic/qemu-avr-merger-rc4
> >>
> >> History:
> >>
> >> Since v3:
> >>
> >> - Removed a patch on load_elf() modification, since it has been merged
> >> - Removed references to CONFIG_USER_ONLY and provided a guard against
> >>building lunux user mode for AVR
> >> - Removed all references to 'Atmel' (including file renames)
> >> - Rebased the code (there was common interface change regarding 'props')
> >> - Various corrections of commit messages
> >> - A bit field for AVRFeatures is nor 64 bit long
> >> - Other minor fixes
> >>
> >> Since v2:
> >>
> >> - First patch is split into six smaller logical units (net result
> >>remains the same)
> >> - Patch "hw/core/loader: Let load_elf populate the processor-specific
> >>flags" was redone to reflect the original intent that was lost in
> >>transalation between multiple autors
> >> - Patch "hw/avr: Add helper to load raw/ELF firmwar

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

[Michael Rolnik]

Sounds good.

Sent from my cell phone, please ignore typos

On Wed, Jan 29, 2020, 5:12 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:

> On Wed, Jan 29, 2020 at 1:20 PM Sarah Harris  wrote:
> >
> > Hi,
> >
> > I think I've found a minor bug: the stack pointer should be initialised
> to the size of SRAM in some or most cases.
> > Currently, SP is initialised to zero.
> >
>
> Very good (that you spotted the bug)!
>
> > It seems modern AVRs set SP to the size of SRAM (RAMEND) at power-on,
> though a few older ones initialise to zero.
> > The ATmega328 (from 2009) [1], ATmega2560 (from 2005) [2], ATtiny2313
> (from 2003) [6], and ATtiny85 (from 2005) [3] all use RAMEND.
> > The ATmega8 (from 2001) [4], ATmega8535 (from 2002) [5], and AT90S8535
> (from 1998) [7] use zero.
>
> It looks we'll have tremendous "fun" dealing with huge variety of AVR SoCs.
>
> > I haven't found a list of which AVRs use which value (other than reading
> every datasheet).
>
> Yes, I find this to be a big practical problem, this glaring lack of
> some summary documentation, and, unfortunately, this affects not only
> this particular case (SP initialization). It appears to me that for
> many features and details (especially regarding SoC devices) one will
> have to carefully examine multiple documents, as you did in this
> email.
>
> >
> > Given that GCC performs this initialisation in software anyway (so what
> the hardware does doesn't matter), I think this is a minor issue.
> > It will only affect hand written assembly programs that don't do their
> own initialisation (which seems to be discouraged as not all resets are
> power-on events).
> > I'm not sure what, if anything, needs to be done about it but it might
> be worth fixing now we're emulating specific chips.
> >
>
> Let's think a little bit about it. In my honest opinion, this may be
> handled after the series merge, and if you guys agree, there is no
> rush.
>
> > Kind regards,
> > Sarah Harris
> >
>
> Thanks!
> Aleksandar
>
> > [1]
> http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-7810-Automotive-Microcontrollers-ATmega328P_Datasheet.pdf
> (section 6.5.1)
> > [2]
> http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf
> (section 7.6)
> > [3]
> http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2586-AVR-8-bit-Microcontroller-ATtiny25-ATtiny45-ATtiny85_Datasheet.pdf
> (section 4.6.1)
> > [4]
> http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2486-8-bit-AVR-microcontroller-ATmega8_L_datasheet.pdf
> (page 13)
> > [5] http://ww1.microchip.com/downloads/en/DeviceDoc/doc2502.pdf (page
> 12)
> > [6]
> http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2543-AVR-ATtiny2313_Datasheet.pdf
> (page 11)
> > [7] http://ww1.microchip.com/downloads/en/DeviceDoc/doc1041.pdf (page
> 20)
> >
> > On Sun, 26 Jan 2020 23:54:43 +0100
> > Aleksandar Markovic  wrote:
> >
> > > +static void avr_cpu_reset(CPUState *cs)
> > > +{
> > > +AVRCPU *cpu = AVR_CPU(cs);
> > > +AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
> > > +CPUAVRState *env = >env;
> > > +
> > > +mcc->parent_reset(cs);
> > > +
> > > +env->pc_w = 0;
> > > +env->sregI = 1;
> > > +env->sregC = 0;
> > > +env->sregZ = 0;
> > > +env->sregN = 0;
> > > +env->sregV = 0;
> > > +env->sregS = 0;
> > > +env->sregH = 0;
> > > +env->sregT = 0;
> > > +
> > > +env->rampD = 0;
> > > +env->rampX = 0;
> > > +env->rampY = 0;
> > > +env->rampZ = 0;
> > > +env->eind = 0;
> > > +env->sp = 0;
> > > +
> > > +env->skip = 0;
> > > +
> > > +memset(env->r, 0, sizeof(env->r));
> > > +
> > > +tlb_flush(cs);
> > > +}
>

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

[Michael Rolnik]

Sounds good to me.

On Tue, Jan 28, 2020 at 3:49 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:

>
>
> On Tuesday, January 28, 2020, Michael Rolnik  wrote:
>
>> Hi all.
>>
>> I am totally lost in the email.
>> Are there any action items for me / someone else ?
>>
>> Regards,
>> Michael Rolnik
>>
>>
> I think it would be helpful if we have rc4 with two action items:
>
>- remove CONFIG_USER_ONLY references, and all dead code thay may have
> come with it + add check in cpu.h that Philippe suggested.
>- remove "Atmel" word from all elements of the series (patch names,
> messages, filenames, structure names, ...)
>
> Needless to say that this must be done with extreme care.
>
> I propose that Philippe do rc4.
>
> Sincerely,
> Aleksandar
>
>
>
>>
>> On Mon, Jan 27, 2020 at 10:54 AM Michael Rolnik 
>> wrote:
>>
>>> Thanks for you help guys.
>>>
>>> On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic <
>>> aleksandar.marko...@rt-rk.com> wrote:
>>>
>>>> From: Michael Rolnik 
>>>>
>>>> This includes definitions of various basic parameters needed
>>>> for integration of a new platform into QEMU.
>>>>
>>>> Co-developed-by: Michael Rolnik 
>>>> Co-developed-by: Sarah Harris 
>>>> Signed-off-by: Michael Rolnik 
>>>> Signed-off-by: Sarah Harris 
>>>> Signed-off-by: Michael Rolnik 
>>>> Acked-by: Igor Mammedov 
>>>> Tested-by: Philippe Mathieu-Daudé 
>>>> Signed-off-by: Richard Henderson 
>>>> Signed-off-by: Aleksandar Markovic 
>>>> ---
>>>>  target/avr/cpu-param.h | 37 ++
>>>>  target/avr/cpu.h   | 72
>>>> ++++++++++
>>>>  2 files changed, 109 insertions(+)
>>>>  create mode 100644 target/avr/cpu-param.h
>>>>  create mode 100644 target/avr/cpu.h
>>>>
>>>> diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
>>>> new file mode 100644
>>>> index 000..0c29ce4
>>>> --- /dev/null
>>>> +++ b/target/avr/cpu-param.h
>>>> @@ -0,0 +1,37 @@
>>>> +/*
>>>> + * QEMU AVR CPU
>>>> + *
>>>> + * Copyright (c) 2019 Michael Rolnik
>>>> + *
>>>> + * This library is free software; you can redistribute it and/or
>>>> + * modify it under the terms of the GNU Lesser General Public
>>>> + * License as published by the Free Software Foundation; either
>>>> + * version 2.1 of the License, or (at your option) any later version.
>>>> + *
>>>> + * This library is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>>>> + * Lesser General Public License for more details.
>>>> + *
>>>> + * You should have received a copy of the GNU Lesser General Public
>>>> + * License along with this library; if not, see
>>>> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
>>>> + */
>>>> +
>>>> +#ifndef AVR_CPU_PARAM_H
>>>> +#define AVR_CPU_PARAM_H
>>>> +
>>>> +#define TARGET_LONG_BITS 32
>>>> +/*
>>>> + * TARGET_PAGE_BITS cannot be more than 8 bits because
>>>> + * 1.  all IO registers occupy [0x .. 0x00ff] address range, and
>>>> they
>>>> + * should be implemented as a device and not memory
>>>> + * 2.  SRAM starts at the address 0x0100
>>>> + */
>>>> +#define TARGET_PAGE_BITS 8
>>>> +#define TARGET_PHYS_ADDR_SPACE_BITS 24
>>>> +#define TARGET_VIRT_ADDR_SPACE_BITS 24
>>>> +#define NB_MMU_MODES 2
>>>> +
>>>> +
>>>> +#endif
>>>> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
>>>> new file mode 100644
>>>> index 000..d122611
>>>> --- /dev/null
>>>> +++ b/target/avr/cpu.h
>>>> @@ -0,0 +1,72 @@
>>>> +/*
>>>> + * QEMU AVR CPU
>>>> + *
>>>> + * Copyright (c) 2019 Michael Rolnik
>>>> + *
>>>> + * This library is free software; you can redistribute it and/or
>>>> + * modify it under the terms of the GNU Lesser General Public
>>>> + * License as published by t

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

[Michael Rolnik]

Hi all.

I am totally lost in the email.
Are there any action items for me / someone else ?

Regards,
Michael Rolnik


On Mon, Jan 27, 2020 at 10:54 AM Michael Rolnik  wrote:

> Thanks for you help guys.
>
> On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic <
> aleksandar.marko...@rt-rk.com> wrote:
>
>> From: Michael Rolnik 
>>
>> This includes definitions of various basic parameters needed
>> for integration of a new platform into QEMU.
>>
>> Co-developed-by: Michael Rolnik 
>> Co-developed-by: Sarah Harris 
>> Signed-off-by: Michael Rolnik 
>> Signed-off-by: Sarah Harris 
>> Signed-off-by: Michael Rolnik 
>> Acked-by: Igor Mammedov 
>> Tested-by: Philippe Mathieu-Daudé 
>> Signed-off-by: Richard Henderson 
>> Signed-off-by: Aleksandar Markovic 
>> ---
>>  target/avr/cpu-param.h | 37 ++
>>  target/avr/cpu.h   | 72
>> ++
>>  2 files changed, 109 insertions(+)
>>  create mode 100644 target/avr/cpu-param.h
>>  create mode 100644 target/avr/cpu.h
>>
>> diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
>> new file mode 100644
>> index 000..0c29ce4
>> --- /dev/null
>> +++ b/target/avr/cpu-param.h
>> @@ -0,0 +1,37 @@
>> +/*
>> + * QEMU AVR CPU
>> + *
>> + * Copyright (c) 2019 Michael Rolnik
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2.1 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see
>> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
>> + */
>> +
>> +#ifndef AVR_CPU_PARAM_H
>> +#define AVR_CPU_PARAM_H
>> +
>> +#define TARGET_LONG_BITS 32
>> +/*
>> + * TARGET_PAGE_BITS cannot be more than 8 bits because
>> + * 1.  all IO registers occupy [0x .. 0x00ff] address range, and they
>> + * should be implemented as a device and not memory
>> + * 2.  SRAM starts at the address 0x0100
>> + */
>> +#define TARGET_PAGE_BITS 8
>> +#define TARGET_PHYS_ADDR_SPACE_BITS 24
>> +#define TARGET_VIRT_ADDR_SPACE_BITS 24
>> +#define NB_MMU_MODES 2
>> +
>> +
>> +#endif
>> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
>> new file mode 100644
>> index 000..d122611
>> --- /dev/null
>> +++ b/target/avr/cpu.h
>> @@ -0,0 +1,72 @@
>> +/*
>> + * QEMU AVR CPU
>> + *
>> + * Copyright (c) 2019 Michael Rolnik
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2.1 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see
>> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
>> + */
>> +
>> +#ifndef QEMU_AVR_CPU_H
>> +#define QEMU_AVR_CPU_H
>> +
>> +#include "cpu-qom.h"
>> +#include "exec/cpu-defs.h"
>> +
>> +#define TCG_GUEST_DEFAULT_MO 0
>> +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
>> +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
>> +#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
>> +
>> +/*
>> + * AVR has two memory spaces, data & code.
>> + * e.g. both have 0 address
>> + * ST/LD instructions access data space
>> + * LPM/SPM and instruction fetching access code memory space
>> + */
>> +#define MMU_CODE_IDX 0
>> +#define MMU_DATA_IDX 1
>> +
>> +#define EXCP_RESET 1
>> +#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
>> +
>> +/* Number of CPU

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

Hi Joaquin.

I looks like that the CPU families are not well defined. There are some
small variations within the families themselves i.e. some MCUs do not
support all the features of their families.
To get the features I looked at this file in gcc
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c
Have a look here
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-mcus.def.
you can see that not all xmega support RMW instructions. so whenever QEMU
has atxmega128d4 implemented, atxmega128d4 model it will have to remove RMW
feature.

Regards,
Michael Rolnik

On Mon, Jan 27, 2020 at 3:27 PM Joaquin de Andres 
wrote:

> On 1/24/20 1:51 AM, Philippe Mathieu-Daudé wrote:
> > From: Michael Rolnik 
> >
> > This includes:
> > - CPU data structures
> > - object model classes and functions
> > - migration functions
> > - GDB hooks
> >
> > Co-developed-by: Michael Rolnik 
> > Co-developed-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Signed-off-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Acked-by: Igor Mammedov 
> > Tested-by: Philippe Mathieu-Daudé 
> > Message-Id: <20200118191416.19934-2-mrol...@gmail.com>
> > Signed-off-by: Richard Henderson 
> > ---
> > ...
> > diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> > new file mode 100644
> > index 00..c74c5106fe
> > --- /dev/null
> > +++ b/target/avr/cpu.c
> > @@ -0,0 +1,826 @@
> > ...
> > +/*
> > + * Setting features of AVR core type avr1
> > + * --
> > + *
> > + * This type of AVR core is present in the following AVR MCUs:
> > + *
> > + * at90s1200, attiny11, attiny12, attiny15, attiny28
> > + */
> > +static void avr_avr1_initfn(Object *obj)
> > +{
> > +AVRCPU *cpu = AVR_CPU(obj);
> > +CPUAVRState *env = >env;
> > +> +avr_set_feature(env, AVR_FEATURE_LPM);
>
> Hi! According to the datasheets the at90s1200 is an special case and the
> LPM instruction is not present.
>
> > +avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
>
> Ok. Checked with at90s1200 datasheet.
>
> > +}
> > +
> > +/*
> > + * Setting features of AVR core type avr2
> > + * --
> > + *
> > + * This type of AVR core is present in the following AVR MCUs:
> > + *
> > + * at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26,
> at90s4414,
> > + * at90s4433, at90s4434, at90s8515, at90c8534, at90s8535
> > + */
> > +static void avr_avr2_initfn(Object *obj)
> > +{
> > +AVRCPU *cpu = AVR_CPU(obj);
> > +CPUAVRState *env = >env;
> > +
> > +avr_set_feature(env, AVR_FEATURE_LPM);
>
> Ok. Checked with at90s2313 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
>
> Ok. Checked with at90s2313 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
>
> Ok. Checked with at90s2313 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_SRAM);
>
> Ok. Checked with at90s2313 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
>
> Ok. Checked with at90s2313 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +}
> > +
> > +/*
> > + * Setting features of AVR core type avr25
> > + * --
> > + *
> > + * This type of AVR core is present in the following AVR MCUs:
> > + *
> > + * ata5272, ata6616c, attiny13, attiny13a, attiny2313, attiny2313a,
> attiny24,
> > + * attiny24a, attiny4313, attiny44, attiny44a, attiny441, attiny84,
> attiny84a,
> > + * attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461,
> attiny461a,
> > + * attiny861, attiny861a, attiny43u, attiny87, attiny48, attiny88,
> attiny828,
> > + * attiny841, at86rf401
> > + */
> > +static void avr_avr25_initfn(Object *obj)
> > +{
> > +AVRCPU *cpu = AVR_CPU(obj);
> > +CPUAVRState *env = >env;
> > +
> > +avr_set_feature(env, AVR_FEATURE_LPM);
>
> Ok. Checked with attiny13 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
>
> Ok. Checked with attiny13 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
>
> Ok. Checked with attiny13 datasheet.
>
> > +avr_set_feature(env, AVR_FEATURE_SRAM);
>
> Ok. Checked with attiny13 datasheet.
>
> > +avr_set_feature(env, AVR_

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

[Michael Rolnik]

Thanks for you help guys.

On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic <
aleksandar.marko...@rt-rk.com> wrote:

> From: Michael Rolnik 
>
> This includes definitions of various basic parameters needed
> for integration of a new platform into QEMU.
>
> Co-developed-by: Michael Rolnik 
> Co-developed-by: Sarah Harris 
> Signed-off-by: Michael Rolnik 
> Signed-off-by: Sarah Harris 
> Signed-off-by: Michael Rolnik 
> Acked-by: Igor Mammedov 
> Tested-by: Philippe Mathieu-Daudé 
> Signed-off-by: Richard Henderson 
> Signed-off-by: Aleksandar Markovic 
> ---
>  target/avr/cpu-param.h | 37 ++
>  target/avr/cpu.h   | 72
> ++
>  2 files changed, 109 insertions(+)
>  create mode 100644 target/avr/cpu-param.h
>  create mode 100644 target/avr/cpu.h
>
> diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
> new file mode 100644
> index 000..0c29ce4
> --- /dev/null
> +++ b/target/avr/cpu-param.h
> @@ -0,0 +1,37 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#ifndef AVR_CPU_PARAM_H
> +#define AVR_CPU_PARAM_H
> +
> +#define TARGET_LONG_BITS 32
> +/*
> + * TARGET_PAGE_BITS cannot be more than 8 bits because
> + * 1.  all IO registers occupy [0x .. 0x00ff] address range, and they
> + * should be implemented as a device and not memory
> + * 2.  SRAM starts at the address 0x0100
> + */
> +#define TARGET_PAGE_BITS 8
> +#define TARGET_PHYS_ADDR_SPACE_BITS 24
> +#define TARGET_VIRT_ADDR_SPACE_BITS 24
> +#define NB_MMU_MODES 2
> +
> +
> +#endif
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> new file mode 100644
> index 000..d122611
> --- /dev/null
> +++ b/target/avr/cpu.h
> @@ -0,0 +1,72 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#ifndef QEMU_AVR_CPU_H
> +#define QEMU_AVR_CPU_H
> +
> +#include "cpu-qom.h"
> +#include "exec/cpu-defs.h"
> +
> +#define TCG_GUEST_DEFAULT_MO 0
> +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
> +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
> +#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
> +
> +/*
> + * AVR has two memory spaces, data & code.
> + * e.g. both have 0 address
> + * ST/LD instructions access data space
> + * LPM/SPM and instruction fetching access code memory space
> + */
> +#define MMU_CODE_IDX 0
> +#define MMU_DATA_IDX 1
> +
> +#define EXCP_RESET 1
> +#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
> +
> +/* Number of CPU registers */
> +#define NUMBER_OF_CPU_REGISTERS 32
> +/* Number of IO registers accessible by ld/st/in/out */
> +#define NUMBER_OF_IO_REGISTERS 64
> +
> +/*
> + * Offsets of AVR memory regions in host memory space.
> + *
> + * This is needed because the AVR has separate code and data address
> + * spaces that both have start from zero but have to go somewhere in
> + * host memory.
> + *
> + * It's also useful to know where some things are, like the IO registers.
> + */
> +/* Flash program memory */
> +#define OFFSET_CODE 0x
> +/* CPU registers, IO registers, and SRAM */
> +#define OFFSET_DATA 0

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

Hi Joaquin.

`AVR_FEATURE_1_BYTE_PC` is used in `gen_push_ret` function
(target/avr/translate.c)

Regards,
Michael Rolnik

On Sun, Jan 26, 2020 at 2:15 PM Joaquin de Andres 
wrote:

> Hi! In this mail I only checked the general code and one of the listed
> features for the different types of avr. I will check the rest in
> following emails.
>
> On 1/24/20 1:51 AM, Philippe Mathieu-Daudé wrote:
> > From: Michael Rolnik 
> >
> > This includes:
> > - CPU data structures
> > - object model classes and functions
> > - migration functions
> > - GDB hooks
> >
> > Co-developed-by: Michael Rolnik 
> > Co-developed-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Signed-off-by: Sarah Harris 
> > Signed-off-by: Michael Rolnik 
> > Acked-by: Igor Mammedov 
> > Tested-by: Philippe Mathieu-Daudé 
> > Message-Id: <20200118191416.19934-2-mrol...@gmail.com>
> > Signed-off-by: Richard Henderson 
> > ---
> >  target/avr/cpu-param.h |  37 ++
> >  target/avr/cpu-qom.h   |  54 +++
> >  target/avr/cpu.h   | 258 +
> >  target/avr/cpu.c   | 826 +
> >  target/avr/gdbstub.c   |  84 +
> >  target/avr/machine.c   | 121 ++
> >  gdb-xml/avr-cpu.xml|  49 +++
> >  7 files changed, 1429 insertions(+)
> >  create mode 100644 target/avr/cpu-param.h
> >  create mode 100644 target/avr/cpu-qom.h
> >  create mode 100644 target/avr/cpu.h
> >  create mode 100644 target/avr/cpu.c
> >  create mode 100644 target/avr/gdbstub.c
> >  create mode 100644 target/avr/machine.c
> >  create mode 100644 gdb-xml/avr-cpu.xml
> >
> > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
> > new file mode 100644
> > index 00..0c29ce4223
> > --- /dev/null
> > +++ b/target/avr/cpu-param.h
> > @@ -0,0 +1,37 @@
> > +/*
> > + * QEMU AVR CPU
> > + *
> > + * Copyright (c) 2019 Michael Rolnik
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see
> > + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> > + */
> > +
> > +#ifndef AVR_CPU_PARAM_H
> > +#define AVR_CPU_PARAM_H
> > +
> > +#define TARGET_LONG_BITS 32
> > +/*
> > + * TARGET_PAGE_BITS cannot be more than 8 bits because
> > + * 1.  all IO registers occupy [0x .. 0x00ff] address range, and
> they
> > + * should be implemented as a device and not memory
> > + * 2.  SRAM starts at the address 0x0100
> > + */
> > +#define TARGET_PAGE_BITS 8
> > +#define TARGET_PHYS_ADDR_SPACE_BITS 24
> > +#define TARGET_VIRT_ADDR_SPACE_BITS 24
> > +#define NB_MMU_MODES 2
> > +
> > +
> > +#endif
> > diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
> > new file mode 100644
> > index 00..e28b58c897
> > --- /dev/null
> > +++ b/target/avr/cpu-qom.h
> > @@ -0,0 +1,54 @@
> > +/*
> > + * QEMU AVR CPU
> > + *
> > + * Copyright (c) 2019 Michael Rolnik
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see
> > + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> > + */
> > +
> > +#ifndef QEMU_AVR_QOM_H
> > +#define QEMU_AVR_QOM_H
> > +
> > +#include "hw/core/cpu.h"
> > 

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

[Michael Rolnik]

Hi all.

As for now I have no plans to add support for AVR 32 bit CPU. If there are
requests I might consider it.
When I started to implement AVR 8 bit CPU I added that `#ifndef
CONFIG_USER_ONLY` as other CPUs did, so I guess they could be removed.

Regards,
Michael Rolnik

On Mon, Jan 27, 2020 at 4:39 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:

> > +static void avr_cpu_initfn(Object *obj)
> > +{
> > +AVRCPU *cpu = AVR_CPU(obj);
> > +
> > +cpu_set_cpustate_pointers(cpu);
> > +
> > +#ifndef CONFIG_USER_ONLY
> > +/* Set the number of interrupts supported by the CPU. */
> > +qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
> > +sizeof(cpu->env.intsrc) * 8);
> > +#endif
> > +}
>
> A question for Michael:
>
> What is CONFIG_USER_ONLY doing here, if we know AVR cores from this
> series doesn't have and will never have user mode, since they do not
> work with the kernel?
>
> Do you plan to support some AVR 32-bit CPUs in the same file, which
> would be able to have linux-user mode? But, in this case, many files
> must be completely redone. My advice is to separate them completely,
> and that this file supports only 8-bit AVR cores, and in that case
> checks for CONFIG_USER_ONLY do not make sense.
>
> Regards,
> Aleksandar
>
> > +
> > +static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
> > +{
> > +ObjectClass *oc;
> > +
> > +oc = object_class_by_name(cpu_model);
> > +if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
> > +object_class_is_abstract(oc)) {
> > +oc = NULL;
> > +}
> > +return oc;
> > +}
> > +
> > +static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> > +{
> > +AVRCPU *cpu = AVR_CPU(cs);
> > +CPUAVRState *env = >env;
> > +int i;
> > +
> > +qemu_fprintf(f, "\n");
> > +qemu_fprintf(f, "PC:%06x\n", env->pc_w);
> > +qemu_fprintf(f, "SP:  %04x\n", env->sp);
> > +qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
> > +qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
> > +qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
> > +qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
> > +qemu_fprintf(f, "EIND:  %02x\n", env->eind >> 16);
> > +qemu_fprintf(f, "X:   %02x%02x\n", env->r[27], env->r[26]);
> > +qemu_fprintf(f, "Y:   %02x%02x\n", env->r[29], env->r[28]);
> > +qemu_fprintf(f, "Z:   %02x%02x\n", env->r[31], env->r[30]);
> > +qemu_fprintf(f, "SREG:[ %c %c %c %c %c %c %c %c ]\n",
> > +env->sregI ? 'I' : '-',
> > +env->sregT ? 'T' : '-',
> > +env->sregH ? 'H' : '-',
> > +env->sregS ? 'S' : '-',
> > +env->sregV ? 'V' : '-',
> > +env->sregN ? '-' : 'N', /* Zf has negative
> logic */
> > +env->sregZ ? 'Z' : '-',
> > +env->sregC ? 'I' : '-');
> > +qemu_fprintf(f, "SKIP:%02x\n", env->skip);
> > +
> > +qemu_fprintf(f, "\n");
> > +for (i = 0; i < ARRAY_SIZE(env->r); i++) {
> > +qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
> > +
> > +if ((i % 8) == 7) {
> > +qemu_fprintf(f, "\n");
> > +}
> > +}
> > +qemu_fprintf(f, "\n");
> > +}
> > +
> > +static void avr_cpu_class_init(ObjectClass *oc, void *data)
> > +{
> > +DeviceClass *dc = DEVICE_CLASS(oc);
> > +CPUClass *cc = CPU_CLASS(oc);
> > +AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
> > +
> > +mcc->parent_realize = dc->realize;
> > +dc->realize = avr_cpu_realizefn;
> > +
> > +mcc->parent_reset = cc->reset;
> > +cc->reset = avr_cpu_reset;
> > +
> > +cc->class_by_name = avr_cpu_class_by_name;
> > +
> > +cc->has_work = avr_cpu_has_work;
> > +cc->do_interrupt = avr_cpu_do_interrupt;
> > +cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
> > +cc->dump_state = avr_cpu_dump_state;
> > +cc->set_pc = avr_cpu_set_pc;
> > +#if !defined(CONFIG_USER_ONLY)
> > +cc->memory_rw_debug = av

Re: [PATCH rc2 00/25] target/avr merger

[Michael Rolnik]

Just one patch attached.
Thanks.

On Fri, Jan 24, 2020 at 2:49 PM Philippe Mathieu-Daudé 
wrote:

> On 1/24/20 12:41 PM, Michael Rolnik wrote:
> > Tested-by: Michael Rolnik mailto:mrol...@gmail.com>>
>
> Thanks a lot!
>
> > The only thing I want to change is instead of -kernel put -bios in
> > qemu-doc.texi file. Should I send a new series?
>
> Please do NOT :)
>
> Richard can do the trivial fixup directly.
>
> > On Fri, Jan 24, 2020 at 2:51 AM Philippe Mathieu-Daudé  > <mailto:f4...@amsat.org>> wrote:
> >
> > This is the AVR port from Michael release (merge) candidate 2.
> >
> > Since v1 [1]:
> > - Addressed Thomas comments
> > - Fixed a non-critical bug in ATmega (incorrect SRAM base address)
> > - Added ELF parsing requested by Aleksandar
> > - Dropped default machine (as with the ARM port)
> >
> > Change since rc1:
> >
> > $ git backport-diff -u avr-rc1 -r origin/master..
> > Key:
> > [] : patches are identical
> > [] : number of functional differences between
> > upstream/downstream patch
> > [down] : patch is downstream-only
> > The flags [FC] indicate (F)unctional and (C)ontextual differences,
> > respectively
> >
> > 001/25:[] [--] 'target/avr: Add outward facing interfaces and
> > core CPU logic'
> > 002/25:[] [--] 'target/avr: Add instruction helpers'
> > 003/25:[] [--] 'target/avr: Add instruction translation -
> > Registers definition'
> > 004/25:[] [--] 'target/avr: Add instruction translation -
> > Arithmetic and Logic Instructions'
> > 005/25:[] [--] 'target/avr: Add instruction translation - Branch
> > Instructions'
> > 006/25:[] [--] 'target/avr: Add instruction translation - Data
> > Transfer Instructions'
> > 007/25:[] [--] 'target/avr: Add instruction translation - Bit
> > and Bit-test Instructions'
> > 008/25:[] [--] 'target/avr: Add instruction translation - MCU
> > Control Instructions'
> > 009/25:[] [--] 'target/avr: Add instruction translation - CPU
> > main translation function'
> > 010/25:[] [--] 'target/avr: Add instruction disassembly function'
> > 011/25:[] [--] 'hw/char: Add limited support for Atmel USART
> > peripheral'
> > 012/25:[0045] [FC] 'hw/timer: Add limited support for Atmel 16 bit
> > timer peripheral'
> > 013/25:[] [--] 'hw/misc: Add Atmel power device'
> > 014/25:[0024] [FC] 'target/avr: Add section about AVR into QEMU
> > documentation'
> > 015/25:[] [--] 'target/avr: Register AVR support with the rest
> > of QEMU'
> > 016/25:[] [--] 'target/avr: Add machine none test'
> > 017/25:[0002] [FC] 'target/avr: Update MAINTAINERS file'
> > 018/25:[down]  'hw/core/loader: Let load_elf populate the
> > processor-specific flags'
> > 019/25:[down]  'hw/avr: Add helper to load raw/ELF firmware
> > binaries'
> > 020/25:[0015] [FC] 'hw/avr: Add some ATmega microcontrollers'
> > 021/25:[0040] [FC] 'hw/avr: Add some Arduino boards'
> > 022/25:[] [--] 'target/avr: Update build system'
> > 023/25:[] [--] 'tests/boot-serial-test: Test some Arduino boards
> > (AVR based)'
> > 024/25:[] [--] 'tests/acceptance: Test the Arduino MEGA2560
> board'
> > 025/25:[] [--] '.travis.yml: Run the AVR acceptance tests'
> >
> > Repo: https://gitlab.com/philmd/qemu/commits/avr-rc2
> >
> > [1]
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg672926.html
> > Supersedes: <20200123000307.11541-1-richard.hender...@linaro.org
> > <mailto:20200123000307.11541-1-richard.hender...@linaro.org>>
> >
> > Michael Rolnik (20):
> >target/avr: Add outward facing interfaces and core CPU logic
> >target/avr: Add instruction helpers
> >target/avr: Add instruction translation - Registers definition
> >target/avr: Add instruction translation - Arithmetic and Logic
> >  Instructions
> >target/avr: Add instruction translation - Branch Instructions
> >target/avr: Add instruction translation - Data Transfer
> Instructions
> >target/avr: Add instruction translation - Bit and Bit-test
> >  Instructions
> >target/avr: Add instruction translation - MCU Control Instructions
> >target/avr: Add instruction translation - CPU main translation
> >

Re: [PATCH rc2 14/25] target/avr: Add section about AVR into QEMU documentation

[Michael Rolnik]

Hi Thomas.

I will fix it. thanks.

Michael Rolnik

On Fri, Jan 24, 2020 at 9:14 AM Thomas Huth  wrote:

> On 24/01/2020 01.51, Philippe Mathieu-Daudé wrote:
> > From: Michael Rolnik 
> >
> > Signed-off-by: Michael Rolnik 
> > Message-Id: <20200118191416.19934-16-mrol...@gmail.com>
> > Signed-off-by: Richard Henderson 
> > [PMD: Fixed typos]
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> > rc2: Fixed typos, s/sample/Arduino/, removed -serial section (thuth)
> > ---
> >  qemu-doc.texi | 51 +++
> >  1 file changed, 51 insertions(+)
> >
> > diff --git a/qemu-doc.texi b/qemu-doc.texi
> > index 39f950471f..89df1d325e 100644
> > --- a/qemu-doc.texi
> > +++ b/qemu-doc.texi
> > @@ -1741,6 +1741,7 @@ differences are mentioned in the following
> sections.
> >  * Microblaze System emulator::
> >  * SH4 System emulator::
> >  * Xtensa System emulator::
> > +* AVR System emulator::
> >  @end menu
> >
> >  @node PowerPC System emulator
> > @@ -2514,6 +2515,56 @@ so should only be used with trusted guest OS.
> >
> >  @c man end
> >
> > +@node AVR System emulator
> > +@section AVR System emulator
> > +@cindex system emulation (AVR)
> > +
> > +Use the executable @file{qemu-system-avr} to emulates a AVR 8 bit based
> machine
> > +having one for the following cores: avr1, avr2, avr25, avr3, avr31,
> avr35, avr4,
> > +avr5, avr51, avr6, avrtiny, xmega2, xmega3, xmega4, xmega5, xmega6 and
> xmega7.
> > +
> > +As for now it supports few Arduino boards for educational and testing
> purposes.
> > +These boards use a ATmega controller, which model is limited to USART &
> 16 bit
> > +timer devices, enought to run FreeRTOS based applications (like this
> @url{
> https://github.com/seharris/qemu-avr-tests/blob/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf,,demo
> })
> > +
> > +Following are examples of possible usages, assuming program.elf is
> compiled for
> > +AVR cpu
> > +@itemize
> > +
> > +@item Continuous non interrupted execution
> > +@example
> > +qemu-system-avr -kernel program.elf
> > +@end example
> > +
> > +@item Continuous non interrupted execution with serial output into
> telnet window
> > +@example
> > +qemu-system-avr -kernel program.elf -serial tcp::5678,server,nowait
> -nographic
> > +@end example
> > +and then in another shell
> > +@example
> > +telnet localhost 5678
> > +@end example
> > +
> > +@item Debugging wit GDB debugger
> > +@example
> > +qemu-system-avr -kernel program.elf -s -S
> > +@end example
> > +and then in another shell
> > +@example
> > +avr-gdb program.elf
> > +@end example
> > +and then within GDB shell
> > +@example
> > +target remote :1234
> > +@end example
> > +
> > +@item Print out executed instructions
> > +@example
> > +qemu-system-avr -kernel program.elf -d in_asm
>
> If you don't have a default board anymore, I think you need to list -M
> here, too.
> And didn't you mention that -kernel is not working anyway? Do you need
> to replace it with -bios ?
>
>  Thomas
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH rc2 00/25] target/avr merger

[Michael Rolnik]

Tested-by: Michael Rolnik 



The only thing I want to change is instead of -kernel put -bios in
qemu-doc.texi file. Should I send a new series?

On Fri, Jan 24, 2020 at 2:51 AM Philippe Mathieu-Daudé 
wrote:

> This is the AVR port from Michael release (merge) candidate 2.
>
> Since v1 [1]:
> - Addressed Thomas comments
> - Fixed a non-critical bug in ATmega (incorrect SRAM base address)
> - Added ELF parsing requested by Aleksandar
> - Dropped default machine (as with the ARM port)
>
> Change since rc1:
>
> $ git backport-diff -u avr-rc1 -r origin/master..
> Key:
> [] : patches are identical
> [] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/25:[] [--] 'target/avr: Add outward facing interfaces and core CPU
> logic'
> 002/25:[] [--] 'target/avr: Add instruction helpers'
> 003/25:[] [--] 'target/avr: Add instruction translation - Registers
> definition'
> 004/25:[] [--] 'target/avr: Add instruction translation - Arithmetic
> and Logic Instructions'
> 005/25:[] [--] 'target/avr: Add instruction translation - Branch
> Instructions'
> 006/25:[] [--] 'target/avr: Add instruction translation - Data
> Transfer Instructions'
> 007/25:[] [--] 'target/avr: Add instruction translation - Bit and
> Bit-test Instructions'
> 008/25:[] [--] 'target/avr: Add instruction translation - MCU Control
> Instructions'
> 009/25:[] [--] 'target/avr: Add instruction translation - CPU main
> translation function'
> 010/25:[] [--] 'target/avr: Add instruction disassembly function'
> 011/25:[] [--] 'hw/char: Add limited support for Atmel USART
> peripheral'
> 012/25:[0045] [FC] 'hw/timer: Add limited support for Atmel 16 bit timer
> peripheral'
> 013/25:[] [--] 'hw/misc: Add Atmel power device'
> 014/25:[0024] [FC] 'target/avr: Add section about AVR into QEMU
> documentation'
> 015/25:[] [--] 'target/avr: Register AVR support with the rest of QEMU'
> 016/25:[] [--] 'target/avr: Add machine none test'
> 017/25:[0002] [FC] 'target/avr: Update MAINTAINERS file'
> 018/25:[down]  'hw/core/loader: Let load_elf populate the
> processor-specific flags'
> 019/25:[down]  'hw/avr: Add helper to load raw/ELF firmware binaries'
> 020/25:[0015] [FC] 'hw/avr: Add some ATmega microcontrollers'
> 021/25:[0040] [FC] 'hw/avr: Add some Arduino boards'
> 022/25:[] [--] 'target/avr: Update build system'
> 023/25:[] [--] 'tests/boot-serial-test: Test some Arduino boards (AVR
> based)'
> 024/25:[] [--] 'tests/acceptance: Test the Arduino MEGA2560 board'
> 025/25:[] [--] '.travis.yml: Run the AVR acceptance tests'
>
> Repo: https://gitlab.com/philmd/qemu/commits/avr-rc2
>
> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg672926.html
> Supersedes: <20200123000307.11541-1-richard.hender...@linaro.org>
>
> Michael Rolnik (20):
>   target/avr: Add outward facing interfaces and core CPU logic
>   target/avr: Add instruction helpers
>   target/avr: Add instruction translation - Registers definition
>   target/avr: Add instruction translation - Arithmetic and Logic
> Instructions
>   target/avr: Add instruction translation - Branch Instructions
>   target/avr: Add instruction translation - Data Transfer Instructions
>   target/avr: Add instruction translation - Bit and Bit-test
> Instructions
>   target/avr: Add instruction translation - MCU Control Instructions
>   target/avr: Add instruction translation - CPU main translation
> function
>   target/avr: Add instruction disassembly function
>   hw/char: Add limited support for Atmel USART peripheral
>   hw/timer: Add limited support for Atmel 16 bit timer peripheral
>   hw/misc: Add Atmel power device
>   target/avr: Add section about AVR into QEMU documentation
>   target/avr: Register AVR support with the rest of QEMU
>   target/avr: Add machine none test
>   target/avr: Update MAINTAINERS file
>   target/avr: Update build system
>   tests/boot-serial-test: Test some Arduino boards (AVR based)
>   tests/acceptance: Test the Arduino MEGA2560 board
>
> Philippe Mathieu-Daudé (5):
>   hw/core/loader: Let load_elf populate the processor-specific flags
>   hw/avr: Add helper to load raw/ELF firmware binaries
>   hw/avr: Add some ATmega microcontrollers
>   hw/avr: Add some Arduino boards
>   .travis.yml: Run the AVR acceptance tests
>
>  qemu-doc.texi|   51 +
>  configure|7 +
>  default-configs/avr-softmmu.mak  |5 +
>  qapi/machine.json|3 +-
>  hw/avr/atmel_atmega.h|   48 +
&

Re: [PATCH rc1 00/24] target/avr merger

[Michael Rolnik]

How do I get it? from where?

On Thu, Jan 23, 2020 at 7:12 AM Thomas Huth  wrote:

> On 23/01/2020 01.02, Richard Henderson wrote:
> > This is a merger of Michael's v41 of the base avr architecture,
> > and v4 of Phil's arduino target boards.  Call this release, or
> > merge, candidate 1.
> >
> > Has all commentary been addressed?  How much more, if anything,
> > does anyone require before allowing normal development in tree?
>
> I just had a quick look at the series. Apart from some few nits, it
> looks fine to me, so I think it's fine to merge it now.
>
>  Thomas
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v4 00/18] hw/avr: Introduce few Arduino boards

[Michael Rolnik]

Hi Philippe.

1. I cannot access https://gitlab.com/philmd/qemu/commits/arduino-v4
2. I merged your series into my workspace using patchwork
3. I payed attention that that you don't use automatic CPU detection (as
suggested by Aleksandar) by reading elf.
4. There is difference between -bios and -kernel (arduino boars crash when
-bios is used, but this seems because I run avr6 on avr5 CPU). I would be
happy if you explained what is the difference between these two arguments.
5. make check-acceptance pass correctly
6. make check-qtest-avr pass correctly


On Tue, Jan 21, 2020 at 12:01 AM Philippe Mathieu-Daudé 
wrote:

> Hi,
>
> This series add the arduino boards, aiming at removing the
> 'sample' board that doesn't follow any specification.
>
> Since v3:
> - Rebased on Michael's v41
> - Drop 'extram' unused field (Igor)
> - Renamed devices AVR -> Atmel (Aleksandar)
>   (I haven't renamed structure names to ease review)
>
> Since v2:
> - rebased on Michael's v40
>
> Since v1:
> - Addressed Igor comments
> - Addressed Aleksandar comments
> - Fixed UART issue (was due to IRQ shifted by 2 in CPU)
>
> Since Michael's work is not yet merged, Various of my patches
> - which are trivials or simple renames - could be squashed
> directly on his patches, if we ever care.
> [I believe sending this patches is easier/quicker than keeping
> asking Michael to respin his series infinitely].
>
> Michael, do you mind testing it? The full series is available
> here: https://gitlab.com/philmd/qemu/commits/arduino-v4
>
> Regards,
>
> Phil.
>
> Obsoletes: <20191229224505.24466-1-f4...@amsat.org>
> Based-on: <20200118191416.19934-1-mrol...@gmail.com>
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg671707.html
>
> Philippe Mathieu-Daudé (18):
>   MAINTAINERS: Move machine test to the machine section (not ARCH one)
>   MAINTAINERS: Move the AVR machines in new section (not within ARM)
>   tests/acceptance: Do not set the machine type manually
>   tests/acceptance: Keep multilines comment consistent with other tests
>   hw/char/avr: Reduce USART I/O size
>   hw/timer/avr_timer16: Rename memory region debugging name
>   hw/misc/avr_mask: Remove unused include
>   hw/avr/Makefile: Use CONFIG_AVR_SAMPLE variable
>   hw/char: Rename avr_usart -> atmel_usart
>   hw/timer: Rename avr_timer16 -> atmel_timer16
>   hw/misc: Rename avr_mask -> atmel_power
>   hw/avr: Introduce ATMEL_ATMEGA_MCU config
>   hw/avr: Add some ATmega microcontrollers
>   hw/avr: Add some Arduino boards
>   tests/boot-serial-test: Test some Arduino boards (AVR based)
>   tests/acceptance: Test the Arduino MEGA2560 board
>   hw/avr: Remove the unrealistic AVR 'sample' board
>   .travis.yml: Run the AVR acceptance tests
>
>  default-configs/avr-softmmu.mak   |   2 +-
>  hw/avr/atmel_atmega.h |  48 ++
>  .../hw/char/{avr_usart.h => atmel_usart.h}|  10 +-
>  include/hw/misc/{avr_mask.h => atmel_power.h} |  11 +-
>  .../timer/{avr_timer16.h => atmel_timer16.h}  |  10 +-
>  hw/avr/arduino.c  | 175 +++
>  hw/avr/atmel_atmega.c | 464 ++
>  hw/avr/sample.c   | 295 ---
>  hw/char/{avr_usart.c => atmel_usart.c}|   6 +-
>  hw/misc/{avr_mask.c => atmel_power.c} |   4 +-
>  hw/timer/{avr_timer16.c => atmel_timer16.c}   |  10 +-
>  tests/qtest/boot-serial-test.c|   3 +-
>  .travis.yml   |   2 +-
>  MAINTAINERS   |  29 +-
>  hw/avr/Kconfig|  11 +-
>  hw/avr/Makefile.objs  |   3 +-
>  hw/char/Kconfig   |   2 +-
>  hw/char/Makefile.objs |   2 +-
>  hw/misc/Kconfig   |   2 +-
>  hw/misc/Makefile.objs |   2 +-
>  hw/timer/Kconfig  |   2 +-
>  hw/timer/Makefile.objs|   2 +-
>  tests/acceptance/machine_avr6.py  |  11 +-
>  23 files changed, 751 insertions(+), 355 deletions(-)
>  create mode 100644 hw/avr/atmel_atmega.h
>  rename include/hw/char/{avr_usart.h => atmel_usart.h} (93%)
>  rename include/hw/misc/{avr_mask.h => atmel_power.h} (89%)
>  rename include/hw/timer/{avr_timer16.h => atmel_timer16.h} (92%)
>  create mode 100644 hw/avr/arduino.c
>  create mode 100644 hw/avr/atmel_atmega.c
>  delete mode 100644 hw/avr/sample.c
>  rename hw/char/{avr_usart.c => atmel_usart.c} (99%)
>  rename hw/misc/{avr_mask.c => atmel_power.c} (97%)
>  rename hw/timer/{avr_timer16.c => atmel_timer16.c} (98%)
>
> --
> 2.21.1
>
>

-- 
Best Regards,
Michael Rolnik

Re: [PATCH v3 0/8] hw/avr: Introduce the Arduino boards

[Michael Rolnik]

Sure, no problem.

On Mon, Jan 20, 2020 at 12:50 AM Philippe Mathieu-Daudé 
wrote:

> Hi Michael,
>
> On 12/30/19 7:17 PM, Michael Rolnik wrote:
> > Hi Philippe.
> >
> > Thank you for joining the effort.
>
> Could you test this series?
>
> Are you OK if we use the Arduino machines it introduces to replace your
> 'sample' board?
>
> > Regards,
> > Michael Rolnik
> >
> >
> > On Mon, Dec 30, 2019 at 12:45 AM Philippe Mathieu-Daudé  > <mailto:f4...@amsat.org>> wrote:
> >
> > Hi,
> >
> > This series add the arduino boards, aiming at removing the
> > 'sample' board that doesn't follow any specification.
> >
> > Since v2:
> > - rebased on Michael's v40
> >
> > Since v1:
> > - Addressed Igor comments
> > - Addressed Aleksandar comments
> > - Fixed UART issue (was due to IRQ shifted by 2 in CPU)
> >
> > TODO after merge is:
> > - Extract Timer8 common parts from Timer16
> > - Add GPIOs
> > - Connect LED to GPIO on Arduino
> > - Plug to Scratch (See http://s4a.cat/).
> >   (I plan to purpose that as a GSoC idea).
> >
> > Michael, thank you for having insisted with this port during so long!
> >
> > Regards,
> >
> > Phil.
> >
> > Series available at
> https://gitlab.com/philmd/qemu/commits/arduino-v3
> >
> > Regards,
> >
> > Phil.
> >
> > Based-on: <20191229215158.5788-1-mrol...@gmail.com
> > <mailto:20191229215158.5788-1-mrol...@gmail.com>>
> > https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg05309.html
> >
> > Philippe Mathieu-Daudé (8):
> >   hw/char/avr: Reduce USART I/O size
> >   hw/timer/avr_timer16: Rename memory region debugging name
> >   hw/avr: Add some ATmega microcontrollers
> >   hw/avr: Add some Arduino boards
> >   tests/boot-serial-test: Test some Arduino boards (AVR based)
> >   tests/acceptance: Do not set the machine type manually
> >   tests/acceptance: Keep multilines comment consistent with other
> tests
> >   tests/acceptance: Test the Arduino MEGA2560 board
> >
> >  hw/avr/atmega.h  |  48 
> >  hw/avr/arduino.c | 177 
> >  hw/avr/atmega.c  | 464
> +++
> >  hw/char/avr_usart.c  |   2 +-
> >  hw/timer/avr_timer16.c   |   6 +-
> >  tests/boot-serial-test.c     |   2 +
> >  hw/avr/Makefile.objs |   2 +
> >  tests/acceptance/machine_avr6.py |  11 +-
> >  8 files changed, 701 insertions(+), 11 deletions(-)
> >  create mode 100644 hw/avr/atmega.h
> >  create mode 100644 hw/avr/arduino.c
> >  create mode 100644 hw/avr/atmega.c
> >
> > --
> > 2.21.0
> >
> >
> >
> > --
> > Best Regards,
> > Michael Rolnik
>


-- 
Best Regards,
Michael Rolnik

[PATCH v41 21/21] target/avr: Update MAINTAINERS file

[Michael Rolnik]

Include AVR maintaners in MAINTAINERS file

Signed-off-by: Michael Rolnik 
---
 MAINTAINERS | 21 +
 1 file changed, 21 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 55d3642e6c..c70d77b1ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -163,6 +163,15 @@ S: Maintained
 F: hw/arm/smmu*
 F: include/hw/arm/smmu*
 
+AVR TCG CPUs
+M: Michael Rolnik 
+R: Sarah Harris 
+S: Maintained
+F: target/avr/
+F: tests/acceptance/machine_avr6.py
+F: default-configs/avr-softmmu.mak
+F: gdb-xml/avr-cpu.xml
+
 CRIS TCG CPUs
 M: Edgar E. Iglesias 
 S: Maintained
@@ -481,6 +490,18 @@ F: hw/*/allwinner*
 F: include/hw/*/allwinner*
 F: hw/arm/cubieboard.c
 
+AVR Machines
+M: Michael Rolnik 
+R: Sarah Harris 
+S: Maintained
+F: hw/avr/
+F: hw/char/avr_usart.c
+F: include/hw/char/avr_usart.h
+F: hw/timer/avr_timer16.c
+F: include/hw/timer/avr_timer16.h
+F: hw/misc/avr_mask.c
+F: include/hw/misc/avr_mask.h
+
 ARM PrimeCell and CMSDK devices
 M: Peter Maydell 
 L: qemu-...@nongnu.org
-- 
2.17.2 (Apple Git-113)

[PATCH v41 19/21] target/avr: Add boot serial test

[Michael Rolnik]

Print out 'T' through serial port

Signed-off-by: Michael Rolnik 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
Acked-by: Thomas Huth 

tests/Makefile.include
---
 tests/qtest/boot-serial-test.c | 10 ++
 tests/qtest/Makefile.include   |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index 05c7f44457..e556f09db8 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -16,6 +16,15 @@
 #include "qemu/osdep.h"
 #include "libqtest.h"
 
+static const uint8_t bios_avr[] = {
+0x88, 0xe0, /* ldi r24, 0x08   */
+0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
+0x86, 0xe0, /* ldi r24, 0x06   */
+0x80, 0x93, 0xc2, 0x00, /* sts 0x00C2, r24 ; Set the data bits to 8 */
+0x84, 0xe5, /* ldi r24, 0x54   */
+0x80, 0x93, 0xc6, 0x00, /* sts 0x00C6, r24 ; Output 'T' */
+};
+
 static const uint8_t kernel_mcf5208[] = {
 0x41, 0xf9, 0xfc, 0x06, 0x00, 0x00, /* lea 0xfc06,%a0 */
 0x10, 0x3c, 0x00, 0x54, /* move.b #'T',%d0 */
@@ -103,6 +112,7 @@ typedef struct testdef {
 
 static testdef_t tests[] = {
 { "alpha", "clipper", "", "PCI:" },
+{ "avr", "sample", "", "T", sizeof(bios_avr), NULL, bios_avr },
 { "ppc", "ppce500", "", "U-Boot" },
 { "ppc", "40p", "-vga none -boot d", "Trying cd:," },
 { "ppc", "g3beige", "", "PowerPC,750" },
diff --git a/tests/qtest/Makefile.include b/tests/qtest/Makefile.include
index e6bb4ab28c..4817b6320f 100644
--- a/tests/qtest/Makefile.include
+++ b/tests/qtest/Makefile.include
@@ -65,6 +65,8 @@ check-qtest-i386-y += numa-test
 
 check-qtest-x86_64-y += $(check-qtest-i386-y)
 
+check-qtest-avr-y += boot-serial-test
+
 check-qtest-alpha-y += boot-serial-test
 check-qtest-alpha-$(CONFIG_VGA) += display-vga-test
 
-- 
2.17.2 (Apple Git-113)

[PATCH v41 18/21] target/avr: Update build system

[Michael Rolnik]

Make AVR support buildable

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
Reviewed-by: Aleksandar Markovic 
---
 configure   |  7 +++
 default-configs/avr-softmmu.mak |  5 +
 target/avr/Makefile.objs| 34 +
 3 files changed, 46 insertions(+)
 create mode 100644 default-configs/avr-softmmu.mak
 create mode 100644 target/avr/Makefile.objs

diff --git a/configure b/configure
index 557e4382ea..94e79ca634 100755
--- a/configure
+++ b/configure
@@ -7612,6 +7612,10 @@ case "$target_name" in
 mttcg="yes"
 gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml 
arm-vfp3.xml arm-neon.xml"
   ;;
+  avr)
+gdb_xml_files="avr-cpu.xml"
+target_compiler=$cross_cc_avr
+  ;;
   cris)
   ;;
   hppa)
@@ -7831,6 +7835,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
   disas_config "ARM_A64"
 fi
   ;;
+  avr)
+disas_config "AVR"
+  ;;
   cris)
 disas_config "CRIS"
   ;;
diff --git a/default-configs/avr-softmmu.mak b/default-configs/avr-softmmu.mak
new file mode 100644
index 00..d1e1c28118
--- /dev/null
+++ b/default-configs/avr-softmmu.mak
@@ -0,0 +1,5 @@
+# Default configuration for avr-softmmu
+
+# Boards:
+#
+CONFIG_AVR_SAMPLE=y
diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs
new file mode 100644
index 00..7523e0c6e2
--- /dev/null
+++ b/target/avr/Makefile.objs
@@ -0,0 +1,34 @@
+#
+#  QEMU AVR CPU
+#
+#  Copyright (c) 2019 Michael Rolnik
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, see
+#  <http://www.gnu.org/licenses/lgpl-2.1.html>
+#
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+decode-y = $(SRC_PATH)/target/avr/insn.decode
+
+target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
+   $(call quiet-command, \
+ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, 
\
+ "GEN", $(TARGET_DIR)$@)
+
+target/avr/translate.o: target/avr/decode_insn.inc.c
+
+obj-y += translate.o cpu.o helper.o
+obj-y += gdbstub.o
+obj-y += disas.o
+obj-$(CONFIG_SOFTMMU) += machine.o
-- 
2.17.2 (Apple Git-113)

[PATCH v41 16/21] target/avr: Register AVR support with the rest of QEMU

[Michael Rolnik]

Add AVR related definitions into QEMU

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
Reviewed-by: Aleksandar Markovic 

include/disas/dis-asm.h
---
 qapi/machine.json  |  3 ++-
 include/disas/dis-asm.h| 19 +++
 include/sysemu/arch_init.h |  1 +
 arch_init.c|  2 ++
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/qapi/machine.json b/qapi/machine.json
index b3d30bc816..f2dc385167 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -21,11 +21,12 @@
 #is true even for "qemu-system-x86_64".
 #
 # ppcemb: dropped in 3.1
+# avr: since 5.0
 #
 # Since: 3.0
 ##
 { 'enum' : 'SysEmuTarget',
-  'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32',
+  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm32',
  'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
  'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc',
  'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index e9c7dd8eb4..79bbc8b498 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -211,6 +211,25 @@ enum bfd_architecture
 #define bfd_mach_m32r  0  /* backwards compatibility */
   bfd_arch_mn10200,/* Matsushita MN10200 */
   bfd_arch_mn10300,/* Matsushita MN10300 */
+  bfd_arch_avr,   /* Atmel AVR microcontrollers.  */
+#define bfd_mach_avr1   1
+#define bfd_mach_avr2   2
+#define bfd_mach_avr25  25
+#define bfd_mach_avr3   3
+#define bfd_mach_avr31  31
+#define bfd_mach_avr35  35
+#define bfd_mach_avr4   4
+#define bfd_mach_avr5   5
+#define bfd_mach_avr51  51
+#define bfd_mach_avr6   6
+#define bfd_mach_avrtiny100
+#define bfd_mach_avrxmega1  101
+#define bfd_mach_avrxmega2  102
+#define bfd_mach_avrxmega3  103
+#define bfd_mach_avrxmega4  104
+#define bfd_mach_avrxmega5  105
+#define bfd_mach_avrxmega6  106
+#define bfd_mach_avrxmega7  107
   bfd_arch_cris,   /* Axis CRIS */
 #define bfd_mach_cris_v0_v10   255
 #define bfd_mach_cris_v32  32
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 62c6fe4cf1..893df26ce2 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
 QEMU_ARCH_NIOS2 = (1 << 17),
 QEMU_ARCH_HPPA = (1 << 18),
 QEMU_ARCH_RISCV = (1 << 19),
+QEMU_ARCH_AVR = (1 << 20),
 };
 
 extern const uint32_t arch_type;
diff --git a/arch_init.c b/arch_init.c
index 705d0b94ad..6a741165b2 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -89,6 +89,8 @@ int graphic_depth = 32;
 #define QEMU_ARCH QEMU_ARCH_UNICORE32
 #elif defined(TARGET_XTENSA)
 #define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_AVR)
+#define QEMU_ARCH QEMU_ARCH_AVR
 #endif
 
 const uint32_t arch_type = QEMU_ARCH;
-- 
2.17.2 (Apple Git-113)

[PATCH v41 20/21] target/avr: Add Avocado test

[Michael Rolnik]

The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working

Signed-off-by: Michael Rolnik 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
Acked-by: Thomas Huth 
---
 tests/acceptance/machine_avr6.py | 53 
 1 file changed, 53 insertions(+)
 create mode 100644 tests/acceptance/machine_avr6.py

diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py
new file mode 100644
index 00..43501b26a3
--- /dev/null
+++ b/tests/acceptance/machine_avr6.py
@@ -0,0 +1,53 @@
+#
+# QEMU AVR
+#
+# Copyright (c) 2019 Michael Rolnik 
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+import time
+
+from avocado_qemu import Test
+
+class AVR6Machine(Test):
+timeout = 5
+
+def test_freertos(self):
+"""
+:avocado: tags=arch:avr
+:avocado: tags=machine:sample
+"""
+"""
+
https://github.com/seharris/qemu-avr-tests/raw/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
+constantly prints out 
'ABCDEFGHIJKLMNOPQRSTUVWXABCDEFGHIJKLMNOPQRSTUVWX'
+"""
+rom_url = 'https://github.com/seharris/qemu-avr-tests'
+rom_sha1= '36c3e67b8755dcf37e06af6730ef5d477b8ed16d'
+rom_url += '/raw/'
+rom_url += rom_sha1
+rom_url += '/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf'
+rom_hash = '7eb521f511ca8f2622e0a3c5e8dd686efbb911d4'
+rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash)
+
+self.vm.set_machine('sample')
+self.vm.add_args('-bios', rom_path)
+self.vm.add_args('-nographic')
+self.vm.launch()
+
+time.sleep(2)
+self.vm.shutdown()
+
+self.assertIn('ABCDEFGHIJKLMNOPQRSTUVWXABCDEFGHIJKLMNOPQRSTUVWX',
+self.vm.get_log())
-- 
2.17.2 (Apple Git-113)

[PATCH v41 11/21] hw/avr: Add limited support for USART peripheral

[Michael Rolnik]

These were designed to facilitate testing but should provide enough function to 
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to 
the lack of a standard way to handle electrical connections (like GPIO pins).

Signed-off-by: Sarah Harris 
---
 include/hw/char/avr_usart.h |  93 +++
 hw/char/avr_usart.c | 320 
 hw/char/Kconfig |   3 +
 hw/char/Makefile.objs   |   1 +
 4 files changed, 417 insertions(+)
 create mode 100644 include/hw/char/avr_usart.h
 create mode 100644 hw/char/avr_usart.c

diff --git a/include/hw/char/avr_usart.h b/include/hw/char/avr_usart.h
new file mode 100644
index 00..467e97e8c0
--- /dev/null
+++ b/include/hw/char/avr_usart.h
@@ -0,0 +1,93 @@
+/*
+ * AVR USART
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Sarah Harris
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * 
+ */
+
+#ifndef HW_AVR_USART_H
+#define HW_AVR_USART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/hw.h"
+
+/* Offsets of registers. */
+#define USART_DR   0x06
+#define USART_CSRA  0x00
+#define USART_CSRB  0x01
+#define USART_CSRC  0x02
+#define USART_BRRH 0x05
+#define USART_BRRL 0x04
+
+/* Relevant bits in regiters. */
+#define USART_CSRA_RXC(1 << 7)
+#define USART_CSRA_TXC(1 << 6)
+#define USART_CSRA_DRE(1 << 5)
+#define USART_CSRA_MPCM   (1 << 0)
+
+#define USART_CSRB_RXCIE  (1 << 7)
+#define USART_CSRB_TXCIE  (1 << 6)
+#define USART_CSRB_DREIE  (1 << 5)
+#define USART_CSRB_RXEN   (1 << 4)
+#define USART_CSRB_TXEN   (1 << 3)
+#define USART_CSRB_CSZ2   (1 << 2)
+#define USART_CSRB_RXB8   (1 << 1)
+#define USART_CSRB_TXB8   (1 << 0)
+
+#define USART_CSRC_MSEL1  (1 << 7)
+#define USART_CSRC_MSEL0  (1 << 6)
+#define USART_CSRC_PM1(1 << 5)
+#define USART_CSRC_PM0(1 << 4)
+#define USART_CSRC_CSZ1   (1 << 2)
+#define USART_CSRC_CSZ0   (1 << 1)
+
+#define TYPE_AVR_USART "avr-usart"
+#define AVR_USART(obj) \
+OBJECT_CHECK(AVRUsartState, (obj), TYPE_AVR_USART)
+
+typedef struct {
+/*  */
+SysBusDevice parent_obj;
+
+/*  */
+MemoryRegion mmio;
+
+CharBackend chr;
+
+bool enabled;
+
+uint8_t data;
+bool data_valid;
+uint8_t char_mask;
+/* Control and Status Registers */
+uint8_t csra;
+uint8_t csrb;
+uint8_t csrc;
+/* Baud Rate Registers (low/high byte) */
+uint8_t brrh;
+uint8_t brrl;
+
+/* Receive Complete */
+qemu_irq rxc_irq;
+/* Transmit Complete */
+qemu_irq txc_irq;
+/* Data Register Empty */
+qemu_irq dre_irq;
+} AVRUsartState;
+
+#endif /* HW_AVR_USART_H */
diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
new file mode 100644
index 00..cb307fe23d
--- /dev/null
+++ b/hw/char/avr_usart.c
@@ -0,0 +1,320 @@
+/*
+ * AVR USART
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Sarah Harris
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * 
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/avr_usart.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+static int avr_usart_can_receive(void *opaque)
+{
+AVRUsartState *usart = opaque;
+
+if (usart->data_valid || !(usart->csrb & USART_CSRB_RXEN)) {
+return 0;
+}
+return 1;
+}
+
+static void avr_usart_receive(void *opaque, const uint8_t *buffer, int size)
+{
+AVRUsartState *usart = opaque;
+assert(size == 1);
+assert(!usart->data_valid);
+usart->data = buffer[0];
+usart->data_valid = true;
+usart->csra |= USART_CSRA_RXC;
+if (usart->csrb & USART_CSRB_RXCIE) {
+qemu_set_irq(usart->rxc_irq, 1);
+}
+}
+
+static void 

[PATCH v41 15/21] target/avr: Add section about AVR into QEMU documentation

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 qemu-doc.texi | 51 +++
 1 file changed, 51 insertions(+)

diff --git a/qemu-doc.texi b/qemu-doc.texi
index 39f950471f..515aacfae9 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -1741,6 +1741,7 @@ differences are mentioned in the following sections.
 * Microblaze System emulator::
 * SH4 System emulator::
 * Xtensa System emulator::
+* AVR System emulator::
 @end menu
 
 @node PowerPC System emulator
@@ -2514,6 +2515,56 @@ so should only be used with trusted guest OS.
 
 @c man end
 
+@node AVR System emulator
+@section AVR System emulator
+@cindex system emulation (AVR)
+
+Use the executable @file{qemu-system-avr} to emulates a AVR 8 bit based 
machine having one for the following cores: avr1, avr2, avr25, avr3, avr31, 
avr35, avr4, avr5, avr51, avr6, avrtiny, xmega2, xmega3, xmega4, xmega5, xmega6 
and xmega7.
+
+As for now it does not support any real MCUs. However, it does support a 
"sample" board for educational and testing purposes. This "sample" board hosts 
USART & 16 bit timer devices and it's enought to run FreeRTOS based applicaton 
(like this 
@url{https://github.com/seharris/qemu-avr-tests/blob/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf,,demo})
+
+Following are examples of possible usages, assuming program.elf is compiled 
for AVR cpu
+@itemize
+
+@item Continious non interrupted execution
+@example
+qemu-system-avr -kernel program.elf
+@end example
+
+@item Continious non interrupted execution with serial output into telnet 
window
+@example
+qemu-system-avr -kernel program.elf -serial tcp::5678,server,nowait -nographic
+@end example
+and then in another shell
+@example
+telent localhost 5678
+@end example
+
+@item Continious non interrupted execution with serial output into stdout
+@example
+qemu-system-avr -kernel program.elf -serial stdio
+@end example
+
+@item Debugging wit GDB debugger
+@example
+qemu-system-avr -kernel program.elf -s -S
+@end example
+and then in another shell
+@example
+avr-gdb program.elf
+@end example
+and then within GDB shell
+@example
+target remote :1234
+@end example
+
+@item Print out executed instructions
+@example
+qemu-system-avr -kernel program.elf -d in_asm
+@end example
+
+@end itemize
+
 @node QEMU User space emulator
 @chapter QEMU User space emulator
 
-- 
2.17.2 (Apple Git-113)

[PATCH v41 17/21] target/avr: Add machine none test

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
Reviewed-by: Aleksandar Markovic 
---
 tests/qtest/machine-none-test.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
index 5953d31755..3e5c74e73e 100644
--- a/tests/qtest/machine-none-test.c
+++ b/tests/qtest/machine-none-test.c
@@ -27,6 +27,7 @@ static struct arch2cpu cpus_map[] = {
 /* tested targets list */
 { "arm", "cortex-a15" },
 { "aarch64", "cortex-a57" },
+{ "avr", "avr6-avr-cpu" },
 { "x86_64", "qemu64,apic-id=0" },
 { "i386", "qemu32,apic-id=0" },
 { "alpha", "ev67" },
-- 
2.17.2 (Apple Git-113)

[PATCH v41 13/21] hw/avr: Add dummy mask device

[Michael Rolnik]

This is a simple device of just one register, whenver this register is
written it calls qemu_set_irq function for each of 8 bits/IRQs..
It is used to implement AVR Power Reduction

Signed-off-by: Michael Rolnik 
---
 include/hw/misc/avr_mask.h |  47 
 hw/misc/avr_mask.c | 112 +
 hw/misc/Kconfig|   3 +
 hw/misc/Makefile.objs  |   2 +
 4 files changed, 164 insertions(+)
 create mode 100644 include/hw/misc/avr_mask.h
 create mode 100644 hw/misc/avr_mask.c

diff --git a/include/hw/misc/avr_mask.h b/include/hw/misc/avr_mask.h
new file mode 100644
index 00..d3e21972d8
--- /dev/null
+++ b/include/hw/misc/avr_mask.h
@@ -0,0 +1,47 @@
+/*
+ * AVR Power Reduction
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_avr_mask_H
+#define HW_avr_mask_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/hw.h"
+
+
+#define TYPE_AVR_MASK "avr-mask"
+#define AVR_MASK(obj) OBJECT_CHECK(AVRMaskState, (obj), TYPE_AVR_MASK)
+
+typedef struct {
+/*  */
+SysBusDevice parent_obj;
+
+/*  */
+MemoryRegion iomem;
+
+uint8_t val;
+qemu_irq irq[8];
+} AVRMaskState;
+
+#endif /* HW_avr_mask_H */
diff --git a/hw/misc/avr_mask.c b/hw/misc/avr_mask.c
new file mode 100644
index 00..3af82ed9c1
--- /dev/null
+++ b/hw/misc/avr_mask.c
@@ -0,0 +1,112 @@
+/*
+ * AVR Power Reduction
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/avr_mask.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/irq.h"
+
+#define DB_PRINT(fmt, args...) /* Nothing */
+/*#define DB_PRINT(fmt, args...) printf("%s: " fmt "\n", __func__, ## args)*/
+
+static void avr_mask_reset(DeviceState *dev)
+{
+AVRMaskState *s = AVR_MASK(dev);
+
+s->val = 0x00;
+
+for (int i = 0; i < 8; i++) {
+qemu_set_irq(s->irq[i], 0);
+}
+}
+
+static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size)
+{
+assert(size == 1);
+assert(offset == 0);
+AVRMaskState *s = opaque;
+
+return (uint64_t)s->val;
+}
+
+static void avr_mask_write(void *opaque, hwaddr offset,
+  uint64_t val64, unsigned size)
+{
+assert(size == 1);
+assert(offset == 0);
+AVRMaskState *s = opaque;
+uint8_t val8 = val64;
+
+DB_PRINT("write %d to offset %d", val8, (uint8_t)offset);
+
+s->val = val8;
+for (int i = 0; i < 8; i++) {
+qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0);
+}
+}
+
+static const MemoryRegionOps avr_mask_ops = {
+.read = avr_mask_read,

[PATCH v41 07/21] target/avr: Add instruction translation - Bit and Bit-test Instructions

[Michael Rolnik]

This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 241 +
 target/avr/insn.decode |  14 +++
 2 files changed, 255 insertions(+)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 4a62d9312a..58775af17c 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2440,3 +2440,244 @@ static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
 
 return true;
 }
+
+/*
+ * Bit and Bit-test Instructions
+ */
+static void gen_rshift_ZNVSf(TCGv R)
+{
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
+tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is
+ *  loaded into the C Flag of the SREG. This operation effectively divides an
+ *  unsigned value by two. The C Flag can be used to round the result.
+ */
+static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
+{
+TCGv Rd = cpu_r[a->rd];
+
+tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+tcg_gen_shri_tl(Rd, Rd, 1);
+/* update status register */
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */
+tcg_gen_movi_tl(cpu_Nf, 0);
+tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
+tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
+
+return true;
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. The C Flag is shifted into
+ *  bit 7 of Rd. Bit 0 is shifted into the C Flag.  This operation, combined
+ *  with ASR, effectively divides multi-byte signed values by two. Combined 
with
+ *  LSR it effectively divides multi-byte unsigned values by two. The Carry 
Flag
+ *  can be used to round the result.
+ */
+static bool trans_ROR(DisasContext *ctx, arg_ROR *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv t0 = tcg_temp_new_i32();
+
+tcg_gen_shli_tl(t0, cpu_Cf, 7);
+/* update status register */
+tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+/* update output register */
+tcg_gen_shri_tl(Rd, Rd, 1);
+tcg_gen_or_tl(Rd, Rd, t0);
+/* update status register */
+gen_rshift_ZNVSf(Rd);
+
+tcg_temp_free_i32(t0);
+
+return true;
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0
+ *  is loaded into the C Flag of the SREG. This operation effectively divides a
+ *  signed value by two without changing its sign. The Carry Flag can be used 
to
+ *  round the result.
+ */
+static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv t0 = tcg_temp_new_i32();
+
+/* update status register */
+tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */
+/* update output register */
+tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
+tcg_gen_shri_tl(Rd, Rd, 1);
+tcg_gen_or_tl(Rd, Rd, t0);
+/* update status register */
+gen_rshift_ZNVSf(Rd);
+
+tcg_temp_free_i32(t0);
+
+return true;
+}
+
+/*
+ *  Swaps high and low nibbles in a register.
+ */
+static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv t0 = tcg_temp_new_i32();
+TCGv t1 = tcg_temp_new_i32();
+
+tcg_gen_andi_tl(t0, Rd, 0x0f);
+tcg_gen_shli_tl(t0, t0, 4);
+tcg_gen_andi_tl(t1, Rd, 0xf0);
+tcg_gen_shri_tl(t1, t1, 4);
+tcg_gen_or_tl(Rd, t0, t1);
+
+tcg_temp_free_i32(t1);
+tcg_temp_free_i32(t0);
+
+return true;
+}
+
+/*
+ *  Sets a specified bit in an I/O Register. This instruction operates on
+ *  the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
+{
+TCGv data = tcg_temp_new_i32();
+TCGv port = tcg_const_i32(a->reg);
+
+gen_helper_inb(data, cpu_env, port);
+tcg_gen_ori_tl(data, data, 1 << a->bit);
+gen_helper_outb(cpu_env, port, data);
+
+tcg_temp_free_i32(port);
+tcg_temp_free_i32(data);
+
+return true;
+}
+
+/*
+ *  Clears a specified bit in an I/O Register. This instruction operates on
+ *  the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
+{
+TCGv data = tcg_temp_new_i32();
+TCGv port = tcg_const_i32(a->reg);
+
+gen_helper_inb(data, cpu_env, port);
+tcg_gen_andi_tl(data, data, ~(1 << a->bit));
+gen_helper_outb(cpu_env, port, data);
+
+tcg_temp_free_i32(data);
+tcg_temp_free_i32(port);
+
+return true;
+}
+
+/*
+ *  Stores bit b from Rd to the T Flag in SREG (Status Register).
+ */
+static bool trans_BST(DisasContext *ctx, arg_BST *a)
+{
+TCGv Rd = cpu_r[a->rd];
+
+tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
+tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
+
+return true;
+}
+
+/*
+ *  Copies the T Flag in the SREG (Status Register) to bit b in regist

[PATCH v41 10/21] target/avr: Add instruction disassembly function

[Michael Rolnik]

Provide function disassembles executed instruction when `-d in_asm` is
provided

Example:
`./avr-softmmu/qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf 
-d in_asm` will produce something like the following

```
...
IN:
0x014a:  CALL  0x3808

IN: main
0x3808:  CALL  0x4b4

IN: vParTestInitialise
0x04b4:  LDI   r24, 255
0x04b6:  STS   r24, 0
0x04b8:  MULS  r16, r20
0x04ba:  OUT   $1, r24
0x04bc:  LDS   r24, 0
0x04be:  MULS  r16, r20
0x04c0:  OUT   $2, r24
0x04c2:  RET
...
```

Signed-off-by: Michael Rolnik 
Suggested-by: Richard Henderson 
Suggested-by: Philippe Mathieu-Daudé 
Suggested-by: Aleksandar Markovic 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/cpu.h   |   1 +
 target/avr/cpu.c   |   2 +-
 target/avr/disas.c | 245 +
 target/avr/translate.c |  12 ++
 4 files changed, 259 insertions(+), 1 deletion(-)
 create mode 100644 target/avr/disas.c

diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index b74bcf01ae..af89b6611e 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -160,6 +160,7 @@ bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
 hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int avr_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int avr_print_insn(bfd_vma addr, disassemble_info *info);
 
 static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
 {
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index c74c5106fe..fa51f771c0 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -84,7 +84,7 @@ static void avr_cpu_reset(CPUState *cs)
 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 {
 info->mach = bfd_arch_avr;
-info->print_insn = NULL;
+info->print_insn = avr_print_insn;
 }
 
 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target/avr/disas.c b/target/avr/disas.c
new file mode 100644
index 00..f3fa3d6bef
--- /dev/null
+++ b/target/avr/disas.c
@@ -0,0 +1,245 @@
+/*
+ * AVR disassembler
+ *
+ * Copyright (c) 2019 Richard Henderson 
+ * Copyright (c) 2019 Michael Rolnik 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+
+typedef struct {
+disassemble_info *info;
+uint16_t next_word;
+bool next_word_used;
+} DisasContext;
+
+static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
+{
+return 16 + (indx % 16);
+}
+
+static int to_regs_16_23_by_one(DisasContext *ctx, int indx)
+{
+return 16 + (indx % 8);
+}
+static int to_regs_24_30_by_two(DisasContext *ctx, int indx)
+{
+return 24 + (indx % 4) * 2;
+}
+static int to_regs_00_30_by_two(DisasContext *ctx, int indx)
+{
+return (indx % 16) * 2;
+}
+
+static uint16_t next_word(DisasContext *ctx)
+{
+ctx->next_word_used = true;
+return ctx->next_word;
+}
+
+static int append_16(DisasContext *ctx, int x)
+{
+return x << 16 | next_word(ctx);
+}
+
+
+/* Include the auto-generated decoder.  */
+static bool decode_insn(DisasContext *ctx, uint16_t insn);
+#include "decode_insn.inc.c"
+
+#define output(mnemonic, format, ...) \
+(pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \
+mnemonic, ##__VA_ARGS__))
+
+int avr_print_insn(bfd_vma addr, disassemble_info *info)
+{
+DisasContext ctx;
+DisasContext *pctx = 
+bfd_byte buffer[4];
+uint16_t insn;
+int status;
+
+ctx.info = info;
+
+status = info->read_memory_func(addr, buffer, 4, info);
+if (status != 0) {
+info->memory_error_func(status, addr, info);
+return -1;
+}
+insn = bfd_getl16(buffer);
+ctx.next_word = bfd_getl16(buffer + 2);
+ctx.next_word_used = false;
+
+if (!decode_insn(, insn)) {
+output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]);
+}
+
+return ctx.next_word_used ? 4 : 2;
+}
+
+
+#define INSN(opcode, format, ...)   \
+static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a)\
+{  

[PATCH v41 12/21] hw/avr: Add limited support for 16 bit timer peripheral

[Michael Rolnik]

These were designed to facilitate testing but should provide enough function to 
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to 
the lack of a standard way to handle electrical connections (like GPIO pins).

Signed-off-by: Sarah Harris 
---
 include/hw/timer/avr_timer16.h |  94 +
 hw/timer/avr_timer16.c | 602 +
 hw/timer/Kconfig   |   3 +
 hw/timer/Makefile.objs |   2 +
 4 files changed, 701 insertions(+)
 create mode 100644 include/hw/timer/avr_timer16.h
 create mode 100644 hw/timer/avr_timer16.c

diff --git a/include/hw/timer/avr_timer16.h b/include/hw/timer/avr_timer16.h
new file mode 100644
index 00..4ae0c64a34
--- /dev/null
+++ b/include/hw/timer/avr_timer16.h
@@ -0,0 +1,94 @@
+/*
+ * AVR 16 bit timer
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Ed Robbins
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * 
+ */
+
+/*
+ * Driver for 16 bit timers on 8 bit AVR devices.
+ * Note:
+ * On ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
+ */
+
+#ifndef AVR_TIMER16_H
+#define AVR_TIMER16_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/hw.h"
+
+enum NextInterrupt {
+OVERFLOW,
+COMPA,
+COMPB,
+COMPC,
+CAPT
+};
+
+#define TYPE_AVR_TIMER16 "avr-timer16"
+#define AVR_TIMER16(obj) \
+OBJECT_CHECK(AVRTimer16State, (obj), TYPE_AVR_TIMER16)
+
+typedef struct AVRTimer16State {
+/*  */
+SysBusDevice parent_obj;
+
+/*  */
+MemoryRegion iomem;
+MemoryRegion imsk_iomem;
+MemoryRegion ifr_iomem;
+QEMUTimer *timer;
+qemu_irq capt_irq;
+qemu_irq compa_irq;
+qemu_irq compb_irq;
+qemu_irq compc_irq;
+qemu_irq ovf_irq;
+
+bool enabled;
+
+/* registers */
+uint8_t cra;
+uint8_t crb;
+uint8_t crc;
+uint8_t cntl;
+uint8_t cnth;
+uint8_t icrl;
+uint8_t icrh;
+uint8_t ocral;
+uint8_t ocrah;
+uint8_t ocrbl;
+uint8_t ocrbh;
+uint8_t ocrcl;
+uint8_t ocrch;
+/*
+ * Reads and writes to CNT and ICR utilise a bizarre temporary
+ * register, which we emulate
+ */
+uint8_t rtmp;
+uint8_t imsk;
+uint8_t ifr;
+
+uint8_t id;
+uint64_t cpu_freq_hz;
+uint64_t freq_hz;
+uint64_t period_ns;
+uint64_t reset_time_ns;
+enum NextInterrupt next_interrupt;
+} AVRTimer16State;
+
+#endif /* AVR_TIMER16_H */
diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c
new file mode 100644
index 00..aea1bf009e
--- /dev/null
+++ b/hw/timer/avr_timer16.c
@@ -0,0 +1,602 @@
+/*
+ * AVR 16 bit timer
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Ed Robbins
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * 
+ */
+
+/*
+ * Driver for 16 bit timers on 8 bit AVR devices.
+ * Note:
+ * ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
+ */
+
+/*
+ * XXX TODO: Power Reduction Register support
+ *   prescaler pause support
+ *   PWM modes, GPIO, output capture pins, input compare pin
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/avr_timer16.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+/* Register offsets */
+#define T16_CRA 0x0
+#define T16_CRB 0x1
+#define T16_CRC 0x2
+#define T16_CNTL0x4
+#define T16_CNTH0x5
+#define T16_ICRL0x6
+#define T16_ICRH0x7
+#define T16_OCRAL   0x8
+#define T16_OCRAH   0x9
+#define T16_OCRBL   0xa
+#define T16_OCRBH   0xb
+#define T16_OCRCL   0xc
+#define T16_OCRCH   0xd
+
+/* Field masks */
+#define T16_CRA_WGM01   0x3
+#define T16_CRA_COMC0xc
+#define T16_CRA_COMB

[PATCH v41 05/21] target/avr: Add instruction translation - Branch Instructions

[Michael Rolnik]

This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 533 +
 target/avr/insn.decode |  24 ++
 2 files changed, 557 insertions(+)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 00fb3f5350..475f502e72 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -921,3 +921,536 @@ static bool trans_DES(DisasContext *ctx, arg_DES *a)
 
 return true;
 }
+
+/*
+ * Branch Instructions
+ */
+static void gen_jmp_ez(DisasContext *ctx)
+{
+tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
+tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
+ctx->bstate = DISAS_LOOKUP;
+}
+
+static void gen_jmp_z(DisasContext *ctx)
+{
+tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
+ctx->bstate = DISAS_LOOKUP;
+}
+
+static void gen_push_ret(DisasContext *ctx, int ret)
+{
+if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
+
+TCGv t0 = tcg_const_i32((ret & 0xff));
+
+tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
+tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+tcg_temp_free_i32(t0);
+} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
+
+TCGv t0 = tcg_const_i32((ret & 0x00));
+
+tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+tcg_temp_free_i32(t0);
+
+} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
+
+TCGv lo = tcg_const_i32((ret & 0xff));
+TCGv hi = tcg_const_i32((ret & 0x00) >> 8);
+
+tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
+tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
+tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+tcg_temp_free_i32(lo);
+tcg_temp_free_i32(hi);
+}
+}
+
+static void gen_pop_ret(DisasContext *ctx, TCGv ret)
+{
+if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
+tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
+} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
+tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
+TCGv lo = tcg_temp_new_i32();
+TCGv hi = tcg_temp_new_i32();
+
+tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+
+tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
+tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
+
+tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
+
+tcg_temp_free_i32(lo);
+tcg_temp_free_i32(hi);
+}
+}
+
+static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+{
+TranslationBlock *tb = ctx->tb;
+
+if (ctx->singlestep == 0) {
+tcg_gen_goto_tb(n);
+tcg_gen_movi_i32(cpu_pc, dest);
+tcg_gen_exit_tb(tb, n);
+} else {
+tcg_gen_movi_i32(cpu_pc, dest);
+gen_helper_debug(cpu_env);
+tcg_gen_exit_tb(NULL, 0);
+}
+ctx->bstate = DISAS_NORETURN;
+}
+
+/*
+ *  Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
+ *  AVR microcontrollers with Program memory not exceeding 4K words (8KB) this
+ *  instruction can address the entire memory from every address location. See
+ *  also JMP.
+ */
+static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a)
+{
+int dst = ctx->npc + a->imm;
+
+gen_goto_tb(ctx, 0, dst);
+
+return true;
+}
+
+/*
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File. The Z-pointer Register is 16 bits wide and
+ *  allows jump within the lowest 64K words (128KB) section of Program memory.
+ *  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
+{
+if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
+return true;
+}
+
+gen_jmp_z(ctx);
+
+return true;
+}
+
+/*
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File and the EIND Register in the I/O space. This
+ *  instruction allows for indirect jumps to the entire 4M (words) Program
+ *  memory space. See also IJMP.  This instruction is not available in all
+ *  devices. Refer to the device specific instruction set summary.
+ */
+static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
+{
+if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
+return true;
+}

[PATCH v41 09/21] target/avr: Add instruction translation - CPU main translation function

[Michael Rolnik]

Co-developed-by: Richard Henderson 
Co-developed-by: Michael Rolnik 

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 234 +
 1 file changed, 234 insertions(+)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 4c680070e2..af88bb2e5a 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2749,3 +2749,237 @@ static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
 
 return true;
 }
+
+
+void avr_cpu_tcg_init(void)
+{
+int i;
+
+#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
+cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
+cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
+cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
+cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
+cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
+cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
+cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
+cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
+cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
+cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
+cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
+cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
+cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
+cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
+cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
+cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+
+for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
+cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+  reg_names[i]);
+}
+#undef AVR_REG_OFFS
+}
+
+static void translate(DisasContext *ctx)
+{
+uint32_t opcode = next_word(ctx);
+
+if (!decode_insn(ctx, opcode)) {
+gen_helper_unsupported(cpu_env);
+ctx->bstate = DISAS_NORETURN;
+}
+}
+
+/* Standardize the cpu_skip condition to NE.  */
+static bool canonicalize_skip(DisasContext *ctx)
+{
+switch (ctx->skip_cond) {
+case TCG_COND_NEVER:
+/* Normal case: cpu_skip is known to be false.  */
+return false;
+
+case TCG_COND_ALWAYS:
+/*
+ * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP.
+ * The breakpoint is on the instruction being skipped, at the start
+ * of the TranslationBlock.  No need to update.
+ */
+return false;
+
+case TCG_COND_NE:
+if (ctx->skip_var1 == NULL) {
+tcg_gen_mov_tl(cpu_skip, ctx->skip_var0);
+} else {
+tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1);
+ctx->skip_var1 = NULL;
+}
+break;
+
+default:
+/* Convert to a NE condition vs 0. */
+if (ctx->skip_var1 == NULL) {
+tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0);
+} else {
+tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip,
+   ctx->skip_var0, ctx->skip_var1);
+ctx->skip_var1 = NULL;
+}
+ctx->skip_cond = TCG_COND_NE;
+break;
+}
+if (ctx->free_skip_var0) {
+tcg_temp_free(ctx->skip_var0);
+ctx->free_skip_var0 = false;
+}
+ctx->skip_var0 = cpu_skip;
+return true;
+}
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
+{
+CPUAVRState *env = cs->env_ptr;
+DisasContext ctx = {
+.tb = tb,
+.cs = cs,
+.env = env,
+.memidx = 0,
+.bstate = DISAS_NEXT,
+.skip_cond = TCG_COND_NEVER,
+.singlestep = cs->singlestep_enabled,
+};
+target_ulong pc_start = tb->pc / 2;
+int num_insns = 0;
+
+if (tb->flags & TB_FLAGS_FULL_ACCESS) {
+/*
+ * This flag is set by ST/LD instruction we will regenerate it ONLY
+ * with mem/cpu memory access instead of mem access
+ */
+max_insns = 1;
+}
+if (ctx.singlestep) {
+max_insns = 1;
+}
+
+gen_tb_start(tb);
+
+ctx.npc = pc_start;
+if (tb->flags & TB_FLAGS_SKIP) {
+ctx.skip_cond = TCG_COND_ALWAYS;
+ctx.skip_var0 = cpu_skip;
+}
+
+do {
+TCGLabel *skip_label = NULL;
+
+/* translate current instruction */
+tcg_gen_insn_start(ctx.npc);
+num_insns++;
+
+/*
+ * this is due to s

[PATCH v41 04/21] target/avr: Add instruction translation - Arithmetic and Logic Instructions

[Michael Rolnik]

This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 751 +
 target/avr/insn.decode |  93 +
 2 files changed, 844 insertions(+)
 create mode 100644 target/avr/insn.decode

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 241083dc2d..00fb3f5350 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -170,3 +170,754 @@ static bool avr_have_feature(DisasContext *ctx, int 
feature)
 static bool decode_insn(DisasContext *ctx, uint16_t insn);
 #include "decode_insn.inc.c"
 
+/*
+ * Arithmetic Instructions
+ */
+
+static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+TCGv t3 = tcg_temp_new_i32();
+
+tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
+tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
+tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
+tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
+tcg_gen_or_tl(t1, t1, t3);
+tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
+tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+
+/* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */
+/*= (Rd ^ R) & ~(Rd ^ Rr) */
+tcg_gen_xor_tl(t1, Rd, R);
+tcg_gen_xor_tl(t2, Rd, Rr);
+tcg_gen_andc_tl(t1, t1, t2);
+tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+TCGv t3 = tcg_temp_new_i32();
+
+tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
+tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
+tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
+tcg_gen_and_tl(t3, t3, R);
+tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
+tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
+tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+
+/* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */
+/*= (Rd ^ R) & (Rd ^ R) */
+tcg_gen_xor_tl(t1, Rd, R);
+tcg_gen_xor_tl(t2, Rd, Rr);
+tcg_gen_and_tl(t1, t1, t2);
+tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_NSf(TCGv R)
+{
+tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+
+static void gen_ZNSf(TCGv R)
+{
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+/*
+ *  Adds two registers without the C Flag and places the result in the
+ *  destination register Rd.
+ */
+static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
+tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+/* update status register */
+gen_add_CHf(R, Rd, Rr);
+gen_add_Vf(R, Rd, Rr);
+gen_ZNSf(R);
+/* update output registers */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+/*
+ *  Adds two registers and the contents of the C Flag and places the result in
+ *  the destination register Rd.
+ */
+static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
+tcg_gen_add_tl(R, R, cpu_Cf);
+tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+/* update status register */
+gen_add_CHf(R, Rd, Rr);
+gen_add_Vf(R, Rd, Rr);
+gen_ZNSf(R);
+/* update output registers */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+/*
+ *  Adds an immediate value (0 - 63) to a register pair and places the result
+ *  in the register pair. This instruction operates on the upper four register
+ *  pairs, and is well suited for operations on the pointer registers.  This
+ *  instruction is not available in all devices. Refer to the device s

[PATCH v41 03/21] target/avr: Add instruction translation - Registers definition

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 172 +
 1 file changed, 172 insertions(+)
 create mode 100644 target/avr/translate.c

diff --git a/target/avr/translate.c b/target/avr/translate.c
new file mode 100644
index 00..241083dc2d
--- /dev/null
+++ b/target/avr/translate.c
@@ -0,0 +1,172 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/qemu-print.h"
+#include "tcg/tcg.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "tcg/tcg-op.h"
+#include "exec/cpu_ldst.h"
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+#include "exec/log.h"
+#include "exec/translator.h"
+#include "exec/gen-icount.h"
+
+/*
+ *  Define if you want a BREAK instruction translated to a breakpoint
+ *  Active debugging connection is assumed
+ *  This is for
+ *  https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
+ *  tests
+ */
+#undef BREAKPOINT_ON_BREAK
+
+static TCGv cpu_pc;
+
+static TCGv cpu_Cf;
+static TCGv cpu_Zf;
+static TCGv cpu_Nf;
+static TCGv cpu_Vf;
+static TCGv cpu_Sf;
+static TCGv cpu_Hf;
+static TCGv cpu_Tf;
+static TCGv cpu_If;
+
+static TCGv cpu_rampD;
+static TCGv cpu_rampX;
+static TCGv cpu_rampY;
+static TCGv cpu_rampZ;
+
+static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS];
+static TCGv cpu_eind;
+static TCGv cpu_sp;
+
+static TCGv cpu_skip;
+
+static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = {
+"r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
+"r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
+"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+};
+#define REG(x) (cpu_r[x])
+
+enum {
+DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main loop.  */
+DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition exit.  */
+DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.  */
+};
+
+typedef struct DisasContext DisasContext;
+
+/* This is the state at translation time. */
+struct DisasContext {
+TranslationBlock *tb;
+
+CPUAVRState *env;
+CPUState *cs;
+
+target_long npc;
+uint32_t opcode;
+
+/* Routine used to access memory */
+int memidx;
+int bstate;
+int singlestep;
+
+/*
+ * some AVR instructions can make the following instruction to be skipped
+ * Let's name those instructions
+ * A   - instruction that can skip the next one
+ * B   - instruction that can be skipped. this depends on execution of 
A
+ * there are two scenarios
+ * 1. A and B belong to the same translation block
+ * 2. A is the last instruction in the translation block and B is the last
+ *
+ * following variables are used to simplify the skipping logic, they are
+ * used in the following manner (sketch)
+ *
+ * TCGLabel *skip_label = NULL;
+ * if (ctx.skip_cond != TCG_COND_NEVER) {
+ * skip_label = gen_new_label();
+ * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label);
+ * }
+ *
+ * if (free_skip_var0) {
+ * tcg_temp_free(skip_var0);
+ * free_skip_var0 = false;
+ * }
+ *
+ * translate();
+ *
+ * if (skip_label) {
+ * gen_set_label(skip_label);
+ * }
+ */
+TCGv skip_var0;
+TCGv skip_var1;
+TCGCond skip_cond;
+bool free_skip_var0;
+};
+
+static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
+{
+return 16 + (indx % 16);
+}
+
+static int to_regs_16_23_by_one(DisasContext *ctx, int indx)
+{
+return 16 + (indx % 8);
+}
+static int to_regs_24_30_by_two(DisasContext *ctx, int indx)
+{
+return 24 + (indx % 4) * 2;
+}
+static int to_regs

[PATCH v41 08/21] target/avr: Add instruction translation - MCU Control Instructions

[Michael Rolnik]

This includes:
- BREAK
- NOP
- SLEEP
- WDR

Signed-off-by: Michael Rolnik 
---
 target/avr/translate.c | 68 ++
 target/avr/insn.decode |  9 ++
 2 files changed, 77 insertions(+)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 58775af17c..4c680070e2 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2681,3 +2681,71 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
 
 return true;
 }
+
+/*
+ * MCU Control Instructions
+ */
+
+/*
+ *  The BREAK instruction is used by the On-chip Debug system, and is
+ *  normally not used in the application software. When the BREAK instruction 
is
+ *  executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ *  Debugger access to internal resources.  If any Lock bits are set, or either
+ *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ *  instruction as a NOP and will not enter the Stopped mode.  This instruction
+ *  is not available in all devices. Refer to the device specific instruction
+ *  set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+return true;
+}
+
+#ifdef BREAKPOINT_ON_BREAK
+tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+gen_helper_debug(cpu_env);
+ctx->bstate = DISAS_EXIT;
+#else
+/* NOP */
+#endif
+
+return true;
+}
+
+
+/*
+ *  This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+/* NOP */
+
+return true;
+}
+
+
+/*
+ *  This instruction sets the circuit in sleep mode defined by the MCU
+ *  Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+gen_helper_sleep(cpu_env);
+ctx->bstate = DISAS_NORETURN;
+return true;
+}
+
+
+/*
+ *  This instruction resets the Watchdog Timer. This instruction must be
+ *  executed within a limited time given by the WD prescaler. See the Watchdog
+ *  Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+gen_helper_wdr(cpu_env);
+
+return true;
+}
diff --git a/target/avr/insn.decode b/target/avr/insn.decode
index 4ee55862b2..0e4ec9ddf0 100644
--- a/target/avr/insn.decode
+++ b/target/avr/insn.decode
@@ -172,3 +172,12 @@ BST  101 rd:5 0 bit:3
 BLD  100 rd:5 0 bit:3
 BSET1001 0100 0 bit:3 1000
 BCLR1001 0100 1 bit:3 1000
+
+#
+# MCU Control Instructions
+#
+BREAK   1001 0101 1001 1000
+NOP    
+SLEEP   1001 0101 1000 1000
+WDR 1001 0101 1010 1000
+
-- 
2.17.2 (Apple Git-113)

[PATCH v41 02/21] target/avr: Add instruction helpers

[Michael Rolnik]

Stubs for unimplemented instructions and helpers for instructions that need to 
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex 
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to 
generate wake interrupts.
Memory access instructions are implemented here because some address ranges 
actually refer to CPU registers.

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/helper.h |  29 
 target/avr/helper.c | 347 
 2 files changed, 376 insertions(+)
 create mode 100644 target/avr/helper.h
 create mode 100644 target/avr/helper.c

diff --git a/target/avr/helper.h b/target/avr/helper.h
new file mode 100644
index 00..bf087504a8
--- /dev/null
+++ b/target/avr/helper.h
@@ -0,0 +1,29 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+DEF_HELPER_1(wdr, void, env)
+DEF_HELPER_1(debug, void, env)
+DEF_HELPER_1(break, void, env)
+DEF_HELPER_1(sleep, void, env)
+DEF_HELPER_1(unsupported, void, env)
+DEF_HELPER_3(outb, void, env, i32, i32)
+DEF_HELPER_2(inb, tl, env, i32)
+DEF_HELPER_3(fullwr, void, env, i32, i32)
+DEF_HELPER_2(fullrd, tl, env, i32)
diff --git a/target/avr/helper.c b/target/avr/helper.c
new file mode 100644
index 00..c43a4b7340
--- /dev/null
+++ b/target/avr/helper.c
@@ -0,0 +1,347 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+
+bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+bool ret = false;
+CPUClass *cc = CPU_GET_CLASS(cs);
+AVRCPU *cpu = AVR_CPU(cs);
+CPUAVRState *env = >env;
+
+if (interrupt_request & CPU_INTERRUPT_RESET) {
+if (cpu_interrupts_enabled(env)) {
+cs->exception_index = EXCP_RESET;
+cc->do_interrupt(cs);
+
+cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
+
+ret = true;
+}
+}
+if (interrupt_request & CPU_INTERRUPT_HARD) {
+if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
+int index = ctz32(env->intsrc);
+cs->exception_index = EXCP_INT(index);
+cc->do_interrupt(cs);
+
+env->intsrc &= env->intsrc - 1; /* clear the interrupt */
+cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+
+ret = true;
+}
+}
+return ret;
+}
+
+void avr_cpu_do_interrupt(CPUState *cs)
+{
+AVRCPU *cpu = AVR_CPU(cs);
+CPUAVRState *env = >env;
+
+uint32_t ret = env->pc_w;
+int vector = 0;
+int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
+int base = 0;
+
+if (cs->exception_index == EXCP_RESET) {
+vector = 0;
+} else if (env->intsrc != 0) {
+vector = ctz32(env->intsrc) + 1;
+}
+
+if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
+cpu_stb_data(env, env->sp--, (ret & 0xff));
+cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
+cpu_stb_data(env, env->sp--, (ret & 0xff) >> 16);
+} else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
+cpu_stb_data(env, env->sp--, (ret & 0xff));
+cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
+} else {
+cpu_stb_data(env, env->sp--, (ret & 0xff));
+}
+
+env-&g

[PATCH v41 06/21] target/avr: Add instruction translation - Data Transfer Instructions

[Michael Rolnik]

This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT

Signed-off-by: Michael Rolnik 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/translate.c | 986 +
 target/avr/insn.decode |  43 ++
 2 files changed, 1029 insertions(+)

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 475f502e72..4a62d9312a 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1454,3 +1454,989 @@ static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
 return true;
 }
 
+/*
+ * Data Transfer Instructions
+ */
+
+/*
+ *  in the gen_set_addr & gen_get_addr functions
+ *  H assumed to be in 0x00ff format
+ *  M assumed to be in 0x00ff format
+ *  L assumed to be in 0x00ff format
+ */
+static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
+{
+
+tcg_gen_andi_tl(L, addr, 0x00ff);
+
+tcg_gen_andi_tl(M, addr, 0xff00);
+tcg_gen_shri_tl(M, M, 8);
+
+tcg_gen_andi_tl(H, addr, 0x00ff);
+}
+
+static void gen_set_xaddr(TCGv addr)
+{
+gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
+}
+
+static void gen_set_yaddr(TCGv addr)
+{
+gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
+}
+
+static void gen_set_zaddr(TCGv addr)
+{
+gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
+}
+
+static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
+{
+TCGv addr = tcg_temp_new_i32();
+
+tcg_gen_deposit_tl(addr, M, H, 8, 8);
+tcg_gen_deposit_tl(addr, L, addr, 8, 16);
+
+return addr;
+}
+
+static TCGv gen_get_xaddr(void)
+{
+return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
+}
+
+static TCGv gen_get_yaddr(void)
+{
+return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
+}
+
+static TCGv gen_get_zaddr(void)
+{
+return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
+}
+
+/*
+ *  Load one byte indirect from data space to register and stores an clear
+ *  the bits in data space specified by the register. The instruction can only
+ *  be used towards internal SRAM.  The data location is pointed to by the Z 
(16
+ *  bits) Pointer Register in the Register File. Memory access is limited to 
the
+ *  current data segment of 64KB. To access another data segment in devices 
with
+ *  more than 64KB data space, the RAMPZ in register in the I/O area has to be
+ *  changed.  The Z-pointer Register is left unchanged by the operation. This
+ *  instruction is especially suited for clearing status bits stored in SRAM.
+ */
+static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
+{
+if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
+gen_helper_fullwr(cpu_env, data, addr);
+} else {
+tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
+}
+}
+
+static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
+{
+if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
+gen_helper_fullrd(data, cpu_env, addr);
+} else {
+tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
+}
+}
+
+/*
+ *  This instruction makes a copy of one register into another. The source
+ *  register Rr is left unchanged, while the destination register Rd is loaded
+ *  with a copy of Rr.
+ */
+static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+
+tcg_gen_mov_tl(Rd, Rr);
+
+return true;
+}
+
+/*
+ *  This instruction makes a copy of one register pair into another register
+ *  pair. The source register pair Rr+1:Rr is left unchanged, while the
+ *  destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.  This
+ *  instruction is not available in all devices. Refer to the device specific
+ *  instruction set summary.
+ */
+static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
+{
+if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
+return true;
+}
+
+TCGv RdL = cpu_r[a->rd];
+TCGv RdH = cpu_r[a->rd + 1];
+TCGv RrL = cpu_r[a->rr];
+TCGv RrH = cpu_r[a->rr + 1];
+
+tcg_gen_mov_tl(RdH, RrH);
+tcg_gen_mov_tl(RdL, RrL);
+
+return true;
+}
+
+/*
+ * Loads an 8 bit constant directly to register 16 to 31.
+ */
+static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
+{
+TCGv Rd = cpu_r[a->rd];
+int imm = a->imm;
+
+tcg_gen_movi_tl(Rd, imm);
+
+return true;
+}
+
+/*
+ *  Loads one byte from the data space to a register. For parts with SRAM,
+ *  the data space consists of the Register File, I/O memory and internal SRAM
+ *  (and external SRAM if applicable). For parts without SRAM, the data space
+ *  consists of the register file only. The EEPROM has a separate address 
space.
+ *  A 16-bit address must be supplied. Memory access is limited to the current
+ *  data segment of 64KB. The LDS instruction uses the RAMPD Regi

[PATCH v41 14/21] hw/avr: Add example board configuration

[Michael Rolnik]

A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs 
include a lot of on-board peripherals.

NOTE: this is not a real board 
NOTE: it's used for CPU testing

Signed-off-by: Michael Rolnik 
Reviewed-by: Aleksandar Markovic 
Nacked-by: Philippe Mathieu-Daudé 
---
 include/elf.h|   2 +
 include/hw/elf_ops.h |   6 +-
 include/hw/loader.h  |   6 +-
 hw/avr/sample.c  | 295 +++
 hw/core/loader.c |  15 ++-
 hw/riscv/boot.c  |   2 +-
 hw/Kconfig   |   1 +
 hw/avr/Kconfig   |   6 +
 hw/avr/Makefile.objs |   1 +
 9 files changed, 323 insertions(+), 11 deletions(-)
 create mode 100644 hw/avr/sample.c
 create mode 100644 hw/avr/Kconfig
 create mode 100644 hw/avr/Makefile.objs

diff --git a/include/elf.h b/include/elf.h
index 3501e0c8d0..53cdfa23b7 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -202,6 +202,8 @@ typedef struct mips_elf_abiflags_v0 {
 #define EM_MOXIE   223 /* Moxie processor family */
 #define EM_MOXIE_OLD   0xFEED
 
+#define EM_AVR 83 /* AVR 8-bit microcontroller */
+
 /* This is the info that is needed to parse the dynamic section of the file */
 #define DT_NULL0
 #define DT_NEEDED  1
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index e07d276df7..70de85fa72 100644
--- a/include/hw/elf_ops.h
+++ b/include/hw/elf_ops.h
@@ -316,7 +316,8 @@ static int glue(load_elf, SZ)(const char *name, int fd,
   void *translate_opaque,
   int must_swab, uint64_t *pentry,
   uint64_t *lowaddr, uint64_t *highaddr,
-  int elf_machine, int clear_lsb, int data_swab,
+  uint32_t *pe_flags, int elf_machine,
+  int clear_lsb, int data_swab,
   AddressSpace *as, bool load_rom,
   symbol_fn_t sym_cb)
 {
@@ -594,6 +595,9 @@ static int glue(load_elf, SZ)(const char *name, int fd,
 }
 }
 
+if (pe_flags) {
+*pe_flags = (uint32_t)(elf_sword)ehdr.e_flags;
+}
 if (lowaddr)
 *lowaddr = (uint64_t)(elf_sword)low;
 if (highaddr)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 48a96cd559..22b59e15ba 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -101,6 +101,7 @@ const char *load_elf_strerror(int error);
  * @pentry: Populated with program entry point. Ignored if NULL.
  * @lowaddr: Populated with lowest loaded address. Ignored if NULL.
  * @highaddr: Populated with highest loaded address. Ignored if NULL.
+ * @pe_flags: Populated with e_flags. Ignore if NULL.
  * @bigendian: Expected ELF endianness. 0 for LE otherwise BE
  * @elf_machine: Expected ELF machine type
  * @clear_lsb: Set to mask off LSB of addresses (Some architectures use
@@ -131,8 +132,9 @@ int load_elf_ram_sym(const char *filename,
  uint64_t (*elf_note_fn)(void *, void *, bool),
  uint64_t (*translate_fn)(void *, uint64_t),
  void *translate_opaque, uint64_t *pentry,
- uint64_t *lowaddr, uint64_t *highaddr, int big_endian,
- int elf_machine, int clear_lsb, int data_swab,
+ uint64_t *lowaddr, uint64_t *highaddr, uint32_t *pe_flags,
+ int big_endian, int elf_machine,
+ int clear_lsb, int data_swab,
  AddressSpace *as, bool load_rom, symbol_fn_t sym_cb);
 
 /** load_elf_ram:
diff --git a/hw/avr/sample.c b/hw/avr/sample.c
new file mode 100644
index 00..95094a8d6c
--- /dev/null
+++ b/hw/avr/sample.c
@@ -0,0 +1,295 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+/*
+ *  NOTE:
+ *  This is not a real AVR board, this is an example!
+ *  The CPU is an approximation of an ATmega2560, but is missing various
+ *  built-in peripherals.
+ *
+ *  This example board loads provided binary file into flash memory and
+ *  executes it from 0x address in the code memory space.
+ *
+ *  Currently used for AVR CPU validation
+ *
+ */
+
+#i

[PATCH v41 00/21] QEMU AVR 8 bit cores

[Michael Rolnik]

 instead of `master`` in avocado test

changes since v37
1.  rebase
2.  moving all data transfer instructions into a separate commit
3.  splitting tests into 
1.  avocado test
2.  boot serial test
3.  machine none test
4.  split periperals commit into 
1.  timer
2.  usart
3.  mask
5.  add function `avr_flags_to_cpu_type` that translates ELF flags into core 
name
6.  add avrtiny, xmega3 cores
7.  remove unnecessary includes from target/avr/helper.c file
8.  remove empty lines from target/avr/translate.c file
9.  set number of interrupt lines to 64
10. determine cpu type by reading ELF flags
11. update license of all new files to be LGPL
12. udpate QEMU documentation

changes since v38
1.  rebase
2.  add examples of AVR emulator invokation into the QEMU doc
3.  reorder instructions to match AVR documentation
4.  fix elf loader function bug introduced by prev version

changes since v39
1.  rename target/avr to hw/avr for hw related commits
2.  spread instruction decoding commit
3.  add frequency parameter to AVR timer

changes since v40
1.  rebase
2.  remove not necessary imports from avocado test

Michael Rolnik (21):
  target/avr: Add outward facing interfaces and core CPU logic
  target/avr: Add instruction helpers
  target/avr: Add instruction translation - Registers definition
  target/avr: Add instruction translation - Arithmetic and Logic
Instructions
  target/avr: Add instruction translation - Branch Instructions
  target/avr: Add instruction translation - Data Transfer Instructions
  target/avr: Add instruction translation - Bit and Bit-test
Instructions
  target/avr: Add instruction translation - MCU Control Instructions
  target/avr: Add instruction translation - CPU main translation
function
  target/avr: Add instruction disassembly function
  hw/avr: Add limited support for USART peripheral
  hw/avr: Add limited support for 16 bit timer peripheral
  hw/avr: Add dummy mask device
  hw/avr: Add example board configuration
  target/avr: Add section about AVR into QEMU documentation
  target/avr: Register AVR support with the rest of QEMU
  target/avr: Add machine none test
  target/avr: Update build system
  target/avr: Add boot serial test
  target/avr: Add Avocado test
  target/avr: Update MAINTAINERS file

 qemu-doc.texi|   51 +
 configure|7 +
 default-configs/avr-softmmu.mak  |5 +
 qapi/machine.json|3 +-
 include/disas/dis-asm.h  |   19 +
 include/elf.h|2 +
 include/hw/char/avr_usart.h  |   93 +
 include/hw/elf_ops.h |6 +-
 include/hw/loader.h  |6 +-
 include/hw/misc/avr_mask.h   |   47 +
 include/hw/timer/avr_timer16.h   |   94 +
 include/sysemu/arch_init.h   |1 +
 target/avr/cpu-param.h   |   37 +
 target/avr/cpu-qom.h |   54 +
 target/avr/cpu.h |  259 +++
 target/avr/helper.h  |   29 +
 arch_init.c  |2 +
 hw/avr/sample.c  |  295 +++
 hw/char/avr_usart.c  |  320 
 hw/core/loader.c |   15 +-
 hw/misc/avr_mask.c   |  112 ++
 hw/riscv/boot.c  |2 +-
 hw/timer/avr_timer16.c   |  602 ++
 target/avr/cpu.c |  826 
 target/avr/disas.c   |  245 +++
 target/avr/gdbstub.c |   84 +
 target/avr/helper.c  |  347 
 target/avr/machine.c |  121 ++
 target/avr/translate.c   | 2997 ++
 tests/qtest/boot-serial-test.c   |   10 +
 tests/qtest/machine-none-test.c  |1 +
 MAINTAINERS  |   21 +
 gdb-xml/avr-cpu.xml  |   49 +
 hw/Kconfig   |1 +
 hw/avr/Kconfig   |6 +
 hw/avr/Makefile.objs |1 +
 hw/char/Kconfig  |3 +
 hw/char/Makefile.objs|1 +
 hw/misc/Kconfig  |3 +
 hw/misc/Makefile.objs|2 +
 hw/timer/Kconfig |3 +
 hw/timer/Makefile.objs   |2 +
 target/avr/Makefile.objs |   34 +
 target/avr/insn.decode   |  183 ++
 tests/acceptance/machine_avr6.py |   53 +
 tests/qtest/Makefile.include |2 +
 46 files changed, 7044 insertions(+), 12 deletions(-)
 create mode 100644 default-configs/avr-softmmu.mak
 create mode 100644 include/hw/char/avr_usart.h
 create mode 100644 include/hw/misc/avr_mask.h
 create mode 100644 include/hw/timer/avr_timer16.h
 create mode 100644 target/avr/cpu-param.h
 create mode 100644 target/avr/cpu-qom.h
 create mode 100644 target/avr/cpu.h
 create mode 100644 target/avr/helper.h
 create mode 100644 hw/avr/sample.c
 create mode 100644 hw/char/avr_usart.c
 create mode 100644 hw/misc/avr_mask.c
 create mode 100644 hw/timer/avr_timer16.c
 create mode 100644 target/avr/cpu.c
 create mode 100644 target/avr/disas.c
 create mode 100644 targe

[PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

[Michael Rolnik]

This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks

Co-developed-by: Michael Rolnik 
Co-developed-by: Sarah Harris 
Signed-off-by: Michael Rolnik 
Signed-off-by: Sarah Harris 
Signed-off-by: Michael Rolnik 
Acked-by: Igor Mammedov 
Tested-by: Philippe Mathieu-Daudé 
---
 target/avr/cpu-param.h |  37 ++
 target/avr/cpu-qom.h   |  54 +++
 target/avr/cpu.h   | 258 +
 target/avr/cpu.c   | 826 +
 target/avr/gdbstub.c   |  84 +
 target/avr/machine.c   | 121 ++
 gdb-xml/avr-cpu.xml|  49 +++
 7 files changed, 1429 insertions(+)
 create mode 100644 target/avr/cpu-param.h
 create mode 100644 target/avr/cpu-qom.h
 create mode 100644 target/avr/cpu.h
 create mode 100644 target/avr/cpu.c
 create mode 100644 target/avr/gdbstub.c
 create mode 100644 target/avr/machine.c
 create mode 100644 gdb-xml/avr-cpu.xml

diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
new file mode 100644
index 00..0c29ce4223
--- /dev/null
+++ b/target/avr/cpu-param.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef AVR_CPU_PARAM_H
+#define AVR_CPU_PARAM_H
+
+#define TARGET_LONG_BITS 32
+/*
+ * TARGET_PAGE_BITS cannot be more than 8 bits because
+ * 1.  all IO registers occupy [0x .. 0x00ff] address range, and they
+ * should be implemented as a device and not memory
+ * 2.  SRAM starts at the address 0x0100
+ */
+#define TARGET_PAGE_BITS 8
+#define TARGET_PHYS_ADDR_SPACE_BITS 24
+#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define NB_MMU_MODES 2
+
+
+#endif
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
new file mode 100644
index 00..e28b58c897
--- /dev/null
+++ b/target/avr/cpu-qom.h
@@ -0,0 +1,54 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_QOM_H
+#define QEMU_AVR_QOM_H
+
+#include "hw/core/cpu.h"
+
+#define TYPE_AVR_CPU "avr-cpu"
+
+#define AVR_CPU_CLASS(klass) \
+OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
+#define AVR_CPU(obj) \
+OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
+#define AVR_CPU_GET_CLASS(obj) \
+OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
+
+/**
+ *  AVRCPUClass:
+ *  @parent_realize: The parent class' realize handler.
+ *  @parent_reset: The parent class' reset handler.
+ *  @vr: Version Register value.
+ *
+ *  A AVR CPU model.
+ */
+typedef struct AVRCPUClass {
+/*< private >*/
+CPUClass parent_class;
+/*< public >*/
+DeviceRealize parent_realize;
+void (*parent_reset)(CPUState *cpu);
+} AVRCPUClass;
+
+typedef struct AVRCPU AVRCPU;
+
+
+#endif /* !defined (QEMU_AVR_CPU_QOM_H) */
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
new file mode 100644
index 00..b74bcf01ae
--- /dev/null
+++ b/target/avr/cpu.h
@@ -0,0 +1,258 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License al

Re: [PATCH v40 00/21] QEMU AVR 8 bit cores

[Michael Rolnik]

Hi all,

any news?

Regards,
Michael Rolnik


On Sun, Dec 29, 2019 at 1:52 PM Michael Rolnik  wrote:

> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> tested yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This series of patches include a non real, sample board.
> No fuses support yet. PC is set to 0 at reset.
>
> Following are examples of possible usages, assuming program.elf is
> compiled for AVR cpu
> 1.  Continious non interrupted execution
> run `qemu-system-avr -kernel program.elf`
> 2.  Continious non interrupted execution with serial output into telnet
> window
> run `qemu-system-avr -kernel program.elf -serial
> tcp::5678,server,nowait -nographic `
> run `telent localhost 5678`
> 3.  Continious non interrupted execution with serial output into stdout
> run `qemu-system-avr -kernel program.elf -serial stdio`
> 4.  Debugging wit GDB debugger
> run `qemu-system-avr -kernel program.elf -s -S`
> run `avr-gdb program.elf` and then within GDB shell `target remote
> :1234`
> 5.  Print out executed instructions
> run `qemu-system-avr -kernel program.elf -d in_asm`
>
>
> the patches include the following
> 1. just a basic 8bit AVR CPU, without instruction decoding or translation
> 2. CPU features which allow define the following 8bit AVR cores
>  avr1
>  avr2 avr25
>  avr3 avr31 avr35
>  avr4
>  avr5 avr51
>  avr6
>  xmega2 xmega4 xmega5 xmega6 xmega7
> 3. a definition of sample machine with SRAM, FLASH and CPU which allows to
> execute simple code
> 4. encoding for all AVR instructions
> 5. interrupt handling
> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
> 7. a decoder which given an opcode decides what istruction it is
> 8. translation of AVR instruction into TCG
> 9. all features together
>
> changes since v3
> 1. rampD/X/Y/Z registers are encoded as 0x00ff (instead of 0x00ff)
> for faster address manipulaton
> 2. ffs changed to ctz32
> 3. duplicate code removed at avr_cpu_do_interrupt
> 4. using andc instead of not + and
> 5. fixing V flag calculation in varios instructions
> 6. freeing local variables in PUSH
> 7. tcg_const_local_i32 -> tcg_const_i32
> 8. using sextract32 instead of my implementation
> 9. fixing BLD instruction
> 10.xor(r) instead of 0xff - r at COM
> 11.fixing MULS/MULSU not to modify inputs' content
> 12.using SUB for NEG
> 13.fixing tcg_gen_qemu_ld/st call in XCH
>
> changes since v4
> 1. target is now defined as big endian in order to optimize
> push_ret/pop_ret
> 2. all style warnings are fixed
> 3. adding cpu_set/get_sreg functions
> 4. simplifying gen_goto_tb as there is no real paging
> 5. env->pc -> env->pc_w
> 6. making flag dump more compact
> 7. more spacing
> 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX
> 9. removing avr_set_feature
> 10. SPL/SPH set bug fix
> 11. switching stb_phys to cpu_stb_data
> 12. cleaning up avr_decode
> 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm)
> 14. saving CPU features (savevm)
>
> changes since v5
> 1. BLD bug fix
> 2. decoder generator is added
>
> chages since v6
> 1. using cpu_get_sreg/cpu_set_sreg in
> avr_cpu_gdb_read_register/avr_cpu_gdb_write_register
> 2. configure the target as little endian because otherwise GDB does not
> work
> 3. fixing and testing gen_push_ret/gen_pop_ret
>
> changes since v7
> 1. folding back v6
> 2. logging at helper_outb and helper_inb are done for non supported yet
> registers only
> 3. MAINTAINERS updated
>
> changes since v8
> 1. removing hw/avr from hw/Makefile.obj as it should not be built for all
> 2. making linux compilable
> 3. testing on
> a. Mac, Apple LLVM version 7.0.0
> b. Ubuntu 12.04, gcc 4.9.2
> c. Fedora 23, gcc 5.3.1
> 4. folding back some patches
> 5. translation bug fixes for ORI, CPI, XOR instructions
> 6. propper handling of cpu register writes though memory
>
> changes since v9
> 1. removing forward declarations of static functions
> 2. disabling debug prints
> 3. switching to case range instead of if else if ...
> 4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any
> device
> 5. commenst about sample board and sample IO device added
> 6. sample board description is more descriptive now
> 7. memory_region_allocate_system_memory is used to create RAM
> 8. now there are helper_fullrd & helper_fullwr when LD/ST try to access
> registers
>
> changes since v10
> 1. movig back fullwr & fullrd into the commit where outb and inb were
> introduced

Re: [PATCH v3 0/8] hw/avr: Introduce the Arduino boards

[Michael Rolnik]

Hi Philippe.

Thank you for joining the effort.

Regards,
Michael Rolnik


On Mon, Dec 30, 2019 at 12:45 AM Philippe Mathieu-Daudé 
wrote:

> Hi,
>
> This series add the arduino boards, aiming at removing the
> 'sample' board that doesn't follow any specification.
>
> Since v2:
> - rebased on Michael's v40
>
> Since v1:
> - Addressed Igor comments
> - Addressed Aleksandar comments
> - Fixed UART issue (was due to IRQ shifted by 2 in CPU)
>
> TODO after merge is:
> - Extract Timer8 common parts from Timer16
> - Add GPIOs
> - Connect LED to GPIO on Arduino
> - Plug to Scratch (See http://s4a.cat/).
>   (I plan to purpose that as a GSoC idea).
>
> Michael, thank you for having insisted with this port during so long!
>
> Regards,
>
> Phil.
>
> Series available at https://gitlab.com/philmd/qemu/commits/arduino-v3
>
> Regards,
>
> Phil.
>
> Based-on: <20191229215158.5788-1-mrol...@gmail.com>
> https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg05309.html
>
> Philippe Mathieu-Daudé (8):
>   hw/char/avr: Reduce USART I/O size
>   hw/timer/avr_timer16: Rename memory region debugging name
>   hw/avr: Add some ATmega microcontrollers
>   hw/avr: Add some Arduino boards
>   tests/boot-serial-test: Test some Arduino boards (AVR based)
>   tests/acceptance: Do not set the machine type manually
>   tests/acceptance: Keep multilines comment consistent with other tests
>   tests/acceptance: Test the Arduino MEGA2560 board
>
>  hw/avr/atmega.h  |  48 
>  hw/avr/arduino.c | 177 
>  hw/avr/atmega.c  | 464 +++
>  hw/char/avr_usart.c  |   2 +-
>  hw/timer/avr_timer16.c   |   6 +-
>  tests/boot-serial-test.c |   2 +
>  hw/avr/Makefile.objs |   2 +
>  tests/acceptance/machine_avr6.py |  11 +-
>  8 files changed, 701 insertions(+), 11 deletions(-)
>  create mode 100644 hw/avr/atmega.h
>  create mode 100644 hw/avr/arduino.c
>  create mode 100644 hw/avr/atmega.c
>
> --
> 2.21.0
>
>

-- 
Best Regards,
Michael Rolnik