Re: Question: SiFive U SPI and SD

2020-02-12 Thread Nikita Ermakov
Hello, Bin, Alistair,

Thank you for the answers!

On Thu, 13 Feb 2020 at 00:16, Alistair Francis  wrote:

> I had a crack at this awhile ago and you can see the patches here (I
> just rebased them):
> https://github.com/alistair23/qemu/tree/mainline/alistair/sifive_spi.next
>
> Debugging failures was really hard in Linux, but now that U-Boot and
> Oreboot (https://github.com/oreboot/oreboot/pull/234) have SPI support
> it is probably easier to debug.
>
> If you wanted to help you could try to debug that branch and figure
> out why it isn't working.
>
Thanks! I will try that.

-- 
Thanks,
Nikita
B8 00 4C CD 21


Question: SiFive U SPI and SD

2020-02-09 Thread Nikita Ermakov
Hello!

I am trying to make an SD card working on the sifive_u
(hw/riscv/sifive_u.c) SoC machine.
As far as I understand there is no way to connect an SD card to the SoC
with cmdline for now. So, I started to dig in to the QEMU internals and
especially sifive_u SoC implementation to try to understand how I could
connect SD card to this SoC.

>From what I understood I need to:
1) Implement SiFive U SPI controller.
2) Implement spi-sd adapter in a way like the hw/sd/ssi-sd.c

Probably I should merge 1) and 2) into one hw/riscv/sifive_u_spi.c source
file.

Could somebody correct me please if I am wrong at some point?
I am newbie in the QEMU internals :)

The purpose is why I want to implement this is to boot up the Linux kernel
on '-machine sifive_u' and load rootfs from SD.

-- 
Thanks,
Nikita
B8 00 4C CD 21


Re: Debugging heterogeneous SoC

2020-01-28 Thread Nikita Ermakov
On Wed, 29 Jan 2020 at 03:43, Alistair Francis  wrote:

> Use these commands to attach GDB to QEMU:
>
> target extended-remote :1234
> add-inferior
> inferior 2
> attach 2
> set schedule-multiple
> info threads
>
> Alistair
>
Thank you! It is worked! :)

-- 
Thanks,
Nikita
B8 00 4C CD 21


Debugging heterogeneous SoC

2020-01-28 Thread Nikita Ermakov
Hello,

I am trying to debug the sifive_u SoC in the QEMU with GDB.
SiFive Unleashed contains one E51 core and four U54 cores.
In the hw/riscv/sifve_u.c E51 and U54 cores are placed in the different CPU
clusters.
In the gdbstub.c, it is searches only the first cluster and it always finds
cluster with E51 core, if I understand it correctly.
In the GDB with `info threads` I could see only E51 core but none of the
U54 cores.

Is it possible to somehow get an access to another CPU cluster in the
GDB/QEMU?

-- 
Thanks,
Nikita
B8 00 4C CD 21