[Qemu-devel] Fixing Snowridge CPU model name and features
Changing the name to Snowridge from SnowRidge-Server.
There is no client model of Snowridge, so "-Server" is unnecessary.
Removing CPUID_EXT_VMX from Snowridge cpu feature list.
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
target/i386/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63d89276fe..7f56e887ae 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2688,7 +2688,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon Processor (Icelake)",
},
{
-.name = "SnowRidge-Server",
+.name = "Snowridge",
.level = 27,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
@@ -2706,7 +2706,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
-CPUID_EXT_VMX |
CPUID_EXT_SSSE3 |
CPUID_EXT_CX16 |
CPUID_EXT_SSE41 |
--
2.17.2
[Qemu-devel] Add SPLIT_LOCK DETECT capability to SnowRidge (SNR) cpu model
SPLIT_LOCK DETECT is enabled in qemu patch:
x86: define a new MSR based feature word -- FEAT_CORE_CAPABILITY
and kernel patch series that includes:
x86/split_lock: Align x86_capability to unsigned long to avoid split locked
access
WAITPKG (UMONITOR/UMWAIT/TPAUSE) supplied in:
x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE
are turned off by default, so not added to this cpu model.
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
Changes in v4:
Add SPLIT_LOCK DETECT capability to SnowRidge (SNR) cpu model
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c96f032f03..63d89276fe 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2739,7 +2739,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_ECX_MOVDIR64B,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL |
-CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
+CPUID_7_0_EDX_CORE_CAPABILITY,
+.features[FEAT_CORE_CAPABILITY] =
+MSR_CORE_CAP_SPLIT_LOCK_DETECT,
/*
* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
--
2.17.2
[Qemu-devel] [Qemu-devel v4] Introduce SnowRidge CPU model
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.
MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access
References can be found in either:
https://software.intel.com/en-us/articles/intel-sdm
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
Somehow v3 didn't have the desired -Server on the model name ...
---
target/i386/cpu.c | 68 +++
1 file changed, 68 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index da6eb67cfb..c96f032f03 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2687,6 +2687,74 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8008,
.model_id = "Intel Xeon Processor (Icelake)",
},
+{
+.name = "SnowRidge-Server",
+.level = 27,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 6,
+.model = 134,
+.stepping = 1,
+.features[FEAT_1_EDX] =
+/* missing: CPUID_PN CPUID_IA64 */
+/* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
+CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
+CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
+CPUID_CX8 | CPUID_APIC | CPUID_SEP |
+CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
+CPUID_MMX |
+CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
+.features[FEAT_1_ECX] =
+CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
+CPUID_EXT_VMX |
+CPUID_EXT_SSSE3 |
+CPUID_EXT_CX16 |
+CPUID_EXT_SSE41 |
+CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+CPUID_EXT_POPCNT |
+CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+CPUID_EXT_RDRAND,
+.features[FEAT_8000_0001_EDX] =
+CPUID_EXT2_SYSCALL |
+CPUID_EXT2_NX |
+CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+CPUID_EXT2_LM,
+.features[FEAT_8000_0001_ECX] =
+CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_3DNOWPREFETCH,
+.features[FEAT_7_0_EBX] =
+CPUID_7_0_EBX_FSGSBASE |
+CPUID_7_0_EBX_SMEP |
+CPUID_7_0_EBX_ERMS |
+CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
+CPUID_7_0_EBX_RDSEED |
+CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+CPUID_7_0_EBX_CLWB |
+CPUID_7_0_EBX_SHA_NI,
+.features[FEAT_7_0_ECX] =
+CPUID_7_0_ECX_UMIP |
+/* missing bit 5 */
+CPUID_7_0_ECX_GFNI |
+CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
+CPUID_7_0_ECX_MOVDIR64B,
+.features[FEAT_7_0_EDX] =
+CPUID_7_0_EDX_SPEC_CTRL |
+CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+/*
+ * Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+.features[FEAT_XSAVE] =
+CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+CPUID_XSAVE_XGETBV1,
+.features[FEAT_6_EAX] =
+CPUID_6_EAX_ARAT,
+.xlevel = 0x8008,
+.model_id = "Intel Atom Processor (SnowRidge)",
+},
{
.name = "KnightsMill",
.level = 0xd,
--
2.17.2
[Qemu-devel] [Qemu-devel v3] Introduce SnowRidge CPU model
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.
MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access
References can be found in either:
https://software.intel.com/en-us/articles/intel-sdm
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
We fix name to "SnowRidge-Server".
---
target/i386/cpu.c | 68 +++
1 file changed, 68 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index da6eb67cfb..868190673e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2687,6 +2687,74 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8008,
.model_id = "Intel Xeon Processor (Icelake)",
},
+{
+.name = "SnowRidge",
+.level = 27,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 6,
+.model = 134,
+.stepping = 1,
+.features[FEAT_1_EDX] =
+/* missing: CPUID_PN CPUID_IA64 */
+/* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
+CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
+CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
+CPUID_CX8 | CPUID_APIC | CPUID_SEP |
+CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
+CPUID_MMX |
+CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
+.features[FEAT_1_ECX] =
+CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
+CPUID_EXT_VMX |
+CPUID_EXT_SSSE3 |
+CPUID_EXT_CX16 |
+CPUID_EXT_SSE41 |
+CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+CPUID_EXT_POPCNT |
+CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+CPUID_EXT_RDRAND,
+.features[FEAT_8000_0001_EDX] =
+CPUID_EXT2_SYSCALL |
+CPUID_EXT2_NX |
+CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+CPUID_EXT2_LM,
+.features[FEAT_8000_0001_ECX] =
+CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_3DNOWPREFETCH,
+.features[FEAT_7_0_EBX] =
+CPUID_7_0_EBX_FSGSBASE |
+CPUID_7_0_EBX_SMEP |
+CPUID_7_0_EBX_ERMS |
+CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
+CPUID_7_0_EBX_RDSEED |
+CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+CPUID_7_0_EBX_CLWB |
+CPUID_7_0_EBX_SHA_NI,
+.features[FEAT_7_0_ECX] =
+CPUID_7_0_ECX_UMIP |
+/* missing bit 5 */
+CPUID_7_0_ECX_GFNI |
+CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
+CPUID_7_0_ECX_MOVDIR64B,
+.features[FEAT_7_0_EDX] =
+CPUID_7_0_EDX_SPEC_CTRL |
+CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+/*
+ * Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+.features[FEAT_XSAVE] =
+CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+CPUID_XSAVE_XGETBV1,
+.features[FEAT_6_EAX] =
+CPUID_6_EAX_ARAT,
+.xlevel = 0x8008,
+.model_id = "Intel Atom Processor (SnowRidge)",
+},
{
.name = "KnightsMill",
.level = 0xd,
--
2.17.2
[Qemu-devel] [Qemu-devel v2] Introduce SnowRidge CPU model
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.
MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access
References can be found in either:
https://software.intel.com/en-us/articles/intel-sdm
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
target/i386/cpu.c | 68 +++
1 file changed, 68 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d6bb57d210..1c03d9f6b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2663,6 +2663,74 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8008,
.model_id = "Intel Xeon Processor (Icelake)",
},
+{
+.name = "SnowRidge",
+.level = 27,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 6,
+.model = 134,
+.stepping = 1,
+.features[FEAT_1_EDX] =
+/* missing: CPUID_PN CPUID_IA64 */
+/* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
+CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
+CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
+CPUID_CX8 | CPUID_APIC | CPUID_SEP |
+CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
+CPUID_MMX |
+CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
+.features[FEAT_1_ECX] =
+CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
+CPUID_EXT_VMX |
+CPUID_EXT_SSSE3 |
+CPUID_EXT_CX16 |
+CPUID_EXT_SSE41 |
+CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+CPUID_EXT_POPCNT |
+CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+CPUID_EXT_RDRAND,
+.features[FEAT_8000_0001_EDX] =
+CPUID_EXT2_SYSCALL |
+CPUID_EXT2_NX |
+CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+CPUID_EXT2_LM,
+.features[FEAT_8000_0001_ECX] =
+CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_3DNOWPREFETCH,
+.features[FEAT_7_0_EBX] =
+CPUID_7_0_EBX_FSGSBASE |
+CPUID_7_0_EBX_SMEP |
+CPUID_7_0_EBX_ERMS |
+CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
+CPUID_7_0_EBX_RDSEED |
+CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+CPUID_7_0_EBX_CLWB |
+CPUID_7_0_EBX_SHA_NI,
+.features[FEAT_7_0_ECX] =
+CPUID_7_0_ECX_UMIP |
+/* missing bit 5 */
+CPUID_7_0_ECX_GFNI |
+CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
+CPUID_7_0_ECX_MOVDIR64B,
+.features[FEAT_7_0_EDX] =
+CPUID_7_0_EDX_SPEC_CTRL |
+CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+/*
+ * Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+.features[FEAT_XSAVE] =
+CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+CPUID_XSAVE_XGETBV1,
+.features[FEAT_6_EAX] =
+CPUID_6_EAX_ARAT,
+.xlevel = 0x8008,
+.model_id = "Intel Atom Processor (SnowRidge)",
+},
{
.name = "KnightsMill",
.level = 0xd,
--
2.17.2
[Qemu-devel] [PATCH] Introduce SnowRidge CPU model
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.
MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access
References can be found in either:
https://software.intel.com/en-us/articles/intel-sdm
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference
Signed-off-by: Paul Lai
Tested-by: Tao3 Xu
---
target/i386/cpu.c | 66 +++
1 file changed, 66 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d6bb57d210..e81da09709 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2663,6 +2663,72 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8008,
.model_id = "Intel Xeon Processor (Icelake)",
},
+{
+.name = "SnowRidge",
+.level = 27,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 6,
+.model = 134,
+.stepping = 1,
+.features[FEAT_1_EDX] =
+ /* missing: CPUID_PN CPUID_IA64 */
+/* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
+CPUID_FP87 | CPUID_VME | CPUID_DE| CPUID_PSE |
+CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
+CPUID_CX8 | CPUID_APIC | CPUID_SEP |
+CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+CPUID_PAT | CPUID_PSE36 | /* CPUID_PN | */ CPUID_CLFLUSH |
+CPUID_MMX |
+CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
+.features[FEAT_1_ECX] =
+CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
+CPUID_EXT_VMX |
+CPUID_EXT_SSSE3 |
+CPUID_EXT_CX16 |
+CPUID_EXT_SSE41 |
+CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
CPUID_EXT_POPCNT |
+CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+CPUID_EXT_RDRAND,
+.features[FEAT_8000_0001_EDX] =
+CPUID_EXT2_SYSCALL |
+CPUID_EXT2_NX |
+CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+CPUID_EXT2_LM,
+.features[FEAT_8000_0001_ECX] =
+CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_3DNOWPREFETCH,
+.features[FEAT_7_0_EBX] =
+CPUID_7_0_EBX_FSGSBASE |
+CPUID_7_0_EBX_SMEP |
+CPUID_7_0_EBX_ERMS |
+CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
+CPUID_7_0_EBX_RDSEED |
+CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+CPUID_7_0_EBX_CLWB |
+CPUID_7_0_EBX_SHA_NI,
+.features[FEAT_7_0_ECX] =
+CPUID_7_0_ECX_UMIP |
+/* missing bit 5 */
+CPUID_7_0_ECX_GFNI |
+CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
+CPUID_7_0_ECX_MOVDIR64B,
+.features[FEAT_7_0_EDX] =
+CPUID_7_0_EDX_SPEC_CTRL |
+CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, /*
missing bit 30 */
+/* Missing: XSAVES (not supported by some Linux versions,
+* including v4.1 to v4.12).
+* KVM doesn't yet expose any XSAVES state save component,
+* and the only one defined in Skylake (processor tracing)
+* probably will block migration anyway.
+*/
+.features[FEAT_XSAVE] =
+CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+CPUID_XSAVE_XGETBV1,
+.features[FEAT_6_EAX] =
+CPUID_6_EAX_ARAT,
+.xlevel = 0x8008,
+.model_id = "Intel Atom Processor (SnowRidge)",
+},
{
.name = "KnightsMill",
.level = 0xd,
--
2.17.2
