Re: [PATCH 04/13] cxl/mailbox: make range overlap check more readable
On 22/7/24 06:07, Yao Xingtao via wrote: use ranges_overlap() instead of open-coding the overlap check to improve the readability of the code. Signed-off-by: Yao Xingtao --- hw/cxl/cxl-mailbox-utils.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH 02/13] arm/boot: make range overlap check more readable
On 22/7/24 06:07, Yao Xingtao via wrote: use ranges_overlap() instead of open-coding the overlap check to improve the readability of the code. Signed-off-by: Yao Xingtao --- hw/arm/boot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index d480a7da02cf..a004a90e87be 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -26,6 +26,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "qemu/range.h" /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt @@ -238,8 +239,8 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); /* check that these blobs don't overlap */ -assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) - || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); +assert(!ranges_overlap(mvbar_addr, sizeof(mvbar_blob), + info->board_setup_addr, sizeof(board_setup_blob))); Indentation is of, otherwise: Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH 01/13] range: Make ranges_overlap() return bool
On 22/7/24 06:07, Yao Xingtao via wrote: Just like range_overlaps_range(), use the returned bool value to check whether 2 given ranges overlap. Signed-off-by: Yao Xingtao --- include/qemu/range.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 00/13] make range overlap check more readable
Hi Yao, On 22/7/24 06:07, Yao Xingtao via wrote: Currently, some components still open-coding the range overlap check. Sometimes this check may be fail because some patterns are missed. How did you catch all these use cases? To avoid the above problems and improve the readability of the code, it is better to use the ranges_overlap() to do this check. Yao Xingtao (13): range: Make ranges_overlap() return bool arm/boot: make range overlap check more readable core/loader: make range overlap check more readable cxl/mailbox: make range overlap check more readable display/sm501: make range overlap check more readable aspeed_smc: make range overlap check more readable qtest/fuzz: make range overlap check more readable sparc/ldst_helper: make range overlap check more readable system/memory_mapping: make range overlap check more readable block/vhdx: make range overlap check more readable crypto/block-luks: make range overlap check more readable dump: make range overlap check more readable block/qcow2-cluster: make range overlap check more readable
Re: [PULL 00/15] aspeed queue
On 22/7/24 07:21, Richard Henderson wrote: On 7/21/24 18:13, Cédric Le Goater wrote: The following changes since commit a87a7c449e532130d4fa8faa391ff7e1f04ed660: Merge tag 'pull-loongarch-20240719' ofhttps://gitlab.com/gaosong/qemu into staging (2024-07-19 16:28:28 +1000) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20240721 for you to fetch changes up to 4db1c16441923fc152142ae4bcc1cba23064cb8b: aspeed: fix coding style (2024-07-21 07:46:38 +0200) aspeed queue: * SMC model fix (Coverity) * AST2600 boot for eMMC support and test 拾 拾 * AST2700 ADC model * I2C model changes preparing AST2700 I2C support Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
[PATCH v5 06/16] hw/char/pl011: Extract pl011_write_txdata() from pl011_write()
When implementing FIFO, this code will become more complex.
Start by factoring it out to a new pl011_write_txdata() function.
No functional change intended.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
hw/char/pl011.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 3d294c3b52..c2ee9b0321 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -221,6 +221,18 @@ static void pl011_loopback_tx(PL011State *s, uint32_t
value)
pl011_put_fifo(s, value);
}
+static void pl011_write_txdata(PL011State *s, uint8_t data)
+{
+/* ??? Check if transmitter is enabled. */
+
+/* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+qemu_chr_fe_write_all(>chr, , 1);
+pl011_loopback_tx(s, data);
+s->int_level |= INT_TX;
+pl011_update(s);
+}
+
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -388,14 +400,8 @@ static void pl011_write(void *opaque, hwaddr offset,
switch (offset >> 2) {
case 0: /* UARTDR */
-/* ??? Check if transmitter is enabled. */
ch = value;
-/* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
-qemu_chr_fe_write_all(>chr, , 1);
-pl011_loopback_tx(s, ch);
-s->int_level |= INT_TX;
-pl011_update(s);
+pl011_write_txdata(s, ch);
break;
case 1: /* UARTRSR/UARTECR */
s->rsr = 0;
--
2.41.0
[PATCH v5 07/16] hw/char/pl011: Extract pl011_read_rxdata() from pl011_read()
To keep MemoryRegionOps read/write handlers with similar logic,
factor pl011_read_txdata() out of pl011_read(), similar to what
the previous commit did to pl011_write().
No functional change intended.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 41 -
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c2ee9b0321..5e44837206 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -233,31 +233,38 @@ static void pl011_write_txdata(PL011State *s, uint8_t
data)
pl011_update(s);
}
+static uint32_t pl011_read_rxdata(PL011State *s)
+{
+uint32_t c;
+
+s->flags &= ~PL011_FLAG_RXFF;
+c = s->read_fifo[s->read_pos];
+if (s->read_count > 0) {
+s->read_count--;
+s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
+}
+if (s->read_count == 0) {
+s->flags |= PL011_FLAG_RXFE;
+}
+if (s->read_count == s->read_trigger - 1) {
+s->int_level &= ~ INT_RX;
+}
+trace_pl011_read_fifo(s->read_count);
+s->rsr = c >> 8;
+pl011_update(s);
+qemu_chr_fe_accept_input(>chr);
+return c;
+}
+
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
PL011State *s = (PL011State *)opaque;
-uint32_t c;
uint64_t r;
switch (offset >> 2) {
case 0: /* UARTDR */
-s->flags &= ~PL011_FLAG_RXFF;
-c = s->read_fifo[s->read_pos];
-if (s->read_count > 0) {
-s->read_count--;
-s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
-}
-if (s->read_count == 0) {
-s->flags |= PL011_FLAG_RXFE;
-}
-if (s->read_count == s->read_trigger - 1)
-s->int_level &= ~ INT_RX;
-trace_pl011_read_fifo(s->read_count);
-s->rsr = c >> 8;
-pl011_update(s);
-qemu_chr_fe_accept_input(>chr);
-r = c;
+r = pl011_read_rxdata(s);
break;
case 1: /* UARTRSR */
r = s->rsr;
--
2.41.0
[PATCH v5 01/16] tests/avocado: Add 'device:pl011' tag to tests exercising PL011 UART
Add the 'device:pl011' tag to various tests using the
PL011 UART, so we can run them all at once using:
$ make check-avocado AVOCADO_TAGS='device:pl011'
Signed-off-by: Philippe Mathieu-Daudé
---
tests/avocado/boot_linux.py | 1 +
tests/avocado/boot_linux_console.py | 2 ++
tests/avocado/boot_xen.py| 1 +
tests/avocado/machine_aarch64_sbsaref.py | 1 +
tests/avocado/machine_aarch64_virt.py| 1 +
tests/avocado/smmu.py| 1 +
tests/avocado/tuxrun_baselines.py| 5 +
7 files changed, 12 insertions(+)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index df6cf209ef..6717f452eb 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -70,6 +70,7 @@ class BootLinuxAarch64(LinuxTest):
def test_virt_kvm(self):
"""
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
:avocado: tags=accel:kvm
:avocado: tags=cpu:host
"""
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index c35fc5e9ba..f595324979 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -362,6 +362,7 @@ def test_arm_virt(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
:avocado: tags=accel:tcg
"""
kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora'
@@ -1380,6 +1381,7 @@ def test_arm_vexpressa9(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:vexpress-a9
+:avocado: tags=device:pl011
"""
tar_hash = '32b7677ce8b6f1471fb0059865f451169934245b'
self.vm.add_args('-dtb', self.workdir + '/day16/vexpress-v2p-ca9.dtb')
diff --git a/tests/avocado/boot_xen.py b/tests/avocado/boot_xen.py
index 93bfb0c161..c4c01afa76 100644
--- a/tests/avocado/boot_xen.py
+++ b/tests/avocado/boot_xen.py
@@ -66,6 +66,7 @@ class BootXen(BootXenBase):
:avocado: tags=accel:tcg
:avocado: tags=cpu:cortex-a57
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
"""
def test_arm64_xen_411_and_dom0(self):
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado/machine_aarch64_sbsaref.py
index e920bbf08c..f04ac2b11c 100644
--- a/tests/avocado/machine_aarch64_sbsaref.py
+++ b/tests/avocado/machine_aarch64_sbsaref.py
@@ -20,6 +20,7 @@ class Aarch64SbsarefMachine(QemuSystemTest):
"""
:avocado: tags=arch:aarch64
:avocado: tags=machine:sbsa-ref
+:avocado: tags=device:pl011
:avocado: tags=accel:tcg
As firmware runs at a higher privilege level than the hypervisor we
diff --git a/tests/avocado/machine_aarch64_virt.py
b/tests/avocado/machine_aarch64_virt.py
index 0ef6df4b0d..2d586c8459 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -23,6 +23,7 @@ class Aarch64VirtMachine(QemuSystemTest):
"""
:avocado: tags=arch:aarch64
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
"""
KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
timeout = 360
diff --git a/tests/avocado/smmu.py b/tests/avocado/smmu.py
index 4ebfa7128c..4b265e2435 100644
--- a/tests/avocado/smmu.py
+++ b/tests/avocado/smmu.py
@@ -21,6 +21,7 @@ class SMMU(LinuxTest):
:avocado: tags=arch:aarch64
:avocado: tags=machine:virt
:avocado: tags=distro:fedora
+:avocado: tags=device:pl011
:avocado: tags=smmu
:avocado: tags=flaky
"""
diff --git a/tests/avocado/tuxrun_baselines.py
b/tests/avocado/tuxrun_baselines.py
index 736e4aa289..98ab40bbb5 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -254,6 +254,7 @@ def test_arm64(self):
:avocado: tags=arch:aarch64
:avocado: tags=cpu:cortex-a57
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
:avocado: tags=tuxboot:arm64
:avocado: tags=console:ttyAMA0
:avocado: tags=shutdown:nowait
@@ -270,6 +271,7 @@ def test_arm64be(self):
:avocado: tags=cpu:cortex-a57
:avocado: tags=endian:big
:avocado: tags=machine:virt
+:avocado: tags=device:pl011
:avocado: tags=tuxboot:arm64be
:avocado: tags=console:ttyAMA0
:avocado: tags=shutdown:nowait
@@ -285,6 +287,7 @@ def test_armv5(self):
:avocado: tags=arch:arm
:avocado: tags=cpu:arm926
:avocado: tags=machine:versatilepb
+:avocado: tags=device:pl011
:avocado: tags=tuxboot:armv5
:avocado: tags=image:zImage
:avocado: tags=console:ttyAMA0
@@ -306,6 +309,7 @@ def test_armv7(self):
:avocado: tags=arch:arm
[RFC PATCH v5 16/16] hw/char/pl011: Implement TX FIFO
If the UART back-end chardev doesn't drain data as fast as stdout
does or blocks, buffer in the TX FIFO to try again later.
This avoids having the IO-thread busy waiting on chardev back-ends,
reported recently when testing the Trusted Reference Stack and
using the socket backend.
Implement registering a front-end 'watch' callback on back-end
events, so we can resume transmitting when the back-end is writable
again, not blocking the main loop.
Similarly to the RX FIFO path, FIFO level selection is not
implemented (interrupt is triggered when a single byte is available
in the FIFO).
Reported-by: Mikko Rapeli
Suggested-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: Something is still broken, some characters are emitted async...
---
hw/char/pl011.c | 60
hw/char/trace-events | 1 +
2 files changed, 51 insertions(+), 10 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index cfa3fd3da4..9f72b6a765 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -240,7 +240,9 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition
cond, void *opaque)
{
PL011State *s = opaque;
int bytes_consumed;
-uint8_t data;
+const uint8_t *buf;
+uint32_t buflen;
+uint32_t count;
if (!(s->cr & CR_UARTEN)) {
qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled
UART\n");
@@ -249,25 +251,40 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition
cond, void *opaque)
qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
}
+count = fifo8_num_used(>xmit_fifo);
+if (count < 1) {
+/* FIFO empty */
+return G_SOURCE_REMOVE;
+}
+
if (!qemu_chr_fe_backend_connected(>chr)) {
/* Instant drain the fifo when there's no back-end. */
pl011_drain_tx(s);
return G_SOURCE_REMOVE;
}
-data = fifo8_pop(>xmit_fifo);
-bytes_consumed = 1;
+buf = fifo8_peek_buf(>xmit_fifo, count, );
-/*
- * XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks
- */
-qemu_chr_fe_write_all(>chr, , bytes_consumed);
+/* Transmit as much data as we can. */
+bytes_consumed = qemu_chr_fe_write(>chr, buf, buflen);
trace_pl011_fifo_tx_xmit(bytes_consumed);
+if (bytes_consumed < 0) {
+/* Error in back-end: drain the fifo. */
+pl011_drain_tx(s);
+return G_SOURCE_REMOVE;
+}
+
+/* Pop the data we could transmit. */
+fifo8_pop_buf(>xmit_fifo, bytes_consumed, NULL);
s->int_level |= INT_TX;
pl011_update(s);
+if (!fifo8_is_empty(>xmit_fifo)) {
+/* Reschedule another transmission if we couldn't transmit all. */
+return G_SOURCE_CONTINUE;
+}
+
return G_SOURCE_REMOVE;
}
@@ -290,6 +307,10 @@ static void pl011_write_txdata(PL011State *s, uint8_t data)
trace_pl011_fifo_tx_put(data);
pl011_loopback_tx(s, data);
fifo8_push(>xmit_fifo, data);
+if (fifo8_is_full(>xmit_fifo)) {
+s->flags |= PL011_FLAG_TXFF;
+}
+
pl011_xmit(NULL, G_IO_OUT, s);
}
@@ -488,10 +509,24 @@ static void pl011_write(void *opaque, hwaddr offset,
pl011_trace_baudrate_change(s);
break;
case 11: /* UARTLCR_H */
-/* Reset the FIFO state on FIFO enable or disable */
if ((s->lcr ^ value) & LCR_FEN) {
-pl011_reset_rx_fifo(s);
+bool fifo_enabled = value & LCR_FEN;
+
+trace_pl011_fifo_enable(fifo_enabled);
+if (fifo_enabled) {
+/* Transmit and receive FIFO buffers are enabled (FIFO mode).
*/
+fifo8_change_capacity(>xmit_fifo, PL011_FIFO_DEPTH);
+} else {
+/*
+ * FIFOs are disabled (character mode) that is, the FIFOs
+ * become 1-byte-deep holding registers.
+ */
+pl011_drain_tx(s);
+fifo8_change_capacity(>xmit_fifo, 1);
+}
+/* Reset the FIFO state on FIFO enable or disable */
pl011_reset_tx_fifo(s);
+pl011_reset_rx_fifo(s);
}
if ((s->lcr ^ value) & LCR_BRK) {
int break_enable = value & LCR_BRK;
@@ -636,6 +671,11 @@ static int pl011_post_load(void *opaque, int version_id)
s->read_pos = 0;
}
+if (!fifo8_is_empty(>xmit_fifo)) {
+/* Reschedule another transmission */
+qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, pl011_xmit, s);
+}
+
s->ibrd &= IBRD_MASK;
s->fbrd &= FBRD_MASK;
diff --git a/hw/char/trace-events b/hw/char/trace-events
index bf586ba664..2405819812 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -58,6 +58,7 @@ pl011_read(uint32_t addr, uint32_t value, const char
*regname) &quo
[PATCH v5 11/16] hw/char/pl011: Rename RX FIFO methods
In preparation of having a TX FIFO, rename the RX FIFO methods.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
hw/char/pl011.c | 12 ++--
hw/char/trace-events | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 0ce91c13d3..c42c6d1ac2 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -174,7 +174,7 @@ static inline void pl011_reset_tx_fifo(PL011State *s)
s->flags |= PL011_FLAG_TXFE;
}
-static void pl011_put_fifo(void *opaque, uint32_t value)
+static void pl011_fifo_rx_put(void *opaque, uint32_t value)
{
PL011State *s = (PL011State *)opaque;
int slot;
@@ -185,9 +185,9 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
-trace_pl011_put_fifo(value, s->read_count);
+trace_pl011_fifo_rx_put(value, s->read_count);
if (s->read_count == pipe_depth) {
-trace_pl011_put_fifo_full();
+trace_pl011_fifo_rx_full();
s->flags |= PL011_FLAG_RXFF;
}
if (s->read_count == s->read_trigger) {
@@ -221,7 +221,7 @@ static void pl011_loopback_tx(PL011State *s, uint32_t value)
*
* For simplicity, the above described is not emulated.
*/
-pl011_put_fifo(s, value);
+pl011_fifo_rx_put(s, value);
}
static void pl011_write_txdata(PL011State *s, uint8_t data)
@@ -502,13 +502,13 @@ static void pl011_receive(void *opaque, const uint8_t
*buf, int size)
return;
}
-pl011_put_fifo(opaque, *buf);
+pl011_fifo_rx_put(opaque, *buf);
}
static void pl011_event(void *opaque, QEMUChrEvent event)
{
if (event == CHR_EVENT_BREAK && !pl011_loopback_enabled(opaque)) {
-pl011_put_fifo(opaque, DR_BE);
+pl011_fifo_rx_put(opaque, DR_BE);
}
}
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 8875758076..59e1f734a7 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -58,8 +58,8 @@ pl011_read(uint32_t addr, uint32_t value, const char
*regname) "addr 0x%03x valu
pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x
value 0x%08x reg %s"
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count
%d returning %d"
-pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
-pl011_put_fifo_full(void) "FIFO now full, RXFF set"
+pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now
%d"
+pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd,
uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd:
%" PRIu32 ")"
# cmsdk-apb-uart.c
--
2.41.0
[PATCH v5 09/16] tests/qtest: Update tests using PL011 UART
We weren't enabling the PL011 TX UART before using it
on the raspi and virt machines. Update the ASM code
prefixing:
*UART_CTRL = UART_ENABLE | TX_ENABLE;
to:
while (true) {
*UART_DATA = 'T';
}
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/boot-serial-test.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index 3b92fa5d50..5cb309ccf0 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -70,18 +70,23 @@ static const uint8_t kernel_plml605[] = {
};
static const uint8_t bios_raspi2[] = {
-0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8]Get base */
+0x10, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8]Get base
*/
+0x10, 0x20, 0x9f, 0xe5, /* ldr r2,[pc,#8]Get CR */
+0xb0, 0x23, 0xc3, 0xe1, /* strhr2,[r3, #48] Set CR */
0x54, 0x20, 0xa0, 0xe3, /* mov r2,#'T' */
-0x00, 0x20, 0xc3, 0xe5, /* strbr2,[r3] */
-0xfb, 0xff, 0xff, 0xea, /* b loop */
+0x00, 0x20, 0xc3, 0xe5, /* strbr2,[r3] loop: */
+0xfd, 0xff, 0xff, 0xea, /* b loop */
0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */
+0x01, 0x01, 0x00, 0x00, /* 0x101 = CR UARTEN|TXE */
};
static const uint8_t kernel_aarch64[] = {
-0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x900 */
+0x21, 0x20, 0x80, 0x52, /* mov w1, #0x101 */
+0x41, 0x60, 0x00, 0x79, /* strhw1, [x2, #48] */
+0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */
0x41, 0x00, 0x00, 0x39, /* strbw1, [x2] */
-0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
+0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */
};
static const uint8_t kernel_nrf51[] = {
--
2.41.0
[PATCH v5 15/16] hw/char/pl011: Drain TX FIFO when no backend connected
When no character backend is connected, the PL011 frontend
just drains the FIFO.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 13 +
hw/char/trace-events | 1 +
2 files changed, 14 insertions(+)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index b8cde03f98..cfa3fd3da4 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -229,6 +229,13 @@ static void pl011_loopback_tx(PL011State *s, uint32_t
value)
pl011_fifo_rx_put(s, value);
}
+static void pl011_drain_tx(PL011State *s)
+{
+trace_pl011_fifo_tx_drain(fifo8_num_used(>xmit_fifo));
+pl011_reset_tx_fifo(s);
+s->rsr &= ~RSR_OE;
+}
+
static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque)
{
PL011State *s = opaque;
@@ -242,6 +249,12 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition
cond, void *opaque)
qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
}
+if (!qemu_chr_fe_backend_connected(>chr)) {
+/* Instant drain the fifo when there's no back-end. */
+pl011_drain_tx(s);
+return G_SOURCE_REMOVE;
+}
+
data = fifo8_pop(>xmit_fifo);
bytes_consumed = 1;
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 4a9c0bd271..bf586ba664 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -63,6 +63,7 @@ pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"
pl011_fifo_tx_xmit(int count) "TX FIFO pop %d chars"
pl011_fifo_tx_overrun(void) "TX FIFO overrun"
+pl011_fifo_tx_drain(unsigned drained) "TX FIFO draining %u chars"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd,
uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd:
%" PRIu32 ")"
# cmsdk-apb-uart.c
--
2.41.0
[PATCH v5 13/16] hw/char/pl011: Introduce pl011_xmit() as GSource
Extract pl011_xmit() from pl011_write_txdata(). Use the
FIFO to pass the character to be transmitted.
Implement it using the FEWatchFunc prototype, since we want
to register it as GSource later. While the return value is
not yet used, we return G_SOURCE_REMOVE meaning the GSource
is removed from the main loop (because we only send one char).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 30 +-
hw/char/trace-events | 2 ++
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 6519340b50..6394d6eb36 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -226,6 +226,28 @@ static void pl011_loopback_tx(PL011State *s, uint32_t
value)
pl011_fifo_rx_put(s, value);
}
+static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque)
+{
+PL011State *s = opaque;
+int bytes_consumed;
+uint8_t data;
+
+data = fifo8_pop(>xmit_fifo);
+bytes_consumed = 1;
+
+/*
+ * XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks
+ */
+qemu_chr_fe_write_all(>chr, , bytes_consumed);
+trace_pl011_fifo_tx_xmit(bytes_consumed);
+s->int_level |= INT_TX;
+
+pl011_update(s);
+
+return G_SOURCE_REMOVE;
+}
+
static void pl011_write_txdata(PL011State *s, uint8_t data)
{
if (!(s->cr & CR_UARTEN)) {
@@ -235,12 +257,10 @@ static void pl011_write_txdata(PL011State *s, uint8_t
data)
qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
}
-/* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
-qemu_chr_fe_write_all(>chr, , 1);
+trace_pl011_fifo_tx_put(data);
pl011_loopback_tx(s, data);
-s->int_level |= INT_TX;
-pl011_update(s);
+fifo8_push(>xmit_fifo, data);
+pl011_xmit(NULL, G_IO_OUT, s);
}
static uint32_t pl011_read_rxdata(PL011State *s)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 59e1f734a7..30d06a2383 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -60,6 +60,8 @@ pl011_write(uint32_t addr, uint32_t value, const char
*regname) "addr 0x%03x val
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count
%d returning %d"
pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now
%d"
pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
+pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"
+pl011_fifo_tx_xmit(int count) "TX FIFO pop %d chars"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd,
uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd:
%" PRIu32 ")"
# cmsdk-apb-uart.c
--
2.41.0
[PATCH v5 12/16] hw/char/pl011: Add transmit FIFO to PL011State
In order to make the next commit easier to review,
introduce the transmit FIFO, but do not yet use it.
We only migrate the TX FIFO if it is in use.
When migrating from new to old VM:
- if the fifo is empty, migration will still work because
of the subsection.
- if the fifo is not empty, the subsection will be ignored,
with the only consequence being that some characters will
be dropped.
Since the FIFO is created empty, we don't need a migration
pre_load() handler.
Uninline pl011_reset_tx_fifo().
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/char/pl011.h | 2 ++
hw/char/pl011.c | 37 +++--
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index 4fcaf3d7d3..e8d95961f6 100644
--- a/include/hw/char/pl011.h
+++ b/include/hw/char/pl011.h
@@ -18,6 +18,7 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
+#include "qemu/fifo8.h"
#define TYPE_PL011 "pl011"
OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
@@ -52,6 +53,7 @@ struct PL011State {
Clock *clk;
bool migrate_clk;
const unsigned char *id;
+Fifo8 xmit_fifo;
};
DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c42c6d1ac2..6519340b50 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -167,11 +167,13 @@ static inline void pl011_reset_rx_fifo(PL011State *s)
s->flags |= PL011_FLAG_RXFE;
}
-static inline void pl011_reset_tx_fifo(PL011State *s)
+static void pl011_reset_tx_fifo(PL011State *s)
{
/* Reset FIFO flags */
s->flags &= ~PL011_FLAG_TXFF;
s->flags |= PL011_FLAG_TXFE;
+
+fifo8_reset(>xmit_fifo);
}
static void pl011_fifo_rx_put(void *opaque, uint32_t value)
@@ -545,6 +547,24 @@ static const VMStateDescription vmstate_pl011_clock = {
}
};
+static bool pl011_xmit_fifo_state_needed(void *opaque)
+{
+PL011State* s = opaque;
+
+return (s->lcr & LCR_FEN) && !fifo8_is_empty(>xmit_fifo);
+}
+
+static const VMStateDescription vmstate_pl011_xmit_fifo = {
+.name = "pl011/xmit_fifo",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = pl011_xmit_fifo_state_needed,
+.fields = (VMStateField[]) {
+VMSTATE_FIFO8(xmit_fifo, PL011State),
+VMSTATE_END_OF_LIST()
+}
+};
+
static int pl011_post_load(void *opaque, int version_id)
{
PL011State* s = opaque;
@@ -599,7 +619,11 @@ static const VMStateDescription vmstate_pl011 = {
.subsections = (const VMStateDescription * const []) {
_pl011_clock,
NULL
-}
+},
+.subsections = (const VMStateDescription * []) {
+_pl011_xmit_fifo,
+NULL
+},
};
static Property pl011_properties[] = {
@@ -614,6 +638,7 @@ static void pl011_init(Object *obj)
PL011State *s = PL011(obj);
int i;
+fifo8_create(>xmit_fifo, PL011_FIFO_DEPTH);
memory_region_init_io(>iomem, OBJECT(s), _ops, s, "pl011",
0x1000);
sysbus_init_mmio(sbd, >iomem);
for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
@@ -626,6 +651,13 @@ static void pl011_init(Object *obj)
s->id = pl011_id_arm;
}
+static void pl011_finalize(Object *obj)
+{
+PL011State *s = PL011(obj);
+
+fifo8_destroy(>xmit_fifo);
+}
+
static void pl011_realize(DeviceState *dev, Error **errp)
{
PL011State *s = PL011(dev);
@@ -669,6 +701,7 @@ static const TypeInfo pl011_arm_info = {
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PL011State),
.instance_init = pl011_init,
+.instance_finalize = pl011_finalize,
.class_init= pl011_class_init,
};
--
2.41.0
[PATCH v5 14/16] hw/char/pl011: Consider TX FIFO overrun error
When transmission is disabled, characters are still queued
to the FIFO which eventually overruns. Report that error
condition in the status register.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 17 +
hw/char/trace-events | 1 +
2 files changed, 18 insertions(+)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 6394d6eb36..b8cde03f98 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -61,6 +61,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev
*chr)
/* Data Register, UARTDR */
#define DR_BE (1 << 10)
+/* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */
+#define RSR_OE (1 << 3)
+
/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
#define INT_OE (1 << 10)
#define INT_BE (1 << 9)
@@ -232,6 +235,13 @@ static gboolean pl011_xmit(void *do_not_use, GIOCondition
cond, void *opaque)
int bytes_consumed;
uint8_t data;
+if (!(s->cr & CR_UARTEN)) {
+qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled
UART\n");
+}
+if (!(s->cr & CR_TXE)) {
+qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
+}
+
data = fifo8_pop(>xmit_fifo);
bytes_consumed = 1;
@@ -257,6 +267,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data)
qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
}
+if (fifo8_is_full(>xmit_fifo)) {
+/* The FIFO is already full. Content remains valid. */
+trace_pl011_fifo_tx_overrun();
+s->rsr |= RSR_OE;
+return;
+}
+
trace_pl011_fifo_tx_put(data);
pl011_loopback_tx(s, data);
fifo8_push(>xmit_fifo, data);
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 30d06a2383..4a9c0bd271 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -62,6 +62,7 @@ pl011_fifo_rx_put(uint32_t c, int read_count) "new char
0x%02x read_count now %d
pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"
pl011_fifo_tx_xmit(int count) "TX FIFO pop %d chars"
+pl011_fifo_tx_overrun(void) "TX FIFO overrun"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd,
uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd:
%" PRIu32 ")"
# cmsdk-apb-uart.c
--
2.41.0
[PATCH v5 10/16] hw/char/pl011: Check if receiver is enabled
Do not receive characters when UART or receiver are disabled.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/char/pl011.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c76283dccf..0ce91c13d3 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -85,6 +85,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev
*chr)
#define CR_OUT1 (1 << 12)
#define CR_RTS (1 << 11)
#define CR_DTR (1 << 10)
+#define CR_RXE (1 << 9)
#define CR_TXE (1 << 8)
#define CR_LBE (1 << 7)
#define CR_UARTEN (1 << 0)
@@ -481,9 +482,11 @@ static void pl011_write(void *opaque, hwaddr offset,
static int pl011_can_receive(void *opaque)
{
PL011State *s = (PL011State *)opaque;
-int r;
+int r = 0;
-r = s->read_count < pl011_get_fifo_depth(s);
+if ((s->cr & CR_UARTEN) && (s->cr & CR_RXE)) {
+r = s->read_count < pl011_get_fifo_depth(s);
+}
trace_pl011_can_receive(s->lcr, s->read_count, r);
return r;
}
--
2.41.0
[PATCH v5 02/16] hw/char/pl011: Remove unused 'readbuff' field
Since its introduction in commit cdbdb648b7 ("ARM Versatile
Platform Baseboard emulation.") PL011State::readbuff as never
been used. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/char/pl011.h | 1 -
hw/char/pl011.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index d853802132..4fcaf3d7d3 100644
--- a/include/hw/char/pl011.h
+++ b/include/hw/char/pl011.h
@@ -32,7 +32,6 @@ struct PL011State {
SysBusDevice parent_obj;
MemoryRegion iomem;
-uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
uint32_t rsr;
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index f8078aa216..260f5fc0bc 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -549,7 +549,7 @@ static const VMStateDescription vmstate_pl011 = {
.minimum_version_id = 2,
.post_load = pl011_post_load,
.fields = (const VMStateField[]) {
-VMSTATE_UINT32(readbuff, PL011State),
+VMSTATE_UNUSED(sizeof(uint32_t)),
VMSTATE_UINT32(flags, PL011State),
VMSTATE_UINT32(lcr, PL011State),
VMSTATE_UINT32(rsr, PL011State),
--
2.41.0
[PATCH v5 05/16] hw/char/pl011: Split RX/TX path of pl011_reset_fifo()
To be able to reset the RX or TX FIFO separately,
split pl011_reset_fifo() in two.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
hw/char/pl011.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 22195ead7b..3d294c3b52 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -154,14 +154,21 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
}
-static inline void pl011_reset_fifo(PL011State *s)
+static inline void pl011_reset_rx_fifo(PL011State *s)
{
s->read_count = 0;
s->read_pos = 0;
/* Reset FIFO flags */
-s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
-s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+s->flags &= ~PL011_FLAG_RXFF;
+s->flags |= PL011_FLAG_RXFE;
+}
+
+static inline void pl011_reset_tx_fifo(PL011State *s)
+{
+/* Reset FIFO flags */
+s->flags &= ~PL011_FLAG_TXFF;
+s->flags |= PL011_FLAG_TXFE;
}
static void pl011_put_fifo(void *opaque, uint32_t value)
@@ -410,7 +417,8 @@ static void pl011_write(void *opaque, hwaddr offset,
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
if ((s->lcr ^ value) & LCR_FEN) {
-pl011_reset_fifo(s);
+pl011_reset_rx_fifo(s);
+pl011_reset_tx_fifo(s);
}
if ((s->lcr ^ value) & LCR_BRK) {
int break_enable = value & LCR_BRK;
@@ -619,7 +627,8 @@ static void pl011_reset(DeviceState *dev)
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0;
-pl011_reset_fifo(s);
+pl011_reset_rx_fifo(s);
+pl011_reset_tx_fifo(s);
}
static void pl011_class_init(ObjectClass *oc, void *data)
--
2.41.0
[PATCH v5 04/16] hw/char/pl011: Move pl011_loopback_enabled|tx() around
We'll soon use pl011_loopback_enabled() and pl011_loopback_tx()
from functions defined before their declarations. In order to
avoid forward-declaring them, move them around.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 66 -
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index edb5395fb8..22195ead7b 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -138,6 +138,11 @@ static void pl011_update(PL011State *s)
}
}
+static bool pl011_loopback_enabled(PL011State *s)
+{
+return !!(s->cr & CR_LBE);
+}
+
static bool pl011_is_fifo_enabled(PL011State *s)
{
return (s->lcr & LCR_FEN) != 0;
@@ -181,6 +186,34 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
}
}
+static void pl011_loopback_tx(PL011State *s, uint32_t value)
+{
+if (!pl011_loopback_enabled(s)) {
+return;
+}
+
+/*
+ * Caveat:
+ *
+ * In real hardware, TX loopback happens at the serial-bit level
+ * and then reassembled by the RX logics back into bytes and placed
+ * into the RX fifo. That is, loopback happens after TX fifo.
+ *
+ * Because the real hardware TX fifo is time-drained at the frame
+ * rate governed by the configured serial format, some loopback
+ * bytes in TX fifo may still be able to get into the RX fifo
+ * that could be full at times while being drained at software
+ * pace.
+ *
+ * In such scenario, the RX draining pace is the major factor
+ * deciding which loopback bytes get into the RX fifo, unless
+ * hardware flow-control is enabled.
+ *
+ * For simplicity, the above described is not emulated.
+ */
+pl011_put_fifo(s, value);
+}
+
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -290,11 +323,6 @@ static void pl011_trace_baudrate_change(const PL011State
*s)
s->ibrd, s->fbrd);
}
-static bool pl011_loopback_enabled(PL011State *s)
-{
-return !!(s->cr & CR_LBE);
-}
-
static void pl011_loopback_mdmctrl(PL011State *s)
{
uint32_t cr, fr, il;
@@ -336,34 +364,6 @@ static void pl011_loopback_mdmctrl(PL011State *s)
pl011_update(s);
}
-static void pl011_loopback_tx(PL011State *s, uint32_t value)
-{
-if (!pl011_loopback_enabled(s)) {
-return;
-}
-
-/*
- * Caveat:
- *
- * In real hardware, TX loopback happens at the serial-bit level
- * and then reassembled by the RX logics back into bytes and placed
- * into the RX fifo. That is, loopback happens after TX fifo.
- *
- * Because the real hardware TX fifo is time-drained at the frame
- * rate governed by the configured serial format, some loopback
- * bytes in TX fifo may still be able to get into the RX fifo
- * that could be full at times while being drained at software
- * pace.
- *
- * In such scenario, the RX draining pace is the major factor
- * deciding which loopback bytes get into the RX fifo, unless
- * hardware flow-control is enabled.
- *
- * For simplicity, the above described is not emulated.
- */
-pl011_put_fifo(s, value);
-}
-
static void pl011_loopback_break(PL011State *s, int brk_enable)
{
if (brk_enable) {
--
2.41.0
[PATCH v5 08/16] hw/char/pl011: Warn when using disabled transmitter
We shouldn't transmit characters when the full UART or its
transmitter is disabled. However we don't want to break the
possibly incomplete "my first bare metal assembly program"s,
so we choose to simply display a warning when this occurs.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
hw/char/pl011.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 5e44837206..c76283dccf 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -85,7 +85,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev
*chr)
#define CR_OUT1 (1 << 12)
#define CR_RTS (1 << 11)
#define CR_DTR (1 << 10)
+#define CR_TXE (1 << 8)
#define CR_LBE (1 << 7)
+#define CR_UARTEN (1 << 0)
/* Integer Baud Rate Divider, UARTIBRD */
#define IBRD_MASK 0x3f
@@ -223,7 +225,12 @@ static void pl011_loopback_tx(PL011State *s, uint32_t
value)
static void pl011_write_txdata(PL011State *s, uint8_t data)
{
-/* ??? Check if transmitter is enabled. */
+if (!(s->cr & CR_UARTEN)) {
+qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled
UART\n");
+}
+if (!(s->cr & CR_TXE)) {
+qemu_log_mask(LOG_GUEST_ERROR, "PL011 data written to disabled TX
UART\n");
+}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
--
2.41.0
[PATCH v5 03/16] hw/char/pl011: Move pl011_put_fifo() earlier
Avoid forward-declaring pl011_put_fifo() by moving it earlier.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 46 ++
1 file changed, 22 insertions(+), 24 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 260f5fc0bc..edb5395fb8 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -159,6 +159,28 @@ static inline void pl011_reset_fifo(PL011State *s)
s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
}
+static void pl011_put_fifo(void *opaque, uint32_t value)
+{
+PL011State *s = (PL011State *)opaque;
+int slot;
+unsigned pipe_depth;
+
+pipe_depth = pl011_get_fifo_depth(s);
+slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
+s->read_fifo[slot] = value;
+s->read_count++;
+s->flags &= ~PL011_FLAG_RXFE;
+trace_pl011_put_fifo(value, s->read_count);
+if (s->read_count == pipe_depth) {
+trace_pl011_put_fifo_full();
+s->flags |= PL011_FLAG_RXFF;
+}
+if (s->read_count == s->read_trigger) {
+s->int_level |= INT_RX;
+pl011_update(s);
+}
+}
+
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -314,8 +336,6 @@ static void pl011_loopback_mdmctrl(PL011State *s)
pl011_update(s);
}
-static void pl011_put_fifo(void *opaque, uint32_t value);
-
static void pl011_loopback_tx(PL011State *s, uint32_t value)
{
if (!pl011_loopback_enabled(s)) {
@@ -440,28 +460,6 @@ static int pl011_can_receive(void *opaque)
return r;
}
-static void pl011_put_fifo(void *opaque, uint32_t value)
-{
-PL011State *s = (PL011State *)opaque;
-int slot;
-unsigned pipe_depth;
-
-pipe_depth = pl011_get_fifo_depth(s);
-slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
-s->read_fifo[slot] = value;
-s->read_count++;
-s->flags &= ~PL011_FLAG_RXFE;
-trace_pl011_put_fifo(value, s->read_count);
-if (s->read_count == pipe_depth) {
-trace_pl011_put_fifo_full();
-s->flags |= PL011_FLAG_RXFF;
-}
-if (s->read_count == s->read_trigger) {
-s->int_level |= INT_RX;
-pl011_update(s);
-}
-}
-
static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
/*
--
2.41.0
[PATCH v5 00/16] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop
Hi, This series add support for (async) FIFO on the transmit path of the PL011 UART. Last patch still broken (chars are emitted async), still patches 1-11 could be merged for this release... Since v4: - Rebased (loopback) - Addressed Richard & Juan migration comments - Split in smaller patches Since v3: - Document migration bits (Alex, Richard) - Just check FIFO is not empty in pl011_xmit_fifo_state_needed (rth) - In pl011_xmit check TX enabled first, and ignore < 8-bit TX (rth) Since v2: - Added R-b tags - Addressed Richard comments on migration Since v1: - Restrict pl011_ops[] impl access_size, - Do not check transmitter is enabled (Peter), - Addressed Alex's review comments, - Simplified migration trying to care about backward compat, but still unsure... Philippe Mathieu-Daudé (16): tests/avocado: Add 'device:pl011' tag to tests exercising PL011 UART hw/char/pl011: Remove unused 'readbuff' field hw/char/pl011: Move pl011_put_fifo() earlier hw/char/pl011: Move pl011_loopback_enabled|tx() around hw/char/pl011: Split RX/TX path of pl011_reset_fifo() hw/char/pl011: Extract pl011_write_txdata() from pl011_write() hw/char/pl011: Extract pl011_read_rxdata() from pl011_read() hw/char/pl011: Warn when using disabled transmitter tests/qtest: Update tests using PL011 UART hw/char/pl011: Check if receiver is enabled hw/char/pl011: Rename RX FIFO methods hw/char/pl011: Add transmit FIFO to PL011State hw/char/pl011: Introduce pl011_xmit() as GSource hw/char/pl011: Consider TX FIFO overrun error hw/char/pl011: Drain TX FIFO when no backend connected hw/char/pl011: Implement TX FIFO include/hw/char/pl011.h | 3 +- hw/char/pl011.c | 339 --- tests/qtest/boot-serial-test.c | 15 +- hw/char/trace-events | 9 +- tests/avocado/boot_linux.py | 1 + tests/avocado/boot_linux_console.py | 2 + tests/avocado/boot_xen.py| 1 + tests/avocado/machine_aarch64_sbsaref.py | 1 + tests/avocado/machine_aarch64_virt.py| 1 + tests/avocado/smmu.py| 1 + tests/avocado/tuxrun_baselines.py| 5 + 11 files changed, 277 insertions(+), 101 deletions(-) -- 2.41.0
[PATCH] tests/avocado: Allow overwritting AVOCADO_SHOW env variable
The 'app' level logging is useful, but sometimes we want more, for example QEMU leverages the 'console' logging. Allow overwritting AVOCADO_SHOW from environment, i.e.: $ make check-avocado AVOCADO_SHOW='app,console' Signed-off-by: Philippe Mathieu-Daudé --- tests/Makefile.include | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/Makefile.include b/tests/Makefile.include index d39d5dd6a4..6618bfed70 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -97,7 +97,7 @@ endif # Controls the output generated by Avocado when running tests. # Any number of command separated loggers are accepted. For more # information please refer to "avocado --help". -AVOCADO_SHOW=app +AVOCADO_SHOW?=app ifndef AVOCADO_TAGS AVOCADO_CMDLINE_TAGS=$(patsubst %-softmmu,-t arch:%, \ $(filter %-softmmu,$(TARGETS))) -- 2.41.0
[PATCH 0/3] util/fifo8: Introduce fifo8_change_capacity()
Preliminary series to PL011 FIFO work: - Clarify doc in qemu_chr_fe_* - Introduce fifo8_change_capacity() Philippe Mathieu-Daudé (3): chardev/char-fe: Document returned value on error util/fifo8: Use fifo8_reset() in fifo8_create() util/fifo8: Introduce fifo8_change_capacity() include/chardev/char-fe.h | 3 +++ include/qemu/fifo8.h | 10 ++ util/fifo8.c | 22 ++ 3 files changed, 27 insertions(+), 8 deletions(-) -- 2.41.0
[PATCH 3/3] util/fifo8: Introduce fifo8_change_capacity()
FIFOs can be resized at runtime. Introduce the
fifo8_change_capacity() method to do that.
When capacity is changed, the FIFO must be reset.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/fifo8.h | 10 ++
util/fifo8.c | 7 +++
2 files changed, 17 insertions(+)
diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h
index c6295c6ff0..9fe0555a24 100644
--- a/include/qemu/fifo8.h
+++ b/include/qemu/fifo8.h
@@ -31,6 +31,16 @@ void fifo8_create(Fifo8 *fifo, uint32_t capacity);
void fifo8_destroy(Fifo8 *fifo);
+/**
+ * fifo8_change_capacity:
+ * @fifo: struct Fifo8 to change the capacity
+ * @capacity: new capacity of the FIFO
+ *
+ * Change a FIFO capacity to the specified size. The FIFO is reset.
+ */
+
+void fifo8_change_capacity(Fifo8 *fifo, uint32_t capacity);
+
/**
* fifo8_push:
* @fifo: FIFO to push to
diff --git a/util/fifo8.c b/util/fifo8.c
index 2925fe5611..c453afd774 100644
--- a/util/fifo8.c
+++ b/util/fifo8.c
@@ -34,6 +34,13 @@ void fifo8_destroy(Fifo8 *fifo)
g_free(fifo->data);
}
+void fifo8_change_capacity(Fifo8 *fifo, uint32_t capacity)
+{
+fifo->data = g_renew(uint8_t, fifo->data, capacity);
+fifo->capacity = capacity;
+fifo8_reset(fifo);
+}
+
void fifo8_push(Fifo8 *fifo, uint8_t data)
{
assert(fifo->num < fifo->capacity);
--
2.41.0
[PATCH 1/3] chardev/char-fe: Document returned value on error
qemu_chr_fe_add_watch() and qemu_chr_fe_write[_all]() return -1 on error. Mention it in the documentation. Signed-off-by: Philippe Mathieu-Daudé --- include/chardev/char-fe.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index ecef182835..3310449eaf 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -228,6 +228,7 @@ guint qemu_chr_fe_add_watch(CharBackend *be, GIOCondition cond, * is thread-safe. * * Returns: the number of bytes consumed (0 if no associated Chardev) + * or -1 on error. */ int qemu_chr_fe_write(CharBackend *be, const uint8_t *buf, int len); @@ -242,6 +243,7 @@ int qemu_chr_fe_write(CharBackend *be, const uint8_t *buf, int len); * attempted to be written. This function is thread-safe. * * Returns: the number of bytes consumed (0 if no associated Chardev) + * or -1 on error. */ int qemu_chr_fe_write_all(CharBackend *be, const uint8_t *buf, int len); @@ -253,6 +255,7 @@ int qemu_chr_fe_write_all(CharBackend *be, const uint8_t *buf, int len); * Read data to a buffer from the back end. * * Returns: the number of bytes read (0 if no associated Chardev) + * or -1 on error. */ int qemu_chr_fe_read_all(CharBackend *be, uint8_t *buf, int len); -- 2.41.0
[PATCH 2/3] util/fifo8: Use fifo8_reset() in fifo8_create()
Avoid open-coding fifo8_reset() in fifo8_create().
Signed-off-by: Philippe Mathieu-Daudé
---
util/fifo8.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/util/fifo8.c b/util/fifo8.c
index 4e01b532d9..2925fe5611 100644
--- a/util/fifo8.c
+++ b/util/fifo8.c
@@ -16,12 +16,17 @@
#include "migration/vmstate.h"
#include "qemu/fifo8.h"
+void fifo8_reset(Fifo8 *fifo)
+{
+fifo->num = 0;
+fifo->head = 0;
+}
+
void fifo8_create(Fifo8 *fifo, uint32_t capacity)
{
fifo->data = g_new(uint8_t, capacity);
fifo->capacity = capacity;
-fifo->head = 0;
-fifo->num = 0;
+fifo8_reset(fifo);
}
void fifo8_destroy(Fifo8 *fifo)
@@ -97,12 +102,6 @@ const uint8_t *fifo8_pop_buf(Fifo8 *fifo, uint32_t max,
uint32_t *numptr)
return fifo8_peekpop_buf(fifo, max, numptr, true);
}
-void fifo8_reset(Fifo8 *fifo)
-{
-fifo->num = 0;
-fifo->head = 0;
-}
-
bool fifo8_is_empty(Fifo8 *fifo)
{
return (fifo->num == 0);
--
2.41.0
[PATCH] tests/avocado: Move common Avocado tags to class
When Avocado tags apply to all tests in a class,
we can define them once in the class: they will
be applied to all test methods.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/avocado/boot_linux.py | 2 +-
tests/avocado/boot_xen.py | 17 +
tests/avocado/machine_aarch64_virt.py | 10 --
3 files changed, 6 insertions(+), 23 deletions(-)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index cdce4cbcba..df6cf209ef 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -64,12 +64,12 @@ def test_pc_q35_kvm(self):
class BootLinuxAarch64(LinuxTest):
"""
:avocado: tags=arch:aarch64
-:avocado: tags=machine:virt
"""
timeout = 720
def test_virt_kvm(self):
"""
+:avocado: tags=machine:virt
:avocado: tags=accel:kvm
:avocado: tags=cpu:host
"""
diff --git a/tests/avocado/boot_xen.py b/tests/avocado/boot_xen.py
index fc2faeedb5..93bfb0c161 100644
--- a/tests/avocado/boot_xen.py
+++ b/tests/avocado/boot_xen.py
@@ -61,8 +61,6 @@ def launch_xen(self, xen_path):
class BootXen(BootXenBase):
-
-def test_arm64_xen_411_and_dom0(self):
"""
:avocado: tags=arch:aarch64
:avocado: tags=accel:tcg
@@ -70,6 +68,7 @@ def test_arm64_xen_411_and_dom0(self):
:avocado: tags=machine:virt
"""
+def test_arm64_xen_411_and_dom0(self):
# archive of file from https://deb.debian.org/debian/pool/main/x/xen/
xen_url = ('https://fileserver.linaro.org/s/JSsewXGZ6mqxPr5/'
'download?path=%2F='
@@ -81,13 +80,6 @@ def test_arm64_xen_411_and_dom0(self):
self.launch_xen(xen_path)
def test_arm64_xen_414_and_dom0(self):
-"""
-:avocado: tags=arch:aarch64
-:avocado: tags=accel:tcg
-:avocado: tags=cpu:cortex-a57
-:avocado: tags=machine:virt
-"""
-
# archive of file from https://deb.debian.org/debian/pool/main/x/xen/
xen_url = ('https://fileserver.linaro.org/s/JSsewXGZ6mqxPr5/'
'download?path=%2F='
@@ -99,13 +91,6 @@ def test_arm64_xen_414_and_dom0(self):
self.launch_xen(xen_path)
def test_arm64_xen_415_and_dom0(self):
-"""
-:avocado: tags=arch:aarch64
-:avocado: tags=accel:tcg
-:avocado: tags=cpu:cortex-a57
-:avocado: tags=machine:virt
-"""
-
xen_url = ('https://fileserver.linaro.org/'
's/JSsewXGZ6mqxPr5/download'
'?path=%2F=xen-upstream-4.15-unstable.deb')
diff --git a/tests/avocado/machine_aarch64_virt.py
b/tests/avocado/machine_aarch64_virt.py
index a90dc6ff4b..0ef6df4b0d 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -20,6 +20,10 @@
from avocado.utils.path import find_command
class Aarch64VirtMachine(QemuSystemTest):
+"""
+:avocado: tags=arch:aarch64
+:avocado: tags=machine:virt
+"""
KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
timeout = 360
@@ -33,8 +37,6 @@ def wait_for_console_pattern(self, success_message, vm=None):
# Other test profiles should use more minimal boots
def test_alpine_virt_tcg_gic_max(self):
"""
-:avocado: tags=arch:aarch64
-:avocado: tags=machine:virt
:avocado: tags=accel:tcg
"""
iso_url = ('https://dl-cdn.alpinelinux.org/'
@@ -129,8 +131,6 @@ def common_aarch64_virt(self, machine):
def test_aarch64_virt_gicv3(self):
"""
-:avocado: tags=arch:aarch64
-:avocado: tags=machine:virt
:avocado: tags=accel:tcg
:avocado: tags=cpu:max
"""
@@ -138,8 +138,6 @@ def test_aarch64_virt_gicv3(self):
def test_aarch64_virt_gicv2(self):
"""
-:avocado: tags=arch:aarch64
-:avocado: tags=machine:virt
:avocado: tags=accel:tcg
:avocado: tags=cpu:max
"""
--
2.41.0
Re: [PATCH] tests/avocado: Move LinuxTest related code into a separate file
On 19/7/24 14:49, Philippe Mathieu-Daudé wrote: On 19/7/24 11:50, Thomas Huth wrote: Only some few tests are using the LinuxTest class. Move the related code into a separate file so that this does not pollute the main namespace. Signed-off-by: Thomas Huth --- tests/avocado/avocado_qemu/__init__.py | 239 +- tests/avocado/avocado_qemu/linuxtest.py | 253 tests/avocado/boot_linux.py | 3 +- tests/avocado/hotplug_blk.py | 2 +- tests/avocado/hotplug_cpu.py | 2 +- tests/avocado/intel_iommu.py | 2 +- tests/avocado/replay_linux.py | 2 +- tests/avocado/smmu.py | 3 +- 8 files changed, 262 insertions(+), 244 deletions(-) create mode 100644 tests/avocado/avocado_qemu/linuxtest.py Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé
Re: [PATCH v6 0/4] docs/interop/firmware.json: scripts/qapi-gen.py compatibility
On 19/7/24 09:37, Thomas Weißschuh wrote: Thomas Weißschuh (4): docs/interop/firmware.json: add new enum FirmwareFormat docs/interop/firmware.json: add new enum FirmwareArchitecture docs/interop/firmware.json: convert "Example" section docs: add test for firmware.json QAPI Thanks, series queued!
Re: [PATCH v5 00/19] Reconstruct loongson ipi driver
On 19/7/24 14:56, Jiaxun Yang wrote: 在2024年7月18日七月 下午9:32，Philippe Mathieu-Daudé写道： Since v4: - Fix build failure due to rebase (Song) - Loongarch -> LoongArch (Song) - Added Song's tags Since v3: - Use DEFINE_TYPES() macro (unreviewed patch #1) - Update MAINTAINERS - Added Bibo's tags For the whole series: Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Yeah! Thanks! Tested on MIPS loongson3-virt with 2, 4 CPUs, all working fine. I'll get this covered by CI later. Thanks, I'm queuing this series.
Re: [PATCH] tests/avocado: Move LinuxTest related code into a separate file
On 19/7/24 11:50, Thomas Huth wrote: Only some few tests are using the LinuxTest class. Move the related code into a separate file so that this does not pollute the main namespace. Signed-off-by: Thomas Huth --- tests/avocado/avocado_qemu/__init__.py | 239 +- tests/avocado/avocado_qemu/linuxtest.py | 253 tests/avocado/boot_linux.py | 3 +- tests/avocado/hotplug_blk.py| 2 +- tests/avocado/hotplug_cpu.py| 2 +- tests/avocado/intel_iommu.py| 2 +- tests/avocado/replay_linux.py | 2 +- tests/avocado/smmu.py | 3 +- 8 files changed, 262 insertions(+), 244 deletions(-) create mode 100644 tests/avocado/avocado_qemu/linuxtest.py Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH] tests/avocado/mem-addr-space-check: Remove unused "import signal"
On 19/7/24 11:54, Thomas Huth wrote: The "signal" module is not used here, so we can remove this import statement. Signed-off-by: Thomas Huth --- tests/avocado/mem-addr-space-check.py | 1 - 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PULL 3/3] hw/loongarch: Modify flash block size to 256K
On 19/7/24 10:18, Daniel P. Berrangé wrote: On Fri, Jul 19, 2024 at 10:12:20AM +0200, Philippe Mathieu-Daudé wrote: On 19/7/24 04:26, Song Gao wrote: From: Xianglai Li loongarch added a common library for edk2 to parse flash base addresses through fdt. For compatibility with other architectures, the flash block size in qemu is now changed to 256k. Signed-off-by: Xianglai Li Reviewed-by: Song Gao Message-Id: <20240624033319.999631-1-lixiang...@loongson.cn> Signed-off-by: Song Gao --- include/hw/loongarch/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..603c1cebdb 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -20,7 +20,7 @@ #define VIRT_FWCFG_BASE 0x1e02UL #define VIRT_BIOS_BASE 0x1c00UL #define VIRT_BIOS_SIZE (16 * MiB) -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) Again, I believe this breaks machine migration. See the recent example Daniel explained to me: https://lore.kernel.org/qemu-devel/zn6eq39q57ktm...@redhat.com/ Yes, changing flash size breaks migration compat, but note that loongarch does not have any versioned machine types, so it has zero migration compat right now regardles of this change. IOW, now is the right time to make the change, before someone asks for versioned machines with loongarch. Oh I see now, thanks for clarifying! It would have been nice to mention that in the commit description, but too late so I don't mind. Regards, Phil.
Re: [PULL 3/3] hw/loongarch: Modify flash block size to 256K
On 19/7/24 04:26, Song Gao wrote: From: Xianglai Li loongarch added a common library for edk2 to parse flash base addresses through fdt. For compatibility with other architectures, the flash block size in qemu is now changed to 256k. Signed-off-by: Xianglai Li Reviewed-by: Song Gao Message-Id: <20240624033319.999631-1-lixiang...@loongson.cn> Signed-off-by: Song Gao --- include/hw/loongarch/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..603c1cebdb 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -20,7 +20,7 @@ #define VIRT_FWCFG_BASE 0x1e02UL #define VIRT_BIOS_BASE 0x1c00UL #define VIRT_BIOS_SIZE (16 * MiB) -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) Again, I believe this breaks machine migration. See the recent example Daniel explained to me: https://lore.kernel.org/qemu-devel/zn6eq39q57ktm...@redhat.com/
Re: [PATCH] tests/tcg/aarch64: Fix test-mte.py
On 19/7/24 02:41, Richard Henderson wrote:
Python 3.12 warns:
TESTgdbstub MTE support on aarch64
/home/rth/qemu/src/tests/tcg/aarch64/gdbstub/test-mte.py:21: SyntaxWarning:
invalid escape sequence '\('
PATTERN_0 = "Memory tags for address 0x[0-9a-f]+ match \(0x[0-9a-f]+\)."
Double up the \ to pass one through to the pattern.
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/gdbstub/test-mte.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2] mem/cxl_type3: Fix overlapping region validation error
On 19/7/24 03:28, Yao Xingtao via wrote:
When injecting a new poisoned region through qmp_cxl_inject_poison(),
the newly injected region should not overlap with existing poisoned
regions.
The current validation method does not consider the following
overlapping region:
+---+---+---+
| a | b(a) | a |
+---+---+---+
(a is a newly added region, b is an existing region, and b is a
subregion of a)
Cc: qemu-sta...@nongnu.org
Fixes: 9547754f40 ("hw/cxl: QMP based poison injection support")
Reviewed-by: Jonathan Cameron
Suggested-by: Peter Maydell
Signed-off-by: Yao Xingtao
---
V1[1] -> V2:
- Use ranges_overlap() to improve code readability
- Replace the ASCII extended graph to ASCII basic in comment.
[1]
https://lore.kernel.org/qemu-devel/20240718090753.59163-1-yaoxt.f...@fujitsu.com
---
hw/mem/cxl_type3.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Re: [PATCH] qapi/machine: Belatedly document target loongarch64 is since 7.1
On 18/7/24 16:10, Markus Armbruster wrote: Fixes: a8a506c39070 (hw/loongarch: Add support loongson3 virt machine type.) Signed-off-by: Markus Armbruster --- qapi/machine.json | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
[PATCH v5 04/19] hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_finalize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index d870af39c1..960d1e604f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -357,13 +357,18 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
dc->vmsd = _loongson_ipi;
}
-static void loongson_ipi_finalize(Object *obj)
+static void loongson_ipi_common_finalize(Object *obj)
{
LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
+static void loongson_ipi_finalize(Object *obj)
+{
+loongson_ipi_common_finalize(obj);
+}
+
static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
--
2.41.0
[PATCH v5 02/19] hw/intc/loongson_ipi: Access memory in little endian
From: Bibo Mao
Loongson IPI is only available in little-endian,
so use that to access the guest memory (in case
we run on a big-endian host).
Signed-off-by: Bibo Mao
Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support")
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index dc82caea0d..d315f6f303 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
+#include "exec/memory.h"
#include "migration/vmstate.h"
#ifdef TARGET_LOONGARCH64
#include "target/loongarch/cpu.h"
@@ -102,7 +103,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
-data = address_space_ldl(iocsr_as, addr, attrs, NULL);
+data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
@@ -113,7 +114,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
data &= mask;
data |= (val >> 32) & ~mask;
-address_space_stl(iocsr_as, addr, data, attrs, NULL);
+address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
return MEMTX_OK;
}
--
2.41.0
[PATCH v5 13/19] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers
From: Bibo Mao
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi_common.h | 6 ++
hw/intc/loongson_ipi.c| 10 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 5447e9f650..a75882f775 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -10,6 +10,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#include "exec/memattrs.h"
#define IPI_MBX_NUM 4
@@ -44,6 +45,11 @@ struct LoongsonIPICommonClass {
CPUState *(*cpu_by_arch_id)(int64_t id);
};
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs);
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs);
+
/* Mainy used by iocsr read and write */
#define SMP_IPI_MAILBOX 0x1000ULL
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 39bcf0031d..a2db8bb2e2 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,9 +24,8 @@
#endif
#include "trace.h"
-static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
uint64_t ret = 0;
@@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
-uint64_t val, unsigned size,
-MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
--
2.41.0
[PATCH v5 10/19] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data()
From: Bibo Mao
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index f3d1f031bc..a54db87638 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
return NULL;
}
-static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
@@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
return MEMTX_OK;
}
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult mail_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs
attrs)
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult any_send(LoongsonIPICommonState *ipi,
+uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = val & 0x;
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
@@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = {
static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
+LoongsonIPICommonState *ipi = opaque;
MemTxResult ret = MEMTX_OK;
addr &= 0xfff;
switch (addr) {
case MAIL_SEND_OFFSET:
-ret = mail_send(val, attrs);
+ret = mail_send(ipi, val, attrs);
break;
case ANY_SEND_OFFSET:
-ret = any_send(val, attrs);
+ret = any_send(ipi, val, attrs);
break;
default:
break;
--
2.41.0
[PATCH v5 15/19] hw/intc/loongarch_ipi: Add loongarch IPI support
From: Bibo Mao
Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.
Signed-off-by: Bibo Mao
[PMD: Rebased and simplified]
Co-Developed-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Song Gao
---
include/hw/intc/loongarch_ipi.h | 25
hw/intc/loongarch_ipi.c | 68 +
hw/intc/Kconfig | 4 ++
hw/intc/meson.build | 1 +
4 files changed, 98 insertions(+)
create mode 100644 include/hw/intc/loongarch_ipi.h
create mode 100644 hw/intc/loongarch_ipi.c
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 00..276b3040a3
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch IPI interrupt header files
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI)
+
+struct LoongarchIPIState {
+LoongsonIPICommonState parent_obj;
+};
+
+struct LoongarchIPIClass {
+LoongsonIPICommonClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 00..2ae1a42c46
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch IPI interrupt support
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "target/loongarch/cpu.h"
+
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
+return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
+
+static int archid_cmp(const void *a, const void *b)
+{
+ CPUArchId *archid_a = (CPUArchId *)a;
+ CPUArchId *archid_b = (CPUArchId *)b;
+
+ return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+CPUArchId apic_id, *found_cpu;
+
+apic_id.arch_id = id;
+found_cpu = bsearch(_id, ms->possible_cpus->cpus,
+ms->possible_cpus->len,
+sizeof(*ms->possible_cpus->cpus),
+archid_cmp);
+
+return found_cpu;
+}
+
+static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+{
+MachineState *machine = MACHINE(qdev_get_machine());
+CPUArchId *archid;
+
+archid = find_cpu_by_archid(machine, arch_id);
+if (archid) {
+return CPU(archid->cpu);
+}
+
+return NULL;
+}
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+
+licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
+}
+
+static const TypeInfo loongarch_ipi_types[] = {
+{
+.name = TYPE_LOONGARCH_IPI,
+.parent = TYPE_LOONGSON_IPI_COMMON,
+.class_init = loongarch_ipi_class_init,
+}
+};
+
+DEFINE_TYPES(loongarch_ipi_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a2a0fdca85..dd405bdb5d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -94,6 +94,10 @@ config LOONGSON_IPI
bool
select LOONGSON_IPI_COMMON
+config LOONGARCH_IPI
+bool
+select LOONGSON_IPI_COMMON
+
config LOONGARCH_PCH_PIC
bool
select UNIMP
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a09a527207..f4d81eb8e4 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true:
files('loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true:
files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true:
files('loongarch_extioi.c'))
--
2.41.0
[PATCH v5 17/19] hw/intc/loongson_ipi: Restrict to MIPS
From: Bibo Mao
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
MAINTAINERS| 2 --
hw/intc/loongson_ipi.c | 14 --
2 files changed, 16 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a670c8ee67..c2d51b0158 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1250,10 +1250,8 @@ F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
F: include/hw/intc/loongson_ipi_common.h
-F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
F: hw/intc/loongson_ipi_common.c
-F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
F: gdb-xml/loongarch*.xml
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 86badb2972..051e910586 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -16,22 +16,9 @@
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "migration/vmstate.h"
-#ifdef TARGET_LOONGARCH64
-#include "target/loongarch/cpu.h"
-#endif
-#ifdef TARGET_MIPS
#include "target/mips/cpu.h"
-#endif
#include "trace.h"
-#ifdef TARGET_LOONGARCH64
-static AddressSpace *get_iocsr_as(CPUState *cpu)
-{
-return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
-}
-#endif
-
-#ifdef TARGET_MIPS
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
if (ase_lcsr_available(_CPU(cpu)->env)) {
@@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
return NULL;
}
-#endif
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
--
2.41.0
[PATCH v5 11/19] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi_common.h | 2 ++
hw/intc/loongson_ipi.c| 16
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 891b43644d..e49c156db3 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -39,6 +39,8 @@ struct LoongsonIPICommonState {
struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
+
+AddressSpace *(*get_iocsr_as)(CPUState *cpu);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a54db87638..2c8829c3cc 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
return loongson_ipi_core_readl(s, addr, data, size, attrs);
}
-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
-{
#ifdef TARGET_LOONGARCH64
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
#endif
+
#ifdef TARGET_MIPS
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
if (ase_lcsr_available(_CPU(cpu)->env)) {
return _CPU(cpu)->env.iocsr.as;
}
-#endif
+
return NULL;
}
+#endif
static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
+AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
if (!iocsr_as) {
return MEMTX_DECODE_ERROR;
@@ -338,9 +344,11 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
+licc->get_iocsr_as = get_iocsr_as;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v5 19/19] docs: Correct Loongarch -> LoongArch
Signed-off-by: Philippe Mathieu-Daudé --- docs/about/emulation.rst | 2 +- hw/rtc/ls7a_rtc.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index b5ff9c5f69..3bfe8cc14a 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -42,7 +42,7 @@ depending on the guest architecture. - :ref:`Yes` - Yes - The ubiquitous desktop PC CPU architecture, 32 and 64 bit. - * - Loongarch + * - LoongArch - Yes - Yes - A MIPS-like 64bit RISC architecture developed in China diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c index 052201c2cd..3226b6105e 100644 --- a/hw/rtc/ls7a_rtc.c +++ b/hw/rtc/ls7a_rtc.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Loongarch LS7A Real Time Clock emulation + * LoongArch LS7A Real Time Clock emulation * * Copyright (C) 2021 Loongson Technology Corporation Limited */ -- 2.41.0
[PATCH v5 18/19] hw/intc/loongson_ipi: Remove unused headers
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 051e910586..aa1b0a474c 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -6,18 +6,9 @@
*/
#include "qemu/osdep.h"
-#include "hw/boards.h"
-#include "hw/sysbus.h"
#include "hw/intc/loongson_ipi.h"
-#include "hw/irq.h"
-#include "hw/qdev-properties.h"
#include "qapi/error.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "exec/memory.h"
-#include "migration/vmstate.h"
#include "target/mips/cpu.h"
-#include "trace.h"
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
--
2.41.0
[PATCH v5 16/19] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI
From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig| 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ -ipi = qdev_new(TYPE_LOONGSON_IPI); +ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), _fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS -select LOONGSON_IPI +select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI -- 2.41.0
[PATCH v5 07/19] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h
From: Bibo Mao
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi.h| 18 --
include/hw/intc/loongson_ipi_common.h | 19 +++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 82cb64ca40..d53bd5dcfe 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,24 +12,6 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-/* Mainy used by iocsr read and write */
-#define SMP_IPI_MAILBOX 0x1000ULL
-#define CORE_STATUS_OFF 0x0
-#define CORE_EN_OFF 0x4
-#define CORE_SET_OFF 0x8
-#define CORE_CLEAR_OFF0xc
-#define CORE_BUF_20 0x20
-#define CORE_BUF_28 0x28
-#define CORE_BUF_30 0x30
-#define CORE_BUF_38 0x38
-#define IOCSR_IPI_SEND0x40
-#define IOCSR_MAIL_SEND 0x48
-#define IOCSR_ANY_SEND0x158
-
-#define MAIL_SEND_ADDR(SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
-#define MAIL_SEND_OFFSET 0
-#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
-
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 70ac69d0ba..b43b77bda6 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -23,4 +23,23 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
};
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+#define IOCSR_MAIL_SEND 0x48
+#define IOCSR_ANY_SEND 0x158
+
+#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET0
+#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+
#endif
--
2.41.0
[PATCH v5 14/19] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c
From: Bibo Mao
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c| 269 +
hw/intc/loongson_ipi_common.c | 272 ++
2 files changed, 274 insertions(+), 267 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a2db8bb2e2..86badb2972 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,56 +24,6 @@
#endif
#include "trace.h"
-MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-uint64_t ret = 0;
-int index = 0;
-
-addr &= 0xff;
-switch (addr) {
-case CORE_STATUS_OFF:
-ret = s->status;
-break;
-case CORE_EN_OFF:
-ret = s->en;
-break;
-case CORE_SET_OFF:
-ret = 0;
-break;
-case CORE_CLEAR_OFF:
-ret = 0;
-break;
-case CORE_BUF_20 ... CORE_BUF_38 + 4:
-index = (addr - CORE_BUF_20) >> 2;
-ret = s->buf[index];
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
-break;
-}
-
-trace_loongson_ipi_read(size, (uint64_t)addr, ret);
-*data = ret;
-return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
-uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-LoongsonIPICommonState *ipi = opaque;
-IPICore *s;
-
-if (attrs.requester_id >= ipi->num_cpu) {
-return MEMTX_DECODE_ERROR;
-}
-
-s = >cpu[attrs.requester_id];
-return loongson_ipi_core_readl(s, addr, data, size, attrs);
-}
-
#ifdef TARGET_LOONGARCH64
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
@@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
}
#endif
-static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
- uint64_t val, hwaddr addr, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
-
-if (!iocsr_as) {
-return MEMTX_DECODE_ERROR;
-}
-
-/*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
-if ((val >> 27) & 0xf) {
-data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
-for (i = 0; i < 4; i++) {
-/* get mask for byte writing */
-if (val & (0x1 << (27 + i))) {
-mask |= 0xff << (i * 8);
-}
-}
-}
-
-data &= mask;
-data |= (val >> 32) & ~mask;
-address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
-
-return MEMTX_OK;
-}
-
-static MemTxResult mail_send(LoongsonIPICommonState *ipi,
- uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-static MemTxResult any_send(LoongsonIPICommonState *ipi,
-uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = val & 0x;
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-LoongsonIPICommonState *ipi = s->ipi;
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int index = 0;
-uint32_t cpuid;
-uint8_t vector;
-CPUState *cs;
-
-addr &= 0xff;
-trace_loongson_ipi_write(size, (uint64_t)addr, val);
-switch (ad
[PATCH v5 12/19] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own
cpu_by_arch_id() handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi_common.h | 1 +
hw/intc/loongson_ipi.c| 10 +++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index e49c156db3..5447e9f650 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -41,6 +41,7 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
+CPUState *(*cpu_by_arch_id)(int64_t id);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 2c8829c3cc..39bcf0031d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState
*ipi, CPUState *cpu,
static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
@@ -349,6 +352,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = cpu_by_arch_id;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v5 06/19] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub
From: Bibo Mao
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
MAINTAINERS | 4
include/hw/intc/loongson_ipi.h| 13 +++--
include/hw/intc/loongson_ipi_common.h | 26 ++
hw/intc/loongson_ipi.c| 7 ---
hw/intc/loongson_ipi_common.c | 22 ++
hw/intc/Kconfig | 4
hw/intc/meson.build | 1 +
7 files changed, 72 insertions(+), 5 deletions(-)
create mode 100644 include/hw/intc/loongson_ipi_common.h
create mode 100644 hw/intc/loongson_ipi_common.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d9811458c..a670c8ee67 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1249,8 +1249,10 @@ F: configs/devices/loongarch64-softmmu/default.mak
F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
@@ -1385,11 +1387,13 @@ Loongson-3 virtual platforms
M: Huacai Chen
R: Jiaxun Yang
S: Maintained
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: hw/intc/loongson_liointc.c
F: hw/mips/loongson3_bootp.c
F: hw/mips/loongson3_bootp.h
F: hw/mips/loongson3_virt.c
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: include/hw/intc/loongson_liointc.h
F: tests/avocado/machine_mips_loongson3v.py
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index efb772f384..82cb64ca40 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -8,6 +8,8 @@
#ifndef HW_LOONGSON_IPI_H
#define HW_LOONGSON_IPI_H
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
/* Mainy used by iocsr read and write */
@@ -31,7 +33,7 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
+OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
@@ -45,8 +47,15 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
+struct LoongsonIPIClass {
+LoongsonIPICommonClass parent_class;
+
+DeviceRealize parent_realize;
+};
+
struct LoongsonIPIState {
-SysBusDevice parent_obj;
+LoongsonIPICommonState parent_obj;
+
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
new file mode 100644
index 00..70ac69d0ba
--- /dev/null
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGSON_IPI_COMMON_H
+#define HW_LOONGSON_IPI_COMMON_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
+OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
+LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+
+struct LoongsonIPICommonState {
+SysBusDevice parent_obj;
+};
+
+struct LoongsonIPICommonClass {
+SysBusDeviceClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index bab4d8816b..20f3f6bd3f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -362,8 +362,10 @@ static Property ipi_properties[] = {
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
-dc->realize = loongson_ipi_realize;
+device_class_set_parent_realize(dc, loongson_ipi_realize,
+>parent_realize);
device_class_set_props(dc, ipi_properties);
dc->vmsd = _loongson_ipi;
}
@@ -383,8 +385,7 @@ static void loongson_ipi_finalize(Object *obj)
static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
-.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPIState),
+.parent = TYPE_LOONGSON_IPI_COMMON,
.class_init = loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
}
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
new file mode 100644
index 00..970525c242
--- /dev/null
+++ b/hw/i
[PATCH v5 00/19] Reconstruct loongson ipi driver
Since v4: - Fix build failure due to rebase (Song) - Loongarch -> LoongArch (Song) - Added Song's tags Since v3: - Use DEFINE_TYPES() macro (unreviewed patch #1) - Update MAINTAINERS - Added Bibo's tags Thanks, Phil. Bibo Mao (16): hw/intc/loongson_ipi: Access memory in little endian hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize() hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c hw/intc/loongarch_ipi: Add loongarch IPI support hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé (3): hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro hw/intc/loongson_ipi: Remove unused headers docs: Correct Loongarch -> LoongArch MAINTAINERS | 6 +- docs/about/emulation.rst | 2 +- include/hw/intc/loongarch_ipi.h | 25 ++ include/hw/intc/loongson_ipi.h| 50 +--- include/hw/intc/loongson_ipi_common.h | 72 ++ include/hw/loongarch/virt.h | 1 - hw/intc/loongarch_ipi.c | 68 + hw/intc/loongson_ipi.c| 355 +++--- hw/intc/loongson_ipi_common.c | 344 + hw/loongarch/virt.c | 4 +- hw/rtc/ls7a_rtc.c | 2 +- hw/intc/Kconfig | 8 + hw/intc/meson.build | 2 + hw/loongarch/Kconfig | 2 +- 14 files changed, 570 insertions(+), 371 deletions(-) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongson_ipi_common.c -- 2.41.0
[PATCH v5 05/19] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 960d1e604f..bab4d8816b 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
sysbus_init_mmio(sbd, >ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
-if (s->cpu == NULL) {
-error_setg(errp, "Memory allocation for IPICore faile");
+for (i = 0; i < s->num_cpu; i++) {
+s->cpu[i].ipi = s;
+
+qdev_init_gpio_out(dev, >cpu[i].irq, 1);
+}
+}
+
+static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+{
+LoongsonIPIState *s = LOONGSON_IPI(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+Error *local_err = NULL;
+
+loongson_ipi_common_realize(dev, _err);
+if (local_err) {
+error_propagate(errp, local_err);
return;
}
-for (i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi = s;
+for (unsigned i = 0; i < s->num_cpu; i++) {
s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
-
-qdev_init_gpio_out(dev, >cpu[i].irq, 1);
}
}
--
2.41.0
[PATCH v5 08/19] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState
From: Bibo Mao
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi.h | 2 +-
hw/intc/loongson_ipi.c | 9 ++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index d53bd5dcfe..00a65a82fb 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass,
LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
-MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
uint32_t set;
@@ -38,6 +37,7 @@ struct LoongsonIPIClass {
struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
+MemoryRegion *ipi_mmio_mem;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 20f3f6bd3f..2319aea18f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
+s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
for (unsigned i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
-memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
+memory_region_init_io(>ipi_mmio_mem[i], OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
-sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
+sysbus_init_mmio(sbd, >ipi_mmio_mem[i]);
}
}
@@ -379,6 +379,9 @@ static void loongson_ipi_common_finalize(Object *obj)
static void loongson_ipi_finalize(Object *obj)
{
+LoongsonIPIState *s = LOONGSON_IPI(obj);
+
+g_free(s->ipi_mmio_mem);
loongson_ipi_common_finalize(obj);
}
--
2.41.0
[PATCH v5 09/19] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h
From: Bibo Mao
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi.h| 17
include/hw/intc/loongson_ipi_common.h | 18 +
hw/intc/loongson_ipi.c| 56 +--
hw/intc/loongson_ipi_common.c | 50
4 files changed, 77 insertions(+), 64 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 00a65a82fb..bb5581 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,22 +12,9 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-#define IPI_MBX_NUM 4
-
#define TYPE_LOONGSON_IPI "loongson_ipi"
OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
-typedef struct IPICore {
-LoongsonIPIState *ipi;
-uint32_t status;
-uint32_t en;
-uint32_t set;
-uint32_t clear;
-/* 64bit buf divide into 2 32bit buf */
-uint32_t buf[IPI_MBX_NUM * 2];
-qemu_irq irq;
-} IPICore;
-
struct LoongsonIPIClass {
LoongsonIPICommonClass parent_class;
@@ -38,10 +25,6 @@ struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
MemoryRegion *ipi_mmio_mem;
-MemoryRegion ipi_iocsr_mem;
-MemoryRegion ipi64_iocsr_mem;
-uint32_t num_cpu;
-IPICore *cpu;
};
#endif
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index b43b77bda6..891b43644d 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -11,12 +11,30 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#define IPI_MBX_NUM 4
+
#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+typedef struct IPICore {
+LoongsonIPICommonState *ipi;
+uint32_t status;
+uint32_t en;
+uint32_t set;
+uint32_t clear;
+/* 64bit buf divide into 2 32bit buf */
+uint32_t buf[IPI_MBX_NUM * 2];
+qemu_irq irq;
+} IPICore;
+
struct LoongsonIPICommonState {
SysBusDevice parent_obj;
+
+MemoryRegion ipi_iocsr_mem;
+MemoryRegion ipi64_iocsr_mem;
+uint32_t num_cpu;
+IPICore *cpu;
};
struct LoongsonIPICommonClass {
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 2319aea18f..f3d1f031bc 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPIState *ipi = s->ipi;
+LoongsonIPICommonState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPIState *s = LOONGSON_IPI(dev);
+LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev,
Error **errp)
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
+LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev);
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *local_err = NULL;
@@ -320,45 +321,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
-s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
-for (unsigned i = 0; i < s->num_cpu; i++) {
+s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
+for (unsigned i = 0; i < sc->num_cpu; i++) {
g_autofree char *nam
[PATCH v5 01/19] hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Song Gao
---
hw/intc/loongson_ipi.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e6a7142480..dc82caea0d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -363,17 +363,14 @@ static void loongson_ipi_finalize(Object *obj)
g_free(s->cpu);
}
-static const TypeInfo loongson_ipi_info = {
-.name = TYPE_LOONGSON_IPI,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPI),
-.class_init= loongson_ipi_class_init,
-.instance_finalize = loongson_ipi_finalize,
+static const TypeInfo loongson_ipi_types[] = {
+{
+.name = TYPE_LOONGSON_IPI,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(LoongsonIPI),
+.class_init = loongson_ipi_class_init,
+.instance_finalize = loongson_ipi_finalize,
+}
};
-static void loongson_ipi_register_types(void)
-{
-type_register_static(_ipi_info);
-}
-
-type_init(loongson_ipi_register_types)
+DEFINE_TYPES(loongson_ipi_types)
--
2.41.0
[PATCH v5 03/19] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Acked-by: Song Gao
---
include/hw/intc/loongson_ipi.h | 6 +++---
hw/intc/loongson_ipi.c | 16
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 3f795edbf3..efb772f384 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -31,10 +31,10 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
+OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
typedef struct IPICore {
-LoongsonIPI *ipi;
+LoongsonIPIState *ipi;
MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
@@ -45,7 +45,7 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
-struct LoongsonIPI {
+struct LoongsonIPIState {
SysBusDevice parent_obj;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index d315f6f303..d870af39c1 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPI *ipi = s->ipi;
+LoongsonIPIState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPI *s = LOONGSON_IPI(dev);
+LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -337,14 +337,14 @@ static const VMStateDescription vmstate_loongson_ipi = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
-VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
+VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
vmstate_ipi_core, IPICore),
VMSTATE_END_OF_LIST()
}
};
static Property ipi_properties[] = {
-DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
+DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -359,7 +359,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
static void loongson_ipi_finalize(Object *obj)
{
-LoongsonIPI *s = LOONGSON_IPI(obj);
+LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
@@ -368,7 +368,7 @@ static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPI),
+.instance_size = sizeof(LoongsonIPIState),
.class_init = loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
}
--
2.41.0
Re: [PATCH 06/15] tests/plugins: use qemu_plugin_outs for inline stats
On 18/7/24 11:45, Alex Bennée wrote: Using bare printf's in plugins is perfectly acceptable but they do rather mess up the output of "make check-tcg". Convert the printfs to use g_string and then output with the plugin output helper which will already be captured to .pout files by the test harness. Signed-off-by: Alex Bennée --- tests/plugin/inline.c | 58 --- 1 file changed, 33 insertions(+), 25 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 01/15] testing: bump to latest libvirt-ci
On 18/7/24 11:45, Alex Bennée wrote: This brings in the latest python mappings for the BSD updates. Signed-off-by: Alex Bennée --- .gitlab-ci.d/cirrus/freebsd-13.vars | 2 +- tests/lcitool/libvirt-ci| 2 +- tests/vm/generated/freebsd.json | 14 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v4 00/18] Reconstruct loongson ipi driver
On 18/7/24 12:00, gaosong wrote: 在 2024/7/18 下午4:38, Philippe Mathieu-Daudé 写道: Since v3: - Use DEFINE_TYPES() macro (unreviewed patch #1) - Update MAINTAINERS - Added Bibo's tags Song, since Bibo reviewed/tested, if you provide your Acked-by I can queue that to my next hw-misc PR (pending Jiaxun testing). Thanks, Phil. Bibo Mao (16): hw/intc/loongson_ipi: Access memory in little endian hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize() hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c hw/intc/loongarch_ipi: Add loongarch IPI support hw/loongarch/virt: Replace loongson IPI with loongarch IPI hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé (2): hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro hw/intc/loongson_ipi: Remove unused headers MAINTAINERS | 6 +- include/hw/intc/loongarch_ipi.h | 25 ++ include/hw/intc/loongson_ipi.h | 50 +--- include/hw/intc/loongson_ipi_common.h | 72 ++ include/hw/loongarch/virt.h | 1 - hw/intc/loongarch_ipi.c | 68 + hw/intc/loongson_ipi.c | 355 +++--- hw/intc/loongson_ipi_common.c | 344 + hw/loongarch/virt.c | 4 +- hw/intc/Kconfig | 8 + hw/intc/meson.build | 2 + hw/loongarch/Kconfig | 2 +- 12 files changed, 568 insertions(+), 369 deletions(-) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongson_ipi_common.c A build error occurred with patch 15. Oops, introduced when adding patch 1 :/ Will fix. sed -i g/Loongarch/LoongArch/g *.c and *.h OK. For this series: Acked-by: Song Gao Thanks!
[PATCH v4 15/18] hw/intc/loongarch_ipi: Add loongarch IPI support
From: Bibo Mao
Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.
Signed-off-by: Bibo Mao
[PMD: Rebased and simplified]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongarch_ipi.h | 25
hw/intc/loongarch_ipi.c | 68 +
hw/intc/Kconfig | 4 ++
hw/intc/meson.build | 1 +
4 files changed, 98 insertions(+)
create mode 100644 include/hw/intc/loongarch_ipi.h
create mode 100644 hw/intc/loongarch_ipi.c
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 00..d134c9d0c7
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt header files
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI)
+
+struct LoongarchIPIState {
+LoongsonIPICommonState parent_obj;
+};
+
+struct LoongarchIPIClass {
+LoongsonIPICommonClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 00..ccbfad07b7
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt support
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "target/loongarch/cpu.h"
+
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
+return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
+
+static int archid_cmp(const void *a, const void *b)
+{
+ CPUArchId *archid_a = (CPUArchId *)a;
+ CPUArchId *archid_b = (CPUArchId *)b;
+
+ return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+CPUArchId apic_id, *found_cpu;
+
+apic_id.arch_id = id;
+found_cpu = bsearch(_id, ms->possible_cpus->cpus,
+ms->possible_cpus->len,
+sizeof(*ms->possible_cpus->cpus),
+archid_cmp);
+
+return found_cpu;
+}
+
+static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+{
+MachineState *machine = MACHINE(qdev_get_machine());
+CPUArchId *archid;
+
+archid = find_cpu_by_archid(machine, arch_id);
+if (archid) {
+return CPU(archid->cpu);
+}
+
+return NULL;
+}
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+
+licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
+}
+
+static const TypeInfo loongarch_ipi_types[] = {
+{
+.name = TYPE_LOONGARCH_IPI,
+.parent = TYPE_LOONGSON_IPI_COMMON,
+.class_init = loongson_ipi_class_init,
+}
+};
+
+DEFINE_TYPES(loongarch_ipi_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a2a0fdca85..dd405bdb5d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -94,6 +94,10 @@ config LOONGSON_IPI
bool
select LOONGSON_IPI_COMMON
+config LOONGARCH_IPI
+bool
+select LOONGSON_IPI_COMMON
+
config LOONGARCH_PCH_PIC
bool
select UNIMP
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a09a527207..f4d81eb8e4 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true:
files('loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true:
files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true:
files('loongarch_extioi.c'))
--
2.41.0
[PATCH v4 14/18] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c
From: Bibo Mao
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c| 269 +
hw/intc/loongson_ipi_common.c | 272 ++
2 files changed, 274 insertions(+), 267 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a2db8bb2e2..86badb2972 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,56 +24,6 @@
#endif
#include "trace.h"
-MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-uint64_t ret = 0;
-int index = 0;
-
-addr &= 0xff;
-switch (addr) {
-case CORE_STATUS_OFF:
-ret = s->status;
-break;
-case CORE_EN_OFF:
-ret = s->en;
-break;
-case CORE_SET_OFF:
-ret = 0;
-break;
-case CORE_CLEAR_OFF:
-ret = 0;
-break;
-case CORE_BUF_20 ... CORE_BUF_38 + 4:
-index = (addr - CORE_BUF_20) >> 2;
-ret = s->buf[index];
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
-break;
-}
-
-trace_loongson_ipi_read(size, (uint64_t)addr, ret);
-*data = ret;
-return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
-uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-LoongsonIPICommonState *ipi = opaque;
-IPICore *s;
-
-if (attrs.requester_id >= ipi->num_cpu) {
-return MEMTX_DECODE_ERROR;
-}
-
-s = >cpu[attrs.requester_id];
-return loongson_ipi_core_readl(s, addr, data, size, attrs);
-}
-
#ifdef TARGET_LOONGARCH64
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
@@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
}
#endif
-static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
- uint64_t val, hwaddr addr, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
-
-if (!iocsr_as) {
-return MEMTX_DECODE_ERROR;
-}
-
-/*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
-if ((val >> 27) & 0xf) {
-data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
-for (i = 0; i < 4; i++) {
-/* get mask for byte writing */
-if (val & (0x1 << (27 + i))) {
-mask |= 0xff << (i * 8);
-}
-}
-}
-
-data &= mask;
-data |= (val >> 32) & ~mask;
-address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
-
-return MEMTX_OK;
-}
-
-static MemTxResult mail_send(LoongsonIPICommonState *ipi,
- uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-static MemTxResult any_send(LoongsonIPICommonState *ipi,
-uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = val & 0x;
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-LoongsonIPICommonState *ipi = s->ipi;
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int index = 0;
-uint32_t cpuid;
-uint8_t vector;
-CPUState *cs;
-
-addr &= 0xff;
-trace_loongson_ipi_write(size, (uint64_t)addr, val);
-switch (addr) {
-case CORE_STATUS_
[PATCH v4 17/18] hw/intc/loongson_ipi: Restrict to MIPS
From: Bibo Mao
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
MAINTAINERS| 2 --
hw/intc/loongson_ipi.c | 14 --
2 files changed, 16 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a670c8ee67..c2d51b0158 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1250,10 +1250,8 @@ F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
F: include/hw/intc/loongson_ipi_common.h
-F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
F: hw/intc/loongson_ipi_common.c
-F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
F: gdb-xml/loongarch*.xml
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 86badb2972..051e910586 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -16,22 +16,9 @@
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "migration/vmstate.h"
-#ifdef TARGET_LOONGARCH64
-#include "target/loongarch/cpu.h"
-#endif
-#ifdef TARGET_MIPS
#include "target/mips/cpu.h"
-#endif
#include "trace.h"
-#ifdef TARGET_LOONGARCH64
-static AddressSpace *get_iocsr_as(CPUState *cpu)
-{
-return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
-}
-#endif
-
-#ifdef TARGET_MIPS
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
if (ase_lcsr_available(_CPU(cpu)->env)) {
@@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
return NULL;
}
-#endif
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
--
2.41.0
[PATCH v4 16/18] hw/loongarch/virt: Replace loongson IPI with loongarch IPI
From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig| 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ -ipi = qdev_new(TYPE_LOONGSON_IPI); +ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), _fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS -select LOONGSON_IPI +select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI -- 2.41.0
[PATCH v4 10/18] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data()
From: Bibo Mao
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index f3d1f031bc..a54db87638 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
return NULL;
}
-static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
@@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
return MEMTX_OK;
}
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult mail_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs
attrs)
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult any_send(LoongsonIPICommonState *ipi,
+uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = val & 0x;
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
@@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = {
static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
+LoongsonIPICommonState *ipi = opaque;
MemTxResult ret = MEMTX_OK;
addr &= 0xfff;
switch (addr) {
case MAIL_SEND_OFFSET:
-ret = mail_send(val, attrs);
+ret = mail_send(ipi, val, attrs);
break;
case ANY_SEND_OFFSET:
-ret = any_send(val, attrs);
+ret = any_send(ipi, val, attrs);
break;
default:
break;
--
2.41.0
[PATCH v4 18/18] hw/intc/loongson_ipi: Remove unused headers
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 051e910586..aa1b0a474c 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -6,18 +6,9 @@
*/
#include "qemu/osdep.h"
-#include "hw/boards.h"
-#include "hw/sysbus.h"
#include "hw/intc/loongson_ipi.h"
-#include "hw/irq.h"
-#include "hw/qdev-properties.h"
#include "qapi/error.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "exec/memory.h"
-#include "migration/vmstate.h"
#include "target/mips/cpu.h"
-#include "trace.h"
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
--
2.41.0
[PATCH v4 13/18] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers
From: Bibo Mao
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi_common.h | 6 ++
hw/intc/loongson_ipi.c| 10 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 5447e9f650..a75882f775 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -10,6 +10,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#include "exec/memattrs.h"
#define IPI_MBX_NUM 4
@@ -44,6 +45,11 @@ struct LoongsonIPICommonClass {
CPUState *(*cpu_by_arch_id)(int64_t id);
};
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs);
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs);
+
/* Mainy used by iocsr read and write */
#define SMP_IPI_MAILBOX 0x1000ULL
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 39bcf0031d..a2db8bb2e2 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,9 +24,8 @@
#endif
#include "trace.h"
-static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
uint64_t ret = 0;
@@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
-uint64_t val, unsigned size,
-MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
--
2.41.0
[PATCH v4 07/18] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h
From: Bibo Mao
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi.h| 18 --
include/hw/intc/loongson_ipi_common.h | 19 +++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 82cb64ca40..d53bd5dcfe 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,24 +12,6 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-/* Mainy used by iocsr read and write */
-#define SMP_IPI_MAILBOX 0x1000ULL
-#define CORE_STATUS_OFF 0x0
-#define CORE_EN_OFF 0x4
-#define CORE_SET_OFF 0x8
-#define CORE_CLEAR_OFF0xc
-#define CORE_BUF_20 0x20
-#define CORE_BUF_28 0x28
-#define CORE_BUF_30 0x30
-#define CORE_BUF_38 0x38
-#define IOCSR_IPI_SEND0x40
-#define IOCSR_MAIL_SEND 0x48
-#define IOCSR_ANY_SEND0x158
-
-#define MAIL_SEND_ADDR(SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
-#define MAIL_SEND_OFFSET 0
-#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
-
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 70ac69d0ba..b43b77bda6 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -23,4 +23,23 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
};
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+#define IOCSR_MAIL_SEND 0x48
+#define IOCSR_ANY_SEND 0x158
+
+#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET0
+#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+
#endif
--
2.41.0
[PATCH v4 11/18] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi_common.h | 2 ++
hw/intc/loongson_ipi.c| 16
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 891b43644d..e49c156db3 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -39,6 +39,8 @@ struct LoongsonIPICommonState {
struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
+
+AddressSpace *(*get_iocsr_as)(CPUState *cpu);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a54db87638..2c8829c3cc 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
return loongson_ipi_core_readl(s, addr, data, size, attrs);
}
-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
-{
#ifdef TARGET_LOONGARCH64
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
#endif
+
#ifdef TARGET_MIPS
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
if (ase_lcsr_available(_CPU(cpu)->env)) {
return _CPU(cpu)->env.iocsr.as;
}
-#endif
+
return NULL;
}
+#endif
static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
+AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
if (!iocsr_as) {
return MEMTX_DECODE_ERROR;
@@ -338,9 +344,11 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
+licc->get_iocsr_as = get_iocsr_as;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v4 12/18] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own cpu_by_arch_id()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi_common.h | 1 +
hw/intc/loongson_ipi.c| 10 +++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index e49c156db3..5447e9f650 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -41,6 +41,7 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
+CPUState *(*cpu_by_arch_id)(int64_t id);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 2c8829c3cc..39bcf0031d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState
*ipi, CPUState *cpu,
static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
@@ -349,6 +352,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = cpu_by_arch_id;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v4 08/18] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState
From: Bibo Mao
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi.h | 2 +-
hw/intc/loongson_ipi.c | 9 ++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index d53bd5dcfe..00a65a82fb 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass,
LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
-MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
uint32_t set;
@@ -38,6 +37,7 @@ struct LoongsonIPIClass {
struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
+MemoryRegion *ipi_mmio_mem;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 20f3f6bd3f..2319aea18f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
+s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
for (unsigned i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
-memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
+memory_region_init_io(>ipi_mmio_mem[i], OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
-sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
+sysbus_init_mmio(sbd, >ipi_mmio_mem[i]);
}
}
@@ -379,6 +379,9 @@ static void loongson_ipi_common_finalize(Object *obj)
static void loongson_ipi_finalize(Object *obj)
{
+LoongsonIPIState *s = LOONGSON_IPI(obj);
+
+g_free(s->ipi_mmio_mem);
loongson_ipi_common_finalize(obj);
}
--
2.41.0
[PATCH v4 09/18] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h
From: Bibo Mao
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi.h| 17
include/hw/intc/loongson_ipi_common.h | 18 +
hw/intc/loongson_ipi.c| 56 +--
hw/intc/loongson_ipi_common.c | 50
4 files changed, 77 insertions(+), 64 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 00a65a82fb..bb5581 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,22 +12,9 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-#define IPI_MBX_NUM 4
-
#define TYPE_LOONGSON_IPI "loongson_ipi"
OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
-typedef struct IPICore {
-LoongsonIPIState *ipi;
-uint32_t status;
-uint32_t en;
-uint32_t set;
-uint32_t clear;
-/* 64bit buf divide into 2 32bit buf */
-uint32_t buf[IPI_MBX_NUM * 2];
-qemu_irq irq;
-} IPICore;
-
struct LoongsonIPIClass {
LoongsonIPICommonClass parent_class;
@@ -38,10 +25,6 @@ struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
MemoryRegion *ipi_mmio_mem;
-MemoryRegion ipi_iocsr_mem;
-MemoryRegion ipi64_iocsr_mem;
-uint32_t num_cpu;
-IPICore *cpu;
};
#endif
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index b43b77bda6..891b43644d 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -11,12 +11,30 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#define IPI_MBX_NUM 4
+
#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+typedef struct IPICore {
+LoongsonIPICommonState *ipi;
+uint32_t status;
+uint32_t en;
+uint32_t set;
+uint32_t clear;
+/* 64bit buf divide into 2 32bit buf */
+uint32_t buf[IPI_MBX_NUM * 2];
+qemu_irq irq;
+} IPICore;
+
struct LoongsonIPICommonState {
SysBusDevice parent_obj;
+
+MemoryRegion ipi_iocsr_mem;
+MemoryRegion ipi64_iocsr_mem;
+uint32_t num_cpu;
+IPICore *cpu;
};
struct LoongsonIPICommonClass {
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 2319aea18f..f3d1f031bc 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPIState *ipi = s->ipi;
+LoongsonIPICommonState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPIState *s = LOONGSON_IPI(dev);
+LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev,
Error **errp)
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
+LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev);
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *local_err = NULL;
@@ -320,45 +321,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
-s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
-for (unsigned i = 0; i < s->num_cpu; i++) {
+s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
+for (unsigned i = 0; i < sc->num_cpu; i++) {
g_autofree char *nam
[PATCH v4 00/18] Reconstruct loongson ipi driver
Since v3: - Use DEFINE_TYPES() macro (unreviewed patch #1) - Update MAINTAINERS - Added Bibo's tags Song, since Bibo reviewed/tested, if you provide your Acked-by I can queue that to my next hw-misc PR (pending Jiaxun testing). Thanks, Phil. Bibo Mao (16): hw/intc/loongson_ipi: Access memory in little endian hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize() hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c hw/intc/loongarch_ipi: Add loongarch IPI support hw/loongarch/virt: Replace loongson IPI with loongarch IPI hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé (2): hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro hw/intc/loongson_ipi: Remove unused headers MAINTAINERS | 6 +- include/hw/intc/loongarch_ipi.h | 25 ++ include/hw/intc/loongson_ipi.h| 50 +--- include/hw/intc/loongson_ipi_common.h | 72 ++ include/hw/loongarch/virt.h | 1 - hw/intc/loongarch_ipi.c | 68 + hw/intc/loongson_ipi.c| 355 +++--- hw/intc/loongson_ipi_common.c | 344 + hw/loongarch/virt.c | 4 +- hw/intc/Kconfig | 8 + hw/intc/meson.build | 2 + hw/loongarch/Kconfig | 2 +- 12 files changed, 568 insertions(+), 369 deletions(-) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongson_ipi_common.c -- 2.41.0
[PATCH v4 06/18] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub
From: Bibo Mao
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
MAINTAINERS | 4
include/hw/intc/loongson_ipi.h| 13 +++--
include/hw/intc/loongson_ipi_common.h | 26 ++
hw/intc/loongson_ipi.c| 7 ---
hw/intc/loongson_ipi_common.c | 22 ++
hw/intc/Kconfig | 4
hw/intc/meson.build | 1 +
7 files changed, 72 insertions(+), 5 deletions(-)
create mode 100644 include/hw/intc/loongson_ipi_common.h
create mode 100644 hw/intc/loongson_ipi_common.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d9811458c..a670c8ee67 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1249,8 +1249,10 @@ F: configs/devices/loongarch64-softmmu/default.mak
F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
@@ -1385,11 +1387,13 @@ Loongson-3 virtual platforms
M: Huacai Chen
R: Jiaxun Yang
S: Maintained
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: hw/intc/loongson_liointc.c
F: hw/mips/loongson3_bootp.c
F: hw/mips/loongson3_bootp.h
F: hw/mips/loongson3_virt.c
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: include/hw/intc/loongson_liointc.h
F: tests/avocado/machine_mips_loongson3v.py
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index efb772f384..82cb64ca40 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -8,6 +8,8 @@
#ifndef HW_LOONGSON_IPI_H
#define HW_LOONGSON_IPI_H
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
/* Mainy used by iocsr read and write */
@@ -31,7 +33,7 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
+OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
@@ -45,8 +47,15 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
+struct LoongsonIPIClass {
+LoongsonIPICommonClass parent_class;
+
+DeviceRealize parent_realize;
+};
+
struct LoongsonIPIState {
-SysBusDevice parent_obj;
+LoongsonIPICommonState parent_obj;
+
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
new file mode 100644
index 00..70ac69d0ba
--- /dev/null
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGSON_IPI_COMMON_H
+#define HW_LOONGSON_IPI_COMMON_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
+OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
+LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+
+struct LoongsonIPICommonState {
+SysBusDevice parent_obj;
+};
+
+struct LoongsonIPICommonClass {
+SysBusDeviceClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index bab4d8816b..20f3f6bd3f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -362,8 +362,10 @@ static Property ipi_properties[] = {
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
-dc->realize = loongson_ipi_realize;
+device_class_set_parent_realize(dc, loongson_ipi_realize,
+>parent_realize);
device_class_set_props(dc, ipi_properties);
dc->vmsd = _loongson_ipi;
}
@@ -383,8 +385,7 @@ static void loongson_ipi_finalize(Object *obj)
static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
-.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPIState),
+.parent = TYPE_LOONGSON_IPI_COMMON,
.class_init = loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
}
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
new file mode 100644
index 00..87d992aa95
--- /dev/null
+++ b/hw/intc/loong
[PATCH v4 02/18] hw/intc/loongson_ipi: Access memory in little endian
From: Bibo Mao
Loongson IPI is only available in little-endian,
so use that to access the guest memory (in case
we run on a big-endian host).
Signed-off-by: Bibo Mao
Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support")
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index dc82caea0d..d315f6f303 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
+#include "exec/memory.h"
#include "migration/vmstate.h"
#ifdef TARGET_LOONGARCH64
#include "target/loongarch/cpu.h"
@@ -102,7 +103,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
-data = address_space_ldl(iocsr_as, addr, attrs, NULL);
+data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
@@ -113,7 +114,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
data &= mask;
data |= (val >> 32) & ~mask;
-address_space_stl(iocsr_as, addr, data, attrs, NULL);
+address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
return MEMTX_OK;
}
--
2.41.0
[PATCH v4 03/18] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi.h | 6 +++---
hw/intc/loongson_ipi.c | 16
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 3f795edbf3..efb772f384 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -31,10 +31,10 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
+OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
typedef struct IPICore {
-LoongsonIPI *ipi;
+LoongsonIPIState *ipi;
MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
@@ -45,7 +45,7 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
-struct LoongsonIPI {
+struct LoongsonIPIState {
SysBusDevice parent_obj;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index d315f6f303..d870af39c1 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPI *ipi = s->ipi;
+LoongsonIPIState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPI *s = LOONGSON_IPI(dev);
+LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -337,14 +337,14 @@ static const VMStateDescription vmstate_loongson_ipi = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
-VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
+VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
vmstate_ipi_core, IPICore),
VMSTATE_END_OF_LIST()
}
};
static Property ipi_properties[] = {
-DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
+DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -359,7 +359,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
static void loongson_ipi_finalize(Object *obj)
{
-LoongsonIPI *s = LOONGSON_IPI(obj);
+LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
@@ -368,7 +368,7 @@ static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPI),
+.instance_size = sizeof(LoongsonIPIState),
.class_init = loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
}
--
2.41.0
[PATCH v4 05/18] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 960d1e604f..bab4d8816b 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
sysbus_init_mmio(sbd, >ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
-if (s->cpu == NULL) {
-error_setg(errp, "Memory allocation for IPICore faile");
+for (i = 0; i < s->num_cpu; i++) {
+s->cpu[i].ipi = s;
+
+qdev_init_gpio_out(dev, >cpu[i].irq, 1);
+}
+}
+
+static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+{
+LoongsonIPIState *s = LOONGSON_IPI(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+Error *local_err = NULL;
+
+loongson_ipi_common_realize(dev, _err);
+if (local_err) {
+error_propagate(errp, local_err);
return;
}
-for (i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi = s;
+for (unsigned i = 0; i < s->num_cpu; i++) {
s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
-
-qdev_init_gpio_out(dev, >cpu[i].irq, 1);
}
}
--
2.41.0
[PATCH v4 04/18] hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_finalize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index d870af39c1..960d1e604f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -357,13 +357,18 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
dc->vmsd = _loongson_ipi;
}
-static void loongson_ipi_finalize(Object *obj)
+static void loongson_ipi_common_finalize(Object *obj)
{
LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
+static void loongson_ipi_finalize(Object *obj)
+{
+loongson_ipi_common_finalize(obj);
+}
+
static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
--
2.41.0
[PATCH v4 01/18] hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e6a7142480..dc82caea0d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -363,17 +363,14 @@ static void loongson_ipi_finalize(Object *obj)
g_free(s->cpu);
}
-static const TypeInfo loongson_ipi_info = {
-.name = TYPE_LOONGSON_IPI,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPI),
-.class_init= loongson_ipi_class_init,
-.instance_finalize = loongson_ipi_finalize,
+static const TypeInfo loongson_ipi_types[] = {
+{
+.name = TYPE_LOONGSON_IPI,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(LoongsonIPI),
+.class_init = loongson_ipi_class_init,
+.instance_finalize = loongson_ipi_finalize,
+}
};
-static void loongson_ipi_register_types(void)
-{
-type_register_static(_ipi_info);
-}
-
-type_init(loongson_ipi_register_types)
+DEFINE_TYPES(loongson_ipi_types)
--
2.41.0
Re: [PATCH 0/4] ui: fixes for dbus clipboard hanling
On 17/7/24 19:15, marcandre.lur...@redhat.com wrote: Marc-André Lureau (4): ui: add more tracing for dbus ui/vdagent: improve vdagent_fe_open() trace ui/vdagent: notify clipboard peers of serial reset ui/vdagent: send caps on fe_open Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v3 04/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()
On 18/7/24 04:11, maobibo wrote:
On 2024/7/18 上午5:46, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 3b3481c43e..40ac769aad 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState
*dev, Error **errp)
sysbus_init_mmio(sbd, >ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
- if (s->cpu == NULL) {
- error_setg(errp, "Memory allocation for IPICore faile");
Philippe,
Thanks for the whole series, it looks to me. It is split into small
patches and adds new option CONFIG_LOONGSON_IPI_COMMON, it is easier to
review and compile for multiple targets.
One small nit, do we need keep checking sentence for if (s->cpu == NULL)?
No because g_new0() can not fail. Checking return value only
makes sense for g_try_new0() which returns.
Overall, for the whole series it is ok for me and works well on
LoongArch machine.
Thanks!
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
Jiaxun, do you mind re-testing the series for your MIPS machine?
Regards,
Phil.
[PATCH v3 13/17] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c
From: Bibo Mao
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c| 269 +
hw/intc/loongson_ipi_common.c | 272 ++
2 files changed, 274 insertions(+), 267 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 227fd667d9..464bb6b580 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,56 +24,6 @@
#endif
#include "trace.h"
-MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-uint64_t ret = 0;
-int index = 0;
-
-addr &= 0xff;
-switch (addr) {
-case CORE_STATUS_OFF:
-ret = s->status;
-break;
-case CORE_EN_OFF:
-ret = s->en;
-break;
-case CORE_SET_OFF:
-ret = 0;
-break;
-case CORE_CLEAR_OFF:
-ret = 0;
-break;
-case CORE_BUF_20 ... CORE_BUF_38 + 4:
-index = (addr - CORE_BUF_20) >> 2;
-ret = s->buf[index];
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
-break;
-}
-
-trace_loongson_ipi_read(size, (uint64_t)addr, ret);
-*data = ret;
-return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
-uint64_t *data,
-unsigned size, MemTxAttrs attrs)
-{
-LoongsonIPICommonState *ipi = opaque;
-IPICore *s;
-
-if (attrs.requester_id >= ipi->num_cpu) {
-return MEMTX_DECODE_ERROR;
-}
-
-s = >cpu[attrs.requester_id];
-return loongson_ipi_core_readl(s, addr, data, size, attrs);
-}
-
#ifdef TARGET_LOONGARCH64
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
@@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
}
#endif
-static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
- uint64_t val, hwaddr addr, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
-
-if (!iocsr_as) {
-return MEMTX_DECODE_ERROR;
-}
-
-/*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
-if ((val >> 27) & 0xf) {
-data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
-for (i = 0; i < 4; i++) {
-/* get mask for byte writing */
-if (val & (0x1 << (27 + i))) {
-mask |= 0xff << (i * 8);
-}
-}
-}
-
-data &= mask;
-data |= (val >> 32) & ~mask;
-address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
-
-return MEMTX_OK;
-}
-
-static MemTxResult mail_send(LoongsonIPICommonState *ipi,
- uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-static MemTxResult any_send(LoongsonIPICommonState *ipi,
-uint64_t val, MemTxAttrs attrs)
-{
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = licc->cpu_by_arch_id(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = val & 0x;
-attrs.requester_id = cs->cpu_index;
-return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
-IPICore *s = opaque;
-LoongsonIPICommonState *ipi = s->ipi;
-LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
-int index = 0;
-uint32_t cpuid;
-uint8_t vector;
-CPUState *cs;
-
-addr &= 0xff;
-trace_loongson_ipi_write(size, (uint64_t)addr, val);
-switch (addr) {
-case CORE_STATUS_OFF:
-qemu_log_mask(LOG_GUEST_ERROR, "can not be written&quo
[PATCH v3 16/17] hw/intc/loongson_ipi: Restrict to MIPS
From: Bibo Mao
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 464bb6b580..61375d89ff 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -16,22 +16,9 @@
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "migration/vmstate.h"
-#ifdef TARGET_LOONGARCH64
-#include "target/loongarch/cpu.h"
-#endif
-#ifdef TARGET_MIPS
#include "target/mips/cpu.h"
-#endif
#include "trace.h"
-#ifdef TARGET_LOONGARCH64
-static AddressSpace *get_iocsr_as(CPUState *cpu)
-{
-return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
-}
-#endif
-
-#ifdef TARGET_MIPS
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
if (ase_lcsr_available(_CPU(cpu)->env)) {
@@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
return NULL;
}
-#endif
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
--
2.41.0
[PATCH v3 17/17] hw/intc/loongson_ipi: Remove unused headers
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 61375d89ff..6dd08aa9cb 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -6,18 +6,9 @@
*/
#include "qemu/osdep.h"
-#include "hw/boards.h"
-#include "hw/sysbus.h"
#include "hw/intc/loongson_ipi.h"
-#include "hw/irq.h"
-#include "hw/qdev-properties.h"
#include "qapi/error.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "exec/memory.h"
-#include "migration/vmstate.h"
#include "target/mips/cpu.h"
-#include "trace.h"
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
--
2.41.0
[PATCH v3 04/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 3b3481c43e..40ac769aad 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
sysbus_init_mmio(sbd, >ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
-if (s->cpu == NULL) {
-error_setg(errp, "Memory allocation for IPICore faile");
+for (i = 0; i < s->num_cpu; i++) {
+s->cpu[i].ipi = s;
+
+qdev_init_gpio_out(dev, >cpu[i].irq, 1);
+}
+}
+
+static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+{
+LoongsonIPIState *s = LOONGSON_IPI(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+Error *local_err = NULL;
+
+loongson_ipi_common_realize(dev, _err);
+if (local_err) {
+error_propagate(errp, local_err);
return;
}
-for (i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi = s;
+for (unsigned i = 0; i < s->num_cpu; i++) {
s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
-
-qdev_init_gpio_out(dev, >cpu[i].irq, 1);
}
}
--
2.41.0
[PATCH v3 12/17] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers
From: Bibo Mao
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi_common.h | 6 ++
hw/intc/loongson_ipi.c| 10 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 5447e9f650..a75882f775 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -10,6 +10,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#include "exec/memattrs.h"
#define IPI_MBX_NUM 4
@@ -44,6 +45,11 @@ struct LoongsonIPICommonClass {
CPUState *(*cpu_by_arch_id)(int64_t id);
};
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs);
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs);
+
/* Mainy used by iocsr read and write */
#define SMP_IPI_MAILBOX 0x1000ULL
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 603a88356d..227fd667d9 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,9 +24,8 @@
#endif
#include "trace.h"
-static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
uint64_t ret = 0;
@@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
-uint64_t val, unsigned size,
-MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
--
2.41.0
[PATCH v3 11/17] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own cpu_by_arch_id()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi_common.h | 1 +
hw/intc/loongson_ipi.c| 10 +++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index e49c156db3..5447e9f650 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -41,6 +41,7 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
+CPUState *(*cpu_by_arch_id)(int64_t id);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 4a7a1fa38d..603a88356d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState
*ipi, CPUState *cpu,
static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
-cs = cpu_by_arch_id(cpuid);
+cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
@@ -349,6 +352,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = cpu_by_arch_id;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v3 01/17] hw/intc/loongson_ipi: Access memory in little endian
From: Bibo Mao
Loongson IPI is only available in little-endian,
so use that to access the guest memory (in case
we run on a big-endian host).
Signed-off-by: Bibo Mao
Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support")
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e6a7142480..e7979dbdd8 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
+#include "exec/memory.h"
#include "migration/vmstate.h"
#ifdef TARGET_LOONGARCH64
#include "target/loongarch/cpu.h"
@@ -102,7 +103,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
-data = address_space_ldl(iocsr_as, addr, attrs, NULL);
+data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
@@ -113,7 +114,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
data &= mask;
data |= (val >> 32) & ~mask;
-address_space_stl(iocsr_as, addr, data, attrs, NULL);
+address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
return MEMTX_OK;
}
--
2.41.0
[PATCH v3 15/17] hw/loongarch/virt: Replace loongson IPI with loongarch IPI
From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig| 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ -ipi = qdev_new(TYPE_LOONGSON_IPI); +ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), _fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS -select LOONGSON_IPI +select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI -- 2.41.0
[PATCH v3 10/17] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler
From: Bibo Mao
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi_common.h | 2 ++
hw/intc/loongson_ipi.c| 16
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 891b43644d..e49c156db3 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -39,6 +39,8 @@ struct LoongsonIPICommonState {
struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
+
+AddressSpace *(*get_iocsr_as)(CPUState *cpu);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 8acd563db9..4a7a1fa38d 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
return loongson_ipi_core_readl(s, addr, data, size, attrs);
}
-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
-{
#ifdef TARGET_LOONGARCH64
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
#endif
+
#ifdef TARGET_MIPS
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
if (ase_lcsr_available(_CPU(cpu)->env)) {
return _CPU(cpu)->env.iocsr.as;
}
-#endif
+
return NULL;
}
+#endif
static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int i, mask = 0, data = 0;
-AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
+AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
if (!iocsr_as) {
return MEMTX_DECODE_ERROR;
@@ -338,9 +344,11 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
device_class_set_parent_realize(dc, loongson_ipi_realize,
>parent_realize);
+licc->get_iocsr_as = get_iocsr_as;
}
static void loongson_ipi_finalize(Object *obj)
--
2.41.0
[PATCH v3 08/17] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h
From: Bibo Mao
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi.h| 17
include/hw/intc/loongson_ipi_common.h | 18 +
hw/intc/loongson_ipi.c| 56 +--
hw/intc/loongson_ipi_common.c | 50
4 files changed, 77 insertions(+), 64 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 00a65a82fb..bb5581 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,22 +12,9 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-#define IPI_MBX_NUM 4
-
#define TYPE_LOONGSON_IPI "loongson_ipi"
OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
-typedef struct IPICore {
-LoongsonIPIState *ipi;
-uint32_t status;
-uint32_t en;
-uint32_t set;
-uint32_t clear;
-/* 64bit buf divide into 2 32bit buf */
-uint32_t buf[IPI_MBX_NUM * 2];
-qemu_irq irq;
-} IPICore;
-
struct LoongsonIPIClass {
LoongsonIPICommonClass parent_class;
@@ -38,10 +25,6 @@ struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
MemoryRegion *ipi_mmio_mem;
-MemoryRegion ipi_iocsr_mem;
-MemoryRegion ipi64_iocsr_mem;
-uint32_t num_cpu;
-IPICore *cpu;
};
#endif
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index b43b77bda6..891b43644d 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -11,12 +11,30 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#define IPI_MBX_NUM 4
+
#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+typedef struct IPICore {
+LoongsonIPICommonState *ipi;
+uint32_t status;
+uint32_t en;
+uint32_t set;
+uint32_t clear;
+/* 64bit buf divide into 2 32bit buf */
+uint32_t buf[IPI_MBX_NUM * 2];
+qemu_irq irq;
+} IPICore;
+
struct LoongsonIPICommonState {
SysBusDevice parent_obj;
+
+MemoryRegion ipi_iocsr_mem;
+MemoryRegion ipi64_iocsr_mem;
+uint32_t num_cpu;
+IPICore *cpu;
};
struct LoongsonIPICommonClass {
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a9fca28430..5346bbb267 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPIState *ipi = s->ipi;
+LoongsonIPICommonState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPIState *ipi = opaque;
+LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPIState *s = LOONGSON_IPI(dev);
+LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev,
Error **errp)
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
+LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev);
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *local_err = NULL;
@@ -320,45 +321,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
-s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
-for (unsigned i = 0; i < s->num_cpu; i++) {
+s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
+for (unsigned i = 0; i < sc->num_cpu; i++) {
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
+
[PATCH v3 14/17] hw/intc/loongarch_ipi: Add loongarch IPI support
From: Bibo Mao
Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.
Signed-off-by: Bibo Mao
[PMD: Rebased and simplified]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongarch_ipi.h | 25
hw/intc/loongarch_ipi.c | 71 +
hw/intc/Kconfig | 4 ++
hw/intc/meson.build | 1 +
4 files changed, 101 insertions(+)
create mode 100644 include/hw/intc/loongarch_ipi.h
create mode 100644 hw/intc/loongarch_ipi.c
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 00..d134c9d0c7
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt header files
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI)
+
+struct LoongarchIPIState {
+LoongsonIPICommonState parent_obj;
+};
+
+struct LoongarchIPIClass {
+LoongsonIPICommonClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 00..277de7c4e4
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongarch ipi interrupt support
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "target/loongarch/cpu.h"
+
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
+return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
+
+static int archid_cmp(const void *a, const void *b)
+{
+ CPUArchId *archid_a = (CPUArchId *)a;
+ CPUArchId *archid_b = (CPUArchId *)b;
+
+ return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+CPUArchId apic_id, *found_cpu;
+
+apic_id.arch_id = id;
+found_cpu = bsearch(_id, ms->possible_cpus->cpus,
+ms->possible_cpus->len,
+sizeof(*ms->possible_cpus->cpus),
+archid_cmp);
+
+return found_cpu;
+}
+
+static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+{
+MachineState *machine = MACHINE(qdev_get_machine());
+CPUArchId *archid;
+
+archid = find_cpu_by_archid(machine, arch_id);
+if (archid) {
+return CPU(archid->cpu);
+}
+
+return NULL;
+}
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+
+licc->get_iocsr_as = get_iocsr_as;
+licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
+}
+
+static const TypeInfo loongarch_ipi_info = {
+.name = TYPE_LOONGARCH_IPI,
+.parent= TYPE_LOONGSON_IPI_COMMON,
+.class_init= loongarch_ipi_class_init,
+};
+
+static void loongarch_ipi_register_types(void)
+{
+type_register_static(_ipi_info);
+}
+
+type_init(loongarch_ipi_register_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a2a0fdca85..dd405bdb5d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -94,6 +94,10 @@ config LOONGSON_IPI
bool
select LOONGSON_IPI_COMMON
+config LOONGARCH_IPI
+bool
+select LOONGSON_IPI_COMMON
+
config LOONGARCH_PCH_PIC
bool
select UNIMP
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a09a527207..f4d81eb8e4 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true:
files('loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true:
files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true:
files('loongarch_extioi.c'))
--
2.41.0
[PATCH v3 09/17] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data()
From: Bibo Mao
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 5346bbb267..8acd563db9 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
return NULL;
}
-static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
@@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
return MEMTX_OK;
}
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult mail_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs
attrs)
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult any_send(LoongsonIPICommonState *ipi,
+uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = val & 0x;
attrs.requester_id = cs->cpu_index;
-return send_ipi_data(cs, val, addr, attrs);
+return send_ipi_data(ipi, cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
@@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = {
static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
+LoongsonIPICommonState *ipi = opaque;
MemTxResult ret = MEMTX_OK;
addr &= 0xfff;
switch (addr) {
case MAIL_SEND_OFFSET:
-ret = mail_send(val, attrs);
+ret = mail_send(ipi, val, attrs);
break;
case ANY_SEND_OFFSET:
-ret = any_send(val, attrs);
+ret = any_send(ipi, val, attrs);
break;
default:
break;
--
2.41.0
[PATCH v3 07/17] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState
From: Bibo Mao
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi.h | 2 +-
hw/intc/loongson_ipi.c | 9 ++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index d53bd5dcfe..00a65a82fb 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass,
LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
-MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
uint32_t set;
@@ -38,6 +37,7 @@ struct LoongsonIPIClass {
struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
+MemoryRegion *ipi_mmio_mem;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e8772f1b96..a9fca28430 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error
**errp)
return;
}
+s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
for (unsigned i = 0; i < s->num_cpu; i++) {
-s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
-memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
+memory_region_init_io(>ipi_mmio_mem[i], OBJECT(dev),
_ipi_core_ops, >cpu[i], name, 0x48);
-sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
+sysbus_init_mmio(sbd, >ipi_mmio_mem[i]);
}
}
@@ -379,6 +379,9 @@ static void loongson_ipi_common_finalize(Object *obj)
static void loongson_ipi_finalize(Object *obj)
{
+LoongsonIPIState *s = LOONGSON_IPI(obj);
+
+g_free(s->ipi_mmio_mem);
loongson_ipi_common_finalize(obj);
}
--
2.41.0
[PATCH v3 05/17] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub
From: Bibo Mao
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi.h| 13 +++--
include/hw/intc/loongson_ipi_common.h | 26 ++
hw/intc/loongson_ipi.c| 7 ---
hw/intc/loongson_ipi_common.c | 25 +
hw/intc/Kconfig | 4
hw/intc/meson.build | 1 +
6 files changed, 71 insertions(+), 5 deletions(-)
create mode 100644 include/hw/intc/loongson_ipi_common.h
create mode 100644 hw/intc/loongson_ipi_common.c
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index efb772f384..82cb64ca40 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -8,6 +8,8 @@
#ifndef HW_LOONGSON_IPI_H
#define HW_LOONGSON_IPI_H
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
/* Mainy used by iocsr read and write */
@@ -31,7 +33,7 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
+OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
@@ -45,8 +47,15 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
+struct LoongsonIPIClass {
+LoongsonIPICommonClass parent_class;
+
+DeviceRealize parent_realize;
+};
+
struct LoongsonIPIState {
-SysBusDevice parent_obj;
+LoongsonIPICommonState parent_obj;
+
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
new file mode 100644
index 00..70ac69d0ba
--- /dev/null
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGSON_IPI_COMMON_H
+#define HW_LOONGSON_IPI_COMMON_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
+OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
+LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+
+struct LoongsonIPICommonState {
+SysBusDevice parent_obj;
+};
+
+struct LoongsonIPICommonClass {
+SysBusDeviceClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 40ac769aad..e8772f1b96 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -362,8 +362,10 @@ static Property ipi_properties[] = {
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
-dc->realize = loongson_ipi_realize;
+device_class_set_parent_realize(dc, loongson_ipi_realize,
+>parent_realize);
device_class_set_props(dc, ipi_properties);
dc->vmsd = _loongson_ipi;
}
@@ -382,8 +384,7 @@ static void loongson_ipi_finalize(Object *obj)
static const TypeInfo loongson_ipi_info = {
.name = TYPE_LOONGSON_IPI,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPIState),
+.parent= TYPE_LOONGSON_IPI_COMMON,
.class_init= loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
};
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
new file mode 100644
index 00..7e3f74d08a
--- /dev/null
+++ b/hw/intc/loongson_ipi_common.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt common support
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+static const TypeInfo loongson_ipi_common_info = {
+.name = TYPE_LOONGSON_IPI_COMMON,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(LoongsonIPICommonState),
+.class_size = sizeof(LoongsonIPICommonClass),
+.abstract = true,
+};
+
+static void loongson_ipi_common_register_types(void)
+{
+type_register_static(_ipi_common_info);
+}
+
+type_init(loongson_ipi_common_register_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 58b6d3a710..a2a0fdca85 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -87,8 +87,12 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+config LOONGSON_IPI_COMMON
+bool
+
config LOONGSON_IPI
bool
+select LOONGSON_IPI_COMMON
config LOONGARCH_PCH_PIC
bool
diff --git a/hw/intc/
[PATCH v3 06/17] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h
From: Bibo Mao
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi.h| 18 --
include/hw/intc/loongson_ipi_common.h | 19 +++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 82cb64ca40..d53bd5dcfe 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,24 +12,6 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-/* Mainy used by iocsr read and write */
-#define SMP_IPI_MAILBOX 0x1000ULL
-#define CORE_STATUS_OFF 0x0
-#define CORE_EN_OFF 0x4
-#define CORE_SET_OFF 0x8
-#define CORE_CLEAR_OFF0xc
-#define CORE_BUF_20 0x20
-#define CORE_BUF_28 0x28
-#define CORE_BUF_30 0x30
-#define CORE_BUF_38 0x38
-#define IOCSR_IPI_SEND0x40
-#define IOCSR_MAIL_SEND 0x48
-#define IOCSR_ANY_SEND0x158
-
-#define MAIL_SEND_ADDR(SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
-#define MAIL_SEND_OFFSET 0
-#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
-
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
diff --git a/include/hw/intc/loongson_ipi_common.h
b/include/hw/intc/loongson_ipi_common.h
index 70ac69d0ba..b43b77bda6 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -23,4 +23,23 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
};
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+#define IOCSR_MAIL_SEND 0x48
+#define IOCSR_ANY_SEND 0x158
+
+#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET0
+#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+
#endif
--
2.41.0
[PATCH v3 02/17] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/intc/loongson_ipi.h | 6 +++---
hw/intc/loongson_ipi.c | 16
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 3f795edbf3..efb772f384 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -31,10 +31,10 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
+OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
typedef struct IPICore {
-LoongsonIPI *ipi;
+LoongsonIPIState *ipi;
MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
@@ -45,7 +45,7 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
-struct LoongsonIPI {
+struct LoongsonIPIState {
SysBusDevice parent_obj;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index e7979dbdd8..a34e7e634f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque,
hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
-LoongsonIPI *ipi = s->ipi;
+LoongsonIPIState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque,
hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
-LoongsonIPI *ipi = opaque;
+LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
-LoongsonIPI *s = LOONGSON_IPI(dev);
+LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -337,14 +337,14 @@ static const VMStateDescription vmstate_loongson_ipi = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
-VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
+VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
vmstate_ipi_core, IPICore),
VMSTATE_END_OF_LIST()
}
};
static Property ipi_properties[] = {
-DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
+DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -359,7 +359,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
static void loongson_ipi_finalize(Object *obj)
{
-LoongsonIPI *s = LOONGSON_IPI(obj);
+LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
@@ -367,7 +367,7 @@ static void loongson_ipi_finalize(Object *obj)
static const TypeInfo loongson_ipi_info = {
.name = TYPE_LOONGSON_IPI,
.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(LoongsonIPI),
+.instance_size = sizeof(LoongsonIPIState),
.class_init= loongson_ipi_class_init,
.instance_finalize = loongson_ipi_finalize,
};
--
2.41.0
[PATCH v3 03/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize()
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_finalize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index a34e7e634f..3b3481c43e 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -357,13 +357,18 @@ static void loongson_ipi_class_init(ObjectClass *klass,
void *data)
dc->vmsd = _loongson_ipi;
}
-static void loongson_ipi_finalize(Object *obj)
+static void loongson_ipi_common_finalize(Object *obj)
{
LoongsonIPIState *s = LOONGSON_IPI(obj);
g_free(s->cpu);
}
+static void loongson_ipi_finalize(Object *obj)
+{
+loongson_ipi_common_finalize(obj);
+}
+
static const TypeInfo loongson_ipi_info = {
.name = TYPE_LOONGSON_IPI,
.parent= TYPE_SYS_BUS_DEVICE,
--
2.41.0
[PATCH v3 00/17] Reconstruct loongson ipi driver
Hi, this is a respin of Bibo v2 [*] splitting the patches in atomic/trivial changes as I was taking notes reviewing it. I suppose I shoudn't have done that way and asked Bibo to do it, but I felt responsible for merging Jiaxun series and soft freeze is urging. Patch descriptions are expected to be self-explicit. I'm getting sick so I'll defer to Bibo & Jiaxun to follow up. I only build-tested so far, not run any guest code... Regards, Phil. [*] https://lore.kernel.org/qemu-devel/20240704033802.3838618-1-maob...@loongson.cn/ Bibo Mao (16): hw/intc/loongson_ipi: Access memory in little endian hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize() hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c hw/intc/loongarch_ipi: Add loongarch IPI support hw/loongarch/virt: Replace loongson IPI with loongarch IPI hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé (1): hw/intc/loongson_ipi: Remove unused headers include/hw/intc/loongarch_ipi.h | 25 ++ include/hw/intc/loongson_ipi.h| 50 +--- include/hw/intc/loongson_ipi_common.h | 72 ++ include/hw/loongarch/virt.h | 1 - hw/intc/loongarch_ipi.c | 71 ++ hw/intc/loongson_ipi.c| 338 ++--- hw/intc/loongson_ipi_common.c | 347 ++ hw/loongarch/virt.c | 4 +- hw/intc/Kconfig | 8 + hw/intc/meson.build | 2 + hw/loongarch/Kconfig | 2 +- 11 files changed, 563 insertions(+), 357 deletions(-) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongson_ipi_common.c -- 2.41.0
