Re: [PATCH 1/2] hw/arm: Add support for stm32g000 SoC family
Felipe Balbi writes: > +qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); Hi Felipe. This should be 2, not 4. From RM0454 section 11.1 on page 250: "4 programmable priority levels (2 bits of interrupt priority are used)". Sam -- Samuel Tardieu
Re: [PATCH] docs/style: allow C99 mixed declarations
Daniel P. Berrangé writes: $ gcc -Wall -Wuninitialized -o jump jump.c Note that many GCC warnings don't trigger if you don't enable optimizations. In the case you exhibit, adding -O is enough to get a sensible warning: $ gcc -Wall -O -o jump jump.c jump.c: In function ‘main’: jump.c:11:3: warning: ‘foo’ may be used uninitialized [-Wmaybe-uninitialized] 11 | free(foo); | ^ jump.c:8:9: note: ‘foo’ was declared here 8 | char *foo = malloc(30); | ^~~ Best. Sam -- Samuel Tardieu
Re: [PATCH 1/2] docs: introduce dedicated page about code provenance / sign-off
Daniel P. Berrangé writes: Is there any requirement for the order of tags? My previous understanding was that if the Reviewed-by/Tested-by tags were obtained by the author within his company, then those tags should be placed before the signed-off-by of the author. If the Reviewed-by/ Tested-by were acquired in the community, then they should be placed after the author's signed-off-by, right? Common practice is for Signed-off-by tags to be kept in time order from earliest author to latest author / maintainer. Common case is 2 S-o-B, the first from the patch author, and the last from the sub-system maintainer who sends the pull request. For other tags I don't see any broadly acceptable pattern. Some people add Reviewed-by before the S-o-B, others add Reviewed-by after the S-o-B. Either is fine IMHO. From what I've seen in other projects, S-o-B means that you accept accountability for everything above. One scenario would be: - Send original patch, which has been tested inside the company: Tested-by: Tester Signed-off-by: Developper - Get some R-b, but need to make some requested minor changes and resend a new patch series: Tested-by: Tester Reviewed-by: Reviewer Signed-off-by: Developper This is a way of saying "I guarantee that the R-b still applies after the new changes I made to this series" - Then reviewed and pulled into their tree by the maintainer: Tested-by: Tester Reviewed-by: Reviewer Signed-off-by: Developper Reviewed-by: Maintainer Signed-off-by: Maintainer If, after being reviewed, the initial patch would not have needed any change, the order would have been: Tested-by: Tester Signed-off-by: Developper Reviewed-by: Reviewer Reviewed-by: Maintainer Signed-off-by: Maintainer This is consistent with what software like "b4" do: if the S-o of the current user is present, it is moved last, as the current user is the one accepting accountability at this point. However, this is not what QEMU has been using as far as I can see, as S-o-b tend to stay in their original positions. I even opened an issue on b4 a few weeks ago because of this <https://github.com/mricon/b4/issues/16>, and I reverted to using git-publish. But if this is ok to use an arbitrary order for non-S-o-b headers, I can get back to b4. Sam -- Samuel Tardieu
Re: [PATCH 7/7] Add tests for the STM32L4x5_RCC
Arnaud Minier writes: + * The procedure is taken from a program by Samuel Tardieu. You may drop this line as I used the same procedure which is used in other tests, this does not deserve a mention here. Sam -- Samuel Tardieu
[PATCH] hw/timer: fix systick trace message
Signed-off-by: Samuel Tardieu
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
---
hw/timer/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 3eccef83858..8145e18e3da 100644
--- a/hw/timer/trace-events
+++ b/hw/timer/trace-events
@@ -35,7 +35,7 @@ aspeed_timer_read(uint64_t offset, unsigned size, uint64_t
value) "From 0x%" PRI
# armv7m_systick.c
systick_reload(void) "systick reload"
-systick_timer_tick(void) "systick reload"
+systick_timer_tick(void) "systick tick"
systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr
0x%" PRIx64 " data 0x%" PRIx32 " size %u"
systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write
addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
--
2.42.0
Re: [PATCH v2 0/2] Deprecate the shix machine and the TC58128 flash device
Samuel Tardieu writes: The shix machine was a research project started around 2003 at Télécom Paris. Preliminary support in QEMU was added in 2005 back when the QEMU architecture was less structured than it is now. Unfortunately, the support for the shix machine and its peripherals, such as the TC58128 16MiB flash device, has never been maintained as the research project used the real machine. This project stopped around 2010 and to the best of my knowledge and after consulting with the original author Alexis Polti, I propose to deprecate it in QEMU as well as the TC58128 flash device which does not implement the QOM model and still contains debug fprintf statements. I forgot to include the change from v1: simplify the deprecation statements. Sam -- Samuel Tardieu
[PATCH v2 2/2] hw/block: Deprecate the TC58128 block device
The 16MiB flash device is only used by the deprecated shix machine.
Its code it old and unmaintained, and has never been adapted to the
QOM architecture. It still contains debug statements and uses global
variables. It is time to deprecate it.
Signed-off-by: Samuel Tardieu
Reviewed-by: Cédric Le Goater
---
docs/about/deprecated.rst | 2 +-
hw/block/tc58128.c| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index e6a12c9077..15e39f8bbb 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -273,7 +273,7 @@ The Nios II architecture is orphan.
The machine is no longer in existence and has been long unmaintained
-in QEMU.
+in QEMU. This also holds for the TC51828 16MiB flash that it uses.
Backend options
---
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
index d350126b27..6944cf58fa 100644
--- a/hw/block/tc58128.c
+++ b/hw/block/tc58128.c
@@ -202,6 +202,7 @@ static sh7750_io_device tc58128 = {
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
{
+warn_report_once("The TC58128 flash device is deprecated");
init_dev(_devs[0], zone1);
init_dev(_devs[1], zone2);
return sh7750_register_io_device(s, );
--
2.42.0
[PATCH v2 1/2] target/sh4: Deprecate the shix machine
The shix machine has been designed and used at Télécom Paris from 2003
to 2010. It had been added to QEMU in 2005 and has not been maintained
since. Since nobody is using the physical board anymore nor interested
in maintaining the QEMU port, it is time to deprecate it.
Signed-off-by: Samuel Tardieu
Reviewed-by: Cédric Le Goater
Reviewed-by: Yoshinori Sato
---
docs/about/deprecated.rst | 5 +
hw/sh4/shix.c | 1 +
2 files changed, 6 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 2e15040246..e6a12c9077 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -269,6 +269,11 @@ Nios II ``10m50-ghrd`` and ``nios2-generic-nommu``
machines (since 8.2)
The Nios II architecture is orphan.
+``shix`` (since 9.0)
+
+
+The machine is no longer in existence and has been long unmaintained
+in QEMU.
Backend options
---
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index aa812512f0..eb3150b5bc 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -80,6 +80,7 @@ static void shix_machine_init(MachineClass *mc)
mc->init = shix_init;
mc->is_default = true;
mc->default_cpu_type = TYPE_SH7750R_CPU;
+mc->deprecation_reason = "old and unmaintained";
}
DEFINE_MACHINE("shix", shix_machine_init)
--
2.42.0
[PATCH v2 0/2] Deprecate the shix machine and the TC58128 flash device
The shix machine was a research project started around 2003 at Télécom Paris. Preliminary support in QEMU was added in 2005 back when the QEMU architecture was less structured than it is now. Unfortunately, the support for the shix machine and its peripherals, such as the TC58128 16MiB flash device, has never been maintained as the research project used the real machine. This project stopped around 2010 and to the best of my knowledge and after consulting with the original author Alexis Polti, I propose to deprecate it in QEMU as well as the TC58128 flash device which does not implement the QOM model and still contains debug fprintf statements. Samuel Tardieu (2): target/sh4: Deprecate the shix machine hw/block: Deprecate the TC58128 block device docs/about/deprecated.rst | 5 + hw/block/tc58128.c| 1 + hw/sh4/shix.c | 1 + 3 files changed, 7 insertions(+) -- 2.42.0
Re: [PATCH 1/2] target/sh4: Deprecate the shix machine
Philippe Mathieu-Daudé writes: mc->default_cpu_type = TYPE_SH7750R_CPU; +mc->deprecation_reason = "old and unmaintained - use a newer machine instead"; "use a newer machine instead" bugs me, what would that be? Could we stick to "old and unmaintained"? You're right. I removed the extra part in both the shix and the tc58128 deprecation messages. Sam -- Samuel Tardieu
[PATCH 2/2] hw/block: Deprecate the TC58128 block device
The 16MiB flash device is only used by the deprecated shix machine.
Its code it old and unmaintained, and has never been adapted to the
QOM architecture. It still contains debug statements and uses global
variables. It is time to deprecate it.
Signed-off-by: Samuel Tardieu
---
docs/about/deprecated.rst | 2 +-
hw/block/tc58128.c| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index e6a12c9077..15e39f8bbb 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -273,7 +273,7 @@ The Nios II architecture is orphan.
The machine is no longer in existence and has been long unmaintained
-in QEMU.
+in QEMU. This also holds for the TC51828 16MiB flash that it uses.
Backend options
---
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
index d350126b27..354c13ccf0 100644
--- a/hw/block/tc58128.c
+++ b/hw/block/tc58128.c
@@ -202,6 +202,7 @@ static sh7750_io_device tc58128 = {
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
{
+warn_report_once("The TC58128 flash device is deprecated - use a newer
component");
init_dev(_devs[0], zone1);
init_dev(_devs[1], zone2);
return sh7750_register_io_device(s, );
--
2.42.0
[PATCH 1/2] target/sh4: Deprecate the shix machine
The shix machine has been designed and used at Télécom Paris from 2003
to 2010. It had been added to QEMU in 2005 and has not been maintained
since. Since nobody is using the physical board anymore nor interested
in maintaining the QEMU port, it is time to deprecate it.
Signed-off-by: Samuel Tardieu
---
docs/about/deprecated.rst | 5 +
hw/sh4/shix.c | 1 +
2 files changed, 6 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 2e15040246..e6a12c9077 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -269,6 +269,11 @@ Nios II ``10m50-ghrd`` and ``nios2-generic-nommu``
machines (since 8.2)
The Nios II architecture is orphan.
+``shix`` (since 9.0)
+
+
+The machine is no longer in existence and has been long unmaintained
+in QEMU.
Backend options
---
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index aa812512f0..58530b8ede 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -80,6 +80,7 @@ static void shix_machine_init(MachineClass *mc)
mc->init = shix_init;
mc->is_default = true;
mc->default_cpu_type = TYPE_SH7750R_CPU;
+mc->deprecation_reason = "old and unmaintained - use a newer machine
instead";
}
DEFINE_MACHINE("shix", shix_machine_init)
--
2.42.0
[PATCH 0/2] Deprecate the shix machine and the TC58128 flash device
The shix machine was a research project started around 2003 at Télécom Paris. Preliminary support in QEMU was added in 2005 back when the QEMU architecture was less structured than it is now. Unfortunately, the support for the shix machine and its peripherals, such as the TC58128 16MiB flash device, has never been maintained as the research project used the real machine. This project stopped around 2010 and to the best of my knowledge and after consulting with the original author Alexis Polti, I propose to deprecate it in QEMU as well as the TC58128 flash device which does not implement the QOM model and still contains debug fprintf statements. Samuel Tardieu (2): target/sh4: Deprecate the shix machine hw/block: Deprecate the TC58128 block device docs/about/deprecated.rst | 5 + hw/block/tc58128.c| 1 + hw/sh4/shix.c | 1 + 3 files changed, 7 insertions(+) -- 2.42.0
[PATCH v3 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property
A SoC will not have a direct access to the NVIC embedded in its ARM core. By aliasing the "num-prio-bits" property similarly to what is done for the "num-irq" one, a SoC can easily configure it on its armv7m instance. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell --- hw/arm/armv7m.c | 2 ++ include/hw/arm/armv7m.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index e39b61bc1a..1f21827773 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -256,6 +256,8 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "nvic", >nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(>nvic), "num-irq"); +object_property_add_alias(obj, "num-prio-bits", + OBJECT(>nvic), "num-prio-bits"); object_initialize_child(obj, "systick-reg-ns", >systick[M_REG_NS], TYPE_SYSTICK); diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index e2cebbd15c..5c057ab2ec 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -43,6 +43,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). * + Property "cpu-type": CPU type to instantiate * + Property "num-irq": number of external IRQ lines + * + Property "num-prio-bits": number of priority bits in the NVIC * + Property "memory": MemoryRegion defining the physical address space * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal * devices will be automatically layered on top of this view.) -- 2.42.0
[PATCH v3 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
Reviewed-by: Peter Maydell
---
hw/intc/armv7m_nvic.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 50f9a973a2..404a445138 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = {
static Property props_nvic[] = {
/* Number of external IRQ lines (so excluding the 16 internal exceptions)
*/
DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
+/*
+ * Number of the maximum priority bits that can be used. 0 means
+ * to use a reasonable default.
+ */
+DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0),
DEFINE_PROP_END_OF_LIST()
};
@@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error
**errp)
/* include space for internal exception vectors */
s->num_irq += NVIC_FIRST_IRQ;
-s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+if (s->num_prio_bits == 0) {
+/*
+ * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1
+ * and 8 bits otherwise.
+ */
+s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+} else {
+uint8_t min_prio_bits =
+arm_feature(>cpu->env, ARM_FEATURE_V7) ? 3 : 2;
+if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) {
+error_setg(errp,
+ "num-prio-bits %d is outside "
+ "NVIC acceptable range [%d-8]",
+ s->num_prio_bits, min_prio_bits);
+return;
+}
+}
/*
* This device provides a single memory region which covers the
--
2.42.0
[PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices
This patch series builds on a discussion initiated by Anton Kochkov on
this list in 2022. It allows setting the appropriate number of priority
bits for Cortex-M devices. For example, FreeRTOS checks at startup that
the right number of priority bits is available in order to guarantee
its runtime structures safety. They have added a configuration option
to disable this check when running on QEMU because QEMU always use 2
bits for Cortex-M0/M0+/M1 and 8 bits for other devices.
While this change allows the number of priority bits to be properly
configured, it keeps the same default as before in order to preserve
backward compatibility unless the SoC configures the exact value.
Changes from v2:
- Add the description of the new armv7m property in include/hw/arm/armv7m.h.
Changes from v1:
- Add support for the STM32L4x5 SOC family (which is currently
under review for integration) and fix the Based-on: trailer
in the cover letter.
- Fix a typo in one of the commit messages ("compatibility")
Based-on: <20240106163905.42027-1-ines.var...@telecom-paris.fr>
([PATCH v5 0/2] Add minimal support for the B-L475E-IOT01A board)
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-prio-bits" property
hw/arm/socs: configure priority bits for existing SOCs
hw/arm/armv7m.c | 2 ++
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
hw/arm/stm32l4x5_soc.c | 1 +
hw/intc/armv7m_nvic.c | 23 ++-
include/hw/arm/armv7m.h | 1 +
8 files changed, 31 insertions(+), 1 deletion(-)
--
2.42.0
[PATCH v3 3/3] hw/arm/socs: configure priority bits for existing SOCs
Update the number of priority bits for a number of existing
SoCs according to their technical documentation:
- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
---
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
hw/arm/stm32l4x5_soc.c | 1 +
5 files changed, 6 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 729a8bf569..d18b1144af 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -47,6 +47,7 @@
#define BP_GAMEPAD 0x04
#define NUM_IRQ_LINES 64
+#define NUM_PRIO_BITS 3
typedef const struct {
const char *name;
@@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms,
stellaris_board_info *board)
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
+qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
qdev_connect_clock_in(nvic, "cpuclk",
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index b90d440d7a..808b783515 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -115,6 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,
Error **errp)
/* Init ARMv7m */
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 61);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 1a548646f6..a451e21f59 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -127,6 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index a65bbe298d..2ad5b79a06 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -149,6 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index 7513db0d6a..cc70c83d20 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -105,6 +105,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,
Error **errp)
object_initialize_child(OBJECT(dev_soc), "armv7m", >armv7m,
TYPE_ARMV7M);
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
--
2.42.0
[PATCH] tests/qtest/virtio-ccw: Fix device presence checking
An apparent copy-paste error tests for the presence of the
virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw
device.
Signed-off-by: Samuel Tardieu
---
tests/qtest/virtio-ccw-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/virtio-ccw-test.c b/tests/qtest/virtio-ccw-test.c
index f4f5858b84..7a5357c212 100644
--- a/tests/qtest/virtio-ccw-test.c
+++ b/tests/qtest/virtio-ccw-test.c
@@ -85,7 +85,7 @@ int main(int argc, char **argv)
if (qtest_has_device("virtio-rng-ccw")) {
qtest_add_func("/virtio/rng/nop", virtio_rng_nop);
}
-if (qtest_has_device("virtio-rng-ccw")) {
+if (qtest_has_device("virtio-scsi-ccw")) {
qtest_add_func("/virtio/scsi/nop", virtio_scsi_nop);
qtest_add_func("/virtio/scsi/hotplug", virtio_scsi_hotplug);
}
--
2.42.0
Re: [PATCH v2 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property
Peter Maydell writes: There's a comment in include/hw/arm/armv7m.h which documents all the GPIO inputs, QOM properties, etc, that this device has -- that also needs a line adding to it for this property. Thanks Peter for your review. I'll send a v3 containing the requested change after Inès has submitted an updated version of her "Add minimal support for the B-L475E-IOT01A board" serie on which this one is based. Best. Sam -- Samuel Tardieu
Re: [PATCH v5 1/3] hw/misc: Implement STM32L4x5 EXTI
On 04/01/2024 14:40, Philippe Mathieu-Daudé wrote:
On 4/1/24 14:23, Samuel Tardieu wrote:
Philippe Mathieu-Daudé writes:
This doesn't build:
../../hw/misc/stm32l4x5_exti.c:172:9: error: expected expression
const uint32_t set1 = value & ~DIRECT_LINE_MASK1;
[…]
I could build using:
- case EXTI_SWIER1:
+ case EXTI_SWIER1: {
Out or curiosity, which C compiler or option do you use for checking?
I have no problem building this using "./configure
--target-list=arm-softmmu" with GCC 12.3.0.
C compiler for the host machine: clang (clang 15.0.0 "Apple clang
version 15.0.0 (clang-1500.0.40.1)")
C linker for the host machine: clang ld64 1015.7
Indeed, it looks like mixing labels, declarations and statements is a
GCC extension. I've switched to clang and can reproduce the failure. Thanks!
Re: [PATCH v5 1/3] hw/misc: Implement STM32L4x5 EXTI
Philippe Mathieu-Daudé writes:
This doesn't build:
../../hw/misc/stm32l4x5_exti.c:172:9: error: expected expression
const uint32_t set1 = value & ~DIRECT_LINE_MASK1;
[…]
I could build using:
-case EXTI_SWIER1:
+case EXTI_SWIER1: {
Out or curiosity, which C compiler or option do you use for
checking? I have no problem building this using "./configure
--target-list=arm-softmmu" with GCC 12.3.0.
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
[PATCH] docs: use "buses" rather than "busses"
If "busses" might be encountered as a plural of "bus" (5 instances), the correct spelling is "buses" (26 instances). Fixing those 5 instances makes the doc more consistent. Signed-off-by: Samuel Tardieu --- docs/system/arm/palm.rst| 2 +- docs/system/arm/xscale.rst | 2 +- docs/system/devices/can.rst | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/palm.rst b/docs/system/arm/palm.rst index 47ff9b36d4..61bc8d34f4 100644 --- a/docs/system/arm/palm.rst +++ b/docs/system/arm/palm.rst @@ -14,7 +14,7 @@ following elements: - On-chip Real Time Clock - TI TSC2102i touchscreen controller / analog-digital converter / - Audio CODEC, connected through MicroWire and |I2S| busses + Audio CODEC, connected through MicroWire and |I2S| buses - GPIO-connected matrix keypad diff --git a/docs/system/arm/xscale.rst b/docs/system/arm/xscale.rst index d2d5949e10..e239136c3c 100644 --- a/docs/system/arm/xscale.rst +++ b/docs/system/arm/xscale.rst @@ -32,4 +32,4 @@ The clamshell PDA models emulation includes the following peripherals: - Three on-chip UARTs -- WM8750 audio CODEC on |I2C| and |I2S| busses +- WM8750 audio CODEC on |I2C| and |I2S| buses diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst index 0af3d9912a..09121836fd 100644 --- a/docs/system/devices/can.rst +++ b/docs/system/devices/can.rst @@ -1,12 +1,12 @@ CAN Bus Emulation Support = The CAN bus emulation provides mechanism to connect multiple -emulated CAN controller chips together by one or multiple CAN busses -(the controller device "canbus" parameter). The individual busses +emulated CAN controller chips together by one or multiple CAN buses +(the controller device "canbus" parameter). The individual buses can be connected to host system CAN API (at this time only Linux SocketCAN is supported). -The concept of busses is generic and different CAN controllers +The concept of buses is generic and different CAN controllers can be implemented. The initial submission implemented SJA1000 controller which -- 2.42.0
[PATCH] tests/unit/test-qga: do not qualify executable paths
guest-exec invocation does not need the full path of the executable to
execute. Using only the command names ensures correct execution of the
test on systems not adhering to the FHS.
Signed-off-by: Samuel Tardieu
---
tests/unit/test-qga.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/unit/test-qga.c b/tests/unit/test-qga.c
index 671e83cb86..8cddf5dc37 100644
--- a/tests/unit/test-qga.c
+++ b/tests/unit/test-qga.c
@@ -822,7 +822,7 @@ static void test_qga_guest_exec(gconstpointer fix)
/* exec 'echo foo bar' */
ret = qmp_fd(fixture->fd, "{'execute': 'guest-exec', 'arguments': {"
- " 'path': '/bin/echo', 'arg': [ '-n', '\" test_str \"' ],"
+ " 'path': 'echo', 'arg': [ '-n', '\" test_str \"' ],"
" 'capture-output': true } }");
g_assert_nonnull(ret);
qmp_assert_no_error(ret);
@@ -883,7 +883,7 @@ static void test_qga_guest_exec_separated(gconstpointer fix)
/* exec 'echo foo bar' */
ret = qmp_fd(fixture->fd, "{'execute': 'guest-exec', 'arguments': {"
- " 'path': '/bin/bash',"
+ " 'path': 'bash',"
" 'arg': [ '-c', 'for i in $(seq 4); do if (( $i %% 2 ));
then echo stdout; else echo stderr 1>&2; fi; done;' ],"
" 'capture-output': 'separated' } }");
g_assert_nonnull(ret);
@@ -924,7 +924,7 @@ static void test_qga_guest_exec_merged(gconstpointer fix)
/* exec 'echo foo bar' */
ret = qmp_fd(fixture->fd, "{'execute': 'guest-exec', 'arguments': {"
- " 'path': '/bin/bash',"
+ " 'path': 'bash',"
" 'arg': [ '-c', 'for i in $(seq 4); do if (( $i %% 2 ));
then echo stdout; else echo stderr 1>&2; fi; done;' ],"
" 'capture-output': 'merged' } }");
g_assert_nonnull(ret);
--
2.42.0
[PATCH v2 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
---
hw/intc/armv7m_nvic.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 942be7bd11..82aacd7f22 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = {
static Property props_nvic[] = {
/* Number of external IRQ lines (so excluding the 16 internal exceptions)
*/
DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
+/*
+ * Number of the maximum priority bits that can be used. 0 means
+ * to use a reasonable default.
+ */
+DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0),
DEFINE_PROP_END_OF_LIST()
};
@@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error
**errp)
/* include space for internal exception vectors */
s->num_irq += NVIC_FIRST_IRQ;
-s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+if (s->num_prio_bits == 0) {
+/*
+ * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1
+ * and 8 bits otherwise.
+ */
+s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+} else {
+uint8_t min_prio_bits =
+arm_feature(>cpu->env, ARM_FEATURE_V7) ? 3 : 2;
+if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) {
+error_setg(errp,
+ "num-prio-bits %d is outside "
+ "NVIC acceptable range [%d-8]",
+ s->num_prio_bits, min_prio_bits);
+return;
+}
+}
/*
* This device provides a single memory region which covers the
--
2.42.0
[PATCH v2 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property
A SoC will not have a direct access to the NVIC embedded in its ARM core. By aliasing the "num-prio-bits" property similarly to what is done for the "num-irq" one, a SoC can easily configure it on its armv7m instance. Signed-off-by: Samuel Tardieu --- hw/arm/armv7m.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index d10abb36a8..4fda2d1d47 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -256,6 +256,8 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "nvic", >nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(>nvic), "num-irq"); +object_property_add_alias(obj, "num-prio-bits", + OBJECT(>nvic), "num-prio-bits"); object_initialize_child(obj, "systick-reg-ns", >systick[M_REG_NS], TYPE_SYSTICK); -- 2.42.0
[PATCH v2 3/3] hw/arm/socs: configure priority bits for existing SOCs
Update the number of priority bits for a number of existing
SoCs according to their technical documentation:
- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
---
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
hw/arm/stm32l4x5_soc.c | 1 +
5 files changed, 6 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index dd90f686bf..38981967f3 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -47,6 +47,7 @@
#define BP_GAMEPAD 0x04
#define NUM_IRQ_LINES 64
+#define NUM_PRIO_BITS 3
typedef const struct {
const char *name;
@@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms,
stellaris_board_info *board)
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
+qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
qdev_connect_clock_in(nvic, "cpuclk",
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index b90d440d7a..808b783515 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -115,6 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,
Error **errp)
/* Init ARMv7m */
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 61);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 1a548646f6..a451e21f59 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -127,6 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index a65bbe298d..2ad5b79a06 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -149,6 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index 7513db0d6a..cc70c83d20 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -105,6 +105,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,
Error **errp)
object_initialize_child(OBJECT(dev_soc), "armv7m", >armv7m,
TYPE_ARMV7M);
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
--
2.42.0
[PATCH v2 0/3] Add "num-prio-bits" property for Cortex-M devices
This patch series builds on a discussion initiated by Anton Kochkov on
this list in 2022. It allows setting the appropriate number of priority
bits for Cortex-M devices. For example, FreeRTOS checks at startup that
the right number of priority bits is available in order to guarantee
its runtime structures safety. They have added a configuration option
to disable this check when running on QEMU because QEMU always use 2
bits for Cortex-M0/M0+/M1 and 8 bits for other devices.
While this change allows the number of priority bits to be properly
configured, it keeps the same default as before in order to preserve
backward compatibility unless the SoC configures the exact value.
Changes from v1:
- Add support for the STM32L4x5 SOC family (which is currently
under review for integration) and fix the Based-on: trailer
in the cover letter.
- Fix a typo in one of the commit messages ("compatibility")
Based-on: <20231221213838.54944-1-ines.var...@telecom-paris.fr>
([PATCH v4 0/2] Add minimal support for the B-L475E-IOT01A board)
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-prio-bits" property
hw/arm/socs: configure priority bits for existing SOCs
hw/arm/armv7m.c| 2 ++
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
hw/arm/stm32l4x5_soc.c | 1 +
hw/intc/armv7m_nvic.c | 23 ++-
7 files changed, 30 insertions(+), 1 deletion(-)
--
2.42.0
Re: [PATCH v2] scripts/checkpatch: Support codespell checking
+ --codespellUse the codespell dictionary for spelling/typos + (default:$codespellfile) Nitpick: I would have used a space after ":". + # If /usr/share/codespell/dictionary.txt is not present, try to find it + # under codespell's install directory: /data/dictionary.txt This works correctly on my NixOS system using a non-FHS layout and properly locates the codespell file. This patch made me find a typo in one of my commit messages. Tested-by: Samuel Tardieu Sam -- Samuel Tardieu Télécom Paris - Institut Polytechnique de Paris
Re: [PATCH] target/hexagon/idef-parser/prepare: use env to invoke bash
Michael Tokarev writes: -#!/bin/bash +#!/usr/bin/env bash What's the reason for this indirection? bash has been /bin/bash for decades, it is used this way in many other places in qemu code and in other projects. Yes I know about current move /bin => /usr/bin etc, but the thing is that traditional paths like this one (or like /bin/sh) is not going away any time soon. What's the matter here? In addition to Stefan's answer, some modern systems use a per-user file system hierarchy where each user (or even each environment development for a user) gets a global set of directories with only the applications they want. This is done either through adding each application directory into the user PATH or by using a set of user-specific bin/lib/... directories full of symlinks to the chosen applications. In those environments, /usr/bin might only contain "env", such as "/usr/bin/env application" works. This is the case for example on NixOS, which is more and more used in research environments for their easily reproducible build environments. Sam -- Samuel Tardieu Télécom Paris - Institut Polytechnique de Paris
Re: [PATCH 0/3] Add "num-prio-bits" property for Cortex-M devices
Peter Maydell writes: Any idea to why patchew fails to apply thoses patches? The mbox at <https://patchew.org/QEMU/20231216182740.3305724-1-...@rfc1149.net/> applies cleanly on master AFAICS. This is because you put a Based-on: tag in the cover letter. Based-on: means "please apply this other patch first before this series, because there is a dependency" (we use it for things like "this patchset has to sit on top of some other cleanup patchset I sent last week and which hasn't got into git yet"). So patchew applied Anton's original patch from 2022, and then tried to apply your three patches on top of that, which caused a conflict. Thanks for the explanation. I thought "Based-on:" was just a polite way of attributing credit to past discussions. I'll keep that in mind. Do you want me to resubmit it as a v2 without the "Based-on:" tag so that patchew gets it right? Anyway, I just wanted to say that this patchset is on my todo list to review but I'm not going to be able to get to it before I break for Christmas, so I'll get back to it in January. Thanks for the contribution! Noted! Best. Sam -- Samuel Tardieu
[PATCH v2 2/2] tcg: Make the cleanup-on-error path unique
By calling `error_setg_errno()` before jumping to the cleanup-on-error
path at the `fail` label, the cleanup path is clearer.
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index 467e51cf6f..478ec051c4 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -584,7 +584,9 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size,
Error **errp)
buf_rx = mmap(NULL, size, host_prot_read_exec(), MAP_SHARED, fd, 0);
if (buf_rx == MAP_FAILED) {
-goto fail_rx;
+error_setg_errno(errp, errno,
+ "failed to map shared memory for execute");
+goto fail;
}
close(fd);
@@ -594,8 +596,6 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size,
Error **errp)
return PROT_READ | PROT_WRITE;
- fail_rx:
-error_setg_errno(errp, errno, "failed to map shared memory for execute");
fail:
/* buf_rx is always equal to MAP_FAILED here and does not require cleanup
*/
if (buf_rw) {
--
2.42.0
[PATCH v2 0/2] tcg: Jump after always false condition
Unreachable code in an error handling block is listed in issue https://gitlab.com/qemu-project/qemu/-/issues/2030. After removing this code, the `fail` label is now immediately followed by a test whose condition can never be true when coming explicitly via this label. Moving the label down preserves the fall-through case while avoiding testing an always false condition. Changes from v1: - Add a comment explaining that `buf_rx` does not require cleanup - Use a unique cleanup path for the function by setting `errno` before jumping to the cleanup block. Samuel Tardieu (2): tcg: Remove unreachable code tcg: Make the cleanup-on-error path unique tcg/region.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.42.0
[PATCH v2 1/2] tcg: Remove unreachable code
The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to
its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never
executed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
---
tcg/region.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index 86692455c0..467e51cf6f 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -597,9 +597,7 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size,
Error **errp)
fail_rx:
error_setg_errno(errp, errno, "failed to map shared memory for execute");
fail:
-if (buf_rx != MAP_FAILED) {
-munmap(buf_rx, size);
-}
+/* buf_rx is always equal to MAP_FAILED here and does not require cleanup
*/
if (buf_rw) {
munmap(buf_rw, size);
}
--
2.42.0
Re: [PATCH 2/2] tcg: Jump after always false condition
Peter Maydell writes: So, well, all of this is definitely removing dead code, but on the other hand it's also moving away from the coding-style pattern the function has at the moment, which is "there is a fail-and-exit codepath which is robust against wherever you might choose to jump to it, and so if we need to add new code to this function then it also can jump to 'fail' without any further updates to that error-exit path". Instead we end up with an "every error-exit check does its own tidyup" idiom. For the sake of not having a static checker say "this is technically dead code", is that worth doing, or does it make the code a little less readable and less amenable to future modification? I'm not sure... Hi Peter. I see your point and I agree with you. Perhaps we could get the best of both worlds by: - renaming `fail_rx` as `fail`, so that we get a unique exit block — not only will the compiler optimize the jump if it can, and this is the slow path anyway - adding a one-line comment saying that `buf_rx` is always `MAP_FAILED` – that will let people know that they might need to add a cleanup if they add another jump to `fail` - calling `error_setg_errno()` at the right place before jumping to `fail` I will produce a v2 to make this proposal clearer. Sam -- Samuel Tardieu
Re: [PATCH 0/3] Add "num-prio-bits" property for Cortex-M devices
Samuel Tardieu (3): hw/intc/armv7m_nvic: add "num-prio-bits" property hw/arm/armv7m: alias the NVIC "num-prio-bits" property hw/arm/socs: configure priority bits for existing SOCs Any idea to why patchew fails to apply thoses patches? The mbox at <https://patchew.org/QEMU/20231216182740.3305724-1-...@rfc1149.net/> applies cleanly on master AFAICS. Sam -- Samuel Tardieu
[PATCH 3/3] hw/arm/socs: configure priority bits for existing SOCs
Update the number of priority bits for a number of existing
SOCsaccording to their technical documentation:
- STM32F100/F205/F405: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
---
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index dd90f686bf..38981967f3 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -47,6 +47,7 @@
#define BP_GAMEPAD 0x04
#define NUM_IRQ_LINES 64
+#define NUM_PRIO_BITS 3
typedef const struct {
const char *name;
@@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms,
stellaris_board_info *board)
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
+qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
qdev_connect_clock_in(nvic, "cpuclk",
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index b90d440d7a..808b783515 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -115,6 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,
Error **errp)
/* Init ARMv7m */
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 61);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 1a548646f6..a451e21f59 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -127,6 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index a65bbe298d..2ad5b79a06 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -149,6 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,
Error **errp)
armv7m = DEVICE(>armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
+qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
--
2.42.0
[PATCH 0/3] Add "num-prio-bits" property for Cortex-M devices
This patch series builds on a discussion initiated by Anton Kochkov on this list in 2022. It allows setting the appropriate number of priority bits for Cortex-M devices. For example, FreeRTOS checks at startup that the right number of priority bits is available in order to guarantee its runtime structures safety. They added a configuration option specially for QEMU to disable this check because QEMU always use 2 bits for Cortex-M0/M0+/M1 and 8 bits for other devices. While this change allows the number of priority bits to be properly configured, it keeps the same default as before in order to preserve backward compatibility. Based-on: <20220813112559.1974427-1-anton.koch...@proton.me> ([PATCH] hw/arm/nvic: implement "num-prio-bits" property) Samuel Tardieu (3): hw/intc/armv7m_nvic: add "num-prio-bits" property hw/arm/armv7m: alias the NVIC "num-prio-bits" property hw/arm/socs: configure priority bits for existing SOCs hw/arm/armv7m.c| 2 ++ hw/arm/stellaris.c | 2 ++ hw/arm/stm32f100_soc.c | 1 + hw/arm/stm32f205_soc.c | 1 + hw/arm/stm32f405_soc.c | 1 + hw/intc/armv7m_nvic.c | 23 ++- 6 files changed, 29 insertions(+), 1 deletion(-) -- 2.42.0
[PATCH 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibiltiy.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
---
hw/intc/armv7m_nvic.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 942be7bd11..82aacd7f22 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = {
static Property props_nvic[] = {
/* Number of external IRQ lines (so excluding the 16 internal exceptions)
*/
DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
+/*
+ * Number of the maximum priority bits that can be used. 0 means
+ * to use a reasonable default.
+ */
+DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0),
DEFINE_PROP_END_OF_LIST()
};
@@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error
**errp)
/* include space for internal exception vectors */
s->num_irq += NVIC_FIRST_IRQ;
-s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+if (s->num_prio_bits == 0) {
+/*
+ * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1
+ * and 8 bits otherwise.
+ */
+s->num_prio_bits = arm_feature(>cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+} else {
+uint8_t min_prio_bits =
+arm_feature(>cpu->env, ARM_FEATURE_V7) ? 3 : 2;
+if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) {
+error_setg(errp,
+ "num-prio-bits %d is outside "
+ "NVIC acceptable range [%d-8]",
+ s->num_prio_bits, min_prio_bits);
+return;
+}
+}
/*
* This device provides a single memory region which covers the
--
2.42.0
[PATCH 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property
Signed-off-by: Samuel Tardieu --- hw/arm/armv7m.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index d10abb36a8..4fda2d1d47 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -256,6 +256,8 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "nvic", >nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(>nvic), "num-irq"); +object_property_add_alias(obj, "num-prio-bits", + OBJECT(>nvic), "num-prio-bits"); object_initialize_child(obj, "systick-reg-ns", >systick[M_REG_NS], TYPE_SYSTICK); -- 2.42.0
[PATCH 2/2] tcg: Jump after always false condition
`buf_rw` is always `NULL` when jumping to the `fail` label. Move the
label `down` after the `if (buf_rw) { ... }` statement.
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/region.c b/tcg/region.c
index 6d657e8c33..691a726eae 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -596,10 +596,10 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t
size, Error **errp)
fail_rx:
error_setg_errno(errp, errno, "failed to map shared memory for execute");
- fail:
if (buf_rw) {
munmap(buf_rw, size);
}
+ fail:
if (fd >= 0) {
close(fd);
}
--
2.42.0
[PATCH 1/2] tcg: Remove unreachable code
The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to
its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never
executed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index 86692455c0..6d657e8c33 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -597,9 +597,6 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size,
Error **errp)
fail_rx:
error_setg_errno(errp, errno, "failed to map shared memory for execute");
fail:
-if (buf_rx != MAP_FAILED) {
-munmap(buf_rx, size);
-}
if (buf_rw) {
munmap(buf_rw, size);
}
--
2.42.0
[PATCH 0/2] Remove unreachable code and move label after unreachable condition
Unreachable code in an error handling block is listed in issue https://gitlab.com/qemu-project/qemu/-/issues/2030. After removing this code, the `fail` label is now immediately followed by a test whose condition can never be true when coming explicitly via this label. Moving the label down preserves the fall-through case while avoiding testing an always false condition. Samuel Tardieu (2): tcg: Remove unreachable code tcg: Jump after always false condition tcg/region.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.42.0
[PATCH] docs: fix typo
Signed-off-by: Samuel Tardieu --- docs/tools/qemu-img.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/tools/qemu-img.rst b/docs/tools/qemu-img.rst index 4459c065f1..3653adb963 100644 --- a/docs/tools/qemu-img.rst +++ b/docs/tools/qemu-img.rst @@ -406,7 +406,7 @@ Command description: Compare exits with ``0`` in case the images are equal and with ``1`` in case the images differ. Other exit codes mean an error occurred during execution and standard error output should contain an error message. - The following table sumarizes all exit codes of the compare subcommand: + The following table summarizes all exit codes of the compare subcommand: 0 Images are identical (or requested help was printed) -- 2.42.0
Re: [PATCH] qemu/timer: Don't use RDTSC on i486
Petr Cvek writes: Actually I was thinking about mentioning it in the commit message also, but I wasn't able to find any specification for that (if all compilers use it). Note that this change would be safe: at worst, some compilers don't use __tune_i386__ and the situation would be the same as today without the patch. Other problem is the __tune_i386__ is also set when -mtune=i386 (but with -march=i686). Indeed, this is the case for GCC (not clang). Sam -- Samuel Tardieu Télécom Paris - Institut Polytechnique de Paris
Re: [PATCH] qemu/timer: Don't use RDTSC on i486
Petr Cvek writes: GCC defines __i386__ for i386 and i486, which both lack RDTSC instruction. The i386 seems to be impossible to distinguish, but i486 can be identified by checking for undefined __i486__. Couldn't you check for an undefined __tune_i386__, which would be set by both GCC and LLVM when using -march=i386. Sam -- Samuel Tardieu Télécom Paris - Institut Polytechnique de Paris
[PATCH] target/hexagon/idef-parser/prepare: use env to invoke bash
This file is the only one involved in the compilation process which still uses the /bin/bash path. Signed-off-by: Samuel Tardieu --- target/hexagon/idef-parser/prepare | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/idef-parser/prepare b/target/hexagon/idef-parser/prepare index 72d6fcbd21..cb3622d4f8 100755 --- a/target/hexagon/idef-parser/prepare +++ b/target/hexagon/idef-parser/prepare @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved. -- 2.42.0
[Qemu-devel] Re: Interesting QEMU + OpenVPN
Paul == Paul Brook [EMAIL PROTECTED] writes: Paul You can already bridge the host and gues using the existing Paul networking options (and/or VDE - http://vde.sf.net), without the Paul encryption overhead and without needing any special setup on the Paul guest. This is precisely what I do. When my host system starts up, it creates a bridge called localnet with only one card in it (my physical ethernet card). My /etc/qemu-ifup reads: #! /bin/sh sudo ifconfig $1 up sudo brctl addif localnet $1 I run qemu with -net nic -net tap and that's it, the qemu instance has access to my local network, DHCP server, IPv6 routers, etc. Sam -- Samuel Tardieu -- [EMAIL PROTECTED] -- http://www.rfc1149.net/ ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu port for sh4 target in progress
Just so that people do not start to work on it on their side, I have started a qemu for the sh4 target (sh7750s variant). However, I will not be able to work on it for one month as I'm going to Japan for vacation. At this time, qemu is able to start the Shix 2.0 board by Alexis Polti described here (in French): http://perso.enst.fr/~polti/realisations/shix20/ qemu runs the bootloader, reads the Linux kernel from the NAND flash connected to the sh4 GPIO ports and starts to execute it. The port is not complete and not ready to be integrated with qemu, but if people want to work on it while I am away, drop me a mail in the next 48 hours so that I can send you the patch. I plan to end this port when I come back in January 2006. Sam -- Samuel Tardieu -- [EMAIL PROTECTED] -- http://www.rfc1149.net/ ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
