[Qemu-devel] [PATCH v2 1/1] Add support for PCI Enhanced Allocation "BARs"
PCI Enhanced Allocation is a new method of allocating MMIO & IO
resources for PCI devices & bridges. It can be used instead
of the traditional PCI method of using BARs.
EA entries are hardware-initialized to a fixed address.
Unlike BARs, regions described by EA are cannot be moved.
Because of this, only devices which are permanently connected to
the PCI bus can use EA. A removable PCI card must not use EA.
This patch enables any existing QEMU PCI model to use EA instead of
BARs. It adds EA options to the PCI device parameters.
The Enhanced Allocation ECN is publicly available here:
https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf
Signed-off-by: Sean O. Stalley
---
hw/pci/Makefile.objs| 2 +-
hw/pci/pci.c| 95 +--
hw/pci/pci_ea.c | 202
include/hw/pci/pci.h| 6 ++
include/hw/pci/pci_ea.h | 42 ++
include/qemu/typedefs.h | 1 +
6 files changed, 324 insertions(+), 24 deletions(-)
create mode 100644 hw/pci/pci_ea.c
create mode 100644 include/hw/pci/pci_ea.h
diff --git a/hw/pci/Makefile.objs b/hw/pci/Makefile.objs
index 9f905e6..e5d80cf 100644
--- a/hw/pci/Makefile.objs
+++ b/hw/pci/Makefile.objs
@@ -3,7 +3,7 @@ common-obj-$(CONFIG_PCI) += msix.o msi.o
common-obj-$(CONFIG_PCI) += shpc.o
common-obj-$(CONFIG_PCI) += slotid_cap.o
common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
-common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o pcie_port.o
+common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o pcie_port.o pci_ea.o
common-obj-$(call lnot,$(CONFIG_PCI)) += pci-stub.o
common-obj-$(CONFIG_ALL) += pci-stub.o
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 2158043..f3b255a 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -23,6 +23,7 @@
*/
#include "hw/hw.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_ea.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
@@ -58,6 +59,9 @@ static Property pci_props[] = {
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
QEMU_PCI_CAP_SERR_BITNR, true),
+DEFINE_PROP_ARRAY("ea_addr", PCIDevice, ea_addr_len, ea_addr,
+ qdev_prop_uint64, hwaddr),
+
DEFINE_PROP_END_OF_LIST()
};
@@ -955,43 +959,76 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint32_t addr;
uint64_t wmask;
pcibus_t size = memory_region_size(memory);
+bool enhanced = (pci_dev->ea_addr_len > 0);
assert(region_num >= 0);
assert(region_num < PCI_NUM_REGIONS);
-if (size & (size-1)) {
+
+/* TODO: these checks should be done earlier */
+if (!enhanced && (size & (size-1))) {
fprintf(stderr, "ERROR: PCI region size must be pow2 "
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
exit(1);
}
+if (enhanced) {
+
+if (pci_dev->ea_addr_len <= region_num) {
+fprintf(stderr, "ERROR: Address for EA entry %i not given\n",
+region_num);
+exit(1);
+}
+
+if (pci_dev->ea_addr[region_num] == 0x0) {
+fprintf(stderr, "ERROR: Address for EA entry %i not set\n",
+region_num);
+exit(1);
+}
+
+if (pci_ea_invalid_addr(pci_dev->ea_addr[region_num])) {
+fprintf(stderr, "ERROR: Address for EA entry %i not valid\n",
+region_num);
+exit(1);
+}
+
+}
+
r = &pci_dev->io_regions[region_num];
r->addr = PCI_BAR_UNMAPPED;
r->size = size;
r->type = type;
-r->memory = NULL;
-
-wmask = ~(size - 1);
-addr = pci_bar(pci_dev, region_num);
-if (region_num == PCI_ROM_SLOT) {
-/* ROM enable bit is writable */
-wmask |= PCI_ROM_ADDRESS_ENABLE;
-}
-pci_set_long(pci_dev->config + addr, type);
-if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
-r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
-pci_set_quad(pci_dev->wmask + addr, wmask);
-pci_set_quad(pci_dev->cmask + addr, ~0ULL);
-} else {
-pci_set_long(pci_dev->wmask + addr, wmask & 0x);
-pci_set_long(pci_dev->cmask + addr, 0x);
+r->enhanced = enhanced;
+r->memory = memory;
+r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO ?
+pci_dev->bus->address_space_io : pci_dev->bus->address_space_mem;
+
+if (!enhanced) {
+
+wmask = ~(size - 1);
+addr = pci_bar(pci_dev, region_num);
+if (region_num == PCI_ROM_SLOT) {
+/* ROM enable bit is writable */
+
[Qemu-devel] [PATCH v2 0/1] Add support for PCI Enhanced Allocation "BARs"
Changes from v1: - added a cover letter with a change log - made spelling fixes throughout patch - no longer add unnecessary whitespace - removed brackets in return calls - only add 1 PCI device parameter instead of 2 - don't add definitions to imported include/hw/pci/pci_regs.h Sean O. Stalley (1): Add support for PCI Enhanced Allocation "BARs" hw/pci/Makefile.objs| 2 +- hw/pci/pci.c| 95 +-- hw/pci/pci_ea.c | 202 include/hw/pci/pci.h| 6 ++ include/hw/pci/pci_ea.h | 42 ++ include/qemu/typedefs.h | 1 + 6 files changed, 324 insertions(+), 24 deletions(-) create mode 100644 hw/pci/pci_ea.c create mode 100644 include/hw/pci/pci_ea.h -- 1.9.1
Re: [Qemu-devel] [PATCH 1/1] Add support for PCI Enhanced Allocation "BARs"
On Sun, May 31, 2015 at 08:13:49PM +0200, Michael S. Tsirkin wrote: > On Wed, May 13, 2015 at 10:29:42AM -0700, Sean O. Stalley wrote: > > On Wed, May 13, 2015 at 08:09:46AM +0200, Michael S. Tsirkin wrote: > > > On Tue, May 12, 2015 at 02:23:07PM -0700, Sean O. Stalley wrote: > > > > On Tue, May 12, 2015 at 11:33:49AM +0200, Michael S. Tsirkin wrote: > > > > > On Mon, May 11, 2015 at 01:08:05PM -0700, Sean O. Stalley wrote: > > > > > > On Mon, May 11, 2015 at 09:26:08PM +0200, Michael S. Tsirkin wrote: > > > > > > > On Mon, May 11, 2015 at 11:56:44AM -0700, Sean O. Stalley wrote: > > > > > > > > PCI Enhanced Allocation is a new method of allocating MMIO & IO > > > > > > > > resources for PCI devices & bridges. It can be used instead > > > > > > > > of the traditional PCI method of using BARs. > > > > > > > > > > > > > > > > EA entries are hardware-initialized to a fixed address. > > > > > > > > Unlike BARs, regions described by EA are cannot be moved. > > > > > > > > Because of this, only devices which are perminately connected to > > > > > > > > the PCI bus can use EA. A removeable PCI card must not use EA. > > > > > > > > > > > > > > > > This patchset enables any existing QEMU PCI model to use EA in > > > > > > > > leiu of > > > > > > > > BARs. It adds EA options to the PCI device paramaters. > > > > > > > > > > > > > > > > The Enhanced Allocation ECN is publicly available here: > > > > > > > > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf > > > > > > > > > > > > > > > > Signed-off-by: Sean O. Stalley > > > > > > > > > > > > > > > > > > > > > I will review this, thanks. Will you also be sending a seabios > > > > > > > patch to > > > > > > > support these registers? When you do, please Cc me. > > > > > > > > > > > > Thanks Michael, > > > > > > > > > > > > I wasn't planning on sending a seabios patch. > > > > > > > > > > Won't this mean that bios might allocate PCI BARs conflicting with > > > > > EA entries, causing guest to crash? > > > > > > > > The short answer is yes, having EA hardware without an EA-aware bios > > > > could cause the guest to crash. > > > > > > > > To make matters worse, EA may cause old OSes may crash as well. > > > > If the OS supports hot-swap, and tries to remap the BARs, it could have > > > > the same problem. > > > > > > Should _CRS in ACPI be updated to exclude the EA regions? > > > If we do this, this problem will go away, won't it? > > > > > > > I think that would work, assuming the OS uses the _CRS. > > (https://lwn.net/Articles/373551/) > > > > I wasn't quite sure how EA should affect ACPI. > > This is why I pushed out the QEMU hardware changes before the EDKII changes. > > > So I'm waiting for v2 of this? > I wasn't planning on changing the hardware models in this patch (at least not until they are reviewed). Based on our discussion about ACPI, I was going to make changes to the firmware patches. I don't think I need to change anything in this patchset to fix ACPI. > > > > > > > > This patch allows the user to add EA devices to an existing machine, > > > > which is something that would never happen with real EA hardware. > > > > > > > > EA devices will only be present on new platforms. > > > > Because of this, I thought it made more sense to add EA support to > > > > EDKII than to seabios. > > > > Will adding EA support to seabios be necessary as well? > > > > > > If the problem with old OSes is fixable, then I think it's a good idea. > > > > > > > > > I do have some EDKII/OVMF patches I hope to send out soon. I will > > > > > > Cc you on those. > > > > > > > > > > > > -Sean > > > > > > > > > > > > > > > > > > > > > > > > > > > > --- > > > > > > > > hw/pci/Makefile.objs | 2 +- > > > > > > > > hw/pci/pci.c | 96 -- > > > > > > > > hw/pci/pci_ea.c | 203 > > > > > > > > ++ > > > > > > > > include/hw/pci/pci.h | 7 ++ > > > > > > > > include/hw/pci/pci_ea.h | 39 + > > > > > > > > include/hw/pci/pci_regs.h | 4 + > > > > > > > > include/qemu/typedefs.h | 1 + > > > > > > > > 7 files changed, 328 insertions(+), 24 deletions(-) > > > > > > > > create mode 100644 hw/pci/pci_ea.c > > > > > > > > create mode 100644 include/hw/pci/pci_ea.h
Re: [Qemu-devel] [PATCH 1/1] Add support for PCI Enhanced Allocation "BARs"
On Wed, May 13, 2015 at 08:09:46AM +0200, Michael S. Tsirkin wrote: > On Tue, May 12, 2015 at 02:23:07PM -0700, Sean O. Stalley wrote: > > On Tue, May 12, 2015 at 11:33:49AM +0200, Michael S. Tsirkin wrote: > > > On Mon, May 11, 2015 at 01:08:05PM -0700, Sean O. Stalley wrote: > > > > On Mon, May 11, 2015 at 09:26:08PM +0200, Michael S. Tsirkin wrote: > > > > > On Mon, May 11, 2015 at 11:56:44AM -0700, Sean O. Stalley wrote: > > > > > > PCI Enhanced Allocation is a new method of allocating MMIO & IO > > > > > > resources for PCI devices & bridges. It can be used instead > > > > > > of the traditional PCI method of using BARs. > > > > > > > > > > > > EA entries are hardware-initialized to a fixed address. > > > > > > Unlike BARs, regions described by EA are cannot be moved. > > > > > > Because of this, only devices which are perminately connected to > > > > > > the PCI bus can use EA. A removeable PCI card must not use EA. > > > > > > > > > > > > This patchset enables any existing QEMU PCI model to use EA in leiu > > > > > > of > > > > > > BARs. It adds EA options to the PCI device paramaters. > > > > > > > > > > > > The Enhanced Allocation ECN is publicly available here: > > > > > > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf > > > > > > > > > > > > Signed-off-by: Sean O. Stalley > > > > > > > > > > > > > > > I will review this, thanks. Will you also be sending a seabios patch > > > > > to > > > > > support these registers? When you do, please Cc me. > > > > > > > > Thanks Michael, > > > > > > > > I wasn't planning on sending a seabios patch. > > > > > > Won't this mean that bios might allocate PCI BARs conflicting with > > > EA entries, causing guest to crash? > > > > The short answer is yes, having EA hardware without an EA-aware bios could > > cause the guest to crash. > > > > To make matters worse, EA may cause old OSes may crash as well. > > If the OS supports hot-swap, and tries to remap the BARs, it could have the > > same problem. > > Should _CRS in ACPI be updated to exclude the EA regions? > If we do this, this problem will go away, won't it? > I think that would work, assuming the OS uses the _CRS. (https://lwn.net/Articles/373551/) I wasn't quite sure how EA should affect ACPI. This is why I pushed out the QEMU hardware changes before the EDKII changes. > > > > This patch allows the user to add EA devices to an existing machine, > > which is something that would never happen with real EA hardware. > > > > EA devices will only be present on new platforms. > > Because of this, I thought it made more sense to add EA support to EDKII > > than to seabios. > > Will adding EA support to seabios be necessary as well? > > If the problem with old OSes is fixable, then I think it's a good idea. > > > > > I do have some EDKII/OVMF patches I hope to send out soon. I will Cc > > > > you on those. > > > > > > > > -Sean > > > > > > > > > > > > > > > > > > > > --- > > > > > > hw/pci/Makefile.objs | 2 +- > > > > > > hw/pci/pci.c | 96 -- > > > > > > hw/pci/pci_ea.c | 203 > > > > > > ++ > > > > > > include/hw/pci/pci.h | 7 ++ > > > > > > include/hw/pci/pci_ea.h | 39 + > > > > > > include/hw/pci/pci_regs.h | 4 + > > > > > > include/qemu/typedefs.h | 1 + > > > > > > 7 files changed, 328 insertions(+), 24 deletions(-) > > > > > > create mode 100644 hw/pci/pci_ea.c > > > > > > create mode 100644 include/hw/pci/pci_ea.h
Re: [Qemu-devel] [PATCH 1/1] Add support for PCI Enhanced Allocation "BARs"
On Tue, May 12, 2015 at 11:33:49AM +0200, Michael S. Tsirkin wrote: > On Mon, May 11, 2015 at 01:08:05PM -0700, Sean O. Stalley wrote: > > On Mon, May 11, 2015 at 09:26:08PM +0200, Michael S. Tsirkin wrote: > > > On Mon, May 11, 2015 at 11:56:44AM -0700, Sean O. Stalley wrote: > > > > PCI Enhanced Allocation is a new method of allocating MMIO & IO > > > > resources for PCI devices & bridges. It can be used instead > > > > of the traditional PCI method of using BARs. > > > > > > > > EA entries are hardware-initialized to a fixed address. > > > > Unlike BARs, regions described by EA are cannot be moved. > > > > Because of this, only devices which are perminately connected to > > > > the PCI bus can use EA. A removeable PCI card must not use EA. > > > > > > > > This patchset enables any existing QEMU PCI model to use EA in leiu of > > > > BARs. It adds EA options to the PCI device paramaters. > > > > > > > > The Enhanced Allocation ECN is publicly available here: > > > > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf > > > > > > > > Signed-off-by: Sean O. Stalley > > > > > > > > > I will review this, thanks. Will you also be sending a seabios patch to > > > support these registers? When you do, please Cc me. > > > > Thanks Michael, > > > > I wasn't planning on sending a seabios patch. > > Won't this mean that bios might allocate PCI BARs conflicting with > EA entries, causing guest to crash? The short answer is yes, having EA hardware without an EA-aware bios could cause the guest to crash. To make matters worse, EA may cause old OSes may crash as well. If the OS supports hot-swap, and tries to remap the BARs, it could have the same problem. This patch allows the user to add EA devices to an existing machine, which is something that would never happen with real EA hardware. EA devices will only be present on new platforms. Because of this, I thought it made more sense to add EA support to EDKII than to seabios. Will adding EA support to seabios be necessary as well? > > I do have some EDKII/OVMF patches I hope to send out soon. I will Cc you on > > those. > > > > -Sean > > > > > > > > > > > > --- > > > > hw/pci/Makefile.objs | 2 +- > > > > hw/pci/pci.c | 96 -- > > > > hw/pci/pci_ea.c | 203 > > > > ++ > > > > include/hw/pci/pci.h | 7 ++ > > > > include/hw/pci/pci_ea.h | 39 + > > > > include/hw/pci/pci_regs.h | 4 + > > > > include/qemu/typedefs.h | 1 + > > > > 7 files changed, 328 insertions(+), 24 deletions(-) > > > > create mode 100644 hw/pci/pci_ea.c > > > > create mode 100644 include/hw/pci/pci_ea.h
Re: [Qemu-devel] [PATCH 1/1] Add support for PCI Enhanced Allocation "BARs"
On Mon, May 11, 2015 at 09:26:08PM +0200, Michael S. Tsirkin wrote: > On Mon, May 11, 2015 at 11:56:44AM -0700, Sean O. Stalley wrote: > > PCI Enhanced Allocation is a new method of allocating MMIO & IO > > resources for PCI devices & bridges. It can be used instead > > of the traditional PCI method of using BARs. > > > > EA entries are hardware-initialized to a fixed address. > > Unlike BARs, regions described by EA are cannot be moved. > > Because of this, only devices which are perminately connected to > > the PCI bus can use EA. A removeable PCI card must not use EA. > > > > This patchset enables any existing QEMU PCI model to use EA in leiu of > > BARs. It adds EA options to the PCI device paramaters. > > > > The Enhanced Allocation ECN is publicly available here: > > https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf > > > > Signed-off-by: Sean O. Stalley > > > I will review this, thanks. Will you also be sending a seabios patch to > support these registers? When you do, please Cc me. Thanks Michael, I wasn't planning on sending a seabios patch. I do have some EDKII/OVMF patches I hope to send out soon. I will Cc you on those. -Sean > > > > --- > > hw/pci/Makefile.objs | 2 +- > > hw/pci/pci.c | 96 -- > > hw/pci/pci_ea.c | 203 > > ++ > > include/hw/pci/pci.h | 7 ++ > > include/hw/pci/pci_ea.h | 39 + > > include/hw/pci/pci_regs.h | 4 + > > include/qemu/typedefs.h | 1 + > > 7 files changed, 328 insertions(+), 24 deletions(-) > > create mode 100644 hw/pci/pci_ea.c > > create mode 100644 include/hw/pci/pci_ea.h
[Qemu-devel] [PATCH 1/1] Add support for PCI Enhanced Allocation "BARs"
PCI Enhanced Allocation is a new method of allocating MMIO & IO
resources for PCI devices & bridges. It can be used instead
of the traditional PCI method of using BARs.
EA entries are hardware-initialized to a fixed address.
Unlike BARs, regions described by EA are cannot be moved.
Because of this, only devices which are perminately connected to
the PCI bus can use EA. A removeable PCI card must not use EA.
This patchset enables any existing QEMU PCI model to use EA in leiu of
BARs. It adds EA options to the PCI device paramaters.
The Enhanced Allocation ECN is publicly available here:
https://www.pcisig.com/specifications/conventional/ECN_Enhanced_Allocation_23_Oct_2014_Final.pdf
Signed-off-by: Sean O. Stalley
---
hw/pci/Makefile.objs | 2 +-
hw/pci/pci.c | 96 --
hw/pci/pci_ea.c | 203 ++
include/hw/pci/pci.h | 7 ++
include/hw/pci/pci_ea.h | 39 +
include/hw/pci/pci_regs.h | 4 +
include/qemu/typedefs.h | 1 +
7 files changed, 328 insertions(+), 24 deletions(-)
create mode 100644 hw/pci/pci_ea.c
create mode 100644 include/hw/pci/pci_ea.h
diff --git a/hw/pci/Makefile.objs b/hw/pci/Makefile.objs
index 9f905e6..e5d80cf 100644
--- a/hw/pci/Makefile.objs
+++ b/hw/pci/Makefile.objs
@@ -3,7 +3,7 @@ common-obj-$(CONFIG_PCI) += msix.o msi.o
common-obj-$(CONFIG_PCI) += shpc.o
common-obj-$(CONFIG_PCI) += slotid_cap.o
common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
-common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o pcie_port.o
+common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o pcie_port.o pci_ea.o
common-obj-$(call lnot,$(CONFIG_PCI)) += pci-stub.o
common-obj-$(CONFIG_ALL) += pci-stub.o
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index b3d5100..c7552ca 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -23,6 +23,7 @@
*/
#include "hw/hw.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_ea.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
@@ -58,6 +59,10 @@ static Property pci_props[] = {
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
QEMU_PCI_CAP_SERR_BITNR, true),
+DEFINE_PROP_BOOL("enhanced_allocation", PCIDevice, enhanced, false),
+DEFINE_PROP_ARRAY("ea_addr", PCIDevice, ea_addr_len, ea_addr,
+ qdev_prop_uint64, hwaddr),
+
DEFINE_PROP_END_OF_LIST()
};
@@ -882,6 +887,7 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev, PCIBus *bus,
config_read = pci_default_read_config;
if (!config_write)
config_write = pci_default_write_config;
+
pci_dev->config_read = config_read;
pci_dev->config_write = config_write;
bus->devices[devfn] = pci_dev;
@@ -929,40 +935,72 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
assert(region_num >= 0);
assert(region_num < PCI_NUM_REGIONS);
-if (size & (size-1)) {
+
+
+/* TODO: these checks should be done earlier */
+if (!pci_dev->enhanced && (size & (size-1))) {
fprintf(stderr, "ERROR: PCI region size must be pow2 "
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
exit(1);
}
+if (pci_dev->enhanced) {
+
+if (pci_dev->ea_addr_len <= region_num) {
+fprintf(stderr, "ERROR: Address for EA entry %i not given\n",
+region_num);
+exit(1);
+}
+
+if (pci_dev->ea_addr[region_num] == 0x0) {
+fprintf(stderr, "ERROR: Address for EA entry %i not set\n",
+region_num);
+exit(1);
+}
+
+if (pci_ea_invalid_addr(pci_dev->ea_addr[region_num])) {
+fprintf(stderr, "ERROR: Address for EA entry %i not valid\n",
+region_num);
+exit(1);
+}
+}
+
r = &pci_dev->io_regions[region_num];
r->addr = PCI_BAR_UNMAPPED;
r->size = size;
r->type = type;
-r->memory = NULL;
-
-wmask = ~(size - 1);
-addr = pci_bar(pci_dev, region_num);
-if (region_num == PCI_ROM_SLOT) {
-/* ROM enable bit is writable */
-wmask |= PCI_ROM_ADDRESS_ENABLE;
-}
-pci_set_long(pci_dev->config + addr, type);
-if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
-r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
-pci_set_quad(pci_dev->wmask + addr, wmask);
-pci_set_quad(pci_dev->cmask + addr, ~0ULL);
-} else {
-pci_set_long(pci_dev->wmask + addr, wmask & 0x);
-pci_set_long(pci_dev->cmask + addr, 0x);
+r->enhanced = pci_dev->enhanced;
+r->memory =
