Re: [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions

2021-09-23 Thread eric tang 
Ok, thanks. ^ ^!

Alistair Francis  于2021年9月24日周五 下午12:39写道：

> On Sat, Sep 18, 2021 at 6:20 PM Eric Tang 
> wrote:
> >
> > These patches fixed some issues about srow/sroiw/clzw instructions and
> > add the rest of riscv bitmapip-0.93 instructions except fsri/fsriw &
> > bext/bdep & bextw/bdepw for opcode coding or name conflict problems. The
> > problems had been fixed in riscv bitmapip-1.0 version.
> >
> > I have tested these bitmapip instructions, passed by compare the results
> > that produced by qemu and spike.
> >
> > Please review and give your opinion kindly :)
>
> Hey Eric,
>
> Thanks for the patches!
>
> Unfortunately there is already a series "target/riscv: Update QEmu for
> Zb[abcs] 1.0.0"
> (https://www.mail-archive.com/qemu-devel@nongnu.org/msg839086.html)
> that adds support for the v1.0.0 bit manip extension. That has been
> reviewed and queued to be merged.
>
> If you have fixes or features that apply on top of that please send
> them though :)
>
> Alistair
>
> >
> > Eric Tang (10):
> >   target/riscv: rvb: fixed an error about srow/sroiw instructions
> >   target/riscv: rvb: add carry-less multiply instructions
> >   target/riscv: rvb: add cmix/cmov instructions
> >   target/riscv: rvb: add generalized shuffle instructions
> >   target/riscv: rvb: add crossbar permutation instructions
> >   target/riscv: rvb: add bfp/bfpw instructions
> >   target/riscv: rvb: add CRC instructions
> >   target/riscv: rvb: add bit-matrix instructions
> >   target/riscv: rvb: fixed an issue about clzw instruction
> >   target/riscv: rvb: add funnel shfit instructions
> >
> >  target/riscv/bitmanip_helper.c  | 351 
> >  target/riscv/helper.h   |  28 ++
> >  target/riscv/insn32.decode  |  36 +++
> >  target/riscv/insn_trans/trans_rvb.c.inc | 215 ++-
> >  target/riscv/translate.c|  14 +
> >  5 files changed, 641 insertions(+), 3 deletions(-)
> >
> > --
> > 2.17.1
> >
> >
>

[RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index fa4597b44b..35f7b0926b 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -245,3 +245,30 @@ target_ulong HELPER(xperm_w)(target_ulong rs1, 
target_ulong rs2)
 {
 return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS);
 }
+
+static target_ulong do_bfp(target_ulong rs1,
+   target_ulong rs2,
+   int bits)
+{
+target_ulong cfg = rs2 >> (bits / 2);
+if ((cfg >> 30) == 2) {
+cfg = cfg >> 16;
+}
+int len = (cfg >> 8) & ((bits / 2) - 1);
+int off = cfg & (bits - 1);
+len = len ? len : (bits / 2);
+target_ulong mask = ~(~(target_ulong)0 << len) << off;
+target_ulong data = rs2 << off;
+
+return (data & mask) | (rs1 & ~mask);
+}
+
+target_ulong HELPER(bfp)(target_ulong rs1, target_ulong rs2)
+{
+return do_bfp(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
+{
+return do_bfp(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ac57982e4f..474b1add63 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -74,6 +74,8 @@ DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 60b56dbf95..5d354f63a2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -702,6 +702,7 @@ unshfl 100 .. 101 . 0110011 @r
 xperm_n0010100 .. 010 . 0110011 @r
 xperm_b0010100 .. 100 . 0110011 @r
 xperm_h0010100 .. 110 . 0110011 @r
+bfp0100100 .. 111 . 0110011 @r
 cmix   .11 .. 001 . 0110011 @r4
 cmov   .11 .. 101 . 0110011 @r4
 
@@ -741,6 +742,7 @@ add_uw 100 .. 000 . 0111011 @r
 shflw  100 .. 001 . 0111011 @r
 unshflw100 .. 101 . 0111011 @r
 xperm_w0010100 .. 000 . 0110011 @r
+bfpw   0100100 .. 111 . 0111011 @r
 
 bsetiw 0010100 .. 001 . 0011011 @sh5
 bclriw 0100100 .. 001 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index e869d82c8f..1997d33008 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -369,6 +369,12 @@ static bool trans_xperm_h(DisasContext *ctx, arg_xperm_h 
*a)
 return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_h);
 }
 
+static bool trans_bfp(DisasContext *ctx, arg_bfp *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_bfp);
+}
+
 #define GEN_TRANS_CLMUL(NAME)   \
 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
 {   \
@@ -775,3 +781,11 @@ static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w 
*a)
 ctx->w = true;
 return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_w);
 }
+
+static bool trans_bfpw(DisasContext *ctx, arg_bfpw *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+ctx->w = true;
+return gen_arith(ctx, a, EXT_NONE, gen_helper_bfpw);
+}
-- 
2.17.1

[RFC 10/10] target/riscv: rvb: add funnel shfit instructions

2021-09-18 Thread Eric Tang 
Add funnel shfit instructions except fsri/fsriw for opcode ecoding
reason.

Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e936444c12..08a2fbb376 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -124,6 +124,43 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong 
rs2)
 return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
 }
 
+static target_ulong do_fsl(target_ulong rs1,
+   target_ulong rs2,
+   target_ulong rs3,
+   int bits)
+{
+int shamt = rs2 & ((2 * bits) - 1);
+target_ulong a = rs1, b = rs3;
+
+if (shamt >= bits) {
+shamt -= bits;
+a = rs3;
+b = rs1;
+}
+
+return shamt ? (a << shamt) | (b >> (bits - shamt)) : a;
+}
+
+target_ulong HELPER(fsl)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+return do_fsl(rs1, rs2, rs3, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(fsr)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+return do_fsl(rs1, -rs2, rs3, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(fslw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+return do_fsl(rs1, rs2, rs3, 32);
+}
+
+target_ulong HELPER(fsrw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
+{
+return do_fsl(rs1, -rs2, rs3, 32);
+}
+
 static target_ulong shuffle_stage(target_ulong src,
   uint64_t maskl,
   uint64_t maskr,
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8c8fb71bb4..619f635b6d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -87,6 +87,10 @@ DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fslw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(fsrw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 73f956486b..65e574709a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -713,6 +713,8 @@ xperm_h0010100 .. 110 . 0110011 @r
 bfp0100100 .. 111 . 0110011 @r
 cmix   .11 .. 001 . 0110011 @r4
 cmov   .11 .. 101 . 0110011 @r4
+fsl.10 .. 001 . 0110011 @r4
+fsr.10 .. 101 . 0110011 @r4
 
 bseti  00101. ... 001 . 0010011 @sh
 bclri  01001. ... 001 . 0010011 @sh
@@ -754,6 +756,8 @@ xperm_w0010100 .. 000 . 0110011 @r
 bfpw   0100100 .. 111 . 0111011 @r
 bmator 100 .. 011 . 0110011 @r
 bmatxor0100100 .. 011 . 0110011 @r
+fslw   .10 .. 001 . 0111011 @r4
+fsrw   .10 .. 101 . 0111011 @r4
 
 bsetiw 0010100 .. 001 . 0011011 @sh5
 bclriw 0100100 .. 001 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 4523a5cd4c..5315baa185 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -428,6 +428,18 @@ static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
 return gen_quat(ctx, a, EXT_NONE, gen_cmov);
 }
 
+static bool trans_fsl(DisasContext *ctx, arg_fsl *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_quat(ctx, a, EXT_NONE, gen_helper_fsl);
+}
+
+static bool trans_fsr(DisasContext *ctx, arg_fsr *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_quat(ctx, a, EXT_NONE, gen_helper_fsr);
+}
+
 #define GEN_SHADD(SHAMT)   \
 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 {  \
@@ -827,3 +839,19 @@ static bool trans_bmator(DisasContext *ctx, arg_bmator *a)
 REQUIRE_EXT(ctx, RVB);
 return gen_arith(ctx, a, EXT_NONE, gen_helper_bmator);
 }
+
+static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+ctx->w = true;
+return gen_quat(ctx, a, EXT_ZERO, gen_helper_fslw);
+}
+
+static bool trans_fsrw(DisasContext *ctx, arg_fsrw *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+ctx->w = true;
+return gen_quat(ctx, a, EXT_ZERO, gen_helper_fsrw);
+}
-- 
2.17.1

[RFC 05/10] target/riscv: rvb: add crossbar permutation instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 19c64756c5..fa4597b44b 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -205,3 +205,43 @@ target_ulong HELPER(unshflw)(target_ulong rs1, 
target_ulong rs2)
 {
 return do_unshfl(rs1, rs2, 32);
 }
+
+static target_ulong do_xperm(target_ulong rs1,
+ target_ulong rs2,
+ int sz_log2,
+ int bits)
+{
+target_ulong pos = 0;
+target_ulong r = 0;
+target_ulong sz = 1LL << sz_log2;
+target_ulong mask = (1LL << sz) - 1;
+int i;
+for (i = 0; i < bits; i += sz) {
+pos = ((rs2 >> i) & mask) << sz_log2;
+if (pos < bits) {
+r |= ((rs1 >> pos) & mask) << i;
+}
+}
+
+return r;
+}
+
+target_ulong HELPER(xperm_n)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(xperm_b)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 3, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(xperm_h)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 4, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2)
+{
+return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 015526faf0..ac57982e4f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -70,6 +70,10 @@ DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e70a38a5c6..60b56dbf95 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -699,6 +699,9 @@ clmulh 101 .. 011 . 0110011 @r
 clmulr 101 .. 010 . 0110011 @r
 shfl   100 .. 001 . 0110011 @r
 unshfl 100 .. 101 . 0110011 @r
+xperm_n0010100 .. 010 . 0110011 @r
+xperm_b0010100 .. 100 . 0110011 @r
+xperm_h0010100 .. 110 . 0110011 @r
 cmix   .11 .. 001 . 0110011 @r4
 cmov   .11 .. 101 . 0110011 @r4
 
@@ -737,6 +740,7 @@ sh3add_uw  001 .. 110 . 0111011 @r
 add_uw 100 .. 000 . 0111011 @r
 shflw  100 .. 001 . 0111011 @r
 unshflw100 .. 101 . 0111011 @r
+xperm_w0010100 .. 000 . 0110011 @r
 
 bsetiw 0010100 .. 001 . 0011011 @sh5
 bclriw 0100100 .. 001 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index cbd48b4c8c..e869d82c8f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -351,6 +351,24 @@ static bool trans_unshfli(DisasContext *ctx, arg_unshfli 
*a)
 return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_helper_unshfl);
 }
 
+static bool trans_xperm_n(DisasContext *ctx, arg_xperm_n *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_n);
+}
+
+static bool trans_xperm_b(DisasContext *ctx, arg_xperm_b *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_b);
+}
+
+static bool trans_xperm_h(DisasContext *ctx, arg_xperm_h *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_h);
+}
+
 #define GEN_TRANS_CLMUL(NAME)   \
 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
 {   \
@@ -749,3 +767,11 @@ static bool trans_unshflw(DisasContext *ctx, arg_unshflw 
*a)
 ctx->w = true;
 return gen_arith(ctx, a, EXT_ZERO, gen_helper_unshflw);
 }
+
+static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+ctx->w = true;
+return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_w);
+}
-- 
2.17.1

[RFC 08/10] target/riscv: rvb: add bit-matrix instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 469145ffa9..e936444c12 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -327,3 +327,78 @@ target_ulong HELPER(crc32c_d)(target_ulong rs1)
 {
 return do_crc32c(rs1, 64);
 }
+
+static target_ulong do_bmatflip(target_ulong rs1,
+int bits)
+{
+target_ulong x = rs1;
+for (int i = 0; i < 3; i++) {
+x = do_shfl(x, 31, bits);
+}
+return x;
+}
+
+static target_ulong do_bmatxor(target_ulong rs1,
+   target_ulong rs2,
+   int bits)
+{
+int i;
+uint8_t u[8];
+uint8_t v[8];
+uint64_t x = 0;
+
+target_ulong rs2t = do_bmatflip(rs2, bits);
+
+for (i = 0; i < 8; i++) {
+u[i] = rs1 >> (i * 8);
+v[i] = rs2t >> (i * 8);
+}
+
+for (int i = 0; i < 64; i++) {
+if (__builtin_popcount(u[i / 8] & v[i % 8]) & 1) {
+x |= 1LL << i;
+}
+}
+
+return x;
+}
+
+static target_ulong do_bmator(target_ulong rs1,
+  target_ulong rs2,
+  int bits)
+{
+int i;
+uint8_t u[8];
+uint8_t v[8];
+uint64_t x = 0;
+
+target_ulong rs2t = do_bmatflip(rs2, bits);
+
+for (i = 0; i < 8; i++) {
+u[i] = rs1 >> (i * 8);
+v[i] = rs2t >> (i * 8);
+}
+
+for (int i = 0; i < 64; i++) {
+if ((u[i / 8] & v[i % 8]) != 0) {
+x |= 1LL << i;
+}
+}
+
+return x;
+}
+
+target_ulong HELPER(bmatflip)(target_ulong rs1)
+{
+return do_bmatflip(rs1, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(bmatxor)(target_ulong rs1, target_ulong rs2)
+{
+return do_bmatxor(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(bmator)(target_ulong rs1, target_ulong rs2)
+{
+return do_bmator(rs1, rs2, TARGET_LONG_BITS);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9654d6f7a7..8c8fb71bb4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,6 +84,9 @@ DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b08e38823b..73f956486b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -730,6 +730,7 @@ unshfli10 ... 101 . 0010011 @sh6
 clzw   011 0 . 001 . 0011011 @r2
 ctzw   011 1 . 001 . 0011011 @r2
 cpopw  011 00010 . 001 . 0011011 @r2
+bmatflip   011 00011 . 001 . 0010011 @r2
 
 packw  100 .. 100 . 0111011 @r
 packuw 0100100 .. 100 . 0111011 @r
@@ -751,6 +752,8 @@ shflw  100 .. 001 . 0111011 @r
 unshflw100 .. 101 . 0111011 @r
 xperm_w0010100 .. 000 . 0110011 @r
 bfpw   0100100 .. 111 . 0111011 @r
+bmator 100 .. 011 . 0110011 @r
+bmatxor0100100 .. 011 . 0110011 @r
 
 bsetiw 0010100 .. 001 . 0011011 @sh5
 bclriw 0100100 .. 001 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 0d734bfd10..39ca5a573f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -805,3 +805,24 @@ static bool trans_bfpw(DisasContext *ctx, arg_bfpw *a)
 ctx->w = true;
 return gen_arith(ctx, a, EXT_NONE, gen_helper_bfpw);
 }
+
+static bool trans_bmatflip(DisasContext *ctx, arg_bmatflip *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+return gen_unary(ctx, a, EXT_NONE, gen_helper_bmatflip);
+}
+
+static bool trans_bmatxor(DisasContext *ctx, arg_bmatxor *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_bmatxor);
+}
+
+static bool trans_bmator(DisasContext *ctx, arg_bmator *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_EXT(ctx, RVB);
+return gen_arith(ctx, a, EXT_NONE, gen_helper_bmator);
+}
-- 
2.17.1

[RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 39ca5a573f..4523a5cd4c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -456,7 +456,7 @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-tcg_gen_clzi_tl(ret, ret, 64);
+tcg_gen_clzi_tl(ret, arg1, 64);
 tcg_gen_subi_tl(ret, ret, 32);
 }
 
@@ -464,6 +464,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
 REQUIRE_64BIT(ctx);
 REQUIRE_EXT(ctx, RVB);
+ctx->w = true;
 return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
 }
 
-- 
2.17.1

[RFC 02/10] target/riscv: rvb: add carry-less multiply instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 5b2f795d03..e31cf582ca 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -88,3 +88,38 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong 
rs2)
 {
 return do_gorc(rs1, rs2, 32);
 }
+
+#define DO_CLMULA(NAME, NUM, BODY)  \
+static target_ulong do_##NAME(target_ulong rs1, \
+  target_ulong rs2, \
+  int bits) \
+{   \
+target_ulong x = 0; \
+int i;  \
+\
+for (i = NUM; i < bits; i++) {  \
+if ((rs2 >> i) & 1) {   \
+x ^= BODY;  \
+}   \
+}   \
+return x;   \
+}
+
+DO_CLMULA(clmul, 0, (rs1 << i))
+DO_CLMULA(clmulh, 1, (rs1 >> (bits - i)))
+DO_CLMULA(clmulr, 0, (rs1 >> (bits - i - 1)))
+
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
+{
+return do_clmul(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(clmulh)(target_ulong rs1, target_ulong rs2)
+{
+return do_clmulh(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+{
+return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 460eee9988..7cbcee48e6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -63,6 +63,9 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2cd921d51c..9eff9d5f5c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -690,6 +690,9 @@ gorc   0010100 .. 101 . 0110011 @r
 sh1add 001 .. 010 . 0110011 @r
 sh2add 001 .. 100 . 0110011 @r
 sh3add 001 .. 110 . 0110011 @r
+clmul  101 .. 001 . 0110011 @r
+clmulh 101 .. 011 . 0110011 @r
+clmulr 101 .. 010 . 0110011 @r
 
 bseti  00101. ... 001 . 0010011 @sh
 bclri  01001. ... 001 . 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 96b6fcb41d..1d29de 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -321,6 +321,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
 return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
+#define GEN_TRANS_CLMUL(NAME)   \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
+{   \
+REQUIRE_EXT(ctx, RVB);  \
+return gen_arith(ctx, a, EXT_NONE, gen_helper_##NAME);  \
+}
+
+GEN_TRANS_CLMUL(clmul)
+GEN_TRANS_CLMUL(clmulh)
+GEN_TRANS_CLMUL(clmulr)
+
 #define GEN_SHADD(SHAMT)   \
 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 {  \
-- 
2.17.1

[RFC 07/10] target/riscv: rvb: add CRC instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 35f7b0926b..469145ffa9 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -272,3 +272,58 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong 
rs2)
 {
 return do_bfp(rs1, rs2, 32);
 }
+
+#define DO_CRC(NAME, VALUE)  \
+static target_ulong do_##NAME(target_ulong rs1,  \
+  int nbits) \
+{\
+int i;   \
+target_ulong x = rs1;\
+for (i = 0; i < nbits; i++) {\
+x = (x >> 1) ^ ((VALUE) & ~((x & 1) - 1));   \
+}\
+return x;\
+}
+
+DO_CRC(crc32, 0xEDB88320)
+DO_CRC(crc32c, 0x82F63B78)
+
+target_ulong HELPER(crc32_b)(target_ulong rs1)
+{
+return do_crc32(rs1, 8);
+}
+
+target_ulong HELPER(crc32_h)(target_ulong rs1)
+{
+return do_crc32(rs1, 16);
+}
+
+target_ulong HELPER(crc32_w)(target_ulong rs1)
+{
+return do_crc32(rs1, 32);
+}
+
+target_ulong HELPER(crc32_d)(target_ulong rs1)
+{
+return do_crc32(rs1, 64);
+}
+
+target_ulong HELPER(crc32c_b)(target_ulong rs1)
+{
+return do_crc32c(rs1, 8);
+}
+
+target_ulong HELPER(crc32c_h)(target_ulong rs1)
+{
+return do_crc32c(rs1, 16);
+}
+
+target_ulong HELPER(crc32c_w)(target_ulong rs1)
+{
+return do_crc32c(rs1, 32);
+}
+
+target_ulong HELPER(crc32c_d)(target_ulong rs1)
+{
+return do_crc32c(rs1, 64);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 474b1add63..9654d6f7a7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,6 +76,14 @@ DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_b, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_h, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_w, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32_d, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5d354f63a2..b08e38823b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -670,6 +670,14 @@ ctz011000 01 . 001 . 0010011 @r2
 cpop   011000 10 . 001 . 0010011 @r2
 sext_b 011000 000100 . 001 . 0010011 @r2
 sext_h 011000 000101 . 001 . 0010011 @r2
+crc32_b011 1 . 001 . 0010011 @r2
+crc32_h011 10001 . 001 . 0010011 @r2
+crc32_w011 10010 . 001 . 0010011 @r2
+crc32_d011 10011 . 001 . 0010011 @r2
+crc32c_b   011 11000 . 001 . 0010011 @r2
+crc32c_h   011 11001 . 001 . 0010011 @r2
+crc32c_w   011 11010 . 001 . 0010011 @r2
+crc32c_d   011 11011 . 001 . 0010011 @r2
 
 andn   010 .. 111 . 0110011 @r
 orn010 .. 110 . 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 1997d33008..0d734bfd10 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -386,6 +386,22 @@ GEN_TRANS_CLMUL(clmul)
 GEN_TRANS_CLMUL(clmulh)
 GEN_TRANS_CLMUL(clmulr)
 
+#define GEN_TRANS_CRC(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
+{   \
+REQUIRE_EXT(ctx, RVB);  \
+return gen_unary(ctx, a, EXT_NONE, gen_helper_##NAME);  \
+}   \
+
+GEN_TRANS_CRC(crc32_b)
+GEN_TRANS_CRC(crc32_h)
+GEN_TRANS_CRC(crc32_w)
+GEN_TRANS_CRC(crc32_d)
+GEN_TRANS_CRC(crc32c_b)
+GEN_TRANS_CRC(crc32c_h)
+GEN_TRANS_CRC(crc32c_w)
+GEN_TRANS_CRC(crc32c_d)
+
 static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
 {
 tcg_gen_and_tl(arg1, arg1, arg2);
-- 
2.17.1

[RFC 04/10] target/riscv: rvb: add generalized shuffle instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e31cf582ca..19c64756c5 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -123,3 +123,85 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong 
rs2)
 {
 return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
 }
+
+static target_ulong shuffle_stage(target_ulong src,
+  uint64_t maskl,
+  uint64_t maskr,
+  int n)
+{
+target_ulong x = src & ~(maskl | maskr);
+x |= ((src << n) & maskl) | ((src >> n) & maskr);
+return x;
+}
+
+static target_ulong do_shfl(target_ulong rs1,
+target_ulong rs2,
+int bits)
+{
+target_ulong x = rs1;
+int shamt = rs2 & ((bits - 1) >> 1);
+
+if (shamt & 16) {
+x = shuffle_stage(x, 0xLL, 0xLL, 16);
+}
+if (shamt & 8) {
+x = shuffle_stage(x, 0x00ff00ffLL, 0xff00ff00LL, 8);
+}
+if (shamt & 4) {
+x = shuffle_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
+}
+if (shamt & 2) {
+x = shuffle_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
+}
+if (shamt & 1) {
+x = shuffle_stage(x, 0xLL, 0xLL, 1);
+}
+
+return x;
+}
+
+static target_ulong do_unshfl(target_ulong rs1,
+  target_ulong rs2,
+  int bits)
+{
+target_ulong x = rs1;
+int shamt = rs2 & ((bits - 1) >> 1);
+
+if (shamt & 1) {
+x = shuffle_stage(x, 0xLL, 0xLL, 1);
+}
+if (shamt & 2) {
+x = shuffle_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
+}
+if (shamt & 4) {
+x = shuffle_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
+}
+if (shamt & 8) {
+x = shuffle_stage(x, 0x00ff00ffLL, 0xff00ff00LL, 8);
+}
+if (shamt & 16) {
+x = shuffle_stage(x, 0xLL, 0xLL, 16);
+}
+
+return x;
+}
+
+target_ulong HELPER(shfl)(target_ulong rs1, target_ulong rs2)
+{
+return do_shfl(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(unshfl)(target_ulong rs1, target_ulong rs2)
+{
+return do_unshfl(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(shflw)(target_ulong rs1, target_ulong rs2)
+{
+return do_shfl(rs1, rs2, 32);
+}
+
+target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2)
+{
+return do_unshfl(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7cbcee48e6..015526faf0 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,10 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 989ea3c602..e70a38a5c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@
 %rd7:5
 %sh5   20:5
 
+%sh620:6
 %sh720:7
 %csr20:12
 %rm 12:3
@@ -63,6 +64,7 @@
 @j     . ... &j  imm=%imm_j  
%rd
 
 @sh  ..  .. .  ... . ... &shift  shamt=%sh7 %rs1 
%rd
+@sh6 ..  .. .  ... . ... &shift  shamt=%sh6 %rs1 
%rd
 @csr    .  ... . ...   %csr %rs1 
%rd
 
 @atom_ld . aq:1 rl:1 .  . ... &atomic rs2=0 %rs1 
%rd
@@ -695,6 +697,8 @@ sh3add 001 .. 110 . 0110011 @r
 clmul  101 .. 001 . 0110011 @r
 clmulh 101 .. 011 . 0110011 @r
 clmulr 101 .. 010 . 0110011 @r
+shfl   100 .. 001 . 0110011 @r
+unshfl 100 .. 101 . 0110011 @r
 cmix   .11 .. 001 . 0110011 @r4
 cmov   .11 .. 101 . 0110011 @r4
 
@@ -707,6 +711,8 @@ sroi   00100. ... 101 . 0010011 @sh
 rori   01100. ... 101 . 0010011 @sh
 grevi  01101. ... 101 . 0010011 @sh
 gorci  00101. ... 101 . 0010011 @sh
+shfli  10 ... 001 . 0010011 @sh6
+unshfli10 ... 101 . 0010011 @sh6
 
 # *** RV64B

[RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions

2021-09-18 Thread Eric Tang 
According to spec, these instructions ignore the upper 32 bit of
their input and sign-extend their 32 bit output values. Fixed the
output's error when their input values greater than 0x.

Signed-off-by: Eric Tang 

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..96b6fcb41d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -484,12 +484,32 @@ static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
 return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
 }
 
+static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+TCGv_i32 t1 = tcg_temp_new_i32();
+TCGv_i32 t2 = tcg_temp_new_i32();
+
+/* truncate to 32-bits */
+tcg_gen_trunc_tl_i32(t1, arg1);
+tcg_gen_trunc_tl_i32(t2, arg2);
+
+tcg_gen_not_i32(t1, t1);
+tcg_gen_shr_i32(t1, t1, t2);
+tcg_gen_not_i32(t1, t1);
+
+/* sign-extend 64-bits */
+tcg_gen_ext_i32_tl(ret, t1);
+
+tcg_temp_free_i32(t1);
+tcg_temp_free_i32(t2);
+}
+
 static bool trans_srow(DisasContext *ctx, arg_srow *a)
 {
 REQUIRE_64BIT(ctx);
 REQUIRE_EXT(ctx, RVB);
 ctx->w = true;
-return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+return gen_shift(ctx, a, EXT_ZERO, gen_srow);
 }
 
 static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
@@ -497,7 +517,7 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
 REQUIRE_64BIT(ctx);
 REQUIRE_EXT(ctx, RVB);
 ctx->w = true;
-return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
+return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_srow);
 }
 
 static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-- 
2.17.1

[RFC 03/10] target/riscv: rvb: add cmix/cmov instructions

2021-09-18 Thread Eric Tang 
Signed-off-by: Eric Tang 

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9eff9d5f5c..989ea3c602 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -43,6 +43,7 @@
 &rrd rs1 rs2
 &r2   rd rs1
 &r2_s rs1 rs2
+&r4   rd rs1 rs2 rs3
 &simm rs1 rs2
 &uimm rd
 &shift shamt rs1 rd
@@ -82,6 +83,7 @@
 @r_wdvm  . wd:1 vm:1 . . ... . ... &rwdvm %rs2 %rs1 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 @r2_s...   . . ... . ... %rs2 %rs1
+@r4  . ..  . . ... . ... &r4 %rs3 %rs2 %rs1 %rd
 
 @hfence_gvma ... . .   ... . ... %rs2 %rs1
 @hfence_vvma ... . .   ... . ... %rs2 %rs1
@@ -693,6 +695,8 @@ sh3add 001 .. 110 . 0110011 @r
 clmul  101 .. 001 . 0110011 @r
 clmulh 101 .. 011 . 0110011 @r
 clmulr 101 .. 010 . 0110011 @r
+cmix   .11 .. 001 . 0110011 @r4
+cmov   .11 .. 101 . 0110011 @r4
 
 bseti  00101. ... 001 . 0010011 @sh
 bclri  01001. ... 001 . 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 1d29de..ebcbb341cb 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -332,6 +332,32 @@ GEN_TRANS_CLMUL(clmul)
 GEN_TRANS_CLMUL(clmulh)
 GEN_TRANS_CLMUL(clmulr)
 
+static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+tcg_gen_and_tl(arg1, arg1, arg2);
+tcg_gen_not_tl(arg2, arg2);
+tcg_gen_and_tl(arg3, arg3, arg2);
+tcg_gen_or_tl(ret, arg1, arg3);
+}
+
+static void gen_cmov(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+TCGv zero = tcg_const_tl(0);
+tcg_gen_movcond_tl(TCG_COND_NE, ret, arg2, zero, arg1, arg3);
+}
+
+static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_quat(ctx, a, EXT_NONE, gen_cmix);
+}
+
+static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
+{
+REQUIRE_EXT(ctx, RVB);
+return gen_quat(ctx, a, EXT_NONE, gen_cmov);
+}
+
 #define GEN_SHADD(SHAMT)   \
 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 {  \
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..0a62666ce7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -395,6 +395,20 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, 
DisasExtend ext,
 return true;
 }
 
+static bool gen_quat(DisasContext *ctx, arg_r4 *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv, TCGv))
+{
+TCGv dest = dest_gpr(ctx, a->rd);
+TCGv src1 = get_gpr(ctx, a->rs1, ext);
+TCGv src2 = get_gpr(ctx, a->rs2, ext);
+TCGv src3 = get_gpr(ctx, a->rs3, ext);
+
+func(dest, src1, src2, src3);
+
+gen_set_gpr(ctx, a->rd, dest);
+return true;
+}
+
 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
  void (*func)(TCGv, TCGv, target_long))
 {
-- 
2.17.1

[RFC 00/10] add the rest of riscv bitmapip-0.93 instructions

2021-09-18 Thread Eric Tang 
These patches fixed some issues about srow/sroiw/clzw instructions and
add the rest of riscv bitmapip-0.93 instructions except fsri/fsriw &
bext/bdep & bextw/bdepw for opcode coding or name conflict problems. The
problems had been fixed in riscv bitmapip-1.0 version.

I have tested these bitmapip instructions, passed by compare the results
that produced by qemu and spike.

Please review and give your opinion kindly :)

Eric Tang (10):
  target/riscv: rvb: fixed an error about srow/sroiw instructions
  target/riscv: rvb: add carry-less multiply instructions
  target/riscv: rvb: add cmix/cmov instructions
  target/riscv: rvb: add generalized shuffle instructions
  target/riscv: rvb: add crossbar permutation instructions
  target/riscv: rvb: add bfp/bfpw instructions
  target/riscv: rvb: add CRC instructions
  target/riscv: rvb: add bit-matrix instructions
  target/riscv: rvb: fixed an issue about clzw instruction
  target/riscv: rvb: add funnel shfit instructions

 target/riscv/bitmanip_helper.c  | 351 
 target/riscv/helper.h   |  28 ++
 target/riscv/insn32.decode  |  36 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 215 ++-
 target/riscv/translate.c|  14 +
 5 files changed, 641 insertions(+), 3 deletions(-)

-- 
2.17.1