[Qemu-devel] [PATCH] unicore32-softmmu: Add is_default setting for puv3 machine
From: Guan Xuetao
This patch sets is_default to 1 for puv3 machine, so that
find_default_machine() returns puv3 machine.
Thanks Dunrong for pointing it out.
Cc: Dunrong Huang
Signed-off-by: Guan Xuetao
---
hw/puv3.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/puv3.c b/hw/puv3.c
index 271df97..43f7216 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -119,6 +119,7 @@ static QEMUMachine puv3_machine = {
.name = "puv3",
.desc = "PKUnity Version-3 based on UniCore32",
.init = puv3_init,
+.is_default = 1,
.use_scsi = 0,
};
--
1.7.0.4
[Qemu-devel] [PATCH] unicore32: Split UniCore-F64 instruction helpers from helper.c
From: Guan Xuetao
This patch just splits ucf64 instruction simulation helpers from
helper.c.
Also, two checkpatch warnings are solved.
Signed-off-by: Guan Xuetao
---
target-unicore32/Makefile.objs |2 +
target-unicore32/helper.c | 330 -
target-unicore32/ucf64_helper.c | 344 +++
3 files changed, 346 insertions(+), 330 deletions(-)
create mode 100644 target-unicore32/ucf64_helper.c
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 6af1089..777f01f 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,6 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += ucf64_helper.o
+
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index c0e6f41..5604c9e 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -215,333 +215,3 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
return 1;
}
#endif
-
-/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
- Single precition routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to f64 form. */
-static inline int ucf64_exceptbits_from_host(int host_bits)
-{
-int target_bits = 0;
-
-if (host_bits & float_flag_invalid) {
-target_bits |= UCF64_FPSCR_FLAG_INVALID;
-}
-if (host_bits & float_flag_divbyzero) {
-target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
-}
-if (host_bits & float_flag_overflow) {
-target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
-}
-if (host_bits & float_flag_underflow) {
-target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
-}
-if (host_bits & float_flag_inexact) {
-target_bits |= UCF64_FPSCR_FLAG_INEXACT;
-}
-return target_bits;
-}
-
-uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
-{
-int i;
-uint32_t fpscr;
-
-fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
-i = get_float_exception_flags(&env->ucf64.fp_status);
-fpscr |= ucf64_exceptbits_from_host(i);
-return fpscr;
-}
-
-/* Convert ucf64 exception flags to target form. */
-static inline int ucf64_exceptbits_to_host(int target_bits)
-{
-int host_bits = 0;
-
-if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
-host_bits |= float_flag_invalid;
-}
-if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
-host_bits |= float_flag_divbyzero;
-}
-if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
-host_bits |= float_flag_overflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
-host_bits |= float_flag_underflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
-host_bits |= float_flag_inexact;
-}
-return host_bits;
-}
-
-void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
-{
-int i;
-uint32_t changed;
-
-changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
-env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
-
-changed ^= val;
-if (changed & (UCF64_FPSCR_RND_MASK)) {
-i = UCF64_FPSCR_RND(val);
-switch (i) {
-case 0:
-i = float_round_nearest_even;
-break;
-case 1:
-i = float_round_to_zero;
-break;
-case 2:
-i = float_round_up;
-break;
-case 3:
-i = float_round_down;
-break;
-default: /* 100 and 101 not implement */
-cpu_abort(env, "Unsupported UniCore-F64 round mode");
-}
-set_float_rounding_mode(i, &env->ucf64.fp_status);
-}
-
-i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
-set_float_exception_flags(i, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_add(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_add(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_sub(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_sub(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_mul(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_mul(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_div(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_div(a, b, &env->ucf
[Qemu-devel] [PULL] UniCore32 PUV3 machine support
are available in the git repository at: git://github.com/gxt/QEMU.git unicore32 Andreas Färber (1): target-unicore32: Drop UC32_CPUID macros Guan Xuetao (13): unicore32-softmmu: Add unicore32-softmmu build support unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable unicore32-softmmu: Implement softmmu specific functions unicore32-softmmu: Make sure that kernel can access user space unicore32-softmmu: Add puv3 soc/board support unicore32-softmmu: Add puv3 interrupt support unicore32-softmmu: Add puv3 ostimer support unicore32-softmmu: Add puv3 gpio support unicore32-softmmu: Add puv3 pm support unicore32-softmmu: Add puv3 dma support unicore32-softmmu: Add ps2 support unicore32-softmmu: Add maintainer information for UniCore32 machine MAINTAINERS |8 + arch_init.c |2 + arch_init.h |1 + configure |1 + cpu-exec.c|1 + default-configs/unicore32-softmmu.mak |4 + hw/Makefile.objs |7 + hw/puv3.c | 130 hw/puv3.h | 49 ++ hw/puv3_dma.c | 109 + hw/puv3_gpio.c| 141 + hw/puv3_intc.c| 135 + hw/puv3_ost.c | 151 +++ hw/puv3_pm.c | 149 ++ hw/unicore32/Makefile.objs|6 + linux-user/main.c |3 +- target-unicore32/Makefile.objs|2 +- target-unicore32/cpu.c| 19 ++- target-unicore32/cpu.h| 18 +-- target-unicore32/helper.c | 180 ++ target-unicore32/helper.h | 17 +-- target-unicore32/machine.c| 23 +++ target-unicore32/op_helper.c | 44 ++- target-unicore32/softmmu.c| 267 + target-unicore32/translate.c | 116 +-- 25 files changed, 1509 insertions(+), 74 deletions(-) create mode 100644 default-configs/unicore32-softmmu.mak create mode 100644 hw/puv3.c create mode 100644 hw/puv3.h create mode 100644 hw/puv3_dma.c create mode 100644 hw/puv3_gpio.c create mode 100644 hw/puv3_intc.c create mode 100644 hw/puv3_ost.c create mode 100644 hw/puv3_pm.c create mode 100644 hw/unicore32/Makefile.objs create mode 100644 target-unicore32/machine.c create mode 100644 target-unicore32/softmmu.c
[Qemu-devel] [PATCHv2 2/2] unicore32: Disintegrate cpu_dump_state_ucf64 function
From: Guan Xuetao
This patch disintegrates cpu_dump_state_ucf64 function from cpu_dump_state.
Since of tedious output, we close this dump in its default state.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 41 +
1 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 5ee3a59..c74c49a 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2139,11 +2139,11 @@ static const char *cpu_mode_names[16] = {
};
#define UCF64_DUMP_STATE
-void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function
cpu_fprintf,
-int flags)
+#ifdef UCF64_DUMP_STATE
+static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
{
int i;
-#ifdef UCF64_DUMP_STATE
union {
uint32_t i;
float s;
@@ -2155,7 +2155,28 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
float64 f64;
double d;
} d0;
+
+for (i = 0; i < 16; i++) {
+d.d = env->ucf64.regs[i];
+s0.i = d.l.lower;
+s1.i = d.l.upper;
+d0.f64 = d.d;
+cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
+i * 2, (int)s0.i, s0.s,
+i * 2 + 1, (int)s1.i, s1.s);
+cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
+i, (uint64_t)d0.f64, d0.d);
+}
+cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
+}
+#else
+#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
#endif
+
+void cpu_dump_state(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
+{
+int i;
uint32_t psr;
for (i = 0; i < 32; i++) {
@@ -2175,19 +2196,7 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
psr & (1 << 28) ? 'V' : '-',
cpu_mode_names[psr & 0xf]);
-#ifdef UCF64_DUMP_STATE
-for (i = 0; i < 16; i++) {
-d.d = env->ucf64.regs[i];
-s0.i = d.l.lower;
-s1.i = d.l.upper;
-d0.f64 = d.d;
-cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%" PRIx64
"(%8g)\n",
-i * 2, (int)s0.i, s0.s,
-i * 2 + 1, (int)s1.i, s1.s,
-i, (uint64_t)d0.f64, d0.d);
-}
-cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
-#endif
+cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
}
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int
pc_pos)
--
1.7.0.4
[Qemu-devel] [PATCHv2 1/2] unicore32: Split UniCore-F64 instruction helpers from helper.c
From: Guan Xuetao
This patch just splits ucf64 instruction simulation helpers from
helper.c.
Also, two checkpatch warnings are solved.
v1->v2: adjust copyright information for new ucf64_helper.c
Signed-off-by: Guan Xuetao
---
target-unicore32/Makefile.objs |2 +
target-unicore32/helper.c | 330 -
target-unicore32/ucf64_helper.c | 345 +++
3 files changed, 347 insertions(+), 330 deletions(-)
create mode 100644 target-unicore32/ucf64_helper.c
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 6af1089..777f01f 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,6 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += ucf64_helper.o
+
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f9f1960..d6eb758 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -213,333 +213,3 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
return 1;
}
#endif
-
-/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
- Single precition routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to f64 form. */
-static inline int ucf64_exceptbits_from_host(int host_bits)
-{
-int target_bits = 0;
-
-if (host_bits & float_flag_invalid) {
-target_bits |= UCF64_FPSCR_FLAG_INVALID;
-}
-if (host_bits & float_flag_divbyzero) {
-target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
-}
-if (host_bits & float_flag_overflow) {
-target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
-}
-if (host_bits & float_flag_underflow) {
-target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
-}
-if (host_bits & float_flag_inexact) {
-target_bits |= UCF64_FPSCR_FLAG_INEXACT;
-}
-return target_bits;
-}
-
-uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
-{
-int i;
-uint32_t fpscr;
-
-fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
-i = get_float_exception_flags(&env->ucf64.fp_status);
-fpscr |= ucf64_exceptbits_from_host(i);
-return fpscr;
-}
-
-/* Convert ucf64 exception flags to target form. */
-static inline int ucf64_exceptbits_to_host(int target_bits)
-{
-int host_bits = 0;
-
-if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
-host_bits |= float_flag_invalid;
-}
-if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
-host_bits |= float_flag_divbyzero;
-}
-if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
-host_bits |= float_flag_overflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
-host_bits |= float_flag_underflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
-host_bits |= float_flag_inexact;
-}
-return host_bits;
-}
-
-void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
-{
-int i;
-uint32_t changed;
-
-changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
-env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
-
-changed ^= val;
-if (changed & (UCF64_FPSCR_RND_MASK)) {
-i = UCF64_FPSCR_RND(val);
-switch (i) {
-case 0:
-i = float_round_nearest_even;
-break;
-case 1:
-i = float_round_to_zero;
-break;
-case 2:
-i = float_round_up;
-break;
-case 3:
-i = float_round_down;
-break;
-default: /* 100 and 101 not implement */
-cpu_abort(env, "Unsupported UniCore-F64 round mode");
-}
-set_float_rounding_mode(i, &env->ucf64.fp_status);
-}
-
-i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
-set_float_exception_flags(i, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_add(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_add(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_sub(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_sub(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_mul(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_mul(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_div(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUn
[Qemu-devel] [PATCH] unicore32-softmmu: Add a minimal curses screen support
From: Guan Xuetao
This patch adds a minimal curses screen support for unicore32-softmmu.
We assume 80*30 screen size to minimize the implementation.
Two problems are not solved, but they are innocuous.
1. curses windows will be blank when switching to monitor screen and back
2. backspace is not handled yet
Signed-off-by: Zhang Mengchi
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c | 35 +--
1 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d6eb758..8556beb 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -13,6 +13,7 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
+#include "console.h"
#undef DEBUG_UC32
@@ -186,10 +187,40 @@ uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t
creg, uint32_t cop)
return 0;
}
+#ifdef CONFIG_CURSES
+/*
+ * FIXME:
+ * 1. curses windows will be blank when switching back
+ * 2. backspace is not handled yet
+ */
+static void putc_on_screen(unsigned char ch)
+{
+static WINDOW *localwin;
+static int init;
+
+if (!init) {
+/* Assume 80 * 30 screen to minimize the implementation */
+localwin = newwin(30, 80, 0, 0);
+scrollok(localwin, TRUE);
+init = TRUE;
+}
+
+if ((isprint(ch)) || (ch == '\n') || (ch == '\r')) {
+wprintw(localwin, "%c", ch);
+} else {
+wprintw(localwin, "0x%h", ch);
+}
+
+wrefresh(localwin);
+}
+#else
+#define putc_on_screen(c) do { } while (0)
+#endif
+
void helper_cp1_putc(target_ulong x)
{
-/* TODO: curses display should be added here for screen output. */
-DPRINTF("%c", x);
+putc_on_screen((unsigned char)x); /* Output to screen */
+DPRINTF("%c", x); /* Output to stdout */
}
#endif
--
1.7.0.4
[Qemu-devel] [PATCHv3 2/3] unicore32: Disintegrate cpu_dump_state_ucf64 function
From: Guan Xuetao
This patch disintegrates cpu_dump_state_ucf64 function from cpu_dump_state.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 41 +
1 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 5ee3a59..c74c49a 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2139,11 +2139,11 @@ static const char *cpu_mode_names[16] = {
};
#define UCF64_DUMP_STATE
-void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function
cpu_fprintf,
-int flags)
+#ifdef UCF64_DUMP_STATE
+static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
{
int i;
-#ifdef UCF64_DUMP_STATE
union {
uint32_t i;
float s;
@@ -2155,7 +2155,28 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
float64 f64;
double d;
} d0;
+
+for (i = 0; i < 16; i++) {
+d.d = env->ucf64.regs[i];
+s0.i = d.l.lower;
+s1.i = d.l.upper;
+d0.f64 = d.d;
+cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
+i * 2, (int)s0.i, s0.s,
+i * 2 + 1, (int)s1.i, s1.s);
+cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
+i, (uint64_t)d0.f64, d0.d);
+}
+cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
+}
+#else
+#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
#endif
+
+void cpu_dump_state(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
+{
+int i;
uint32_t psr;
for (i = 0; i < 32; i++) {
@@ -2175,19 +2196,7 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
psr & (1 << 28) ? 'V' : '-',
cpu_mode_names[psr & 0xf]);
-#ifdef UCF64_DUMP_STATE
-for (i = 0; i < 16; i++) {
-d.d = env->ucf64.regs[i];
-s0.i = d.l.lower;
-s1.i = d.l.upper;
-d0.f64 = d.d;
-cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%" PRIx64
"(%8g)\n",
-i * 2, (int)s0.i, s0.s,
-i * 2 + 1, (int)s1.i, s1.s,
-i, (uint64_t)d0.f64, d0.d);
-}
-cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
-#endif
+cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
}
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int
pc_pos)
--
1.7.0.4
[Qemu-devel] [PATCHv3 1/3] unicore32: Split UniCore-F64 instruction helpers from helper.c
From: Guan Xuetao
This patch just splits ucf64 instruction simulation helpers from
helper.c.
Also, two checkpatch warnings are solved.
v1->v2: adjust copyright information for new ucf64_helper.c
Signed-off-by: Guan Xuetao
---
target-unicore32/Makefile.objs |2 +
target-unicore32/helper.c | 330 -
target-unicore32/ucf64_helper.c | 345 +++
3 files changed, 347 insertions(+), 330 deletions(-)
create mode 100644 target-unicore32/ucf64_helper.c
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 6af1089..777f01f 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,6 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += ucf64_helper.o
+
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f9f1960..d6eb758 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -213,333 +213,3 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
return 1;
}
#endif
-
-/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
- Single precition routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to f64 form. */
-static inline int ucf64_exceptbits_from_host(int host_bits)
-{
-int target_bits = 0;
-
-if (host_bits & float_flag_invalid) {
-target_bits |= UCF64_FPSCR_FLAG_INVALID;
-}
-if (host_bits & float_flag_divbyzero) {
-target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
-}
-if (host_bits & float_flag_overflow) {
-target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
-}
-if (host_bits & float_flag_underflow) {
-target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
-}
-if (host_bits & float_flag_inexact) {
-target_bits |= UCF64_FPSCR_FLAG_INEXACT;
-}
-return target_bits;
-}
-
-uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
-{
-int i;
-uint32_t fpscr;
-
-fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
-i = get_float_exception_flags(&env->ucf64.fp_status);
-fpscr |= ucf64_exceptbits_from_host(i);
-return fpscr;
-}
-
-/* Convert ucf64 exception flags to target form. */
-static inline int ucf64_exceptbits_to_host(int target_bits)
-{
-int host_bits = 0;
-
-if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
-host_bits |= float_flag_invalid;
-}
-if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
-host_bits |= float_flag_divbyzero;
-}
-if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
-host_bits |= float_flag_overflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
-host_bits |= float_flag_underflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
-host_bits |= float_flag_inexact;
-}
-return host_bits;
-}
-
-void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
-{
-int i;
-uint32_t changed;
-
-changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
-env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
-
-changed ^= val;
-if (changed & (UCF64_FPSCR_RND_MASK)) {
-i = UCF64_FPSCR_RND(val);
-switch (i) {
-case 0:
-i = float_round_nearest_even;
-break;
-case 1:
-i = float_round_to_zero;
-break;
-case 2:
-i = float_round_up;
-break;
-case 3:
-i = float_round_down;
-break;
-default: /* 100 and 101 not implement */
-cpu_abort(env, "Unsupported UniCore-F64 round mode");
-}
-set_float_rounding_mode(i, &env->ucf64.fp_status);
-}
-
-i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
-set_float_exception_flags(i, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_add(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_add(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_sub(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_sub(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_mul(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_mul(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_div(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUn
[Qemu-devel] [PATCHv3 3/3] unicore32: Close dump-option of cpu_dump_state_ucf64 function
From: Guan Xuetao
Since of tedious output, we close dump-option of cpu_dump_state_ucf64 function.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c74c49a..188bf8c 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2138,7 +2138,7 @@ static const char *cpu_mode_names[16] = {
"UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
};
-#define UCF64_DUMP_STATE
+#undef UCF64_DUMP_STATE
#ifdef UCF64_DUMP_STATE
static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprintf, int flags)
--
1.7.0.4
[Qemu-devel] [PATCHv2] unicore32-softmmu: Add a minimal curses screen support
From: Guan Xuetao
This patch adds a minimal curses screen support for unicore32-softmmu.
We assume 80*30 screen size to minimize the implementation.
Two problems are not solved, but they are innocuous.
1. curses windows will be blank when switching to monitor screen and back
2. backspace is not handled yet
v1->v2: add extra handler for '\r'
Signed-off-by: Zhang Mengchi
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c | 45 +++--
1 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d6eb758..d21e7df 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -13,6 +13,7 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
+#include "console.h"
#undef DEBUG_UC32
@@ -186,10 +187,50 @@ uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t
creg, uint32_t cop)
return 0;
}
+#ifdef CONFIG_CURSES
+/*
+ * FIXME:
+ * 1. curses windows will be blank when switching back
+ * 2. backspace is not handled yet
+ */
+static void putc_on_screen(unsigned char ch)
+{
+static WINDOW *localwin;
+static int init;
+
+if (!init) {
+/* Assume 80 * 30 screen to minimize the implementation */
+localwin = newwin(30, 80, 0, 0);
+scrollok(localwin, TRUE);
+init = TRUE;
+}
+
+if (isprint(ch)) {
+wprintw(localwin, "%c", ch);
+} else {
+switch (ch) {
+case '\n':
+wprintw(localwin, "%c", ch);
+break;
+case '\r':
+/* If '\r' is put before '\n', the curses window will destroy the
+ * last print line. And meanwhile, '\n' implifies '\r' inside. */
+break;
+default: /* Not handled, so just print it hex code */
+wprintw(localwin, "-- 0x%h --", ch);
+}
+}
+
+wrefresh(localwin);
+}
+#else
+#define putc_on_screen(c) do { } while (0)
+#endif
+
void helper_cp1_putc(target_ulong x)
{
-/* TODO: curses display should be added here for screen output. */
-DPRINTF("%c", x);
+putc_on_screen((unsigned char)x); /* Output to screen */
+DPRINTF("%c", x); /* Output to stdout */
}
#endif
--
1.7.0.4
[Qemu-devel] [RESEND PULL REQUEST] UniCore32 PUV3 machine support
are available in the git repository at: git://github.com/gxt/QEMU.git unicore32 Andreas Färber (1): target-unicore32: Drop UC32_CPUID macros Guan Xuetao (14): unicore32-softmmu: Add unicore32-softmmu build support unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable unicore32-softmmu: Implement softmmu specific functions unicore32-softmmu: Make sure that kernel can access user space unicore32-softmmu: Add puv3 soc/board support unicore32-softmmu: Add puv3 interrupt support unicore32-softmmu: Add puv3 ostimer support unicore32-softmmu: Add puv3 gpio support unicore32-softmmu: Add puv3 pm support unicore32-softmmu: Add puv3 dma support unicore32-softmmu: Add ps2 support unicore32-softmmu: Add maintainer information for UniCore32 machine unicore32-softmmu: Add is_default setting for puv3 machine MAINTAINERS |8 + arch_init.c |2 + arch_init.h |1 + configure |1 + cpu-exec.c|1 + default-configs/unicore32-softmmu.mak |4 + hw/Makefile.objs |7 + hw/puv3.c | 131 hw/puv3.h | 49 ++ hw/puv3_dma.c | 109 + hw/puv3_gpio.c| 141 + hw/puv3_intc.c| 135 + hw/puv3_ost.c | 151 +++ hw/puv3_pm.c | 149 ++ hw/unicore32/Makefile.objs|6 + linux-user/main.c |3 +- target-unicore32/Makefile.objs|2 +- target-unicore32/cpu.c| 19 ++- target-unicore32/cpu.h| 18 +-- target-unicore32/helper.c | 180 ++ target-unicore32/helper.h | 17 +-- target-unicore32/machine.c| 23 +++ target-unicore32/op_helper.c | 44 ++- target-unicore32/softmmu.c| 267 + target-unicore32/translate.c | 116 +-- 25 files changed, 1510 insertions(+), 74 deletions(-) create mode 100644 default-configs/unicore32-softmmu.mak create mode 100644 hw/puv3.c create mode 100644 hw/puv3.h create mode 100644 hw/puv3_dma.c create mode 100644 hw/puv3_gpio.c create mode 100644 hw/puv3_intc.c create mode 100644 hw/puv3_ost.c create mode 100644 hw/puv3_pm.c create mode 100644 hw/unicore32/Makefile.objs create mode 100644 target-unicore32/machine.c create mode 100644 target-unicore32/softmmu.c
[Qemu-devel] [PATCH 01/19] unicore32-softmmu: Add unicore32-softmmu build support
From: Guan Xuetao
This patch adds unicore32-softmmu build support, include configure,
makefile, arch_init, and all missing functions needed by softmmu.
Although all missing functions are empty, unicore32-softmmu could
be build successfully.
By 20120804: change QEMU_ARCH_UNICORE32 to 0x4000
Signed-off-by: Guan Xuetao
---
arch_init.c |2 +
arch_init.h |1 +
configure |1 +
default-configs/unicore32-softmmu.mak |1 +
hw/unicore32/Makefile.objs|1 +
target-unicore32/Makefile.objs|2 +-
target-unicore32/helper.c | 27 +++---
target-unicore32/machine.c| 23 +++
target-unicore32/op_helper.c | 24 +++-
target-unicore32/softmmu.c| 39 +
10 files changed, 106 insertions(+), 15 deletions(-)
create mode 100644 default-configs/unicore32-softmmu.mak
create mode 100644 hw/unicore32/Makefile.objs
create mode 100644 target-unicore32/machine.c
create mode 100644 target-unicore32/softmmu.c
diff --git a/arch_init.c b/arch_init.c
index 60823ba..7b65c48 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -91,6 +91,8 @@ int graphic_depth = 15;
#define QEMU_ARCH QEMU_ARCH_SPARC
#elif defined(TARGET_XTENSA)
#define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_UNICORE32)
+#define QEMU_ARCH QEMU_ARCH_UNICORE32
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/arch_init.h b/arch_init.h
index 3dfea3b..547f93c 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -17,6 +17,7 @@ enum {
QEMU_ARCH_SPARC = 2048,
QEMU_ARCH_XTENSA = 4096,
QEMU_ARCH_OPENRISC = 8192,
+QEMU_ARCH_UNICORE32 = 0x4000,
};
extern const uint32_t arch_type;
diff --git a/configure b/configure
index 280726c..efaff00 100755
--- a/configure
+++ b/configure
@@ -935,6 +935,7 @@ sparc64-softmmu \
s390x-softmmu \
xtensa-softmmu \
xtensaeb-softmmu \
+unicore32-softmmu \
"
fi
# the following are Linux specific
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
new file mode 100644
index 000..5f04fe3
--- /dev/null
+++ b/default-configs/unicore32-softmmu.mak
@@ -0,0 +1 @@
+# Default configuration for unicore32-softmmu
diff --git a/hw/unicore32/Makefile.objs b/hw/unicore32/Makefile.objs
new file mode 100644
index 000..b6a3383
--- /dev/null
+++ b/hw/unicore32/Makefile.objs
@@ -0,0 +1 @@
+# For UniCore32 machines and boards
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 2e0e093..6af1089 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,4 @@
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9fe4a37..9b8ff06 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -45,18 +45,26 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifdef CONFIG_USER_ONLY
+void switch_mode(CPUUniCore32State *env, int mode)
+{
+if (mode != ASR_MODE_USER) {
+cpu_abort(env, "Tried to switch out of user mode\n");
+}
+}
+
void do_interrupt(CPUUniCore32State *env)
{
-env->exception_index = -1;
+cpu_abort(env, "NO interrupt in user mode\n");
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
int rw,
- int mmu_idx)
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+ int access_type, int mmu_idx)
{
-env->exception_index = UC32_EXCP_TRAP;
-env->cp0.c4_faultaddr = address;
+cpu_abort(env, "NO mmu fault in user mode\n");
return 1;
}
+#endif
/* These should probably raise undefined insn exceptions. */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
@@ -84,13 +92,6 @@ uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t
insn)
return 0;
}
-void switch_mode(CPUUniCore32State *env, int mode)
-{
-if (mode != ASR_MODE_USER) {
-cpu_abort(env, "Tried to switch out of user mode\n");
-}
-}
-
void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t
val)
{
cpu_abort(env, "banked r29 write\n");
diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
new file mode 100644
index 000..60b2ec1
--- /dev/null
+++ b/target-unicore32/machine.c
@@ -0,0 +1,23 @@
+/*
+ * Generic machine functions for UniCore32 ISA
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is fre
[Qemu-devel] [PATCH 00/19] unicore32: Add unicore32-softmmu support
From: Guan Xuetao These patches implement softmmu support on unicore32 architecture. Based on master branch of qemu, these patches can be fetched from: git://github.com/gxt/QEMU.git for-review UniCore32 CPU is embedded in PKUnity-3 SoC, so we add necessary puv3 devices simulation codes together. Only minimal system control modules are simulated, to make linux kernel boot and busybox run in initramfs. Thanks Andreas Farber, Blue Swirl, Chen Weiren and Dunrong Huang for their priceless advice. Any advice is greatly appreciated. Thanks, Guan Xuetao --- Andreas Färber (1): target-unicore32: Drop UC32_CPUID macros Guan Xuetao (18): unicore32-softmmu: Add unicore32-softmmu build support unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable unicore32-softmmu: Implement softmmu specific functions unicore32-softmmu: Make sure that kernel can access user space unicore32-softmmu: Add puv3 soc/board support unicore32-softmmu: Add puv3 interrupt support unicore32-softmmu: Add puv3 ostimer support unicore32-softmmu: Add puv3 gpio support unicore32-softmmu: Add puv3 pm support unicore32-softmmu: Add puv3 dma support unicore32-softmmu: Add ps2 support unicore32-softmmu: Add maintainer information for UniCore32 machine unicore32-softmmu: Add is_default setting for puv3 machine unicore32: Split UniCore-F64 instruction helpers from helper.c unicore32: Disintegrate cpu_dump_state_ucf64 function unicore32: Close dump-option of cpu_dump_state_ucf64 function unicore32-softmmu: Add a minimal curses screen support MAINTAINERS |8 + arch_init.c |2 + arch_init.h |1 + configure |1 + cpu-exec.c|1 + default-configs/unicore32-softmmu.mak |4 + hw/Makefile.objs |7 + hw/puv3.c | 131 + hw/puv3.h | 49 hw/puv3_dma.c | 109 +++ hw/puv3_gpio.c| 141 + hw/puv3_intc.c| 135 + hw/puv3_ost.c | 151 ++ hw/puv3_pm.c | 149 ++ hw/unicore32/Makefile.objs|6 + linux-user/main.c |3 +- target-unicore32/Makefile.objs|4 +- target-unicore32/cpu.c| 19 +- target-unicore32/cpu.h| 18 +- target-unicore32/helper.c | 511 +++-- target-unicore32/helper.h | 17 +- target-unicore32/machine.c| 23 ++ target-unicore32/op_helper.c | 44 +++- target-unicore32/softmmu.c| 267 + target-unicore32/translate.c | 159 +-- target-unicore32/ucf64_helper.c | 345 ++ 26 files changed, 1904 insertions(+), 401 deletions(-) create mode 100644 default-configs/unicore32-softmmu.mak create mode 100644 hw/puv3.c create mode 100644 hw/puv3.h create mode 100644 hw/puv3_dma.c create mode 100644 hw/puv3_gpio.c create mode 100644 hw/puv3_intc.c create mode 100644 hw/puv3_ost.c create mode 100644 hw/puv3_pm.c create mode 100644 hw/unicore32/Makefile.objs create mode 100644 target-unicore32/machine.c create mode 100644 target-unicore32/softmmu.c create mode 100644 target-unicore32/ucf64_helper.c
[Qemu-devel] [PATCH 03/19] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable
From: Guan Xuetao
This patch initializes the cpuid to exactly correct value because
linux kernel will check it.
In addition, the exception types are specified in proper situations.
Then it could make exceptions generated correctly and timely.
Signed-off-by: Guan Xuetao
---
cpu-exec.c |1 +
linux-user/main.c |3 ++-
target-unicore32/cpu.c | 19 ++-
target-unicore32/cpu.h | 14 --
4 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 543460c..6c4e516 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -447,6 +447,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
+env->exception_index = UC32_EXCP_INTR;
do_interrupt(env);
next_tb = 0;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 53714de..9d921aa 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env)
}
}
break;
-case UC32_EXCP_TRAP:
+case UC32_EXCP_DTRAP:
+case UC32_EXCP_ITRAP:
info.si_signo = SIGSEGV;
info.si_errno = 0;
/* XXX: check env->error_code */
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index de63f58..3425bbe 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -1,7 +1,7 @@
/*
* QEMU UniCore32 CPU
*
- * Copyright (c) 2010-2011 GUAN Xue-tao
+ * Copyright (c) 2010-2012 Guan Xuetao
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This program is free software; you can redistribute it and/or modify
@@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
-env->cp0.c0_cpuid = 0x40010863;
+env->cp0.c0_cpuid = 0x4d000863;
+env->cp0.c0_cachetype = 0x0d152152;
+env->cp0.c1_sys = 0x2000;
+env->cp0.c2_base = 0x0;
+env->cp0.c3_faultstatus = 0x0;
+env->cp0.c4_faultaddr = 0x0;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
-env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
-env->cp0.c0_cachetype = 0x1dd20d2;
-env->cp0.c1_sys = 0x00090078;
}
static void uc32_any_cpu_initfn(Object *obj)
@@ -47,6 +50,7 @@ static void uc32_any_cpu_initfn(Object *obj)
CPUUniCore32State *env = &cpu->env;
env->cp0.c0_cpuid = 0x;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
@@ -65,8 +69,13 @@ static void uc32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
+#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
+#else
+env->uncached_asr = ASR_MODE_PRIV;
+env->regs[31] = 0x0300;
+#endif
tlb_flush(env, 1);
}
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 81c14ff..d14fde5 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -1,15 +1,15 @@
/*
* UniCore32 virtual CPU header
*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation, or (at your option) any
* later version. See the COPYING file in the top-level directory.
*/
-#ifndef __CPU_UC32_H__
-#define __CPU_UC32_H__
+#ifndef QEMU_UNICORE32_CPU_H
+#define QEMU_UNICORE32_CPU_H
#define TARGET_LONG_BITS32
#define TARGET_PAGE_BITS12
@@ -89,8 +89,10 @@ typedef struct CPUUniCore32State {
#define ASR_NZCV(ASR_N | ASR_Z | ASR_C | ASR_V)
#define ASR_RESERVED(~(ASR_M | ASR_I | ASR_NZCV))
-#define UC32_EXCP_PRIV (ASR_MODE_PRIV)
-#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
+#define UC32_EXCP_PRIV (1)
+#define UC32_EXCP_ITRAP (2)
+#define UC32_EXCP_DTRAP (3)
+#define UC32_EXCP_INTR (4)
/* Return the current ASR value. */
target_ulong cpu_asr_read(CPUUniCore32State *env1);
@@ -189,4 +191,4 @@ static inline bool cpu_has_work(CPUUniCore32State *env)
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
-#endif /* __CPU_UC32_H__ */
+#endif /* QEMU_UNICORE32_CPU_H */
--
1.7.0.4
[Qemu-devel] [PATCH 10/19] unicore32-softmmu: Add puv3 gpio support
From: Guan Xuetao
This patch adds puv3 gpio (General Purpose Input/Output) support,
include gpio device simulation and its interrupt support.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|6 ++
hw/puv3_gpio.c | 141 ++
3 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_gpio.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index b96722a..c6cc97b 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -69,6 +69,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
+hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 5a8a27c..0354cf6 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,12 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
+sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
+irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
+irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
+irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
+irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
+irqs[PUV3_IRQS_GPIOHIGH], NULL);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c
new file mode 100644
index 000..d78aac3
--- /dev/null
+++ b/hw/puv3_gpio.c
@@ -0,0 +1,141 @@
+/*
+ * GPIO device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq irq[9];
+
+uint32_t reg_GPLR;
+uint32_t reg_GPDR;
+uint32_t reg_GPIR;
+} PUV3GPIOState;
+
+static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3GPIOState *s = opaque;
+uint32_t ret;
+
+switch (offset) {
+case 0x00:
+ret = s->reg_GPLR;
+break;
+case 0x04:
+ret = s->reg_GPDR;
+break;
+case 0x20:
+ret = s->reg_GPIR;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3GPIOState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x04:
+s->reg_GPDR = value;
+break;
+case 0x08:
+if (s->reg_GPDR & value) {
+s->reg_GPLR |= value;
+} else {
+DPRINTF("Write gpio input port error!");
+}
+break;
+case 0x0c:
+if (s->reg_GPDR & value) {
+s->reg_GPLR &= ~value;
+} else {
+DPRINTF("Write gpio input port error!");
+}
+break;
+case 0x10: /* GRER */
+case 0x14: /* GFER */
+case 0x18: /* GEDR */
+break;
+case 0x20: /* GPIR */
+s->reg_GPIR = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+}
+
+static const MemoryRegionOps puv3_gpio_ops = {
+.read = puv3_gpio_read,
+.write = puv3_gpio_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_gpio_init(SysBusDevice *dev)
+{
+PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev);
+
+s->reg_GPLR = 0;
+s->reg_GPDR = 0;
+
+/* FIXME: these irqs not handled yet */
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
+
+memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_gpio_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_gpio_init;
+}
[Qemu-devel] [PATCH 08/19] unicore32-softmmu: Add puv3 interrupt support
From: Guan Xuetao
This patch adds puv3 interrupt support, include interrupt controler
device simulation and interrupt handler in puv3 machine.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |3 +
hw/puv3.c| 23 +-
hw/puv3_intc.c | 135 ++
3 files changed, 160 insertions(+), 1 deletions(-)
create mode 100644 hw/puv3_intc.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..50554b6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+# PKUnity SoC devices
+hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0dc129d..2870455 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -22,9 +22,30 @@
#define KERNEL_LOAD_ADDR0x0300
#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
+{
+CPUUniCore32State *env = opaque;
+
+assert(irq == 0);
+if (level) {
+cpu_interrupt(env, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+}
+}
+
static void puv3_soc_init(CPUUniCore32State *env)
{
-/* TODO */
+qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
+DeviceState *dev;
+int i;
+
+/* Initialize interrupt controller */
+cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
+for (i = 0; i < PUV3_IRQS_NR; i++) {
+irqs[i] = qdev_get_gpio_in(dev, i);
+}
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
new file mode 100644
index 000..9e0b975
--- /dev/null
+++ b/hw/puv3_intc.c
@@ -0,0 +1,135 @@
+/*
+ * INTC device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq parent_irq;
+
+uint32_t reg_ICMR;
+uint32_t reg_ICPR;
+} PUV3INTCState;
+
+/* Update interrupt status after enabled or pending bits have been changed. */
+static void puv3_intc_update(PUV3INTCState *s)
+{
+if (s->reg_ICMR & s->reg_ICPR) {
+qemu_irq_raise(s->parent_irq);
+} else {
+qemu_irq_lower(s->parent_irq);
+}
+}
+
+/* Process a change in an external INTC input. */
+static void puv3_intc_handler(void *opaque, int irq, int level)
+{
+PUV3INTCState *s = opaque;
+
+DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
+if (level) {
+s->reg_ICPR |= (1 << irq);
+} else {
+s->reg_ICPR &= ~(1 << irq);
+}
+puv3_intc_update(s);
+}
+
+static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3INTCState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x04: /* INTC_ICMR */
+ret = s->reg_ICMR;
+break;
+case 0x0c: /* INTC_ICIP */
+ret = s->reg_ICPR; /* the same value with ICPR */
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3INTCState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* INTC_ICLR */
+case 0x14: /* INTC_ICCR */
+break;
+case 0x04: /* INTC_ICMR */
+s->reg_ICMR = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", (int)offset);
+return;
+}
+puv3_intc_update(s);
+}
+
+static const MemoryRegionOps puv3_intc_ops = {
+.read = puv3_intc_read,
+.write = puv3_intc_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_intc_init(SysBusDevice *dev)
+{
+PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
+
+qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
+sysbus_init_irq(&s->busdev, &s->parent_irq);
+
+s->reg_ICMR = 0;
+s->reg_ICPR = 0;
+
+memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_intc_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc =
[Qemu-devel] [PATCH 17/19] unicore32: Disintegrate cpu_dump_state_ucf64 function
From: Guan Xuetao
This patch disintegrates cpu_dump_state_ucf64 function from cpu_dump_state.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 41 +
1 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 5ee3a59..c74c49a 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2139,11 +2139,11 @@ static const char *cpu_mode_names[16] = {
};
#define UCF64_DUMP_STATE
-void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function
cpu_fprintf,
-int flags)
+#ifdef UCF64_DUMP_STATE
+static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
{
int i;
-#ifdef UCF64_DUMP_STATE
union {
uint32_t i;
float s;
@@ -2155,7 +2155,28 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
float64 f64;
double d;
} d0;
+
+for (i = 0; i < 16; i++) {
+d.d = env->ucf64.regs[i];
+s0.i = d.l.lower;
+s1.i = d.l.upper;
+d0.f64 = d.d;
+cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
+i * 2, (int)s0.i, s0.s,
+i * 2 + 1, (int)s1.i, s1.s);
+cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
+i, (uint64_t)d0.f64, d0.d);
+}
+cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
+}
+#else
+#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
#endif
+
+void cpu_dump_state(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
+{
+int i;
uint32_t psr;
for (i = 0; i < 32; i++) {
@@ -2175,19 +2196,7 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
psr & (1 << 28) ? 'V' : '-',
cpu_mode_names[psr & 0xf]);
-#ifdef UCF64_DUMP_STATE
-for (i = 0; i < 16; i++) {
-d.d = env->ucf64.regs[i];
-s0.i = d.l.lower;
-s1.i = d.l.upper;
-d0.f64 = d.d;
-cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%" PRIx64
"(%8g)\n",
-i * 2, (int)s0.i, s0.s,
-i * 2 + 1, (int)s1.i, s1.s,
-i, (uint64_t)d0.f64, d0.d);
-}
-cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
-#endif
+cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
}
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int
pc_pos)
--
1.7.0.4
[Qemu-devel] [PATCH 19/19] unicore32-softmmu: Add a minimal curses screen support
From: Guan Xuetao
This patch adds a minimal curses screen support for unicore32-softmmu.
We assume 80*30 screen size to minimize the implementation.
Two problems are not solved, but they are innocuous.
1. curses windows will be blank when switching to monitor screen and back
2. backspace is not handled yet
v1->v2: add extra handler for '\r'
Signed-off-by: Zhang Mengchi
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c | 45 +++--
1 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d6eb758..d21e7df 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -13,6 +13,7 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
+#include "console.h"
#undef DEBUG_UC32
@@ -186,10 +187,50 @@ uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t
creg, uint32_t cop)
return 0;
}
+#ifdef CONFIG_CURSES
+/*
+ * FIXME:
+ * 1. curses windows will be blank when switching back
+ * 2. backspace is not handled yet
+ */
+static void putc_on_screen(unsigned char ch)
+{
+static WINDOW *localwin;
+static int init;
+
+if (!init) {
+/* Assume 80 * 30 screen to minimize the implementation */
+localwin = newwin(30, 80, 0, 0);
+scrollok(localwin, TRUE);
+init = TRUE;
+}
+
+if (isprint(ch)) {
+wprintw(localwin, "%c", ch);
+} else {
+switch (ch) {
+case '\n':
+wprintw(localwin, "%c", ch);
+break;
+case '\r':
+/* If '\r' is put before '\n', the curses window will destroy the
+ * last print line. And meanwhile, '\n' implifies '\r' inside. */
+break;
+default: /* Not handled, so just print it hex code */
+wprintw(localwin, "-- 0x%h --", ch);
+}
+}
+
+wrefresh(localwin);
+}
+#else
+#define putc_on_screen(c) do { } while (0)
+#endif
+
void helper_cp1_putc(target_ulong x)
{
-/* TODO: curses display should be added here for screen output. */
-DPRINTF("%c", x);
+putc_on_screen((unsigned char)x); /* Output to screen */
+DPRINTF("%c", x); /* Output to stdout */
}
#endif
--
1.7.0.4
[Qemu-devel] [PATCH 16/19] unicore32: Split UniCore-F64 instruction helpers from helper.c
From: Guan Xuetao
This patch just splits ucf64 instruction simulation helpers from
helper.c.
Also, two checkpatch warnings are solved.
v1->v2: adjust copyright information for new ucf64_helper.c
Signed-off-by: Guan Xuetao
---
target-unicore32/Makefile.objs |2 +
target-unicore32/helper.c | 330 -
target-unicore32/ucf64_helper.c | 345 +++
3 files changed, 347 insertions(+), 330 deletions(-)
create mode 100644 target-unicore32/ucf64_helper.c
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 6af1089..777f01f 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,6 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += ucf64_helper.o
+
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f9f1960..d6eb758 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -213,333 +213,3 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
return 1;
}
#endif
-
-/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
- Single precition routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to f64 form. */
-static inline int ucf64_exceptbits_from_host(int host_bits)
-{
-int target_bits = 0;
-
-if (host_bits & float_flag_invalid) {
-target_bits |= UCF64_FPSCR_FLAG_INVALID;
-}
-if (host_bits & float_flag_divbyzero) {
-target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
-}
-if (host_bits & float_flag_overflow) {
-target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
-}
-if (host_bits & float_flag_underflow) {
-target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
-}
-if (host_bits & float_flag_inexact) {
-target_bits |= UCF64_FPSCR_FLAG_INEXACT;
-}
-return target_bits;
-}
-
-uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
-{
-int i;
-uint32_t fpscr;
-
-fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
-i = get_float_exception_flags(&env->ucf64.fp_status);
-fpscr |= ucf64_exceptbits_from_host(i);
-return fpscr;
-}
-
-/* Convert ucf64 exception flags to target form. */
-static inline int ucf64_exceptbits_to_host(int target_bits)
-{
-int host_bits = 0;
-
-if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
-host_bits |= float_flag_invalid;
-}
-if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
-host_bits |= float_flag_divbyzero;
-}
-if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
-host_bits |= float_flag_overflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
-host_bits |= float_flag_underflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
-host_bits |= float_flag_inexact;
-}
-return host_bits;
-}
-
-void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
-{
-int i;
-uint32_t changed;
-
-changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
-env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
-
-changed ^= val;
-if (changed & (UCF64_FPSCR_RND_MASK)) {
-i = UCF64_FPSCR_RND(val);
-switch (i) {
-case 0:
-i = float_round_nearest_even;
-break;
-case 1:
-i = float_round_to_zero;
-break;
-case 2:
-i = float_round_up;
-break;
-case 3:
-i = float_round_down;
-break;
-default: /* 100 and 101 not implement */
-cpu_abort(env, "Unsupported UniCore-F64 round mode");
-}
-set_float_rounding_mode(i, &env->ucf64.fp_status);
-}
-
-i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
-set_float_exception_flags(i, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_add(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_add(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_sub(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_sub(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_mul(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_mul(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_div(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUn
[Qemu-devel] [PATCH 15/19] unicore32-softmmu: Add is_default setting for puv3 machine
From: Guan Xuetao
This patch sets is_default to 1 for puv3 machine, so that
find_default_machine() returns puv3 machine.
Thanks Dunrong for pointing it out.
Cc: Dunrong Huang
Signed-off-by: Guan Xuetao
---
hw/puv3.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/puv3.c b/hw/puv3.c
index 271df97..43f7216 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -119,6 +119,7 @@ static QEMUMachine puv3_machine = {
.name = "puv3",
.desc = "PKUnity Version-3 based on UniCore32",
.init = puv3_init,
+.is_default = 1,
.use_scsi = 0,
};
--
1.7.0.4
[Qemu-devel] [PATCH 18/19] unicore32: Close dump-option of cpu_dump_state_ucf64 function
From: Guan Xuetao
Since of tedious output, we close dump-option of cpu_dump_state_ucf64 function.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c74c49a..188bf8c 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2138,7 +2138,7 @@ static const char *cpu_mode_names[16] = {
"UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
};
-#define UCF64_DUMP_STATE
+#undef UCF64_DUMP_STATE
#ifdef UCF64_DUMP_STATE
static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprintf, int flags)
--
1.7.0.4
[Qemu-devel] [PATCH 07/19] unicore32-softmmu: Add puv3 soc/board support
From: Guan Xuetao
This patch only add puv3 soc/board support, which introduces puv3
machine description, and specifies console type.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c | 93 +
hw/puv3.h | 49 +
hw/unicore32/Makefile.objs|5 ++
4 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3.c
create mode 100644 hw/puv3.h
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 5f04fe3..726a338 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1 +1,2 @@
# Default configuration for unicore32-softmmu
+CONFIG_PUV3=y
diff --git a/hw/puv3.c b/hw/puv3.c
new file mode 100644
index 000..0dc129d
--- /dev/null
+++ b/hw/puv3.c
@@ -0,0 +1,93 @@
+/*
+ * Generic PKUnity SoC machine and board descriptor
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "console.h"
+#include "elf.h"
+#include "exec-memory.h"
+#include "sysbus.h"
+#include "boards.h"
+#include "loader.h"
+#include "pc.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define KERNEL_LOAD_ADDR0x0300
+#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+
+static void puv3_soc_init(CPUUniCore32State *env)
+{
+/* TODO */
+}
+
+static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
+{
+MemoryRegion *ram_memory = g_new(MemoryRegion, 1);
+
+/* SDRAM at address zero. */
+memory_region_init_ram(ram_memory, "puv3.ram", ram_size);
+vmstate_register_ram_global(ram_memory);
+memory_region_add_subregion(get_system_memory(), 0, ram_memory);
+}
+
+static void puv3_load_kernel(const char *kernel_filename)
+{
+int size;
+
+assert(kernel_filename != NULL);
+
+/* only zImage format supported */
+size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
+KERNEL_MAX_SIZE);
+if (size < 0) {
+hw_error("Load kernel error: '%s'\n", kernel_filename);
+}
+
+/* cheat curses that we have a graphic console, only under ocd console */
+graphic_console_init(NULL, NULL, NULL, NULL, NULL);
+}
+
+static void puv3_init(ram_addr_t ram_size, const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+CPUUniCore32State *env;
+
+if (initrd_filename) {
+hw_error("Please use kernel built-in initramdisk.\n");
+}
+
+if (!cpu_model) {
+cpu_model = "UniCore-II";
+}
+
+env = cpu_init(cpu_model);
+if (!env) {
+hw_error("Unable to find CPU definition\n");
+}
+
+puv3_soc_init(env);
+puv3_board_init(env, ram_size);
+puv3_load_kernel(kernel_filename);
+}
+
+static QEMUMachine puv3_machine = {
+.name = "puv3",
+.desc = "PKUnity Version-3 based on UniCore32",
+.init = puv3_init,
+.use_scsi = 0,
+};
+
+static void puv3_machine_init(void)
+{
+qemu_register_machine(&puv3_machine);
+}
+
+machine_init(puv3_machine_init)
diff --git a/hw/puv3.h b/hw/puv3.h
new file mode 100644
index 000..f37adcb
--- /dev/null
+++ b/hw/puv3.h
@@ -0,0 +1,49 @@
+/*
+ * Misc PKUnity SoC declarations
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef QEMU_HW_PUV3_H
+#define QEMU_HW_PUV3_H
+
+#define PUV3_REGS_OFFSET(0x1000) /* 4K is reasonable */
+
+/* PKUnity System bus (AHB): 0xc000 - 0xedff (640MB) */
+#define PUV3_DMA_BASE (0xc020) /* AHB-4 */
+
+/* PKUnity Peripheral bus (APB): 0xee00 - 0xefff (128MB) */
+#define PUV3_GPIO_BASE (0xee50) /* APB-5 */
+#define PUV3_INTC_BASE (0xee60) /* APB-6 */
+#define PUV3_OST_BASE (0xee80) /* APB-8 */
+#define PUV3_PM_BASE(0xeea0) /* APB-10 */
+#define PUV3_PS2_BASE (0xeeb0) /* APB-11 */
+
+/* Hardware interrupts */
+#define PUV3_IRQS_NR(32)
+
+#define PUV3_IRQS_GPIOLOW0 (0)
+#define PUV3_IRQS_GPIOLOW1 (1)
+#define PUV3_IRQS_GPIOLOW2 (2)
+#define PUV3_IRQS_GPIOLOW3 (3)
+#define PUV3_IRQS_GPIOLOW4 (4)
+#define PUV3_IRQS_GPIOLOW5 (5)
+#define PUV3_IRQS_GPIOLOW6 (6)
+#define PUV3_IRQS_GPIOLOW7 (7)
+#define PUV3_IRQS_GPIOHIGH (8)
+#define PUV3_IRQS_PS2_KBD (22)
+#define PUV3_IRQS_PS
[Qemu-devel] [PATCH 05/19] unicore32-softmmu: Implement softmmu specific functions
From: Guan Xuetao
This patch implements softmmu specific functions, include tlb_fill,
switch_mode, do_interrupt and uc32_cpu_handle_mmu_fault.
So the full exception handlers and page table walking could work now.
Signed-off-by: Guan Xuetao
---
target-unicore32/op_helper.c | 22 -
target-unicore32/softmmu.c | 236 +-
2 files changed, 253 insertions(+), 5 deletions(-)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 6df30db..c63789d 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -267,6 +267,26 @@ uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+TranslationBlock *tb;
+CPUUniCore32State *saved_env;
+unsigned long pc;
+int ret;
+
+saved_env = env;
+env = env1;
+ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
+if (unlikely(ret)) {
+if (retaddr) {
+/* now we have a real cpu fault */
+pc = (unsigned long)retaddr;
+tb = tb_find_pc(pc);
+if (tb) {/* the PC is inside the translated code.
+It means that we have a virtual CPU fault */
+cpu_restore_state(tb, env, pc);
+}
+}
+cpu_loop_exit(env);
+}
+env = saved_env;
}
#endif
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 6fec77e..373f94b 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -14,21 +14,249 @@
#include
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define SUPERPAGE_SIZE (1 << 22)
+#define UC32_PAGETABLE_READ(1 << 8)
+#define UC32_PAGETABLE_WRITE (1 << 7)
+#define UC32_PAGETABLE_EXEC(1 << 6)
+#define UC32_PAGETABLE_EXIST (1 << 2)
+#define PAGETABLE_TYPE(x) ((x) & 3)
+
+
+/* Map CPU modes onto saved register banks. */
+static inline int bank_number(int mode)
+{
+switch (mode) {
+case ASR_MODE_USER:
+case ASR_MODE_SUSR:
+return 0;
+case ASR_MODE_PRIV:
+return 1;
+case ASR_MODE_TRAP:
+return 2;
+case ASR_MODE_EXTN:
+return 3;
+case ASR_MODE_INTR:
+return 4;
+}
+cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
+return -1;
+}
+
void switch_mode(CPUUniCore32State *env, int mode)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+int old_mode;
+int i;
+
+old_mode = env->uncached_asr & ASR_M;
+if (mode == old_mode) {
+return;
+}
+
+i = bank_number(old_mode);
+env->banked_r29[i] = env->regs[29];
+env->banked_r30[i] = env->regs[30];
+env->banked_bsr[i] = env->bsr;
+
+i = bank_number(mode);
+env->regs[29] = env->banked_r29[i];
+env->regs[30] = env->banked_r30[i];
+env->bsr = env->banked_bsr[i];
}
+/* Handle a CPU exception. */
void do_interrupt(CPUUniCore32State *env)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+uint32_t addr;
+int new_mode;
+
+switch (env->exception_index) {
+case UC32_EXCP_PRIV:
+new_mode = ASR_MODE_PRIV;
+addr = 0x08;
+break;
+case UC32_EXCP_ITRAP:
+DPRINTF("itrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x0c;
+break;
+case UC32_EXCP_DTRAP:
+DPRINTF("dtrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x10;
+break;
+case UC32_EXCP_INTR:
+new_mode = ASR_MODE_INTR;
+addr = 0x18;
+break;
+default:
+cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+return;
+}
+/* High vectors. */
+if (env->cp0.c1_sys & (1 << 13)) {
+addr += 0x;
+}
+
+switch_mode(env, new_mode);
+env->bsr = cpu_asr_read(env);
+env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
+env->uncached_asr |= ASR_I;
+/* The PC already points to the proper instruction. */
+env->regs[30] = env->regs[31];
+env->regs[31] = addr;
+env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+}
+
+static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
+int access_type, int is_user, uint32_t *phys_ptr, int *prot,
+target_ulong *page_size)
+{
+int code;
+uint32_t table;
+uint32_t desc;
+uint32_t phys_addr;
+
+/* Pagetable walk. */
+/* Lookup l1 descriptor. */
+table = env->cp0.c2_base & 0xf000;
+table |= (address >> 20) & 0xffc;
+desc = ldl_phys(table);
+code = 0;
+switch (PAGETABLE_TYPE(desc)) {
+case 3:
+/* Superpage */
+if (!(desc & UC32_PAGETABLE_
[Qemu-devel] [PATCH 14/19] unicore32-softmmu: Add maintainer information for UniCore32 machine
From: Guan Xuetao Signed-off-by: Guan Xuetao --- MAINTAINERS |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2d219d2..708ad54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -405,6 +405,14 @@ M: Alexander Graf S: Maintained F: hw/s390-*.c +UniCore32 Machines +- +PKUnity-3 SoC initramfs-with-busybox +M: Guan Xuetao +S: Maintained +F: hw/puv3* +F: hw/unicore32/ + X86 Machines PC -- 1.7.0.4
[Qemu-devel] [PATCH 04/19] target-unicore32: Drop UC32_CPUID macros
From: Andreas Färber Any code that depends on a particular CPU type can now go through callbacks on the QOM UniCore32CPUClass. Signed-off-by: Andreas Färber --- target-unicore32/cpu.h |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index d14fde5..06508a1 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -122,10 +122,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ #define UC32_HWCAP_UCF648 /* 1 << 3 */ -#define UC32_CPUID(env) (env->cp0.c0_cpuid) -#define UC32_CPUID_UCV2 0x40010863 -#define UC32_CPUID_ANY 0x - #define cpu_inituc32_cpu_init #define cpu_execuc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler -- 1.7.0.4
[Qemu-devel] [PATCH 13/19] unicore32-softmmu: Add ps2 support
From: Guan Xuetao
This patch adds ps2/keyboard support, and enables CONFIG_PCKBD.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 4d4fbfc..de38577 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,3 +1,4 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
CONFIG_PTIMER=y
+CONFIG_PCKBD=y
diff --git a/hw/puv3.c b/hw/puv3.c
index 9acfc5a..271df97 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -38,6 +38,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
{
qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
DeviceState *dev;
+MemoryRegion *i8042 = g_new(MemoryRegion, 1);
int i;
/* Initialize interrupt controller */
@@ -57,6 +58,10 @@ static void puv3_soc_init(CPUUniCore32State *env)
irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
irqs[PUV3_IRQS_GPIOHIGH], NULL);
+
+/* Keyboard (i8042), mouse disabled for nographic */
+i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
+memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
--
1.7.0.4
[Qemu-devel] [PATCH 11/19] unicore32-softmmu: Add puv3 pm support
From: Guan Xuetao
This patch adds puv3 pm (power management) support,
include pm device simulation for kernel booting.
Thank Blue Swirl for pointing out the missing "break".
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_pm.c | 149 ++
3 files changed, 151 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_pm.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index c6cc97b..e2a39d6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -70,6 +70,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
+hw-obj-$(CONFIG_PUV3) += puv3_pm.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0354cf6..3a14b27 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -48,6 +48,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
}
/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c
new file mode 100644
index 000..b66fdbe
--- /dev/null
+++ b/hw/puv3_pm.c
@@ -0,0 +1,149 @@
+/*
+ * Power Management device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t reg_PMCR;
+uint32_t reg_PCGR;
+uint32_t reg_PLL_SYS_CFG;
+uint32_t reg_PLL_DDR_CFG;
+uint32_t reg_PLL_VGA_CFG;
+uint32_t reg_DIVCFG;
+} PUV3PMState;
+
+static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3PMState *s = opaque;
+uint32_t ret;
+
+switch (offset) {
+case 0x14:
+ret = s->reg_PCGR;
+break;
+case 0x18:
+ret = s->reg_PLL_SYS_CFG;
+break;
+case 0x1c:
+ret = s->reg_PLL_DDR_CFG;
+break;
+case 0x20:
+ret = s->reg_PLL_VGA_CFG;
+break;
+case 0x24:
+ret = s->reg_DIVCFG;
+break;
+case 0x28: /* PLL SYS STATUS */
+ret = 0x2401;
+break;
+case 0x2c: /* PLL DDR STATUS */
+ret = 0x00100c00;
+break;
+case 0x30: /* PLL VGA STATUS */
+ret = 0x3801;
+break;
+case 0x34: /* DIV STATUS */
+ret = 0x22f52015;
+break;
+case 0x38: /* SW RESET */
+ret = 0x0;
+break;
+case 0x44: /* PLL DFC DONE */
+ret = 0x7;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3PMState *s = opaque;
+
+switch (offset) {
+case 0x0:
+s->reg_PMCR = value;
+break;
+case 0x14:
+s->reg_PCGR = value;
+break;
+case 0x18:
+s->reg_PLL_SYS_CFG = value;
+break;
+case 0x1c:
+s->reg_PLL_DDR_CFG = value;
+break;
+case 0x20:
+s->reg_PLL_VGA_CFG = value;
+break;
+case 0x24:
+case 0x38:
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_pm_ops = {
+.read = puv3_pm_read,
+.write = puv3_pm_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_pm_init(SysBusDevice *dev)
+{
+PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev);
+
+s->reg_PCGR = 0x0;
+
+memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_pm_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_pm_init;
+}
+
+static const TypeInfo puv3_pm_info = {
+.name = "puv3_pm",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3PMState),
+.class_init = puv3_pm_class_init,
+};
+
+static void puv3_pm_register_type(void)
+{
+type_register_static(&puv3_pm_info);
+}
+
+type_init(puv3_pm_register_type)
--
1.7.0.4
[Qemu-devel] [PATCH 06/19] unicore32-softmmu: Make sure that kernel can access user space
From: Guan Xuetao
As a matter of course, we need to access user space in kernel code,
so we need to correct load/store decoders to indicate correct memory
region.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 36 ++--
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index e37d5be..5ee3a59 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -33,9 +33,16 @@ typedef struct DisasContext {
int condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
+#ifndef CONFIG_USER_ONLY
+int user;
+#endif
} DisasContext;
-#define IS_USER(s) 1
+#ifndef CONFIG_USER_ONLY
+#define IS_USER(s) (s->user)
+#else
+#define IS_USER(s) 1
+#endif
/* These instructions trap after executing, so defer them until after the
conditional executions state has been updated. */
@@ -1554,12 +1561,12 @@ static void do_misc(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store I_offset and R_offset */
static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int i;
+unsigned int mmu_idx;
TCGv tmp;
TCGv tmp2;
tmp2 = load_reg(s, UCOP_REG_N);
-i = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
/* immediate */
if (UCOP_SET_P) {
@@ -1569,17 +1576,17 @@ static void do_ldst_ir(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
if (UCOP_SET_L) {
/* load */
if (UCOP_SET_B) {
-tmp = gen_ld8u(tmp2, i);
+tmp = gen_ld8u(tmp2, mmu_idx);
} else {
-tmp = gen_ld32(tmp2, i);
+tmp = gen_ld32(tmp2, mmu_idx);
}
} else {
/* store */
tmp = load_reg(s, UCOP_REG_D);
if (UCOP_SET_B) {
-gen_st8(tmp, tmp2, i);
+gen_st8(tmp, tmp2, mmu_idx);
} else {
-gen_st32(tmp, tmp2, i);
+gen_st32(tmp, tmp2, mmu_idx);
}
}
if (!UCOP_SET_P) {
@@ -1682,7 +1689,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int val, i;
+unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
TCGv tmp2;
@@ -1703,6 +1710,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
}
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
addr = load_reg(s, UCOP_REG_N);
/* compute total size */
@@ -1747,7 +1755,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
if (UCOP_SET(i)) {
if (UCOP_SET_L) { /* load */
-tmp = gen_ld32(addr, IS_USER(s));
+tmp = gen_ld32(addr, mmu_idx);
if (reg == 31) {
gen_bx(s, tmp);
} else if (user) {
@@ -1775,7 +1783,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
} else {
tmp = load_reg(s, reg);
}
-gen_st32(tmp, addr, IS_USER(s));
+gen_st32(tmp, addr, mmu_idx);
}
j++;
/* no need to add after the last transfer */
@@ -1964,6 +1972,14 @@ static inline void
gen_intermediate_code_internal(CPUUniCore32State *env,
max_insns = CF_COUNT_MASK;
}
+#ifndef CONFIG_USER_ONLY
+if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
+dc->user = 1;
+} else {
+dc->user = 0;
+}
+#endif
+
gen_icount_start();
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
--
1.7.0.4
[Qemu-devel] [PATCH 12/19] unicore32-softmmu: Add puv3 dma support
From: Guan Xuetao
This patch adds puv3 dma (Direct Memory Access) support,
include dma device simulation for kernel booting.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_dma.c| 109 ++
3 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_dma.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index e2a39d6..6df346a 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -71,6 +71,7 @@ hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
hw-obj-$(CONFIG_PUV3) += puv3_pm.o
+hw-obj-$(CONFIG_PUV3) += puv3_dma.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 3a14b27..9acfc5a 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
+sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_dma.c b/hw/puv3_dma.c
new file mode 100644
index 000..bd1f43e
--- /dev/null
+++ b/hw/puv3_dma.c
@@ -0,0 +1,109 @@
+/*
+ * DMA device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define PUV3_DMA_CH_NR (6)
+#define PUV3_DMA_CH_MASK(0xff)
+#define PUV3_DMA_CH(offset) ((offset) >> 8)
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t reg_CFG[PUV3_DMA_CH_NR];
+} PUV3DMAState;
+
+static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3DMAState *s = opaque;
+uint32_t ret;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+ret = s->reg_CFG[PUV3_DMA_CH(offset)];
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3DMAState *s = opaque;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+s->reg_CFG[PUV3_DMA_CH(offset)] = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_dma_ops = {
+.read = puv3_dma_read,
+.write = puv3_dma_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_dma_init(SysBusDevice *dev)
+{
+PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev);
+int i;
+
+for (i = 0; i < PUV3_DMA_CH_NR; i++) {
+s->reg_CFG[i] = 0x0;
+}
+
+memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_dma_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_dma_init;
+}
+
+static const TypeInfo puv3_dma_info = {
+.name = "puv3_dma",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3DMAState),
+.class_init = puv3_dma_class_init,
+};
+
+static void puv3_dma_register_type(void)
+{
+type_register_static(&puv3_dma_info);
+}
+
+type_init(puv3_dma_register_type)
--
1.7.0.4
[Qemu-devel] [PATCH 02/19] unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support
From: Guan Xuetao
Coprocessor 0 is system control coprocessor, and we need get/set its contents.
Also, all cache/tlb ops shoule be implemented here, but just ignored with no
harm.
Coprocessor 1 is OCD (on-chip-debugger), which is used for faked console,
so we could output chars to this console without graphic card.
TODO: curses display should be added lator for screen output.
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c| 185 +-
target-unicore32/helper.h| 17 ++---
target-unicore32/translate.c | 80 ++-
3 files changed, 233 insertions(+), 49 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9b8ff06..f9f1960 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -14,6 +14,14 @@
#include "helper.h"
#include "host-utils.h"
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
@@ -45,6 +53,146 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifndef CONFIG_USER_ONLY
+void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
+uint32_t cop)
+{
+/*
+ * movc pp.nn, rn, #imm9
+ * rn: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * 5: cache op. reg.
+ * 6: tlb op. reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 1:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c1_sys = val;
+break;
+case 2:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c2_base = val;
+break;
+case 3:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c3_faultstatus = val;
+break;
+case 4:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c4_faultaddr = val;
+break;
+case 5:
+switch (cop) {
+case 28:
+DPRINTF("Invalidate Entire I&D cache\n");
+return;
+case 20:
+DPRINTF("Invalidate Entire Icache\n");
+return;
+case 12:
+DPRINTF("Invalidate Entire Dcache\n");
+return;
+case 10:
+DPRINTF("Clean Entire Dcache\n");
+return;
+case 14:
+DPRINTF("Flush Entire Dcache\n");
+return;
+case 13:
+DPRINTF("Invalidate Dcache line\n");
+return;
+case 11:
+DPRINTF("Clean Dcache line\n");
+return;
+case 15:
+DPRINTF("Flush Dcache line\n");
+return;
+}
+break;
+case 6:
+if ((cop <= 6) && (cop >= 2)) {
+/* invalid all tlb */
+tlb_flush(env, 1);
+return;
+}
+break;
+default:
+goto unrecognized;
+}
+return;
+unrecognized:
+DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+}
+
+uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
+{
+/*
+ * movc rd, pp.nn, #imm9
+ * rd: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 0: cpuid and cachetype
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 0:
+switch (cop) {
+case 0:
+return env->cp0.c0_cpuid;
+case 1:
+return env->cp0.c0_cachetype;
+}
+break;
+case 1:
+if (cop == 0) {
+return env->cp0.c1_sys;
+}
+break;
+case 2:
+if (cop == 0) {
+return env->cp0.c2_base;
+}
+break;
+case 3:
+if (cop == 0) {
+return env->cp0.c3_faultstatus;
+}
+break;
+case 4:
+if (cop == 0) {
+return env->cp0.c4_faultaddr;
+}
+break;
+}
+DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+return 0;
+}
+
+void helper_cp1_putc(target_ulong x)
+{
+/* TODO: curses display should be added here for screen output. */
+DPRINTF("%c", x);
+}
+#endif
+
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
@@ -66,43 +214,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
}
#endif
-/* These should probably raise undefined insn exceptions. */
-void HELP
[Qemu-devel] [PATCH 09/19] unicore32-softmmu: Add puv3 ostimer support
From: Guan Xuetao
This patch adds puv3 ostimer support, include os timer
device simulation and ptimer support in puv3 machine.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/Makefile.objs |1 +
hw/puv3.c |3 +
hw/puv3_ost.c | 151 +
4 files changed, 156 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_ost.c
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 726a338..4d4fbfc 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,2 +1,3 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
+CONFIG_PTIMER=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 50554b6..b96722a 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -68,6 +68,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+hw-obj-$(CONFIG_PUV3) += puv3_ost.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 2870455..5a8a27c 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -46,6 +46,9 @@ static void puv3_soc_init(CPUUniCore32State *env)
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
}
+
+/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c
new file mode 100644
index 000..dd30cad
--- /dev/null
+++ b/hw/puv3_ost.c
@@ -0,0 +1,151 @@
+/*
+ * OSTimer device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+#include "ptimer.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+/* puv3 ostimer implementation. */
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+QEMUBH *bh;
+qemu_irq irq;
+ptimer_state *ptimer;
+
+uint32_t reg_OSMR0;
+uint32_t reg_OSCR;
+uint32_t reg_OSSR;
+uint32_t reg_OIER;
+} PUV3OSTState;
+
+static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3OSTState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x10: /* Counter Register */
+ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
+break;
+case 0x14: /* Status Register */
+ret = s->reg_OSSR;
+break;
+case 0x1c: /* Interrupt Enable Register */
+ret = s->reg_OIER;
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3OSTState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* Match Register 0 */
+s->reg_OSMR0 = value;
+if (s->reg_OSMR0 > s->reg_OSCR) {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
+} else {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 +
+(0x - s->reg_OSCR));
+}
+ptimer_run(s->ptimer, 2);
+break;
+case 0x14: /* Status Register */
+assert(value == 0);
+if (s->reg_OSSR) {
+s->reg_OSSR = value;
+qemu_irq_lower(s->irq);
+}
+break;
+case 0x1c: /* Interrupt Enable Register */
+s->reg_OIER = value;
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+}
+
+static const MemoryRegionOps puv3_ost_ops = {
+.read = puv3_ost_read,
+.write = puv3_ost_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void puv3_ost_tick(void *opaque)
+{
+PUV3OSTState *s = opaque;
+
+DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
+s->reg_OSCR, s->reg_OSMR0);
+
+s->reg_OSCR = s->reg_OSMR0;
+if (s->reg_OIER) {
+s->reg_OSSR = 1;
+qemu_irq_raise(s->irq);
+}
+}
+
+static int puv3_ost_init(SysBusDevice *dev)
+{
+PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
+
+s->reg_OIER = 0;
+s->reg_OSSR = 0;
+s->reg_OSMR0 = 0;
+s->reg_OSCR = 0;
+
+sysbus_init_irq(dev, &s->irq);
+
+s->bh = qemu_bh_new(puv3_ost_tick, s);
+s->ptimer = ptimer_init(s->bh);
+ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
+
+
[Qemu-devel] [PATCHv2 04/19] target-unicore32: Drop UC32_CPUID macros
From: Andreas Färber Any code that depends on a particular CPU type can now go through callbacks on the QOM UniCore32CPUClass. Signed-off-by: Andreas Färber --- target-unicore32/cpu.h |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index d14fde5..06508a1 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -122,10 +122,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ #define UC32_HWCAP_UCF648 /* 1 << 3 */ -#define UC32_CPUID(env) (env->cp0.c0_cpuid) -#define UC32_CPUID_UCV2 0x40010863 -#define UC32_CPUID_ANY 0x - #define cpu_inituc32_cpu_init #define cpu_execuc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler -- 1.7.0.4
[Qemu-devel] [PATCHv2 03/19] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable
From: Guan Xuetao
This patch initializes the cpuid to exactly correct value because
linux kernel will check it.
In addition, the exception types are specified in proper situations.
Then it could make exceptions generated correctly and timely.
Signed-off-by: Guan Xuetao
---
cpu-exec.c |1 +
linux-user/main.c |3 ++-
target-unicore32/cpu.c | 19 ++-
target-unicore32/cpu.h | 14 --
4 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 543460c..6c4e516 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -447,6 +447,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
+env->exception_index = UC32_EXCP_INTR;
do_interrupt(env);
next_tb = 0;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 53714de..9d921aa 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env)
}
}
break;
-case UC32_EXCP_TRAP:
+case UC32_EXCP_DTRAP:
+case UC32_EXCP_ITRAP:
info.si_signo = SIGSEGV;
info.si_errno = 0;
/* XXX: check env->error_code */
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index de63f58..3425bbe 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -1,7 +1,7 @@
/*
* QEMU UniCore32 CPU
*
- * Copyright (c) 2010-2011 GUAN Xue-tao
+ * Copyright (c) 2010-2012 Guan Xuetao
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This program is free software; you can redistribute it and/or modify
@@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
-env->cp0.c0_cpuid = 0x40010863;
+env->cp0.c0_cpuid = 0x4d000863;
+env->cp0.c0_cachetype = 0x0d152152;
+env->cp0.c1_sys = 0x2000;
+env->cp0.c2_base = 0x0;
+env->cp0.c3_faultstatus = 0x0;
+env->cp0.c4_faultaddr = 0x0;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
-env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
-env->cp0.c0_cachetype = 0x1dd20d2;
-env->cp0.c1_sys = 0x00090078;
}
static void uc32_any_cpu_initfn(Object *obj)
@@ -47,6 +50,7 @@ static void uc32_any_cpu_initfn(Object *obj)
CPUUniCore32State *env = &cpu->env;
env->cp0.c0_cpuid = 0x;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
@@ -65,8 +69,13 @@ static void uc32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
+#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
+#else
+env->uncached_asr = ASR_MODE_PRIV;
+env->regs[31] = 0x0300;
+#endif
tlb_flush(env, 1);
}
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 81c14ff..d14fde5 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -1,15 +1,15 @@
/*
* UniCore32 virtual CPU header
*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation, or (at your option) any
* later version. See the COPYING file in the top-level directory.
*/
-#ifndef __CPU_UC32_H__
-#define __CPU_UC32_H__
+#ifndef QEMU_UNICORE32_CPU_H
+#define QEMU_UNICORE32_CPU_H
#define TARGET_LONG_BITS32
#define TARGET_PAGE_BITS12
@@ -89,8 +89,10 @@ typedef struct CPUUniCore32State {
#define ASR_NZCV(ASR_N | ASR_Z | ASR_C | ASR_V)
#define ASR_RESERVED(~(ASR_M | ASR_I | ASR_NZCV))
-#define UC32_EXCP_PRIV (ASR_MODE_PRIV)
-#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
+#define UC32_EXCP_PRIV (1)
+#define UC32_EXCP_ITRAP (2)
+#define UC32_EXCP_DTRAP (3)
+#define UC32_EXCP_INTR (4)
/* Return the current ASR value. */
target_ulong cpu_asr_read(CPUUniCore32State *env1);
@@ -189,4 +191,4 @@ static inline bool cpu_has_work(CPUUniCore32State *env)
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
-#endif /* __CPU_UC32_H__ */
+#endif /* QEMU_UNICORE32_CPU_H */
--
1.7.0.4
[Qemu-devel] [PATCHv2 07/19] unicore32-softmmu: Add puv3 soc/board support
From: Guan Xuetao
This patch only add puv3 soc/board support, which introduces puv3
machine description, and specifies console type.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c | 93 +
hw/puv3.h | 49 +
hw/unicore32/Makefile.objs|5 ++
4 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3.c
create mode 100644 hw/puv3.h
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 5f04fe3..726a338 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1 +1,2 @@
# Default configuration for unicore32-softmmu
+CONFIG_PUV3=y
diff --git a/hw/puv3.c b/hw/puv3.c
new file mode 100644
index 000..0dc129d
--- /dev/null
+++ b/hw/puv3.c
@@ -0,0 +1,93 @@
+/*
+ * Generic PKUnity SoC machine and board descriptor
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "console.h"
+#include "elf.h"
+#include "exec-memory.h"
+#include "sysbus.h"
+#include "boards.h"
+#include "loader.h"
+#include "pc.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define KERNEL_LOAD_ADDR0x0300
+#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+
+static void puv3_soc_init(CPUUniCore32State *env)
+{
+/* TODO */
+}
+
+static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
+{
+MemoryRegion *ram_memory = g_new(MemoryRegion, 1);
+
+/* SDRAM at address zero. */
+memory_region_init_ram(ram_memory, "puv3.ram", ram_size);
+vmstate_register_ram_global(ram_memory);
+memory_region_add_subregion(get_system_memory(), 0, ram_memory);
+}
+
+static void puv3_load_kernel(const char *kernel_filename)
+{
+int size;
+
+assert(kernel_filename != NULL);
+
+/* only zImage format supported */
+size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
+KERNEL_MAX_SIZE);
+if (size < 0) {
+hw_error("Load kernel error: '%s'\n", kernel_filename);
+}
+
+/* cheat curses that we have a graphic console, only under ocd console */
+graphic_console_init(NULL, NULL, NULL, NULL, NULL);
+}
+
+static void puv3_init(ram_addr_t ram_size, const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+CPUUniCore32State *env;
+
+if (initrd_filename) {
+hw_error("Please use kernel built-in initramdisk.\n");
+}
+
+if (!cpu_model) {
+cpu_model = "UniCore-II";
+}
+
+env = cpu_init(cpu_model);
+if (!env) {
+hw_error("Unable to find CPU definition\n");
+}
+
+puv3_soc_init(env);
+puv3_board_init(env, ram_size);
+puv3_load_kernel(kernel_filename);
+}
+
+static QEMUMachine puv3_machine = {
+.name = "puv3",
+.desc = "PKUnity Version-3 based on UniCore32",
+.init = puv3_init,
+.use_scsi = 0,
+};
+
+static void puv3_machine_init(void)
+{
+qemu_register_machine(&puv3_machine);
+}
+
+machine_init(puv3_machine_init)
diff --git a/hw/puv3.h b/hw/puv3.h
new file mode 100644
index 000..f37adcb
--- /dev/null
+++ b/hw/puv3.h
@@ -0,0 +1,49 @@
+/*
+ * Misc PKUnity SoC declarations
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef QEMU_HW_PUV3_H
+#define QEMU_HW_PUV3_H
+
+#define PUV3_REGS_OFFSET(0x1000) /* 4K is reasonable */
+
+/* PKUnity System bus (AHB): 0xc000 - 0xedff (640MB) */
+#define PUV3_DMA_BASE (0xc020) /* AHB-4 */
+
+/* PKUnity Peripheral bus (APB): 0xee00 - 0xefff (128MB) */
+#define PUV3_GPIO_BASE (0xee50) /* APB-5 */
+#define PUV3_INTC_BASE (0xee60) /* APB-6 */
+#define PUV3_OST_BASE (0xee80) /* APB-8 */
+#define PUV3_PM_BASE(0xeea0) /* APB-10 */
+#define PUV3_PS2_BASE (0xeeb0) /* APB-11 */
+
+/* Hardware interrupts */
+#define PUV3_IRQS_NR(32)
+
+#define PUV3_IRQS_GPIOLOW0 (0)
+#define PUV3_IRQS_GPIOLOW1 (1)
+#define PUV3_IRQS_GPIOLOW2 (2)
+#define PUV3_IRQS_GPIOLOW3 (3)
+#define PUV3_IRQS_GPIOLOW4 (4)
+#define PUV3_IRQS_GPIOLOW5 (5)
+#define PUV3_IRQS_GPIOLOW6 (6)
+#define PUV3_IRQS_GPIOLOW7 (7)
+#define PUV3_IRQS_GPIOHIGH (8)
+#define PUV3_IRQS_PS2_KBD (22)
+#define PUV3_IRQS_PS
[Qemu-devel] [PATCHv2 08/19] unicore32-softmmu: Add puv3 interrupt support
From: Guan Xuetao
This patch adds puv3 interrupt support, include interrupt controler
device simulation and interrupt handler in puv3 machine.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |3 +
hw/puv3.c| 23 +-
hw/puv3_intc.c | 135 ++
3 files changed, 160 insertions(+), 1 deletions(-)
create mode 100644 hw/puv3_intc.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..50554b6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+# PKUnity SoC devices
+hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0dc129d..2870455 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -22,9 +22,30 @@
#define KERNEL_LOAD_ADDR0x0300
#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
+{
+CPUUniCore32State *env = opaque;
+
+assert(irq == 0);
+if (level) {
+cpu_interrupt(env, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+}
+}
+
static void puv3_soc_init(CPUUniCore32State *env)
{
-/* TODO */
+qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
+DeviceState *dev;
+int i;
+
+/* Initialize interrupt controller */
+cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
+for (i = 0; i < PUV3_IRQS_NR; i++) {
+irqs[i] = qdev_get_gpio_in(dev, i);
+}
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
new file mode 100644
index 000..9e0b975
--- /dev/null
+++ b/hw/puv3_intc.c
@@ -0,0 +1,135 @@
+/*
+ * INTC device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq parent_irq;
+
+uint32_t reg_ICMR;
+uint32_t reg_ICPR;
+} PUV3INTCState;
+
+/* Update interrupt status after enabled or pending bits have been changed. */
+static void puv3_intc_update(PUV3INTCState *s)
+{
+if (s->reg_ICMR & s->reg_ICPR) {
+qemu_irq_raise(s->parent_irq);
+} else {
+qemu_irq_lower(s->parent_irq);
+}
+}
+
+/* Process a change in an external INTC input. */
+static void puv3_intc_handler(void *opaque, int irq, int level)
+{
+PUV3INTCState *s = opaque;
+
+DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
+if (level) {
+s->reg_ICPR |= (1 << irq);
+} else {
+s->reg_ICPR &= ~(1 << irq);
+}
+puv3_intc_update(s);
+}
+
+static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3INTCState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x04: /* INTC_ICMR */
+ret = s->reg_ICMR;
+break;
+case 0x0c: /* INTC_ICIP */
+ret = s->reg_ICPR; /* the same value with ICPR */
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3INTCState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* INTC_ICLR */
+case 0x14: /* INTC_ICCR */
+break;
+case 0x04: /* INTC_ICMR */
+s->reg_ICMR = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", (int)offset);
+return;
+}
+puv3_intc_update(s);
+}
+
+static const MemoryRegionOps puv3_intc_ops = {
+.read = puv3_intc_read,
+.write = puv3_intc_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_intc_init(SysBusDevice *dev)
+{
+PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
+
+qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
+sysbus_init_irq(&s->busdev, &s->parent_irq);
+
+s->reg_ICMR = 0;
+s->reg_ICPR = 0;
+
+memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_intc_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc =
[Qemu-devel] [PATCHv2 16/19] unicore32: Split UniCore-F64 instruction helpers from helper.c
From: Guan Xuetao
This patch just splits ucf64 instruction simulation helpers from
helper.c.
Also, two checkpatch warnings are solved.
v1->v2: adjust copyright information for new ucf64_helper.c
Signed-off-by: Guan Xuetao
---
target-unicore32/Makefile.objs |2 +
target-unicore32/helper.c | 330 -
target-unicore32/ucf64_helper.c | 345 +++
3 files changed, 347 insertions(+), 330 deletions(-)
create mode 100644 target-unicore32/ucf64_helper.c
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 6af1089..777f01f 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,6 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += ucf64_helper.o
+
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f9f1960..d6eb758 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -213,333 +213,3 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
return 1;
}
#endif
-
-/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
- Single precition routines have a "s" suffix, double precision a
- "d" suffix. */
-
-/* Convert host exception flags to f64 form. */
-static inline int ucf64_exceptbits_from_host(int host_bits)
-{
-int target_bits = 0;
-
-if (host_bits & float_flag_invalid) {
-target_bits |= UCF64_FPSCR_FLAG_INVALID;
-}
-if (host_bits & float_flag_divbyzero) {
-target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
-}
-if (host_bits & float_flag_overflow) {
-target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
-}
-if (host_bits & float_flag_underflow) {
-target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
-}
-if (host_bits & float_flag_inexact) {
-target_bits |= UCF64_FPSCR_FLAG_INEXACT;
-}
-return target_bits;
-}
-
-uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
-{
-int i;
-uint32_t fpscr;
-
-fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
-i = get_float_exception_flags(&env->ucf64.fp_status);
-fpscr |= ucf64_exceptbits_from_host(i);
-return fpscr;
-}
-
-/* Convert ucf64 exception flags to target form. */
-static inline int ucf64_exceptbits_to_host(int target_bits)
-{
-int host_bits = 0;
-
-if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
-host_bits |= float_flag_invalid;
-}
-if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
-host_bits |= float_flag_divbyzero;
-}
-if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
-host_bits |= float_flag_overflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
-host_bits |= float_flag_underflow;
-}
-if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
-host_bits |= float_flag_inexact;
-}
-return host_bits;
-}
-
-void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
-{
-int i;
-uint32_t changed;
-
-changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
-env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
-
-changed ^= val;
-if (changed & (UCF64_FPSCR_RND_MASK)) {
-i = UCF64_FPSCR_RND(val);
-switch (i) {
-case 0:
-i = float_round_nearest_even;
-break;
-case 1:
-i = float_round_to_zero;
-break;
-case 2:
-i = float_round_up;
-break;
-case 3:
-i = float_round_down;
-break;
-default: /* 100 and 101 not implement */
-cpu_abort(env, "Unsupported UniCore-F64 round mode");
-}
-set_float_rounding_mode(i, &env->ucf64.fp_status);
-}
-
-i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
-set_float_exception_flags(i, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_add(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_add(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_sub(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_sub(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_mul(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
-{
-return float64_mul(a, b, &env->ucf64.fp_status);
-}
-
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
-{
-return float32_div(a, b, &env->ucf64.fp_status);
-}
-
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUn
[Qemu-devel] [PATCHv2 19/19] unicore32-softmmu: Add a minimal curses screen support
From: Guan Xuetao
This patch adds a minimal curses screen support for unicore32-softmmu.
We assume 80*30 screen size to minimize the implementation.
Two problems are not solved, but they are innocuous.
1. curses windows will be blank when switching to monitor screen and back
2. backspace is not handled yet
v1->v2: add extra handler for '\r'
Signed-off-by: Zhang Mengchi
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c | 45 +++--
1 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d6eb758..a9e226b 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -13,6 +13,7 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
+#include "console.h"
#undef DEBUG_UC32
@@ -186,10 +187,50 @@ uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t
creg, uint32_t cop)
return 0;
}
+#ifdef CONFIG_CURSES
+/*
+ * FIXME:
+ * 1. curses windows will be blank when switching back
+ * 2. backspace is not handled yet
+ */
+static void putc_on_screen(unsigned char ch)
+{
+static WINDOW *localwin;
+static int init;
+
+if (!init) {
+/* Assume 80 * 30 screen to minimize the implementation */
+localwin = newwin(30, 80, 0, 0);
+scrollok(localwin, TRUE);
+init = TRUE;
+}
+
+if (isprint(ch)) {
+wprintw(localwin, "%c", ch);
+} else {
+switch (ch) {
+case '\n':
+wprintw(localwin, "%c", ch);
+break;
+case '\r':
+/* If '\r' is put before '\n', the curses window will destroy the
+ * last print line. And meanwhile, '\n' implifies '\r' inside. */
+break;
+default: /* Not handled, so just print it hex code */
+wprintw(localwin, "-- 0x%x --", ch);
+}
+}
+
+wrefresh(localwin);
+}
+#else
+#define putc_on_screen(c) do { } while (0)
+#endif
+
void helper_cp1_putc(target_ulong x)
{
-/* TODO: curses display should be added here for screen output. */
-DPRINTF("%c", x);
+putc_on_screen((unsigned char)x); /* Output to screen */
+DPRINTF("%c", x); /* Output to stdout */
}
#endif
--
1.7.0.4
[Qemu-devel] [PATCHv2 15/19] unicore32-softmmu: Add is_default setting for puv3 machine
From: Guan Xuetao
This patch sets is_default to 1 for puv3 machine, so that
find_default_machine() returns puv3 machine.
Thanks Dunrong for pointing it out.
Cc: Dunrong Huang
Signed-off-by: Guan Xuetao
---
hw/puv3.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/puv3.c b/hw/puv3.c
index 271df97..43f7216 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -119,6 +119,7 @@ static QEMUMachine puv3_machine = {
.name = "puv3",
.desc = "PKUnity Version-3 based on UniCore32",
.init = puv3_init,
+.is_default = 1,
.use_scsi = 0,
};
--
1.7.0.4
[Qemu-devel] [PATCHv2 18/19] unicore32: Close dump-option of cpu_dump_state_ucf64 function
From: Guan Xuetao
Since of tedious output, we close dump-option of cpu_dump_state_ucf64 function.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c74c49a..188bf8c 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2138,7 +2138,7 @@ static const char *cpu_mode_names[16] = {
"UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
};
-#define UCF64_DUMP_STATE
+#undef UCF64_DUMP_STATE
#ifdef UCF64_DUMP_STATE
static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprintf, int flags)
--
1.7.0.4
[Qemu-devel] [PATCHv2 12/19] unicore32-softmmu: Add puv3 dma support
From: Guan Xuetao
This patch adds puv3 dma (Direct Memory Access) support,
include dma device simulation for kernel booting.
v1->v2: Add initialization to ret in puv3_dma_read.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_dma.c| 109 ++
3 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_dma.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index e2a39d6..6df346a 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -71,6 +71,7 @@ hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
hw-obj-$(CONFIG_PUV3) += puv3_pm.o
+hw-obj-$(CONFIG_PUV3) += puv3_dma.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 3a14b27..9acfc5a 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
+sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_dma.c b/hw/puv3_dma.c
new file mode 100644
index 000..85b97bf
--- /dev/null
+++ b/hw/puv3_dma.c
@@ -0,0 +1,109 @@
+/*
+ * DMA device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define PUV3_DMA_CH_NR (6)
+#define PUV3_DMA_CH_MASK(0xff)
+#define PUV3_DMA_CH(offset) ((offset) >> 8)
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t reg_CFG[PUV3_DMA_CH_NR];
+} PUV3DMAState;
+
+static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3DMAState *s = opaque;
+uint32_t ret = 0;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+ret = s->reg_CFG[PUV3_DMA_CH(offset)];
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3DMAState *s = opaque;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+s->reg_CFG[PUV3_DMA_CH(offset)] = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_dma_ops = {
+.read = puv3_dma_read,
+.write = puv3_dma_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_dma_init(SysBusDevice *dev)
+{
+PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev);
+int i;
+
+for (i = 0; i < PUV3_DMA_CH_NR; i++) {
+s->reg_CFG[i] = 0x0;
+}
+
+memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_dma_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_dma_init;
+}
+
+static const TypeInfo puv3_dma_info = {
+.name = "puv3_dma",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3DMAState),
+.class_init = puv3_dma_class_init,
+};
+
+static void puv3_dma_register_type(void)
+{
+type_register_static(&puv3_dma_info);
+}
+
+type_init(puv3_dma_register_type)
--
1.7.0.4
[Qemu-devel] [PATCHv2 17/19] unicore32: Disintegrate cpu_dump_state_ucf64 function
From: Guan Xuetao
This patch disintegrates cpu_dump_state_ucf64 function from cpu_dump_state.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 41 +
1 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 5ee3a59..c74c49a 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2139,11 +2139,11 @@ static const char *cpu_mode_names[16] = {
};
#define UCF64_DUMP_STATE
-void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function
cpu_fprintf,
-int flags)
+#ifdef UCF64_DUMP_STATE
+static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
{
int i;
-#ifdef UCF64_DUMP_STATE
union {
uint32_t i;
float s;
@@ -2155,7 +2155,28 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
float64 f64;
double d;
} d0;
+
+for (i = 0; i < 16; i++) {
+d.d = env->ucf64.regs[i];
+s0.i = d.l.lower;
+s1.i = d.l.upper;
+d0.f64 = d.d;
+cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
+i * 2, (int)s0.i, s0.s,
+i * 2 + 1, (int)s1.i, s1.s);
+cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
+i, (uint64_t)d0.f64, d0.d);
+}
+cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
+}
+#else
+#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
#endif
+
+void cpu_dump_state(CPUUniCore32State *env, FILE *f,
+fprintf_function cpu_fprintf, int flags)
+{
+int i;
uint32_t psr;
for (i = 0; i < 32; i++) {
@@ -2175,19 +2196,7 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f,
fprintf_function cpu_fprint
psr & (1 << 28) ? 'V' : '-',
cpu_mode_names[psr & 0xf]);
-#ifdef UCF64_DUMP_STATE
-for (i = 0; i < 16; i++) {
-d.d = env->ucf64.regs[i];
-s0.i = d.l.lower;
-s1.i = d.l.upper;
-d0.f64 = d.d;
-cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%" PRIx64
"(%8g)\n",
-i * 2, (int)s0.i, s0.s,
-i * 2 + 1, (int)s1.i, s1.s,
-i, (uint64_t)d0.f64, d0.d);
-}
-cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
-#endif
+cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
}
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int
pc_pos)
--
1.7.0.4
[Qemu-devel] [PATCHv2 01/19] unicore32-softmmu: Add unicore32-softmmu build support
From: Guan Xuetao
This patch adds unicore32-softmmu build support, include configure,
makefile, arch_init, and all missing functions needed by softmmu.
Although all missing functions are empty, unicore32-softmmu could
be build successfully.
By 20120804: change QEMU_ARCH_UNICORE32 to 0x4000
Signed-off-by: Guan Xuetao
---
arch_init.c |2 +
arch_init.h |1 +
configure |1 +
default-configs/unicore32-softmmu.mak |1 +
hw/unicore32/Makefile.objs|1 +
target-unicore32/Makefile.objs|2 +-
target-unicore32/helper.c | 27 +++---
target-unicore32/machine.c| 23 +++
target-unicore32/op_helper.c | 24 +++-
target-unicore32/softmmu.c| 39 +
10 files changed, 106 insertions(+), 15 deletions(-)
create mode 100644 default-configs/unicore32-softmmu.mak
create mode 100644 hw/unicore32/Makefile.objs
create mode 100644 target-unicore32/machine.c
create mode 100644 target-unicore32/softmmu.c
diff --git a/arch_init.c b/arch_init.c
index 60823ba..7b65c48 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -91,6 +91,8 @@ int graphic_depth = 15;
#define QEMU_ARCH QEMU_ARCH_SPARC
#elif defined(TARGET_XTENSA)
#define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_UNICORE32)
+#define QEMU_ARCH QEMU_ARCH_UNICORE32
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/arch_init.h b/arch_init.h
index 3dfea3b..547f93c 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -17,6 +17,7 @@ enum {
QEMU_ARCH_SPARC = 2048,
QEMU_ARCH_XTENSA = 4096,
QEMU_ARCH_OPENRISC = 8192,
+QEMU_ARCH_UNICORE32 = 0x4000,
};
extern const uint32_t arch_type;
diff --git a/configure b/configure
index 280726c..efaff00 100755
--- a/configure
+++ b/configure
@@ -935,6 +935,7 @@ sparc64-softmmu \
s390x-softmmu \
xtensa-softmmu \
xtensaeb-softmmu \
+unicore32-softmmu \
"
fi
# the following are Linux specific
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
new file mode 100644
index 000..5f04fe3
--- /dev/null
+++ b/default-configs/unicore32-softmmu.mak
@@ -0,0 +1 @@
+# Default configuration for unicore32-softmmu
diff --git a/hw/unicore32/Makefile.objs b/hw/unicore32/Makefile.objs
new file mode 100644
index 000..b6a3383
--- /dev/null
+++ b/hw/unicore32/Makefile.objs
@@ -0,0 +1 @@
+# For UniCore32 machines and boards
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 2e0e093..6af1089 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,4 @@
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9fe4a37..9b8ff06 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -45,18 +45,26 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifdef CONFIG_USER_ONLY
+void switch_mode(CPUUniCore32State *env, int mode)
+{
+if (mode != ASR_MODE_USER) {
+cpu_abort(env, "Tried to switch out of user mode\n");
+}
+}
+
void do_interrupt(CPUUniCore32State *env)
{
-env->exception_index = -1;
+cpu_abort(env, "NO interrupt in user mode\n");
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
int rw,
- int mmu_idx)
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+ int access_type, int mmu_idx)
{
-env->exception_index = UC32_EXCP_TRAP;
-env->cp0.c4_faultaddr = address;
+cpu_abort(env, "NO mmu fault in user mode\n");
return 1;
}
+#endif
/* These should probably raise undefined insn exceptions. */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
@@ -84,13 +92,6 @@ uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t
insn)
return 0;
}
-void switch_mode(CPUUniCore32State *env, int mode)
-{
-if (mode != ASR_MODE_USER) {
-cpu_abort(env, "Tried to switch out of user mode\n");
-}
-}
-
void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t
val)
{
cpu_abort(env, "banked r29 write\n");
diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
new file mode 100644
index 000..60b2ec1
--- /dev/null
+++ b/target-unicore32/machine.c
@@ -0,0 +1,23 @@
+/*
+ * Generic machine functions for UniCore32 ISA
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is fre
[Qemu-devel] [PATCHv2 02/19] unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support
From: Guan Xuetao
Coprocessor 0 is system control coprocessor, and we need get/set its contents.
Also, all cache/tlb ops shoule be implemented here, but just ignored with no
harm.
Coprocessor 1 is OCD (on-chip-debugger), which is used for faked console,
so we could output chars to this console without graphic card.
TODO: curses display should be added lator for screen output.
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c| 185 +-
target-unicore32/helper.h| 17 ++---
target-unicore32/translate.c | 80 ++-
3 files changed, 233 insertions(+), 49 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9b8ff06..f9f1960 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -14,6 +14,14 @@
#include "helper.h"
#include "host-utils.h"
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
@@ -45,6 +53,146 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifndef CONFIG_USER_ONLY
+void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
+uint32_t cop)
+{
+/*
+ * movc pp.nn, rn, #imm9
+ * rn: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * 5: cache op. reg.
+ * 6: tlb op. reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 1:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c1_sys = val;
+break;
+case 2:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c2_base = val;
+break;
+case 3:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c3_faultstatus = val;
+break;
+case 4:
+if (cop != 0) {
+goto unrecognized;
+}
+env->cp0.c4_faultaddr = val;
+break;
+case 5:
+switch (cop) {
+case 28:
+DPRINTF("Invalidate Entire I&D cache\n");
+return;
+case 20:
+DPRINTF("Invalidate Entire Icache\n");
+return;
+case 12:
+DPRINTF("Invalidate Entire Dcache\n");
+return;
+case 10:
+DPRINTF("Clean Entire Dcache\n");
+return;
+case 14:
+DPRINTF("Flush Entire Dcache\n");
+return;
+case 13:
+DPRINTF("Invalidate Dcache line\n");
+return;
+case 11:
+DPRINTF("Clean Dcache line\n");
+return;
+case 15:
+DPRINTF("Flush Dcache line\n");
+return;
+}
+break;
+case 6:
+if ((cop <= 6) && (cop >= 2)) {
+/* invalid all tlb */
+tlb_flush(env, 1);
+return;
+}
+break;
+default:
+goto unrecognized;
+}
+return;
+unrecognized:
+DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+}
+
+uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
+{
+/*
+ * movc rd, pp.nn, #imm9
+ * rd: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 0: cpuid and cachetype
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 0:
+switch (cop) {
+case 0:
+return env->cp0.c0_cpuid;
+case 1:
+return env->cp0.c0_cachetype;
+}
+break;
+case 1:
+if (cop == 0) {
+return env->cp0.c1_sys;
+}
+break;
+case 2:
+if (cop == 0) {
+return env->cp0.c2_base;
+}
+break;
+case 3:
+if (cop == 0) {
+return env->cp0.c3_faultstatus;
+}
+break;
+case 4:
+if (cop == 0) {
+return env->cp0.c4_faultaddr;
+}
+break;
+}
+DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+return 0;
+}
+
+void helper_cp1_putc(target_ulong x)
+{
+/* TODO: curses display should be added here for screen output. */
+DPRINTF("%c", x);
+}
+#endif
+
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
@@ -66,43 +214,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
}
#endif
-/* These should probably raise undefined insn exceptions. */
-void HELP
[Qemu-devel] [PATCHv2 14/19] unicore32-softmmu: Add maintainer information for UniCore32 machine
From: Guan Xuetao Signed-off-by: Guan Xuetao --- MAINTAINERS |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2d219d2..708ad54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -405,6 +405,14 @@ M: Alexander Graf S: Maintained F: hw/s390-*.c +UniCore32 Machines +- +PKUnity-3 SoC initramfs-with-busybox +M: Guan Xuetao +S: Maintained +F: hw/puv3* +F: hw/unicore32/ + X86 Machines PC -- 1.7.0.4
[Qemu-devel] [PATCHv2 05/19] unicore32-softmmu: Implement softmmu specific functions
From: Guan Xuetao
This patch implements softmmu specific functions, include tlb_fill,
switch_mode, do_interrupt and uc32_cpu_handle_mmu_fault.
So the full exception handlers and page table walking could work now.
Signed-off-by: Guan Xuetao
---
target-unicore32/op_helper.c | 22 -
target-unicore32/softmmu.c | 236 +-
2 files changed, 253 insertions(+), 5 deletions(-)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 6df30db..c63789d 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -267,6 +267,26 @@ uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+TranslationBlock *tb;
+CPUUniCore32State *saved_env;
+unsigned long pc;
+int ret;
+
+saved_env = env;
+env = env1;
+ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
+if (unlikely(ret)) {
+if (retaddr) {
+/* now we have a real cpu fault */
+pc = (unsigned long)retaddr;
+tb = tb_find_pc(pc);
+if (tb) {/* the PC is inside the translated code.
+It means that we have a virtual CPU fault */
+cpu_restore_state(tb, env, pc);
+}
+}
+cpu_loop_exit(env);
+}
+env = saved_env;
}
#endif
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 6fec77e..373f94b 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -14,21 +14,249 @@
#include
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define SUPERPAGE_SIZE (1 << 22)
+#define UC32_PAGETABLE_READ(1 << 8)
+#define UC32_PAGETABLE_WRITE (1 << 7)
+#define UC32_PAGETABLE_EXEC(1 << 6)
+#define UC32_PAGETABLE_EXIST (1 << 2)
+#define PAGETABLE_TYPE(x) ((x) & 3)
+
+
+/* Map CPU modes onto saved register banks. */
+static inline int bank_number(int mode)
+{
+switch (mode) {
+case ASR_MODE_USER:
+case ASR_MODE_SUSR:
+return 0;
+case ASR_MODE_PRIV:
+return 1;
+case ASR_MODE_TRAP:
+return 2;
+case ASR_MODE_EXTN:
+return 3;
+case ASR_MODE_INTR:
+return 4;
+}
+cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
+return -1;
+}
+
void switch_mode(CPUUniCore32State *env, int mode)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+int old_mode;
+int i;
+
+old_mode = env->uncached_asr & ASR_M;
+if (mode == old_mode) {
+return;
+}
+
+i = bank_number(old_mode);
+env->banked_r29[i] = env->regs[29];
+env->banked_r30[i] = env->regs[30];
+env->banked_bsr[i] = env->bsr;
+
+i = bank_number(mode);
+env->regs[29] = env->banked_r29[i];
+env->regs[30] = env->banked_r30[i];
+env->bsr = env->banked_bsr[i];
}
+/* Handle a CPU exception. */
void do_interrupt(CPUUniCore32State *env)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+uint32_t addr;
+int new_mode;
+
+switch (env->exception_index) {
+case UC32_EXCP_PRIV:
+new_mode = ASR_MODE_PRIV;
+addr = 0x08;
+break;
+case UC32_EXCP_ITRAP:
+DPRINTF("itrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x0c;
+break;
+case UC32_EXCP_DTRAP:
+DPRINTF("dtrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x10;
+break;
+case UC32_EXCP_INTR:
+new_mode = ASR_MODE_INTR;
+addr = 0x18;
+break;
+default:
+cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+return;
+}
+/* High vectors. */
+if (env->cp0.c1_sys & (1 << 13)) {
+addr += 0x;
+}
+
+switch_mode(env, new_mode);
+env->bsr = cpu_asr_read(env);
+env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
+env->uncached_asr |= ASR_I;
+/* The PC already points to the proper instruction. */
+env->regs[30] = env->regs[31];
+env->regs[31] = addr;
+env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+}
+
+static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
+int access_type, int is_user, uint32_t *phys_ptr, int *prot,
+target_ulong *page_size)
+{
+int code;
+uint32_t table;
+uint32_t desc;
+uint32_t phys_addr;
+
+/* Pagetable walk. */
+/* Lookup l1 descriptor. */
+table = env->cp0.c2_base & 0xf000;
+table |= (address >> 20) & 0xffc;
+desc = ldl_phys(table);
+code = 0;
+switch (PAGETABLE_TYPE(desc)) {
+case 3:
+/* Superpage */
+if (!(desc & UC32_PAGETABLE_
[Qemu-devel] [PATCHv2 06/19] unicore32-softmmu: Make sure that kernel can access user space
From: Guan Xuetao
As a matter of course, we need to access user space in kernel code,
so we need to correct load/store decoders to indicate correct memory
region.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 36 ++--
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index e37d5be..5ee3a59 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -33,9 +33,16 @@ typedef struct DisasContext {
int condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
+#ifndef CONFIG_USER_ONLY
+int user;
+#endif
} DisasContext;
-#define IS_USER(s) 1
+#ifndef CONFIG_USER_ONLY
+#define IS_USER(s) (s->user)
+#else
+#define IS_USER(s) 1
+#endif
/* These instructions trap after executing, so defer them until after the
conditional executions state has been updated. */
@@ -1554,12 +1561,12 @@ static void do_misc(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store I_offset and R_offset */
static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int i;
+unsigned int mmu_idx;
TCGv tmp;
TCGv tmp2;
tmp2 = load_reg(s, UCOP_REG_N);
-i = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
/* immediate */
if (UCOP_SET_P) {
@@ -1569,17 +1576,17 @@ static void do_ldst_ir(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
if (UCOP_SET_L) {
/* load */
if (UCOP_SET_B) {
-tmp = gen_ld8u(tmp2, i);
+tmp = gen_ld8u(tmp2, mmu_idx);
} else {
-tmp = gen_ld32(tmp2, i);
+tmp = gen_ld32(tmp2, mmu_idx);
}
} else {
/* store */
tmp = load_reg(s, UCOP_REG_D);
if (UCOP_SET_B) {
-gen_st8(tmp, tmp2, i);
+gen_st8(tmp, tmp2, mmu_idx);
} else {
-gen_st32(tmp, tmp2, i);
+gen_st32(tmp, tmp2, mmu_idx);
}
}
if (!UCOP_SET_P) {
@@ -1682,7 +1689,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int val, i;
+unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
TCGv tmp2;
@@ -1703,6 +1710,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
}
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
addr = load_reg(s, UCOP_REG_N);
/* compute total size */
@@ -1747,7 +1755,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
if (UCOP_SET(i)) {
if (UCOP_SET_L) { /* load */
-tmp = gen_ld32(addr, IS_USER(s));
+tmp = gen_ld32(addr, mmu_idx);
if (reg == 31) {
gen_bx(s, tmp);
} else if (user) {
@@ -1775,7 +1783,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
} else {
tmp = load_reg(s, reg);
}
-gen_st32(tmp, addr, IS_USER(s));
+gen_st32(tmp, addr, mmu_idx);
}
j++;
/* no need to add after the last transfer */
@@ -1964,6 +1972,14 @@ static inline void
gen_intermediate_code_internal(CPUUniCore32State *env,
max_insns = CF_COUNT_MASK;
}
+#ifndef CONFIG_USER_ONLY
+if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
+dc->user = 1;
+} else {
+dc->user = 0;
+}
+#endif
+
gen_icount_start();
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
--
1.7.0.4
[Qemu-devel] [PATCHv2 10/19] unicore32-softmmu: Add puv3 gpio support
From: Guan Xuetao
This patch adds puv3 gpio (General Purpose Input/Output) support,
include gpio device simulation and its interrupt support.
v1->v2: Add initialization to ret in puv3_gpio_read.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|6 ++
hw/puv3_gpio.c | 141 ++
3 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_gpio.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index b96722a..c6cc97b 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -69,6 +69,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
+hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 5a8a27c..0354cf6 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,12 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
+sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
+irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
+irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
+irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
+irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
+irqs[PUV3_IRQS_GPIOHIGH], NULL);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c
new file mode 100644
index 000..9436e6c
--- /dev/null
+++ b/hw/puv3_gpio.c
@@ -0,0 +1,141 @@
+/*
+ * GPIO device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq irq[9];
+
+uint32_t reg_GPLR;
+uint32_t reg_GPDR;
+uint32_t reg_GPIR;
+} PUV3GPIOState;
+
+static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3GPIOState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x00:
+ret = s->reg_GPLR;
+break;
+case 0x04:
+ret = s->reg_GPDR;
+break;
+case 0x20:
+ret = s->reg_GPIR;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3GPIOState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x04:
+s->reg_GPDR = value;
+break;
+case 0x08:
+if (s->reg_GPDR & value) {
+s->reg_GPLR |= value;
+} else {
+DPRINTF("Write gpio input port error!");
+}
+break;
+case 0x0c:
+if (s->reg_GPDR & value) {
+s->reg_GPLR &= ~value;
+} else {
+DPRINTF("Write gpio input port error!");
+}
+break;
+case 0x10: /* GRER */
+case 0x14: /* GFER */
+case 0x18: /* GEDR */
+break;
+case 0x20: /* GPIR */
+s->reg_GPIR = value;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+}
+
+static const MemoryRegionOps puv3_gpio_ops = {
+.read = puv3_gpio_read,
+.write = puv3_gpio_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_gpio_init(SysBusDevice *dev)
+{
+PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev);
+
+s->reg_GPLR = 0;
+s->reg_GPDR = 0;
+
+/* FIXME: these irqs not handled yet */
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
+
+memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_gpio_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_
[Qemu-devel] [PATCHv2 09/19] unicore32-softmmu: Add puv3 ostimer support
From: Guan Xuetao
This patch adds puv3 ostimer support, include os timer
device simulation and ptimer support in puv3 machine.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/Makefile.objs |1 +
hw/puv3.c |3 +
hw/puv3_ost.c | 151 +
4 files changed, 156 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_ost.c
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 726a338..4d4fbfc 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,2 +1,3 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
+CONFIG_PTIMER=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 50554b6..b96722a 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -68,6 +68,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+hw-obj-$(CONFIG_PUV3) += puv3_ost.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 2870455..5a8a27c 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -46,6 +46,9 @@ static void puv3_soc_init(CPUUniCore32State *env)
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
}
+
+/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c
new file mode 100644
index 000..dd30cad
--- /dev/null
+++ b/hw/puv3_ost.c
@@ -0,0 +1,151 @@
+/*
+ * OSTimer device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+#include "ptimer.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+/* puv3 ostimer implementation. */
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+QEMUBH *bh;
+qemu_irq irq;
+ptimer_state *ptimer;
+
+uint32_t reg_OSMR0;
+uint32_t reg_OSCR;
+uint32_t reg_OSSR;
+uint32_t reg_OIER;
+} PUV3OSTState;
+
+static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3OSTState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x10: /* Counter Register */
+ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
+break;
+case 0x14: /* Status Register */
+ret = s->reg_OSSR;
+break;
+case 0x1c: /* Interrupt Enable Register */
+ret = s->reg_OIER;
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3OSTState *s = opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* Match Register 0 */
+s->reg_OSMR0 = value;
+if (s->reg_OSMR0 > s->reg_OSCR) {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
+} else {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 +
+(0x - s->reg_OSCR));
+}
+ptimer_run(s->ptimer, 2);
+break;
+case 0x14: /* Status Register */
+assert(value == 0);
+if (s->reg_OSSR) {
+s->reg_OSSR = value;
+qemu_irq_lower(s->irq);
+}
+break;
+case 0x1c: /* Interrupt Enable Register */
+s->reg_OIER = value;
+break;
+default:
+DPRINTF("Bad offset %x\n", (int)offset);
+}
+}
+
+static const MemoryRegionOps puv3_ost_ops = {
+.read = puv3_ost_read,
+.write = puv3_ost_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void puv3_ost_tick(void *opaque)
+{
+PUV3OSTState *s = opaque;
+
+DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
+s->reg_OSCR, s->reg_OSMR0);
+
+s->reg_OSCR = s->reg_OSMR0;
+if (s->reg_OIER) {
+s->reg_OSSR = 1;
+qemu_irq_raise(s->irq);
+}
+}
+
+static int puv3_ost_init(SysBusDevice *dev)
+{
+PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
+
+s->reg_OIER = 0;
+s->reg_OSSR = 0;
+s->reg_OSMR0 = 0;
+s->reg_OSCR = 0;
+
+sysbus_init_irq(dev, &s->irq);
+
+s->bh = qemu_bh_new(puv3_ost_tick, s);
+s->ptimer = ptimer_init(s->bh);
+ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
+
+
[Qemu-devel] [PATCHv2 11/19] unicore32-softmmu: Add puv3 pm support
From: Guan Xuetao
This patch adds puv3 pm (power management) support,
include pm device simulation for kernel booting.
Thank Blue Swirl for pointing out the missing "break".
v1->v2: Add initialization to ret in puv3_pm_read.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_pm.c | 149 ++
3 files changed, 151 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_pm.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index c6cc97b..e2a39d6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -70,6 +70,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
+hw-obj-$(CONFIG_PUV3) += puv3_pm.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0354cf6..3a14b27 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -48,6 +48,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
}
/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c
new file mode 100644
index 000..621c968
--- /dev/null
+++ b/hw/puv3_pm.c
@@ -0,0 +1,149 @@
+/*
+ * Power Management device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t reg_PMCR;
+uint32_t reg_PCGR;
+uint32_t reg_PLL_SYS_CFG;
+uint32_t reg_PLL_DDR_CFG;
+uint32_t reg_PLL_VGA_CFG;
+uint32_t reg_DIVCFG;
+} PUV3PMState;
+
+static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3PMState *s = opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x14:
+ret = s->reg_PCGR;
+break;
+case 0x18:
+ret = s->reg_PLL_SYS_CFG;
+break;
+case 0x1c:
+ret = s->reg_PLL_DDR_CFG;
+break;
+case 0x20:
+ret = s->reg_PLL_VGA_CFG;
+break;
+case 0x24:
+ret = s->reg_DIVCFG;
+break;
+case 0x28: /* PLL SYS STATUS */
+ret = 0x2401;
+break;
+case 0x2c: /* PLL DDR STATUS */
+ret = 0x00100c00;
+break;
+case 0x30: /* PLL VGA STATUS */
+ret = 0x3801;
+break;
+case 0x34: /* DIV STATUS */
+ret = 0x22f52015;
+break;
+case 0x38: /* SW RESET */
+ret = 0x0;
+break;
+case 0x44: /* PLL DFC DONE */
+ret = 0x7;
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3PMState *s = opaque;
+
+switch (offset) {
+case 0x0:
+s->reg_PMCR = value;
+break;
+case 0x14:
+s->reg_PCGR = value;
+break;
+case 0x18:
+s->reg_PLL_SYS_CFG = value;
+break;
+case 0x1c:
+s->reg_PLL_DDR_CFG = value;
+break;
+case 0x20:
+s->reg_PLL_VGA_CFG = value;
+break;
+case 0x24:
+case 0x38:
+break;
+default:
+DPRINTF("Bad offset 0x%x\n", offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_pm_ops = {
+.read = puv3_pm_read,
+.write = puv3_pm_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_pm_init(SysBusDevice *dev)
+{
+PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev);
+
+s->reg_PCGR = 0x0;
+
+memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_pm_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_pm_init;
+}
+
+static const TypeInfo puv3_pm_info = {
+.name = "puv3_pm",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3PMState),
+.class_init = puv3_pm_class_init,
+};
+
+static void puv3_pm_register_type(void)
+{
+type_register_static(&puv3_pm_info);
+}
+
+type_init(puv3_pm_register_
[Qemu-devel] [PATCHv2 13/19] unicore32-softmmu: Add ps2 support
From: Guan Xuetao
This patch adds ps2/keyboard support, and enables CONFIG_PCKBD.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 4d4fbfc..de38577 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,3 +1,4 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
CONFIG_PTIMER=y
+CONFIG_PCKBD=y
diff --git a/hw/puv3.c b/hw/puv3.c
index 9acfc5a..271df97 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -38,6 +38,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
{
qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
DeviceState *dev;
+MemoryRegion *i8042 = g_new(MemoryRegion, 1);
int i;
/* Initialize interrupt controller */
@@ -57,6 +58,10 @@ static void puv3_soc_init(CPUUniCore32State *env)
irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
irqs[PUV3_IRQS_GPIOHIGH], NULL);
+
+/* Keyboard (i8042), mouse disabled for nographic */
+i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
+memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
--
1.7.0.4
[Qemu-devel] [PATCHv2 00/19] unicore32: Add unicore32-softmmu support
From: Guan Xuetao These patches implement softmmu support on unicore32 architecture. v1->v2: Correct maybe-uninitialized warning in gpio/pm/dma handlers. UniCore32 CPU is embedded in PKUnity-3 SoC, so we add necessary puv3 devices simulation codes together. Only minimal system control modules are simulated, to make linux kernel boot and busybox run in initramfs. Thanks Andreas Farber, Blue Swirl, Chen Weiren and Dunrong Huang for their priceless advice. Any advice is greatly appreciated. Thanks, Guan Xuetao --- Andreas Färber (1): target-unicore32: Drop UC32_CPUID macros Guan Xuetao (18): unicore32-softmmu: Add unicore32-softmmu build support unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable unicore32-softmmu: Implement softmmu specific functions unicore32-softmmu: Make sure that kernel can access user space unicore32-softmmu: Add puv3 soc/board support unicore32-softmmu: Add puv3 interrupt support unicore32-softmmu: Add puv3 ostimer support unicore32-softmmu: Add puv3 gpio support unicore32-softmmu: Add puv3 pm support unicore32-softmmu: Add puv3 dma support unicore32-softmmu: Add ps2 support unicore32-softmmu: Add maintainer information for UniCore32 machine unicore32-softmmu: Add is_default setting for puv3 machine unicore32: Split UniCore-F64 instruction helpers from helper.c unicore32: Disintegrate cpu_dump_state_ucf64 function unicore32: Close dump-option of cpu_dump_state_ucf64 function unicore32-softmmu: Add a minimal curses screen support MAINTAINERS |8 + arch_init.c |2 + arch_init.h |1 + configure |1 + cpu-exec.c|1 + default-configs/unicore32-softmmu.mak |4 + hw/Makefile.objs |7 + hw/puv3.c | 131 + hw/puv3.h | 49 hw/puv3_dma.c | 109 +++ hw/puv3_gpio.c| 141 + hw/puv3_intc.c| 135 + hw/puv3_ost.c | 151 ++ hw/puv3_pm.c | 149 ++ hw/unicore32/Makefile.objs|6 + linux-user/main.c |3 +- target-unicore32/Makefile.objs|4 +- target-unicore32/cpu.c| 19 +- target-unicore32/cpu.h| 18 +- target-unicore32/helper.c | 511 +++-- target-unicore32/helper.h | 17 +- target-unicore32/machine.c| 23 ++ target-unicore32/op_helper.c | 44 +++- target-unicore32/softmmu.c| 267 + target-unicore32/translate.c | 159 +-- target-unicore32/ucf64_helper.c | 345 ++ 26 files changed, 1904 insertions(+), 401 deletions(-) create mode 100644 default-configs/unicore32-softmmu.mak create mode 100644 hw/puv3.c create mode 100644 hw/puv3.h create mode 100644 hw/puv3_dma.c create mode 100644 hw/puv3_gpio.c create mode 100644 hw/puv3_intc.c create mode 100644 hw/puv3_ost.c create mode 100644 hw/puv3_pm.c create mode 100644 hw/unicore32/Makefile.objs create mode 100644 target-unicore32/machine.c create mode 100644 target-unicore32/softmmu.c create mode 100644 target-unicore32/ucf64_helper.c
