Re: [Qemu-devel] [RFC] acpi: add reset register to fadt

2015-03-30 Thread Reza Jelveh 
On Mon, Mar 30, 2015 at 2:36 PM, Igor Mammedov imamm...@redhat.com wrote:

 you are extending structure beyond of what specified by ACPI 1.0b spec,
 that might break guests.
 We probably can't change revision since Windows ACPI implementation
 is mostly 1.0b based so we are stuck with it.
 Patch needs to be tested with Windows guests starting with XP.


Works fine with XP as long as you don't use q35, but i guess that's
unsupported by xp by default.


 related issue,
 adding fields without changing major version to a corresponding
 one doesn't look correct.


What do you suggest? saying we support 2.0a just because of introducing
reset_reg is not really valid is it?

[Qemu-devel] [RFC PATCH v2] acpi: add reset register to fadt

2015-03-30 Thread Reza Jelveh 
Some operating systems such as FreeBSD and Mac OSX need the reset_register
section of the FADT filled to know which port to write to for a system reset.

Signed-off-by: Reza Jelveh fish...@saucelabs.com
---
 hw/i386/acpi-build.c | 9 +
 hw/i386/acpi-defs.h  | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d0a5c85..d029896 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -338,6 +338,8 @@ build_facs(GArray *table_data, GArray *linker, PcGuestInfo 
*guest_info)
 /* Load chipset information in FADT */
 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
 {
+Object *lpc = ich9_lpc_find();
+
 fadt-model = 1;
 fadt-reserved1 = 0;
 fadt-sci_int = cpu_to_le16(pm-sci_int);
@@ -361,6 +363,13 @@ static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, 
AcpiPmInfo *pm)
   (1  ACPI_FADT_F_SLP_BUTTON) |
   (1  ACPI_FADT_F_RTC_S4));
 fadt-flags |= cpu_to_le32(1  ACPI_FADT_F_USE_PLATFORM_CLOCK);
+if (lpc) {
+  fadt-flags |= cpu_to_le32(1  ACPI_FADT_F_RESET_REG_SUP);
+  fadt-reset_val = 0xA;
+  fadt-reset_reg.address_space_id   = aml_system_io;
+  fadt-reset_reg.register_bit_width = 8;
+  fadt-reset_reg.address= ICH9_RST_CNT_IOPORT;
+}
 /* APIC destination mode (Flat Logical) has an upper limit of 8 CPUs
  * For more than 8 CPUs, Clustered Logical mode has to be used
  */
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
index c4468f8..960c833 100644
--- a/hw/i386/acpi-defs.h
+++ b/hw/i386/acpi-defs.h
@@ -132,6 +132,8 @@ struct AcpiFadtDescriptorRev1
 uint8_t  reserved4a; /* Reserved */
 uint8_t  reserved4b; /* Reserved */
 uint32_t flags;
+Acpi20GenericAddress reset_reg;
+uint8_t reset_val;
 } QEMU_PACKED;
 typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
 
-- 
2.3.4

[Qemu-devel] [RFC] acpi: add reset register to fadt

2015-03-28 Thread Reza Jelveh 
Some operating systems such as FreeBSD and Mac OSX need the reset_register
section of the FADT filled to know which port to write to for a system reset.

What is the right way to set the reset_val and the reset addr in this case?
---
 hw/i386/acpi-build.c | 5 +
 hw/i386/acpi-defs.h  | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d0a5c85..21c1453 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -361,6 +361,11 @@ static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, 
AcpiPmInfo *pm)
   (1  ACPI_FADT_F_SLP_BUTTON) |
   (1  ACPI_FADT_F_RTC_S4));
 fadt-flags |= cpu_to_le32(1  ACPI_FADT_F_USE_PLATFORM_CLOCK);
+fadt-flags |= cpu_to_le32(1  ACPI_FADT_F_RESET_REG_SUP);
+fadt-reset_val = 0xf;
+fadt-reset_reg.address_space_id   = aml_system_io;
+fadt-reset_reg.register_bit_width = 8;
+fadt-reset_reg.address= ICH9_RST_CNT_IOPORT;
 /* APIC destination mode (Flat Logical) has an upper limit of 8 CPUs
  * For more than 8 CPUs, Clustered Logical mode has to be used
  */
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
index c4468f8..960c833 100644
--- a/hw/i386/acpi-defs.h
+++ b/hw/i386/acpi-defs.h
@@ -132,6 +132,8 @@ struct AcpiFadtDescriptorRev1
 uint8_t  reserved4a; /* Reserved */
 uint8_t  reserved4b; /* Reserved */
 uint32_t flags;
+Acpi20GenericAddress reset_reg;
+uint8_t reset_val;
 } QEMU_PACKED;
 typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
 
-- 
2.3.4

Re: [Qemu-devel] [edk2] license for binary drivers

2014-08-06 Thread Reza Jelveh 
On 06/08/14 14:51, Andrew Fish wrote:
 How you write a GPL licensed FAT driver seems like a legal quagmire. Probably 
 something better discussed with a lawyer.  From the outside looking in it 
 seems like the IP rights are enforced by charging licensing fees to devices 
 that support FAT. So free can still cost you….

This is about whether a Hfs driver under the GPL is acceptable not about the
FAT driver really. And about how legal it is to bundle these in a firmware.

The question arises because I want to know how legal it is to bundle these
things together along with Qemu

Thanks,
Reza

[Qemu-devel] [PATCH_v2] ahci.c: mask unused flags when reading size PRDT DBC

2014-07-01 Thread reza . jelveh 
From: Reza Jelveh reza.jel...@tuhh.de

The data byte count(DBC) read from the description information is defined for
bits 21:00. Bits 30:22 are reserved and bit 31 is the Interrupt on Completion
(I) flag.

Completion interrupts are triggered after every transaction instead of on
I-flag in QEMU. tbl_entry_size is a signed integer and improperly reading the
DBC leads to a negative offset that causes sglist allocation to fail.

Signed-off-by: Reza Jelveh reza.jel...@tuhh.de
---
This requires a custom ovmf image with sata controller for testing:

http://reza.jelveh.me/assets/OVMF.fd.bz2

Signed-off-by: Reza Jelveh reza.jel...@tuhh.de
---
 hw/ide/ahci.c | 11 ---
 hw/ide/ahci.h |  2 ++
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9bae22e..cd140d1 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -639,6 +639,11 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t 
*cmd_fis)
 }
 }
 
+static int prdt_tbl_entry_size(const AHCI_SG *tbl)
+{
+return (le32_to_cpu(tbl-flags_size)  AHCI_PRDT_SIZE_MASK) + 1;
+}
+
 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 {
 AHCICmdHdr *cmd = ad-cur_cmd;
@@ -681,7 +686,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList 
*sglist, int offset)
 sum = 0;
 for (i = 0; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
-tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1);
+tbl_entry_size = prdt_tbl_entry_size(tbl[i]);
 if (offset = (sum + tbl_entry_size)) {
 off_idx = i;
 off_pos = offset - sum;
@@ -700,12 +705,12 @@ static int ahci_populate_sglist(AHCIDevice *ad, 
QEMUSGList *sglist, int offset)
 qemu_sglist_init(sglist, qbus-parent, (sglist_alloc_hint - off_idx),
  ad-hba-as);
 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
-le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
+prdt_tbl_entry_size(tbl[off_idx]) - off_pos);
 
 for (i = off_idx + 1; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
-le32_to_cpu(tbl[i].flags_size) + 1);
+prdt_tbl_entry_size(tbl[i]));
 }
 }
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 9a4064f..f418b30 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -201,6 +201,8 @@
 
 #define AHCI_COMMAND_TABLE_ACMD0x40
 
+#define AHCI_PRDT_SIZE_MASK0x3f
+
 #define IDE_FEATURE_DMA1
 
 #define READ_FPDMA_QUEUED  0x60
-- 
1.9.2

[Qemu-devel] [PATCH] ahci.c: mask unused flags when reading size PRDT DBC

2014-06-29 Thread reza . jelveh 
From: Reza Jelveh reza.jel...@tuhh.de

The data byte count(DBC) read from the description information is defined for
21:00. 30:22 are reserved and 31 is the Interrupt on Completion (I) flag.

Interrupt is not implemented in QEMU. tbl_entry_size is a signed integer and
improperly reading the DBC leads to a negative offset that causes sglist
allocation to fail.

Signed-off-by: Reza Jelveh reza.jel...@tuhh.de
---
 hw/ide/ahci.c | 12 +---
 hw/ide/ahci.h |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9bae22e..93aa981 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -639,6 +639,12 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t 
*cmd_fis)
 }
 }
 
+static int prdt_tbl_entry_size(const AHCI_SG tbl)
+{
+return (le32_to_cpu(tbl.flags_size)  AHCI_PRDT_SIZE_MASK) + 1;
+}
+
+
 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 {
 AHCICmdHdr *cmd = ad-cur_cmd;
@@ -681,7 +687,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList 
*sglist, int offset)
 sum = 0;
 for (i = 0; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
-tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1);
+tbl_entry_size = prdt_tbl_entry_size(tbl[i]);
 if (offset = (sum + tbl_entry_size)) {
 off_idx = i;
 off_pos = offset - sum;
@@ -700,12 +706,12 @@ static int ahci_populate_sglist(AHCIDevice *ad, 
QEMUSGList *sglist, int offset)
 qemu_sglist_init(sglist, qbus-parent, (sglist_alloc_hint - off_idx),
  ad-hba-as);
 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
-le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
+prdt_tbl_entry_size(tbl[off_idx]) - off_pos);
 
 for (i = off_idx + 1; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
-le32_to_cpu(tbl[i].flags_size) + 1);
+prdt_tbl_entry_size(tbl[i]));
 }
 }
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 9a4064f..f418b30 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -201,6 +201,8 @@
 
 #define AHCI_COMMAND_TABLE_ACMD0x40
 
+#define AHCI_PRDT_SIZE_MASK0x3f
+
 #define IDE_FEATURE_DMA1
 
 #define READ_FPDMA_QUEUED  0x60
-- 
1.9.2

[Qemu-devel] [PATCH] ahci.c: mask unused flags when reading size PRDT DBC

2014-06-29 Thread reza . jelveh 
This requires a custom ovmf image with sata controller for testing [0]

[0]: http://reza.jelveh.me/assets/OVMF.fd.bz2

Re: [Qemu-devel] [PATCH] ahci.c: mask the interrupt on complete flag to allow ahci.c to read the correct size for the PRDT

2014-06-27 Thread Reza Jelveh 
On 27/06/14 18:19, Alexander Graf wrote:
 I do agree that this should have been in the patch description. Reza, 
 could you please repost this with a proper patch description and as a 
 checkpatch.pl compliant patch? Also please CC me on the next iteration :).

Sorry about this, I didn't see it when I posted the 2nd version of the patch.

New version is attached.
From fd18e0a7f287cbe176dbb98a530dd54ea3cc27c7 Mon Sep 17 00:00:00 2001
From: Reza Jelveh reza.jel...@tuhh.de
Date: Fri, 27 Jun 2014 01:13:19 +0200
Subject: [PATCH] ahci.c: mask the interrupt on complete flag to allow ahci.c
 to read the correct size for the PRDT

The last PRDT usually sets the I bit set, but qemu does not emulate it. The I bit needs to be masked when interpreting the length.

Signed-off-by: Reza Jelveh reza.jel...@tuhh.de
---
 hw/ide/ahci.c | 12 +---
 hw/ide/ahci.h |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9bae22e..93aa981 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -639,6 +639,12 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
 }
 }
 
+static int prdt_tbl_entry_size(const AHCI_SG tbl)
+{
+return (le32_to_cpu(tbl.flags_size)  AHCI_PRDT_SIZE_MASK) + 1;
+}
+
+
 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 {
 AHCICmdHdr *cmd = ad-cur_cmd;
@@ -681,7 +687,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 sum = 0;
 for (i = 0; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
-tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1);
+tbl_entry_size = prdt_tbl_entry_size(tbl[i]);
 if (offset = (sum + tbl_entry_size)) {
 off_idx = i;
 off_pos = offset - sum;
@@ -700,12 +706,12 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 qemu_sglist_init(sglist, qbus-parent, (sglist_alloc_hint - off_idx),
  ad-hba-as);
 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
-le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
+prdt_tbl_entry_size(tbl[off_idx]) - off_pos);
 
 for (i = off_idx + 1; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
-le32_to_cpu(tbl[i].flags_size) + 1);
+prdt_tbl_entry_size(tbl[i]));
 }
 }
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 9a4064f..f418b30 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -201,6 +201,8 @@
 
 #define AHCI_COMMAND_TABLE_ACMD0x40
 
+#define AHCI_PRDT_SIZE_MASK0x3f
+
 #define IDE_FEATURE_DMA1
 
 #define READ_FPDMA_QUEUED  0x60
-- 
1.9.2

[Qemu-devel] [PATCH] ahci.c: mask the interrupt on complete flag to allow ahci.c to read the correct size for the PRDT

2014-06-26 Thread Reza Jelveh 
Signed-off-by: Reza Jelveh reza.jel...@tuhh.de
---
 hw/ide/ahci.c | 11 ---
 hw/ide/ahci.h |  2 ++
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9bae22e..ee3613f 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -639,6 +639,11 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t 
*cmd_fis)
 }
 }
 
+static int prdt_tbl_entry_size(const AHCI_SG tbl) {
+  return (le32_to_cpu(tbl.flags_size)  AHCI_PRDT_SIZE_MASK) + 1;
+}
+
+
 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 {
 AHCICmdHdr *cmd = ad-cur_cmd;
@@ -681,7 +686,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList 
*sglist, int offset)
 sum = 0;
 for (i = 0; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
-tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1);
+tbl_entry_size = prdt_tbl_entry_size(tbl[i]);
 if (offset = (sum + tbl_entry_size)) {
 off_idx = i;
 off_pos = offset - sum;
@@ -700,12 +705,12 @@ static int ahci_populate_sglist(AHCIDevice *ad, 
QEMUSGList *sglist, int offset)
 qemu_sglist_init(sglist, qbus-parent, (sglist_alloc_hint - off_idx),
  ad-hba-as);
 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
-le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
+prdt_tbl_entry_size(tbl[off_idx]) - off_pos);
 
 for (i = off_idx + 1; i  sglist_alloc_hint; i++) {
 /* flags_size is zero-based */
 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
-le32_to_cpu(tbl[i].flags_size) + 1);
+prdt_tbl_entry_size(tbl[i]));
 }
 }
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 9a4064f..f418b30 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -201,6 +201,8 @@
 
 #define AHCI_COMMAND_TABLE_ACMD0x40
 
+#define AHCI_PRDT_SIZE_MASK0x3f
+
 #define IDE_FEATURE_DMA1
 
 #define READ_FPDMA_QUEUED  0x60
-- 
1.9.2