[PATCH] hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
When Enabled bit is cleared in GITS_CTLR,ITS feature continues
to be enabled.This patch fixes the issue.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 84bcbb5f56..c929a9cb5c 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -896,13 +896,14 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset,
switch (offset) {
case GITS_CTLR:
-s->ctlr |= (value & ~(s->ctlr));
-
-if (s->ctlr & ITS_CTLR_ENABLED) {
+if (value & R_GITS_CTLR_ENABLED_MASK) {
+s->ctlr |= ITS_CTLR_ENABLED;
extract_table_params(s);
extract_cmdq_params(s);
s->creadr = 0;
process_cmdq(s);
+} else {
+s->ctlr &= ~ITS_CTLR_ENABLED;
}
break;
case GITS_CBASER:
--
2.27.0
RE: [for-6.2] hw/intc/arm_gicv3: Update cached state after acknowledging LPI
Since LPIs do not have an active or active and pending state,the current implementation only clears the LPI pending state from the pending table once ICC_IAR1_EL1 acknowledges the interrupt.But, as part of gicv3_lpi_pending() processing, cs->hpplpi is updated with the next best priotiy lpi (only if the current acknowledged irq was best priority irq).By calling gicv3_redist_update() in icc_activate_irq(), we are re-initiating high priority irqs scan in redistributor and if applicable trigger of next best pending lpi from the latest cs->hpplpi info(which otherwise would have happened on next irq trigger from source).Is this the behaviour expected? ThanksShashi Sent from Mail for Windows From: Peter MaydellSent: November 23, 2021 12:46 PMTo: qemu-...@nongnu.org; qemu-devel@nongnu.orgCc: Alex Bennée; Shashi MallelaSubject: Re: [for-6.2] hw/intc/arm_gicv3: Update cached state after acknowledging LPI On Tue, 23 Nov 2021 at 17:10, Peter Maydell wrote:> > In gicv3_redist_lpi_pending() we update cs->hpplpi to indicate the> new highest priority pending LPI after changing the requested LPI> pending bit. However the overall highest priority pending interrupt> information won't be updated unless we call gicv3_redist_update().> We do that from the callsite in gicv3-redist_process_lpi(), but not> from the callsite in icc_activate_irq(). The effect is that when the> guest acknowledges an LPI by reading ICC_IAR1_EL1, we mark it as not> pending in the data structure but still leave it in cs->hppi so will> offer it to the guest again.> > The effect is that if we are using an emulated GICv3 and ITS and> using devices which use LPIs (ie PCI devices) then Linux will> complain "irq 54: nobody cared" and then hang (probably because the> stale bogus interrupt info meant we never tried to deliver some other> real interrupt). Hmm; this is definitely a bug, but maybe it's not the cause ofthe symptoms listed above -- I've just seen them again evenwith this fix. I'll keep digging... -- PMM
RE: [PATCH v8 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
From: Leif LindholmSent: November 11, 2021 1:21 PMTo: Peter MaydellCc: Shashi Mallela; Radoslaw Biernacki; Michael S. Tsirkin; Igor Mammedov; qemu-arm; QEMU Developers; Eric Auger; narmstr...@baylibre.com; Alex Bennée; Marcin JuszkiewiczSubject: Re: [PATCH v8 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC On Thu, Nov 11, 2021 at 16:55:09 +, Peter Maydell wrote:> On Tue, 9 Nov 2021 at 22:52, Leif Lindholm wrote:> >> > On Tue, Nov 09, 2021 at 21:21:46 +, Peter Maydell wrote:> > > The other thing we should nail down is how the user is going to> > > select which flavour of machine they want to provide. Three> > > options:> > > (1) no control, QEMU just emulates whatever the newest flavour is.> > > User needs to go find a firmware image new enough to cope.> > > (2) different flavours exposed as different machine types> > > (analogous to how we have musca-a and musca-b1, or raspi3ap and> > > raspi3b, for instance). Old user command lines keep working> > > because -M sbsa-ref doesn't change; the new stuff would be> > > available via -M sbsa-ref-2 or whatever.> > > (3) different flavours exposed via a property> > > (so you would have -M sbsa-ref,machine-revision=2 or something).> > > If the revision defaults to 1 then old user setups still work> > > but everybody starts to have to cart around an extra command> > > line argument. If it defaults to "newest we know about" you> > > get the opposite set of tradeoffs.> >> > I'm leaning towards (1), at least while working towards a "complete"> > platform (when we may still add/change features, but not how those> > features are communicated to the firmware).> > That's certainly the easiest on the QEMU side; you know the> userbase so would know whether that kind of compat break is> going to be OK with them.> > Q1: who is going to write the code for this? Me, my team, and perhaps a little bit of help from Shashi where itintersects his code. > Q2: do we want to try to land "ITS in sbsa-ref" in 6.2? Given> we're in freeze we're quite short of time even if we handwave> the fact it's a new feature, not a bugfix, so I would lean> towards 'no'... Shashi - what is your feeling?If we could make ITS support depend on the platform version beingcommunicated through TF-A, we could simplify the transition a lot.But that would definitely mean missing 6.2. Sounds okay to me too. Peter - could we sneak in an "add version node to DT" into 6.2? / Leif
[PATCH] hw/intc: GIC maintenance interrupt not triggered
During sbsa acs level 3 testing,it is seen that the GIC
maintenance interrupts are not triggered and the related test
cases failed.On debugging the cause,found that the value of
MISR register (from maintenance_interrupt_state()) was being
passed to qemu_set_irq() as level.Updated logic to set level
to 1 if any of the maintenance interrupt attributes are set.
Confirmed that the GIC maintanence interrupts are triggered and
sbsa acs test cases passed with this change.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_cpuif.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 462a35f66e..34691d4fe2 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -418,7 +418,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
}
if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
-maintlevel = maintenance_interrupt_state(cs);
+if (maintenance_interrupt_state(cs)) {
+maintlevel = 1;
+}
}
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
--
2.27.0
Re: SMMU Stage 2 translation in QEMU
Hi Eric, On Mon, 2021-09-13 at 10:19 +0200, Eric Auger wrote: > Hi Shashi, > > On 9/10/21 3:32 PM, shashi.mall...@linaro.org wrote: > > So that would be the driver code running in guest OS because i see > > tables being setup by arm-smmu driver code in linux,which is > > similar to > > what happens with ITS(table base addresses programmed in registers > > by > > linux driver). > Stage2 SMMU tables are generally not used today. Only stage 1 is > used, > even with VFIO (with KVM). The stage 2 SMMU capability is required for qemu sbsa reference platform to satisfy the sbsa level 3 acs(arm compliance suite) requirements. > SMMUv3 upstream driver does not support S1+S2 (nested). It only > supports > either S1 or S2. Enabling S2 can be done through VFIO driver, if you > select the VFIO_TYPE1_NESTING_IOMMU IOMMU type. This then calls IOMMU > .enable_nesting = arm_smmu_enable_nesting which sets smmu_domain- > >stage > = ARM_SMMU_DOMAIN_NESTED. But the name is misleading as it actually > forces the use of S2 instead of S1. > > However if you look at QEMU VFIO code, no one uses > VFIO_TYPE1_NESTING_IOMMU. Since the current smmuv3 implementation in qemu advertises only stage 1 support,from the qemu device point of view is the stage 2 support included in the integration effort you mentioned or does it need to be taken up from scratch? > > Note I have worked on 2 stage integration for years, without much > success yet: > [RFC v9 00/29] vSMMUv3/pSMMUv3 2 stage VFIO integration > > [PATCH v15 00/12] SMMUv3 Nested Stage Setup (IOMMU part) > [PATCH v13 00/13] SMMUv3 Nested Stage Setup (VFIO part) > > > Thanks > > Eric > > On Fri, 2021-09-10 at 13:54 +0100, Peter Maydell wrote: > > > On Fri, 10 Sept 2021 at 13:39, wrote: > > > > I am referring to the latter,"purely emulated QEMU with an > > > > emulated > > > > SMMU that handles accesses to emulated devices" > > > In that case, the stage 2 tables are set up by the guest > > > code (running at emulated EL2), just as they would be if > > > it were running on real hardware. > > > > > > -- PMM
[PATCH v9 9/9] tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3 ITS changes. Full diff of new file disassembly: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 4]Signature : "IORT"[IO Remapping Table] [004h 0004 4] Table Length : 007C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 07 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC" [018h 0024 4] Oem Revision : 0001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4]Asl Compiler Revision : 0001 [024h 0036 4] Node Count : 0002 [028h 0040 4] Node Offset : 0030 [02Ch 0044 4] Reserved : [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 00 [034h 0052 4] Reserved : [038h 0056 4]Mapping Count : [03Ch 0060 4] Mapping Offset : [040h 0064 4] ItsCount : 0001 [044h 0068 4] Identifiers : [048h 0072 1] Type : 02 [049h 0073 2] Length : 0034 [04Bh 0075 1] Revision : 00 [04Ch 0076 4] Reserved : [050h 0080 4]Mapping Count : 0001 [054h 0084 4] Mapping Offset : 0020 [058h 0088 8]Memory Properties : [IORT Memory Access Properties] [058h 0088 4] Cache Coherency : 0001 [05Ch 0092 1]Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [05Dh 0093 2] Reserved : [05Fh 0095 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [060h 0096 4]ATS Attribute : [064h 0100 4] PCI Segment Number : [068h 0104 1]Memory Size Limit : 00 [069h 0105 3] Reserved : 00 [068h 0104 4] Input base : [06Ch 0108 4] ID Count : [070h 0112 4] Output Base : [074h 0116 4] Output Reference : 0030 [078h 0120 4]Flags (decoded below) : Single Mapping : 0 Raw Table Data: Length 124 (0x7C) : 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPCBXPC 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // 0... 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .4.. 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // ... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0... Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov Reviewed-by: Peter Maydell --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binar
[PATCH v9 8/9] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 29 +++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 73e9c6bb7c..1d59f0e59f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -584,6 +584,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -621,7 +627,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -655,6 +661,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2742,6 +2756,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2791,8 +2811,13 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 2)
static void virt_machine_6_1_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_6_2_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
+
+/* qemu ITS was introduced with 6.2 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 1)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9661c46699..b461b8d261 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v9 7/9] tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov Reviewed-by: Peter Maydell --- tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ef211df59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v9 6/9] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
Tested-by: Neil Armstrong
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc/arm_gicv3_redist.c | 141 +
hw/intc/gicv3_internal.h | 9 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+(cs->hpplpi.prio != 0xff)) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+for (i = 0; i < s->num_cpu; i++) {
+gicv3_redist_update_lpi(&s->cpu[i]);
+}
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index a032d505f5..462a35f66e 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) &&
+!(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 03c6800997..efb1b5ecab 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -233,6 +233,7 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t
value, uint32_t offset,
uint64_t cte = 0;
bool cte_valid = false;
bool result = false;
+uint64_t rdbase;
if (cmd == NONE) {
devid = offset;
@@ -293,6 +294,18 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t
value, uint32_t offset,
* Current implementation only supports rdbase == procnum
* Hence rdbase physical address is ignored
*/
+rdbase = (cte & GITS_CTE_RDBASE_PROCNUM_MASK) >> 1U;
+
+if (rdbase > s->gicv3->num_cpu) {
+return result;
+}
+
+if ((cmd == CLEAR) || (cmd == DISCAR
[PATCH v9 3/9] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c | 319 +++
hw/intc/gicv3_internal.h | 40 +
2 files changed, 359 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 8234939ccc..fcd152271a 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -50,6 +50,318 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return true;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return false;
+}
+
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+if (res != MEMTX_OK) {
+return false;
+} else {
+return true;
+}
+}
+
+static bool process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+bool result = false;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return result;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
+rdbase &= RDBASE_PROCNUM_MASK;
+
+valid = (value & CMD_FIELD_VALID_MASK);
+
+if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+result = update_cte(s, icid, valid, rdbase);
+}
+
+return result;
+}
+
+static bool update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ (itt_addr << GITS_DTE_ITTADDR_SHIFT);
+}
+} else {
+return true;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+
[PATCH v9 4/9] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 365 -
hw/intc/gicv3_internal.h | 12 +
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 378 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index fcd152271a..03c6800997 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
+typedef struct {
+uint32_t iteh;
+uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -50,6 +66,329 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static bool update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) +
+ sizeof(uint32_t))), ite.itel, MEMTXATTRS_UNSPECIFIED,
+ &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + (eventid * (sizeof(uint64_t) +
+ sizeof(uint32_t))) + sizeof(uint32_t), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+}
+if (res != MEMTX_OK) {
+return false;
+} else {
+return true;
+}
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+IteEntry ite = {};
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+ite.itel = address_space_ldq_le(as, itt_addr +
+(eventid * (sizeof(uint64_t) +
+sizeof(uint32_t))), MEMTXATTRS_UNSPECIFIED,
+res);
+
+if (*res == MEMTX_OK) {
+ite.iteh = address_space_ldl_le(as, itt_addr +
+(eventid * (sizeof(uint64_t) +
+sizeof(uint32_t))) + sizeof(uint32_t),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (ite.itel & TABLE_ENTRY_VALI
[PATCH v9 5/9] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 5 -
hw/intc/arm_gicv3_redist.c | 12 +---
hw/intc/gicv3_internal.h | 2 ++
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 5beb7c4235..4164500ea9 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -384,7 +384,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -399,6 +401,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return true;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 53da703ed8..2108abfe9c 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+if (value & GICR_CTLR_ENABLE_LPIS) {
+cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+} else {
+cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+}
+}
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 1966444790..530d1c1789 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,8 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_SHIFT 17
+
/* 16 bits EventId */
#define GICD_TYPER_IDBITS0xf
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/int
[PATCH v9 2/9] hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 431 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 83ece7c4c1..8234939ccc 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+uint64_t result = 0;
+
+switch (page_sz) {
+case GITS_PAGE_SIZE_4K:
+case GITS_PAGE_SIZE_16K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12;
+break;
+
+case GITS_PAGE_SIZE_64K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+break;
+
+default:
+break;
+}
+return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+uint16_t num_pages = 0;
+uint8_t page_sz_type;
+uint8_t type;
+uint32_t page_sz = 0;
+uint64_t value;
+
+for (int i = 0; i < 8; i++) {
+value = s->baser[i];
+
+if (!value) {
+continue;
+}
+
+page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+switch (page_sz_type) {
+case 0:
+page_sz = GITS_PAGE_SIZE_4K;
+break;
+
+case 1:
+page_sz = GITS_PAGE_SIZE_16K;
+break;
+
+case 2:
+case 3:
+page_sz = GITS_PAGE_SIZE_64K;
+break;
+
+default:
+g_assert_not_reached();
+}
+
+num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+switch (type) {
+
+case GITS_BASER_TYPE_DEVICE:
+memset(&s->dt, 0 , sizeof(s->dt));
+s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+if (!s->dt.valid) {
+return;
+}
+
+s->dt.page_sz = page_sz;
+s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->dt.indirect) {
+s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+} else {
+s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+}
+
+s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+s->dt.base_addr = baser_base_addr(value, page_sz);
+
+break;
+
+case GITS_BASER_TYPE_COLLECTION:
+memset(&s->ct, 0 , sizeof(s->ct));
+s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+/*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+if (!s->ct.valid) {
+return;
+}
+
+s->ct.page_sz = page_sz;
+s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->ct.indirect) {
+s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+} else {
+s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+}
+
+if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+GITS_TYPER, CIDBITS) + 1));
+} else {
+/* 16-bit CollectionId supported when CIL == 0 */
+s->ct.maxids.max_collids = (1UL << 16)
[PATCH v9 0/9] GICv3 LPI and ITS feature implementation
This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v9: - removed sbsa-ref patch due to inconclusive ongoing discussion regarding ITS placement and version in sbsa-ref platform.This will be taken up as a separate functionality later - updated its enable code as per latest virt 6.2 - updated its code to replace usage of MEMTX_ with bool - All kvm_unit_tests PASS - Verified Linux Boot functionality Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/virt.c | 29 +- hw/intc/arm_gicv3.c| 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c |7 +- hw/intc/arm_gicv3_dist.c |5 +- hw/intc/arm_gicv3_its.c| 1322 hw/intc/arm_gicv3_its_common.c |7 +- hw/intc/arm_gicv3_its_kvm.c|2 +- hw/intc/arm_gicv3_redist.c | 153 ++- hw/intc/gicv3_internal.h | 188 +++- hw/intc/meson.build|1 + include/hw/arm/virt.h |2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h |4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp| Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 19 files changed, 1768 insertions(+), 24 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb -- 2.27.0
[PATCH v9 1/9] hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 241 +
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c| 2 +-
hw/intc/gicv3_internal.h | 96 +-
hw/intc/meson.build| 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 342 insertions(+), 14 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 00..83ece7c4c1
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,241 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+#include "qapi/error.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+GICv3ITSCommonClass parent_class;
+void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+return MEMTX_OK;
+}
+
+static bool its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+bool result = true;
+
+return result;
+}
+
+static bool its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+bool result = true;
+
+return result;
+}
+
+static bool its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+bool result = true;
+
+return result;
+}
+
+static bool its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+bool result = true;
+
+return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+bool result;
+
+switch (size) {
+case 4:
+result = its_readl(s, offset, data, attrs);
+break;
+case 8:
+result = its_readll(s, offset, data, attrs);
+break;
+default:
+result = false;
+break;
+}
+
+if (!result) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use false returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+*data = 0;
+}
+return MEMTX_OK;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+bool result;
+
+switch (size) {
+case 4:
+result = its_writel(s, offset, data, attrs);
+break;
+case 8:
+result = its_writell(s, offset, data, attrs);
+break;
+default:
+result = false;
+break;
+}
+
+if (!result) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use false returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+}
+return MEMTX_OK;
+}
+
+static const MemoryRegionOps gicv3_its_control_ops = {
+.read_with_attrs = gicv3_its_read,
+.wr
Re: SMMU Stage 2 translation in QEMU
So that would be the driver code running in guest OS because i see tables being setup by arm-smmu driver code in linux,which is similar to what happens with ITS(table base addresses programmed in registers by linux driver). On Fri, 2021-09-10 at 13:54 +0100, Peter Maydell wrote: > On Fri, 10 Sept 2021 at 13:39, wrote: > > I am referring to the latter,"purely emulated QEMU with an emulated > > SMMU that handles accesses to emulated devices" > > In that case, the stage 2 tables are set up by the guest > code (running at emulated EL2), just as they would be if > it were running on real hardware. > > -- PMM
Re: SMMU Stage 2 translation in QEMU
I am referring to the latter,"purely emulated QEMU with an emulated SMMU that handles accesses to emulated devices" Thanks Shashi On Fri, 2021-09-10 at 10:25 +0100, Peter Maydell wrote: > On Thu, 9 Sept 2021 at 21:18, wrote: > > I am trying to understand the approach required for an emulated > > SMMU to > > convert IPAs(from each qemu guest) to PAs(respective host > > addresses) > > using stage 2 tables. > > > > The questions i have are:- > > > > 1) Since SMMU stage 2 tables are expected to be created and managed > > by > > a hypervisor,if there is no kvm support,who is responsible to > > create > > the stage 2 tables in host memory? is it even a valid use case to > > consider smmu stage 2 support with no hypervisor present? > > So what exactly is the use case you're talking about here? > Do you mean "purely emulated QEMU, but using a host hardware > IOMMU to do device passthrough of host devices to the guest"? > Or do you mean "purely emulated QEMU with an emulated SMMU > that handles accesses to emulated devices" ? > > thanks > -- PMM
SMMU Stage 2 translation in QEMU
Hi All, I am trying to understand the approach required for an emulated SMMU to convert IPAs(from each qemu guest) to PAs(respective host addresses) using stage 2 tables. The questions i have are:- 1) Since SMMU stage 2 tables are expected to be created and managed by a hypervisor,if there is no kvm support,who is responsible to create the stage 2 tables in host memory? is it even a valid use case to consider smmu stage 2 support with no hypervisor present? 2) with SMMU emulated by qemu:- a) who is responsible for hosting and programming the stage 2 table base address registers? b) what are the APIs available in qemu to access the stage 2 tables? (will address_space_ API variants apply here?) 3) if each qemu instance (for a guest) emulates an SMMU,will there be a need to protect concurrent access of stage 2 table(in host) by each of the SMMUs? Thanks Shashi
Re: [PATCH v8 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
On Thu, 2021-08-19 at 14:27 +0100, Peter Maydell wrote:
> On Thu, 12 Aug 2021 at 17:53, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Included creation of ITS as part of SBSA platform GIC
> > initialization.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/arm/sbsa-ref.c | 79
> > ---
> > 1 file changed, 75 insertions(+), 4 deletions(-)
> >
> > +static char *sbsa_get_version(Object *obj, Error **errp)
> > +{
> > +SBSAMachineState *sms = SBSA_MACHINE(obj);
> > +
> > +switch (sms->version) {
> > +case SBSA_DEFAULT:
> > +return g_strdup("default");
> > +case SBSA_ITS:
> > +return g_strdup("sbsaits");
> > +default:
> > +g_assert_not_reached();
> > +}
> > +}
> > +
> > +static void sbsa_set_version(Object *obj, const char *value, Error
> > **errp)
> > +{
> > +SBSAMachineState *sms = SBSA_MACHINE(obj);
> > +
> > +if (!strcmp(value, "sbsaits")) {
> > +sms->version = SBSA_ITS;
> > +} else if (!strcmp(value, "default")) {
> > +sms->version = SBSA_DEFAULT;
> > +} else {
> > +error_setg(errp, "Invalid version value");
> > +error_append_hint(errp, "Valid values are default,
> > sbsaits.\n");
> > +}
> > +}
> >
> > static void sbsa_ref_instance_init(Object *obj)
> > {
> > SBSAMachineState *sms = SBSA_MACHINE(obj);
> >
> > +sms->version = SBSA_ITS;
> > sbsa_flash_create(sms);
> > }
> >
> > @@ -850,6 +915,12 @@ static void sbsa_ref_class_init(ObjectClass
> > *oc, void *data)
> > mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
> > mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
> > mc->get_default_cpu_node_id =
> > sbsa_ref_get_default_cpu_node_id;
> > +
> > +object_class_property_add_str(oc, "version", sbsa_get_version,
> > + sbsa_set_version);
> > +object_class_property_set_description(oc, "version",
> > + "Set the Version type. "
> > + "Valid values are
> > default & sbsaits");
>
> This doesn't look right; where has it come from ?
>
> If you want a command line switch to let the user say whether the
> ITS should be present or not, you should use the same thing the
> virt board does, which is a bool property "its".
>
> If you want the sbsa-ref board to become a proper "versioned machine
> type" such that users can say "-M sbsa-ref-6.1" and get the SBSA
> board exactly as QEMU 6.1 supplied it, that looks completely
> different
> (and is a heavy back-compatibility burden, so needs discussion about
> whether now is the right time to do it), and probably is better not
> tangled up with this patchseries.
>
> thanks
> -- PMM
Since the memory map for sbsa-ref has been updated with ITS address
range added between distributor and redistributor regions(as per last
reveiw comments),this has resulted in a change in the redistributor
base address(as compared to previous sbsa-ref with no ITS
support).Hence there was a subsequent request for creating a versioning
logic to differentiate between ITS presence or absence which would be
of use to other modules (like TF-A) to pick the relevant redistributor
base address based on this versioning.
Re: [PATCH v7 09/10] hw/arm/virt: add ITS support in virt GIC
On Fri, 2021-08-06 at 13:09 +0200, Igor Mammedov wrote:
> On Thu, 5 Aug 2021 18:30:01 -0400
> Shashi Mallela wrote:
>
> > Included creation of ITS as part of virt platform GIC
> > initialization. This Emulated ITS model now co-exists with kvm
> > ITS and is enabled in absence of kvm irq kernel support in a
> > platform.
> >
> > Signed-off-by: Shashi Mallela
> > Reviewed-by: Peter Maydell
> > ---
> > hw/arm/virt.c | 28 ++--
> > include/hw/arm/virt.h | 2 ++
> > target/arm/kvm_arm.h | 4 ++--
> > 3 files changed, 30 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > index 81eda46b0b..99cf4f9dbd 100644
> > --- a/hw/arm/virt.c
> > +++ b/hw/arm/virt.c
> > @@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
> > const char *itsclass = its_class_name();
> > DeviceState *dev;
> >
> > +if (!strcmp(itsclass, "arm-gicv3-its")) {
> > +if (!vms->tcg_its) {
> > +itsclass = NULL;
> > +}
> > +}
> > +
> > if (!itsclass) {
> > /* Do nothing if not supported */
> > return;
> > @@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
> > vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
> > }
> >
> > -static void create_gic(VirtMachineState *vms)
> > +static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
> > {
> > MachineState *ms = MACHINE(vms);
> > /* We create a standalone GIC */
> > @@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
> > nb_redist_regions);
> > qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
> > redist0_count);
> >
> > +if (!kvm_irqchip_in_kernel()) {
> > +if (vms->tcg_its) {
> > +object_property_set_link(OBJECT(vms->gic),
> > "sysmem",
> > + OBJECT(mem),
> > &error_fatal);
> > +qdev_prop_set_bit(vms->gic, "has-lpi", true);
> > +}
> > +}
> > +
> > if (nb_redist_regions == 2) {
> > uint32_t redist1_capacity =
> > vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
> > GICV3_REDIST_SIZE;
> > @@ -2043,7 +2057,7 @@ static void machvirt_init(MachineState
> > *machine)
> >
> > virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
> >
> > -create_gic(vms);
> > +create_gic(vms, sysmem);
> >
> > virt_cpu_post_init(vms, sysmem);
> >
> > @@ -2746,6 +2760,12 @@ static void virt_instance_init(Object *obj)
> > } else {
> > /* Default allows ITS instantiation */
> > vms->its = true;
> > +
> > +if (vmc->no_tcg_its) {
> > +vms->tcg_its = false;
> > +} else {
> > +vms->tcg_its = true;
> > +}
> > }
> >
> > /* Default disallows iommu instantiation */
> > @@ -2795,8 +2815,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
> >
> > static void virt_machine_6_0_options(MachineClass *mc)
> > {
> > +VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
> > +
> > virt_machine_6_1_options(mc);
> > compat_props_add(mc->compat_props, hw_compat_6_0,
> > hw_compat_6_0_len);
> > +/* qemu ITS was introduced with 6.1 */
> > +vmc->no_tcg_its = true;
>
> given it's not going to be in 6.1, shouldn't it be moved to
> virt_machine_6_1_options() with updated comment?
Agreed,moved to virt_machine_6_1_options() and updated comment
>
> > }
> > DEFINE_VIRT_MACHINE(6, 0)
> >
> > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> > index 9661c46699..b461b8d261 100644
> > --- a/include/hw/arm/virt.h
> > +++ b/include/hw/arm/virt.h
> > @@ -120,6 +120,7 @@ struct VirtMachineClass {
> > MachineClass parent;
> > bool disallow_affinity_adjustment;
> > bool no_its;
> > +bool no_tcg_its;
> > bool no_pmu;
> > bool claim_edge_triggered_timers;
> > bool smbios_old_sys_ver;
> > @@ -141,6 +142,7 @@ struct VirtMachineState {
> > bool highmem;
> > bool highmem_ecam;
> > bool its;
> > +bool tcg_its;
> > bool virt;
> > bool ras;
> > bool mte;
> > diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
> > index 34f8daa377..0613454975 100644
> > --- a/target/arm/kvm_arm.h
> > +++ b/target/arm/kvm_arm.h
> > @@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
> > /* KVM implementation requires this capability */
> > return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
> > } else {
> > -/* Software emulation is not implemented yet */
> > -return NULL;
> > +/* Software emulation based model */
> > +return "arm-gicv3-its";
> > }
> > }
> >
[PATCH v8 09/10] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 ++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 81eda46b0b..3cea2aa039 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2043,7 +2057,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2746,6 +2760,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2790,6 +2810,10 @@ type_init(machvirt_machine_init);
static void virt_machine_6_1_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
+/* qemu ITS was introduced with 6.2 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9661c46699..b461b8d261 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v8 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603..feadae2f33 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -58,12 +58,26 @@
#define ARCH_TIMER_NS_EL1_IRQ 14
#define ARCH_TIMER_NS_EL2_IRQ 10
+/*
+ * Enumeration of the possible values of sbsa-ref version
+ * property. These are arbitrary QEMU-internal values.
+ * values are :-
+ * DEFAULT = without ITS memory map
+ * SBSA_GIC_ITS = with ITS memory map between distributor & redistributor
+ *regions. This is the current version supported.
+ */
+typedef enum SbsaRefVersion {
+SBSA_DEFAULT,
+SBSA_ITS,
+} SbsaRefVersion;
+
enum {
SBSA_FLASH,
SBSA_MEM,
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -91,6 +105,7 @@ struct SBSAMachineState {
void *fdt;
int fdt_size;
int psci_conduit;
+SbsaRefVersion version;
DeviceState *gic;
PFlashCFI01 *flash[2];
};
@@ -105,8 +120,11 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_SECURE_MEM] = { 0x2000, 0x2000 },
/* Space reserved for CPU peripheral devices */
[SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
+/* GIC components reserved space Start */
[SBSA_GIC_DIST] = { 0x4006, 0x0001 },
-[SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
+[SBSA_GIC_ITS] ={ 0x4007, 0x0002 },
+[SBSA_GIC_REDIST] = { 0x400B, 0x0400 },
+/* GIC components reserved space End */
[SBSA_SECURE_EC] = { 0x5000, 0x1000 },
[SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
@@ -377,7 +395,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_ARM_GICV3_ITS);
+SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+sysbus_realize_and_unref(s, &error_fatal);
+sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +435,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +485,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -755,7 +791,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
-create_gic(sms);
+create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
@@ -825,10 +861,39 @@ sbsa_ref_get_default_cpu_node_id(const MachineState *ms,
int idx)
return idx % ms->numa_state->num_nodes;
}
+static char *sbsa_get_version(Object *obj, Error **errp)
+{
+SBSAMachineState *sms = SBSA_MACHINE(obj);
+
+switch (sms->version) {
+case SBSA_DEFAULT:
+return g_strdup("default");
+case SBSA_ITS:
+return g_strdup("sbsaits");
+default:
+g_assert_not_reached();
+}
+}
+
+static void sbsa_set_version(Object *obj, const char *value, Error **errp)
+{
+SBSAMachineState *sms = SBSA_MACHINE(obj);
+
+if (!strcmp(value, "sbsaits")) {
+
[PATCH v8 10/10] tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3 ITS changes. Full diff of new file disassembly: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 4]Signature : "IORT"[IO Remapping Table] [004h 0004 4] Table Length : 007C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 07 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC" [018h 0024 4] Oem Revision : 0001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4]Asl Compiler Revision : 0001 [024h 0036 4] Node Count : 0002 [028h 0040 4] Node Offset : 0030 [02Ch 0044 4] Reserved : [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 00 [034h 0052 4] Reserved : [038h 0056 4]Mapping Count : [03Ch 0060 4] Mapping Offset : [040h 0064 4] ItsCount : 0001 [044h 0068 4] Identifiers : [048h 0072 1] Type : 02 [049h 0073 2] Length : 0034 [04Bh 0075 1] Revision : 00 [04Ch 0076 4] Reserved : [050h 0080 4]Mapping Count : 0001 [054h 0084 4] Mapping Offset : 0020 [058h 0088 8]Memory Properties : [IORT Memory Access Properties] [058h 0088 4] Cache Coherency : 0001 [05Ch 0092 1]Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [05Dh 0093 2] Reserved : [05Fh 0095 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [060h 0096 4]ATS Attribute : [064h 0100 4] PCI Segment Number : [068h 0104 1]Memory Size Limit : 00 [069h 0105 3] Reserved : 00 [068h 0104 4] Input base : [06Ch 0108 4] ID Count : [070h 0112 4] Output Base : [074h 0116 4] Output Reference : 0030 [078h 0120 4]Flags (decoded below) : Single Mapping : 0 Raw Table Data: Length 124 (0x7C) : 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPCBXPC 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // 0... 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .4.. 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // ... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0... Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmeb
[PATCH v8 08/10] tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela Acked-by: Igor Mammedov --- tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ef211df59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v8 04/10] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 351 +
hw/intc/gicv3_internal.h | 12 +
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 365 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 8bdbebbeca..d98b0e0f4c 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
+typedef struct {
+uint32_t iteh;
+uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -50,6 +66,323 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * (sizeof(uint64_t) +
+ sizeof(uint32_t))), ite.itel, MEMTXATTRS_UNSPECIFIED,
+ &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + (eventid * (sizeof(uint64_t) +
+ sizeof(uint32_t))) + sizeof(uint32_t), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+}
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+IteEntry ite = {};
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+ite.itel = address_space_ldq_le(as, itt_addr +
+(eventid * (sizeof(uint64_t) +
+sizeof(uint32_t))), MEMTXATTRS_UNSPECIFIED,
+res);
+
+if (*res == MEMTX_OK) {
+ite.iteh = address_space_ldl_le(as, itt_addr +
+(eventid * (sizeof(uint64_t) +
+sizeof(uint32_t))) + sizeof(uint32_t),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (ite.itel & TABLE_ENTRY_VALID_MASK) {
+if ((ite.itel >> ITE_ENTRY_INTTYPE
[PATCH v8 06/10] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc/arm_gicv3_redist.c | 141 +
hw/intc/gicv3_internal.h | 9 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+(cs->hpplpi.prio != 0xff)) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+for (i = 0; i < s->num_cpu; i++) {
+gicv3_redist_update_lpi(&s->cpu[i]);
+}
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index a032d505f5..462a35f66e 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) &&
+!(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index d98b0e0f4c..d09ad6f556 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -228,6 +228,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+uint64_t rdbase;
if (cmd == NONE) {
devid = offset;
@@ -288,6 +289,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
* Current implementation only supports rdbase == procnum
* Hence rdbase physical address is ignored
*/
+rdbase = (cte & GITS_CTE_RDBASE_PROCNUM_MASK) >> 1U;
+
+if (rdbase > s->gicv3->num_cpu) {
+return res;
+}
+
+if ((cmd == CLEAR) || (cmd == DISCARD)) {
+gicv3_redist_process_lpi(&
[PATCH v8 05/10] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 5 -
hw/intc/arm_gicv3_redist.c | 12 +---
hw/intc/gicv3_internal.h | 2 ++
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..43128b376d 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return MEMTX_OK;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 53da703ed8..2108abfe9c 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+if (value & GICR_CTLR_ENABLE_LPIS) {
+cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+} else {
+cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+}
+}
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 1966444790..530d1c1789 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,8 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_SHIFT 17
+
/* 16 bits EventId */
#define GICD_TYPER_IDBITS0xf
diff --git a/include/hw/intc/arm_gicv3_com
[PATCH v8 02/10] hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 431 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 2286b3f757..b2210dffdc 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+uint64_t result = 0;
+
+switch (page_sz) {
+case GITS_PAGE_SIZE_4K:
+case GITS_PAGE_SIZE_16K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12;
+break;
+
+case GITS_PAGE_SIZE_64K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+break;
+
+default:
+break;
+}
+return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+uint16_t num_pages = 0;
+uint8_t page_sz_type;
+uint8_t type;
+uint32_t page_sz = 0;
+uint64_t value;
+
+for (int i = 0; i < 8; i++) {
+value = s->baser[i];
+
+if (!value) {
+continue;
+}
+
+page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+switch (page_sz_type) {
+case 0:
+page_sz = GITS_PAGE_SIZE_4K;
+break;
+
+case 1:
+page_sz = GITS_PAGE_SIZE_16K;
+break;
+
+case 2:
+case 3:
+page_sz = GITS_PAGE_SIZE_64K;
+break;
+
+default:
+g_assert_not_reached();
+}
+
+num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+switch (type) {
+
+case GITS_BASER_TYPE_DEVICE:
+memset(&s->dt, 0 , sizeof(s->dt));
+s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+if (!s->dt.valid) {
+return;
+}
+
+s->dt.page_sz = page_sz;
+s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->dt.indirect) {
+s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+} else {
+s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+}
+
+s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+s->dt.base_addr = baser_base_addr(value, page_sz);
+
+break;
+
+case GITS_BASER_TYPE_COLLECTION:
+memset(&s->ct, 0 , sizeof(s->ct));
+s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+/*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+if (!s->ct.valid) {
+return;
+}
+
+s->ct.page_sz = page_sz;
+s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->ct.indirect) {
+s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+} else {
+s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+}
+
+if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+GITS_TYPER, CIDBITS) + 1));
+} else {
+/* 16-bit CollectionId supported when CIL == 0 */
+s->ct.maxids.max_collids = (1UL << 16)
[PATCH v8 03/10] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c | 306 +++
hw/intc/gicv3_internal.h | 40 +
2 files changed, 346 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index b2210dffdc..8bdbebbeca 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -50,6 +50,305 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return res;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
+rdbase &= RDBASE_PROCNUM_MASK;
+
+valid = (value & CMD_FIELD_VALID_MASK);
+
+if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+res = update_cte(s, icid, valid, rdbase);
+}
+
+return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ (itt_addr << GITS_DTE_ITTADDR_SHIFT);
+}
+} else {
+return res;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABL
[PATCH v8 01/10] hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 245 +
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c| 2 +-
hw/intc/gicv3_internal.h | 96 +-
hw/intc/meson.build| 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 346 insertions(+), 14 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 00..2286b3f757
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,245 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+#include "qapi/error.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+GICv3ITSCommonClass parent_class;
+void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_readl(s, offset, data, attrs);
+break;
+case 8:
+result = its_readll(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+result = MEMTX_OK;
+*data = 0;
+}
+return result;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_writel(s, offset, data, attrs);
+break;
+case 8:
+result = its_writell(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we
[PATCH v8 00/10] GICv3 LPI and ITS feature implementation
This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v8: - moved tcg ITS support to virt platform 6.1 options (since it will be supported in 6.2) - modified the ite entry access offset based on latest test results - All kvm_unit_tests PASS - Verified Linux Boot functionality Shashi Mallela (10): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/sbsa-ref.c | 79 +- hw/arm/virt.c | 28 +- hw/intc/arm_gicv3.c| 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c |7 +- hw/intc/arm_gicv3_dist.c |5 +- hw/intc/arm_gicv3_its.c| 1301 hw/intc/arm_gicv3_its_common.c |7 +- hw/intc/arm_gicv3_its_kvm.c|2 +- hw/intc/arm_gicv3_redist.c | 153 ++- hw/intc/gicv3_internal.h | 188 +++- hw/intc/meson.build|1 + include/hw/arm/virt.h |2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h |4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp| Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 20 files changed, 1821 insertions(+), 28 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb -- 2.27.0
Re: [PATCH v7 04/10] hw/intc: GICv3 ITS Command processing
Thanks for sharing the observations Neil.
Will take care of it in the next patch-set.
On Fri, 2021-08-06 at 10:58 +0200, Neil Armstrong wrote:
> Hi,
>
> On 06/08/2021 00:29, Shashi Mallela wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GITS_TRANSLATER register,defined enum to differentiate between
> > ITS
> > command interrupt trigger and GITS_TRANSLATER based interrupt
> > trigger.
> > Each of these commands make use of other functionalities
> > implemented to
> > get device table entry,collection table entry or interrupt
> > translation
> > table entry required for their processing.
> >
> > Signed-off-by: Shashi Mallela
> > Reviewed-by: Peter Maydell
> > ---
> > hw/intc/arm_gicv3_its.c| 348
> > +
> > hw/intc/gicv3_internal.h | 12 +
> > include/hw/intc/arm_gicv3_common.h | 2 +
> > 3 files changed, 362 insertions(+)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index 8bdbebbeca..35308f1c32 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -29,6 +29,22 @@ struct GICv3ITSClass {
> > void (*parent_reset)(DeviceState *dev);
> > };
> >
> > +/*
> > + * This is an internal enum used to distinguish between LPI
> > triggered
> > + * via command queue and LPI triggered via gits_translater write.
> > + */
> > +typedef enum ItsCmdType {
> > +NONE = 0, /* internal indication for GITS_TRANSLATER write */
> > +CLEAR = 1,
> > +DISCARD = 2,
> > +INT = 3,
> > +} ItsCmdType;
> > +
> > +typedef struct {
> > +uint32_t iteh;
> > +uint64_t itel;
> > +} IteEntry;
> > +
> > static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> > {
> > uint64_t result = 0;
> > @@ -50,6 +66,320 @@ static uint64_t baser_base_addr(uint64_t value,
> > uint32_t page_sz)
> > return result;
> > }
> >
> > +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t
> > *cte,
> > +MemTxResult *res)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint64_t l2t_addr;
> > +uint64_t value;
> > +bool valid_l2t;
> > +uint32_t l2t_id;
> > +uint32_t max_l2_entries;
> > +
> > +if (s->ct.indirect) {
> > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > +value = address_space_ldq_le(as,
> > + s->ct.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > +if (*res == MEMTX_OK) {
> > +valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
> > +
> > +if (valid_l2t) {
> > +max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > +
> > +l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > +*cte = address_space_ldq_le(as, l2t_addr +
> > +((icid % max_l2_entries) *
> > GITS_CTE_SIZE),
> > +MEMTXATTRS_UNSPECIFIED, res);
> > + }
> > + }
> > +} else {
> > +/* Flat level table */
> > +*cte = address_space_ldq_le(as, s->ct.base_addr +
> > + (icid * GITS_CTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED,
> > res);
> > +}
> > +
> > +return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
> > +}
> > +
> > +static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid,
> > uint64_t dte,
> > + IteEntry ite)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint64_t itt_addr;
> > +MemTxResult res = MEMTX_OK;
> > +
> > +itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >>
> > GITS_DTE_ITTADDR_SHIFT;
> > +itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> > +
> > +address_space_stq_le(as, itt_addr + (eventid *
> > sizeof(uint64_t)),
> > + ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > +if (res == MEMTX_OK) {
> > +address_space_stl_le(as, itt_addr + ((eventid
[PATCH v7 09/10] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 ++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 81eda46b0b..99cf4f9dbd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2043,7 +2057,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2746,6 +2760,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2795,8 +2815,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
static void virt_machine_6_0_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_6_1_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+/* qemu ITS was introduced with 6.1 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9661c46699..b461b8d261 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v7 10/10] tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3 ITS changes. Full diff of new file disassembly: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 4]Signature : "IORT"[IO Remapping Table] [004h 0004 4] Table Length : 007C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 07 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC" [018h 0024 4] Oem Revision : 0001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4]Asl Compiler Revision : 0001 [024h 0036 4] Node Count : 0002 [028h 0040 4] Node Offset : 0030 [02Ch 0044 4] Reserved : [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 00 [034h 0052 4] Reserved : [038h 0056 4]Mapping Count : [03Ch 0060 4] Mapping Offset : [040h 0064 4] ItsCount : 0001 [044h 0068 4] Identifiers : [048h 0072 1] Type : 02 [049h 0073 2] Length : 0034 [04Bh 0075 1] Revision : 00 [04Ch 0076 4] Reserved : [050h 0080 4]Mapping Count : 0001 [054h 0084 4] Mapping Offset : 0020 [058h 0088 8]Memory Properties : [IORT Memory Access Properties] [058h 0088 4] Cache Coherency : 0001 [05Ch 0092 1]Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [05Dh 0093 2] Reserved : [05Fh 0095 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [060h 0096 4]ATS Attribute : [064h 0100 4] PCI Segment Number : [068h 0104 1]Memory Size Limit : 00 [069h 0105 3] Reserved : 00 [068h 0104 4] Input base : [06Ch 0108 4] ID Count : [070h 0112 4] Output Base : [074h 0116 4] Output Reference : 0030 [078h 0120 4]Flags (decoded below) : Single Mapping : 0 Raw Table Data: Length 124 (0x7C) : 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPCBXPC 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // 0... 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .4.. 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // ... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0... Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&am
[PATCH v7 06/10] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc/arm_gicv3_redist.c | 141 +
hw/intc/gicv3_internal.h | 9 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+(cs->hpplpi.prio != 0xff)) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+for (i = 0; i < s->num_cpu; i++) {
+gicv3_redist_update_lpi(&s->cpu[i]);
+}
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index a032d505f5..462a35f66e 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) &&
+!(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 35308f1c32..efa43b0333 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -225,6 +225,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+uint64_t rdbase;
if (cmd == NONE) {
devid = offset;
@@ -285,6 +286,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
* Current implementation only supports rdbase == procnum
* Hence rdbase physical address is ignored
*/
+rdbase = (cte & GITS_CTE_RDBASE_PROCNUM_MASK) >> 1U;
+
+if (rdbase > s->gicv3->num_cpu) {
+return res;
+}
+
+if ((cmd == CLEAR) || (cmd == DISCARD)) {
+gicv3_redist_process_lpi(&s->gicv3->cpu[rdbas
[PATCH v7 04/10] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 348 +
hw/intc/gicv3_internal.h | 12 +
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 362 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 8bdbebbeca..35308f1c32 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
+typedef struct {
+uint32_t iteh;
+uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -50,6 +66,320 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+ ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
+ sizeof(uint32_t)), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+}
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+IteEntry ite = {};
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+ite.itel = address_space_ldq_le(as, itt_addr +
+(eventid * sizeof(uint64_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
+sizeof(uint64_t)) * sizeof(uint32_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (ite.itel & TABLE_ENTRY_VALID_MASK) {
+if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
+GITS_TYPE_PHYSICAL) {
+*pIntid = (ite.itel & ITE_ENTRY_INTID_MASK) >>
+
[PATCH v7 08/10] tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ef211df59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v7 02/10] hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 431 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 2286b3f757..b2210dffdc 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+uint64_t result = 0;
+
+switch (page_sz) {
+case GITS_PAGE_SIZE_4K:
+case GITS_PAGE_SIZE_16K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12;
+break;
+
+case GITS_PAGE_SIZE_64K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+break;
+
+default:
+break;
+}
+return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+uint16_t num_pages = 0;
+uint8_t page_sz_type;
+uint8_t type;
+uint32_t page_sz = 0;
+uint64_t value;
+
+for (int i = 0; i < 8; i++) {
+value = s->baser[i];
+
+if (!value) {
+continue;
+}
+
+page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+switch (page_sz_type) {
+case 0:
+page_sz = GITS_PAGE_SIZE_4K;
+break;
+
+case 1:
+page_sz = GITS_PAGE_SIZE_16K;
+break;
+
+case 2:
+case 3:
+page_sz = GITS_PAGE_SIZE_64K;
+break;
+
+default:
+g_assert_not_reached();
+}
+
+num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+switch (type) {
+
+case GITS_BASER_TYPE_DEVICE:
+memset(&s->dt, 0 , sizeof(s->dt));
+s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+if (!s->dt.valid) {
+return;
+}
+
+s->dt.page_sz = page_sz;
+s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->dt.indirect) {
+s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+} else {
+s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+}
+
+s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+s->dt.base_addr = baser_base_addr(value, page_sz);
+
+break;
+
+case GITS_BASER_TYPE_COLLECTION:
+memset(&s->ct, 0 , sizeof(s->ct));
+s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+/*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+if (!s->ct.valid) {
+return;
+}
+
+s->ct.page_sz = page_sz;
+s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->ct.indirect) {
+s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+} else {
+s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+}
+
+if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+GITS_TYPER, CIDBITS) + 1));
+} else {
+/* 16-bit CollectionId supported when CIL == 0 */
+s->ct.maxids.max_collids = (1UL << 16);
+}
+
+s->
[PATCH v7 03/10] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c | 306 +++
hw/intc/gicv3_internal.h | 40 +
2 files changed, 346 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index b2210dffdc..8bdbebbeca 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -50,6 +50,305 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return res;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
+rdbase &= RDBASE_PROCNUM_MASK;
+
+valid = (value & CMD_FIELD_VALID_MASK);
+
+if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+res = update_cte(s, icid, valid, rdbase);
+}
+
+return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ (itt_addr << GITS_DTE_ITTADDR_SHIFT);
+}
+} else {
+return res;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+
[PATCH v7 05/10] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 5 -
hw/intc/arm_gicv3_redist.c | 12 +---
hw/intc/gicv3_internal.h | 2 ++
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..43128b376d 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return MEMTX_OK;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 53da703ed8..2108abfe9c 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+if (value & GICR_CTLR_ENABLE_LPIS) {
+cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+} else {
+cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+}
+}
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 1966444790..530d1c1789 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,8 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_SHIFT 17
+
/* 16 bits EventId */
#define GICD_TYPER_IDBITS0xf
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_com
[PATCH v7 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603..feadae2f33 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -58,12 +58,26 @@
#define ARCH_TIMER_NS_EL1_IRQ 14
#define ARCH_TIMER_NS_EL2_IRQ 10
+/*
+ * Enumeration of the possible values of sbsa-ref version
+ * property. These are arbitrary QEMU-internal values.
+ * values are :-
+ * DEFAULT = without ITS memory map
+ * SBSA_GIC_ITS = with ITS memory map between distributor & redistributor
+ *regions. This is the current version supported.
+ */
+typedef enum SbsaRefVersion {
+SBSA_DEFAULT,
+SBSA_ITS,
+} SbsaRefVersion;
+
enum {
SBSA_FLASH,
SBSA_MEM,
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -91,6 +105,7 @@ struct SBSAMachineState {
void *fdt;
int fdt_size;
int psci_conduit;
+SbsaRefVersion version;
DeviceState *gic;
PFlashCFI01 *flash[2];
};
@@ -105,8 +120,11 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_SECURE_MEM] = { 0x2000, 0x2000 },
/* Space reserved for CPU peripheral devices */
[SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
+/* GIC components reserved space Start */
[SBSA_GIC_DIST] = { 0x4006, 0x0001 },
-[SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
+[SBSA_GIC_ITS] ={ 0x4007, 0x0002 },
+[SBSA_GIC_REDIST] = { 0x400B, 0x0400 },
+/* GIC components reserved space End */
[SBSA_SECURE_EC] = { 0x5000, 0x1000 },
[SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
@@ -377,7 +395,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_ARM_GICV3_ITS);
+SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+sysbus_realize_and_unref(s, &error_fatal);
+sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +435,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +485,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -755,7 +791,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
-create_gic(sms);
+create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
@@ -825,10 +861,39 @@ sbsa_ref_get_default_cpu_node_id(const MachineState *ms,
int idx)
return idx % ms->numa_state->num_nodes;
}
+static char *sbsa_get_version(Object *obj, Error **errp)
+{
+SBSAMachineState *sms = SBSA_MACHINE(obj);
+
+switch (sms->version) {
+case SBSA_DEFAULT:
+return g_strdup("default");
+case SBSA_ITS:
+return g_strdup("sbsaits");
+default:
+g_assert_not_reached();
+}
+}
+
+static void sbsa_set_version(Object *obj, const char *value, Error **errp)
+{
+SBSAMachineState *sms = SBSA_MACHINE(obj);
+
+if (!strcmp(value, "sbsaits")) {
+
[PATCH v7 01/10] hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c| 245 +
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c| 2 +-
hw/intc/gicv3_internal.h | 96 +-
hw/intc/meson.build| 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 346 insertions(+), 14 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 00..2286b3f757
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,245 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+#include "qapi/error.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+GICv3ITSCommonClass parent_class;
+void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_readl(s, offset, data, attrs);
+break;
+case 8:
+result = its_readll(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+result = MEMTX_OK;
+*data = 0;
+}
+return result;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_writel(s, offset, data, attrs);
+break;
+case 8:
+result = its_writell(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a
[PATCH v7 00/10] GICv3 LPI and ITS feature implementation
This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v7: - Restructured the lpi pending table scan logic as per comments in v6 - Addressed minor comments from v6 - For sbsa-ref platform,ITS memory map has been inserted between distributor & redistributors region similar to GIC-600 layout. Also, introduced sbsa-ref versioning to reflect the latest its memory map change and subsequent future use for helper functions - All kvm_unit_tests PASS - Verified Linux Boot functionality Shashi Mallela (10): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/sbsa-ref.c | 79 +- hw/arm/virt.c | 28 +- hw/intc/arm_gicv3.c| 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c |7 +- hw/intc/arm_gicv3_dist.c |5 +- hw/intc/arm_gicv3_its.c| 1298 hw/intc/arm_gicv3_its_common.c |7 +- hw/intc/arm_gicv3_its_kvm.c|2 +- hw/intc/arm_gicv3_redist.c | 153 ++- hw/intc/gicv3_internal.h | 188 +++- hw/intc/meson.build|1 + include/hw/arm/virt.h |2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h |4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp| Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 20 files changed, 1818 insertions(+), 28 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb -- 2.27.0
Re: [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
On Thu, 2021-07-08 at 19:27 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 7/6/21 11:29 AM, Eric Auger wrote:
> > Hi,
> >
> > On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > > Defined descriptors for ITS device table,collection table and ITS
> > > command queue entities.Implemented register read/write functions,
> > > extract ITS table parameters and command queue
> > > parameters,extended
> > > gicv3 common to capture qemu address space(which host the ITS
> > > table
> > > platform memories required for subsequent ITS processing) and
> > > initialize the same in ITS device.
> > >
> > > Signed-off-by: Shashi Mallela
> > > Reviewed-by: Peter Maydell
> > > ---
> > > hw/intc/arm_gicv3_its.c| 376
> > > +
> > > hw/intc/gicv3_internal.h | 31 +-
> > > include/hw/intc/arm_gicv3_common.h | 3 +
> > > include/hw/intc/arm_gicv3_its_common.h | 23 ++
> > > 4 files changed, 432 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > index 545cda3665..2d786a1e21 100644
> > > --- a/hw/intc/arm_gicv3_its.c
> > > +++ b/hw/intc/arm_gicv3_its.c
> > > @@ -28,6 +28,160 @@ struct GICv3ITSClass {
> > > void (*parent_reset)(DeviceState *dev);
> > > };
> > >
> > > +static uint64_t baser_base_addr(uint64_t value, uint32_t
> > > page_sz)
> > > +{
> > > +uint64_t result = 0;
> > > +
> > > +switch (page_sz) {
> > > +case GITS_PAGE_SIZE_4K:
> > > +case GITS_PAGE_SIZE_16K:
> > > +result = FIELD_EX64(value, GITS_BASER, PHYADDR);
> > << 12 ?
> Did you check that? Seems unchanged in v6?
>
> Thanks
>
> Eric
Have taken care of it in the v7 patch
> > > +break;
> > > +
> > > +case GITS_PAGE_SIZE_64K:
> > > +result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) <<
> > > 16;
> > > +result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) <<
> > > 48;
> > > +break;
> > > +
> > > +default:
> > > +break;
> > > +}
> > > +return result;
> > > +}
> > > +
> > > +/*
> > > + * This function extracts the ITS Device and Collection table
> > > specific
> > > + * parameters (like base_addr, size etc) from GITS_BASER
> > > register.
> > > + * It is called during ITS enable and also during post_load
> > > migration
> > > + */
> > > +static void extract_table_params(GICv3ITSState *s)
> > > +{
> > > +uint16_t num_pages = 0;
> > > +uint8_t page_sz_type;
> > > +uint8_t type;
> > > +uint32_t page_sz = 0;
> > > +uint64_t value;
> > > +
> > > +for (int i = 0; i < 8; i++) {
> > > +value = s->baser[i];
> > > +
> > > +if (!value) {
> > > +continue;
> > > +}
> > > +
> > > +page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
> > > +
> > > +switch (page_sz_type) {
> > > +case 0:
> > > +page_sz = GITS_PAGE_SIZE_4K;
> > > +break;
> > > +
> > > +case 1:
> > > +page_sz = GITS_PAGE_SIZE_16K;
> > > +break;
> > > +
> > > +case 2:
> > > +case 3:
> > > +page_sz = GITS_PAGE_SIZE_64K;
> > > +break;
> > > +
> > > +default:
> > > +g_assert_not_reached();
> > > +}
> > > +
> > > +num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
> > > +
> > > +type = FIELD_EX64(value, GITS_BASER, TYPE);
> > > +
> > > +switch (type) {
> > > +
> > > +case GITS_ITT_TYPE_DEVICE:
> > > +memset(&s->dt, 0 , sizeof(s->dt));
> > > +s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
> > > +
> > > +if (!s->dt.valid) {
> > > +return;
> > > +}
> > > +
> > > +s->dt.page_sz = page_sz;
> > > +s->dt.indirect = FIELD_EX64(value, GITS_BASER,
> > > INDIRECT);
> > > +s->dt.entry_sz = FIELD_EX
Re: [PATCH v4 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC
On Thu, 2021-07-08 at 23:05 +0100, Leif Lindholm wrote: > On Thu, Jul 08, 2021 at 21:05:02 +0100, Peter Maydell wrote: > > On Thu, 8 Jul 2021 at 20:40, Leif Lindholm > > wrote: > > > I think my summary-summary would be: > > > - I think we will need to introduce a compatiblity-breaking > > > change to > > > sbsa-ref. > > > - I think we will need to have support for more than one ITS if > > > we're > > > going to be able to use QEMU to prototype real systems. > > > - I think we should then start versioning sbsa-ref (like many > > > other > > > platforms already are). And there are other reasons why I would > > > want > > > to do this. > > > - But I think it would be unfair to hold this set back for it. > > > > FWIW, I do not currently expect this series to make 6.1, so we > > have some time to get things right. > > Ah, ok. > > Then I would ideally like to see this patch add the ITS block between > Distributor and Redistributors regions. I think it makes the most > sense > for this version to match the GIC-600 layout. Have added ITS block between Distributor and Redistributors regions,with comments. Also,added sbsa versioning support (as discussed in last call) > > I am also going to rework those two remaining gicv4-ish patches based > on my acquired understanding, to be sent out post v6.1. > > And, I would like to switch the default CPU of sbsa-ref to "max" as > part of that platform versioning, now that is supported in TF-A > (from v2.5). > > / > Leif
[PATCH v6 10/10] tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3 ITS changes. Full diff of new file disassembly: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 4]Signature : "IORT"[IO Remapping Table] [004h 0004 4] Table Length : 007C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 07 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC" [018h 0024 4] Oem Revision : 0001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4]Asl Compiler Revision : 0001 [024h 0036 4] Node Count : 0002 [028h 0040 4] Node Offset : 0030 [02Ch 0044 4] Reserved : [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 00 [034h 0052 4] Reserved : [038h 0056 4]Mapping Count : [03Ch 0060 4] Mapping Offset : [040h 0064 4] ItsCount : 0001 [044h 0068 4] Identifiers : [048h 0072 1] Type : 02 [049h 0073 2] Length : 0034 [04Bh 0075 1] Revision : 00 [04Ch 0076 4] Reserved : [050h 0080 4]Mapping Count : 0001 [054h 0084 4] Mapping Offset : 0020 [058h 0088 8]Memory Properties : [IORT Memory Access Properties] [058h 0088 4] Cache Coherency : 0001 [05Ch 0092 1]Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [05Dh 0093 2] Reserved : [05Fh 0095 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [060h 0096 4]ATS Attribute : [064h 0100 4] PCI Segment Number : [068h 0104 1]Memory Size Limit : 00 [069h 0105 3] Reserved : 00 [068h 0104 4] Input base : [06Ch 0108 4] ID Count : [070h 0112 4] Output Base : [074h 0116 4] Output Reference : 0030 [078h 0120 4]Flags (decoded below) : Single Mapping : 0 Raw Table Data: Length 124 (0x7C) : 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPCBXPC 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // 0... 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .4.. 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // ... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0... Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&am
[PATCH v6 08/10] tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ef211df59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v6 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -64,6 +64,7 @@ enum {
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
[SBSA_GIC_DIST] = { 0x4006, 0x0001 },
[SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
+[SBSA_GIC_ITS] ={ 0x4409, 0x0002 },
[SBSA_SECURE_EC] = { 0x5000, 0x1000 },
[SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
@@ -377,7 +379,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_ARM_GICV3_ITS);
+SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+sysbus_realize_and_unref(s, &error_fatal);
+sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +419,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +469,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -762,7 +782,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
-create_gic(sms);
+create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
--
2.27.0
[PATCH v6 06/10] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc/arm_gicv3_redist.c | 142 +
hw/intc/gicv3_internal.h | 9 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 201 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+(cs->hpplpi.prio != 0xff)) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+for (i = 0; i < s->num_cpu; i++) {
+gicv3_redist_update_lpi(&s->cpu[i]);
+}
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 3e0641aff9..184b92e7de 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) &&
+!(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index bf92a8d0f1..20f85a3759 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -226,6 +226,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+uint64_t rdbase;
IteEntry ite;
if (cmd == NONE) {
@@ -287,6 +288,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
* Current implementation only supports rdbase == procnum
* Hence rdbase physical address is ignored
*/
+rdbase = (cte & GITS_CTE_RDBASE_PROCNUM_MASK) >> 1U;
+
+if (rdbase > s->gicv3->num_cpu) {
+return res;
+}
+
+if ((cmd == CLEAR) || (cmd == DISCARD)) {
+gicv3_redist_process_lpi(&s->gicv3
[PATCH v6 05/10] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 5 -
hw/intc/arm_gicv3_redist.c | 12 +---
hw/intc/gicv3_internal.h | 2 ++
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..43128b376d 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return MEMTX_OK;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8645220d61..fc3d95dcc6 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+if (value & GICR_CTLR_ENABLE_LPIS) {
+cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+} else {
+cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+}
+}
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 6e0343b0e2..b27e25dea3 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,8 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_SHIFT 17
+
/* 16 bits EventId */
#define GICD_TYPER_IDBITS0xf
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_com
[PATCH v6 01/10] hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 245 +
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c| 2 +-
hw/intc/gicv3_internal.h | 97 +-
hw/intc/meson.build| 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 347 insertions(+), 14 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 00..2286b3f757
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,245 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+#include "qapi/error.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+GICv3ITSCommonClass parent_class;
+void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_readl(s, offset, data, attrs);
+break;
+case 8:
+result = its_readll(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+result = MEMTX_OK;
+*data = 0;
+}
+return result;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_writel(s, offset, data, attrs);
+break;
+case 8:
+result = its_writell(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data a
[PATCH v6 03/10] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c | 305 +++
hw/intc/gicv3_internal.h | 40 +
2 files changed, 345 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 683d40182f..05cdc15e77 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -50,6 +50,304 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return res;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
+
+valid = (value & CMD_FIELD_VALID_MASK);
+
+if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+res = update_cte(s, icid, valid, rdbase);
+}
+
+return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ (itt_addr << GITS_DTE_ITTADDR_SHIFT);
+}
+} else {
+return res;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTX
[PATCH v6 04/10] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 354 -
hw/intc/gicv3_internal.h | 12 +
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 367 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 05cdc15e77..bf92a8d0f1 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
+typedef struct {
+uint32_t iteh;
+uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -50,6 +66,323 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+ ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
+ sizeof(uint32_t)), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+}
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+IteEntry ite;
+
+itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+memset(&ite, 0 , sizeof(ite));
+ite.itel = address_space_ldq_le(as, itt_addr +
+(eventid * sizeof(uint64_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
+sizeof(uint64_t)) * sizeof(uint32_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (ite.itel & TABLE_ENTRY_VALID_MASK) {
+if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
+GITS_TYPE_PHYSICAL) {
+*pIntid = (ite.itel & ITE_ENTRY_INTID_MASK) >>
+
[PATCH v6 09/10] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 ++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b96f06014..1d8c44685c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2720,6 +2734,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2766,8 +2786,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
static void virt_machine_6_0_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_6_1_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+/* qemu ITS was introduced with 6.1 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 921416f918..f873ab9068 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v6 00/10] GICv3 LPI and ITS feature implementation
This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v6: - made changes to masking scheme being used in all relevant sections - updated process_mapti to validate idbits based on GICD_TYPER.IDbits instead of GICR_PROPBASER.IDbits - updated its_realize() to check every CPU for physical LPI support in each associated redistibutor and return error if not - removed GICR_TYPER_PLPIS check in its_reset() - addressed pending v4 comments in gicv3_internal.h #defines - refactored gicv3_redist_lpi_pending() as per v5 comments - added iasl disassembly for new IORT.pxb file - addressed all v5 comments around code formatting and gicv3_internal.h #defines - All kvm_unit_tests PASS Shashi Mallela (10): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/sbsa-ref.c | 26 +- hw/arm/virt.c | 28 +- hw/intc/arm_gicv3.c| 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c |7 +- hw/intc/arm_gicv3_dist.c |5 +- hw/intc/arm_gicv3_its.c| 1301 hw/intc/arm_gicv3_its_common.c |7 +- hw/intc/arm_gicv3_its_kvm.c|2 +- hw/intc/arm_gicv3_redist.c | 154 ++- hw/intc/gicv3_internal.h | 189 +++- hw/intc/meson.build|1 + include/hw/arm/virt.h |2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h |4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp| Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 20 files changed, 1771 insertions(+), 27 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb -- 2.27.0
[PATCH v6 02/10] hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 431 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 2286b3f757..683d40182f 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -29,6 +29,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+uint64_t result = 0;
+
+switch (page_sz) {
+case GITS_PAGE_SIZE_4K:
+case GITS_PAGE_SIZE_16K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDR);
+break;
+
+case GITS_PAGE_SIZE_64K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+break;
+
+default:
+break;
+}
+return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+uint16_t num_pages = 0;
+uint8_t page_sz_type;
+uint8_t type;
+uint32_t page_sz = 0;
+uint64_t value;
+
+for (int i = 0; i < 8; i++) {
+value = s->baser[i];
+
+if (!value) {
+continue;
+}
+
+page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+switch (page_sz_type) {
+case 0:
+page_sz = GITS_PAGE_SIZE_4K;
+break;
+
+case 1:
+page_sz = GITS_PAGE_SIZE_16K;
+break;
+
+case 2:
+case 3:
+page_sz = GITS_PAGE_SIZE_64K;
+break;
+
+default:
+g_assert_not_reached();
+}
+
+num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+switch (type) {
+
+case GITS_BASER_TYPE_DEVICE:
+memset(&s->dt, 0 , sizeof(s->dt));
+s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+if (!s->dt.valid) {
+return;
+}
+
+s->dt.page_sz = page_sz;
+s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->dt.indirect) {
+s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+} else {
+s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+}
+
+s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+s->dt.base_addr = baser_base_addr(value, page_sz);
+
+break;
+
+case GITS_BASER_TYPE_COLLECTION:
+memset(&s->ct, 0 , sizeof(s->ct));
+s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+/*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+if (!s->ct.valid) {
+return;
+}
+
+s->ct.page_sz = page_sz;
+s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->ct.indirect) {
+s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+} else {
+s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+}
+
+if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+GITS_TYPER, CIDBITS) + 1));
+} else {
+/* 16-bit CollectionId supported when CIL == 0 */
+s->ct.maxids.max_collids = (1UL << 16);
+}
+
+s->ct.ba
Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
On Mon, 2021-07-05 at 19:58 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 18:04, wrote:
> > On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> > > On Mon, 5 Jul 2021 at 16:55, wrote:
> > > > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > > > shashi.mall...@linaro.org> wrote:
> > > > > > Added register definitions relevant to ITS,implemented
> > > > > > overall
> > > > > > ITS device framework with stubs for ITS control and
> > > > > > translater
> > > > > > regions read/write,extended ITS common to handle mmio init
> > > > > > between
> > > > > > existing kvm device and newer qemu device.
> > > > > >
> > > > > > Signed-off-by: Shashi Mallela
> > > > > > Reviewed-by: Peter Maydell
> > > > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > > > **errp)
> > > > > > +{
> > > > > > +GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > > > +
> > > > > > +gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > > > &gicv3_its_translation_ops);
> > > > > > +
> > > > > > +if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > > > >
> > > > > Can you remind me why we make this check, please? When would
> > > > > we
> > > > > have created an ITS device but not have a GICv3 with LPI
> > > > > support?
> > > > This check applies to GIC's physical LPI support only as
> > > > against
> > > > GIC's
> > > > virtual LPI support.
> > >
> > > Right, but when would we have a GIC with no physical LPI support
> > > but an ITS is present ?
> > If we only support Direct injection of virtual interrupts (which
> > can
> > have their own vPEID and the vPE table),then the ITS present could
> > havejust virtual LPI support
>
> This patchset does not support a virtual-LPI-only ITS, though:
> it doesn't support virtual LPIs at all.
> If you use it with CPUs without physical LPI support , this code will
> skip
> entirely setting GITS_TYPER and will make reset do nothing, and then
> the
> rest of the ITS implementation will misbehave.
>
> I think what we should do is:
> * in realize, check every CPU to make sure its redistributor
>supports physical LPIs, and return an error from realize if not
> * in reset, don't check anything
Done
>
> If we add virtual-LPI-only ITS support later, we can always update
> this code appropriately.
>
> thanks
> -- PMM
Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
On Tue, 2021-07-06 at 14:27 +0100, Peter Maydell wrote: > On Tue, 6 Jul 2021 at 13:46, wrote: > > On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote: > > > On Tue, 6 Jul 2021 at 04:25, wrote: > > > > > > But the pseudocode for MAPTI does not say anywhere that we should > > > be checking the pIntID against any CPU's GICR_PROPBASER field. > > > It is checked only by the checks in LPIOutOfRange(), which tests: > > > * is it larger than permitted by GICD_TYPER.IDbits > > > * is it not in the LPI range and not 1023 > > > > > > Checking whether the intID is too big and would cause us to index > > > off the end of the redistributor's configuration table should be > > > done > > > later, only when the ITS actually sends the interrupt to a > > > particular > > > redistributor, I think. > > > > > > (You can't rely on the guest having done the MAPC before the > > > MAPTI; > > > and in any case the guest could choose to do a MAPC to a > > > different > > > redistributor after it's done the MAPTI.) > > We already have the "intID too big check" in place within the > > redistributor processing when ITS sends the interrupt trigger. > > "the LPI range and not 1023" is also handled in this function,but > > for > > validating "is it larger than permitted by GICD_TYPER.IDbits",the > > source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up > > min of > > GICR_PROPBASER.IDbits and GICD_TYPER.IDBits. > > > > If we are to not use gicr_propbaser,then are we good to just accept > > the > > intID value here since we are validating the same during interrupt > > processing? > > You should check the things the pseudocode says you should check. > When processing MAPTI, that's GICD_TYPER.IDbits. > GICR_PROPBASER.IDbits > is not the same thing because the guest can set it to a smaller > value. Have made changes in code to check "intID too big" case using GICD_TYPER.IDbits instead of GICR_PROPBASER.IDbits > thanks > -- PMM
Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
On Tue, 2021-07-06 at 09:44 +0200, Eric Auger wrote:
> Hi,
>
> On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS common to handle mmio init between
> > existing kvm device and newer qemu device.
> >
> > Signed-off-by: Shashi Mallela
> > Reviewed-by: Peter Maydell
>
> Some of my comments in v4 were not commented nor addressed in v5.
>
> Also here and in the other respinned patches, please add an
> individual
> history log to track the major changes you made from n-1 to n to help
> the review.
Have addressed all the pending v4 comments and summarized all major
changes in v6 series in the cover-letter section
> Thanks
>
> Eric
> > ---
> > hw/intc/arm_gicv3_its.c| 240
> > +
> > hw/intc/arm_gicv3_its_common.c | 7 +-
> > hw/intc/arm_gicv3_its_kvm.c| 2 +-
> > hw/intc/gicv3_internal.h | 88 +++--
> > hw/intc/meson.build| 1 +
> > include/hw/intc/arm_gicv3_its_common.h | 9 +-
> > 6 files changed, 331 insertions(+), 16 deletions(-)
> > create mode 100644 hw/intc/arm_gicv3_its.c
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > new file mode 100644
> > index 00..545cda3665
> > --- /dev/null
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -0,0 +1,240 @@
> > +/*
> > + * ITS emulation for a GICv3-based system
> > + *
> > + * Copyright Linaro.org 2021
> > + *
> > + * Authors:
> > + * Shashi Mallela
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2
> > or (at your
> > + * option) any later version. See the COPYING file in the top-
> > level directory.
> > + *
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/intc/arm_gicv3_its_common.h"
> > +#include "gicv3_internal.h"
> > +#include "qom/object.h"
> > +
> > +typedef struct GICv3ITSClass GICv3ITSClass;
> > +/* This is reusing the GICv3ITSState typedef from
> > ARM_GICV3_ITS_COMMON */
> > +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> > + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> > +
> > +struct GICv3ITSClass {
> > +GICv3ITSCommonClass parent_class;
> > +void (*parent_reset)(DeviceState *dev);
> > +};
> > +
> > +static MemTxResult gicv3_its_translation_write(void *opaque,
> > hwaddr offset,
> > + uint64_t data,
> > unsigned size,
> > + MemTxAttrs attrs)
> > +{
> > +MemTxResult result = MEMTX_OK;
> > +
> > +return result;
> > +}
> > +
> > +static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > +MemTxResult result = MEMTX_OK;
> > +
> > +return result;
> > +}
> > +
> > +static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > +MemTxResult result = MEMTX_OK;
> > +
> > +return result;
> > +}
> > +
> > +static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > +MemTxResult result = MEMTX_OK;
> > +
> > +return result;
> > +}
> > +
> > +static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > +MemTxResult result = MEMTX_OK;
> > +
> > +return result;
> > +}
> > +
> > +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset,
> > uint64_t *data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
> > +GICv3ITSState *s = (GICv3ITSState *)opaque;
> > +MemTxResult result;
> > +
> > +switch (size) {
> > +case 4:
> > +result = its_readl(s, offset, data, attrs);
> > +break;
> > +case 8:
> > +result = its_readll(s, offset, data, attrs);
> > +break;
> > +default:
> > +result =
Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
On Tue, 2021-07-06 at 11:27 +0200, Eric Auger wrote: > Hi, > > On 7/5/21 4:07 PM, Peter Maydell wrote: > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela < > > shashi.mall...@linaro.org> wrote: > > > Added ITS command queue handling for MAPTI,MAPI commands,handled > > > ITS > > > translation which triggers an LPI via INT command as well as > > > write > > > to GITS_TRANSLATER register,defined enum to differentiate between > > > ITS > > > command interrupt trigger and GITS_TRANSLATER based interrupt > > > trigger. > > > Each of these commands make use of other functionalities > > > implemented to > > > get device table entry,collection table entry or interrupt > > > translation > > > table entry required for their processing. > > > > > > Signed-off-by: Shashi Mallela > > > --- > > > hw/intc/arm_gicv3_its.c| 361 > > > - > > > hw/intc/gicv3_internal.h | 26 +++ > > > include/hw/intc/arm_gicv3_common.h | 2 + > > > 3 files changed, 388 insertions(+), 1 deletion(-) > > > +/* > > > + * This function handles the processing of following commands > > > based on > > > + * the ItsCmdType parameter passed:- > > > + * 1. trigerring of lpi interrupt translation via ITS INT > > > command > > > + * 2. trigerring of lpi interrupt translation via > > > gits_translater register > > > + * 3. handling of ITS CLEAR command > > > + * 4. handling of ITS DISCARD command > > > + */ > > > > "triggering" > > > > > #define DEVID_SHIFT 32 > > > #define DEVID_MASKMAKE_64BIT_MASK(32, 32) > > > @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32) > > > * vPEID = 16 bits > > > */ > > > #define ITS_ITT_ENTRY_SIZE0xC > > > +#define ITE_ENTRY_INTTYPE_SHIFT1 > > > +#define ITE_ENTRY_INTID_SHIFT 2 > > > +#define ITE_ENTRY_INTID_MASK ((1ULL << 24) - 1) > > > +#define ITE_ENTRY_INTSP_SHIFT 26 > > > +#define ITE_ENTRY_ICID_MASK ((1ULL << 16) - 1) > > > > This is still using a MASK value that's at the bottom of the > > integer, not in its shifted location. > There are other locations, pointed out by former comments, where this > kind of unusual masking scheme is used but well... Have taken care of masking scheme as desired in all relevant sections in v6 patch > > Thanks > > Eric > > > Otherwise > > Reviewed-by: Peter Maydell > > > > thanks > > -- PMM > >
Re: [PATCH v4 1/8] hw/intc: GICv3 ITS initial framework
On Tue, 2021-07-06 at 16:04 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 7/6/21 3:24 PM, shashi.mall...@linaro.org wrote:
> > Hi Eric,
> >
> > Please find my response inline(below):-
> >
> > On Tue, 2021-07-06 at 09:38 +0200, Eric Auger wrote:
> > > Hi,
> > >
> > > On 6/11/21 6:21 PM, Eric Auger wrote:
> > > > Hi,
> > > >
> > > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > > Added register definitions relevant to ITS,implemented
> > > > > overall
> > > > > ITS device framework with stubs for ITS control and
> > > > > translater
> > > > > regions read/write,extended ITS common to handle mmio init
> > > > > between
> > > > > existing kvm device and newer qemu device.
> > > > >
> > > > > Signed-off-by: Shashi Mallela
> > > > > ---
> > > > > hw/intc/arm_gicv3_its.c| 240
> > > > > +
> > > > > hw/intc/arm_gicv3_its_common.c | 8 +-
> > > > > hw/intc/arm_gicv3_its_kvm.c| 2 +-
> > > > > hw/intc/gicv3_internal.h | 88 +++--
> > > > > hw/intc/meson.build| 1 +
> > > > > include/hw/intc/arm_gicv3_its_common.h | 9 +-
> > > > > 6 files changed, 331 insertions(+), 17 deletions(-)
> > > > > create mode 100644 hw/intc/arm_gicv3_its.c
> > > > >
> > > > > diff --git a/hw/intc/arm_gicv3_its.c
> > > > > b/hw/intc/arm_gicv3_its.c
> > > > > new file mode 100644
> > > > > index 00..545cda3665
> > > > > --- /dev/null
> > > > > +++ b/hw/intc/arm_gicv3_its.c
> > > > > @@ -0,0 +1,240 @@
> > > > > +/*
> > > > > + * ITS emulation for a GICv3-based system
> > > > > + *
> > > > > + * Copyright Linaro.org 2021
> > > > > + *
> > > > > + * Authors:
> > > > > + * Shashi Mallela
> > > > > + *
> > > > > + * This work is licensed under the terms of the GNU GPL,
> > > > > version
> > > > > 2 or (at your
> > > > > + * option) any later version. See the COPYING file in the
> > > > > top-
> > > > > level directory.
> > > > > + *
> > > > > + */
> > > > > +
> > > > > +#include "qemu/osdep.h"
> > > > > +#include "qemu/log.h"
> > > > > +#include "hw/qdev-properties.h"
> > > > > +#include "hw/intc/arm_gicv3_its_common.h"
> > > > > +#include "gicv3_internal.h"
> > > > > +#include "qom/object.h"
> > > > > +
> > > > > +typedef struct GICv3ITSClass GICv3ITSClass;
> > > > > +/* This is reusing the GICv3ITSState typedef from
> > > > > ARM_GICV3_ITS_COMMON */
> > > > > +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> > > > > + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> > > > > +
> > > > > +struct GICv3ITSClass {
> > > > > +GICv3ITSCommonClass parent_class;
> > > > > +void (*parent_reset)(DeviceState *dev);
> > > > > +};
> > > > > +
> > > > > +static MemTxResult gicv3_its_translation_write(void *opaque,
> > > > > hwaddr offset,
> > > > > + uint64_t
> > > > > data,
> > > > > unsigned size,
> > > > > + MemTxAttrs
> > > > > attrs)
> > > > > +{
> > > > > +MemTxResult result = MEMTX_OK;
> > > > > +
> > > > > +return result;
> > > > > +}
> > > > > +
> > > > > +static MemTxResult its_writel(GICv3ITSState *s, hwaddr
> > > > > offset,
> > > > > + uint64_t value, MemTxAttrs
> > > > > attrs)
> > > > > +{
> > > > > +MemTxResult result = MEMTX_OK;
> > > > > +
> > > > > +return result;
> > > > > +}
> > > > > +
> > > > > +static MemTxResult its_readl(GICv3ITSState *s, hwaddr
> > > > > offset,
> > > > > +
Re: [PATCH v4 1/8] hw/intc: GICv3 ITS initial framework
Hi Eric,
Please find my response inline(below):-
On Tue, 2021-07-06 at 09:38 +0200, Eric Auger wrote:
> Hi,
>
> On 6/11/21 6:21 PM, Eric Auger wrote:
> > Hi,
> >
> > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > Added register definitions relevant to ITS,implemented overall
> > > ITS device framework with stubs for ITS control and translater
> > > regions read/write,extended ITS common to handle mmio init
> > > between
> > > existing kvm device and newer qemu device.
> > >
> > > Signed-off-by: Shashi Mallela
> > > ---
> > > hw/intc/arm_gicv3_its.c| 240
> > > +
> > > hw/intc/arm_gicv3_its_common.c | 8 +-
> > > hw/intc/arm_gicv3_its_kvm.c| 2 +-
> > > hw/intc/gicv3_internal.h | 88 +++--
> > > hw/intc/meson.build| 1 +
> > > include/hw/intc/arm_gicv3_its_common.h | 9 +-
> > > 6 files changed, 331 insertions(+), 17 deletions(-)
> > > create mode 100644 hw/intc/arm_gicv3_its.c
> > >
> > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > new file mode 100644
> > > index 00..545cda3665
> > > --- /dev/null
> > > +++ b/hw/intc/arm_gicv3_its.c
> > > @@ -0,0 +1,240 @@
> > > +/*
> > > + * ITS emulation for a GICv3-based system
> > > + *
> > > + * Copyright Linaro.org 2021
> > > + *
> > > + * Authors:
> > > + * Shashi Mallela
> > > + *
> > > + * This work is licensed under the terms of the GNU GPL, version
> > > 2 or (at your
> > > + * option) any later version. See the COPYING file in the top-
> > > level directory.
> > > + *
> > > + */
> > > +
> > > +#include "qemu/osdep.h"
> > > +#include "qemu/log.h"
> > > +#include "hw/qdev-properties.h"
> > > +#include "hw/intc/arm_gicv3_its_common.h"
> > > +#include "gicv3_internal.h"
> > > +#include "qom/object.h"
> > > +
> > > +typedef struct GICv3ITSClass GICv3ITSClass;
> > > +/* This is reusing the GICv3ITSState typedef from
> > > ARM_GICV3_ITS_COMMON */
> > > +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> > > + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> > > +
> > > +struct GICv3ITSClass {
> > > +GICv3ITSCommonClass parent_class;
> > > +void (*parent_reset)(DeviceState *dev);
> > > +};
> > > +
> > > +static MemTxResult gicv3_its_translation_write(void *opaque,
> > > hwaddr offset,
> > > + uint64_t data,
> > > unsigned size,
> > > + MemTxAttrs attrs)
> > > +{
> > > +MemTxResult result = MEMTX_OK;
> > > +
> > > +return result;
> > > +}
> > > +
> > > +static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> > > + uint64_t value, MemTxAttrs attrs)
> > > +{
> > > +MemTxResult result = MEMTX_OK;
> > > +
> > > +return result;
> > > +}
> > > +
> > > +static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> > > + uint64_t *data, MemTxAttrs attrs)
> > > +{
> > > +MemTxResult result = MEMTX_OK;
> > > +
> > > +return result;
> > > +}
> > > +
> > > +static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> > > + uint64_t value, MemTxAttrs attrs)
> > > +{
> > > +MemTxResult result = MEMTX_OK;
> > > +
> > > +return result;
> > > +}
> > > +
> > > +static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> > > + uint64_t *data, MemTxAttrs attrs)
> > > +{
> > > +MemTxResult result = MEMTX_OK;
> > > +
> > > +return result;
> > > +}
> > > +
> > > +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset,
> > > uint64_t *data,
> > > + unsigned size, MemTxAttrs
> > > attrs)
> > > +{
> > > +GICv3ITSState *s = (GICv3ITSState *)opaque;
> > > +MemTxResult result;
> > > +
> > > +switch (size) {
> > > +case 4:
&
Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote: > On Tue, 6 Jul 2021 at 04:25, wrote: > > On Mon, 2021-07-05 at 20:47 -0400, shashi.mall...@linaro.org wrote: > > > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote: > > > > I missed this the first time around, but I don't think this is > > > > right. > > > > Different CPUs could have different GICR_PROPBASER values, so > > > > checking > > > > against just one of them is wrong. The pseudocode only tests > > > > LPIOutOfRange() > > > > which is documented as testing "larger than GICD_TYPER.IDbits > > > > or > > > > not > > > > in > > > > the LPI range and not 1023". So I don't think we should be > > > > looking > > > > at the GICR_PROPBASER field here. > > > > > > > > More generally, "s->gicv3->cpu->something" is usually going to > > > > be > > > > wrong, because it is implicitly looking at CPU 0; often either > > > > there > > > > should be something else telling is which CPU to use (as in > > > > &s->gicv3->cpu[rdbase] where the CTE told us which > > > > redistributor), > > > > or we might need to operate on all CPUs/redistributors. The > > > > only > > > > exception is where we can guarantee that all the CPUs are the > > > > same > > > > (eg when looking at GICR_TYPER.PLPIS.) > > Please ignore my last comment. > > > > To address this scenario,i think the feasible option would be to > > call > > get_cte() to get the rdbase corresponding to icid value passed to > > mapti > > command.Since each icid is mapped to a rdbase(by virtue of calling > > MAPC > > command),if the collection table has a valid mapping for this icid > > we > > continue processing this MAPTI command using &s->gicv3->cpu[rdbase] > > applicable propbaser value to validate idbits, else return without > > further processing. > > But the pseudocode for MAPTI does not say anywhere that we should > be checking the pIntID against any CPU's GICR_PROPBASER field. > It is checked only by the checks in LPIOutOfRange(), which tests: > * is it larger than permitted by GICD_TYPER.IDbits > * is it not in the LPI range and not 1023 > > Checking whether the intID is too big and would cause us to index > off the end of the redistributor's configuration table should be done > later, only when the ITS actually sends the interrupt to a particular > redistributor, I think. > > (You can't rely on the guest having done the MAPC before the MAPTI; > and in any case the guest could choose to do a MAPC to a different > redistributor after it's done the MAPTI.) > > thanks > -- PMM We already have the "intID too big check" in place within the redistributor processing when ITS sends the interrupt trigger. "the LPI range and not 1023" is also handled in this function,but for validating "is it larger than permitted by GICD_TYPER.IDbits",the source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up min of GICR_PROPBASER.IDbits and GICD_TYPER.IDBits. If we are to not use gicr_propbaser,then are we good to just accept the intID value here since we are validating the same during interrupt processing?
Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
On Mon, 2021-07-05 at 20:47 -0400, shashi.mall...@linaro.org wrote:
> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mall...@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > > ITS
> > > translation which triggers an LPI via INT command as well as
> > > write
> > > to GITS_TRANSLATER register,defined enum to differentiate between
> > > ITS
> > > command interrupt trigger and GITS_TRANSLATER based interrupt
> > > trigger.
> > > Each of these commands make use of other functionalities
> > > implemented to
> > > get device table entry,collection table entry or interrupt
> > > translation
> > > table entry required for their processing.
> > >
> > > Signed-off-by: Shashi Mallela
> > > ---
> > > +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t
> > > value,
> > > + uint32_t offset, bool
> > > ignore_pInt)
> > > +{
> > > +AddressSpace *as = &s->gicv3->dma_as;
> > > +uint32_t devid, eventid;
> > > +uint32_t pIntid = 0;
> > > +uint32_t max_eventid, max_Intid;
> > > +bool dte_valid;
> > > +MemTxResult res = MEMTX_OK;
> > > +uint16_t icid = 0;
> > > +uint64_t dte = 0;
> > > +IteEntry ite;
> > > +uint32_t int_spurious = INTID_SPURIOUS;
> > > +uint64_t idbits;
> > > +
> > > +devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> > > +offset += NUM_BYTES_IN_DW;
> > > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > > + MEMTXATTRS_UNSPECIFIED, &res);
> > > +
> > > +if (res != MEMTX_OK) {
> > > +return res;
> > > +}
> > > +
> > > +eventid = (value & EVENTID_MASK);
> > > +
> > > +if (!ignore_pInt) {
> > > +pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> > > +}
> > > +
> > > +offset += NUM_BYTES_IN_DW;
> > > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > > + MEMTXATTRS_UNSPECIFIED, &res);
> > > +
> > > +if (res != MEMTX_OK) {
> > > +return res;
> > > +}
> > > +
> > > +icid = value & ICID_MASK;
> > > +
> > > +dte = get_dte(s, devid, &res);
> > > +
> > > +if (res != MEMTX_OK) {
> > > +return res;
> > > +}
> > > +dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> > > +
> > > +max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> > > +
> > > +if (!ignore_pInt) {
> > > +idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser,
> > > GICR_PROPBASER,
> > > +IDBITS), GICD_TYPER_IDBITS);
> >
> > I missed this the first time around, but I don't think this is
> > right.
> > Different CPUs could have different GICR_PROPBASER values, so
> > checking
> > against just one of them is wrong. The pseudocode only tests
> > LPIOutOfRange()
> > which is documented as testing "larger than GICD_TYPER.IDbits or
> > not
> > in
> > the LPI range and not 1023". So I don't think we should be looking
> > at the GICR_PROPBASER field here.
> >
> > More generally, "s->gicv3->cpu->something" is usually going to be
> > wrong, because it is implicitly looking at CPU 0; often either
> > there
> > should be something else telling is which CPU to use (as in
> > &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
> > or we might need to operate on all CPUs/redistributors. The only
> > exception is where we can guarantee that all the CPUs are the same
> > (eg when looking at GICR_TYPER.PLPIS.)
> In that case,the validation of IDBITS(in case of ITS enabled) could
> be
> done during the write of gicr_propbaser register value itself(in
> arm_gicv3_redist.c) and the its command processing code here can just
> extract the idbits for its use.
> > thanks
> > -- PMM
Hi Peter
Please ignore my last comment.
To address this scenario,i think the feasible option would be to call
get_cte() to get the rdbase corresponding to icid value passed to mapti
command.Since each icid is mapped to a rdbase(by virtue of calling MAPC
command),if the collection table has a valid mapping for this icid we
continue processing this MAPTI command using &s->gicv3->cpu[rdbase]
applicable propbaser value to validate idbits, else return without
further processing.
Thanks
Shashi
Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GITS_TRANSLATER register,defined enum to differentiate between
> > ITS
> > command interrupt trigger and GITS_TRANSLATER based interrupt
> > trigger.
> > Each of these commands make use of other functionalities
> > implemented to
> > get device table entry,collection table entry or interrupt
> > translation
> > table entry required for their processing.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
> > + uint32_t offset, bool
> > ignore_pInt)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint32_t devid, eventid;
> > +uint32_t pIntid = 0;
> > +uint32_t max_eventid, max_Intid;
> > +bool dte_valid;
> > +MemTxResult res = MEMTX_OK;
> > +uint16_t icid = 0;
> > +uint64_t dte = 0;
> > +IteEntry ite;
> > +uint32_t int_spurious = INTID_SPURIOUS;
> > +uint64_t idbits;
> > +
> > +devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> > +offset += NUM_BYTES_IN_DW;
> > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +
> > +eventid = (value & EVENTID_MASK);
> > +
> > +if (!ignore_pInt) {
> > +pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> > +}
> > +
> > +offset += NUM_BYTES_IN_DW;
> > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +
> > +icid = value & ICID_MASK;
> > +
> > +dte = get_dte(s, devid, &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> > +
> > +max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> > +
> > +if (!ignore_pInt) {
> > +idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser,
> > GICR_PROPBASER,
> > +IDBITS), GICD_TYPER_IDBITS);
>
> I missed this the first time around, but I don't think this is right.
> Different CPUs could have different GICR_PROPBASER values, so
> checking
> against just one of them is wrong. The pseudocode only tests
> LPIOutOfRange()
> which is documented as testing "larger than GICD_TYPER.IDbits or not
> in
> the LPI range and not 1023". So I don't think we should be looking
> at the GICR_PROPBASER field here.
>
> More generally, "s->gicv3->cpu->something" is usually going to be
> wrong, because it is implicitly looking at CPU 0; often either there
> should be something else telling is which CPU to use (as in
> &s->gicv3->cpu[rdbase] where the CTE told us which redistributor),
> or we might need to operate on all CPUs/redistributors. The only
> exception is where we can guarantee that all the CPUs are the same
> (eg when looking at GICR_TYPER.PLPIS.)
In that case,the validation of IDBITS(in case of ITS enabled) could be
done during the write of gicr_propbaser register value itself(in
arm_gicv3_redist.c) and the its command processing code here can just
extract the idbits for its use.
>
> thanks
> -- PMM
Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 16:55, wrote:
> > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > shashi.mall...@linaro.org> wrote:
> > > > Added register definitions relevant to ITS,implemented overall
> > > > ITS device framework with stubs for ITS control and translater
> > > > regions read/write,extended ITS common to handle mmio init
> > > > between
> > > > existing kvm device and newer qemu device.
> > > >
> > > > Signed-off-by: Shashi Mallela
> > > > Reviewed-by: Peter Maydell
> > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > **errp)
> > > > +{
> > > > +GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > +
> > > > +gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > &gicv3_its_translation_ops);
> > > > +
> > > > +if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > >
> > > Can you remind me why we make this check, please? When would we
> > > have created an ITS device but not have a GICv3 with LPI support?
> > This check applies to GIC's physical LPI support only as against
> > GIC's
> > virtual LPI support.
>
> Right, but when would we have a GIC with no physical LPI support
> but an ITS is present ?
If we only support Direct injection of virtual interrupts (which can
have their own vPEID and the vPE table),then the ITS present could havejust
virtual LPI support
>
> thanks
> -- PMM
Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS common to handle mmio init between
> > existing kvm device and newer qemu device.
> >
> > Signed-off-by: Shashi Mallela
> > Reviewed-by: Peter Maydell
> > +static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
> > +{
> > +GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > +
> > +gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > &gicv3_its_translation_ops);
> > +
> > +if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
>
> Can you remind me why we make this check, please? When would we
> have created an ITS device but not have a GICv3 with LPI support?
This check applies to GIC's physical LPI support only as against GIC's
virtual LPI support.
>
> Maybe it would be better to either
> (a) simply create the ITS and assume that the board connected it up
> to a GICv3 that supports it
> (b) check every CPU for whether PLPIS is set, and if one of them does
> not have it set then return an error from the ITS realize
>
> ?
>
> (Found this by looking for code where we do s->gicv3->cpu-
> >something...)
>
> > +/* set the ITS default features supported */
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
> > + GITS_TYPE_PHYSICAL);
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER,
> > ITT_ENTRY_SIZE,
> > + ITS_ITT_ENTRY_SIZE - 1);
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS,
> > ITS_IDBITS);
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS,
> > ITS_DEVBITS);
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
> > +s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS,
> > ITS_CIDBITS);
> > +}
> > +}
> > +
> > +static void gicv3_its_reset(DeviceState *dev)
> > +{
> > +GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > +GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
> > +
> > +if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
>
> Similarly here.
>
> > +c->parent_reset(dev);
> > +
> > +/* Quiescent bit reset to 1 */
> > +s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
> > +
> > +/*
> > + * setting GITS_BASER0.Type = 0b001 (Device)
> > + * GITS_BASER1.Type = 0b100 (Collection Table)
> > + * GITS_BASER.Type,where n = 3 to 7 are 0b00
> > (Unimplemented)
> > + * GITS_BASER<0,1>.Page_Size = 64KB
> > + * and default translation table entry size to 16 bytes
> > + */
> > +s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_DEVICE);
> > +s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > +s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_DTE_SIZE - 1);
> > +
> > +s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
> > + GITS_ITT_TYPE_COLLECTION);
> > +s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > PAGESIZE,
> > + GITS_BASER_PAGESIZE_64K);
> > +s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER,
> > ENTRYSIZE,
> > + GITS_CTE_SIZE - 1);
> > +}
> > +}
>
> thanks
> -- PMM
[PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3 ITS changes. Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..521acefe9ba66706c5607321a82d330586f3f280 100644 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 2ef211df59..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/IORT", -"tests/data/acpi/virt/IORT.memhp", -"tests/data/acpi/virt/IORT.numamem", -"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 ++--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b96f06014..1d8c44685c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2720,6 +2734,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2766,8 +2786,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
static void virt_machine_6_0_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_6_1_options(mc);
compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
+/* qemu ITS was introduced with 6.1 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 921416f918..f873ab9068 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes.Temporarily differences in these files are okay. Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | 0 tests/data/acpi/virt/IORT.memhp | 0 tests/data/acpi/virt/IORT.numamem | 0 tests/data/acpi/virt/IORT.pxb | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ef211df59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/IORT", +"tests/data/acpi/virt/IORT.memhp", +"tests/data/acpi/virt/IORT.numamem", +"tests/data/acpi/virt/IORT.pxb", -- 2.27.0
[PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -64,6 +64,7 @@ enum {
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
[SBSA_GIC_DIST] = { 0x4006, 0x0001 },
[SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
+[SBSA_GIC_ITS] ={ 0x4409, 0x0002 },
[SBSA_SECURE_EC] = { 0x5000, 0x1000 },
[SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
@@ -377,7 +379,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_ARM_GICV3_ITS);
+SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+sysbus_realize_and_unref(s, &error_fatal);
+sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +419,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +469,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -762,7 +782,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
-create_gic(sms);
+create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
--
2.27.0
[PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 5 -
hw/intc/arm_gicv3_redist.c | 12 +---
hw/intc/gicv3_internal.h | 9 ++---
include/hw/intc/arm_gicv3_common.h | 1 +
5 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..ae625d758a 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
+(s->lpi_enable << GICD_TYPER_LPIS_OFFSET) |
(0xf << 19) | itlinesnumber;
return MEMTX_OK;
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8645220d61..fc3d95dcc6 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
case GICR_CTLR:
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
- * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
- * implement LPIs) so Enable_LPIs is RES0. So there are no writable
- * bits for us.
+ * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
+ * implement LPIs) so Enable_LPIs is programmable.
*/
+if (cs->gicr_typer & GICR_TYPER_PLPIS) {
+if (value & GICR_CTLR_ENABLE_LPIS) {
+cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
+} else {
+cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
+}
+}
return MEMTX_OK;
case GICR_STATUSR:
/* RAZ/WI for our implementation */
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index f7675a5adc..43ce4a8a95 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,9 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_LPIS_OFFSET 17
+#define GICD_TYPER_IDBITS_OFFSET 19
+#define GICD_TYPER_IDBITS_MASK 0x1f
/* 16 bits EventId */
#define GICD_TYPER_IDBITS0xf
@@ -123,6 +12
[PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 24 -
hw/intc/arm_gicv3_redist.c | 142 +
hw/intc/gicv3_internal.h | 8 ++
include/hw/intc/arm_gicv3_common.h | 7 ++
7 files changed, 197 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..3f24707838 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,16 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
+(cs->hpplpi.prio != 0xff)) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
@@ -339,9 +349,13 @@ static void gicv3_set_irq(void *opaque, int irq, int level)
static void arm_gicv3_post_load(GICv3State *s)
{
+int i;
/* Recalculate our cached idea of the current highest priority
* pending interrupt, but don't set IRQ or FIQ lines.
*/
+for (i = 0; i < s->num_cpu; i++) {
+gicv3_redist_update_lpi(&s->cpu[i]);
+}
gicv3_full_update_noirqset(s);
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
gicv3_cache_all_target_cpustates(s);
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 3e0641aff9..184b92e7de 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -899,10 +899,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1318,7 +1320,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) &&
+!(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index adaee72c1f..5adb55a01a 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -225,6 +225,7 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+uint64_t rdbase;
IteEntry ite;
if (cmd == NONE) {
@@ -282,10 +283,18 @@ static MemTxResult process_its_cmd(GICv3ITSState *s,
uint64_t value,
* command in the queue
*/
} else {
-/*
- * Current implementation only supports rdbase == procnum
- * Hence rdbase physical address is ignored
- */
+rdbase = (cte >> 1U) & RDBASE_PROCNUM_MASK;
+
+if (rdbase > s->gicv3->num_cpu) {
+return res;
+}
+
+if ((cmd == CLEAR) || (cmd == DISCARD)) {
+
[PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 361 -
hw/intc/gicv3_internal.h | 26 +++
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 388 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 5919d8d7b1..adaee72c1f 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,22 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+/*
+ * This is an internal enum used to distinguish between LPI triggered
+ * via command queue and LPI triggered via gits_translater write.
+ */
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
+typedef struct {
+uint32_t iteh;
+uint64_t itel;
+} IteEntry;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -49,6 +65,330 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+return (*cte & TABLE_ENTRY_VALID_MASK) != 0;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ IteEntry ite)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+ ite.itel, MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
+ sizeof(uint32_t)), ite.iteh,
+ MEMTXATTRS_UNSPECIFIED, &res);
+}
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+IteEntry ite;
+
+itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+memset(&ite, 0 , sizeof(ite));
+ite.itel = address_space_ldq_le(as, itt_addr +
+(eventid * sizeof(uint64_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
+sizeof(uint64_t)) * sizeof(uint32_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (ite.itel & TABLE_ENTRY_VALID_MASK) {
+if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
+GITS_TYPE_PHYSICAL) {
+*pIntid = (ite.itel >> ITE_ENTRY_INTID_SHIFT) &
+ ITE_ENTRY_INTID_MASK;
+*icid = ite.iteh & ITE
[PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 31 +-
include/hw/intc/arm_gicv3_common.h | 3 +
include/hw/intc/arm_gicv3_its_common.h | 23 ++
4 files changed, 432 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 545cda3665..2d786a1e21 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,160 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
+{
+uint64_t result = 0;
+
+switch (page_sz) {
+case GITS_PAGE_SIZE_4K:
+case GITS_PAGE_SIZE_16K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDR);
+break;
+
+case GITS_PAGE_SIZE_64K:
+result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
+result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
+break;
+
+default:
+break;
+}
+return result;
+}
+
+/*
+ * This function extracts the ITS Device and Collection table specific
+ * parameters (like base_addr, size etc) from GITS_BASER register.
+ * It is called during ITS enable and also during post_load migration
+ */
+static void extract_table_params(GICv3ITSState *s)
+{
+uint16_t num_pages = 0;
+uint8_t page_sz_type;
+uint8_t type;
+uint32_t page_sz = 0;
+uint64_t value;
+
+for (int i = 0; i < 8; i++) {
+value = s->baser[i];
+
+if (!value) {
+continue;
+}
+
+page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
+
+switch (page_sz_type) {
+case 0:
+page_sz = GITS_PAGE_SIZE_4K;
+break;
+
+case 1:
+page_sz = GITS_PAGE_SIZE_16K;
+break;
+
+case 2:
+case 3:
+page_sz = GITS_PAGE_SIZE_64K;
+break;
+
+default:
+g_assert_not_reached();
+}
+
+num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
+
+type = FIELD_EX64(value, GITS_BASER, TYPE);
+
+switch (type) {
+
+case GITS_ITT_TYPE_DEVICE:
+memset(&s->dt, 0 , sizeof(s->dt));
+s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+if (!s->dt.valid) {
+return;
+}
+
+s->dt.page_sz = page_sz;
+s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->dt.indirect) {
+s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
+} else {
+s->dt.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->dt.entry_sz));
+}
+
+s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
+ DEVBITS) + 1));
+
+s->dt.base_addr = baser_base_addr(value, page_sz);
+
+break;
+
+case GITS_ITT_TYPE_COLLECTION:
+memset(&s->ct, 0 , sizeof(s->ct));
+s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
+
+/*
+ * GITS_TYPER.HCC is 0 for this implementation
+ * hence writes are discarded if ct.valid is 0
+ */
+if (!s->ct.valid) {
+return;
+}
+
+s->ct.page_sz = page_sz;
+s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
+s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
+
+if (!s->ct.indirect) {
+s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
+} else {
+s->ct.max_entries = (((num_pages * page_sz) /
+ L1TABLE_ENTRY_SIZE) *
+ (page_sz / s->ct.entry_sz));
+}
+
+if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
+s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
+GITS_TYPER, CIDBITS) + 1));
+} else {
+/* 16-bit CollectionId supported when CIL == 0 */
+s->ct.maxids.max_collids = (1UL << 16);
+}
+
+s->ct.base_addr = baser_base
[PATCH v5 01/10] hw/intc: GICv3 ITS initial framework
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 240 +
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c| 2 +-
hw/intc/gicv3_internal.h | 88 +++--
hw/intc/meson.build| 1 +
include/hw/intc/arm_gicv3_its_common.h | 9 +-
6 files changed, 331 insertions(+), 16 deletions(-)
create mode 100644 hw/intc/arm_gicv3_its.c
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
new file mode 100644
index 00..545cda3665
--- /dev/null
+++ b/hw/intc/arm_gicv3_its.c
@@ -0,0 +1,240 @@
+/*
+ * ITS emulation for a GICv3-based system
+ *
+ * Copyright Linaro.org 2021
+ *
+ * Authors:
+ * Shashi Mallela
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "gicv3_internal.h"
+#include "qom/object.h"
+
+typedef struct GICv3ITSClass GICv3ITSClass;
+/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+ ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
+
+struct GICv3ITSClass {
+GICv3ITSCommonClass parent_class;
+void (*parent_reset)(DeviceState *dev);
+};
+
+static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
+{
+MemTxResult result = MEMTX_OK;
+
+return result;
+}
+
+static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_readl(s, offset, data, attrs);
+break;
+case 8:
+result = its_readll(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest read at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+result = MEMTX_OK;
+*data = 0;
+}
+return result;
+}
+
+static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+GICv3ITSState *s = (GICv3ITSState *)opaque;
+MemTxResult result;
+
+switch (size) {
+case 4:
+result = its_writel(s, offset, data, attrs);
+break;
+case 8:
+result = its_writell(s, offset, data, attrs);
+break;
+default:
+result = MEMTX_ERROR;
+break;
+}
+
+if (result == MEMTX_ERROR) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid guest write at offset " TARGET_FMT_plx
+ "size %u\n", __func__, offset, size);
+/*
+ * The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+result =
[PATCH v5 00/10] GICv3 LPI and ITS feature implementation
This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v5: - v4 review comments addressed - All kvm_unit_tests PASS Shashi Mallela (10): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/sbsa-ref.c | 26 +- hw/arm/virt.c | 28 +- hw/intc/arm_gicv3.c| 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c |7 +- hw/intc/arm_gicv3_dist.c |5 +- hw/intc/arm_gicv3_its.c| 1296 hw/intc/arm_gicv3_its_common.c |7 +- hw/intc/arm_gicv3_its_kvm.c|2 +- hw/intc/arm_gicv3_redist.c | 154 ++- hw/intc/gicv3_internal.h | 187 +++- hw/intc/meson.build|1 + include/hw/arm/virt.h |2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h |4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp| Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 20 files changed, 1764 insertions(+), 27 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb -- 2.27.0
[PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 305 +++
hw/intc/gicv3_internal.h | 37 +
2 files changed, 342 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 2d786a1e21..5919d8d7b1 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -49,6 +49,304 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return res;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & TABLE_ENTRY_VALID_MASK) | (rdbase << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+valid_l2t = (value & L2_TABLE_VALID_MASK) != 0;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
+
+valid = (value & CMD_FIELD_VALID_MASK);
+
+if ((icid > s->ct.maxids.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation, in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+res = update_cte(s, icid, valid, rdbase);
+}
+
+return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & TABLE_ENTRY_VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ ((itt_addr & ITTADDR_MASK) << 6ULL);
+}
+} else {
+return res;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
Re: [PATCH v4 4/8] hw/intc: GICv3 ITS Command processing
Hi Eric,
Have taken care of the pending & latest "process_int" comment(below) by
renaming it to process_its_cmd to keep it more generic since it is also
handles other ITS commands and interrupt trigger both by INT command as
well as GITS_TRANSLATER write.Have added comments for this function as
well.
Will be sharing the updated patchset with all comments addressed soon.
Thanks
Shashi
On Mon, 2021-06-21 at 12:13 +0200, Eric Auger wrote:
>
> On 6/16/21 11:02 PM, shashi.mall...@linaro.org wrote:
> > Hi Eric,
> >
> > Please find my responses inline (below):-
> >
> > On Sun, 2021-06-13 at 17:55 +0200, Eric Auger wrote:
> > > Hi Shashi,
> > >
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Added ITS command queue handling for MAPTI,MAPI
> > > > commands,handled
> > > > ITS
> > > > translation which triggers an LPI via INT command as well as
> > > > write
> > > > to GITS_TRANSLATER register,defined enum to differentiate
> > > > between
> > > > ITS
> > > > command interrupt trigger and GITS_TRANSLATER based interrupt
> > > > trigger.
> > > > Each of these commands make use of other functionalities
> > > > implemented to
> > > > get device table entry,collection table entry or interrupt
> > > > translation
> > > > table entry required for their processing.
> > > >
> > > > Signed-off-by: Shashi Mallela
> > > > ---
> > > > hw/intc/arm_gicv3_its.c| 334
> > > > +
> > > > hw/intc/gicv3_internal.h | 12 ++
> > > > include/hw/intc/arm_gicv3_common.h | 2 +
> > > > 3 files changed, 348 insertions(+)
> > > >
> > > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > > index 6551c577b3..82bb5b84ef 100644
> > > > --- a/hw/intc/arm_gicv3_its.c
> > > > +++ b/hw/intc/arm_gicv3_its.c
> > > > @@ -28,6 +28,13 @@ struct GICv3ITSClass {
> > > > void (*parent_reset)(DeviceState *dev);
> > > > };
> > > >
> > > > +typedef enum ItsCmdType {
> > > > +NONE = 0, /* internal indication for GITS_TRANSLATER write
> > > > */
> > > > +CLEAR = 1,
> > > > +DISCARD = 2,
> > > > +INT = 3,
> > > > +} ItsCmdType;
> > > Add a comment to explain what this enum stand for. This sounds
> > > misleading to me versus the command IDs. Why don't you use the
> > > cmd id
> > > then and add NONE?
> > This is an internal enum used to distinguish between interrupt
> > triggered via command queue and interrupt triggered via
> > gits_translater
> > write.Will add the same comment in code.
> > Since NONE is only 1 command applicable for GITS_TRANSLATER,started
> > with it so that in the future if any further command queue commands
> > have to be added we can just extend the numbering.
> > > > +
> > > > static uint64_t baser_base_addr(uint64_t value, uint32_t
> > > > page_sz)
> > > > {
> > > > uint64_t result = 0;
> > > > @@ -49,6 +56,315 @@ static uint64_t baser_base_addr(uint64_t
> > > > value,
> > > > uint32_t page_sz)
> > > > return result;
> > > > }
> > > >
> > > > +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t
> > > > *cte,
> > > > +MemTxResult *res)
> > > > +{
> > > > +AddressSpace *as = &s->gicv3->dma_as;
> > > > +uint64_t l2t_addr;
> > > > +uint64_t value;
> > > > +bool valid_l2t;
> > > > +uint32_t l2t_id;
> > > > +uint32_t max_l2_entries;
> > > > +bool status = false;
> > > > +
> > > > +if (s->ct.indirect) {
> > > > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > > > +
> > > > +value = address_space_ldq_le(as,
> > > > + s->ct.base_addr +
> > > > + (l2t_id *
> > > > L1TABLE_ENTRY_SIZE),
> > > > + MEMTXATTRS_UNSPECIFIED,
> > > > res);
> > > > +
> > > > +if (*res == MEMTX_OK) {
> > > > +valid_l2t = (value >> VALID_SHIFT) &
Re: [PATCH v4 3/8] hw/intc: GICv3 ITS command queue framework
Hi Eric,
Please find my responses to your latest comments (taken care of)
inline:-
On Mon, 2021-06-21 at 12:03 +0200, Eric Auger wrote:
>
> On 6/16/21 11:02 PM, shashi.mall...@linaro.org wrote:
> > Hi Eric,
> >
> > Please find my responses inline (below):-
> >
> > On Sun, 2021-06-13 at 16:13 +0200, Eric Auger wrote:
> > > Hi Sashi,
> > >
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Added functionality to trigger ITS command queue processing on
> > > > write to CWRITE register and process each command queue entry
> > > > to
> > > > identify the command type and handle commands like
> > > > MAPD,MAPC,SYNC.
> > > >
> > > > Signed-off-by: Shashi Mallela
> > > > ---
> > > > hw/intc/arm_gicv3_its.c | 295
> > > > +++
> > > > hw/intc/gicv3_internal.h | 37 +
> > > > 2 files changed, 332 insertions(+)
> > > >
> > > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > > index af60f19c98..6551c577b3 100644
> > > > --- a/hw/intc/arm_gicv3_its.c
> > > > +++ b/hw/intc/arm_gicv3_its.c
> > > > @@ -49,6 +49,295 @@ static uint64_t baser_base_addr(uint64_t
> > > > value,
> > > > uint32_t page_sz)
> > > > return result;
> > > > }
> > > >
> > > > +static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid,
> > > > bool valid,
> > > > + uint64_t rdbase)
> > > > +{
> > > > +AddressSpace *as = &s->gicv3->dma_as;
> > > > +uint64_t value;
> > > > +uint64_t l2t_addr;
> > > > +bool valid_l2t;
> > > > +uint32_t l2t_id;
> > > > +uint32_t max_l2_entries;
> > > > +uint64_t cte = 0;
> > > > +MemTxResult res = MEMTX_OK;
> > > > +
> > > > +if (!s->ct.valid) {
> > > Isn't it a guest log error case. Also you return MEMTX_OK in that
> > > case.
> > > Is that what you want?
> > Yes,because the current implementation treats all command specific
> > errors as "ignored" and moves onto next command in the queue.MEMTX
> > return values are significant for dma read/write status and in case
> > of
> > error we stall the command processing
> OK
> > > > +return res;
> > > > +}
> > > > +
> > > > +if (valid) {
> > > > +/* add mapping entry to collection table */
> > > > +cte = (valid & VALID_MASK) |
> > > > + ((rdbase & RDBASE_PROCNUM_MASK) << 1ULL);
> > > Do you really need to sanitize rdbase again?
> > Not required,have rectified it.
> > > > +}
> > > > +
> > > > +/*
> > > > + * The specification defines the format of level 1 entries
> > > > of
> > > > a
> > > > + * 2-level table, but the format of level 2 entries and
> > > > the
> > > > format
> > > > + * of flat-mapped tables is IMPDEF.
> > > > + */
> > > > +if (s->ct.indirect) {
> > > > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > > > +
> > > > +value = address_space_ldq_le(as,
> > > > + s->ct.base_addr +
> > > > + (l2t_id *
> > > > L1TABLE_ENTRY_SIZE),
> > > > + MEMTXATTRS_UNSPECIFIED,
> > > > &res);
> > > > +
> > > > +if (res != MEMTX_OK) {
> > > > +return res;
> > > > +}
> > > > +
> > > > +valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > > > +
> > > > +if (valid_l2t) {
> > > > +max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > > > +
> > > > +l2t_addr = value & ((1ULL << 51) - 1);
> > > > +
> > > > +address_space_stq_le(as, l2t_addr +
> > > > + ((icid % max_l2_entries) *
> > > > GITS_CTE_SIZE),
> > > > + cte, MEMTXATTRS_UNSPECIFIED,
> > > > &res);
> > > > +}
> > >
Re: [PATCH v4 2/8] hw/intc: GICv3 ITS register definitions added
Hi Eric,
Have taken care of your latest comment,please find response inline :-
On Mon, 2021-06-21 at 11:51 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 6/16/21 11:02 PM, shashi.mall...@linaro.org wrote:
> > Hi Eric,
> >
> > Please find my responses inline (below):-
> >
> > On Sat, 2021-06-12 at 08:08 +0200, Eric Auger wrote:
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Defined descriptors for ITS device table,collection table and
> > > > ITS
> > > > command queue entities.Implemented register read/write
> > > > functions,
> > > > extract ITS table parameters and command queue
> > > > parameters,extended
> > > > gicv3 common to capture qemu address space(which host the ITS
> > > > table
> > > > platform memories required for subsequent ITS processing) and
> > > > initialize the same in ITS device.
> > > >
> > > > Signed-off-by: Shashi Mallela
> > > > ---
> > > > hw/intc/arm_gicv3_its.c| 335
> > > > +
> > > > hw/intc/gicv3_internal.h | 28 ++-
> > > > include/hw/intc/arm_gicv3_common.h | 3 +
> > > > include/hw/intc/arm_gicv3_its_common.h | 30 +++
> > > > 4 files changed, 395 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > > > index 545cda3665..af60f19c98 100644
> > > > --- a/hw/intc/arm_gicv3_its.c
> > > > +++ b/hw/intc/arm_gicv3_its.c
> > > > @@ -28,6 +28,157 @@ struct GICv3ITSClass {
> > > > void (*parent_reset)(DeviceState *dev);
> > > > };
> > > >
> > > > +static uint64_t baser_base_addr(uint64_t value, uint32_t
> > > > page_sz)
> > > > +{
> > > > +uint64_t result = 0;
> > > > +
> > > > +switch (page_sz) {
> > > > +case GITS_ITT_PAGE_SIZE_0:
> > > > +case GITS_ITT_PAGE_SIZE_1:
> > > > +result = value & R_GITS_BASER_PHYADDR_MASK;
> > > Use FIELD_EX64 as well for homogeneity?
> > Done
> > > > +break;
> > > > +
> > > > +case GITS_ITT_PAGE_SIZE_2:
> > > > +result = value & R_GITS_BASER_PHYADDRL_64K_MASK;
> > > here as well?
> > Done
> > > > +result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K)
> > > > <<
> > > > 48;
> > > > +break;
> > > > +
> > > > +default:
> > > > +break;
> > > > +}
> > > > +return result;
> > > > +}
> > > > +
> > > > +static void extract_table_params(GICv3ITSState *s)
> > > > +{
> > > > +uint16_t num_pages = 0;
> > > > +uint8_t page_sz_type;
> > > > +uint8_t type;
> > > > +uint32_t page_sz = 0;
> > > > +uint64_t value;
> > > > +
> > > > +for (int i = 0; i < 8; i++) {
> > > > +value = s->baser[i];
> > > > +
> > > > +if (!value) {
> > > > +continue;
> > > > +}
> > > > +
> > > > +page_sz_type = FIELD_EX64(value, GITS_BASER,
> > > > PAGESIZE);
> > > > +
> > > > +switch (page_sz_type) {
> > > > +case 0:
> > > > +page_sz = GITS_ITT_PAGE_SIZE_0;
> > > > +break;
> > > > +
> > > > +case 1:
> > > > +page_sz = GITS_ITT_PAGE_SIZE_1;
> > > > +break;
> > > > +
> > > > +case 2:
> > > > +case 3:
> > > > +page_sz = GITS_ITT_PAGE_SIZE_2;
> > > > +break;
> > > > +
> > > > +default:
> > > > +g_assert_not_reached();
> > > > +}
> > > > +
> > > > +num_pages = FIELD_EX64(value, GITS_BASER, SIZE);
> > > + 1 directly? and remove num_pages + 1 below.
> > Done
> > > > +
> > > > +type = FIELD_EX64(value, GITS_BASER, TYPE);
> > > > +
> > > > +switch (type) {
> > > > +
> > > > +case GITS_ITT_TYPE_DEVICE:
> > > > +memset(&s->dt, 0 , sizeof(s->dt));
> > > > +
Re: [PATCH v4 3/8] hw/intc: GICv3 ITS command queue framework
Hi Eric,
Had missed this comment earlier.Please find my response (inline)below:-
On Sun, 2021-06-13 at 16:39 +0200, Eric Auger wrote:
> Hi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added functionality to trigger ITS command queue processing on
> > write to CWRITE register and process each command queue entry to
> > identify the command type and handle commands like MAPD,MAPC,SYNC.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3_its.c | 295
> > +++
> > hw/intc/gicv3_internal.h | 37 +
> > 2 files changed, 332 insertions(+)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index af60f19c98..6551c577b3 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -49,6 +49,295 @@ static uint64_t baser_base_addr(uint64_t value,
> > uint32_t page_sz)
> > return result;
> > }
> >
> > +static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid,
> > bool valid,
> > + uint64_t rdbase)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint64_t value;
> > +uint64_t l2t_addr;
> > +bool valid_l2t;
> > +uint32_t l2t_id;
> > +uint32_t max_l2_entries;
> > +uint64_t cte = 0;
> > +MemTxResult res = MEMTX_OK;
> > +
> > +if (!s->ct.valid) {
> > +return res;
> > +}
> > +
> > +if (valid) {
> > +/* add mapping entry to collection table */
> > +cte = (valid & VALID_MASK) |
> > + ((rdbase & RDBASE_PROCNUM_MASK) << 1ULL);
> > +}
> > +
> > +/*
> > + * The specification defines the format of level 1 entries of
> > a
> > + * 2-level table, but the format of level 2 entries and the
> > format
> > + * of flat-mapped tables is IMPDEF.
> > + */
> > +if (s->ct.indirect) {
> > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > +value = address_space_ldq_le(as,
> > + s->ct.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED,
> > &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +
> > +valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > +
> > +if (valid_l2t) {
> > +max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > +
> > +l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > +address_space_stq_le(as, l2t_addr +
> > + ((icid % max_l2_entries) *
> > GITS_CTE_SIZE),
> > + cte, MEMTXATTRS_UNSPECIFIED,
> > &res);
> > +}
> > +} else {
> > +/* Flat level table */
> > +address_space_stq_le(as, s->ct.base_addr + (icid *
> > GITS_CTE_SIZE),
> > + cte, MEMTXATTRS_UNSPECIFIED, &res);
> > +}
> > +return res;
> > +}
>
> Looking at your DevTableDesc and CollTableDesc types again, they are
> basically the same except max_devids/max_collids. You may use a
> single
> one and it may be possible to define helpers to access an entry in
> the
> DT or CT.
will replace DevTableDesc/CollTableDesc types with a common TableDesc
type and introduce a new union member to hold one of
max_devids/max_collids to be referenced by all relevant functions.
>
> update_cte/update_dte looks quite similar if you compute the cte and
> dte
> externally and pass a pointer to the associated TableDesc?
update_cte/update_cte will (continue) to reference their respective
tables via existing Gicv3ItsState type but through the newly defined
common TableDesc type.
Hope this helps.
>
> Thanks
>
> Eric
>
>
> > +
> > +static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint16_t icid;
> > +uint64_t rdbase;
> > +bool valid;
> > +MemTxResult res = MEMTX_OK;
> > +uint64_t value;
> > +
> > +offset += NUM_BYTES_IN_DW;
> > +offset += NUM_BYTES_IN_DW;
> > +
> > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res)
Re: GICv3 for MTTCG
> > Thread 3 (Thread 0x7f461e9fd700 (LWP 24973)): > > #0 0x7f477c59ca35 in pthread_cond_wait@@GLIBC_2.3.2 () at > /lib64/libpthread.so.0 > > #1 0x55747d419b1d in qemu_cond_wait_impl (cond=0x55747f9f5b40, > mutex=0x55747e04dc00 , file=0x55747d5dbe5c > "../softmmu/cpus.c", line=417) at ../util/qemu-thread-posix.c:174 > > #2 0x55747d20ae36 in qemu_wait_io_event > (cpu=cpu@entry=0x55747f990ba0) at ../softmmu/cpus.c:417 > > #3 0x55747d18d6a1 in mttcg_cpu_thread_fn > (arg=arg@entry=0x55747f990ba0) at ../accel/tcg/tcg-accel-ops- > mttcg.c:98 > > #4 0x55747d419406 in qemu_thread_start (args=) > at > ../util/qemu-thread-posix.c:521 > > #5 0x7f477c598ea5 in start_thread () at /lib64/libpthread.so.0 > > #6 0x7f477c2c19fd in clone () at /lib64/libc.so.6 > > > > Thread 2 (Thread 0x7f461e1fc700 (LWP 24974)): > > #0 0x7f477c59ca35 in pthread_cond_wait@@GLIBC_2.3.2 () at > /lib64/libpthread.so.0 > > ---Type to continue, or q to quit--- > > #1 0x55747d419b1d in qemu_cond_wait_impl (cond=0x55747fa626c0, > mutex=0x55747e04dc00 , file=0x55747d5dbe5c > "../softmmu/cpus.c", line=417) at ../util/qemu-thread-posix.c:174 > > #2 0x55747d20ae36 in qemu_wait_io_event > (cpu=cpu@entry=0x55747f9fcf00) at ../softmmu/cpus.c:417 > > #3 0x55747d18d6a1 in mttcg_cpu_thread_fn > (arg=arg@entry=0x55747f9fcf00) at ../accel/tcg/tcg-accel-ops- > mttcg.c:98 > > #4 0x55747d419406 in qemu_thread_start (args=) > at > ../util/qemu-thread-posix.c:521 > > #5 0x7f477c598ea5 in start_thread () at /lib64/libpthread.so.0 > > #6 0x7f477c2c19fd in clone () at /lib64/libc.so.6 > > > > Thread 1 (Thread 0x7f4781db4d00 (LWP 24957)): > > #0 0x7f477c2b6d8f in ppoll () at /lib64/libc.so.6 > > #1 0x55747d431439 in qemu_poll_ns (__ss=0x0, > __timeout=0x7ffcc3188330, __nfds=, __fds= out>) > at /usr/include/bits/poll2.h:77 > > #2 0x55747d431439 in qemu_poll_ns (fds=, > nfds=, timeout=timeout@entry=3792947) at > ../util/qemu-timer.c:348 > > #3 0x55747d4466ce in main_loop_wait (timeout=) > at > ../util/main-loop.c:249 > > #4 0x55747d4466ce in main_loop_wait > (nonblocking=nonblocking@entry=0) at ../util/main-loop.c:530 > > #5 0x55747d2695c7 in qemu_main_loop () at > ../softmmu/runstate.c:725 > > #6 0x55747ccc1bde in main (argc=, > argv= out>, envp=) at ../softmmu/main.c:50 > > (gdb) > > > I run QEMU with virt-manager as this: > > qemu 7311 1 70 19:15 ?00:00:05 > /usr/local/bin/qemu-system-aarch64 -name > guest=EulerOS-2.8-Rich,debug-threads=on -S -object > secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-95- > EulerOS-2.8-Rich/master-key.aes > -machine virt-6.1,accel=tcg,usb=off,dump-guest-core=off,gic- > version=3 > -cpu max -drive > file=/usr/share/AAVMF/AAVMF_CODE.fd,if=pflash,format=raw,unit=0,reado > nly=on > -drive > file=/var/lib/libvirt/qemu/nvram/EulerOS-2.8- > Rich_VARS.fd,if=pflash,format=raw,unit=1 > -m 4096 -smp 4,sockets=4,cores=1,threads=1 -uuid > c95e0e92-011b-449a-8e3f-b5f09387 -display none -no-user-config > -nodefaults -chardev socket,id=charmonitor,fd=26,server,nowait -mon > chardev=charmonitor,id=monitor,mode=control -rtc base=utc -no- > shutdown > -boot strict=on -device > pcie-root- > port,port=0x8,chassis=1,id=pci.1,bus=pcie.0,multifunction=on,addr=0x1 > > -device > pcie-root-port,port=0x9,chassis=2,id=pci.2,bus=pcie.0,addr=0x1.0x1 > -device > pcie-root-port,port=0xa,chassis=3,id=pci.3,bus=pcie.0,addr=0x1.0x2 > -device > pcie-root-port,port=0xb,chassis=4,id=pci.4,bus=pcie.0,addr=0x1.0x3 > -device qemu-xhci,p2=8,p3=8,id=usb,bus=pci.2,addr=0x0 -device > virtio-scsi-pci,id=scsi0,bus=pci.3,addr=0x0 -drive > file=/var/lib/libvirt/images/EulerOS-2.8- > Rich.qcow2,format=qcow2,if=none,id=drive-scsi0-0-0-0 > -device > scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0- > 0,id=scsi0-0-0-0,bootindex=1 > -drive if=none,id=drive-scsi0-0-0-1,readonly=on -device > scsi-cd,bus=scsi0.0,channel=0,scsi-id=0,lun=1,drive=drive-scsi0-0-0- > 1,id=scsi0-0-0-1 > -netdev tap,fd=28,id=hostnet0 -device > virtio-net- > pci,netdev=hostnet0,id=net0,mac=52:54:00:f9:e0:69,bus=pci.1,addr=0x0 > -chardev pty,id=charserial0 -serial chardev:charserial0 -msg > timestamp=on > > The issue is reproducible and persists. > 1. Do you think that applying the series results in the dead lock in > MTTCG? Or it may be other reason? > 2. Which piece of QEMU source code should I investigate to locate the > issue? > >
Re: [PATCH v4 6/8] hw/intc: GICv3 redistributor ITS processing
Hi Eric,
Have accepted all comments with responses inline (below):-
On Sun, 2021-06-13 at 18:26 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Implemented lpi processing at redistributor to get lpi config info
> s/Implemented/Implement here are elsewhere.
> > from lpi configuration table,determine priority,set pending state
> > in
> > lpi pending table and forward the lpi to cpuif.Added logic to
> > invoke
> > redistributor lpi processing with translated LPI which set/clear
> > LPI
> > from ITS device as part of ITS INT,CLEAR,DISCARD command and
> > GITS_TRANSLATER processing.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3.c| 9 ++
> > hw/intc/arm_gicv3_common.c | 1 +
> > hw/intc/arm_gicv3_cpuif.c | 7 +-
> > hw/intc/arm_gicv3_its.c| 14 ++-
> > hw/intc/arm_gicv3_redist.c | 145
> > +
> > hw/intc/gicv3_internal.h | 10 ++
> > include/hw/intc/arm_gicv3_common.h | 10 ++
> > 7 files changed, 190 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
> > index d63f8af604..4d19190b9c 100644
> > --- a/hw/intc/arm_gicv3.c
> > +++ b/hw/intc/arm_gicv3.c
> > @@ -165,6 +165,15 @@ static void
> > gicv3_redist_update_noirqset(GICv3CPUState *cs)
> > cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
> > }
> >
> > +if (cs->gic->lpi_enable && cs->lpivalid) {
> > +if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
> > +cs->hppi.irq = cs->hpplpi.irq;
> > +cs->hppi.prio = cs->hpplpi.prio;
> > +cs->hppi.grp = cs->hpplpi.grp;
> > +seenbetter = true;
> > +}
> > +}
> > +
> > /* If the best interrupt we just found would preempt whatever
> > * was the previous best interrupt before this update, then
> > * we know it's definitely the best one now.
> > diff --git a/hw/intc/arm_gicv3_common.c
> > b/hw/intc/arm_gicv3_common.c
> > index 53dea2a775..223db16fec 100644
> > --- a/hw/intc/arm_gicv3_common.c
> > +++ b/hw/intc/arm_gicv3_common.c
> > @@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState
> > *dev)
> > memset(cs->gicr_ipriorityr, 0, sizeof(cs-
> > >gicr_ipriorityr));
> >
> > cs->hppi.prio = 0xff;
> > +cs->hpplpi.prio = 0xff;
> >
> > /* State in the CPU interface must *not* be reset here,
> > because it
> > * is part of the CPU's reset domain, not the GIC
> > device's.
> > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> > index 81f94c7f4a..5be3efaa3f 100644
> > --- a/hw/intc/arm_gicv3_cpuif.c
> > +++ b/hw/intc/arm_gicv3_cpuif.c
> > @@ -898,10 +898,12 @@ static void icc_activate_irq(GICv3CPUState
> > *cs, int irq)
> > cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1,
> > 1);
> > cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
> > gicv3_redist_update(cs);
> > -} else {
> > +} else if (irq < GICV3_LPI_INTID_START) {
> > gicv3_gicd_active_set(cs->gic, irq);
> > gicv3_gicd_pending_clear(cs->gic, irq);
> > gicv3_update(cs->gic, irq, 1);
> > +} else {
> > +gicv3_redist_lpi_pending(cs, irq, 0);
> > }
> > }
> >
> > @@ -1317,7 +1319,8 @@ static void icc_eoir_write(CPUARMState *env,
> > const ARMCPRegInfo *ri,
> > trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
> > gicv3_redist_affid(cs), value);
> >
> > -if (irq >= cs->gic->num_irq) {
> > +if ((irq >= cs->gic->num_irq) && (!(cs->gic->lpi_enable &&
> > +(irq >= GICV3_LPI_INTID_START {
> > /* This handles two cases:
> > * 1. If software writes the ID of a spurious interrupt
> > [ie 1020-1023]
> > * to the GICC_EOIR, the GIC ignores that write.
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index 0a978cf55b..e0fbd4041f 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -211,6 +211,7 @@ static MemTxResult process_int(GICv3ITSState
> > *s, uint64_t value,
> > bool ite_valid = fa
Re: [PATCH v4 3/8] hw/intc: GICv3 ITS command queue framework
Hi Eric,
Please find my responses inline (below):-
On Sun, 2021-06-13 at 16:13 +0200, Eric Auger wrote:
> Hi Sashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added functionality to trigger ITS command queue processing on
> > write to CWRITE register and process each command queue entry to
> > identify the command type and handle commands like MAPD,MAPC,SYNC.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3_its.c | 295
> > +++
> > hw/intc/gicv3_internal.h | 37 +
> > 2 files changed, 332 insertions(+)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index af60f19c98..6551c577b3 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -49,6 +49,295 @@ static uint64_t baser_base_addr(uint64_t value,
> > uint32_t page_sz)
> > return result;
> > }
> >
> > +static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid,
> > bool valid,
> > + uint64_t rdbase)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint64_t value;
> > +uint64_t l2t_addr;
> > +bool valid_l2t;
> > +uint32_t l2t_id;
> > +uint32_t max_l2_entries;
> > +uint64_t cte = 0;
> > +MemTxResult res = MEMTX_OK;
> > +
> > +if (!s->ct.valid) {
> Isn't it a guest log error case. Also you return MEMTX_OK in that
> case.
> Is that what you want?
Yes,because the current implementation treats all command specific
errors as "ignored" and moves onto next command in the queue.MEMTX
return values are significant for dma read/write status and in case of
error we stall the command processing
> > +return res;
> > +}
> > +
> > +if (valid) {
> > +/* add mapping entry to collection table */
> > +cte = (valid & VALID_MASK) |
> > + ((rdbase & RDBASE_PROCNUM_MASK) << 1ULL);
> Do you really need to sanitize rdbase again?
Not required,have rectified it.
> > +}
> > +
> > +/*
> > + * The specification defines the format of level 1 entries of
> > a
> > + * 2-level table, but the format of level 2 entries and the
> > format
> > + * of flat-mapped tables is IMPDEF.
> > + */
> > +if (s->ct.indirect) {
> > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > +value = address_space_ldq_le(as,
> > + s->ct.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED,
> > &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +
> > +valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > +
> > +if (valid_l2t) {
> > +max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > +
> > +l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > +address_space_stq_le(as, l2t_addr +
> > + ((icid % max_l2_entries) *
> > GITS_CTE_SIZE),
> > + cte, MEMTXATTRS_UNSPECIFIED,
> > &res);
> > +}
> > +} else {
> > +/* Flat level table */
> > +address_space_stq_le(as, s->ct.base_addr + (icid *
> > GITS_CTE_SIZE),
> > + cte, MEMTXATTRS_UNSPECIFIED, &res);
> > +}
> > +return res;
> > +}
> > +
> > +static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint16_t icid;
> > +uint64_t rdbase;
> > +bool valid;
> > +MemTxResult res = MEMTX_OK;
> > +uint64_t value;
> > +
> > +offset += NUM_BYTES_IN_DW;
> > +offset += NUM_BYTES_IN_DW;
> May be relevant to add some trace points for debuggability.
Probably the trace functionality for ITS can be taken up as a seperate
task/feature TODO.
> > +
> > +value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > +if (res != MEMTX_OK) {
> > +return res;
> > +}
> > +
> > +icid = value & ICID_MASK;
> > +
> > +rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBA
Re: [PATCH v4 4/8] hw/intc: GICv3 ITS Command processing
Hi Eric,
Please find my responses inline (below):-
On Sun, 2021-06-13 at 17:55 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GITS_TRANSLATER register,defined enum to differentiate between
> > ITS
> > command interrupt trigger and GITS_TRANSLATER based interrupt
> > trigger.
> > Each of these commands make use of other functionalities
> > implemented to
> > get device table entry,collection table entry or interrupt
> > translation
> > table entry required for their processing.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3_its.c| 334
> > +
> > hw/intc/gicv3_internal.h | 12 ++
> > include/hw/intc/arm_gicv3_common.h | 2 +
> > 3 files changed, 348 insertions(+)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index 6551c577b3..82bb5b84ef 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -28,6 +28,13 @@ struct GICv3ITSClass {
> > void (*parent_reset)(DeviceState *dev);
> > };
> >
> > +typedef enum ItsCmdType {
> > +NONE = 0, /* internal indication for GITS_TRANSLATER write */
> > +CLEAR = 1,
> > +DISCARD = 2,
> > +INT = 3,
> > +} ItsCmdType;
> Add a comment to explain what this enum stand for. This sounds
> misleading to me versus the command IDs. Why don't you use the cmd id
> then and add NONE?
This is an internal enum used to distinguish between interrupt
triggered via command queue and interrupt triggered via gits_translater
write.Will add the same comment in code.
Since NONE is only 1 command applicable for GITS_TRANSLATER,started
with it so that in the future if any further command queue commands
have to be added we can just extend the numbering.
> > +
> > static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> > {
> > uint64_t result = 0;
> > @@ -49,6 +56,315 @@ static uint64_t baser_base_addr(uint64_t value,
> > uint32_t page_sz)
> > return result;
> > }
> >
> > +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t
> > *cte,
> > +MemTxResult *res)
> > +{
> > +AddressSpace *as = &s->gicv3->dma_as;
> > +uint64_t l2t_addr;
> > +uint64_t value;
> > +bool valid_l2t;
> > +uint32_t l2t_id;
> > +uint32_t max_l2_entries;
> > +bool status = false;
> > +
> > +if (s->ct.indirect) {
> > +l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > +value = address_space_ldq_le(as,
> > + s->ct.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > +if (*res == MEMTX_OK) {
> > +valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > +
> > +if (valid_l2t) {
> > +max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > +
> > +l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > +*cte = address_space_ldq_le(as, l2t_addr +
> > +((icid % max_l2_entries) *
> > GITS_CTE_SIZE),
> > +MEMTXATTRS_UNSPECIFIED, res);
> > + }
> > + }
> > +} else {
> > +/* Flat level table */
> > +*cte = address_space_ldq_le(as, s->ct.base_addr +
> > + (icid * GITS_CTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED,
> > res);
> > +}
> > +
> > +if (*cte & VALID_MASK) {
> > +status = true;
> > +}
> > +
> > +return status;
> > +}
> > +
> > +static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid,
> > uint64_t dte,
> > + uint64_t itel, uint32_t iteh)
> why not introducing an ite struct instead of the h/l args?based on
> the same reason for packing individual fields within bit positions
> instead of using more memory to store the same fields as struct
> members.
Will create an ite struct with existing itel & iteh as members and
retain their bit fields processing to avoid extra params bein
Re: [PATCH v4 2/8] hw/intc: GICv3 ITS register definitions added
Hi Eric,
Please find my responses inline (below):-
On Sat, 2021-06-12 at 08:08 +0200, Eric Auger wrote:
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Defined descriptors for ITS device table,collection table and ITS
> > command queue entities.Implemented register read/write functions,
> > extract ITS table parameters and command queue parameters,extended
> > gicv3 common to capture qemu address space(which host the ITS table
> > platform memories required for subsequent ITS processing) and
> > initialize the same in ITS device.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3_its.c| 335
> > +
> > hw/intc/gicv3_internal.h | 28 ++-
> > include/hw/intc/arm_gicv3_common.h | 3 +
> > include/hw/intc/arm_gicv3_its_common.h | 30 +++
> > 4 files changed, 395 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index 545cda3665..af60f19c98 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -28,6 +28,157 @@ struct GICv3ITSClass {
> > void (*parent_reset)(DeviceState *dev);
> > };
> >
> > +static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
> > +{
> > +uint64_t result = 0;
> > +
> > +switch (page_sz) {
> > +case GITS_ITT_PAGE_SIZE_0:
> > +case GITS_ITT_PAGE_SIZE_1:
> > +result = value & R_GITS_BASER_PHYADDR_MASK;
> Use FIELD_EX64 as well for homogeneity?
Done
> > +break;
> > +
> > +case GITS_ITT_PAGE_SIZE_2:
> > +result = value & R_GITS_BASER_PHYADDRL_64K_MASK;
> here as well?
Done
> > +result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) <<
> > 48;
> > +break;
> > +
> > +default:
> > +break;
> > +}
> > +return result;
> > +}
> > +
> > +static void extract_table_params(GICv3ITSState *s)
> > +{
> > +uint16_t num_pages = 0;
> > +uint8_t page_sz_type;
> > +uint8_t type;
> > +uint32_t page_sz = 0;
> > +uint64_t value;
> > +
> > +for (int i = 0; i < 8; i++) {
> > +value = s->baser[i];
> > +
> > +if (!value) {
> > +continue;
> > +}
> > +
> > +page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
> > +
> > +switch (page_sz_type) {
> > +case 0:
> > +page_sz = GITS_ITT_PAGE_SIZE_0;
> > +break;
> > +
> > +case 1:
> > +page_sz = GITS_ITT_PAGE_SIZE_1;
> > +break;
> > +
> > +case 2:
> > +case 3:
> > +page_sz = GITS_ITT_PAGE_SIZE_2;
> > +break;
> > +
> > +default:
> > +g_assert_not_reached();
> > +}
> > +
> > +num_pages = FIELD_EX64(value, GITS_BASER, SIZE);
> + 1 directly? and remove num_pages + 1 below.
Done
> > +
> > +type = FIELD_EX64(value, GITS_BASER, TYPE);
> > +
> > +switch (type) {
> > +
> > +case GITS_ITT_TYPE_DEVICE:
> > +memset(&s->dt, 0 , sizeof(s->dt));
> > +s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
> > +
> > +if (!s->dt.valid) {
> > +return;
> > +}
> > +
> > +s->dt.page_sz = page_sz;
> > +s->dt.indirect = FIELD_EX64(value, GITS_BASER,
> > INDIRECT);
> > +s->dt.entry_sz = FIELD_EX64(value, GITS_BASER,
> > ENTRYSIZE);
> > +
> > +if (!s->dt.indirect) {
> > +s->dt.max_entries = ((num_pages + 1) * page_sz) /
> > + s->dt.entry_sz;
> > +} else {
> > +s->dt.max_entries = num_pages + 1) * page_sz)
> > /
> > + L1TABLE_ENTRY_SIZE) *
> > + (page_sz / s->dt.entry_sz));
> > +}
> > +
> > +s->dt.max_devids = (1UL << (FIELD_EX64(s->typer,
> > GITS_TYPER,
> > +DEVBITS) + 1));
> > +
> > +s->dt.base_addr = baser_base_addr(value, page_sz);
> > +
> > +break;
> > +
> > +case GITS_ITT_TYPE_COLLECTION:
> > +memset(&s->ct, 0 , sizeof(s->ct));
Re: [PATCH v4 6/8] hw/intc: GICv3 redistributor ITS processing
On Jun 11 2021, at 4:30 am, Peter Maydell wrote: > On Fri, 11 Jun 2021 at 00:39, Shashi Mallela > wrote: > > > > Have addressed all comments except the ones with responses(inline) below:- > > > > On Jun 8 2021, at 9:57 am, Peter Maydell wrote: > > > > > + cs->lpivalid = false; > > > + cs->hpplpi.prio = 0xff; > > > + gicv3_redist_update_lpi(cs); > > > > You can avoid doing a full update a lot of the time: > > * if this LPI is worse than the current value in hpplpi > > (where by "worse" I mean lower-priority by the same kind of > > comparison irqbetter() does) then we haven't changed the best-available > > pending LPI, so we don't need to do an update > > * if we set the pending bit to 1 and the LPI is enabled and the priority > > of this LPI is better than the current hpplpi, then we know this LPI > > is now the best, so we can just set hpplpi.prio and .irq without > > doing a full rescan > > * if we didn't actually change the value of the pending bit, we > > don't need to do an update (you get this for free if you take the > > simplification suggestion I make above, which does an early-return > > in the "no change" case) > > > > > Accepted the code simplification,but by not calling > > > gicv3_redist_update_lpi(cs) here ,the scenario of an activated LPI fails > > > because > > this LPI's priority (which could be lower than current hpplpi) is never > > checked/updated and gicv3_redist_update_noirqset() fails to present a valid > > active high priority LPI(if applicable) to the cpu,since it is always > > checking against a stale hpplpi info. > > If the LPI is lower priority (higher number) than the current > hpplpi then it would not change the existing hpplpi info in > a full-scan. If the LPI being activated is higher priority > (lower number) than the current hpplpi then that is my point 2 above, > and we set it as the hpplpi without needing the full-scan. And for > the other cases (eg highest-priority LPI being deactivated) we > should fall through to the default "call update_lpi" case. > > So I don't really understand why this wouldn't work. > -- PMM Have got this working as per comments.Please ignore my last comment.
Re: [PATCH v4 1/8] hw/intc: GICv3 ITS initial framework
On Jun 11 2021, at 12:21 pm, Eric Auger wrote:
> Hi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS common to handle mmio init between
> > existing kvm device and newer qemu device.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3_its.c | 240 +
> > hw/intc/arm_gicv3_its_common.c | 8 +-
> > hw/intc/arm_gicv3_its_kvm.c | 2 +-
> > hw/intc/gicv3_internal.h | 88 +++--
> > hw/intc/meson.build | 1 +
> > include/hw/intc/arm_gicv3_its_common.h | 9 +-
> > 6 files changed, 331 insertions(+), 17 deletions(-)
> > create mode 100644 hw/intc/arm_gicv3_its.c
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > new file mode 100644
> > index 00..545cda3665
> > --- /dev/null
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -0,0 +1,240 @@
> > +/*
> > + * ITS emulation for a GICv3-based system
> > + *
> > + * Copyright Linaro.org 2021
> > + *
> > + * Authors:
> > + * Shashi Mallela
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2 or (at
> > your
> > + * option) any later version. See the COPYING file in the top-level
> > directory.
> > + *
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/intc/arm_gicv3_its_common.h"
> > +#include "gicv3_internal.h"
> > +#include "qom/object.h"
> > +
> > +typedef struct GICv3ITSClass GICv3ITSClass;
> > +/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
> > +DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
> > + ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
> > +
> > +struct GICv3ITSClass {
> > + GICv3ITSCommonClass parent_class;
> > + void (*parent_reset)(DeviceState *dev);
> > +};
> > +
> > +static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
> > + uint64_t data, unsigned size,
> > + MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_readl(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
> > + uint64_t value, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult its_readll(GICv3ITSState *s, hwaddr offset,
> > + uint64_t *data, MemTxAttrs attrs)
> > +{
> > + MemTxResult result = MEMTX_OK;
> > +
> > + return result;
> > +}
> > +
> > +static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t
> > *data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
> > + GICv3ITSState *s = (GICv3ITSState *)opaque;
> > + MemTxResult result;
> > +
> > + switch (size) {
> > + case 4:
> > + result = its_readl(s, offset, data, attrs);
> > + break;
> > + case 8:
> > + result = its_readll(s, offset, data, attrs);
> > + break;
> > + default:
> > + result = MEMTX_ERROR;
> > + break;
> > + }
> > +
> > + if (result == MEMTX_ERROR) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: invalid guest read at offset " TARGET_FMT_plx
> > + "size %u\n", __func__, offset, size);
> > + /*
> > + * The spec requires that reserved registers are RAZ/WI;
> > + * so use MEMTX_ERROR returns from leaf functions as a way to
> > + * trigger the guest-error logging but don't return it to
> > + * the caller, or we'll cause a spurious guest data abort.
> > + */
> > + result = MEMTX_OK;
> > + *data = 0;
> > + }
> > + return result;
> > +}
> > +
> > +static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t
> > data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
> > + GICv3ITSState *s = (GICv3ITSState *)opaque;
> > +
Re: [PATCH v4 6/8] hw/intc: GICv3 redistributor ITS processing
Have addressed all comments except the ones with responses(inline) below:-
On Jun 8 2021, at 9:57 am, Peter Maydell wrote:
> On Wed, 2 Jun 2021 at 19:00, Shashi Mallela wrote:
> >
> > Implemented lpi processing at redistributor to get lpi config info
> > from lpi configuration table,determine priority,set pending state in
> > lpi pending table and forward the lpi to cpuif.Added logic to invoke
> > redistributor lpi processing with translated LPI which set/clear LPI
> > from ITS device as part of ITS INT,CLEAR,DISCARD command and
> > GITS_TRANSLATER processing.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/intc/arm_gicv3.c | 9 ++
> > hw/intc/arm_gicv3_common.c | 1 +
> > hw/intc/arm_gicv3_cpuif.c | 7 +-
> > hw/intc/arm_gicv3_its.c | 14 ++-
> > hw/intc/arm_gicv3_redist.c | 145 +
> > hw/intc/gicv3_internal.h | 10 ++
> > include/hw/intc/arm_gicv3_common.h | 10 ++
> > 7 files changed, 190 insertions(+), 6 deletions(-)
>
> The code for finding/updating the best pending LPI looks a lot
> better in this version -- thanks for working through that.
>
> An important thing which I hadn't realized previously:
> the hpplpi information counts as information cached from the
> LPI configuration tables (because it is based on the priority
> and enable-bit information from those tables). That means that when
> the guest sends the ITS INV or INVALL command we need to throw it
> away and recalculate by calling gicv3_redist_update_lpi().
> (The idea here is that the guest can validly raise the priority
> of an interrupt by the sequence "write to table; INVALL; SYNC",
> and we need to correctly figure out that that might mean that
> that LPI is now the interrupt we should be taking.)
>
> Agreed,will be implementing the INV/INVALL command processing in addition to
> existing ITS commands
> diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
> index d63f8af604..4d19190b9c 100644
> --- a/hw/intc/arm_gicv3.c
> +++ b/hw/intc/arm_gicv3.c
> @@ -165,6 +165,15 @@ static void gicv3_redist_update_noirqset(GICv3CPUState
> *cs)
> cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
> }
>
> + if (cs->gic->lpi_enable && cs->lpivalid) {
You don't need a separate lpivalid flag -- you can use
hpplpi.prio == 0xff as your "no pending LPI" indication.
This is how the existing cs->hppi works.
(irqbetter() will always return false if passed an 0xff priority,
so you don't need to special case check anything here.)
> + if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
> + cs->hppi.irq = cs->hpplpi.irq;
> + cs->hppi.prio = cs->hpplpi.prio;
> + cs->hppi.grp = cs->hpplpi.grp;
> + seenbetter = true;
> + }
> + }
> +
> /* If the best interrupt we just found would preempt whatever
> * was the previous best interrupt before this update, then
> * we know it's definitely the best one now.
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index 53dea2a775..223db16fec 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
> memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
>
> cs->hppi.prio = 0xff;
> + cs->hpplpi.prio = 0xff;
>
> /* State in the CPU interface must *not* be reset here, because it
> * is part of the CPU's reset domain, not the GIC device's.
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index 81f94c7f4a..5be3efaa3f 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -898,10 +898,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
> cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
> cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
> gicv3_redist_update(cs);
> - } else {
> + } else if (irq < GICV3_LPI_INTID_START) {
> gicv3_gicd_active_set(cs->gic, irq);
> gicv3_gicd_pending_clear(cs->gic, irq);
> gicv3_update(cs->gic, irq, 1);
> + } else {
> + gicv3_redist_lpi_pending(cs, irq, 0);
> }
> }
>
> @@ -1317,7 +1319,8 @@ static void icc_eoir_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
> gicv3_redist_affid(cs), value);
>
> - if (irq >= cs->gic->num_irq) {
> + if ((irq >= cs->gic->num_irq) && (!(cs->gic->lpi_enable &&
> + (irq >= GICV3_LPI_INTID_START {
Please put the line break after the first &&, not the second. That means
that you avoid linebreaking in the middle of a () expression.
Also you don't nee
Re: [PATCH v4 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC
On Fri, 2021-06-04 at 11:42 +0100, Leif Lindholm wrote:
> On Thu, Jun 03, 2021 at 11:31:21 -0400, shashi.mall...@linaro.org
> wrote:
> > On Thu, 2021-06-03 at 12:42 +0100, Leif Lindholm wrote:
> > > On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> > > > Included creation of ITS as part of SBSA platform GIC
> > > > initialization.
> > > >
> > > > Signed-off-by: Shashi Mallela
> > > > ---
> > > > hw/arm/sbsa-ref.c | 26 +++---
> > > > 1 file changed, 23 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> > > > index 43c19b4923..3d9c073636 100644
> > > > --- a/hw/arm/sbsa-ref.c
> > > > +++ b/hw/arm/sbsa-ref.c
> > > > @@ -34,7 +34,7 @@
> > > > #include "hw/boards.h"
> > > > #include "hw/ide/internal.h"
> > > > #include "hw/ide/ahci_internal.h"
> > > > -#include "hw/intc/arm_gicv3_common.h"
> > > > +#include "hw/intc/arm_gicv3_its_common.h"
> > > > #include "hw/loader.h"
> > > > #include "hw/pci-host/gpex.h"
> > > > #include "hw/qdev-properties.h"
> > > > @@ -64,6 +64,7 @@ enum {
> > > > SBSA_CPUPERIPHS,
> > > > SBSA_GIC_DIST,
> > > > SBSA_GIC_REDIST,
> > > > +SBSA_GIC_ITS,
> > > > SBSA_SECURE_EC,
> > > > SBSA_GWDT,
> > > > SBSA_GWDT_REFRESH,
> > > > @@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[]
> > > > = {
> > > > [SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
> > > > [SBSA_GIC_DIST] = { 0x4006, 0x0001 },
> > > > [SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
> > >
> > > It seems customary in QEMU to flag gaps in memory space (although
> > > admittedly, we'd already failed to do so here). This patch leaves
> > > a
> > > gap of 0x0001. Is there a particular reason?
> > >
> > > > +[SBSA_GIC_ITS] ={ 0x4409, 0x0002 },
> > >
> > > And then again a gap (the one we already had).
> > >
> > > No specific reason,but from ITS point of view tried to stay
> > > within
> > > the GIC's 0x4006 to 0x5000 zone.The gap of 0x0001
> > > would
> > > also account for future GIC additions like virtual LPI support.
>
> Right. I was more thinking 64kB isn't much space to extend into.
> Would it be worth pushing the ITS either all the way up to just below
> 0x5000, 0x4800, or 0x4500?
>
> The current memory allocation size (of 67MB) for
redistributor(SBSA_GIC_REDIST) is already very large relative to its
overall required register address space.Hence ITS started at 0x4409
(considering that redistributor space is sufficiently spaced) until
0x440B.Future virtual LPI addition can still stay within the
0x4500 mark,leaving the whole area between 0x4500 to 0x5000
free for other devices.
are comments still recommended here?
>
> Either way, the gap(s) would be good to point out with comments, and
> potential future use. I only noticed this one on like the third pass
> of reading.
>
> /
> Leif
>
> > > > [SBSA_SECURE_EC] = { 0x5000, 0x1000 },
> > > > [SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
> > > > [SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
> > > > @@ -377,7 +379,20 @@ static void
> > > > create_secure_ram(SBSAMachineState
> > > > *sms,
> > > > memory_region_add_subregion(secure_sysmem, base, secram);
> > > > }
> > > >
> > > > -static void create_gic(SBSAMachineState *sms)
> > > > +static void create_its(SBSAMachineState *sms)
> > > > +{
> > > > +DeviceState *dev;
> > > > +
> > > > +dev = qdev_new(TYPE_ARM_GICV3_ITS);
> > > > +SysBusDevice *s = SYS_BUS_DEVICE(dev);
> > > > +
> > > > +object_property_set_link(OBJECT(dev), "parent-gicv3",
> > > > OBJECT(sms->gic),
> > > > + &error_abort);
> > > > +sysbus_realize_and_unref(s, &error_fatal);
> > > > +sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
> > > > +}
> > > > +
> > &
Re: [PATCH v4 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC
On Thu, 2021-06-03 at 12:42 +0100, Leif Lindholm wrote:
> On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> > Included creation of ITS as part of SBSA platform GIC
> > initialization.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/arm/sbsa-ref.c | 26 +++---
> > 1 file changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> > index 43c19b4923..3d9c073636 100644
> > --- a/hw/arm/sbsa-ref.c
> > +++ b/hw/arm/sbsa-ref.c
> > @@ -34,7 +34,7 @@
> > #include "hw/boards.h"
> > #include "hw/ide/internal.h"
> > #include "hw/ide/ahci_internal.h"
> > -#include "hw/intc/arm_gicv3_common.h"
> > +#include "hw/intc/arm_gicv3_its_common.h"
> > #include "hw/loader.h"
> > #include "hw/pci-host/gpex.h"
> > #include "hw/qdev-properties.h"
> > @@ -64,6 +64,7 @@ enum {
> > SBSA_CPUPERIPHS,
> > SBSA_GIC_DIST,
> > SBSA_GIC_REDIST,
> > +SBSA_GIC_ITS,
> > SBSA_SECURE_EC,
> > SBSA_GWDT,
> > SBSA_GWDT_REFRESH,
> > @@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
> > [SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
> > [SBSA_GIC_DIST] = { 0x4006, 0x0001 },
> > [SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
>
> It seems customary in QEMU to flag gaps in memory space (although
> admittedly, we'd already failed to do so here). This patch leaves a
> gap of 0x0001. Is there a particular reason?
>
> > +[SBSA_GIC_ITS] ={ 0x4409, 0x0002 },
>
> And then again a gap (the one we already had).
>
> /
> Leif
>
> No specific reason,but from ITS point of view tried to stay within
> the GIC's 0x4006 to 0x5000 zone.The gap of 0x0001 would
> also account for future GIC additions like virtual LPI support.
>
>
> > [SBSA_SECURE_EC] = { 0x5000, 0x1000 },
> > [SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
> > [SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
> > @@ -377,7 +379,20 @@ static void create_secure_ram(SBSAMachineState
> > *sms,
> > memory_region_add_subregion(secure_sysmem, base, secram);
> > }
> >
> > -static void create_gic(SBSAMachineState *sms)
> > +static void create_its(SBSAMachineState *sms)
> > +{
> > +DeviceState *dev;
> > +
> > +dev = qdev_new(TYPE_ARM_GICV3_ITS);
> > +SysBusDevice *s = SYS_BUS_DEVICE(dev);
> > +
> > +object_property_set_link(OBJECT(dev), "parent-gicv3",
> > OBJECT(sms->gic),
> > + &error_abort);
> > +sysbus_realize_and_unref(s, &error_fatal);
> > +sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
> > +}
> > +
> > +static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
> > {
> > unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
> > SysBusDevice *gicbusdev;
> > @@ -404,6 +419,10 @@ static void create_gic(SBSAMachineState *sms)
> > qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
> > qdev_prop_set_uint32(sms->gic, "redist-region-count[0]",
> > redist0_count);
> >
> > +object_property_set_link(OBJECT(sms->gic), "sysmem",
> > OBJECT(mem),
> > + &error_fatal);
> > +qdev_prop_set_bit(sms->gic, "has-lpi", true);
> > +
> > gicbusdev = SYS_BUS_DEVICE(sms->gic);
> > sysbus_realize_and_unref(gicbusdev, &error_fatal);
> > sysbus_mmio_map(gicbusdev, 0,
> > sbsa_ref_memmap[SBSA_GIC_DIST].base);
> > @@ -450,6 +469,7 @@ static void create_gic(SBSAMachineState *sms)
> > sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
> > qdev_get_gpio_in(cpudev,
> > ARM_CPU_VFIQ));
> > }
> > +create_its(sms);
> > }
> >
> > static void create_uart(const SBSAMachineState *sms, int uart,
> > @@ -762,7 +782,7 @@ static void sbsa_ref_init(MachineState
> > *machine)
> >
> > create_secure_ram(sms, secure_sysmem);
> >
> > -create_gic(sms);
> > +create_gic(sms, sysmem);
> >
> > create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
> > create_uart(sms, SBSA_SECURE_UART, secure_sysmem,
> > serial_hd(1));
> > --
> > 2.27.0
> >
Re: [PATCH] hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
Yes it does.
Thanks
Shashi
On Jun 3 2021, at 8:56 am, Peter Maydell wrote:
> On Thu, 3 Jun 2021 at 12:01, Jean-Philippe Brucker
> wrote:
> >
> > Commit 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access
> > check logic") added an assert_not_reached() if the guest writes the EOIR
> > register while no interrupt is active.
> >
> > It turns out some software does this: EDK2, in GicV3ExitBootServicesEvent(),
> > unconditionally write EOIR for all interrupts that it manages. This now
> > causes QEMU to abort when running UEFI on a VM with GICv3. Although it
> > is UNPREDICTABLE behavior and EDK2 does need fixing, the punishment
> > seems a little harsh, especially since icc_eoir_write() already
> > tolerates writes of nonexistent interrupt numbers. Simply ignore
> > spurious EOIR writes.
> >
> > Fixes: 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check
> > logic")
> > Signed-off-by: Jean-Philippe Brucker
> > ---
> > hw/intc/arm_gicv3_cpuif.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> > index 81f94c7f4a..1d0964c9bf 100644
> > --- a/hw/intc/arm_gicv3_cpuif.c
> > +++ b/hw/intc/arm_gicv3_cpuif.c
> > @@ -1357,7 +1357,8 @@ static void icc_eoir_write(CPUARMState *env, const
> > ARMCPRegInfo *ri,
> > }
> > break;
> > default:
> > - g_assert_not_reached();
> > + /* No interrupt was active, this is UNPREDICTABLE. Ignore it. */
> > + return;
> >
>
> Makes sense (and looking at the comment in icc_highest_active_group()
> that says "return -1 so the caller ignores the spurious EOI attempt"
> it is what the code originally intended).
>
> Reviewed-by: Peter Maydell
> Shashi, I guess this also fixes the assert you were seeing here ?
> thanks
> -- PMM
>
[PATCH v1 1/1] tests/data/acpi/virt: add IORT files for ITS
Added expected IORT files applicable with latest GICv3 ITS changes. Signed-off-by: Shashi Mallela --- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 4 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb diff --git a/tests/data/acpi/virt/IORT b/tests/data/acpi/virt/IORT new file mode 100644 index ..521acefe9ba66706c5607321a82d330586f3f280 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.memhp b/tests/data/acpi/virt/IORT.memhp new file mode 100644 index ..521acefe9ba66706c5607321a82d330586f3f280 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.numamem b/tests/data/acpi/virt/IORT.numamem new file mode 100644 index ..521acefe9ba66706c5607321a82d330586f3f280 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 diff --git a/tests/data/acpi/virt/IORT.pxb b/tests/data/acpi/virt/IORT.pxb new file mode 100644 index ..521acefe9ba66706c5607321a82d330586f3f280 GIT binary patch literal 124 zcmebD4+^Pa00MR=e`k+i1*eDrX9XZ&1PX!JAesq?4S*O7Bw!2(4Uz`|CKCt^;wu0# QRGb+i3L*dhhtM#y0PN=p0RR91 literal 0 HcmV?d1 -- 2.27.0
[PATCH v4 8/8] hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization.This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
---
hw/arm/virt.c | 27 +--
include/hw/arm/virt.h | 2 ++
target/arm/kvm_arm.h | 4 ++--
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 840758666d..f598f048da 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -583,6 +583,12 @@ static void create_its(VirtMachineState *vms)
const char *itsclass = its_class_name();
DeviceState *dev;
+if (!strcmp(itsclass, "arm-gicv3-its")) {
+if (!vms->tcg_its) {
+itsclass = NULL;
+}
+}
+
if (!itsclass) {
/* Do nothing if not supported */
return;
@@ -620,7 +626,7 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
-static void create_gic(VirtMachineState *vms)
+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
@@ -654,6 +660,14 @@ static void create_gic(VirtMachineState *vms)
nb_redist_regions);
qdev_prop_set_uint32(vms->gic, "redist-region-count[0]",
redist0_count);
+if (!kvm_irqchip_in_kernel()) {
+if (vms->tcg_its) {
+object_property_set_link(OBJECT(vms->gic), "sysmem",
+ OBJECT(mem), &error_fatal);
+qdev_prop_set_bit(vms->gic, "has-lpi", true);
+}
+}
+
if (nb_redist_regions == 2) {
uint32_t redist1_capacity =
vms->memmap[VIRT_HIGH_GIC_REDIST2].size /
GICV3_REDIST_SIZE;
@@ -2039,7 +2053,7 @@ static void machvirt_init(MachineState *machine)
virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
-create_gic(vms);
+create_gic(vms, sysmem);
virt_cpu_post_init(vms, sysmem);
@@ -2718,6 +2732,12 @@ static void virt_instance_init(Object *obj)
} else {
/* Default allows ITS instantiation */
vms->its = true;
+
+if (vmc->no_tcg_its) {
+vms->tcg_its = false;
+} else {
+vms->tcg_its = true;
+}
}
/* Default disallows iommu instantiation */
@@ -2764,6 +2784,9 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
static void virt_machine_6_0_options(MachineClass *mc)
{
+VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+/* qemu ITS was introduced with 6.1 */
+vmc->no_tcg_its = true;
}
DEFINE_VIRT_MACHINE(6, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 921416f918..f873ab9068 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,6 +120,7 @@ struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
+bool no_tcg_its;
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
@@ -141,6 +142,7 @@ struct VirtMachineState {
bool highmem;
bool highmem_ecam;
bool its;
+bool tcg_its;
bool virt;
bool ras;
bool mte;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 34f8daa377..0613454975 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -525,8 +525,8 @@ static inline const char *its_class_name(void)
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
} else {
-/* Software emulation is not implemented yet */
-return NULL;
+/* Software emulation based model */
+return "arm-gicv3-its";
}
}
--
2.27.0
[PATCH v4 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,7 +34,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -64,6 +64,7 @@ enum {
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -107,6 +108,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_CPUPERIPHS] = { 0x4000, 0x0004 },
[SBSA_GIC_DIST] = { 0x4006, 0x0001 },
[SBSA_GIC_REDIST] = { 0x4008, 0x0400 },
+[SBSA_GIC_ITS] ={ 0x4409, 0x0002 },
[SBSA_SECURE_EC] = { 0x5000, 0x1000 },
[SBSA_GWDT_REFRESH] = { 0x5001, 0x1000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x1000 },
@@ -377,7 +379,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+DeviceState *dev;
+
+dev = qdev_new(TYPE_ARM_GICV3_ITS);
+SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+sysbus_realize_and_unref(s, &error_fatal);
+sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -404,6 +419,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -450,6 +469,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -762,7 +782,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
-create_gic(sms);
+create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
--
2.27.0
[PATCH v4 6/8] hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 9 ++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 14 ++-
hw/intc/arm_gicv3_redist.c | 145 +
hw/intc/gicv3_internal.h | 10 ++
include/hw/intc/arm_gicv3_common.h | 10 ++
7 files changed, 190 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index d63f8af604..4d19190b9c 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -165,6 +165,15 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
}
+if (cs->gic->lpi_enable && cs->lpivalid) {
+if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+cs->hppi.irq = cs->hpplpi.irq;
+cs->hppi.prio = cs->hpplpi.prio;
+cs->hppi.grp = cs->hpplpi.grp;
+seenbetter = true;
+}
+}
+
/* If the best interrupt we just found would preempt whatever
* was the previous best interrupt before this update, then
* we know it's definitely the best one now.
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 53dea2a775..223db16fec 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -435,6 +435,7 @@ static void arm_gicv3_common_reset(DeviceState *dev)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+cs->hpplpi.prio = 0xff;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 81f94c7f4a..5be3efaa3f 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -898,10 +898,12 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
gicv3_redist_update(cs);
-} else {
+} else if (irq < GICV3_LPI_INTID_START) {
gicv3_gicd_active_set(cs->gic, irq);
gicv3_gicd_pending_clear(cs->gic, irq);
gicv3_update(cs->gic, irq, 1);
+} else {
+gicv3_redist_lpi_pending(cs, irq, 0);
}
}
@@ -1317,7 +1319,8 @@ static void icc_eoir_write(CPUARMState *env, const
ARMCPRegInfo *ri,
trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1,
gicv3_redist_affid(cs), value);
-if (irq >= cs->gic->num_irq) {
+if ((irq >= cs->gic->num_irq) && (!(cs->gic->lpi_enable &&
+(irq >= GICV3_LPI_INTID_START {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
* to the GICC_EOIR, the GIC ignores that write.
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 0a978cf55b..e0fbd4041f 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -211,6 +211,7 @@ static MemTxResult process_int(GICv3ITSState *s, uint64_t
value,
bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
+uint64_t rdbase;
uint64_t itel = 0;
uint32_t iteh = 0;
@@ -267,10 +268,15 @@ static MemTxResult process_int(GICv3ITSState *s, uint64_t
value,
* command in the queue
*/
} else {
-/*
- * Current implementation only supports rdbase == procnum
- * Hence rdbase physical address is ignored
- */
+rdbase = (cte >> 1U) & RDBASE_PROCNUM_MASK;
+assert(rdbase <= s->gicv3->num_cpu);
+
+if ((cmd == CLEAR) || (cmd == DISCARD)) {
+gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0);
+} else {
+gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1);
+}
+
if (cmd == DISCARD) {
/* remove mapping from interrupt translation table */
res = update_ite(s, eventid, dte, itel, iteh);
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index fb9a4ee3cc..bfc6e4e9b9 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -255,6 +255,11 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
if (cs->gicr_typer & GI
[PATCH v4 5/8] hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c | 7 +--
hw/intc/arm_gicv3_its.c| 9 -
hw/intc/arm_gicv3_redist.c | 14 +++---
hw/intc/gicv3_internal.h | 17 +
include/hw/intc/arm_gicv3_common.h | 1 +
6 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 58ef65f589..53dea2a775 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+if (s->lpi_enable && !s->dma) {
+error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
+return;
+}
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
(1 << 24) |
(i << 8) |
(last << 4);
+
+if (s->lpi_enable) {
+s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
+}
}
}
@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
+DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
redist_region_count, qdev_prop_uint32, uint32_t),
+DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..7e57654061 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
* A3V == 1 (non-zero values of Affinity level 3 supported)
* IDbits == 0xf (we support 16-bit interrupt identifiers)
* DVIS == 0 (Direct virtual LPI injection not supported)
- * LPIS == 0 (LPIs not supported)
+ * LPIS == 1 (LPIs are supported if affinity routing is enabled)
+ * num_LPIs == 0b0 (bits [15:11],Number of LPIs as indicated
+ * by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
@@ -386,7 +388,8 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
-(0xf << 19) | itlinesnumber;
+(s->lpi_enable << GICD_TYPER_LPIS_OFFSET) |
+(GICD_TYPER_IDBITS << GICD_TYPER_IDBITS_OFFSET) | itlinesnumber;
return MEMTX_OK;
}
case GICD_IIDR:
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 82bb5b84ef..0a978cf55b 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -294,6 +294,7 @@ static MemTxResult process_mapti(GICv3ITSState *s, uint64_t
value,
uint64_t itel = 0;
uint32_t iteh = 0;
uint32_t int_spurious = INTID_SPURIOUS;
+uint64_t idbits;
devid = (value >> DEVID_SHIFT) & DEVID_MASK;
offset += NUM_BYTES_IN_DW;
@@ -330,7 +331,13 @@ static MemTxResult process_mapti(GICv3ITSState *s,
uint64_t value,
max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
if (!ignore_pInt) {
-max_Intid = (1UL << (FIELD_EX64(s->typer, GITS_TYPER, IDBITS) + 1));
+idbits = MIN(FIELD_EX64(s->gicv3->cpu->gicr_propbaser, GICR_PROPBASER,
+IDBITS), GICD_TYPER_IDBITS);
+
+if (idbits < GICR_PROPBASER_IDBITS_THRESHOLD) {
+return res;
+}
+max_Intid = (1ULL << (idbits + 1));
}
if ((devid > s->dt.max_devids) || (icid > s->ct.max_collids) ||
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8645220d61..fb9a4ee3cc 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -244,14 +244,21 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr
offset,
static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
[PATCH v4 4/8] hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 334 +
hw/intc/gicv3_internal.h | 12 ++
include/hw/intc/arm_gicv3_common.h | 2 +
3 files changed, 348 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 6551c577b3..82bb5b84ef 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,13 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+typedef enum ItsCmdType {
+NONE = 0, /* internal indication for GITS_TRANSLATER write */
+CLEAR = 1,
+DISCARD = 2,
+INT = 3,
+} ItsCmdType;
+
static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
{
uint64_t result = 0;
@@ -49,6 +56,315 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte,
+MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t l2t_addr;
+uint64_t value;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+bool status = false;
+
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+*cte = address_space_ldq_le(as, l2t_addr +
+((icid % max_l2_entries) * GITS_CTE_SIZE),
+MEMTXATTRS_UNSPECIFIED, res);
+ }
+ }
+} else {
+/* Flat level table */
+*cte = address_space_ldq_le(as, s->ct.base_addr +
+ (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, res);
+}
+
+if (*cte & VALID_MASK) {
+status = true;
+}
+
+return status;
+}
+
+static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+ uint64_t itel, uint32_t iteh)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+MemTxResult res = MEMTX_OK;
+
+itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+address_space_stq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+ itel, MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res == MEMTX_OK) {
+address_space_stl_le(as, itt_addr + ((eventid + sizeof(uint64_t)) *
+ sizeof(uint32_t)), iteh, MEMTXATTRS_UNSPECIFIED,
+ &res);
+}
+ return res;
+}
+
+static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
+uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t itt_addr;
+bool status = false;
+uint64_t itel = 0;
+uint32_t iteh = 0;
+
+itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
+itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
+
+itel = address_space_ldq_le(as, itt_addr + (eventid * sizeof(uint64_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+iteh = address_space_ldl_le(as, itt_addr + ((eventid +
+sizeof(uint64_t)) * sizeof(uint32_t)),
+MEMTXATTRS_UNSPECIFIED, res);
+
+if (*res == MEMTX_OK) {
+if (itel & VALID_MASK) {
+if ((itel >> ITE_ENTRY_INTTYPE_SHIFT) & GITS_TYPE_PHYSICAL) {
+*pIntid = (itel >> ITE_ENTRY_INTID_SHIFT) &
+ ITE_ENTRY_INTID_MASK;
+*icid = iteh & ITE_ENTRY_ICID_MASK;
+status = true;
+}
+}
+}
+}
+return status;
+}
+
+static uint64_t get_dte(GICv3ITSState *s, uint32_t devid, MemTxResult *res)
+{
+AddressSpace *as = &s->gicv3->d
[PATCH v4 3/8] hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c | 295 +++
hw/intc/gicv3_internal.h | 37 +
2 files changed, 332 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index af60f19c98..6551c577b3 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -49,6 +49,295 @@ static uint64_t baser_base_addr(uint64_t value, uint32_t
page_sz)
return result;
}
+static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
+ uint64_t rdbase)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t cte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (!s->ct.valid) {
+return res;
+}
+
+if (valid) {
+/* add mapping entry to collection table */
+cte = (valid & VALID_MASK) |
+ ((rdbase & RDBASE_PROCNUM_MASK) << 1ULL);
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->ct.indirect) {
+l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
+
+if (valid_l2t) {
+max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
+
+l2t_addr = value & ((1ULL << 51) - 1);
+
+address_space_stq_le(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+} else {
+/* Flat level table */
+address_space_stq_le(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ cte, MEMTXATTRS_UNSPECIFIED, &res);
+}
+return res;
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint16_t icid;
+uint64_t rdbase;
+bool valid;
+MemTxResult res = MEMTX_OK;
+uint64_t value;
+
+offset += NUM_BYTES_IN_DW;
+offset += NUM_BYTES_IN_DW;
+
+value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+if (res != MEMTX_OK) {
+return res;
+}
+
+icid = value & ICID_MASK;
+
+rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
+
+valid = (value >> VALID_SHIFT) & VALID_MASK;
+
+if ((icid > s->ct.max_collids) || (rdbase > s->gicv3->num_cpu)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS MAPC: invalid collection table attributes "
+ "icid %d rdbase %lu\n", icid, rdbase);
+/*
+ * in this implementation,in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+} else {
+res = update_cte(s, icid, valid, rdbase);
+}
+
+return res;
+}
+
+static MemTxResult update_dte(GICv3ITSState *s, uint32_t devid, bool valid,
+ uint8_t size, uint64_t itt_addr)
+{
+AddressSpace *as = &s->gicv3->dma_as;
+uint64_t value;
+uint64_t l2t_addr;
+bool valid_l2t;
+uint32_t l2t_id;
+uint32_t max_l2_entries;
+uint64_t dte = 0;
+MemTxResult res = MEMTX_OK;
+
+if (s->dt.valid) {
+if (valid) {
+/* add mapping entry to device table */
+dte = (valid & VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ ((itt_addr & ITTADDR_MASK) << 6ULL);
+}
+} else {
+return res;
+}
+
+/*
+ * The specification defines the format of level 1 entries of a
+ * 2-level table, but the format of level 2 entries and the format
+ * of flat-mapped tables is IMPDEF.
+ */
+if (s->dt.indirect) {
+l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
+
+value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &res);
+
