Re: [PATCH] RISC-V: Allow both Zmmul and M

[Alistair Francis]

On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt  wrote:
>
> We got to talking about how Zmmul and M interact with each other
> https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
> that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
> combination, it just means that the multiplication instructions are
> supported even when M is disabled at runtime via misa.
>
> This just stops overriding M from Zmmul, with that the other checks for
> the multiplication instructions work as per the ISA.
>
> Signed-off-by: Palmer Dabbelt 

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c | 5 -
>  1 file changed, 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2b8e4d30..cab74faaca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  cpu->cfg.ext_ifencei = true;
>  }
>
> -if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
> -warn_report("Zmmul will override M");
> -cpu->cfg.ext_m = false;
> -}
> -
>  if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
>  error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Allow both Zmmul and M

[Alistair Francis]

On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt  wrote:
>
> We got to talking about how Zmmul and M interact with each other
> https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
> that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
> combination, it just means that the multiplication instructions are
> supported even when M is disabled at runtime via misa.
>
> This just stops overriding M from Zmmul, with that the other checks for
> the multiplication instructions work as per the ISA.
>
> Signed-off-by: Palmer Dabbelt 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c | 5 -
>  1 file changed, 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2b8e4d30..cab74faaca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  cpu->cfg.ext_ifencei = true;
>  }
>
> -if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
> -warn_report("Zmmul will override M");
> -cpu->cfg.ext_m = false;
> -}
> -
>  if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
>  error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.34.1
>
>

[PATCH] RISC-V: Allow both Zmmul and M

[Palmer Dabbelt]

We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.

This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.

Signed-off-by: Palmer Dabbelt 
---
 target/riscv/cpu.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db2b8e4d30..cab74faaca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 cpu->cfg.ext_ifencei = true;
 }
 
-if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
-warn_report("Zmmul will override M");
-cpu->cfg.ext_m = false;
-}
-
 if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 error_setg(errp,
"I and E extensions are incompatible");
-- 
2.34.1