Re: [PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
On Fri, Aug 25, 2023 at 10:08:35AM -0300, Daniel Henrique Barboza wrote: > riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different > realize() path during the common riscv_cpu_realize(), making it a good > choice to start moving TCG exclusive code to tcg-cpu.c. > > Rename it to tcg_cpu_realizefn() and assign it as a implementation of > accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during > riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar > approach with KVM in the near future. > > riscv_cpu_validate_set_extensions() is too big and with too many > dependencies to be moved in this same patch. We'll do that next. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 128 --- > target/riscv/tcg/tcg-cpu.c | 132 + > 2 files changed, 132 insertions(+), 128 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 38dcbc4dd2..36c5c6e579 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -23,9 +23,7 @@ > #include "qemu/log.h" > #include "cpu.h" > #include "cpu_vendorid.h" > -#include "pmu.h" > #include "internals.h" > -#include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > #include "qapi/visitor.h" > @@ -1065,29 +1063,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, > RISCVCPUConfig *cfg, > } > } > > -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > -{ > -CPURISCVState *env = >env; > -int priv_version = -1; > - > -if (cpu->cfg.priv_spec) { > -if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > -priv_version = PRIV_VERSION_1_12_0; > -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > -priv_version = PRIV_VERSION_1_11_0; > -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > -priv_version = PRIV_VERSION_1_10_0; > -} else { > -error_setg(errp, > - "Unsupported privilege spec version '%s'", > - cpu->cfg.priv_spec); > -return; > -} > - > -env->priv_ver = priv_version; > -} > -} > - > static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > { > CPURISCVState *env = >env; > @@ -1112,33 +1087,6 @@ static void > riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > } > } > > -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > -{ > -RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); > -CPUClass *cc = CPU_CLASS(mcc); > -CPURISCVState *env = >env; > - > -/* Validate that MISA_MXL is set properly. */ > -switch (env->misa_mxl_max) { > -#ifdef TARGET_RISCV64 > -case MXL_RV64: > -case MXL_RV128: > -cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > -break; > -#endif > -case MXL_RV32: > -cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > -break; > -default: > -g_assert_not_reached(); > -} > - > -if (env->misa_mxl_max != env->misa_mxl) { > -error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); > -return; > -} > -} > - > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > @@ -1512,74 +1460,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, > Error **errp) > #endif > } > > -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > -{ > -if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { > -error_setg(errp, "H extension requires priv spec 1.12.0"); > -return; > -} > -} > - > -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) > -{ > -RISCVCPU *cpu = RISCV_CPU(dev); > -CPURISCVState *env = >env; > -Error *local_err = NULL; > - > -if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { > -error_setg(errp, "'host' CPU is not compatible with TCG > acceleration"); > -return; > -} > - > -riscv_cpu_validate_misa_mxl(cpu, _err); > -if (local_err != NULL) { > -error_propagate(errp, local_err); > -return; > -} > - > -riscv_cpu_validate_priv_spec(cpu, _err); > -if (local_err != NULL) { > -error_propagate(errp, local_err); > -return; > -} > - > -riscv_cpu_validate_misa_priv(env, _err); > -if (local_err != NULL) { > -error_propagate(errp, local_err); > -return; > -} > - > -if (cpu->cfg.epmp && !cpu->cfg.pmp) { > -/* > - * Enhanced PMP should only be available > - * on harts with PMP support > - */ > -error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > -return; > -} > - > -riscv_cpu_validate_set_extensions(cpu, _err); > -if (local_err != NULL) { > -error_propagate(errp, local_err); > -return; > -} > - >
[PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different realize() path during the common riscv_cpu_realize(), making it a good choice to start moving TCG exclusive code to tcg-cpu.c. Rename it to tcg_cpu_realizefn() and assign it as a implementation of accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar approach with KVM in the near future. riscv_cpu_validate_set_extensions() is too big and with too many dependencies to be moved in this same patch. We'll do that next. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 128 --- target/riscv/tcg/tcg-cpu.c | 132 + 2 files changed, 132 insertions(+), 128 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 38dcbc4dd2..36c5c6e579 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "pmu.h" #include "internals.h" -#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -1065,29 +1063,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } } -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ -CPURISCVState *env = >env; -int priv_version = -1; - -if (cpu->cfg.priv_spec) { -if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { -priv_version = PRIV_VERSION_1_12_0; -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { -priv_version = PRIV_VERSION_1_11_0; -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { -priv_version = PRIV_VERSION_1_10_0; -} else { -error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); -return; -} - -env->priv_ver = priv_version; -} -} - static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env = >env; @@ -1112,33 +1087,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) -{ -RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); -CPUClass *cc = CPU_CLASS(mcc); -CPURISCVState *env = >env; - -/* Validate that MISA_MXL is set properly. */ -switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 -case MXL_RV64: -case MXL_RV128: -cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; -break; -#endif -case MXL_RV32: -cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; -break; -default: -g_assert_not_reached(); -} - -if (env->misa_mxl_max != env->misa_mxl) { -error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); -return; -} -} - /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1512,74 +1460,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) #endif } -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ -if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { -error_setg(errp, "H extension requires priv spec 1.12.0"); -return; -} -} - -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) -{ -RISCVCPU *cpu = RISCV_CPU(dev); -CPURISCVState *env = >env; -Error *local_err = NULL; - -if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { -error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); -return; -} - -riscv_cpu_validate_misa_mxl(cpu, _err); -if (local_err != NULL) { -error_propagate(errp, local_err); -return; -} - -riscv_cpu_validate_priv_spec(cpu, _err); -if (local_err != NULL) { -error_propagate(errp, local_err); -return; -} - -riscv_cpu_validate_misa_priv(env, _err); -if (local_err != NULL) { -error_propagate(errp, local_err); -return; -} - -if (cpu->cfg.epmp && !cpu->cfg.pmp) { -/* - * Enhanced PMP should only be available - * on harts with PMP support - */ -error_setg(errp, "Invalid configuration: EPMP requires PMP support"); -return; -} - -riscv_cpu_validate_set_extensions(cpu, _err); -if (local_err != NULL) { -error_propagate(errp, local_err); -return; -} - -#ifndef CONFIG_USER_ONLY -CPU(dev)->tcg_cflags |= CF_PCREL; - -if (cpu->cfg.ext_sstc) { -riscv_timer_init(cpu); -} - -if (cpu->cfg.pmu_num) { -if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { -cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_pmu_timer_cb, cpu); -} -