Re: [PATCH 03/10] arm: allwinner-h3: add Clock Control Unit

2019-12-12 Thread Philippe Mathieu-Daudé 

On 12/2/19 10:09 PM, Niek Linnenbank wrote:

The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.

Signed-off-by: Niek Linnenbank 
---
  hw/arm/allwinner-h3.c  |  11 ++
  hw/misc/Makefile.objs  |   1 +
  hw/misc/allwinner-h3-clk.c | 227 +
  include/hw/arm/allwinner-h3.h  |   2 +
  include/hw/misc/allwinner-h3-clk.h |  41 ++
  5 files changed, 282 insertions(+)
  create mode 100644 hw/misc/allwinner-h3-clk.c
  create mode 100644 include/hw/misc/allwinner-h3-clk.h

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 470fdfebef..5566e979ec 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -37,6 +37,9 @@ static void aw_h3_init(Object *obj)
  
  sysbus_init_child_obj(obj, "timer", >timer, sizeof(s->timer),

TYPE_AW_A10_PIT);
+
+sysbus_init_child_obj(obj, "ccu", >ccu, sizeof(s->ccu),
+  TYPE_AW_H3_CLK);
  }
  
  static void aw_h3_realize(DeviceState *dev, Error **errp)

@@ -172,6 +175,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp)
  memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE,
  >sram_c);
  
+/* Clock Control Unit */

+object_property_set_bool(OBJECT(>ccu), true, "realized", );
+if (err) {
+error_propagate(errp, err);
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(>ccu), 0, AW_H3_CCU_BASE);
+
  /* UART */
  if (serial_hd(0)) {
  serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2,
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ba898a5781..200ed44ce1 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/
  
  common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
  
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o

  common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
  common-obj-$(CONFIG_NSERIES) += cbus.o
  common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
diff --git a/hw/misc/allwinner-h3-clk.c b/hw/misc/allwinner-h3-clk.c
new file mode 100644
index 00..77c55b4f92
--- /dev/null
+++ b/hw/misc/allwinner-h3-clk.c
@@ -0,0 +1,227 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-clk.h"
+
+/* CCU register offsets */
+#define REG_PLL_CPUX (0x) /* PLL CPUX Control */
+#define REG_PLL_AUDIO(0x0008) /* PLL Audio Control */
+#define REG_PLL_VIDEO(0x0010) /* PLL Video Control */
+#define REG_PLL_VE   (0x0018) /* PLL VE Control */
+#define REG_PLL_DDR  (0x0020) /* PLL DDR Control */
+#define REG_PLL_PERIPH0  (0x0028) /* PLL Peripherals 0 Control */
+#define REG_PLL_GPU  (0x0038) /* PLL GPU Control */
+#define REG_PLL_PERIPH1  (0x0044) /* PLL Peripherals 1 Control */
+#define REG_PLL_DE   (0x0048) /* PLL Display Engine Control */
+#define REG_CPUX_AXI (0x0050) /* CPUX/AXI Configuration */
+#define REG_APB1 (0x0054) /* ARM Peripheral Bus 1 Config */
+#define REG_APB2 (0x0058) /* ARM Peripheral Bus 2 Config */
+#define REG_MBUS (0x00FC) /* MBUS Reset */
+#define REG_PLL_TIME0(0x0200) /* PLL Stable Time 0 */
+#define REG_PLL_TIME1(0x0204) /* PLL Stable Time 1 */
+#define REG_PLL_CPUX_BIAS(0x0220) /* PLL CPUX Bias */
+#define REG_PLL_AUDIO_BIAS   (0x0224) /* PLL Audio Bias */
+#define REG_PLL_VIDEO_BIAS   (0x0228) /* PLL Video Bias */
+#define REG_PLL_VE_BIAS  (0x022C) /* PLL VE Bias */
+#define REG_PLL_DDR_BIAS (0x0230) /* PLL DDR Bias */
+#define REG_PLL_PERIPH0_BIAS (0x0234) /* PLL Peripherals 0 Bias */
+#define REG_PLL_GPU_BIAS (0x023C) /* PLL GPU Bias */
+#define REG_PLL_PERIPH1_BIAS (0x0244) /* PLL Peripherals 1 Bias */
+#define REG_PLL_DE_BIAS  (0x0248) /* PLL Display

[PATCH 03/10] arm: allwinner-h3: add Clock Control Unit

2019-12-02 Thread Niek Linnenbank 
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.

Signed-off-by: Niek Linnenbank 
---
 hw/arm/allwinner-h3.c  |  11 ++
 hw/misc/Makefile.objs  |   1 +
 hw/misc/allwinner-h3-clk.c | 227 +
 include/hw/arm/allwinner-h3.h  |   2 +
 include/hw/misc/allwinner-h3-clk.h |  41 ++
 5 files changed, 282 insertions(+)
 create mode 100644 hw/misc/allwinner-h3-clk.c
 create mode 100644 include/hw/misc/allwinner-h3-clk.h

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 470fdfebef..5566e979ec 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -37,6 +37,9 @@ static void aw_h3_init(Object *obj)
 
 sysbus_init_child_obj(obj, "timer", >timer, sizeof(s->timer),
   TYPE_AW_A10_PIT);
+
+sysbus_init_child_obj(obj, "ccu", >ccu, sizeof(s->ccu),
+  TYPE_AW_H3_CLK);
 }
 
 static void aw_h3_realize(DeviceState *dev, Error **errp)
@@ -172,6 +175,14 @@ static void aw_h3_realize(DeviceState *dev, Error **errp)
 memory_region_add_subregion(get_system_memory(), AW_H3_SRAM_C_BASE,
 >sram_c);
 
+/* Clock Control Unit */
+object_property_set_bool(OBJECT(>ccu), true, "realized", );
+if (err) {
+error_propagate(errp, err);
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(>ccu), 0, AW_H3_CCU_BASE);
+
 /* UART */
 if (serial_hd(0)) {
 serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2,
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ba898a5781..200ed44ce1 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) += macio/
 
 common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
 
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-clk.o
 common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
 common-obj-$(CONFIG_NSERIES) += cbus.o
 common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
diff --git a/hw/misc/allwinner-h3-clk.c b/hw/misc/allwinner-h3-clk.c
new file mode 100644
index 00..77c55b4f92
--- /dev/null
+++ b/hw/misc/allwinner-h3-clk.c
@@ -0,0 +1,227 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-clk.h"
+
+/* CCU register offsets */
+#define REG_PLL_CPUX (0x) /* PLL CPUX Control */
+#define REG_PLL_AUDIO(0x0008) /* PLL Audio Control */
+#define REG_PLL_VIDEO(0x0010) /* PLL Video Control */
+#define REG_PLL_VE   (0x0018) /* PLL VE Control */
+#define REG_PLL_DDR  (0x0020) /* PLL DDR Control */
+#define REG_PLL_PERIPH0  (0x0028) /* PLL Peripherals 0 Control */
+#define REG_PLL_GPU  (0x0038) /* PLL GPU Control */
+#define REG_PLL_PERIPH1  (0x0044) /* PLL Peripherals 1 Control */
+#define REG_PLL_DE   (0x0048) /* PLL Display Engine Control */
+#define REG_CPUX_AXI (0x0050) /* CPUX/AXI Configuration */
+#define REG_APB1 (0x0054) /* ARM Peripheral Bus 1 Config */
+#define REG_APB2 (0x0058) /* ARM Peripheral Bus 2 Config */
+#define REG_MBUS (0x00FC) /* MBUS Reset */
+#define REG_PLL_TIME0(0x0200) /* PLL Stable Time 0 */
+#define REG_PLL_TIME1(0x0204) /* PLL Stable Time 1 */
+#define REG_PLL_CPUX_BIAS(0x0220) /* PLL CPUX Bias */
+#define REG_PLL_AUDIO_BIAS   (0x0224) /* PLL Audio Bias */
+#define REG_PLL_VIDEO_BIAS   (0x0228) /* PLL Video Bias */
+#define REG_PLL_VE_BIAS  (0x022C) /* PLL VE Bias */
+#define REG_PLL_DDR_BIAS (0x0230) /* PLL DDR Bias */
+#define REG_PLL_PERIPH0_BIAS (0x0234) /* PLL Peripherals 0 Bias */
+#define REG_PLL_GPU_BIAS (0x023C) /* PLL GPU Bias */
+#define REG_PLL_PERIPH1_BIAS (0x0244) /* PLL Peripherals 1 Bias */
+#define REG_PLL_DE_BIAS  (0x0248) /* PLL Display Engine Bias */
+#define REG_PLL_CPUX_TUNING  (0x0250) /* PLL CPUX Tuning