Re: [PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
On Fri, Aug 25, 2023 at 10:08:36AM -0300, Daniel Henrique Barboza wrote:
> This function is the core of the RISC-V validations for TCG CPUs, and it
> has a lot going on.
>
> Functions in cpu.c were made public to allow them to be used by the KVM
> accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
> hard to move it to another file due to its dependency with isa_edata_arr[]
> array, thus make it public and use it as is for now.
>
> riscv_cpu_validate_set_extensions() is kept public because it's used by
> csr.c in write_misa().
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 361 +
> target/riscv/cpu.h | 8 +-
> target/riscv/csr.c | 1 +
> target/riscv/tcg/tcg-cpu.c | 352
> target/riscv/tcg/tcg-cpu.h | 28 +++
> 5 files changed, 393 insertions(+), 357 deletions(-)
> create mode 100644 target/riscv/tcg/tcg-cpu.h
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 36c5c6e579..12cea62ee7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] = {
> /* Hash that stores user set extensions */
> static GHashTable *multi_ext_user_opts;
>
> -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> {
> bool *ext_enabled = (void *)>cfg + ext_offset;
>
> return *ext_enabled;
> }
>
> -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
> - bool en)
> +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
> {
> bool *ext_enabled = (void *)>cfg + ext_offset;
>
> *ext_enabled = en;
> }
>
> -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> +int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> {
> int i;
>
> @@ -194,38 +193,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t
> ext_offset)
> return PRIV_VERSION_1_10_0;
> }
>
> -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> {
> return g_hash_table_contains(multi_ext_user_opts,
> GUINT_TO_POINTER(ext_offset));
> }
>
> -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> -bool value)
> -{
> -CPURISCVState *env = >env;
> -bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
> -int min_version;
> -
> -if (prev_val == value) {
> -return;
> -}
> -
> -if (cpu_cfg_ext_is_user_set(ext_offset)) {
> -return;
> -}
> -
> -if (value && env->priv_ver != PRIV_VERSION_LATEST) {
> -/* Do not enable it if priv_ver is older than min_version */
> -min_version = cpu_cfg_ext_get_min_version(ext_offset);
> -if (env->priv_ver < min_version) {
> -return;
> -}
> -}
> -
> -isa_ext_update_enabled(cpu, ext_offset, value);
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -1024,46 +997,7 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> disassemble_info *info)
> }
> }
>
> -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> - Error **errp)
> -{
> -if (!is_power_of_2(cfg->vlen)) {
> -error_setg(errp, "Vector extension VLEN must be power of 2");
> -return;
> -}
> -if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
> -error_setg(errp,
> - "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> -return;
> -}
> -if (!is_power_of_2(cfg->elen)) {
> -error_setg(errp, "Vector extension ELEN must be power of 2");
> -return;
> -}
> -if (cfg->elen > 64 || cfg->elen < 8) {
> -error_setg(errp,
> - "Vector extension implementation only supports ELEN "
> - "in the range [8, 64]");
> -return;
> -}
> -if (cfg->vext_spec) {
> -if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
> -env->vext_ver = VEXT_VERSION_1_00_0;
> -} else {
> -error_setg(errp, "Unsupported vector spec version '%s'",
> - cfg->vext_spec);
> -return;
> -}
> -} else if (env->vext_ver == 0) {
> -qemu_log("vector version is not specified, "
> - "use the default value v1.0\n");
> -
> -env->vext_ver = VEXT_VERSION_1_00_0;
> -}
> -}
> -
> -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> {
> CPURISCVState *env =
[PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.
Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa_edata_arr[]
array, thus make it public and use it as is for now.
riscv_cpu_validate_set_extensions() is kept public because it's used by
csr.c in write_misa().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 361 +
target/riscv/cpu.h | 8 +-
target/riscv/csr.c | 1 +
target/riscv/tcg/tcg-cpu.c | 352
target/riscv/tcg/tcg-cpu.h | 28 +++
5 files changed, 393 insertions(+), 357 deletions(-)
create mode 100644 target/riscv/tcg/tcg-cpu.h
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 36c5c6e579..12cea62ee7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] = {
/* Hash that stores user set extensions */
static GHashTable *multi_ext_user_opts;
-static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
{
bool *ext_enabled = (void *)>cfg + ext_offset;
return *ext_enabled;
}
-static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
- bool en)
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
{
bool *ext_enabled = (void *)>cfg + ext_offset;
*ext_enabled = en;
}
-static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
{
int i;
@@ -194,38 +193,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t
ext_offset)
return PRIV_VERSION_1_10_0;
}
-static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
return g_hash_table_contains(multi_ext_user_opts,
GUINT_TO_POINTER(ext_offset));
}
-static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-bool value)
-{
-CPURISCVState *env = >env;
-bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
-int min_version;
-
-if (prev_val == value) {
-return;
-}
-
-if (cpu_cfg_ext_is_user_set(ext_offset)) {
-return;
-}
-
-if (value && env->priv_ver != PRIV_VERSION_LATEST) {
-/* Do not enable it if priv_ver is older than min_version */
-min_version = cpu_cfg_ext_get_min_version(ext_offset);
-if (env->priv_ver < min_version) {
-return;
-}
-}
-
-isa_ext_update_enabled(cpu, ext_offset, value);
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -1024,46 +997,7 @@ static void riscv_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
}
}
-static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
- Error **errp)
-{
-if (!is_power_of_2(cfg->vlen)) {
-error_setg(errp, "Vector extension VLEN must be power of 2");
-return;
-}
-if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
-error_setg(errp,
- "Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
-return;
-}
-if (!is_power_of_2(cfg->elen)) {
-error_setg(errp, "Vector extension ELEN must be power of 2");
-return;
-}
-if (cfg->elen > 64 || cfg->elen < 8) {
-error_setg(errp,
- "Vector extension implementation only supports ELEN "
- "in the range [8, 64]");
-return;
-}
-if (cfg->vext_spec) {
-if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
-env->vext_ver = VEXT_VERSION_1_00_0;
-} else {
-error_setg(errp, "Unsupported vector spec version '%s'",
- cfg->vext_spec);
-return;
-}
-} else if (env->vext_ver == 0) {
-qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-
-env->vext_ver = VEXT_VERSION_1_00_0;
-}
-}
-
-static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
{
CPURISCVState *env = >env;
int i;
@@ -1087,291 +1021,6 @@ static void
riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
-/*
- * Check consistency between chosen extensions while setting
- * cpu->cfg accordingly.
- */
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-{
-CPURISCVState *env = >env;
-Error *local_err = NULL;
-
