Re: [PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c
On Fri, Aug 25, 2023 at 10:08:37AM -0300, Daniel Henrique Barboza wrote:
> Move the remaining of riscv_tcg_ops now that we have a working realize()
> implementation.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 58 -
> target/riscv/cpu.h | 4 ---
> target/riscv/tcg/tcg-cpu.c | 59 ++
> 3 files changed, 59 insertions(+), 62 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 12cea62ee7..839b83e52a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -839,24 +839,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
> return env->pc;
> }
>
> -static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> - const TranslationBlock *tb)
> -{
> -if (!(tb_cflags(tb) & CF_PCREL)) {
> -RISCVCPU *cpu = RISCV_CPU(cs);
> -CPURISCVState *env = >env;
> -RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> -
> -tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> -
> -if (xl == MXL_RV32) {
> -env->pc = (int32_t) tb->pc;
> -} else {
> -env->pc = tb->pc;
> -}
> -}
> -}
> -
> static bool riscv_cpu_has_work(CPUState *cs)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -872,29 +854,6 @@ static bool riscv_cpu_has_work(CPUState *cs)
> #endif
> }
>
> -static void riscv_restore_state_to_opc(CPUState *cs,
> - const TranslationBlock *tb,
> - const uint64_t *data)
> -{
> -RISCVCPU *cpu = RISCV_CPU(cs);
> -CPURISCVState *env = >env;
> -RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> -target_ulong pc;
> -
> -if (tb_cflags(tb) & CF_PCREL) {
> -pc = (env->pc & TARGET_PAGE_MASK) | data[0];
> -} else {
> -pc = data[0];
> -}
> -
> -if (xl == MXL_RV32) {
> -env->pc = (int32_t)pc;
> -} else {
> -env->pc = pc;
> -}
> -env->bins = data[1];
> -}
> -
> static void riscv_cpu_reset_hold(Object *obj)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -1796,23 +1755,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> };
> #endif
>
> -const struct TCGCPUOps riscv_tcg_ops = {
> -.initialize = riscv_translate_init,
> -.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> -.restore_state_to_opc = riscv_restore_state_to_opc,
> -
> -#ifndef CONFIG_USER_ONLY
> -.tlb_fill = riscv_cpu_tlb_fill,
> -.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> -.do_interrupt = riscv_cpu_do_interrupt,
> -.do_transaction_failed = riscv_cpu_do_transaction_failed,
> -.do_unaligned_access = riscv_cpu_do_unaligned_access,
> -.debug_excp_handler = riscv_cpu_debug_excp_handler,
> -.debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
> -.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
> -#endif /* !CONFIG_USER_ONLY */
> -};
> -
> static bool riscv_cpu_is_dynamic(Object *cpu_obj)
> {
> return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 721bd0b119..2ac00a0304 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx {
> RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
> };
>
> -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
> -#include "hw/core/tcg-cpu-ops.h"
> -extern const struct TCGCPUOps riscv_tcg_ops;
> -
> /* used by tcg/tcg-cpu.c*/
> void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fb17097bb1..2024c98793 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -26,7 +26,66 @@
> #include "qemu/accel.h"
> #include "qemu/error-report.h"
> #include "hw/core/accel-cpu.h"
> +#include "hw/core/tcg-cpu-ops.h"
> +#include "tcg/tcg.h"
>
> +static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> + const TranslationBlock *tb)
> +{
> +if (!(tb_cflags(tb) & CF_PCREL)) {
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +CPURISCVState *env = >env;
> +RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +
> +tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> +
> +if (xl == MXL_RV32) {
> +env->pc = (int32_t) tb->pc;
> +} else {
> +env->pc = tb->pc;
> +}
> +}
> +}
> +
> +static void riscv_restore_state_to_opc(CPUState *cs,
> + const TranslationBlock *tb,
> + const uint64_t *data)
> +{
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +CPURISCVState *env = >env;
> +RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +target_ulong pc;
> +
> +if (tb_cflags(tb)
Re: [PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c
On 25/8/23 15:08, Daniel Henrique Barboza wrote:
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 58 -
target/riscv/cpu.h | 4 ---
target/riscv/tcg/tcg-cpu.c | 59 ++
3 files changed, 59 insertions(+), 62 deletions(-)
+const struct TCGCPUOps riscv_tcg_ops = {
+.initialize = riscv_translate_init,
+.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+.restore_state_to_opc = riscv_restore_state_to_opc,
+
+#ifndef CONFIG_USER_ONLY
+.tlb_fill = riscv_cpu_tlb_fill,
+.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+.do_interrupt = riscv_cpu_do_interrupt,
+.do_transaction_failed = riscv_cpu_do_transaction_failed,
+.do_unaligned_access = riscv_cpu_do_unaligned_access,
+.debug_excp_handler = riscv_cpu_debug_excp_handler,
+.debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
We can remove the "riscv_tcg_ops is being imported from cpu.c for now."
comment in tcg_cpu_init_ops(), otherwise:
Reviewed-by: Philippe Mathieu-Daudé
[PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 58 -
target/riscv/cpu.h | 4 ---
target/riscv/tcg/tcg-cpu.c | 59 ++
3 files changed, 59 insertions(+), 62 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 12cea62ee7..839b83e52a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -839,24 +839,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
return env->pc;
}
-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
-{
-if (!(tb_cflags(tb) & CF_PCREL)) {
-RISCVCPU *cpu = RISCV_CPU(cs);
-CPURISCVState *env = >env;
-RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-
-tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
-
-if (xl == MXL_RV32) {
-env->pc = (int32_t) tb->pc;
-} else {
-env->pc = tb->pc;
-}
-}
-}
-
static bool riscv_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -872,29 +854,6 @@ static bool riscv_cpu_has_work(CPUState *cs)
#endif
}
-static void riscv_restore_state_to_opc(CPUState *cs,
- const TranslationBlock *tb,
- const uint64_t *data)
-{
-RISCVCPU *cpu = RISCV_CPU(cs);
-CPURISCVState *env = >env;
-RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-target_ulong pc;
-
-if (tb_cflags(tb) & CF_PCREL) {
-pc = (env->pc & TARGET_PAGE_MASK) | data[0];
-} else {
-pc = data[0];
-}
-
-if (xl == MXL_RV32) {
-env->pc = (int32_t)pc;
-} else {
-env->pc = pc;
-}
-env->bins = data[1];
-}
-
static void riscv_cpu_reset_hold(Object *obj)
{
#ifndef CONFIG_USER_ONLY
@@ -1796,23 +1755,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-const struct TCGCPUOps riscv_tcg_ops = {
-.initialize = riscv_translate_init,
-.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
-.restore_state_to_opc = riscv_restore_state_to_opc,
-
-#ifndef CONFIG_USER_ONLY
-.tlb_fill = riscv_cpu_tlb_fill,
-.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
-.do_interrupt = riscv_cpu_do_interrupt,
-.do_transaction_failed = riscv_cpu_do_transaction_failed,
-.do_unaligned_access = riscv_cpu_do_unaligned_access,
-.debug_excp_handler = riscv_cpu_debug_excp_handler,
-.debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
-.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
{
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 721bd0b119..2ac00a0304 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -706,10 +706,6 @@ enum riscv_pmu_event_idx {
RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
};
-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-#include "hw/core/tcg-cpu-ops.h"
-extern const struct TCGCPUOps riscv_tcg_ops;
-
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fb17097bb1..2024c98793 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -26,7 +26,66 @@
#include "qemu/accel.h"
#include "qemu/error-report.h"
#include "hw/core/accel-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg.h"
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+if (!(tb_cflags(tb) & CF_PCREL)) {
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
+if (xl == MXL_RV32) {
+env->pc = (int32_t) tb->pc;
+} else {
+env->pc = tb->pc;
+}
+}
+}
+
+static void riscv_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+target_ulong pc;
+
+if (tb_cflags(tb) & CF_PCREL) {
+pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+} else {
+pc = data[0];
+}
+
+if (xl == MXL_RV32) {
+env->pc = (int32_t)pc;
+} else {
+env->pc = pc;
+}
+env->bins = data[1];
+}
+
+const struct TCGCPUOps riscv_tcg_ops = {
+.initialize = riscv_translate_init,
+.synchronize_from_tb =
