Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 7 +
target/arm/tcg/translate-a64.c | 54 ++
2 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 613cc9365c..7411d4ba97 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -61,6 +61,7 @@
@qrrr_b . q:1 .. ... rm:5 .. rn:5 rd:5 _e esz=0
@qrrr_h . q:1 .. ... rm:5 .. rn:5 rd:5 _e esz=1
+@qrrr_s . q:1 .. ... rm:5 .. rn:5 rd:5 _e esz=2
@qrrr_sd. q:1 .. ... rm:5 .. rn:5 rd:5 _e esz=%esz_sd
@qrrr_e . q:1 .. esz:2 . rm:5 .. rn:5 rd:5 _e
@qr2r_e . q:1 .. esz:2 . . .. rm:5 rd:5 _e rn=%rd
@@ -946,6 +947,9 @@ SQRDMULH_v 0.10 1110 ..1 . 10110 1 . .
@qrrr_e
SQRDMLAH_v 0.10 1110 ..0 . 1 1 . . @qrrr_e
SQRDMLSH_v 0.10 1110 ..0 . 10001 1 . . @qrrr_e
+SDOT_v 0.00 1110 100 . 10010 1 . . @qrrr_s
+UDOT_v 0.10 1110 100 . 10010 1 . . @qrrr_s
+
### Advanced SIMD scalar x indexed element
FMUL_si 0101 00 .. 1001 . 0 . . @rrx_h
@@ -1020,6 +1024,9 @@ SQRDMLAH_vi 0.10 10 .. 1101 . 0 . .
@qrrx_s
SQRDMLSH_vi 0.10 01 .. . 0 . . @qrrx_h
SQRDMLSH_vi 0.10 10 .. . 0 . . @qrrx_s
+SDOT_vi 0.00 10 .. 1110 . 0 . . @qrrx_s
+UDOT_vi 0.10 10 .. 1110 . 0 . . @qrrx_s
+
# Floating-point conditional select
FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 32c24c7422..f2e7d8d75c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5592,6 +5592,18 @@ TRANS(SQRDMULH_v, do_gvec_fn3_no8_no64, a,
gen_gvec_sqrdmulh_qc)
TRANS_FEAT(SQRDMLAH_v, aa64_rdm, do_gvec_fn3_no8_no64, a, gen_gvec_sqrdmlah_qc)
TRANS_FEAT(SQRDMLSH_v, aa64_rdm, do_gvec_fn3_no8_no64, a, gen_gvec_sqrdmlsh_qc)
+static bool do_dot_vector(DisasContext *s, arg_qrrr_e *a,
+ gen_helper_gvec_4 *fn)
+{
+if (fp_access_check(s)) {
+gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd, 0, fn);
+}
+return true;
+}
+
+TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_sdot_b)
+TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b)
+
/*
* Advanced SIMD scalar/vector x indexed element
*/
@@ -5914,6 +5926,18 @@ static gen_helper_gvec_4 * const
f_vector_idx_sqrdmlsh[2] = {
TRANS_FEAT(SQRDMLSH_vi, aa64_rdm, do_int3_qc_vector_idx, a,
f_vector_idx_sqrdmlsh)
+static bool do_dot_vector_idx(DisasContext *s, arg_qrrx_e *a,
+ gen_helper_gvec_4 *fn)
+{
+if (fp_access_check(s)) {
+gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd, a->idx, fn);
+}
+return true;
+}
+
+TRANS_FEAT(SDOT_vi, aa64_dp, do_dot_vector_idx, a, gen_helper_gvec_sdot_idx_b)
+TRANS_FEAT(UDOT_vi, aa64_dp, do_dot_vector_idx, a, gen_helper_gvec_udot_idx_b)
+
/*
* Advanced SIMD scalar pairwise
*/
@@ -10890,14 +10914,6 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
int rot;
switch (u * 16 + opcode) {
-case 0x02: /* SDOT (vector) */
-case 0x12: /* UDOT (vector) */
-if (size != MO_32) {
-unallocated_encoding(s);
-return;
-}
-feature = dc_isar_feature(aa64_dp, s);
-break;
case 0x03: /* USDOT */
if (size != MO_32) {
unallocated_encoding(s);
@@ -10947,8 +10963,10 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
break;
default:
+case 0x02: /* SDOT (vector) */
case 0x10: /* SQRDMLAH (vector) */
case 0x11: /* SQRDMLSH (vector) */
+case 0x12: /* UDOT (vector) */
unallocated_encoding(s);
return;
}
@@ -10961,11 +10979,6 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
switch (opcode) {
-case 0x2: /* SDOT / UDOT */
-gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0,
- u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
-return;
-
case 0x3: /* USDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_usdot_b);
return;
@@ -12043,13 +12056,6 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
case 0x0b: /* SQDMULL, SQDMULL2 */
is_long = true;
break;
-case 0x0e: /* SDOT */
-case 0x1e: /* UDOT */
-if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {
-unallocated_encoding(s);
-return;
-}
-break;
case 0x0f:
switch (size) {
case
