Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 +
target/arm/tcg/translate-a64.c | 77 +-
2 files changed, 31 insertions(+), 48 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 6819fd2587..15344a73de 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -951,6 +951,7 @@ SDOT_v 0.00 1110 100 . 10010 1 . .
@qrrr_s
UDOT_v 0.10 1110 100 . 10010 1 . . @qrrr_s
USDOT_v 0.00 1110 100 . 10011 1 . . @qrrr_s
BFDOT_v 0.10 1110 010 . 1 1 . . @qrrr_s
+BFMLAL_v0.10 1110 110 . 1 1 . . @qrrr_h
### Advanced SIMD scalar x indexed element
@@ -1031,6 +1032,7 @@ UDOT_vi 0.10 10 .. 1110 . 0 . .
@qrrx_s
SUDOT_vi0.00 00 .. . 0 . . @qrrx_s
USDOT_vi0.00 10 .. . 0 . . @qrrx_s
BFDOT_vi0.00 01 .. . 0 . . @qrrx_s
+BFMLAL_vi 0.00 11 .. . 0 . . @qrrx_h
# Floating-point conditional select
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0f44cd5aee..95be862dde 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5606,6 +5606,19 @@ TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a,
gen_helper_gvec_udot_b)
TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b)
TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfdot)
+static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e *a)
+{
+if (!dc_isar_feature(aa64_bf16, s)) {
+return false;
+}
+if (fp_access_check(s)) {
+/* Q bit selects BFMLALB vs BFMLALT. */
+gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, false, a->q,
+ gen_helper_gvec_bfmlal);
+}
+return true;
+}
+
/*
* Advanced SIMD scalar/vector x indexed element
*/
@@ -5946,6 +5959,20 @@ TRANS_FEAT(USDOT_vi, aa64_i8mm, do_dot_vector_idx, a,
TRANS_FEAT(BFDOT_vi, aa64_bf16, do_dot_vector_idx, a,
gen_helper_gvec_bfdot_idx)
+static bool trans_BFMLAL_vi(DisasContext *s, arg_qrrx_e *a)
+{
+if (!dc_isar_feature(aa64_bf16, s)) {
+return false;
+}
+if (fp_access_check(s)) {
+/* Q bit selects BFMLALB vs BFMLALT. */
+gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, 0,
+ (a->idx << 1) | a->q,
+ gen_helper_gvec_bfmlal_idx);
+}
+return true;
+}
+
/*
* Advanced SIMD scalar pairwise
*/
@@ -10952,23 +10979,13 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = dc_isar_feature(aa64_bf16, s);
break;
-case 0x1f:
-switch (size) {
-case 3: /* BFMLAL{B,T} */
-feature = dc_isar_feature(aa64_bf16, s);
-break;
-default:
-case 1: /* BFDOT */
-unallocated_encoding(s);
-return;
-}
-break;
default:
case 0x02: /* SDOT (vector) */
case 0x03: /* USDOT */
case 0x10: /* SQRDMLAH (vector) */
case 0x11: /* SQRDMLSH (vector) */
case 0x12: /* UDOT (vector) */
+case 0x1f: /* BFDOT / BFMLAL */
unallocated_encoding(s);
return;
}
@@ -11037,17 +11054,6 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
case 0xd: /* BFMMLA */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfmmla);
return;
-case 0xf:
-switch (size) {
-case 3: /* BFMLAL{B,T} */
-gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, false, is_q,
- gen_helper_gvec_bfmlal);
-break;
-default:
-g_assert_not_reached();
-}
-return;
-
default:
g_assert_not_reached();
}
@@ -12051,24 +12057,6 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
case 0x0b: /* SQDMULL, SQDMULL2 */
is_long = true;
break;
-case 0x0f:
-switch (size) {
-case 3: /* BFMLAL{B,T} */
-if (is_scalar || !dc_isar_feature(aa64_bf16, s)) {
-unallocated_encoding(s);
-return;
-}
-/* can't set is_fp without other incorrect size checks */
-size = MO_16;
-break;
-default:
-case 0: /* SUDOT */
-case 1: /* BFDOT */
-case 2: /* USDOT */
-unallocated_encoding(s);
-return;
-}
-break;
case 0x11: /* FCMLA #0 */
case 0x13: /* FCMLA #90 */
case 0x15: /* FCMLA #180 */
@@ -12089,6 +12077,7 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
case 0x0c: /* SQDMULH */
case 0x0d: /* SQRDMULH */
case 0x0e: /* SDOT */
+case 0x0f: /* SUD
