Re: [PATCH 08/24] mips: spelling fixes
On 23/8/23 08:53, Michael Tokarev wrote: Signed-off-by: Michael Tokarev --- hw/mips/malta.c | 2 +- target/mips/cpu-defs.c.inc | 2 +- target/mips/tcg/msa_helper.c| 12 ++-- target/mips/tcg/mxu_translate.c | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
[PATCH 08/24] mips: spelling fixes
Signed-off-by: Michael Tokarev --- hw/mips/malta.c | 2 +- target/mips/cpu-defs.c.inc | 2 +- target/mips/tcg/msa_helper.c| 12 ++-- target/mips/tcg/mxu_translate.c | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f9618fa5f5..16e9c4773f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -628,5 +628,5 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, }; -/* Bus endianess is always reversed */ +/* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32(x) (x) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 03185d9aa0..c0c389c59a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1046,5 +1046,5 @@ static void mvp_init(CPUMIPSState *env) } -/* MVPConf1 implemented, TLB sharable, no gating storage support, +/* MVPConf1 implemented, TLB shareable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 29b31d70fe..6e93a19a93 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -803,7 +803,7 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) * | HADD_S.W | Vector Signed Horizontal Add (word) | * | HADD_S.D | Vector Signed Horizontal Add (doubleword)| - * | HADD_U.H | Vector Unigned Horizontal Add (halfword) | - * | HADD_U.W | Vector Unigned Horizontal Add (word) | - * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) | + * | HADD_U.H | Vector Unsigned Horizontal Add (halfword)| + * | HADD_U.W | Vector Unsigned Horizontal Add (word)| + * | HADD_U.D | Vector Unsigned Horizontal Add (doubleword) | * +---+--+ */ @@ -3452,7 +3452,7 @@ void helper_msa_mulv_d(CPUMIPSState *env, * | HSUB_S.W | Vector Signed Horizontal Subtract (word) | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) | - * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword)| - * | HSUB_U.W | Vector Unigned Horizontal Subtract (word)| - * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) | + * | HSUB_U.H | Vector Unsigned Horizontal Subtract (halfword) | + * | HSUB_U.W | Vector Unsigned Horizontal Subtract (word) | + * | HSUB_U.D | Vector Unsigned Horizontal Subtract (doubleword) | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) | diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index e662acd5df..cfcd8ac9bc 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2978,5 +2978,5 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) *to 16-bit and put results as packed 16-bit data *into XRa and XRd. - *aptn2 manages action add or subract of pairs of data. + *aptn2 manages action add or subtract of pairs of data. * * Q8ACCE XRa, XRb, XRc, XRd, aptn2 @@ -2985,5 +2985,5 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) *to 16-bit and accumulate results as packed 16-bit data *into XRa and XRd. - *aptn2 manages action add or subract of pairs of data. + *aptn2 manages action add or subtract of pairs of data. */ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) @@ -4057,5 +4057,5 @@ static void gen_mxu_s32sfl(DisasContext *ctx) /* * Q8SAD XRa, XRd, XRb, XRc - *Typical SAD opration for motion estimation. + *Typical SAD operation for motion estimation. */ static void gen_mxu_q8sad(DisasContext *ctx) -- 2.39.2
[PATCH 08/24] mips: spelling fixes
Signed-off-by: Michael Tokarev --- hw/mips/malta.c | 2 +- target/mips/cpu-defs.c.inc | 2 +- target/mips/tcg/msa_helper.c| 12 ++-- target/mips/tcg/mxu_translate.c | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f9618fa5f5..16e9c4773f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -628,5 +628,5 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, }; -/* Bus endianess is always reversed */ +/* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32(x) (x) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 03185d9aa0..c0c389c59a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1046,5 +1046,5 @@ static void mvp_init(CPUMIPSState *env) } -/* MVPConf1 implemented, TLB sharable, no gating storage support, +/* MVPConf1 implemented, TLB shareable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 29b31d70fe..6e93a19a93 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -803,7 +803,7 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) * | HADD_S.W | Vector Signed Horizontal Add (word) | * | HADD_S.D | Vector Signed Horizontal Add (doubleword)| - * | HADD_U.H | Vector Unigned Horizontal Add (halfword) | - * | HADD_U.W | Vector Unigned Horizontal Add (word) | - * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) | + * | HADD_U.H | Vector Unsigned Horizontal Add (halfword)| + * | HADD_U.W | Vector Unsigned Horizontal Add (word)| + * | HADD_U.D | Vector Unsigned Horizontal Add (doubleword) | * +---+--+ */ @@ -3452,7 +3452,7 @@ void helper_msa_mulv_d(CPUMIPSState *env, * | HSUB_S.W | Vector Signed Horizontal Subtract (word) | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) | - * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword)| - * | HSUB_U.W | Vector Unigned Horizontal Subtract (word)| - * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) | + * | HSUB_U.H | Vector Unsigned Horizontal Subtract (halfword) | + * | HSUB_U.W | Vector Unsigned Horizontal Subtract (word) | + * | HSUB_U.D | Vector Unsigned Horizontal Subtract (doubleword) | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) | diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index e662acd5df..cfcd8ac9bc 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2978,5 +2978,5 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) *to 16-bit and put results as packed 16-bit data *into XRa and XRd. - *aptn2 manages action add or subract of pairs of data. + *aptn2 manages action add or subtract of pairs of data. * * Q8ACCE XRa, XRb, XRc, XRd, aptn2 @@ -2985,5 +2985,5 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) *to 16-bit and accumulate results as packed 16-bit data *into XRa and XRd. - *aptn2 manages action add or subract of pairs of data. + *aptn2 manages action add or subtract of pairs of data. */ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) @@ -4057,5 +4057,5 @@ static void gen_mxu_s32sfl(DisasContext *ctx) /* * Q8SAD XRa, XRd, XRb, XRc - *Typical SAD opration for motion estimation. + *Typical SAD operation for motion estimation. */ static void gen_mxu_q8sad(DisasContext *ctx) -- 2.39.2
