Re: [PATCH 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

[Peter Maydell]

On Tue, 25 Jun 2024 at 06:09, Richard Henderson
 wrote:
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/tcg/a64.decode  |  4 
>  target/arm/tcg/translate-a64.c | 36 --
>  2 files changed, 12 insertions(+), 28 deletions(-)
>

Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/tcg/a64.decode  |  4 
 target/arm/tcg/translate-a64.c | 36 --
 2 files changed, 12 insertions(+), 28 deletions(-)

diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 15344a73de..b2c7e36969 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -952,6 +952,10 @@ UDOT_v  0.10 1110 100 . 10010 1 . . 
@qrrr_s
 USDOT_v 0.00 1110 100 . 10011 1 . . @qrrr_s
 BFDOT_v 0.10 1110 010 . 1 1 . . @qrrr_s
 BFMLAL_v0.10 1110 110 . 1 1 . . @qrrr_h
+BFMMLA  0110 1110 010 . 11101 1 . . @rrr_q1e0
+SMMLA   0100 1110 100 . 10100 1 . . @rrr_q1e0
+UMMLA   0110 1110 100 . 10100 1 . . @rrr_q1e0
+USMMLA  0100 1110 100 . 10101 1 . . @rrr_q1e0
 
 ### Advanced SIMD scalar x indexed element
 
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 95be862dde..2697c4b305 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5605,6 +5605,10 @@ TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, 
gen_helper_gvec_sdot_b)
 TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b)
 TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b)
 TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfdot)
+TRANS_FEAT(BFMMLA, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfmmla)
+TRANS_FEAT(SMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_smmla_b)
+TRANS_FEAT(UMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_ummla_b)
+TRANS_FEAT(USMMLA, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usmmla_b)
 
 static bool trans_BFMLAL_v(DisasContext *s, arg_qrrr_e *a)
 {
@@ -10949,15 +10953,6 @@ static void 
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
 int rot;
 
 switch (u * 16 + opcode) {
-case 0x04: /* SMMLA */
-case 0x14: /* UMMLA */
-case 0x05: /* USMMLA */
-if (!is_q || size != MO_32) {
-unallocated_encoding(s);
-return;
-}
-feature = dc_isar_feature(aa64_i8mm, s);
-break;
 case 0x18: /* FCMLA, #0 */
 case 0x19: /* FCMLA, #90 */
 case 0x1a: /* FCMLA, #180 */
@@ -10972,19 +10967,16 @@ static void 
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
 }
 feature = dc_isar_feature(aa64_fcma, s);
 break;
-case 0x1d: /* BFMMLA */
-if (size != MO_16 || !is_q) {
-unallocated_encoding(s);
-return;
-}
-feature = dc_isar_feature(aa64_bf16, s);
-break;
 default:
 case 0x02: /* SDOT (vector) */
 case 0x03: /* USDOT */
+case 0x04: /* SMMLA */
+case 0x05: /* USMMLA */
 case 0x10: /* SQRDMLAH (vector) */
 case 0x11: /* SQRDMLSH (vector) */
 case 0x12: /* UDOT (vector) */
+case 0x14: /* UMMLA */
+case 0x1d: /* BFMMLA */
 case 0x1f: /* BFDOT / BFMLAL */
 unallocated_encoding(s);
 return;
@@ -10998,15 +10990,6 @@ static void 
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
 }
 
 switch (opcode) {
-case 0x04: /* SMMLA, UMMLA */
-gen_gvec_op4_ool(s, 1, rd, rn, rm, rd, 0,
- u ? gen_helper_gvec_ummla_b
- : gen_helper_gvec_smmla_b);
-return;
-case 0x05: /* USMMLA */
-gen_gvec_op4_ool(s, 1, rd, rn, rm, rd, 0, gen_helper_gvec_usmmla_b);
-return;
-
 case 0x8: /* FCMLA, #0 */
 case 0x9: /* FCMLA, #90 */
 case 0xa: /* FCMLA, #180 */
@@ -11051,9 +11034,6 @@ static void 
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
 }
 return;
 
-case 0xd: /* BFMMLA */
-gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfmmla);
-return;
 default:
 g_assert_not_reached();
 }
-- 
2.34.1