On 12/12/2019 20:01, Laurent Vivier wrote:
> 0xc020 is for Q900/Q950, Q800 uses 0xc000.
> This value was provided to the kernel, this explains why it was working
> even with wrong value
>
> Signed-off-by: Laurent Vivier
> ---
> hw/m68k/q800.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 4ca8678007..ef0014f4c4 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -67,7 +67,7 @@
> #define VIA_BASE (IO_BASE + 0x0)
> #define SONIC_PROM_BASE (IO_BASE + 0x08000)
> #define SONIC_BASE(IO_BASE + 0x0a000)
> -#define SCC_BASE (IO_BASE + 0x0c020)
> +#define SCC_BASE (IO_BASE + 0x0c000)
> #define ESP_BASE (IO_BASE + 0x1)
> #define ESP_PDMA (IO_BASE + 0x10100)
> #define ASC_BASE (IO_BASE + 0x14000)
I *think* this is correct (see the off-list message I've sent you) since if you
assume a CHRP-like mapping then even with a base of 0xc000 then an access to
0xc020
could potentially still be hitting the ESCC registers, but I'm not confident
enough
to give it an R-B tag :/
ATB,
Mark.
