Re: [PATCH 1/3] target/ppc: Move fsqrt to decodetree

2022-09-05 Thread Richard Henderson

On 9/5/22 13:37, Víctor Colombo wrote:

Signed-off-by: Víctor Colombo
---
  target/ppc/insn32.decode   |  7 +++
  target/ppc/translate/fp-impl.c.inc | 29 +
  target/ppc/translate/fp-ops.c.inc  |  1 -
  3 files changed, 24 insertions(+), 13 deletions(-)


Reviewed-by: Richard Henderson 

r~



[PATCH 1/3] target/ppc: Move fsqrt to decodetree

2022-09-05 Thread Víctor Colombo
Signed-off-by: Víctor Colombo 
---
 target/ppc/insn32.decode   |  7 +++
 target/ppc/translate/fp-impl.c.inc | 29 +
 target/ppc/translate/fp-ops.c.inc  |  1 -
 3 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index eb41efc100..b55d1550f3 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,9 @@
 &A  frt fra frb frc rc:bool
 @A  .. frt:5 fra:5 frb:5 frc:5 . rc:1   &A
 
+&A_tb   frt frb rc:bool
+@A_tb   .. frt:5 . frb:5 . . rc:1   &A_tb
+
 &D  rt ra si:int64_t
 @D  .. rt:5 ra:5 si:s16 &D
 
@@ -353,6 +356,10 @@ STFDU   110111 . .. ... @D
 STFDX   01 . ..  1011010111 -   @X
 STFDUX  01 . ..  100111 -   @X
 
+### Floating-Point Arithmetic Instructions
+
+FSQRT   11 . - . - 10110 .  @A_tb
+
 ### Floating-Point Select Instruction
 
 FSEL11 . . . . 10111 .  @A
diff --git a/target/ppc/translate/fp-impl.c.inc 
b/target/ppc/translate/fp-impl.c.inc
index 0e893eafa7..e8359af005 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -254,29 +254,34 @@ static bool trans_FSEL(DisasContext *ctx, arg_A *a)
 GEN_FLOAT_AB(sub, 0x14, 0x07C0, 1, PPC_FLOAT);
 /* Optional: */
 
-/* fsqrt */
-static void gen_fsqrt(DisasContext *ctx)
+static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb *a,
+void (*helper)(TCGv_i64, TCGv_ptr, TCGv_i64))
 {
-TCGv_i64 t0;
-TCGv_i64 t1;
-if (unlikely(!ctx->fpu_enabled)) {
-gen_exception(ctx, POWERPC_EXCP_FPU);
-return;
-}
+TCGv_i64 t0, t1;
+
+REQUIRE_INSNS_FLAGS(ctx, FLOAT_FSQRT);
+REQUIRE_FPU(ctx);
+
 t0 = tcg_temp_new_i64();
 t1 = tcg_temp_new_i64();
+
 gen_reset_fpstatus();
-get_fpr(t0, rB(ctx->opcode));
-gen_helper_fsqrt(t1, cpu_env, t0);
-set_fpr(rD(ctx->opcode), t1);
+get_fpr(t0, a->frb);
+helper(t1, cpu_env, t0);
+set_fpr(a->frt, t1);
 gen_compute_fprf_float64(t1);
-if (unlikely(Rc(ctx->opcode) != 0)) {
+if (unlikely(a->rc != 0)) {
 gen_set_cr1_from_fpscr(ctx);
 }
+
 tcg_temp_free_i64(t0);
 tcg_temp_free_i64(t1);
+
+return true;
 }
 
+TRANS(FSQRT, do_helper_fsqrt, gen_helper_fsqrt);
+
 static void gen_fsqrts(DisasContext *ctx)
 {
 TCGv_i64 t0;
diff --git a/target/ppc/translate/fp-ops.c.inc 
b/target/ppc/translate/fp-ops.c.inc
index 1b65f5ab73..38759f5939 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -62,7 +62,6 @@ GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x0001, 
PPC_NONE, PPC2_BOOKE206),
 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x0021, PPC_NONE, PPC2_ISA205),
 
 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
-GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x0061, PPC_FLOAT),
 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x0061, PPC_FLOAT),
-- 
2.25.1