Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote: > > Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 9 - > target/riscv/csr.c| 40 --- > target/riscv/gdbstub.c| 4 ++-- > 3 files changed, 18 insertions(+), 35 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index f88c503cf4..e677255f87 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, > int extirq, unsigned int extirq_def_prio, > uint64_t pending, uint8_t *iprio) > { > -RISCVCPU *cpu = env_archcpu(env); > int irq, best_irq = RISCV_EXCP_NONE; > unsigned int prio, best_prio = UINT_MAX; > > @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, > } > > irq = ctz64(pending); > -if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) { > +if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : > + riscv_cpu_cfg(env)->ext_ssaia)) { > return irq; > } > > @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, > hwaddr *physical, > int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; > bool use_background = false; > hwaddr ppn; > -RISCVCPU *cpu = env_archcpu(env); > int napot_bits = 0; > target_ulong napot_mask; > > @@ -946,7 +945,7 @@ restart: > > if (riscv_cpu_sxl(env) == MXL_RV32) { > ppn = pte >> PTE_PPN_SHIFT; > -} else if (pbmte || cpu->cfg.ext_svnapot) { > +} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { > ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; > } else { > ppn = pte >> PTE_PPN_SHIFT; > @@ -1043,7 +1042,7 @@ restart: > benefit. */ > target_ulong vpn = addr >> PGSHIFT; > > -if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { > +if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { > napot_bits = ctzl(ppn) + 1; > if ((i != (levels - 1)) || (napot_bits != 4)) { > return TRANSLATE_FAIL; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ab566639e5..b453d8e8ca 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) > > static RISCVException vs(CPURISCVState *env, int csrno) > { > -RISCVCPU *cpu = env_archcpu(env); > - > -if (cpu->cfg.ext_zve32f) { > +if (riscv_cpu_cfg(env)->ext_zve32f) { > #if !defined(CONFIG_USER_ONLY) > if (!env->debugger && !riscv_cpu_vector_enabled(env)) { > return RISCV_EXCP_ILLEGAL_INST; > @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int > csrno) > > static RISCVException sscofpmf(CPURISCVState *env, int csrno) > { > -RISCVCPU *cpu = env_archcpu(env); > - > -if (!cpu->cfg.ext_sscofpmf) { > +if (!riscv_cpu_cfg(env)->ext_sscofpmf) { > return RISCV_EXCP_ILLEGAL_INST; > } > > @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int > csrno) > > static RISCVException mstateen(CPURISCVState *env, int csrno) > { > -RISCVCPU *cpu = env_archcpu(env); > - > -if (!cpu->cfg.ext_smstateen) { > +if (!riscv_cpu_cfg(env)->ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > } > > @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int > csrno) > > static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) > { > -RISCVCPU *cpu = env_archcpu(env); > - > -if (!cpu->cfg.ext_smstateen) { > +if (!riscv_cpu_cfg(env)->ext_smstateen) { > return RISCV_EXCP_ILLEGAL_INST; > } > > @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int > csrno) > > static RISCVException sstc(CPURISCVState *env, int csrno) > { > -RISCVCPU *cpu = env_archcpu(env); > bool hmode_check = false; > > -if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { > +if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { > return RISCV_EXCP_ILLEGAL_INST; > } > > @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState > *env, int csrno, > static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > target_ulong *val) > { > -RISCVCPU *cpu = env_archcpu(env); > - > -*val = cpu->cfg.mvendorid; > +*val = riscv_cpu_cfg(env)->mvendorid; > return RISCV_EXCP_NONE; > } > > static RISCVException read_marchid(CPURISCVState *env, int csrno, > target_ulong *val) > { > -RISCVCPU *cpu =
Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
On 3/9/23 04:13, Weiwei Li wrote: Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu_helper.c | 9 - target/riscv/csr.c| 40 --- target/riscv/gdbstub.c| 4 ++-- 3 files changed, 18 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f88c503cf4..e677255f87 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, uint8_t *iprio) { -RISCVCPU *cpu = env_archcpu(env); int irq, best_irq = RISCV_EXCP_NONE; unsigned int prio, best_prio = UINT_MAX; @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } irq = ctz64(pending); -if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) { +if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { return irq; } @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background = false; hwaddr ppn; -RISCVCPU *cpu = env_archcpu(env); int napot_bits = 0; target_ulong napot_mask; @@ -946,7 +945,7 @@ restart: if (riscv_cpu_sxl(env) == MXL_RV32) { ppn = pte >> PTE_PPN_SHIFT; -} else if (pbmte || cpu->cfg.ext_svnapot) { +} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn = pte >> PTE_PPN_SHIFT; @@ -1043,7 +1042,7 @@ restart: benefit. */ target_ulong vpn = addr >> PGSHIFT; -if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { +if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { napot_bits = ctzl(ppn) + 1; if ((i != (levels - 1)) || (napot_bits != 4)) { return TRANSLATE_FAIL; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..b453d8e8ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (cpu->cfg.ext_zve32f) { +if (riscv_cpu_cfg(env)->ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno) static RISCVException sscofpmf(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_sscofpmf) { +if (!riscv_cpu_cfg(env)->ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; } @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno) static RISCVException mstateen(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_smstateen) { +if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno) static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_smstateen) { +if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno) static RISCVException sstc(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); bool hmode_check = false; -if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { +if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { -RISCVCPU *cpu = env_archcpu(env); - -*val = cpu->cfg.mvendorid; +*val = riscv_cpu_cfg(env)->mvendorid; return RISCV_EXCP_NONE; } static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { -RISCVCPU *cpu = env_archcpu(env); - -*val = cpu->cfg.marchid; +*val = riscv_cpu_cfg(env)->marchid; return RISCV_EXCP_NONE; } static RISCVException
[PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 9 - target/riscv/csr.c| 40 --- target/riscv/gdbstub.c| 4 ++-- 3 files changed, 18 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f88c503cf4..e677255f87 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_prio, uint64_t pending, uint8_t *iprio) { -RISCVCPU *cpu = env_archcpu(env); int irq, best_irq = RISCV_EXCP_NONE; unsigned int prio, best_prio = UINT_MAX; @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } irq = ctz64(pending); -if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) { +if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { return irq; } @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background = false; hwaddr ppn; -RISCVCPU *cpu = env_archcpu(env); int napot_bits = 0; target_ulong napot_mask; @@ -946,7 +945,7 @@ restart: if (riscv_cpu_sxl(env) == MXL_RV32) { ppn = pte >> PTE_PPN_SHIFT; -} else if (pbmte || cpu->cfg.ext_svnapot) { +} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn = pte >> PTE_PPN_SHIFT; @@ -1043,7 +1042,7 @@ restart: benefit. */ target_ulong vpn = addr >> PGSHIFT; -if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { +if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { napot_bits = ctzl(ppn) + 1; if ((i != (levels - 1)) || (napot_bits != 4)) { return TRANSLATE_FAIL; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..b453d8e8ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (cpu->cfg.ext_zve32f) { +if (riscv_cpu_cfg(env)->ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno) static RISCVException sscofpmf(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_sscofpmf) { +if (!riscv_cpu_cfg(env)->ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; } @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno) static RISCVException mstateen(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_smstateen) { +if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno) static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) { -RISCVCPU *cpu = env_archcpu(env); - -if (!cpu->cfg.ext_smstateen) { +if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno) static RISCVException sstc(CPURISCVState *env, int csrno) { -RISCVCPU *cpu = env_archcpu(env); bool hmode_check = false; -if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { +if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { -RISCVCPU *cpu = env_archcpu(env); - -*val = cpu->cfg.mvendorid; +*val = riscv_cpu_cfg(env)->mvendorid; return RISCV_EXCP_NONE; } static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { -RISCVCPU *cpu = env_archcpu(env); - -*val = cpu->cfg.marchid; +*val = riscv_cpu_cfg(env)->marchid; return RISCV_EXCP_NONE; } static RISCVException read_mimpid(CPURISCVState *env, int csrno, target_ulong *val) { -RISCVCPU *cpu = env_archcpu(env); - -*val = cpu->cfg.mimpid; +*val =