We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 78 ++
1 file changed, 69 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 9e5516f208..8913320259 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s,
arg_VMOV_to_gp *a)
int pass;
uint32_t offset;
+/* SIZE == 2 is a VFP instruction; otherwise NEON. */
+if (a->size == 2
+? !dc_isar_feature(aa32_fpsp_v2, s)
+: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+return false;
+}
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s,
arg_VMOV_to_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
-if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
-return false;
-}
-
if (!vfp_access_check(s)) {
return true;
}
@@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s,
arg_VMOV_from_gp *a)
int pass;
uint32_t offset;
+/* SIZE == 2 is a VFP instruction; otherwise NEON. */
+if (a->size == 2
+? !dc_isar_feature(aa32_fpsp_v2, s)
+: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+return false;
+}
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s,
arg_VMOV_from_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
-if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
-return false;
-}
-
if (!vfp_access_check(s)) {
return true;
}
@@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS
*a)
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/*
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
@@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s,
arg_VMOV_single *a)
{
TCGv_i32 tmp;
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
if (!vfp_access_check(s)) {
return true;
}
@@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s,
arg_VMOV_64_sp *a)
{
TCGv_i32 tmp;
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
/*
* VMOV between two general-purpose registers and two single precision
* floating point registers
@@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s,
arg_VMOV_64_dp *a)
/*
* VMOV between two general-purpose registers and one double precision
- * floating point register
+ * floating point register. Note that this does not require support
+ * for double precision arithmetic.
*/
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
@@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s,
arg_VLDR_VSTR_sp *a)
uint32_t offset;
TCGv_i32 addr, tmp;
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
if (!vfp_access_check(s)) {
return true;
}
@@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s,
arg_VLDR_VSTR_dp *a)
TCGv_i32 addr;
TCGv_i64 tmp;
+/* Note that this does not require support for double arithmetic. */
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
@@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s,
arg_VLDM_VSTM_sp *a)
TCGv_i32 addr, tmp;
int i, n;
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
n = a->imm;
if (n == 0 || (a->vd + n) > 32) {
@@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s,
arg_VLDM_VSTM_dp *a)
TCGv_i64 tmp;
int i, n;
+/* Note that this does not require support for double arithmetic. */
+if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+return false;
+}
+
n = a->imm >> 1;
if (n == 0 || (a->vd + n) > 32 || n > 16) {
@@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn
*fn,
TCGv_i32 f0, f1, fd;
