Re: [PATCH 15/20] target/riscv/tcg: introduce tcg_cpu_instance_init()
On Fri, Aug 25, 2023 at 10:08:48AM -0300, Daniel Henrique Barboza wrote:
> tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
> accelerator. It'll be called from within riscv_cpu_post_init(), via
> accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
> preserve behavior, the implementation will be similar to what
> riscv_cpu_post_init() already does.
>
> In this patch we'll move riscv_cpu_add_user_properties() and
> riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
> All multi-extension properties code was moved. The 'multi_ext_user_opts'
> hash table was also moved to tcg-cpu.c since it's a TCG only structure,
> meaning that we won't have to worry about initializing a TCG hash table
> when running a KVM CPU anymore.
>
> riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
> much code it requires to be moved at the same time. We'll do that in the
> next patch.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 141 +
> target/riscv/cpu.h | 2 +-
> target/riscv/tcg/tcg-cpu.c | 138
> 3 files changed, 140 insertions(+), 141 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f9aea6a80a..89b09a7e89 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0,
> ext_XVentanaCondOps),
> };
>
> -/* Hash that stores user set extensions */
> -static GHashTable *multi_ext_user_opts;
> -
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> {
> bool *ext_enabled = (void *)>cfg + ext_offset;
> @@ -195,12 +192,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> return PRIV_VERSION_1_10_0;
> }
>
> -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> -{
> -return g_hash_table_contains(multi_ext_user_opts,
> - GUINT_TO_POINTER(ext_offset));
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -281,9 +272,6 @@ static const char * const riscv_intr_names[] = {
> "reserved"
> };
>
> -static void riscv_cpu_add_user_properties(Object *obj);
> -static void riscv_init_max_cpu_extensions(Object *obj);
> -
> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> {
> if (async) {
> @@ -295,7 +283,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,
> bool async)
> }
> }
>
> -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> +void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> {
> env->misa_mxl_max = env->misa_mxl = mxl;
> env->misa_ext_mask = env->misa_ext = ext;
> @@ -1198,18 +1186,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq,
> int level)
>
> static void riscv_cpu_post_init(Object *obj)
> {
> -RISCVCPU *cpu = RISCV_CPU(obj);
> -RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
> -
> accel_cpu_instance_init(CPU(obj));
> -
> -if (rcc->user_extension_properties) {
> -riscv_cpu_add_user_properties(obj);
> -}
> -
> -if (cpu->cfg.max_features) {
> -riscv_init_max_cpu_extensions(obj);
> -}
> }
>
> static void riscv_cpu_init(Object *obj)
> @@ -1222,8 +1199,6 @@ static void riscv_cpu_init(Object *obj)
> qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
>IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> #endif /* CONFIG_USER_ONLY */
> -
> -multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> }
>
> typedef struct RISCVCPUMisaExtConfig {
> @@ -1503,120 +1478,6 @@ Property riscv_cpu_options[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> -const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> -bool value;
> -
> -if (!visit_type_bool(v, name, , errp)) {
> -return;
> -}
> -
> -isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
> -
> -g_hash_table_insert(multi_ext_user_opts,
> -GUINT_TO_POINTER(multi_ext_cfg->offset),
> -(gpointer)value);
> -}
> -
> -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> -const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> -bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
> -
> -visit_type_bool(v, name, , errp);
> -}
> -
> -static void cpu_add_multi_ext_prop(Object *cpu_obj,
> - const RISCVCPUMultiExtConfig
[PATCH 15/20] target/riscv/tcg: introduce tcg_cpu_instance_init()
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() already does.
In this patch we'll move riscv_cpu_add_user_properties() and
riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
All multi-extension properties code was moved. The 'multi_ext_user_opts'
hash table was also moved to tcg-cpu.c since it's a TCG only structure,
meaning that we won't have to worry about initializing a TCG hash table
when running a KVM CPU anymore.
riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
much code it requires to be moved at the same time. We'll do that in the
next patch.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 141 +
target/riscv/cpu.h | 2 +-
target/riscv/tcg/tcg-cpu.c | 138
3 files changed, 140 insertions(+), 141 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f9aea6a80a..89b09a7e89 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
};
-/* Hash that stores user set extensions */
-static GHashTable *multi_ext_user_opts;
-
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
{
bool *ext_enabled = (void *)>cfg + ext_offset;
@@ -195,12 +192,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
return PRIV_VERSION_1_10_0;
}
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
-{
-return g_hash_table_contains(multi_ext_user_opts,
- GUINT_TO_POINTER(ext_offset));
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -281,9 +272,6 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void riscv_cpu_add_user_properties(Object *obj);
-static void riscv_init_max_cpu_extensions(Object *obj);
-
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
if (async) {
@@ -295,7 +283,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,
bool async)
}
}
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext;
@@ -1198,18 +1186,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
static void riscv_cpu_post_init(Object *obj)
{
-RISCVCPU *cpu = RISCV_CPU(obj);
-RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
-
accel_cpu_instance_init(CPU(obj));
-
-if (rcc->user_extension_properties) {
-riscv_cpu_add_user_properties(obj);
-}
-
-if (cpu->cfg.max_features) {
-riscv_init_max_cpu_extensions(obj);
-}
}
static void riscv_cpu_init(Object *obj)
@@ -1222,8 +1199,6 @@ static void riscv_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
#endif /* CONFIG_USER_ONLY */
-
-multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
}
typedef struct RISCVCPUMisaExtConfig {
@@ -1503,120 +1478,6 @@ Property riscv_cpu_options[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
-const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-bool value;
-
-if (!visit_type_bool(v, name, , errp)) {
-return;
-}
-
-isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
-g_hash_table_insert(multi_ext_user_opts,
-GUINT_TO_POINTER(multi_ext_cfg->offset),
-(gpointer)value);
-}
-
-static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
-const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
-
-visit_type_bool(v, name, , errp);
-}
-
-static void cpu_add_multi_ext_prop(Object *cpu_obj,
- const RISCVCPUMultiExtConfig *multi_cfg)
-{
-object_property_add(cpu_obj, multi_cfg->name, "bool",
-cpu_get_multi_ext_cfg,
-cpu_set_multi_ext_cfg,
-NULL, (void *)multi_cfg);
-
-/*
- * Set def val directly instead of using
- * object_property_set_bool() to save the set()
- * callback
