Re: [PATCH 2/2] QOMify sifive_uart model

2021-05-16 Thread Lukas Jünger 

On 5/11/21 2:26 PM, Philippe Mathieu-Daudé wrote:

Hi Lukas,

On 5/4/21 5:34 PM, Lukas Jünger wrote:

Signed-off-by: Lukas Jünger 
---
  include/hw/char/sifive_uart.h |  6 +--
  hw/char/sifive_uart.c | 72 ++-
  2 files changed, 65 insertions(+), 13 deletions(-)
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+SiFiveUARTState *s = SIFIVE_UART(dev);
+
+qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
+ uart_be_change, s, NULL, true);
+
+}
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = sifive_uart_realize;
+device_class_set_props(dc, sifive_uart_properties);
+}

You forgot to add the migration fields (VMState) of the SiFiveUARTState
structure. You might want to convert to the Fifo8 API (like the
SiFiveSPIState does) previous to this patch.

Regards,

Phil.


Thank you for your feedback. If I understand correctly, sifive_spi does 
not support migration currently. Would it be possible to merge this 
QOMification without the migration feature for now, as not all devices 
in sifive_u support it at the moment anyways? It seems it would be 
difficult to test on my end.


Best regards,

Lukas

Re: [PATCH 2/2] QOMify sifive_uart model

2021-05-11 Thread Philippe Mathieu-Daudé 
Hi Lukas,

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger 
> ---
>  include/hw/char/sifive_uart.h |  6 +--
>  hw/char/sifive_uart.c | 72 ++-
>  2 files changed, 65 insertions(+), 13 deletions(-)

> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
> + uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +dc->realize = sifive_uart_realize;
> +device_class_set_props(dc, sifive_uart_properties);
> +}

You forgot to add the migration fields (VMState) of the SiFiveUARTState
structure. You might want to convert to the Fifo8 API (like the
SiFiveSPIState does) previous to this patch.

Regards,

Phil.

Re: [PATCH 2/2] QOMify sifive_uart model

2021-05-11 Thread Luc Michel 

On 5/4/21 5:34 PM, Lukas Jünger wrote:

Signed-off-by: Lukas Jünger 


Reviewed-by: Luc Michel 


---
  include/hw/char/sifive_uart.h |  6 +--
  hw/char/sifive_uart.c | 72 ++-
  2 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..45d66b1db5 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@
  #define HW_SIFIVE_UART_H
  
  #include "chardev/char-fe.h"

+#include "hw/qdev-properties.h"
  #include "hw/sysbus.h"
  #include "qom/object.h"
  
@@ -51,10 +52,7 @@ enum {

  #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
  
  #define TYPE_SIFIVE_UART "riscv.sifive.uart"

-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
- TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
  
  struct SiFiveUARTState {

  /*< private >*/
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index cb70374ead..0307568d0a 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -25,6 +25,7 @@
  #include "hw/hw.h"
  #include "hw/irq.h"
  #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
  
  /*

   * Not yet implemented:
@@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
  return 0;
  }
  
+static Property sifive_uart_properties[] = {

+DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+SiFiveUARTState *s = SIFIVE_UART(obj);
+
+memory_region_init_io(>mmio, OBJECT(s), _uart_ops, s,
+  TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+sysbus_init_mmio(sbd, >mmio);
+sysbus_init_irq(sbd, >irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+SiFiveUARTState *s = SIFIVE_UART(dev);
+
+qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
+ uart_be_change, s, NULL, true);
+
+}
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = sifive_uart_realize;
+device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+.name  = TYPE_SIFIVE_UART,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(SiFiveUARTState),
+.instance_init = sifive_uart_init,
+.class_init= sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+type_register_static(_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
  /*
   * Create UART device.
   */
  SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
  Chardev *chr, qemu_irq irq)
  {
-SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-s->irq = irq;
-qemu_chr_fe_init(>chr, chr, _abort);
-qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
-uart_be_change, s, NULL, true);
-memory_region_init_io(>mmio, NULL, _uart_ops, s,
-  TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-memory_region_add_subregion(address_space, base, >mmio);
-return s;
+DeviceState *dev;
+SysBusDevice *s;
+SiFiveUARTState *r;
+
+dev = qdev_new("riscv.sifive.uart");
+s = SYS_BUS_DEVICE(dev);
+qdev_prop_set_chr(dev, "chardev", chr);
+sysbus_realize_and_unref(s, _fatal);
+memory_region_add_subregion(address_space, base,
+sysbus_mmio_get_region(s, 0));
+sysbus_connect_irq(s, 0, irq);
+
+r = SIFIVE_UART(dev);
+return r;
  }

[PATCH 2/2] QOMify sifive_uart model

2021-05-04 Thread Lukas Jünger 
Signed-off-by: Lukas Jünger 
---
 include/hw/char/sifive_uart.h |  6 +--
 hw/char/sifive_uart.c | 72 ++-
 2 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..45d66b1db5 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@
 #define HW_SIFIVE_UART_H
 
 #include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qom/object.h"
 
@@ -51,10 +52,7 @@ enum {
 #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
- TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
 
 struct SiFiveUARTState {
 /*< private >*/
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index cb70374ead..0307568d0a 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -25,6 +25,7 @@
 #include "hw/hw.h"
 #include "hw/irq.h"
 #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
 
 /*
  * Not yet implemented:
@@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
 return 0;
 }
 
+static Property sifive_uart_properties[] = {
+DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+SiFiveUARTState *s = SIFIVE_UART(obj);
+
+memory_region_init_io(>mmio, OBJECT(s), _uart_ops, s,
+  TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+sysbus_init_mmio(sbd, >mmio);
+sysbus_init_irq(sbd, >irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+SiFiveUARTState *s = SIFIVE_UART(dev);
+
+qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
+ uart_be_change, s, NULL, true);
+
+}
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = sifive_uart_realize;
+device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+.name  = TYPE_SIFIVE_UART,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(SiFiveUARTState),
+.instance_init = sifive_uart_init,
+.class_init= sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+type_register_static(_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
 /*
  * Create UART device.
  */
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
 Chardev *chr, qemu_irq irq)
 {
-SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-s->irq = irq;
-qemu_chr_fe_init(>chr, chr, _abort);
-qemu_chr_fe_set_handlers(>chr, uart_can_rx, uart_rx, uart_event,
-uart_be_change, s, NULL, true);
-memory_region_init_io(>mmio, NULL, _uart_ops, s,
-  TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-memory_region_add_subregion(address_space, base, >mmio);
-return s;
+DeviceState *dev;
+SysBusDevice *s;
+SiFiveUARTState *r;
+
+dev = qdev_new("riscv.sifive.uart");
+s = SYS_BUS_DEVICE(dev);
+qdev_prop_set_chr(dev, "chardev", chr);
+sysbus_realize_and_unref(s, _fatal);
+memory_region_add_subregion(address_space, base,
+sysbus_mmio_get_region(s, 0));
+sysbus_connect_irq(s, 0, irq);
+
+r = SIFIVE_UART(dev);
+return r;
 }
-- 
2.30.2