Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

2023-03-13 Thread Philippe Mathieu-Daudé 

On 9/3/23 08:13, Weiwei Li wrote:

Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
  target/riscv/csr.c | 12 
  1 file changed, 4 insertions(+), 8 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

2023-03-13 Thread Alistair Francis 
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li  wrote:
>
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/csr.c | 12 
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53143f4d9a..80fc15e4d6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, 
> int csrno,
>
>  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> int csrno,
> -   bool write_mask,
> -   RISCVCPU *cpu)
> +   bool write_mask)
>  {
>  /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
>  bool read_only = get_field(csrno, 0xC00) == 3;
>  int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
>  /* ensure the CSR extension is enabled */
> -if (!cpu->cfg.ext_icsr) {
> +if (!riscv_cpu_cfg(env)->ext_icsr) {
>  return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> @@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int 
> csrno,
> target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask)
>  {
> -RISCVCPU *cpu = env_archcpu(env);
> -
> -RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
> +RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
>  if (ret != RISCV_EXCP_NONE) {
>  return ret;
>  }
> @@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int 
> csrno,
>  Int128 new_value, Int128 write_mask)
>  {
>  RISCVException ret;
> -RISCVCPU *cpu = env_archcpu(env);
>
> -ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
> +ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
>  if (ret != RISCV_EXCP_NONE) {
>  return ret;
>  }
> --
> 2.25.1
>
>

Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

2023-03-09 Thread Daniel Henrique Barboza 




On 3/9/23 04:13, Weiwei Li wrote:

Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---


Reviewed-by: Daniel Henrique Barboza 


  target/riscv/csr.c | 12 
  1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 53143f4d9a..80fc15e4d6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int 
csrno,
  
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,

 int csrno,
-   bool write_mask,
-   RISCVCPU *cpu)
+   bool write_mask)
  {
  /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
  bool read_only = get_field(csrno, 0xC00) == 3;
  int csr_min_priv = csr_ops[csrno].min_priv_ver;
  
  /* ensure the CSR extension is enabled */

-if (!cpu->cfg.ext_icsr) {
+if (!riscv_cpu_cfg(env)->ext_icsr) {
  return RISCV_EXCP_ILLEGAL_INST;
  }
  
@@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,

 target_ulong *ret_value,
 target_ulong new_value, target_ulong write_mask)
  {
-RISCVCPU *cpu = env_archcpu(env);
-
-RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
  if (ret != RISCV_EXCP_NONE) {
  return ret;
  }
@@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int 
csrno,
  Int128 new_value, Int128 write_mask)
  {
  RISCVException ret;
-RISCVCPU *cpu = env_archcpu(env);
  
-ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);

+ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
  if (ret != RISCV_EXCP_NONE) {
  return ret;
  }

[PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

2023-03-08 Thread Weiwei Li 
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
 target/riscv/csr.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 53143f4d9a..80fc15e4d6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int 
csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno,
-   bool write_mask,
-   RISCVCPU *cpu)
+   bool write_mask)
 {
 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
 bool read_only = get_field(csrno, 0xC00) == 3;
 int csr_min_priv = csr_ops[csrno].min_priv_ver;
 
 /* ensure the CSR extension is enabled */
-if (!cpu->cfg.ext_icsr) {
+if (!riscv_cpu_cfg(env)->ext_icsr) {
 return RISCV_EXCP_ILLEGAL_INST;
 }
 
@@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
 {
-RISCVCPU *cpu = env_archcpu(env);
-
-RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 if (ret != RISCV_EXCP_NONE) {
 return ret;
 }
@@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int 
csrno,
 Int128 new_value, Int128 write_mask)
 {
 RISCVException ret;
-RISCVCPU *cpu = env_archcpu(env);
 
-ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
+ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
 if (ret != RISCV_EXCP_NONE) {
 return ret;
 }
-- 
2.25.1