[PATCH RESEND 11/11] target/ppc: Implement slbiag
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 649b2a9c58..2e7c61e117 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,6 +695,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fb53bce0c8..e4aa336bbf 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
&X_rb rb
@X_rb .. . . rb:5 .. .&X_rb
+&X_rs_l rs l:bool
+@X_rs_l .. rs:5 l:1 . .. . &X_rs_l
+
&X_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . &X_uim5
xt=%x_xt
@@ -822,6 +825,7 @@ SLBIE 01 - - . 0110110010 -
@X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBIAG 01 . . - 1101010010 - @X_rs_l
SLBMTE 01 . - . 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = &env->slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
[PATCH RESEND 11/11] target/ppc: Implement slbiag
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 649b2a9c58..2e7c61e117 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,6 +695,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fb53bce0c8..e4aa336bbf 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
&X_rb rb
@X_rb .. . . rb:5 .. .&X_rb
+&X_rs_l rs l:bool
+@X_rs_l .. rs:5 l:1 . .. . &X_rs_l
+
&X_uim5 xt uim:uint8_t
@X_uim5 .. . . uim:5 .. . &X_uim5
xt=%x_xt
@@ -822,6 +825,7 @@ SLBIE 01 - - . 0110110010 -
@X_rb
SLBIEG 01 . - . 0111010010 - @X_tb
SLBIA 01 --... - - 010010 - @X_ih
+SLBIAG 01 . . - 1101010010 - @X_rs_l
SLBMTE 01 . - . 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = &env->slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
